1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
22 | * |
23 | * Authors: |
24 | * Eric Anholt <eric@anholt.net> |
25 | * Zou Nan hai <nanhai.zou@intel.com> |
26 | * Xiang Hai hao<haihao.xiang@intel.com> |
27 | * |
28 | */ |
29 | |
30 | #include <asm/param.h> |
31 | #include <drm/drmP.h> |
32 | #include "i915_drv.h" |
33 | #include <drm/i915_drm.h> |
34 | #include "i915_trace.h" |
35 | #include "intel_drv.h" |
36 | |
37 | static inline int ring_space(struct intel_ring_buffer *ring) |
38 | { |
39 | int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE); |
40 | if (space < 0) |
41 | space += ring->size; |
42 | return space; |
43 | } |
44 | |
45 | void __intel_ring_advance(struct intel_ring_buffer *ring) |
46 | { |
47 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
48 | |
49 | ring->tail &= ring->size - 1; |
50 | if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring)) |
51 | return; |
52 | ring->write_tail(ring, ring->tail); |
53 | } |
54 | |
55 | static int |
56 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
57 | u32 invalidate_domains, |
58 | u32 flush_domains) |
59 | { |
60 | u32 cmd; |
61 | int ret; |
62 | |
63 | cmd = MI_FLUSH; |
64 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
65 | cmd |= MI_NO_WRITE_FLUSH; |
66 | |
67 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
68 | cmd |= MI_READ_FLUSH; |
69 | |
70 | ret = intel_ring_begin(ring, 2); |
71 | if (ret) |
72 | return ret; |
73 | |
74 | intel_ring_emit(ring, cmd); |
75 | intel_ring_emit(ring, MI_NOOP); |
76 | intel_ring_advance(ring); |
77 | |
78 | return 0; |
79 | } |
80 | |
81 | static int |
82 | gen4_render_ring_flush(struct intel_ring_buffer *ring, |
83 | u32 invalidate_domains, |
84 | u32 flush_domains) |
85 | { |
86 | struct drm_device *dev = ring->dev; |
87 | u32 cmd; |
88 | int ret; |
89 | |
90 | /* |
91 | * read/write caches: |
92 | * |
93 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
94 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
95 | * also flushed at 2d versus 3d pipeline switches. |
96 | * |
97 | * read-only caches: |
98 | * |
99 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
100 | * MI_READ_FLUSH is set, and is always flushed on 965. |
101 | * |
102 | * I915_GEM_DOMAIN_COMMAND may not exist? |
103 | * |
104 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
105 | * invalidated when MI_EXE_FLUSH is set. |
106 | * |
107 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
108 | * invalidated with every MI_FLUSH. |
109 | * |
110 | * TLBs: |
111 | * |
112 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
113 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
114 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
115 | * are flushed at any MI_FLUSH. |
116 | */ |
117 | |
118 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
119 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
120 | cmd &= ~MI_NO_WRITE_FLUSH; |
121 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
122 | cmd |= MI_EXE_FLUSH; |
123 | |
124 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
125 | (IS_G4X(dev) || IS_GEN5(dev))) |
126 | cmd |= MI_INVALIDATE_ISP; |
127 | |
128 | ret = intel_ring_begin(ring, 2); |
129 | if (ret) |
130 | return ret; |
131 | |
132 | intel_ring_emit(ring, cmd); |
133 | intel_ring_emit(ring, MI_NOOP); |
134 | intel_ring_advance(ring); |
135 | |
136 | return 0; |
137 | } |
138 | |
139 | /** |
140 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
141 | * implementing two workarounds on gen6. From section 1.4.7.1 |
142 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
143 | * |
144 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
145 | * produced by non-pipelined state commands), software needs to first |
146 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
147 | * 0. |
148 | * |
149 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
150 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
151 | * |
152 | * And the workaround for these two requires this workaround first: |
153 | * |
154 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
155 | * BEFORE the pipe-control with a post-sync op and no write-cache |
156 | * flushes. |
157 | * |
158 | * And this last workaround is tricky because of the requirements on |
159 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
160 | * volume 2 part 1: |
161 | * |
162 | * "1 of the following must also be set: |
163 | * - Render Target Cache Flush Enable ([12] of DW1) |
164 | * - Depth Cache Flush Enable ([0] of DW1) |
165 | * - Stall at Pixel Scoreboard ([1] of DW1) |
166 | * - Depth Stall ([13] of DW1) |
167 | * - Post-Sync Operation ([13] of DW1) |
168 | * - Notify Enable ([8] of DW1)" |
169 | * |
170 | * The cache flushes require the workaround flush that triggered this |
171 | * one, so we can't use it. Depth stall would trigger the same. |
172 | * Post-sync nonzero is what triggered this second workaround, so we |
173 | * can't use that one either. Notify enable is IRQs, which aren't |
174 | * really our business. That leaves only stall at scoreboard. |
175 | */ |
176 | static int |
177 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) |
178 | { |
179 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
180 | int ret; |
181 | |
182 | |
183 | ret = intel_ring_begin(ring, 6); |
184 | if (ret) |
185 | return ret; |
186 | |
187 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
188 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
189 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
190 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
191 | intel_ring_emit(ring, 0); /* low dword */ |
192 | intel_ring_emit(ring, 0); /* high dword */ |
193 | intel_ring_emit(ring, MI_NOOP); |
194 | intel_ring_advance(ring); |
195 | |
196 | ret = intel_ring_begin(ring, 6); |
197 | if (ret) |
198 | return ret; |
199 | |
200 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
201 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
202 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
203 | intel_ring_emit(ring, 0); |
204 | intel_ring_emit(ring, 0); |
205 | intel_ring_emit(ring, MI_NOOP); |
206 | intel_ring_advance(ring); |
207 | |
208 | return 0; |
209 | } |
210 | |
211 | static int |
212 | gen6_render_ring_flush(struct intel_ring_buffer *ring, |
213 | u32 invalidate_domains, u32 flush_domains) |
214 | { |
215 | u32 flags = 0; |
216 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
217 | int ret; |
218 | |
219 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
220 | ret = intel_emit_post_sync_nonzero_flush(ring); |
221 | if (ret) |
222 | return ret; |
223 | |
224 | /* Just flush everything. Experiments have shown that reducing the |
225 | * number of bits based on the write domains has little performance |
226 | * impact. |
227 | */ |
228 | if (flush_domains) { |
229 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
230 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
231 | /* |
232 | * Ensure that any following seqno writes only happen |
233 | * when the render cache is indeed flushed. |
234 | */ |
235 | flags |= PIPE_CONTROL_CS_STALL; |
236 | } |
237 | if (invalidate_domains) { |
238 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
239 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
240 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
241 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
242 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
243 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
244 | /* |
245 | * TLB invalidate requires a post-sync write. |
246 | */ |
247 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
248 | } |
249 | |
250 | ret = intel_ring_begin(ring, 4); |
251 | if (ret) |
252 | return ret; |
253 | |
254 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
255 | intel_ring_emit(ring, flags); |
256 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
257 | intel_ring_emit(ring, 0); |
258 | intel_ring_advance(ring); |
259 | |
260 | return 0; |
261 | } |
262 | |
263 | static int |
264 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) |
265 | { |
266 | int ret; |
267 | |
268 | ret = intel_ring_begin(ring, 4); |
269 | if (ret) |
270 | return ret; |
271 | |
272 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
273 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
274 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
275 | intel_ring_emit(ring, 0); |
276 | intel_ring_emit(ring, 0); |
277 | intel_ring_advance(ring); |
278 | |
279 | return 0; |
280 | } |
281 | |
282 | static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) |
283 | { |
284 | int ret; |
285 | |
286 | if (!ring->fbc_dirty) |
287 | return 0; |
288 | |
289 | ret = intel_ring_begin(ring, 6); |
290 | if (ret) |
291 | return ret; |
292 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
293 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
294 | intel_ring_emit(ring, MSG_FBC_REND_STATE); |
295 | intel_ring_emit(ring, value); |
296 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
297 | intel_ring_emit(ring, MSG_FBC_REND_STATE); |
298 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
299 | intel_ring_advance(ring); |
300 | |
301 | ring->fbc_dirty = false; |
302 | return 0; |
303 | } |
304 | |
305 | static int |
306 | gen7_render_ring_flush(struct intel_ring_buffer *ring, |
307 | u32 invalidate_domains, u32 flush_domains) |
308 | { |
309 | u32 flags = 0; |
310 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
311 | int ret; |
312 | |
313 | /* |
314 | * Ensure that any following seqno writes only happen when the render |
315 | * cache is indeed flushed. |
316 | * |
317 | * Workaround: 4th PIPE_CONTROL command (except the ones with only |
318 | * read-cache invalidate bits set) must have the CS_STALL bit set. We |
319 | * don't try to be clever and just set it unconditionally. |
320 | */ |
321 | flags |= PIPE_CONTROL_CS_STALL; |
322 | |
323 | /* Just flush everything. Experiments have shown that reducing the |
324 | * number of bits based on the write domains has little performance |
325 | * impact. |
326 | */ |
327 | if (flush_domains) { |
328 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
329 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
330 | } |
331 | if (invalidate_domains) { |
332 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
333 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
334 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
335 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
336 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
337 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
338 | /* |
339 | * TLB invalidate requires a post-sync write. |
340 | */ |
341 | flags |= PIPE_CONTROL_QW_WRITE; |
342 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
343 | |
344 | /* Workaround: we must issue a pipe_control with CS-stall bit |
345 | * set before a pipe_control command that has the state cache |
346 | * invalidate bit set. */ |
347 | gen7_render_ring_cs_stall_wa(ring); |
348 | } |
349 | |
350 | ret = intel_ring_begin(ring, 4); |
351 | if (ret) |
352 | return ret; |
353 | |
354 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
355 | intel_ring_emit(ring, flags); |
356 | intel_ring_emit(ring, scratch_addr); |
357 | intel_ring_emit(ring, 0); |
358 | intel_ring_advance(ring); |
359 | |
360 | if (!invalidate_domains && flush_domains) |
361 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
362 | |
363 | return 0; |
364 | } |
365 | |
366 | static int |
367 | gen8_render_ring_flush(struct intel_ring_buffer *ring, |
368 | u32 invalidate_domains, u32 flush_domains) |
369 | { |
370 | u32 flags = 0; |
371 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
372 | int ret; |
373 | |
374 | flags |= PIPE_CONTROL_CS_STALL; |
375 | |
376 | if (flush_domains) { |
377 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
378 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
379 | } |
380 | if (invalidate_domains) { |
381 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
382 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
383 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
384 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
385 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
386 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
387 | flags |= PIPE_CONTROL_QW_WRITE; |
388 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
389 | } |
390 | |
391 | ret = intel_ring_begin(ring, 6); |
392 | if (ret) |
393 | return ret; |
394 | |
395 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
396 | intel_ring_emit(ring, flags); |
397 | intel_ring_emit(ring, scratch_addr); |
398 | intel_ring_emit(ring, 0); |
399 | intel_ring_emit(ring, 0); |
400 | intel_ring_emit(ring, 0); |
401 | intel_ring_advance(ring); |
402 | |
403 | return 0; |
404 | |
405 | } |
406 | |
407 | static void ring_write_tail(struct intel_ring_buffer *ring, |
408 | u32 value) |
409 | { |
410 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
411 | I915_WRITE_TAIL(ring, value); |
412 | } |
413 | |
414 | u64 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
415 | { |
416 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
417 | u64 acthd; |
418 | |
419 | if (INTEL_INFO(ring->dev)->gen >= 8) |
420 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), |
421 | RING_ACTHD_UDW(ring->mmio_base)); |
422 | else if (INTEL_INFO(ring->dev)->gen >= 4) |
423 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); |
424 | else |
425 | acthd = I915_READ(ACTHD); |
426 | |
427 | return acthd; |
428 | } |
429 | |
430 | static void ring_setup_phys_status_page(struct intel_ring_buffer *ring) |
431 | { |
432 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
433 | u32 addr; |
434 | |
435 | addr = dev_priv->status_page_dmah->busaddr; |
436 | if (INTEL_INFO(ring->dev)->gen >= 4) |
437 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
438 | I915_WRITE(HWS_PGA, addr); |
439 | } |
440 | |
441 | static bool stop_ring(struct intel_ring_buffer *ring) |
442 | { |
443 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
444 | |
445 | if (!IS_GEN2(ring->dev)) { |
446 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); |
447 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
448 | DRM_ERROR("%s :timed out trying to stop ring\n" , ring->name); |
449 | return false; |
450 | } |
451 | } |
452 | |
453 | I915_WRITE_CTL(ring, 0); |
454 | I915_WRITE_HEAD(ring, 0); |
455 | ring->write_tail(ring, 0); |
456 | |
457 | if (!IS_GEN2(ring->dev)) { |
458 | (void)I915_READ_CTL(ring); |
459 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); |
460 | } |
461 | |
462 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
463 | } |
464 | |
465 | static int init_ring_common(struct intel_ring_buffer *ring) |
466 | { |
467 | struct drm_device *dev = ring->dev; |
468 | struct drm_i915_private *dev_priv = dev->dev_private; |
469 | struct drm_i915_gem_object *obj = ring->obj; |
470 | int ret = 0; |
471 | |
472 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
473 | |
474 | if (!stop_ring(ring)) { |
475 | /* G45 ring initialization often fails to reset head to zero */ |
476 | DRM_DEBUG_KMS("%s head not reset to zero " |
477 | "ctl %08x head %08x tail %08x start %08x\n" , |
478 | ring->name, |
479 | I915_READ_CTL(ring), |
480 | I915_READ_HEAD(ring), |
481 | I915_READ_TAIL(ring), |
482 | I915_READ_START(ring)); |
483 | |
484 | if (!stop_ring(ring)) { |
485 | DRM_ERROR("failed to set %s head to zero " |
486 | "ctl %08x head %08x tail %08x start %08x\n" , |
487 | ring->name, |
488 | I915_READ_CTL(ring), |
489 | I915_READ_HEAD(ring), |
490 | I915_READ_TAIL(ring), |
491 | I915_READ_START(ring)); |
492 | ret = -EIO; |
493 | goto out; |
494 | } |
495 | } |
496 | |
497 | if (I915_NEED_GFX_HWS(dev)) |
498 | intel_ring_setup_status_page(ring); |
499 | else |
500 | ring_setup_phys_status_page(ring); |
501 | |
502 | /* Enforce ordering by reading HEAD register back */ |
503 | I915_READ_HEAD(ring); |
504 | |
505 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
506 | * registers with the above sequence (the readback of the HEAD registers |
507 | * also enforces ordering), otherwise the hw might lose the new ring |
508 | * register values. */ |
509 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
510 | |
511 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ |
512 | if (I915_READ_HEAD(ring)) |
513 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n" , |
514 | ring->name, I915_READ_HEAD(ring)); |
515 | I915_WRITE_HEAD(ring, 0); |
516 | (void)I915_READ_HEAD(ring); |
517 | |
518 | I915_WRITE_CTL(ring, |
519 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
520 | | RING_VALID); |
521 | |
522 | /* If the head is still not zero, the ring is dead */ |
523 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
524 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
525 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
526 | DRM_ERROR("%s initialization failed " |
527 | "ctl %08x head %08x tail %08x start %08x\n" , |
528 | ring->name, |
529 | I915_READ_CTL(ring), |
530 | I915_READ_HEAD(ring), |
531 | I915_READ_TAIL(ring), |
532 | I915_READ_START(ring)); |
533 | ret = -EIO; |
534 | goto out; |
535 | } |
536 | |
537 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
538 | i915_kernel_lost_context(ring->dev); |
539 | else { |
540 | ring->head = I915_READ_HEAD(ring); |
541 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
542 | ring->space = ring_space(ring); |
543 | ring->last_retired_head = -1; |
544 | } |
545 | |
546 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
547 | |
548 | out: |
549 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
550 | |
551 | return ret; |
552 | } |
553 | |
554 | static int |
555 | init_pipe_control(struct intel_ring_buffer *ring) |
556 | { |
557 | int ret; |
558 | |
559 | if (ring->scratch.obj) |
560 | return 0; |
561 | |
562 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
563 | if (ring->scratch.obj == NULL) { |
564 | DRM_ERROR("Failed to allocate seqno page\n" ); |
565 | ret = -ENOMEM; |
566 | goto err; |
567 | } |
568 | |
569 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
570 | if (ret) |
571 | goto err_unref; |
572 | |
573 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
574 | if (ret) |
575 | goto err_unref; |
576 | |
577 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
578 | #ifdef __NetBSD__ |
579 | ring->scratch.cpu_page = |
580 | kmap(container_of(TAILQ_FIRST(&ring->scratch.obj->igo_pageq), |
581 | struct page, p_vmp)); |
582 | #else |
583 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); |
584 | #endif |
585 | if (ring->scratch.cpu_page == NULL) { |
586 | ret = -ENOMEM; |
587 | goto err_unpin; |
588 | } |
589 | |
590 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n" , |
591 | ring->name, ring->scratch.gtt_offset); |
592 | return 0; |
593 | |
594 | err_unpin: |
595 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
596 | err_unref: |
597 | drm_gem_object_unreference(&ring->scratch.obj->base); |
598 | err: |
599 | return ret; |
600 | } |
601 | |
602 | static int init_render_ring(struct intel_ring_buffer *ring) |
603 | { |
604 | struct drm_device *dev = ring->dev; |
605 | struct drm_i915_private *dev_priv = dev->dev_private; |
606 | int ret = init_ring_common(ring); |
607 | |
608 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
609 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) |
610 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
611 | |
612 | /* We need to disable the AsyncFlip performance optimisations in order |
613 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be |
614 | * programmed to '1' on all products. |
615 | * |
616 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw |
617 | */ |
618 | if (INTEL_INFO(dev)->gen >= 6) |
619 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
620 | |
621 | /* Required for the hardware to program scanline values for waiting */ |
622 | if (INTEL_INFO(dev)->gen == 6) |
623 | I915_WRITE(GFX_MODE, |
624 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); |
625 | |
626 | if (IS_GEN7(dev)) |
627 | I915_WRITE(GFX_MODE_GEN7, |
628 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
629 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
630 | |
631 | if (INTEL_INFO(dev)->gen >= 5) { |
632 | ret = init_pipe_control(ring); |
633 | if (ret) |
634 | return ret; |
635 | } |
636 | |
637 | if (IS_GEN6(dev)) { |
638 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
639 | * "If this bit is set, STCunit will have LRA as replacement |
640 | * policy. [...] This bit must be reset. LRA replacement |
641 | * policy is not supported." |
642 | */ |
643 | I915_WRITE(CACHE_MODE_0, |
644 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
645 | |
646 | /* This is not explicitly set for GEN6, so read the register. |
647 | * see intel_ring_mi_set_context() for why we care. |
648 | * TODO: consider explicitly setting the bit for GEN5 |
649 | */ |
650 | ring->itlb_before_ctx_switch = |
651 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); |
652 | } |
653 | |
654 | if (INTEL_INFO(dev)->gen >= 6) |
655 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
656 | |
657 | if (HAS_L3_DPF(dev)) |
658 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
659 | |
660 | return ret; |
661 | } |
662 | |
663 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
664 | { |
665 | struct drm_device *dev = ring->dev; |
666 | |
667 | if (ring->scratch.obj == NULL) |
668 | return; |
669 | |
670 | if (INTEL_INFO(dev)->gen >= 5) { |
671 | #ifdef __NetBSD__ |
672 | kunmap(container_of(TAILQ_FIRST(&ring->scratch.obj->igo_pageq), |
673 | struct page, p_vmp)); |
674 | #else |
675 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); |
676 | #endif |
677 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
678 | } |
679 | |
680 | drm_gem_object_unreference(&ring->scratch.obj->base); |
681 | ring->scratch.obj = NULL; |
682 | } |
683 | |
684 | static void |
685 | update_mboxes(struct intel_ring_buffer *ring, |
686 | u32 mmio_offset) |
687 | { |
688 | /* NB: In order to be able to do semaphore MBOX updates for varying number |
689 | * of rings, it's easiest if we round up each individual update to a |
690 | * multiple of 2 (since ring updates must always be a multiple of 2) |
691 | * even though the actual update only requires 3 dwords. |
692 | */ |
693 | #define MBOX_UPDATE_DWORDS 4 |
694 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
695 | intel_ring_emit(ring, mmio_offset); |
696 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
697 | intel_ring_emit(ring, MI_NOOP); |
698 | } |
699 | |
700 | /** |
701 | * gen6_add_request - Update the semaphore mailbox registers |
702 | * |
703 | * @ring - ring that is adding a request |
704 | * @seqno - return seqno stuck into the ring |
705 | * |
706 | * Update the mailbox registers in the *other* rings with the current seqno. |
707 | * This acts like a signal in the canonical semaphore. |
708 | */ |
709 | static int |
710 | gen6_add_request(struct intel_ring_buffer *ring) |
711 | { |
712 | struct drm_device *dev = ring->dev; |
713 | struct drm_i915_private *dev_priv = dev->dev_private; |
714 | struct intel_ring_buffer *useless; |
715 | int i, ret, num_dwords = 4; |
716 | |
717 | if (i915_semaphore_is_enabled(dev)) |
718 | num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS); |
719 | #undef MBOX_UPDATE_DWORDS |
720 | |
721 | ret = intel_ring_begin(ring, num_dwords); |
722 | if (ret) |
723 | return ret; |
724 | |
725 | if (i915_semaphore_is_enabled(dev)) { |
726 | for_each_ring(useless, dev_priv, i) { |
727 | u32 mbox_reg = ring->signal_mbox[i]; |
728 | if (mbox_reg != GEN6_NOSYNC) |
729 | update_mboxes(ring, mbox_reg); |
730 | } |
731 | } |
732 | |
733 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
734 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
735 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
736 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
737 | __intel_ring_advance(ring); |
738 | |
739 | return 0; |
740 | } |
741 | |
742 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
743 | u32 seqno) |
744 | { |
745 | struct drm_i915_private *dev_priv = dev->dev_private; |
746 | return dev_priv->last_seqno < seqno; |
747 | } |
748 | |
749 | /** |
750 | * intel_ring_sync - sync the waiter to the signaller on seqno |
751 | * |
752 | * @waiter - ring that is waiting |
753 | * @signaller - ring which has, or will signal |
754 | * @seqno - seqno which the waiter will block on |
755 | */ |
756 | static int |
757 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
758 | struct intel_ring_buffer *signaller, |
759 | u32 seqno) |
760 | { |
761 | int ret; |
762 | u32 dw1 = MI_SEMAPHORE_MBOX | |
763 | MI_SEMAPHORE_COMPARE | |
764 | MI_SEMAPHORE_REGISTER; |
765 | |
766 | /* Throughout all of the GEM code, seqno passed implies our current |
767 | * seqno is >= the last seqno executed. However for hardware the |
768 | * comparison is strictly greater than. |
769 | */ |
770 | seqno -= 1; |
771 | |
772 | WARN_ON(signaller->semaphore_register[waiter->id] == |
773 | MI_SEMAPHORE_SYNC_INVALID); |
774 | |
775 | ret = intel_ring_begin(waiter, 4); |
776 | if (ret) |
777 | return ret; |
778 | |
779 | /* If seqno wrap happened, omit the wait with no-ops */ |
780 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { |
781 | intel_ring_emit(waiter, |
782 | dw1 | |
783 | signaller->semaphore_register[waiter->id]); |
784 | intel_ring_emit(waiter, seqno); |
785 | intel_ring_emit(waiter, 0); |
786 | intel_ring_emit(waiter, MI_NOOP); |
787 | } else { |
788 | intel_ring_emit(waiter, MI_NOOP); |
789 | intel_ring_emit(waiter, MI_NOOP); |
790 | intel_ring_emit(waiter, MI_NOOP); |
791 | intel_ring_emit(waiter, MI_NOOP); |
792 | } |
793 | intel_ring_advance(waiter); |
794 | |
795 | return 0; |
796 | } |
797 | |
798 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
799 | do { \ |
800 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
801 | PIPE_CONTROL_DEPTH_STALL); \ |
802 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
803 | intel_ring_emit(ring__, 0); \ |
804 | intel_ring_emit(ring__, 0); \ |
805 | } while (0) |
806 | |
807 | static int |
808 | pc_render_add_request(struct intel_ring_buffer *ring) |
809 | { |
810 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
811 | int ret; |
812 | |
813 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
814 | * incoherent with writes to memory, i.e. completely fubar, |
815 | * so we need to use PIPE_NOTIFY instead. |
816 | * |
817 | * However, we also need to workaround the qword write |
818 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
819 | * memory before requesting an interrupt. |
820 | */ |
821 | ret = intel_ring_begin(ring, 32); |
822 | if (ret) |
823 | return ret; |
824 | |
825 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
826 | PIPE_CONTROL_WRITE_FLUSH | |
827 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
828 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
829 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
830 | intel_ring_emit(ring, 0); |
831 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
832 | scratch_addr += 128; /* write to separate cachelines */ |
833 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
834 | scratch_addr += 128; |
835 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
836 | scratch_addr += 128; |
837 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
838 | scratch_addr += 128; |
839 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
840 | scratch_addr += 128; |
841 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
842 | |
843 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
844 | PIPE_CONTROL_WRITE_FLUSH | |
845 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
846 | PIPE_CONTROL_NOTIFY); |
847 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
848 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
849 | intel_ring_emit(ring, 0); |
850 | __intel_ring_advance(ring); |
851 | |
852 | return 0; |
853 | } |
854 | |
855 | static u32 |
856 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
857 | { |
858 | /* Workaround to force correct ordering between irq and seqno writes on |
859 | * ivb (and maybe also on snb) by reading from a CS register (like |
860 | * ACTHD) before reading the status page. */ |
861 | if (!lazy_coherency) { |
862 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
863 | POSTING_READ(RING_ACTHD(ring->mmio_base)); |
864 | } |
865 | |
866 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
867 | } |
868 | |
869 | static u32 |
870 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
871 | { |
872 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
873 | } |
874 | |
875 | static void |
876 | ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno) |
877 | { |
878 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); |
879 | } |
880 | |
881 | static u32 |
882 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
883 | { |
884 | return ring->scratch.cpu_page[0]; |
885 | } |
886 | |
887 | static void |
888 | pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno) |
889 | { |
890 | ring->scratch.cpu_page[0] = seqno; |
891 | } |
892 | |
893 | static bool |
894 | gen5_ring_get_irq(struct intel_ring_buffer *ring) |
895 | { |
896 | struct drm_device *dev = ring->dev; |
897 | struct drm_i915_private *dev_priv = dev->dev_private; |
898 | unsigned long flags; |
899 | |
900 | if (!dev->irq_enabled) |
901 | return false; |
902 | |
903 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
904 | if (ring->irq_refcount++ == 0) |
905 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
906 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
907 | |
908 | return true; |
909 | } |
910 | |
911 | static void |
912 | gen5_ring_put_irq(struct intel_ring_buffer *ring) |
913 | { |
914 | struct drm_device *dev = ring->dev; |
915 | struct drm_i915_private *dev_priv = dev->dev_private; |
916 | unsigned long flags; |
917 | |
918 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
919 | if (--ring->irq_refcount == 0) |
920 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
921 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
922 | } |
923 | |
924 | static bool |
925 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
926 | { |
927 | struct drm_device *dev = ring->dev; |
928 | struct drm_i915_private *dev_priv = dev->dev_private; |
929 | unsigned long flags; |
930 | |
931 | if (!dev->irq_enabled) |
932 | return false; |
933 | |
934 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
935 | if (ring->irq_refcount++ == 0) { |
936 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
937 | I915_WRITE(IMR, dev_priv->irq_mask); |
938 | POSTING_READ(IMR); |
939 | } |
940 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
941 | |
942 | return true; |
943 | } |
944 | |
945 | static void |
946 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
947 | { |
948 | struct drm_device *dev = ring->dev; |
949 | struct drm_i915_private *dev_priv = dev->dev_private; |
950 | unsigned long flags; |
951 | |
952 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
953 | if (--ring->irq_refcount == 0) { |
954 | dev_priv->irq_mask |= ring->irq_enable_mask; |
955 | I915_WRITE(IMR, dev_priv->irq_mask); |
956 | POSTING_READ(IMR); |
957 | } |
958 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
959 | } |
960 | |
961 | static bool |
962 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) |
963 | { |
964 | struct drm_device *dev = ring->dev; |
965 | struct drm_i915_private *dev_priv = dev->dev_private; |
966 | unsigned long flags; |
967 | |
968 | if (!dev->irq_enabled) |
969 | return false; |
970 | |
971 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
972 | if (ring->irq_refcount++ == 0) { |
973 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
974 | I915_WRITE16(IMR, dev_priv->irq_mask); |
975 | POSTING_READ16(IMR); |
976 | } |
977 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
978 | |
979 | return true; |
980 | } |
981 | |
982 | static void |
983 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) |
984 | { |
985 | struct drm_device *dev = ring->dev; |
986 | struct drm_i915_private *dev_priv = dev->dev_private; |
987 | unsigned long flags; |
988 | |
989 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
990 | if (--ring->irq_refcount == 0) { |
991 | dev_priv->irq_mask |= ring->irq_enable_mask; |
992 | I915_WRITE16(IMR, dev_priv->irq_mask); |
993 | POSTING_READ16(IMR); |
994 | } |
995 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
996 | } |
997 | |
998 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
999 | { |
1000 | struct drm_device *dev = ring->dev; |
1001 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1002 | u32 mmio = 0; |
1003 | |
1004 | /* The ring status page addresses are no longer next to the rest of |
1005 | * the ring registers as of gen7. |
1006 | */ |
1007 | if (IS_GEN7(dev)) { |
1008 | switch (ring->id) { |
1009 | case RCS: |
1010 | mmio = RENDER_HWS_PGA_GEN7; |
1011 | break; |
1012 | case BCS: |
1013 | mmio = BLT_HWS_PGA_GEN7; |
1014 | break; |
1015 | case VCS: |
1016 | mmio = BSD_HWS_PGA_GEN7; |
1017 | break; |
1018 | case VECS: |
1019 | mmio = VEBOX_HWS_PGA_GEN7; |
1020 | break; |
1021 | } |
1022 | } else if (IS_GEN6(ring->dev)) { |
1023 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
1024 | } else { |
1025 | /* XXX: gen8 returns to sanity */ |
1026 | mmio = RING_HWS_PGA(ring->mmio_base); |
1027 | } |
1028 | |
1029 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
1030 | POSTING_READ(mmio); |
1031 | |
1032 | /* |
1033 | * Flush the TLB for this page |
1034 | * |
1035 | * FIXME: These two bits have disappeared on gen8, so a question |
1036 | * arises: do we still need this and if so how should we go about |
1037 | * invalidating the TLB? |
1038 | */ |
1039 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { |
1040 | u32 reg = RING_INSTPM(ring->mmio_base); |
1041 | |
1042 | /* ring should be idle before issuing a sync flush*/ |
1043 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); |
1044 | |
1045 | I915_WRITE(reg, |
1046 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | |
1047 | INSTPM_SYNC_FLUSH)); |
1048 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, |
1049 | 1000)) |
1050 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n" , |
1051 | ring->name); |
1052 | } |
1053 | } |
1054 | |
1055 | static int |
1056 | bsd_ring_flush(struct intel_ring_buffer *ring, |
1057 | u32 invalidate_domains, |
1058 | u32 flush_domains) |
1059 | { |
1060 | int ret; |
1061 | |
1062 | ret = intel_ring_begin(ring, 2); |
1063 | if (ret) |
1064 | return ret; |
1065 | |
1066 | intel_ring_emit(ring, MI_FLUSH); |
1067 | intel_ring_emit(ring, MI_NOOP); |
1068 | intel_ring_advance(ring); |
1069 | return 0; |
1070 | } |
1071 | |
1072 | static int |
1073 | i9xx_add_request(struct intel_ring_buffer *ring) |
1074 | { |
1075 | int ret; |
1076 | |
1077 | ret = intel_ring_begin(ring, 4); |
1078 | if (ret) |
1079 | return ret; |
1080 | |
1081 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1082 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
1083 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
1084 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
1085 | __intel_ring_advance(ring); |
1086 | |
1087 | return 0; |
1088 | } |
1089 | |
1090 | static bool |
1091 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
1092 | { |
1093 | struct drm_device *dev = ring->dev; |
1094 | struct drm_i915_private *dev_priv = dev->dev_private; |
1095 | unsigned long flags; |
1096 | |
1097 | if (!dev->irq_enabled) |
1098 | return false; |
1099 | |
1100 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
1101 | if (ring->irq_refcount++ == 0) { |
1102 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
1103 | I915_WRITE_IMR(ring, |
1104 | ~(ring->irq_enable_mask | |
1105 | GT_PARITY_ERROR(dev))); |
1106 | else |
1107 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
1108 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
1109 | } |
1110 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
1111 | |
1112 | return true; |
1113 | } |
1114 | |
1115 | static void |
1116 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
1117 | { |
1118 | struct drm_device *dev = ring->dev; |
1119 | struct drm_i915_private *dev_priv = dev->dev_private; |
1120 | unsigned long flags; |
1121 | |
1122 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
1123 | if (--ring->irq_refcount == 0) { |
1124 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
1125 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
1126 | else |
1127 | I915_WRITE_IMR(ring, ~0); |
1128 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1129 | } |
1130 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
1131 | } |
1132 | |
1133 | static bool |
1134 | hsw_vebox_get_irq(struct intel_ring_buffer *ring) |
1135 | { |
1136 | struct drm_device *dev = ring->dev; |
1137 | struct drm_i915_private *dev_priv = dev->dev_private; |
1138 | unsigned long flags; |
1139 | |
1140 | if (!dev->irq_enabled) |
1141 | return false; |
1142 | |
1143 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
1144 | if (ring->irq_refcount++ == 0) { |
1145 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
1146 | snb_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
1147 | } |
1148 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
1149 | |
1150 | return true; |
1151 | } |
1152 | |
1153 | static void |
1154 | hsw_vebox_put_irq(struct intel_ring_buffer *ring) |
1155 | { |
1156 | struct drm_device *dev = ring->dev; |
1157 | struct drm_i915_private *dev_priv = dev->dev_private; |
1158 | unsigned long flags; |
1159 | |
1160 | if (!dev->irq_enabled) |
1161 | return; |
1162 | |
1163 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
1164 | if (--ring->irq_refcount == 0) { |
1165 | I915_WRITE_IMR(ring, ~0); |
1166 | snb_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
1167 | } |
1168 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
1169 | } |
1170 | |
1171 | static bool |
1172 | gen8_ring_get_irq(struct intel_ring_buffer *ring) |
1173 | { |
1174 | struct drm_device *dev = ring->dev; |
1175 | struct drm_i915_private *dev_priv = dev->dev_private; |
1176 | unsigned long flags; |
1177 | |
1178 | if (!dev->irq_enabled) |
1179 | return false; |
1180 | |
1181 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
1182 | if (ring->irq_refcount++ == 0) { |
1183 | if (HAS_L3_DPF(dev) && ring->id == RCS) { |
1184 | I915_WRITE_IMR(ring, |
1185 | ~(ring->irq_enable_mask | |
1186 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
1187 | } else { |
1188 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
1189 | } |
1190 | POSTING_READ(RING_IMR(ring->mmio_base)); |
1191 | } |
1192 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
1193 | |
1194 | return true; |
1195 | } |
1196 | |
1197 | static void |
1198 | gen8_ring_put_irq(struct intel_ring_buffer *ring) |
1199 | { |
1200 | struct drm_device *dev = ring->dev; |
1201 | struct drm_i915_private *dev_priv = dev->dev_private; |
1202 | unsigned long flags; |
1203 | |
1204 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
1205 | if (--ring->irq_refcount == 0) { |
1206 | if (HAS_L3_DPF(dev) && ring->id == RCS) { |
1207 | I915_WRITE_IMR(ring, |
1208 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
1209 | } else { |
1210 | I915_WRITE_IMR(ring, ~0); |
1211 | } |
1212 | POSTING_READ(RING_IMR(ring->mmio_base)); |
1213 | } |
1214 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
1215 | } |
1216 | |
1217 | static int |
1218 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1219 | u32 offset, u32 length, |
1220 | unsigned flags) |
1221 | { |
1222 | int ret; |
1223 | |
1224 | ret = intel_ring_begin(ring, 2); |
1225 | if (ret) |
1226 | return ret; |
1227 | |
1228 | intel_ring_emit(ring, |
1229 | MI_BATCH_BUFFER_START | |
1230 | MI_BATCH_GTT | |
1231 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
1232 | intel_ring_emit(ring, offset); |
1233 | intel_ring_advance(ring); |
1234 | |
1235 | return 0; |
1236 | } |
1237 | |
1238 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1239 | #define I830_BATCH_LIMIT (256*1024) |
1240 | static int |
1241 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1242 | u32 offset, u32 len, |
1243 | unsigned flags) |
1244 | { |
1245 | int ret; |
1246 | |
1247 | if (flags & I915_DISPATCH_PINNED) { |
1248 | ret = intel_ring_begin(ring, 4); |
1249 | if (ret) |
1250 | return ret; |
1251 | |
1252 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1253 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
1254 | intel_ring_emit(ring, offset + len - 8); |
1255 | intel_ring_emit(ring, MI_NOOP); |
1256 | intel_ring_advance(ring); |
1257 | } else { |
1258 | u32 cs_offset = ring->scratch.gtt_offset; |
1259 | |
1260 | if (len > I830_BATCH_LIMIT) |
1261 | return -ENOSPC; |
1262 | |
1263 | ret = intel_ring_begin(ring, 9+3); |
1264 | if (ret) |
1265 | return ret; |
1266 | /* Blit the batch (which has now all relocs applied) to the stable batch |
1267 | * scratch bo area (so that the CS never stumbles over its tlb |
1268 | * invalidation bug) ... */ |
1269 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | |
1270 | XY_SRC_COPY_BLT_WRITE_ALPHA | |
1271 | XY_SRC_COPY_BLT_WRITE_RGB); |
1272 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); |
1273 | intel_ring_emit(ring, 0); |
1274 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); |
1275 | intel_ring_emit(ring, cs_offset); |
1276 | intel_ring_emit(ring, 0); |
1277 | intel_ring_emit(ring, 4096); |
1278 | intel_ring_emit(ring, offset); |
1279 | intel_ring_emit(ring, MI_FLUSH); |
1280 | |
1281 | /* ... and execute it. */ |
1282 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1283 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
1284 | intel_ring_emit(ring, cs_offset + len - 8); |
1285 | intel_ring_advance(ring); |
1286 | } |
1287 | |
1288 | return 0; |
1289 | } |
1290 | |
1291 | static int |
1292 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1293 | u32 offset, u32 len, |
1294 | unsigned flags) |
1295 | { |
1296 | int ret; |
1297 | |
1298 | ret = intel_ring_begin(ring, 2); |
1299 | if (ret) |
1300 | return ret; |
1301 | |
1302 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1303 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
1304 | intel_ring_advance(ring); |
1305 | |
1306 | return 0; |
1307 | } |
1308 | |
1309 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
1310 | { |
1311 | struct drm_i915_gem_object *obj; |
1312 | |
1313 | obj = ring->status_page.obj; |
1314 | if (obj == NULL) |
1315 | return; |
1316 | |
1317 | #ifdef __NetBSD__ |
1318 | kunmap(container_of(TAILQ_FIRST(&obj->igo_pageq), struct page, p_vmp)); |
1319 | #else |
1320 | kunmap(sg_page(obj->pages->sgl)); |
1321 | #endif |
1322 | i915_gem_object_ggtt_unpin(obj); |
1323 | drm_gem_object_unreference(&obj->base); |
1324 | ring->status_page.obj = NULL; |
1325 | } |
1326 | |
1327 | static int init_status_page(struct intel_ring_buffer *ring) |
1328 | { |
1329 | struct drm_device *dev = ring->dev; |
1330 | struct drm_i915_gem_object *obj; |
1331 | int ret; |
1332 | |
1333 | obj = i915_gem_alloc_object(dev, 4096); |
1334 | if (obj == NULL) { |
1335 | DRM_ERROR("Failed to allocate status page\n" ); |
1336 | ret = -ENOMEM; |
1337 | goto err; |
1338 | } |
1339 | |
1340 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1341 | if (ret) |
1342 | goto err_unref; |
1343 | |
1344 | ret = i915_gem_obj_ggtt_pin(obj, 4096, 0); |
1345 | if (ret) |
1346 | goto err_unref; |
1347 | |
1348 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
1349 | #ifdef __NetBSD__ |
1350 | ring->status_page.page_addr = |
1351 | kmap(container_of(TAILQ_FIRST(&obj->igo_pageq), struct page, |
1352 | p_vmp)); |
1353 | #else |
1354 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
1355 | #endif |
1356 | if (ring->status_page.page_addr == NULL) { |
1357 | ret = -ENOMEM; |
1358 | goto err_unpin; |
1359 | } |
1360 | ring->status_page.obj = obj; |
1361 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
1362 | |
1363 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n" , |
1364 | ring->name, ring->status_page.gfx_addr); |
1365 | |
1366 | return 0; |
1367 | |
1368 | err_unpin: |
1369 | i915_gem_object_ggtt_unpin(obj); |
1370 | err_unref: |
1371 | drm_gem_object_unreference(&obj->base); |
1372 | err: |
1373 | return ret; |
1374 | } |
1375 | |
1376 | static int init_phys_status_page(struct intel_ring_buffer *ring) |
1377 | { |
1378 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1379 | |
1380 | if (!dev_priv->status_page_dmah) { |
1381 | dev_priv->status_page_dmah = |
1382 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); |
1383 | if (!dev_priv->status_page_dmah) |
1384 | return -ENOMEM; |
1385 | } |
1386 | |
1387 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1388 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
1389 | |
1390 | return 0; |
1391 | } |
1392 | |
1393 | static int intel_init_ring_buffer(struct drm_device *dev, |
1394 | struct intel_ring_buffer *ring) |
1395 | { |
1396 | struct drm_i915_gem_object *obj; |
1397 | struct drm_i915_private *dev_priv = dev->dev_private; |
1398 | int ret; |
1399 | |
1400 | ring->dev = dev; |
1401 | INIT_LIST_HEAD(&ring->active_list); |
1402 | INIT_LIST_HEAD(&ring->request_list); |
1403 | ring->size = 32 * PAGE_SIZE; |
1404 | memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno)); |
1405 | |
1406 | #ifdef __NetBSD__ |
1407 | DRM_INIT_WAITQUEUE(&ring->irq_queue, "i915irq" ); |
1408 | #else |
1409 | init_waitqueue_head(&ring->irq_queue); |
1410 | #endif |
1411 | |
1412 | if (I915_NEED_GFX_HWS(dev)) { |
1413 | ret = init_status_page(ring); |
1414 | if (ret) |
1415 | goto err_waitqueue; |
1416 | } else { |
1417 | BUG_ON(ring->id != RCS); |
1418 | ret = init_phys_status_page(ring); |
1419 | if (ret) |
1420 | goto err_waitqueue; |
1421 | } |
1422 | |
1423 | obj = NULL; |
1424 | if (!HAS_LLC(dev)) |
1425 | obj = i915_gem_object_create_stolen(dev, ring->size); |
1426 | if (obj == NULL) |
1427 | obj = i915_gem_alloc_object(dev, ring->size); |
1428 | if (obj == NULL) { |
1429 | DRM_ERROR("Failed to allocate ringbuffer\n" ); |
1430 | ret = -ENOMEM; |
1431 | goto err_hws; |
1432 | } |
1433 | |
1434 | ring->obj = obj; |
1435 | |
1436 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
1437 | if (ret) |
1438 | goto err_unref; |
1439 | |
1440 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1441 | if (ret) |
1442 | goto err_unpin; |
1443 | |
1444 | #ifdef __NetBSD__ |
1445 | /* XXX errno NetBSD->Linux */ |
1446 | ring->bst = dev_priv->dev->pdev->pd_pa.pa_memt; |
1447 | ret = -bus_space_map(ring->bst, (dev_priv->gtt.mappable_base + |
1448 | i915_gem_obj_ggtt_offset(obj)), |
1449 | ring->size, BUS_SPACE_MAP_PREFETCHABLE, &ring->bsh); |
1450 | if (ret) { |
1451 | DRM_ERROR("Failed to map ringbuffer: %d\n" , ret); |
1452 | goto err_unpin; |
1453 | } |
1454 | #else |
1455 | ring->virtual_start = |
1456 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
1457 | ring->size); |
1458 | if (ring->virtual_start == NULL) { |
1459 | DRM_ERROR("Failed to map ringbuffer.\n" ); |
1460 | ret = -EINVAL; |
1461 | goto err_unpin; |
1462 | } |
1463 | #endif |
1464 | |
1465 | ret = ring->init(ring); |
1466 | if (ret) |
1467 | goto err_unmap; |
1468 | |
1469 | /* Workaround an erratum on the i830 which causes a hang if |
1470 | * the TAIL pointer points to within the last 2 cachelines |
1471 | * of the buffer. |
1472 | */ |
1473 | ring->effective_size = ring->size; |
1474 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
1475 | ring->effective_size -= 128; |
1476 | |
1477 | i915_cmd_parser_init_ring(ring); |
1478 | |
1479 | return 0; |
1480 | |
1481 | err_unmap: |
1482 | #ifdef __NetBSD__ |
1483 | bus_space_unmap(ring->bst, ring->bsh, ring->size); |
1484 | #else |
1485 | iounmap(ring->virtual_start); |
1486 | #endif |
1487 | err_unpin: |
1488 | i915_gem_object_ggtt_unpin(obj); |
1489 | err_unref: |
1490 | drm_gem_object_unreference(&obj->base); |
1491 | ring->obj = NULL; |
1492 | err_hws: |
1493 | cleanup_status_page(ring); |
1494 | err_waitqueue: |
1495 | #ifdef __NetBSD__ |
1496 | DRM_DESTROY_WAITQUEUE(&ring->irq_queue); |
1497 | #endif |
1498 | return ret; |
1499 | } |
1500 | |
1501 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
1502 | { |
1503 | struct drm_i915_private *dev_priv; |
1504 | int ret; |
1505 | |
1506 | if (ring->obj == NULL) |
1507 | return; |
1508 | |
1509 | /* Disable the ring buffer. The ring must be idle at this point */ |
1510 | dev_priv = ring->dev->dev_private; |
1511 | ret = intel_ring_idle(ring); |
1512 | if (ret && !i915_reset_in_progress(&dev_priv->gpu_error)) |
1513 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n" , |
1514 | ring->name, ret); |
1515 | |
1516 | I915_WRITE_CTL(ring, 0); |
1517 | |
1518 | #ifdef __NetBSD__ |
1519 | bus_space_unmap(ring->bst, ring->bsh, ring->size); |
1520 | #else |
1521 | iounmap(ring->virtual_start); |
1522 | #endif |
1523 | |
1524 | i915_gem_object_ggtt_unpin(ring->obj); |
1525 | drm_gem_object_unreference(&ring->obj->base); |
1526 | ring->obj = NULL; |
1527 | ring->preallocated_lazy_request = NULL; |
1528 | ring->outstanding_lazy_seqno = 0; |
1529 | |
1530 | if (ring->cleanup) |
1531 | ring->cleanup(ring); |
1532 | |
1533 | cleanup_status_page(ring); |
1534 | |
1535 | #ifdef __NetBSD__ |
1536 | DRM_DESTROY_WAITQUEUE(&ring->irq_queue); |
1537 | #endif |
1538 | } |
1539 | |
1540 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) |
1541 | { |
1542 | struct drm_i915_gem_request *request; |
1543 | u32 seqno = 0, tail; |
1544 | int ret; |
1545 | |
1546 | if (ring->last_retired_head != -1) { |
1547 | ring->head = ring->last_retired_head; |
1548 | ring->last_retired_head = -1; |
1549 | |
1550 | ring->space = ring_space(ring); |
1551 | if (ring->space >= n) |
1552 | return 0; |
1553 | } |
1554 | |
1555 | list_for_each_entry(request, &ring->request_list, list) { |
1556 | int space; |
1557 | |
1558 | if (request->tail == -1) |
1559 | continue; |
1560 | |
1561 | space = request->tail - (ring->tail + I915_RING_FREE_SPACE); |
1562 | if (space < 0) |
1563 | space += ring->size; |
1564 | if (space >= n) { |
1565 | seqno = request->seqno; |
1566 | tail = request->tail; |
1567 | break; |
1568 | } |
1569 | |
1570 | /* Consume this request in case we need more space than |
1571 | * is available and so need to prevent a race between |
1572 | * updating last_retired_head and direct reads of |
1573 | * I915_RING_HEAD. It also provides a nice sanity check. |
1574 | */ |
1575 | request->tail = -1; |
1576 | } |
1577 | |
1578 | if (seqno == 0) |
1579 | return -ENOSPC; |
1580 | |
1581 | ret = i915_wait_seqno(ring, seqno); |
1582 | if (ret) |
1583 | return ret; |
1584 | |
1585 | ring->head = tail; |
1586 | ring->space = ring_space(ring); |
1587 | if (WARN_ON(ring->space < n)) |
1588 | return -ENOSPC; |
1589 | |
1590 | return 0; |
1591 | } |
1592 | |
1593 | static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) |
1594 | { |
1595 | struct drm_device *dev = ring->dev; |
1596 | struct drm_i915_private *dev_priv = dev->dev_private; |
1597 | unsigned long end; |
1598 | int ret; |
1599 | |
1600 | ret = intel_ring_wait_request(ring, n); |
1601 | if (ret != -ENOSPC) |
1602 | return ret; |
1603 | |
1604 | /* force the tail write in case we have been skipping them */ |
1605 | __intel_ring_advance(ring); |
1606 | |
1607 | trace_i915_ring_wait_begin(ring); |
1608 | /* With GEM the hangcheck timer should kick us out of the loop, |
1609 | * leaving it early runs the risk of corrupting GEM state (due |
1610 | * to running on almost untested codepaths). But on resume |
1611 | * timers don't work yet, so prevent a complete hang in that |
1612 | * case by choosing an insanely large timeout. */ |
1613 | end = jiffies + 60 * HZ; |
1614 | |
1615 | do { |
1616 | ring->head = I915_READ_HEAD(ring); |
1617 | ring->space = ring_space(ring); |
1618 | if (ring->space >= n) { |
1619 | trace_i915_ring_wait_end(ring); |
1620 | return 0; |
1621 | } |
1622 | |
1623 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && |
1624 | dev->primary->master) { |
1625 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1626 | if (master_priv->sarea_priv) |
1627 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
1628 | } |
1629 | |
1630 | msleep(1); |
1631 | |
1632 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1633 | dev_priv->mm.interruptible); |
1634 | if (ret) |
1635 | return ret; |
1636 | } while (!time_after(jiffies, end)); |
1637 | trace_i915_ring_wait_end(ring); |
1638 | return -EBUSY; |
1639 | } |
1640 | |
1641 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
1642 | { |
1643 | #ifndef __NetBSD__ |
1644 | uint32_t __iomem *virt; |
1645 | #endif |
1646 | int rem = ring->size - ring->tail; |
1647 | |
1648 | if (ring->space < rem) { |
1649 | int ret = ring_wait_for_space(ring, rem); |
1650 | if (ret) |
1651 | return ret; |
1652 | } |
1653 | |
1654 | #ifdef __NetBSD__ |
1655 | bus_space_set_region_4(ring->bst, ring->bsh, ring->tail, MI_NOOP, |
1656 | rem/4); |
1657 | #else |
1658 | virt = (void __iomem *)((char __iomem *)ring->virtual_start + |
1659 | ring->tail); |
1660 | rem /= 4; |
1661 | while (rem--) |
1662 | iowrite32(MI_NOOP, virt++); |
1663 | #endif |
1664 | |
1665 | ring->tail = 0; |
1666 | ring->space = ring_space(ring); |
1667 | |
1668 | return 0; |
1669 | } |
1670 | |
1671 | int intel_ring_idle(struct intel_ring_buffer *ring) |
1672 | { |
1673 | u32 seqno; |
1674 | int ret; |
1675 | |
1676 | /* We need to add any requests required to flush the objects and ring */ |
1677 | if (ring->outstanding_lazy_seqno) { |
1678 | ret = i915_add_request(ring, NULL); |
1679 | if (ret) |
1680 | return ret; |
1681 | } |
1682 | |
1683 | /* Wait upon the last request to be completed */ |
1684 | if (list_empty(&ring->request_list)) |
1685 | return 0; |
1686 | |
1687 | seqno = list_entry(ring->request_list.prev, |
1688 | struct drm_i915_gem_request, |
1689 | list)->seqno; |
1690 | |
1691 | return i915_wait_seqno(ring, seqno); |
1692 | } |
1693 | |
1694 | static int |
1695 | intel_ring_alloc_seqno(struct intel_ring_buffer *ring) |
1696 | { |
1697 | if (ring->outstanding_lazy_seqno) |
1698 | return 0; |
1699 | |
1700 | if (ring->preallocated_lazy_request == NULL) { |
1701 | struct drm_i915_gem_request *request; |
1702 | |
1703 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
1704 | if (request == NULL) |
1705 | return -ENOMEM; |
1706 | |
1707 | ring->preallocated_lazy_request = request; |
1708 | } |
1709 | |
1710 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
1711 | } |
1712 | |
1713 | static int __intel_ring_prepare(struct intel_ring_buffer *ring, |
1714 | int bytes) |
1715 | { |
1716 | int ret; |
1717 | |
1718 | if (unlikely(ring->tail + bytes > ring->effective_size)) { |
1719 | ret = intel_wrap_ring_buffer(ring); |
1720 | if (unlikely(ret)) |
1721 | return ret; |
1722 | } |
1723 | |
1724 | if (unlikely(ring->space < bytes)) { |
1725 | ret = ring_wait_for_space(ring, bytes); |
1726 | if (unlikely(ret)) |
1727 | return ret; |
1728 | } |
1729 | |
1730 | return 0; |
1731 | } |
1732 | |
1733 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1734 | int num_dwords) |
1735 | { |
1736 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1737 | int ret; |
1738 | |
1739 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1740 | dev_priv->mm.interruptible); |
1741 | if (ret) |
1742 | return ret; |
1743 | |
1744 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
1745 | if (ret) |
1746 | return ret; |
1747 | |
1748 | /* Preallocate the olr before touching the ring */ |
1749 | ret = intel_ring_alloc_seqno(ring); |
1750 | if (ret) |
1751 | return ret; |
1752 | |
1753 | ring->space -= num_dwords * sizeof(uint32_t); |
1754 | return 0; |
1755 | } |
1756 | |
1757 | /* Align the ring tail to a cacheline boundary */ |
1758 | int intel_ring_cacheline_align(struct intel_ring_buffer *ring) |
1759 | { |
1760 | int num_dwords = (64 - (ring->tail & 63)) / sizeof(uint32_t); |
1761 | int ret; |
1762 | |
1763 | if (num_dwords == 0) |
1764 | return 0; |
1765 | |
1766 | ret = intel_ring_begin(ring, num_dwords); |
1767 | if (ret) |
1768 | return ret; |
1769 | |
1770 | while (num_dwords--) |
1771 | intel_ring_emit(ring, MI_NOOP); |
1772 | |
1773 | intel_ring_advance(ring); |
1774 | |
1775 | return 0; |
1776 | } |
1777 | |
1778 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno) |
1779 | { |
1780 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1781 | |
1782 | BUG_ON(ring->outstanding_lazy_seqno); |
1783 | |
1784 | if (INTEL_INFO(ring->dev)->gen >= 6) { |
1785 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
1786 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); |
1787 | if (HAS_VEBOX(ring->dev)) |
1788 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
1789 | } |
1790 | |
1791 | ring->set_seqno(ring, seqno); |
1792 | ring->hangcheck.seqno = seqno; |
1793 | } |
1794 | |
1795 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
1796 | u32 value) |
1797 | { |
1798 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1799 | |
1800 | /* Every tail move must follow the sequence below */ |
1801 | |
1802 | /* Disable notification that the ring is IDLE. The GT |
1803 | * will then assume that it is busy and bring it out of rc6. |
1804 | */ |
1805 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1806 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1807 | |
1808 | /* Clear the context id. Here be magic! */ |
1809 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); |
1810 | |
1811 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
1812 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
1813 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1814 | 50)) |
1815 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n" ); |
1816 | |
1817 | /* Now that the ring is fully powered up, update the tail */ |
1818 | I915_WRITE_TAIL(ring, value); |
1819 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1820 | |
1821 | /* Let the ring send IDLE messages to the GT again, |
1822 | * and so let it sleep to conserve power when idle. |
1823 | */ |
1824 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1825 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1826 | } |
1827 | |
1828 | static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, |
1829 | u32 invalidate, u32 flush) |
1830 | { |
1831 | uint32_t cmd; |
1832 | int ret; |
1833 | |
1834 | ret = intel_ring_begin(ring, 4); |
1835 | if (ret) |
1836 | return ret; |
1837 | |
1838 | cmd = MI_FLUSH_DW; |
1839 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1840 | cmd += 1; |
1841 | /* |
1842 | * Bspec vol 1c.5 - video engine command streamer: |
1843 | * "If ENABLED, all TLBs will be invalidated once the flush |
1844 | * operation is complete. This bit is only valid when the |
1845 | * Post-Sync Operation field is a value of 1h or 3h." |
1846 | */ |
1847 | if (invalidate & I915_GEM_GPU_DOMAINS) |
1848 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
1849 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
1850 | intel_ring_emit(ring, cmd); |
1851 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
1852 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1853 | intel_ring_emit(ring, 0); /* upper addr */ |
1854 | intel_ring_emit(ring, 0); /* value */ |
1855 | } else { |
1856 | intel_ring_emit(ring, 0); |
1857 | intel_ring_emit(ring, MI_NOOP); |
1858 | } |
1859 | intel_ring_advance(ring); |
1860 | return 0; |
1861 | } |
1862 | |
1863 | static int |
1864 | gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1865 | u32 offset, u32 len, |
1866 | unsigned flags) |
1867 | { |
1868 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1869 | bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL && |
1870 | !(flags & I915_DISPATCH_SECURE); |
1871 | int ret; |
1872 | |
1873 | ret = intel_ring_begin(ring, 4); |
1874 | if (ret) |
1875 | return ret; |
1876 | |
1877 | /* FIXME(BDW): Address space and security selectors. */ |
1878 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
1879 | intel_ring_emit(ring, offset); |
1880 | intel_ring_emit(ring, 0); |
1881 | intel_ring_emit(ring, MI_NOOP); |
1882 | intel_ring_advance(ring); |
1883 | |
1884 | return 0; |
1885 | } |
1886 | |
1887 | static int |
1888 | hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1889 | u32 offset, u32 len, |
1890 | unsigned flags) |
1891 | { |
1892 | int ret; |
1893 | |
1894 | ret = intel_ring_begin(ring, 2); |
1895 | if (ret) |
1896 | return ret; |
1897 | |
1898 | intel_ring_emit(ring, |
1899 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | |
1900 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); |
1901 | /* bit0-7 is the length on GEN6+ */ |
1902 | intel_ring_emit(ring, offset); |
1903 | intel_ring_advance(ring); |
1904 | |
1905 | return 0; |
1906 | } |
1907 | |
1908 | static int |
1909 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1910 | u32 offset, u32 len, |
1911 | unsigned flags) |
1912 | { |
1913 | int ret; |
1914 | |
1915 | ret = intel_ring_begin(ring, 2); |
1916 | if (ret) |
1917 | return ret; |
1918 | |
1919 | intel_ring_emit(ring, |
1920 | MI_BATCH_BUFFER_START | |
1921 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
1922 | /* bit0-7 is the length on GEN6+ */ |
1923 | intel_ring_emit(ring, offset); |
1924 | intel_ring_advance(ring); |
1925 | |
1926 | return 0; |
1927 | } |
1928 | |
1929 | /* Blitter support (SandyBridge+) */ |
1930 | |
1931 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
1932 | u32 invalidate, u32 flush) |
1933 | { |
1934 | struct drm_device *dev = ring->dev; |
1935 | uint32_t cmd; |
1936 | int ret; |
1937 | |
1938 | ret = intel_ring_begin(ring, 4); |
1939 | if (ret) |
1940 | return ret; |
1941 | |
1942 | cmd = MI_FLUSH_DW; |
1943 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1944 | cmd += 1; |
1945 | /* |
1946 | * Bspec vol 1c.3 - blitter engine command streamer: |
1947 | * "If ENABLED, all TLBs will be invalidated once the flush |
1948 | * operation is complete. This bit is only valid when the |
1949 | * Post-Sync Operation field is a value of 1h or 3h." |
1950 | */ |
1951 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
1952 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
1953 | MI_FLUSH_DW_OP_STOREDW; |
1954 | intel_ring_emit(ring, cmd); |
1955 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
1956 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1957 | intel_ring_emit(ring, 0); /* upper addr */ |
1958 | intel_ring_emit(ring, 0); /* value */ |
1959 | } else { |
1960 | intel_ring_emit(ring, 0); |
1961 | intel_ring_emit(ring, MI_NOOP); |
1962 | } |
1963 | intel_ring_advance(ring); |
1964 | |
1965 | if (IS_GEN7(dev) && !invalidate && flush) |
1966 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
1967 | |
1968 | return 0; |
1969 | } |
1970 | |
1971 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1972 | { |
1973 | struct drm_i915_private *dev_priv = dev->dev_private; |
1974 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
1975 | |
1976 | ring->name = "render ring" ; |
1977 | ring->id = RCS; |
1978 | ring->mmio_base = RENDER_RING_BASE; |
1979 | |
1980 | if (INTEL_INFO(dev)->gen >= 6) { |
1981 | ring->add_request = gen6_add_request; |
1982 | ring->flush = gen7_render_ring_flush; |
1983 | if (INTEL_INFO(dev)->gen == 6) |
1984 | ring->flush = gen6_render_ring_flush; |
1985 | if (INTEL_INFO(dev)->gen >= 8) { |
1986 | ring->flush = gen8_render_ring_flush; |
1987 | ring->irq_get = gen8_ring_get_irq; |
1988 | ring->irq_put = gen8_ring_put_irq; |
1989 | } else { |
1990 | ring->irq_get = gen6_ring_get_irq; |
1991 | ring->irq_put = gen6_ring_put_irq; |
1992 | } |
1993 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
1994 | ring->get_seqno = gen6_ring_get_seqno; |
1995 | ring->set_seqno = ring_set_seqno; |
1996 | ring->sync_to = gen6_ring_sync; |
1997 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
1998 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV; |
1999 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB; |
2000 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE; |
2001 | ring->signal_mbox[RCS] = GEN6_NOSYNC; |
2002 | ring->signal_mbox[VCS] = GEN6_VRSYNC; |
2003 | ring->signal_mbox[BCS] = GEN6_BRSYNC; |
2004 | ring->signal_mbox[VECS] = GEN6_VERSYNC; |
2005 | } else if (IS_GEN5(dev)) { |
2006 | ring->add_request = pc_render_add_request; |
2007 | ring->flush = gen4_render_ring_flush; |
2008 | ring->get_seqno = pc_render_get_seqno; |
2009 | ring->set_seqno = pc_render_set_seqno; |
2010 | ring->irq_get = gen5_ring_get_irq; |
2011 | ring->irq_put = gen5_ring_put_irq; |
2012 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
2013 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
2014 | } else { |
2015 | ring->add_request = i9xx_add_request; |
2016 | if (INTEL_INFO(dev)->gen < 4) |
2017 | ring->flush = gen2_render_ring_flush; |
2018 | else |
2019 | ring->flush = gen4_render_ring_flush; |
2020 | ring->get_seqno = ring_get_seqno; |
2021 | ring->set_seqno = ring_set_seqno; |
2022 | if (IS_GEN2(dev)) { |
2023 | ring->irq_get = i8xx_ring_get_irq; |
2024 | ring->irq_put = i8xx_ring_put_irq; |
2025 | } else { |
2026 | ring->irq_get = i9xx_ring_get_irq; |
2027 | ring->irq_put = i9xx_ring_put_irq; |
2028 | } |
2029 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
2030 | } |
2031 | ring->write_tail = ring_write_tail; |
2032 | if (IS_HASWELL(dev)) |
2033 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
2034 | else if (IS_GEN8(dev)) |
2035 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
2036 | else if (INTEL_INFO(dev)->gen >= 6) |
2037 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
2038 | else if (INTEL_INFO(dev)->gen >= 4) |
2039 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
2040 | else if (IS_I830(dev) || IS_845G(dev)) |
2041 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
2042 | else |
2043 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
2044 | ring->init = init_render_ring; |
2045 | ring->cleanup = render_ring_cleanup; |
2046 | |
2047 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2048 | if (HAS_BROKEN_CS_TLB(dev)) { |
2049 | struct drm_i915_gem_object *obj; |
2050 | int ret; |
2051 | |
2052 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); |
2053 | if (obj == NULL) { |
2054 | DRM_ERROR("Failed to allocate batch bo\n" ); |
2055 | return -ENOMEM; |
2056 | } |
2057 | |
2058 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
2059 | if (ret != 0) { |
2060 | drm_gem_object_unreference(&obj->base); |
2061 | DRM_ERROR("Failed to ping batch bo\n" ); |
2062 | return ret; |
2063 | } |
2064 | |
2065 | ring->scratch.obj = obj; |
2066 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); |
2067 | } |
2068 | |
2069 | return intel_init_ring_buffer(dev, ring); |
2070 | } |
2071 | |
2072 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
2073 | { |
2074 | struct drm_i915_private *dev_priv = dev->dev_private; |
2075 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
2076 | int ret; |
2077 | |
2078 | ring->name = "render ring" ; |
2079 | ring->id = RCS; |
2080 | ring->mmio_base = RENDER_RING_BASE; |
2081 | |
2082 | if (INTEL_INFO(dev)->gen >= 6) { |
2083 | /* non-kms not supported on gen6+ */ |
2084 | return -ENODEV; |
2085 | } |
2086 | |
2087 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding |
2088 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up |
2089 | * the special gen5 functions. */ |
2090 | ring->add_request = i9xx_add_request; |
2091 | if (INTEL_INFO(dev)->gen < 4) |
2092 | ring->flush = gen2_render_ring_flush; |
2093 | else |
2094 | ring->flush = gen4_render_ring_flush; |
2095 | ring->get_seqno = ring_get_seqno; |
2096 | ring->set_seqno = ring_set_seqno; |
2097 | if (IS_GEN2(dev)) { |
2098 | ring->irq_get = i8xx_ring_get_irq; |
2099 | ring->irq_put = i8xx_ring_put_irq; |
2100 | } else { |
2101 | ring->irq_get = i9xx_ring_get_irq; |
2102 | ring->irq_put = i9xx_ring_put_irq; |
2103 | } |
2104 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
2105 | ring->write_tail = ring_write_tail; |
2106 | if (INTEL_INFO(dev)->gen >= 4) |
2107 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
2108 | else if (IS_I830(dev) || IS_845G(dev)) |
2109 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
2110 | else |
2111 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
2112 | ring->init = init_render_ring; |
2113 | ring->cleanup = render_ring_cleanup; |
2114 | |
2115 | ring->dev = dev; |
2116 | INIT_LIST_HEAD(&ring->active_list); |
2117 | INIT_LIST_HEAD(&ring->request_list); |
2118 | |
2119 | ring->size = size; |
2120 | ring->effective_size = ring->size; |
2121 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
2122 | ring->effective_size -= 128; |
2123 | |
2124 | #ifdef __NetBSD__ |
2125 | /* XXX errno NetBSD->Linux */ |
2126 | ring->bst = dev_priv->dev->pdev->pd_pa.pa_memt; |
2127 | ret = -bus_space_map(ring->bst, start, size, |
2128 | BUS_SPACE_MAP_PREFETCHABLE, &ring->bsh); |
2129 | if (ret) { |
2130 | DRM_ERROR("Failed to map ringbuffer: %d\n" , ret); |
2131 | return ret; |
2132 | } |
2133 | #else |
2134 | ring->virtual_start = ioremap_wc(start, size); |
2135 | if (ring->virtual_start == NULL) { |
2136 | DRM_ERROR("can not ioremap virtual address for" |
2137 | " ring buffer\n" ); |
2138 | return -ENOMEM; |
2139 | } |
2140 | #endif |
2141 | |
2142 | if (!I915_NEED_GFX_HWS(dev)) { |
2143 | ret = init_phys_status_page(ring); |
2144 | if (ret) { |
2145 | #ifdef __NetBSD__ |
2146 | bus_space_unmap(ring->bst, ring->bsh, ring->size); |
2147 | #else |
2148 | iounmap(ring->virtual_start); |
2149 | #endif |
2150 | return ret; |
2151 | } |
2152 | } |
2153 | |
2154 | return 0; |
2155 | } |
2156 | |
2157 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
2158 | { |
2159 | struct drm_i915_private *dev_priv = dev->dev_private; |
2160 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
2161 | |
2162 | ring->name = "bsd ring" ; |
2163 | ring->id = VCS; |
2164 | |
2165 | ring->write_tail = ring_write_tail; |
2166 | if (INTEL_INFO(dev)->gen >= 6) { |
2167 | ring->mmio_base = GEN6_BSD_RING_BASE; |
2168 | /* gen6 bsd needs a special wa for tail updates */ |
2169 | if (IS_GEN6(dev)) |
2170 | ring->write_tail = gen6_bsd_ring_write_tail; |
2171 | ring->flush = gen6_bsd_ring_flush; |
2172 | ring->add_request = gen6_add_request; |
2173 | ring->get_seqno = gen6_ring_get_seqno; |
2174 | ring->set_seqno = ring_set_seqno; |
2175 | if (INTEL_INFO(dev)->gen >= 8) { |
2176 | ring->irq_enable_mask = |
2177 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
2178 | ring->irq_get = gen8_ring_get_irq; |
2179 | ring->irq_put = gen8_ring_put_irq; |
2180 | ring->dispatch_execbuffer = |
2181 | gen8_ring_dispatch_execbuffer; |
2182 | } else { |
2183 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
2184 | ring->irq_get = gen6_ring_get_irq; |
2185 | ring->irq_put = gen6_ring_put_irq; |
2186 | ring->dispatch_execbuffer = |
2187 | gen6_ring_dispatch_execbuffer; |
2188 | } |
2189 | ring->sync_to = gen6_ring_sync; |
2190 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR; |
2191 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID; |
2192 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB; |
2193 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE; |
2194 | ring->signal_mbox[RCS] = GEN6_RVSYNC; |
2195 | ring->signal_mbox[VCS] = GEN6_NOSYNC; |
2196 | ring->signal_mbox[BCS] = GEN6_BVSYNC; |
2197 | ring->signal_mbox[VECS] = GEN6_VEVSYNC; |
2198 | } else { |
2199 | ring->mmio_base = BSD_RING_BASE; |
2200 | ring->flush = bsd_ring_flush; |
2201 | ring->add_request = i9xx_add_request; |
2202 | ring->get_seqno = ring_get_seqno; |
2203 | ring->set_seqno = ring_set_seqno; |
2204 | if (IS_GEN5(dev)) { |
2205 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
2206 | ring->irq_get = gen5_ring_get_irq; |
2207 | ring->irq_put = gen5_ring_put_irq; |
2208 | } else { |
2209 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
2210 | ring->irq_get = i9xx_ring_get_irq; |
2211 | ring->irq_put = i9xx_ring_put_irq; |
2212 | } |
2213 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
2214 | } |
2215 | ring->init = init_ring_common; |
2216 | |
2217 | return intel_init_ring_buffer(dev, ring); |
2218 | } |
2219 | |
2220 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
2221 | { |
2222 | struct drm_i915_private *dev_priv = dev->dev_private; |
2223 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
2224 | |
2225 | ring->name = "blitter ring" ; |
2226 | ring->id = BCS; |
2227 | |
2228 | ring->mmio_base = BLT_RING_BASE; |
2229 | ring->write_tail = ring_write_tail; |
2230 | ring->flush = gen6_ring_flush; |
2231 | ring->add_request = gen6_add_request; |
2232 | ring->get_seqno = gen6_ring_get_seqno; |
2233 | ring->set_seqno = ring_set_seqno; |
2234 | if (INTEL_INFO(dev)->gen >= 8) { |
2235 | ring->irq_enable_mask = |
2236 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
2237 | ring->irq_get = gen8_ring_get_irq; |
2238 | ring->irq_put = gen8_ring_put_irq; |
2239 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
2240 | } else { |
2241 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
2242 | ring->irq_get = gen6_ring_get_irq; |
2243 | ring->irq_put = gen6_ring_put_irq; |
2244 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
2245 | } |
2246 | ring->sync_to = gen6_ring_sync; |
2247 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR; |
2248 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV; |
2249 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID; |
2250 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE; |
2251 | ring->signal_mbox[RCS] = GEN6_RBSYNC; |
2252 | ring->signal_mbox[VCS] = GEN6_VBSYNC; |
2253 | ring->signal_mbox[BCS] = GEN6_NOSYNC; |
2254 | ring->signal_mbox[VECS] = GEN6_VEBSYNC; |
2255 | ring->init = init_ring_common; |
2256 | |
2257 | return intel_init_ring_buffer(dev, ring); |
2258 | } |
2259 | |
2260 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2261 | { |
2262 | struct drm_i915_private *dev_priv = dev->dev_private; |
2263 | struct intel_ring_buffer *ring = &dev_priv->ring[VECS]; |
2264 | |
2265 | ring->name = "video enhancement ring" ; |
2266 | ring->id = VECS; |
2267 | |
2268 | ring->mmio_base = VEBOX_RING_BASE; |
2269 | ring->write_tail = ring_write_tail; |
2270 | ring->flush = gen6_ring_flush; |
2271 | ring->add_request = gen6_add_request; |
2272 | ring->get_seqno = gen6_ring_get_seqno; |
2273 | ring->set_seqno = ring_set_seqno; |
2274 | |
2275 | if (INTEL_INFO(dev)->gen >= 8) { |
2276 | ring->irq_enable_mask = |
2277 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
2278 | ring->irq_get = gen8_ring_get_irq; |
2279 | ring->irq_put = gen8_ring_put_irq; |
2280 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
2281 | } else { |
2282 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
2283 | ring->irq_get = hsw_vebox_get_irq; |
2284 | ring->irq_put = hsw_vebox_put_irq; |
2285 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
2286 | } |
2287 | ring->sync_to = gen6_ring_sync; |
2288 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER; |
2289 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV; |
2290 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB; |
2291 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID; |
2292 | ring->signal_mbox[RCS] = GEN6_RVESYNC; |
2293 | ring->signal_mbox[VCS] = GEN6_VVESYNC; |
2294 | ring->signal_mbox[BCS] = GEN6_BVESYNC; |
2295 | ring->signal_mbox[VECS] = GEN6_NOSYNC; |
2296 | ring->init = init_ring_common; |
2297 | |
2298 | return intel_init_ring_buffer(dev, ring); |
2299 | } |
2300 | |
2301 | int |
2302 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) |
2303 | { |
2304 | int ret; |
2305 | |
2306 | if (!ring->gpu_caches_dirty) |
2307 | return 0; |
2308 | |
2309 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); |
2310 | if (ret) |
2311 | return ret; |
2312 | |
2313 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); |
2314 | |
2315 | ring->gpu_caches_dirty = false; |
2316 | return 0; |
2317 | } |
2318 | |
2319 | int |
2320 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) |
2321 | { |
2322 | uint32_t flush_domains; |
2323 | int ret; |
2324 | |
2325 | flush_domains = 0; |
2326 | if (ring->gpu_caches_dirty) |
2327 | flush_domains = I915_GEM_GPU_DOMAINS; |
2328 | |
2329 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
2330 | if (ret) |
2331 | return ret; |
2332 | |
2333 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
2334 | |
2335 | ring->gpu_caches_dirty = false; |
2336 | return 0; |
2337 | } |
2338 | |