1 | /* $NetBSD: nouveau_engine_disp_nva3.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_disp_nva3.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $" ); |
29 | |
30 | #include <engine/software.h> |
31 | #include <engine/disp.h> |
32 | |
33 | #include <core/class.h> |
34 | |
35 | #include "nv50.h" |
36 | |
37 | /******************************************************************************* |
38 | * Base display object |
39 | ******************************************************************************/ |
40 | |
41 | static struct nouveau_oclass |
42 | nva3_disp_sclass[] = { |
43 | { NVA3_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, |
44 | { NVA3_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs }, |
45 | { NVA3_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs }, |
46 | { NVA3_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs }, |
47 | { NVA3_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs }, |
48 | {} |
49 | }; |
50 | |
51 | static struct nouveau_omthds |
52 | nva3_disp_base_omthds[] = { |
53 | { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos }, |
54 | { SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd }, |
55 | { SOR_MTHD(NVA3_DISP_SOR_HDA_ELD) , nv50_sor_mthd }, |
56 | { SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd }, |
57 | { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd }, |
58 | { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd }, |
59 | { DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd }, |
60 | { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, |
61 | { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, |
62 | { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd }, |
63 | {}, |
64 | }; |
65 | |
66 | static struct nouveau_oclass |
67 | nva3_disp_base_oclass[] = { |
68 | { NVA3_DISP_CLASS, &nv50_disp_base_ofuncs, nva3_disp_base_omthds }, |
69 | {} |
70 | }; |
71 | |
72 | /******************************************************************************* |
73 | * Display engine implementation |
74 | ******************************************************************************/ |
75 | |
76 | static int |
77 | nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
78 | struct nouveau_oclass *oclass, void *data, u32 size, |
79 | struct nouveau_object **pobject) |
80 | { |
81 | struct nv50_disp_priv *priv; |
82 | int ret; |
83 | |
84 | ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP" , |
85 | "display" , &priv); |
86 | *pobject = nv_object(priv); |
87 | if (ret) |
88 | return ret; |
89 | |
90 | nv_engine(priv)->sclass = nva3_disp_base_oclass; |
91 | nv_engine(priv)->cclass = &nv50_disp_cclass; |
92 | nv_subdev(priv)->intr = nv50_disp_intr; |
93 | INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); |
94 | priv->sclass = nva3_disp_sclass; |
95 | priv->head.nr = 2; |
96 | priv->dac.nr = 3; |
97 | priv->sor.nr = 4; |
98 | priv->pior.nr = 3; |
99 | priv->dac.power = nv50_dac_power; |
100 | priv->dac.sense = nv50_dac_sense; |
101 | priv->sor.power = nv50_sor_power; |
102 | priv->sor.hda_eld = nva3_hda_eld; |
103 | priv->sor.hdmi = nva3_hdmi_ctrl; |
104 | priv->sor.dp = &nv94_sor_dp_func; |
105 | priv->pior.power = nv50_pior_power; |
106 | priv->pior.dp = &nv50_pior_dp_func; |
107 | return 0; |
108 | } |
109 | |
110 | struct nouveau_oclass * |
111 | nva3_disp_oclass = &(struct nv50_disp_impl) { |
112 | .base.base.handle = NV_ENGINE(DISP, 0x85), |
113 | .base.base.ofuncs = &(struct nouveau_ofuncs) { |
114 | .ctor = nva3_disp_ctor, |
115 | .dtor = _nouveau_disp_dtor, |
116 | .init = _nouveau_disp_init, |
117 | .fini = _nouveau_disp_fini, |
118 | }, |
119 | .mthd.core = &nv94_disp_mast_mthd_chan, |
120 | .mthd.base = &nv84_disp_sync_mthd_chan, |
121 | .mthd.ovly = &nv84_disp_ovly_mthd_chan, |
122 | .mthd.prev = 0x000004, |
123 | }.base.base; |
124 | |