1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
3 | * Copyright © 2006-2007 Intel Corporation |
4 | * Jesse Barnes <jesse.barnes@intel.com> |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice (including the next |
14 | * paragraph) shall be included in all copies or substantial portions of the |
15 | * Software. |
16 | * |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
23 | * DEALINGS IN THE SOFTWARE. |
24 | * |
25 | * Authors: |
26 | * Eric Anholt <eric@anholt.net> |
27 | */ |
28 | #include <linux/i2c.h> |
29 | #include <linux/slab.h> |
30 | #include <linux/delay.h> |
31 | #include <linux/export.h> |
32 | #include <linux/bitops.h> |
33 | #include <linux/module.h> |
34 | #include <drm/drmP.h> |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> |
37 | #include "intel_drv.h" |
38 | #include <drm/i915_drm.h> |
39 | #include "i915_drv.h" |
40 | #include "intel_sdvo_regs.h" |
41 | |
42 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
43 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) |
44 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) |
45 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) |
46 | |
47 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ |
48 | SDVO_TV_MASK) |
49 | |
50 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) |
51 | #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) |
52 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
53 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
54 | #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) |
55 | |
56 | |
57 | static const char *tv_format_names[] = { |
58 | "NTSC_M" , "NTSC_J" , "NTSC_443" , |
59 | "PAL_B" , "PAL_D" , "PAL_G" , |
60 | "PAL_H" , "PAL_I" , "PAL_M" , |
61 | "PAL_N" , "PAL_NC" , "PAL_60" , |
62 | "SECAM_B" , "SECAM_D" , "SECAM_G" , |
63 | "SECAM_K" , "SECAM_K1" , "SECAM_L" , |
64 | "SECAM_60" |
65 | }; |
66 | |
67 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) |
68 | |
69 | struct intel_sdvo { |
70 | struct intel_encoder base; |
71 | |
72 | struct i2c_adapter *i2c; |
73 | u8 slave_addr; |
74 | |
75 | struct i2c_adapter ddc; |
76 | |
77 | /* Register for the SDVO device: SDVOB or SDVOC */ |
78 | uint32_t sdvo_reg; |
79 | |
80 | /* Active outputs controlled by this SDVO output */ |
81 | uint16_t controlled_output; |
82 | |
83 | /* |
84 | * Capabilities of the SDVO device returned by |
85 | * intel_sdvo_get_capabilities() |
86 | */ |
87 | struct intel_sdvo_caps caps; |
88 | |
89 | /* Pixel clock limitations reported by the SDVO device, in kHz */ |
90 | int pixel_clock_min, pixel_clock_max; |
91 | |
92 | /* |
93 | * For multiple function SDVO device, |
94 | * this is for current attached outputs. |
95 | */ |
96 | uint16_t attached_output; |
97 | |
98 | /* |
99 | * Hotplug activation bits for this device |
100 | */ |
101 | uint16_t hotplug_active; |
102 | |
103 | /** |
104 | * This is used to select the color range of RBG outputs in HDMI mode. |
105 | * It is only valid when using TMDS encoding and 8 bit per color mode. |
106 | */ |
107 | uint32_t color_range; |
108 | bool color_range_auto; |
109 | |
110 | /** |
111 | * This is set if we're going to treat the device as TV-out. |
112 | * |
113 | * While we have these nice friendly flags for output types that ought |
114 | * to decide this for us, the S-Video output on our HDMI+S-Video card |
115 | * shows up as RGB1 (VGA). |
116 | */ |
117 | bool is_tv; |
118 | |
119 | /* On different gens SDVOB is at different places. */ |
120 | bool is_sdvob; |
121 | |
122 | /* This is for current tv format name */ |
123 | int tv_format_index; |
124 | |
125 | /** |
126 | * This is set if we treat the device as HDMI, instead of DVI. |
127 | */ |
128 | bool is_hdmi; |
129 | bool has_hdmi_monitor; |
130 | bool has_hdmi_audio; |
131 | bool rgb_quant_range_selectable; |
132 | |
133 | /** |
134 | * This is set if we detect output of sdvo device as LVDS and |
135 | * have a valid fixed mode to use with the panel. |
136 | */ |
137 | bool is_lvds; |
138 | |
139 | /** |
140 | * This is sdvo fixed pannel mode pointer |
141 | */ |
142 | struct drm_display_mode *sdvo_lvds_fixed_mode; |
143 | |
144 | /* DDC bus used by this SDVO encoder */ |
145 | uint8_t ddc_bus; |
146 | |
147 | /* |
148 | * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd |
149 | */ |
150 | uint8_t dtd_sdvo_flags; |
151 | }; |
152 | |
153 | struct intel_sdvo_connector { |
154 | struct intel_connector base; |
155 | |
156 | /* Mark the type of connector */ |
157 | uint16_t output_flag; |
158 | |
159 | enum hdmi_force_audio force_audio; |
160 | |
161 | /* This contains all current supported TV format */ |
162 | u8 tv_format_supported[TV_FORMAT_NUM]; |
163 | int format_supported_num; |
164 | struct drm_property *tv_format; |
165 | |
166 | /* add the property for the SDVO-TV */ |
167 | struct drm_property *left; |
168 | struct drm_property *right; |
169 | struct drm_property *top; |
170 | struct drm_property *bottom; |
171 | struct drm_property *hpos; |
172 | struct drm_property *vpos; |
173 | struct drm_property *contrast; |
174 | struct drm_property *saturation; |
175 | struct drm_property *hue; |
176 | struct drm_property *sharpness; |
177 | struct drm_property *flicker_filter; |
178 | struct drm_property *flicker_filter_adaptive; |
179 | struct drm_property *flicker_filter_2d; |
180 | struct drm_property *tv_chroma_filter; |
181 | struct drm_property *tv_luma_filter; |
182 | struct drm_property *dot_crawl; |
183 | |
184 | /* add the property for the SDVO-TV/LVDS */ |
185 | struct drm_property *brightness; |
186 | |
187 | /* Add variable to record current setting for the above property */ |
188 | u32 left_margin, right_margin, top_margin, bottom_margin; |
189 | |
190 | /* this is to get the range of margin.*/ |
191 | u32 max_hscan, max_vscan; |
192 | u32 max_hpos, cur_hpos; |
193 | u32 max_vpos, cur_vpos; |
194 | u32 cur_brightness, max_brightness; |
195 | u32 cur_contrast, max_contrast; |
196 | u32 cur_saturation, max_saturation; |
197 | u32 cur_hue, max_hue; |
198 | u32 cur_sharpness, max_sharpness; |
199 | u32 cur_flicker_filter, max_flicker_filter; |
200 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; |
201 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; |
202 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; |
203 | u32 cur_tv_luma_filter, max_tv_luma_filter; |
204 | u32 cur_dot_crawl, max_dot_crawl; |
205 | }; |
206 | |
207 | static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) |
208 | { |
209 | return container_of(encoder, struct intel_sdvo, base); |
210 | } |
211 | |
212 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
213 | { |
214 | return to_sdvo(intel_attached_encoder(connector)); |
215 | } |
216 | |
217 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
218 | { |
219 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); |
220 | } |
221 | |
222 | static bool |
223 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
224 | static bool |
225 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
226 | struct intel_sdvo_connector *intel_sdvo_connector, |
227 | int type); |
228 | static bool |
229 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
230 | struct intel_sdvo_connector *intel_sdvo_connector); |
231 | |
232 | /** |
233 | * Writes the SDVOB or SDVOC with the given value, but always writes both |
234 | * SDVOB and SDVOC to work around apparent hardware issues (according to |
235 | * comments in the BIOS). |
236 | */ |
237 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
238 | { |
239 | struct drm_device *dev = intel_sdvo->base.base.dev; |
240 | struct drm_i915_private *dev_priv = dev->dev_private; |
241 | u32 bval = val, cval = val; |
242 | int i; |
243 | |
244 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { |
245 | I915_WRITE(intel_sdvo->sdvo_reg, val); |
246 | I915_READ(intel_sdvo->sdvo_reg); |
247 | return; |
248 | } |
249 | |
250 | if (intel_sdvo->sdvo_reg == GEN3_SDVOB) |
251 | cval = I915_READ(GEN3_SDVOC); |
252 | else |
253 | bval = I915_READ(GEN3_SDVOB); |
254 | |
255 | /* |
256 | * Write the registers twice for luck. Sometimes, |
257 | * writing them only once doesn't appear to 'stick'. |
258 | * The BIOS does this too. Yay, magic |
259 | */ |
260 | for (i = 0; i < 2; i++) |
261 | { |
262 | I915_WRITE(GEN3_SDVOB, bval); |
263 | I915_READ(GEN3_SDVOB); |
264 | I915_WRITE(GEN3_SDVOC, cval); |
265 | I915_READ(GEN3_SDVOC); |
266 | } |
267 | } |
268 | |
269 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
270 | { |
271 | struct i2c_msg msgs[] = { |
272 | { |
273 | .addr = intel_sdvo->slave_addr, |
274 | .flags = 0, |
275 | .len = 1, |
276 | .buf = &addr, |
277 | }, |
278 | { |
279 | .addr = intel_sdvo->slave_addr, |
280 | .flags = I2C_M_RD, |
281 | .len = 1, |
282 | .buf = ch, |
283 | } |
284 | }; |
285 | int ret; |
286 | |
287 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
288 | return true; |
289 | |
290 | DRM_DEBUG_KMS("i2c transfer returned %d\n" , ret); |
291 | return false; |
292 | } |
293 | |
294 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
295 | /** Mapping of command numbers to names, for debug output */ |
296 | static const struct _sdvo_cmd_name { |
297 | u8 cmd; |
298 | const char *name; |
299 | } sdvo_cmd_names[] = { |
300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), |
302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), |
303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), |
304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), |
305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), |
306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), |
307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), |
308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), |
309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), |
310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), |
311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), |
312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), |
313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), |
314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), |
315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), |
316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), |
317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), |
319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), |
321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), |
322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), |
323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), |
324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), |
325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), |
326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), |
327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), |
328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), |
329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), |
330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), |
331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), |
332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), |
333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), |
334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), |
335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), |
336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), |
337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), |
338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), |
339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), |
340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), |
341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), |
342 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), |
343 | |
344 | /* Add the op code for SDVO enhancements */ |
345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), |
346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), |
347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), |
348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), |
349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), |
350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), |
351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), |
352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), |
353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), |
354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), |
355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), |
356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), |
357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), |
358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), |
359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), |
360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), |
361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), |
362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), |
363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), |
364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), |
365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), |
366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), |
367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), |
368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), |
369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), |
370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), |
371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), |
372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), |
373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), |
374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), |
375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), |
376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), |
377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), |
378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), |
379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), |
380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), |
381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), |
382 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), |
383 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), |
384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), |
385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), |
386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), |
387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), |
388 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), |
389 | |
390 | /* HDMI op code */ |
391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), |
392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), |
393 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), |
394 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), |
395 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), |
396 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), |
397 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), |
398 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), |
399 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), |
400 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), |
401 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), |
402 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), |
403 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), |
404 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), |
405 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), |
406 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), |
407 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), |
408 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), |
409 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), |
410 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), |
411 | }; |
412 | |
413 | #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") |
414 | |
415 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
416 | const void *args, int args_len) |
417 | { |
418 | int i, pos = 0; |
419 | #define BUF_LEN 256 |
420 | char buffer[BUF_LEN]; |
421 | |
422 | #define BUF_PRINT(args...) \ |
423 | pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) |
424 | |
425 | |
426 | for (i = 0; i < args_len; i++) { |
427 | BUF_PRINT("%02X " , ((const u8 *)args)[i]); |
428 | } |
429 | for (; i < 8; i++) { |
430 | BUF_PRINT(" " ); |
431 | } |
432 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
433 | if (cmd == sdvo_cmd_names[i].cmd) { |
434 | BUF_PRINT("(%s)" , sdvo_cmd_names[i].name); |
435 | break; |
436 | } |
437 | } |
438 | if (i == ARRAY_SIZE(sdvo_cmd_names)) { |
439 | BUF_PRINT("(%02X)" , cmd); |
440 | } |
441 | BUG_ON(pos >= BUF_LEN - 1); |
442 | #undef BUF_PRINT |
443 | #undef BUF_LEN |
444 | |
445 | DRM_DEBUG_KMS("%s: W: %02X %s\n" , SDVO_NAME(intel_sdvo), cmd, buffer); |
446 | } |
447 | |
448 | static const char *cmd_status_names[] = { |
449 | "Power on" , |
450 | "Success" , |
451 | "Not supported" , |
452 | "Invalid arg" , |
453 | "Pending" , |
454 | "Target not specified" , |
455 | "Scaling not supported" |
456 | }; |
457 | |
458 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
459 | const void *args, int args_len) |
460 | { |
461 | u8 *buf, status; |
462 | struct i2c_msg *msgs; |
463 | int i, ret = true; |
464 | |
465 | /* Would be simpler to allocate both in one go ? */ |
466 | buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); |
467 | if (!buf) |
468 | return false; |
469 | |
470 | msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); |
471 | if (!msgs) { |
472 | kfree(buf); |
473 | return false; |
474 | } |
475 | |
476 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
477 | |
478 | for (i = 0; i < args_len; i++) { |
479 | msgs[i].addr = intel_sdvo->slave_addr; |
480 | msgs[i].flags = 0; |
481 | msgs[i].len = 2; |
482 | msgs[i].buf = buf + 2 *i; |
483 | buf[2*i + 0] = SDVO_I2C_ARG_0 - i; |
484 | buf[2*i + 1] = ((const u8*)args)[i]; |
485 | } |
486 | msgs[i].addr = intel_sdvo->slave_addr; |
487 | msgs[i].flags = 0; |
488 | msgs[i].len = 2; |
489 | msgs[i].buf = buf + 2*i; |
490 | buf[2*i + 0] = SDVO_I2C_OPCODE; |
491 | buf[2*i + 1] = cmd; |
492 | |
493 | /* the following two are to read the response */ |
494 | status = SDVO_I2C_CMD_STATUS; |
495 | msgs[i+1].addr = intel_sdvo->slave_addr; |
496 | msgs[i+1].flags = 0; |
497 | msgs[i+1].len = 1; |
498 | msgs[i+1].buf = &status; |
499 | |
500 | msgs[i+2].addr = intel_sdvo->slave_addr; |
501 | msgs[i+2].flags = I2C_M_RD; |
502 | msgs[i+2].len = 1; |
503 | msgs[i+2].buf = &status; |
504 | |
505 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); |
506 | if (ret < 0) { |
507 | DRM_DEBUG_KMS("I2c transfer returned %d\n" , ret); |
508 | ret = false; |
509 | goto out; |
510 | } |
511 | if (ret != i+3) { |
512 | /* failure in I2C transfer */ |
513 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n" , ret, i+3); |
514 | ret = false; |
515 | } |
516 | |
517 | out: |
518 | kfree(msgs); |
519 | kfree(buf); |
520 | return ret; |
521 | } |
522 | |
523 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
524 | void *response, int response_len) |
525 | { |
526 | u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ |
527 | u8 status; |
528 | int i, pos = 0; |
529 | #define BUF_LEN 256 |
530 | char buffer[BUF_LEN]; |
531 | |
532 | |
533 | /* |
534 | * The documentation states that all commands will be |
535 | * processed within 15µs, and that we need only poll |
536 | * the status byte a maximum of 3 times in order for the |
537 | * command to be complete. |
538 | * |
539 | * Check 5 times in case the hardware failed to read the docs. |
540 | * |
541 | * Also beware that the first response by many devices is to |
542 | * reply PENDING and stall for time. TVs are notorious for |
543 | * requiring longer than specified to complete their replies. |
544 | * Originally (in the DDX long ago), the delay was only ever 15ms |
545 | * with an additional delay of 30ms applied for TVs added later after |
546 | * many experiments. To accommodate both sets of delays, we do a |
547 | * sequence of slow checks if the device is falling behind and fails |
548 | * to reply within 5*15µs. |
549 | */ |
550 | if (!intel_sdvo_read_byte(intel_sdvo, |
551 | SDVO_I2C_CMD_STATUS, |
552 | &status)) |
553 | goto log_fail; |
554 | |
555 | while ((status == SDVO_CMD_STATUS_PENDING || |
556 | status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { |
557 | if (retry < 10) |
558 | msleep(15); |
559 | else |
560 | udelay(15); |
561 | |
562 | if (!intel_sdvo_read_byte(intel_sdvo, |
563 | SDVO_I2C_CMD_STATUS, |
564 | &status)) |
565 | goto log_fail; |
566 | } |
567 | |
568 | #define BUF_PRINT(args...) \ |
569 | pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) |
570 | |
571 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
572 | BUF_PRINT("(%s)" , cmd_status_names[status]); |
573 | else |
574 | BUF_PRINT("(??? %d)" , status); |
575 | |
576 | if (status != SDVO_CMD_STATUS_SUCCESS) |
577 | goto log_fail; |
578 | |
579 | /* Read the command response */ |
580 | for (i = 0; i < response_len; i++) { |
581 | if (!intel_sdvo_read_byte(intel_sdvo, |
582 | SDVO_I2C_RETURN_0 + i, |
583 | &((u8 *)response)[i])) |
584 | goto log_fail; |
585 | BUF_PRINT(" %02X" , ((u8 *)response)[i]); |
586 | } |
587 | BUG_ON(pos >= BUF_LEN - 1); |
588 | #undef BUF_PRINT |
589 | #undef BUF_LEN |
590 | |
591 | DRM_DEBUG_KMS("%s: R: %s\n" , SDVO_NAME(intel_sdvo), buffer); |
592 | return true; |
593 | |
594 | log_fail: |
595 | DRM_DEBUG_KMS("%s: R: ... failed\n" , SDVO_NAME(intel_sdvo)); |
596 | return false; |
597 | } |
598 | |
599 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
600 | { |
601 | if (mode->clock >= 100000) |
602 | return 1; |
603 | else if (mode->clock >= 50000) |
604 | return 2; |
605 | else |
606 | return 4; |
607 | } |
608 | |
609 | static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
610 | u8 ddc_bus) |
611 | { |
612 | /* This must be the immediately preceding write before the i2c xfer */ |
613 | return intel_sdvo_write_cmd(intel_sdvo, |
614 | SDVO_CMD_SET_CONTROL_BUS_SWITCH, |
615 | &ddc_bus, 1); |
616 | } |
617 | |
618 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
619 | { |
620 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
621 | return false; |
622 | |
623 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); |
624 | } |
625 | |
626 | static bool |
627 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) |
628 | { |
629 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) |
630 | return false; |
631 | |
632 | return intel_sdvo_read_response(intel_sdvo, value, len); |
633 | } |
634 | |
635 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
636 | { |
637 | #ifdef __NetBSD__ |
638 | static const struct intel_sdvo_set_target_input_args zero_targets; |
639 | struct intel_sdvo_set_target_input_args targets = zero_targets; |
640 | #else |
641 | struct intel_sdvo_set_target_input_args targets = {0}; |
642 | #endif |
643 | return intel_sdvo_set_value(intel_sdvo, |
644 | SDVO_CMD_SET_TARGET_INPUT, |
645 | &targets, sizeof(targets)); |
646 | } |
647 | |
648 | /** |
649 | * Return whether each input is trained. |
650 | * |
651 | * This function is making an assumption about the layout of the response, |
652 | * which should be checked against the docs. |
653 | */ |
654 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
655 | { |
656 | struct intel_sdvo_get_trained_inputs_response response; |
657 | |
658 | BUILD_BUG_ON(sizeof(response) != 1); |
659 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
660 | &response, sizeof(response))) |
661 | return false; |
662 | |
663 | *input_1 = response.input0_trained; |
664 | *input_2 = response.input1_trained; |
665 | return true; |
666 | } |
667 | |
668 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
669 | u16 outputs) |
670 | { |
671 | return intel_sdvo_set_value(intel_sdvo, |
672 | SDVO_CMD_SET_ACTIVE_OUTPUTS, |
673 | &outputs, sizeof(outputs)); |
674 | } |
675 | |
676 | static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, |
677 | u16 *outputs) |
678 | { |
679 | return intel_sdvo_get_value(intel_sdvo, |
680 | SDVO_CMD_GET_ACTIVE_OUTPUTS, |
681 | outputs, sizeof(*outputs)); |
682 | } |
683 | |
684 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
685 | int mode) |
686 | { |
687 | u8 state = SDVO_ENCODER_STATE_ON; |
688 | |
689 | switch (mode) { |
690 | case DRM_MODE_DPMS_ON: |
691 | state = SDVO_ENCODER_STATE_ON; |
692 | break; |
693 | case DRM_MODE_DPMS_STANDBY: |
694 | state = SDVO_ENCODER_STATE_STANDBY; |
695 | break; |
696 | case DRM_MODE_DPMS_SUSPEND: |
697 | state = SDVO_ENCODER_STATE_SUSPEND; |
698 | break; |
699 | case DRM_MODE_DPMS_OFF: |
700 | state = SDVO_ENCODER_STATE_OFF; |
701 | break; |
702 | } |
703 | |
704 | return intel_sdvo_set_value(intel_sdvo, |
705 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); |
706 | } |
707 | |
708 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
709 | int *clock_min, |
710 | int *clock_max) |
711 | { |
712 | struct intel_sdvo_pixel_clock_range clocks; |
713 | |
714 | BUILD_BUG_ON(sizeof(clocks) != 4); |
715 | if (!intel_sdvo_get_value(intel_sdvo, |
716 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, |
717 | &clocks, sizeof(clocks))) |
718 | return false; |
719 | |
720 | /* Convert the values from units of 10 kHz to kHz. */ |
721 | *clock_min = clocks.min * 10; |
722 | *clock_max = clocks.max * 10; |
723 | return true; |
724 | } |
725 | |
726 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
727 | u16 outputs) |
728 | { |
729 | return intel_sdvo_set_value(intel_sdvo, |
730 | SDVO_CMD_SET_TARGET_OUTPUT, |
731 | &outputs, sizeof(outputs)); |
732 | } |
733 | |
734 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
735 | struct intel_sdvo_dtd *dtd) |
736 | { |
737 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
738 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); |
739 | } |
740 | |
741 | static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
742 | struct intel_sdvo_dtd *dtd) |
743 | { |
744 | return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
745 | intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); |
746 | } |
747 | |
748 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
749 | struct intel_sdvo_dtd *dtd) |
750 | { |
751 | return intel_sdvo_set_timing(intel_sdvo, |
752 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
753 | } |
754 | |
755 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
756 | struct intel_sdvo_dtd *dtd) |
757 | { |
758 | return intel_sdvo_set_timing(intel_sdvo, |
759 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
760 | } |
761 | |
762 | static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, |
763 | struct intel_sdvo_dtd *dtd) |
764 | { |
765 | return intel_sdvo_get_timing(intel_sdvo, |
766 | SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); |
767 | } |
768 | |
769 | static bool |
770 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
771 | uint16_t clock, |
772 | uint16_t width, |
773 | uint16_t height) |
774 | { |
775 | struct intel_sdvo_preferred_input_timing_args args; |
776 | |
777 | memset(&args, 0, sizeof(args)); |
778 | args.clock = clock; |
779 | args.width = width; |
780 | args.height = height; |
781 | args.interlace = 0; |
782 | |
783 | if (intel_sdvo->is_lvds && |
784 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || |
785 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) |
786 | args.scaled = 1; |
787 | |
788 | return intel_sdvo_set_value(intel_sdvo, |
789 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, |
790 | &args, sizeof(args)); |
791 | } |
792 | |
793 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
794 | struct intel_sdvo_dtd *dtd) |
795 | { |
796 | BUILD_BUG_ON(sizeof(dtd->part1) != 8); |
797 | BUILD_BUG_ON(sizeof(dtd->part2) != 8); |
798 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
799 | &dtd->part1, sizeof(dtd->part1)) && |
800 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, |
801 | &dtd->part2, sizeof(dtd->part2)); |
802 | } |
803 | |
804 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
805 | { |
806 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
807 | } |
808 | |
809 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
810 | const struct drm_display_mode *mode) |
811 | { |
812 | uint16_t width, height; |
813 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; |
814 | uint16_t h_sync_offset, v_sync_offset; |
815 | int mode_clock; |
816 | |
817 | memset(dtd, 0, sizeof(*dtd)); |
818 | |
819 | width = mode->hdisplay; |
820 | height = mode->vdisplay; |
821 | |
822 | /* do some mode translations */ |
823 | h_blank_len = mode->htotal - mode->hdisplay; |
824 | h_sync_len = mode->hsync_end - mode->hsync_start; |
825 | |
826 | v_blank_len = mode->vtotal - mode->vdisplay; |
827 | v_sync_len = mode->vsync_end - mode->vsync_start; |
828 | |
829 | h_sync_offset = mode->hsync_start - mode->hdisplay; |
830 | v_sync_offset = mode->vsync_start - mode->vdisplay; |
831 | |
832 | mode_clock = mode->clock; |
833 | mode_clock /= 10; |
834 | dtd->part1.clock = mode_clock; |
835 | |
836 | dtd->part1.h_active = width & 0xff; |
837 | dtd->part1.h_blank = h_blank_len & 0xff; |
838 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | |
839 | ((h_blank_len >> 8) & 0xf); |
840 | dtd->part1.v_active = height & 0xff; |
841 | dtd->part1.v_blank = v_blank_len & 0xff; |
842 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | |
843 | ((v_blank_len >> 8) & 0xf); |
844 | |
845 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
846 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
847 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | |
848 | (v_sync_len & 0xf); |
849 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
850 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
851 | ((v_sync_len & 0x30) >> 4); |
852 | |
853 | dtd->part2.dtd_flags = 0x18; |
854 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
855 | dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; |
856 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
857 | dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; |
858 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
859 | dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; |
860 | |
861 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
862 | } |
863 | |
864 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, |
865 | const struct intel_sdvo_dtd *dtd) |
866 | { |
867 | static const struct drm_display_mode zero_mode; |
868 | struct drm_display_mode mode = zero_mode; |
869 | |
870 | mode.hdisplay = dtd->part1.h_active; |
871 | mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; |
872 | mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; |
873 | mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
874 | mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; |
875 | mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; |
876 | mode.htotal = mode.hdisplay + dtd->part1.h_blank; |
877 | mode.htotal += (dtd->part1.h_high & 0xf) << 8; |
878 | |
879 | mode.vdisplay = dtd->part1.v_active; |
880 | mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; |
881 | mode.vsync_start = mode.vdisplay; |
882 | mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; |
883 | mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
884 | mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
885 | mode.vsync_end = mode.vsync_start + |
886 | (dtd->part2.v_sync_off_width & 0xf); |
887 | mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
888 | mode.vtotal = mode.vdisplay + dtd->part1.v_blank; |
889 | mode.vtotal += (dtd->part1.v_high & 0xf) << 8; |
890 | |
891 | mode.clock = dtd->part1.clock * 10; |
892 | |
893 | if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) |
894 | mode.flags |= DRM_MODE_FLAG_INTERLACE; |
895 | if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) |
896 | mode.flags |= DRM_MODE_FLAG_PHSYNC; |
897 | else |
898 | mode.flags |= DRM_MODE_FLAG_NHSYNC; |
899 | if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
900 | mode.flags |= DRM_MODE_FLAG_PVSYNC; |
901 | else |
902 | mode.flags |= DRM_MODE_FLAG_NVSYNC; |
903 | |
904 | drm_mode_set_crtcinfo(&mode, 0); |
905 | |
906 | drm_mode_copy(pmode, &mode); |
907 | } |
908 | |
909 | static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) |
910 | { |
911 | struct intel_sdvo_encode encode; |
912 | |
913 | BUILD_BUG_ON(sizeof(encode) != 2); |
914 | return intel_sdvo_get_value(intel_sdvo, |
915 | SDVO_CMD_GET_SUPP_ENCODE, |
916 | &encode, sizeof(encode)); |
917 | } |
918 | |
919 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
920 | uint8_t mode) |
921 | { |
922 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
923 | } |
924 | |
925 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
926 | uint8_t mode) |
927 | { |
928 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
929 | } |
930 | |
931 | #if 0 |
932 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
933 | { |
934 | int i, j; |
935 | uint8_t set_buf_index[2]; |
936 | uint8_t av_split; |
937 | uint8_t buf_size; |
938 | uint8_t buf[48]; |
939 | uint8_t *pos; |
940 | |
941 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
942 | |
943 | for (i = 0; i <= av_split; i++) { |
944 | set_buf_index[0] = i; set_buf_index[1] = 0; |
945 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
946 | set_buf_index, 2); |
947 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
948 | intel_sdvo_read_response(encoder, &buf_size, 1); |
949 | |
950 | pos = buf; |
951 | for (j = 0; j <= buf_size; j += 8) { |
952 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
953 | NULL, 0); |
954 | intel_sdvo_read_response(encoder, pos, 8); |
955 | pos += 8; |
956 | } |
957 | } |
958 | } |
959 | #endif |
960 | |
961 | static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, |
962 | unsigned if_index, uint8_t tx_rate, |
963 | const uint8_t *data, unsigned length) |
964 | { |
965 | uint8_t set_buf_index[2] = { if_index, 0 }; |
966 | uint8_t hbuf_size, tmp[8]; |
967 | int i; |
968 | |
969 | if (!intel_sdvo_set_value(intel_sdvo, |
970 | SDVO_CMD_SET_HBUF_INDEX, |
971 | set_buf_index, 2)) |
972 | return false; |
973 | |
974 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, |
975 | &hbuf_size, 1)) |
976 | return false; |
977 | |
978 | /* Buffer size is 0 based, hooray! */ |
979 | hbuf_size++; |
980 | |
981 | DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n" , |
982 | if_index, length, hbuf_size); |
983 | |
984 | for (i = 0; i < hbuf_size; i += 8) { |
985 | memset(tmp, 0, 8); |
986 | if (i < length) |
987 | memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); |
988 | |
989 | if (!intel_sdvo_set_value(intel_sdvo, |
990 | SDVO_CMD_SET_HBUF_DATA, |
991 | tmp, 8)) |
992 | return false; |
993 | } |
994 | |
995 | return intel_sdvo_set_value(intel_sdvo, |
996 | SDVO_CMD_SET_HBUF_TXRATE, |
997 | &tx_rate, 1); |
998 | } |
999 | |
1000 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, |
1001 | const struct drm_display_mode *adjusted_mode) |
1002 | { |
1003 | uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; |
1004 | struct drm_crtc *crtc = intel_sdvo->base.base.crtc; |
1005 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1006 | union hdmi_infoframe frame; |
1007 | int ret; |
1008 | ssize_t len; |
1009 | |
1010 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
1011 | adjusted_mode); |
1012 | if (ret < 0) { |
1013 | DRM_ERROR("couldn't fill AVI infoframe\n" ); |
1014 | return false; |
1015 | } |
1016 | |
1017 | if (intel_sdvo->rgb_quant_range_selectable) { |
1018 | if (intel_crtc->config.limited_color_range) |
1019 | frame.avi.quantization_range = |
1020 | HDMI_QUANTIZATION_RANGE_LIMITED; |
1021 | else |
1022 | frame.avi.quantization_range = |
1023 | HDMI_QUANTIZATION_RANGE_FULL; |
1024 | } |
1025 | |
1026 | len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data)); |
1027 | if (len < 0) |
1028 | return false; |
1029 | |
1030 | return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, |
1031 | SDVO_HBUF_TX_VSYNC, |
1032 | sdvo_data, sizeof(sdvo_data)); |
1033 | } |
1034 | |
1035 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
1036 | { |
1037 | struct intel_sdvo_tv_format format; |
1038 | uint32_t format_map; |
1039 | |
1040 | format_map = 1 << intel_sdvo->tv_format_index; |
1041 | memset(&format, 0, sizeof(format)); |
1042 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
1043 | |
1044 | BUILD_BUG_ON(sizeof(format) != 6); |
1045 | return intel_sdvo_set_value(intel_sdvo, |
1046 | SDVO_CMD_SET_TV_FORMAT, |
1047 | &format, sizeof(format)); |
1048 | } |
1049 | |
1050 | static bool |
1051 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, |
1052 | const struct drm_display_mode *mode) |
1053 | { |
1054 | struct intel_sdvo_dtd output_dtd; |
1055 | |
1056 | if (!intel_sdvo_set_target_output(intel_sdvo, |
1057 | intel_sdvo->attached_output)) |
1058 | return false; |
1059 | |
1060 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
1061 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
1062 | return false; |
1063 | |
1064 | return true; |
1065 | } |
1066 | |
1067 | /* Asks the sdvo controller for the preferred input mode given the output mode. |
1068 | * Unfortunately we have to set up the full output mode to do that. */ |
1069 | static bool |
1070 | intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, |
1071 | const struct drm_display_mode *mode, |
1072 | struct drm_display_mode *adjusted_mode) |
1073 | { |
1074 | struct intel_sdvo_dtd input_dtd; |
1075 | |
1076 | /* Reset the input timing to the screen. Assume always input 0. */ |
1077 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
1078 | return false; |
1079 | |
1080 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
1081 | mode->clock / 10, |
1082 | mode->hdisplay, |
1083 | mode->vdisplay)) |
1084 | return false; |
1085 | |
1086 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
1087 | &input_dtd)) |
1088 | return false; |
1089 | |
1090 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
1091 | intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; |
1092 | |
1093 | return true; |
1094 | } |
1095 | |
1096 | static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config) |
1097 | { |
1098 | unsigned dotclock = pipe_config->port_clock; |
1099 | struct dpll *clock = &pipe_config->dpll; |
1100 | |
1101 | /* SDVO TV has fixed PLL values depend on its clock range, |
1102 | this mirrors vbios setting. */ |
1103 | if (dotclock >= 100000 && dotclock < 140500) { |
1104 | clock->p1 = 2; |
1105 | clock->p2 = 10; |
1106 | clock->n = 3; |
1107 | clock->m1 = 16; |
1108 | clock->m2 = 8; |
1109 | } else if (dotclock >= 140500 && dotclock <= 200000) { |
1110 | clock->p1 = 1; |
1111 | clock->p2 = 10; |
1112 | clock->n = 6; |
1113 | clock->m1 = 12; |
1114 | clock->m2 = 8; |
1115 | } else { |
1116 | WARN(1, "SDVO TV clock out of range: %i\n" , dotclock); |
1117 | } |
1118 | |
1119 | pipe_config->clock_set = true; |
1120 | } |
1121 | |
1122 | static bool intel_sdvo_compute_config(struct intel_encoder *encoder, |
1123 | struct intel_crtc_config *pipe_config) |
1124 | { |
1125 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
1126 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
1127 | struct drm_display_mode *mode = &pipe_config->requested_mode; |
1128 | |
1129 | DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n" ); |
1130 | pipe_config->pipe_bpp = 8*3; |
1131 | |
1132 | if (HAS_PCH_SPLIT(encoder->base.dev)) |
1133 | pipe_config->has_pch_encoder = true; |
1134 | |
1135 | /* We need to construct preferred input timings based on our |
1136 | * output timings. To do that, we have to set the output |
1137 | * timings, even though this isn't really the right place in |
1138 | * the sequence to do it. Oh well. |
1139 | */ |
1140 | if (intel_sdvo->is_tv) { |
1141 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) |
1142 | return false; |
1143 | |
1144 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
1145 | mode, |
1146 | adjusted_mode); |
1147 | pipe_config->sdvo_tv_clock = true; |
1148 | } else if (intel_sdvo->is_lvds) { |
1149 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
1150 | intel_sdvo->sdvo_lvds_fixed_mode)) |
1151 | return false; |
1152 | |
1153 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
1154 | mode, |
1155 | adjusted_mode); |
1156 | } |
1157 | |
1158 | /* Make the CRTC code factor in the SDVO pixel multiplier. The |
1159 | * SDVO device will factor out the multiplier during mode_set. |
1160 | */ |
1161 | pipe_config->pixel_multiplier = |
1162 | intel_sdvo_get_pixel_multiplier(adjusted_mode); |
1163 | |
1164 | if (intel_sdvo->color_range_auto) { |
1165 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
1166 | /* FIXME: This bit is only valid when using TMDS encoding and 8 |
1167 | * bit per color mode. */ |
1168 | if (intel_sdvo->has_hdmi_monitor && |
1169 | drm_match_cea_mode(adjusted_mode) > 1) |
1170 | intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; |
1171 | else |
1172 | intel_sdvo->color_range = 0; |
1173 | } |
1174 | |
1175 | if (intel_sdvo->color_range) |
1176 | pipe_config->limited_color_range = true; |
1177 | |
1178 | /* Clock computation needs to happen after pixel multiplier. */ |
1179 | if (intel_sdvo->is_tv) |
1180 | i9xx_adjust_sdvo_tv_clock(pipe_config); |
1181 | |
1182 | return true; |
1183 | } |
1184 | |
1185 | static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder) |
1186 | { |
1187 | struct drm_device *dev = intel_encoder->base.dev; |
1188 | struct drm_i915_private *dev_priv = dev->dev_private; |
1189 | struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); |
1190 | struct drm_display_mode *adjusted_mode = |
1191 | &crtc->config.adjusted_mode; |
1192 | struct drm_display_mode *mode = &crtc->config.requested_mode; |
1193 | struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); |
1194 | u32 sdvox; |
1195 | struct intel_sdvo_in_out_map in_out; |
1196 | struct intel_sdvo_dtd input_dtd, output_dtd; |
1197 | int rate; |
1198 | |
1199 | if (!mode) |
1200 | return; |
1201 | |
1202 | /* First, set the input mapping for the first input to our controlled |
1203 | * output. This is only correct if we're a single-input device, in |
1204 | * which case the first input is the output from the appropriate SDVO |
1205 | * channel on the motherboard. In a two-input device, the first input |
1206 | * will be SDVOB and the second SDVOC. |
1207 | */ |
1208 | in_out.in0 = intel_sdvo->attached_output; |
1209 | in_out.in1 = 0; |
1210 | |
1211 | intel_sdvo_set_value(intel_sdvo, |
1212 | SDVO_CMD_SET_IN_OUT_MAP, |
1213 | &in_out, sizeof(in_out)); |
1214 | |
1215 | /* Set the output timings to the screen */ |
1216 | if (!intel_sdvo_set_target_output(intel_sdvo, |
1217 | intel_sdvo->attached_output)) |
1218 | return; |
1219 | |
1220 | /* lvds has a special fixed output timing. */ |
1221 | if (intel_sdvo->is_lvds) |
1222 | intel_sdvo_get_dtd_from_mode(&output_dtd, |
1223 | intel_sdvo->sdvo_lvds_fixed_mode); |
1224 | else |
1225 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
1226 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
1227 | DRM_INFO("Setting output timings on %s failed\n" , |
1228 | SDVO_NAME(intel_sdvo)); |
1229 | |
1230 | /* Set the input timing to the screen. Assume always input 0. */ |
1231 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
1232 | return; |
1233 | |
1234 | if (intel_sdvo->has_hdmi_monitor) { |
1235 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); |
1236 | intel_sdvo_set_colorimetry(intel_sdvo, |
1237 | SDVO_COLORIMETRY_RGB256); |
1238 | intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); |
1239 | } else |
1240 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); |
1241 | |
1242 | if (intel_sdvo->is_tv && |
1243 | !intel_sdvo_set_tv_format(intel_sdvo)) |
1244 | return; |
1245 | |
1246 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
1247 | |
1248 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) |
1249 | input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; |
1250 | if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) |
1251 | DRM_INFO("Setting input timings on %s failed\n" , |
1252 | SDVO_NAME(intel_sdvo)); |
1253 | |
1254 | switch (crtc->config.pixel_multiplier) { |
1255 | default: |
1256 | WARN(1, "unknown pixel mutlipler specified\n" ); |
1257 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
1258 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; |
1259 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; |
1260 | } |
1261 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
1262 | return; |
1263 | |
1264 | /* Set the SDVO control regs. */ |
1265 | if (INTEL_INFO(dev)->gen >= 4) { |
1266 | /* The real mode polarity is set by the SDVO commands, using |
1267 | * struct intel_sdvo_dtd. */ |
1268 | sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; |
1269 | if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi) |
1270 | sdvox |= intel_sdvo->color_range; |
1271 | if (INTEL_INFO(dev)->gen < 5) |
1272 | sdvox |= SDVO_BORDER_ENABLE; |
1273 | } else { |
1274 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
1275 | switch (intel_sdvo->sdvo_reg) { |
1276 | case GEN3_SDVOB: |
1277 | sdvox &= SDVOB_PRESERVE_MASK; |
1278 | break; |
1279 | case GEN3_SDVOC: |
1280 | sdvox &= SDVOC_PRESERVE_MASK; |
1281 | break; |
1282 | } |
1283 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; |
1284 | } |
1285 | |
1286 | if (INTEL_PCH_TYPE(dev) >= PCH_CPT) |
1287 | sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
1288 | else |
1289 | sdvox |= SDVO_PIPE_SEL(crtc->pipe); |
1290 | |
1291 | if (intel_sdvo->has_hdmi_audio) |
1292 | sdvox |= SDVO_AUDIO_ENABLE; |
1293 | |
1294 | if (INTEL_INFO(dev)->gen >= 4) { |
1295 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
1296 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
1297 | /* done in crtc_mode_set as it lives inside the dpll register */ |
1298 | } else { |
1299 | sdvox |= (crtc->config.pixel_multiplier - 1) |
1300 | << SDVO_PORT_MULTIPLY_SHIFT; |
1301 | } |
1302 | |
1303 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && |
1304 | INTEL_INFO(dev)->gen < 5) |
1305 | sdvox |= SDVO_STALL_SELECT; |
1306 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
1307 | } |
1308 | |
1309 | static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) |
1310 | { |
1311 | struct intel_sdvo_connector *intel_sdvo_connector = |
1312 | to_intel_sdvo_connector(&connector->base); |
1313 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); |
1314 | u16 active_outputs = 0; |
1315 | |
1316 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); |
1317 | |
1318 | if (active_outputs & intel_sdvo_connector->output_flag) |
1319 | return true; |
1320 | else |
1321 | return false; |
1322 | } |
1323 | |
1324 | static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, |
1325 | enum i915_pipe *pipe) |
1326 | { |
1327 | struct drm_device *dev = encoder->base.dev; |
1328 | struct drm_i915_private *dev_priv = dev->dev_private; |
1329 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
1330 | u16 active_outputs = 0; |
1331 | u32 tmp; |
1332 | |
1333 | tmp = I915_READ(intel_sdvo->sdvo_reg); |
1334 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); |
1335 | |
1336 | if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) |
1337 | return false; |
1338 | |
1339 | if (HAS_PCH_CPT(dev)) |
1340 | *pipe = PORT_TO_PIPE_CPT(tmp); |
1341 | else |
1342 | *pipe = PORT_TO_PIPE(tmp); |
1343 | |
1344 | return true; |
1345 | } |
1346 | |
1347 | static void intel_sdvo_get_config(struct intel_encoder *encoder, |
1348 | struct intel_crtc_config *pipe_config) |
1349 | { |
1350 | struct drm_device *dev = encoder->base.dev; |
1351 | struct drm_i915_private *dev_priv = dev->dev_private; |
1352 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
1353 | struct intel_sdvo_dtd dtd; |
1354 | int encoder_pixel_multiplier = 0; |
1355 | int dotclock; |
1356 | u32 flags = 0, sdvox; |
1357 | u8 val; |
1358 | bool ret; |
1359 | |
1360 | ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); |
1361 | if (!ret) { |
1362 | /* Some sdvo encoders are not spec compliant and don't |
1363 | * implement the mandatory get_timings function. */ |
1364 | DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n" ); |
1365 | pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; |
1366 | } else { |
1367 | if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) |
1368 | flags |= DRM_MODE_FLAG_PHSYNC; |
1369 | else |
1370 | flags |= DRM_MODE_FLAG_NHSYNC; |
1371 | |
1372 | if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
1373 | flags |= DRM_MODE_FLAG_PVSYNC; |
1374 | else |
1375 | flags |= DRM_MODE_FLAG_NVSYNC; |
1376 | } |
1377 | |
1378 | pipe_config->adjusted_mode.flags |= flags; |
1379 | |
1380 | /* |
1381 | * pixel multiplier readout is tricky: Only on i915g/gm it is stored in |
1382 | * the sdvo port register, on all other platforms it is part of the dpll |
1383 | * state. Since the general pipe state readout happens before the |
1384 | * encoder->get_config we so already have a valid pixel multplier on all |
1385 | * other platfroms. |
1386 | */ |
1387 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
1388 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
1389 | pipe_config->pixel_multiplier = |
1390 | ((sdvox & SDVO_PORT_MULTIPLY_MASK) |
1391 | >> SDVO_PORT_MULTIPLY_SHIFT) + 1; |
1392 | } |
1393 | |
1394 | dotclock = pipe_config->port_clock / pipe_config->pixel_multiplier; |
1395 | |
1396 | if (HAS_PCH_SPLIT(dev)) |
1397 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
1398 | |
1399 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
1400 | |
1401 | /* Cross check the port pixel multiplier with the sdvo encoder state. */ |
1402 | if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, |
1403 | &val, 1)) { |
1404 | switch (val) { |
1405 | case SDVO_CLOCK_RATE_MULT_1X: |
1406 | encoder_pixel_multiplier = 1; |
1407 | break; |
1408 | case SDVO_CLOCK_RATE_MULT_2X: |
1409 | encoder_pixel_multiplier = 2; |
1410 | break; |
1411 | case SDVO_CLOCK_RATE_MULT_4X: |
1412 | encoder_pixel_multiplier = 4; |
1413 | break; |
1414 | } |
1415 | } |
1416 | |
1417 | WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, |
1418 | "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n" , |
1419 | pipe_config->pixel_multiplier, encoder_pixel_multiplier); |
1420 | } |
1421 | |
1422 | static void intel_disable_sdvo(struct intel_encoder *encoder) |
1423 | { |
1424 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1425 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
1426 | u32 temp; |
1427 | |
1428 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
1429 | if (0) |
1430 | intel_sdvo_set_encoder_power_state(intel_sdvo, |
1431 | DRM_MODE_DPMS_OFF); |
1432 | |
1433 | temp = I915_READ(intel_sdvo->sdvo_reg); |
1434 | if ((temp & SDVO_ENABLE) != 0) { |
1435 | /* HW workaround for IBX, we need to move the port to |
1436 | * transcoder A before disabling it. */ |
1437 | if (HAS_PCH_IBX(encoder->base.dev)) { |
1438 | struct drm_crtc *crtc = encoder->base.crtc; |
1439 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
1440 | |
1441 | if (temp & SDVO_PIPE_B_SELECT) { |
1442 | temp &= ~SDVO_PIPE_B_SELECT; |
1443 | I915_WRITE(intel_sdvo->sdvo_reg, temp); |
1444 | POSTING_READ(intel_sdvo->sdvo_reg); |
1445 | |
1446 | /* Again we need to write this twice. */ |
1447 | I915_WRITE(intel_sdvo->sdvo_reg, temp); |
1448 | POSTING_READ(intel_sdvo->sdvo_reg); |
1449 | |
1450 | /* Transcoder selection bits only update |
1451 | * effectively on vblank. */ |
1452 | if (crtc) |
1453 | intel_wait_for_vblank(encoder->base.dev, pipe); |
1454 | else |
1455 | msleep(50); |
1456 | } |
1457 | } |
1458 | |
1459 | intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); |
1460 | } |
1461 | } |
1462 | |
1463 | static void intel_enable_sdvo(struct intel_encoder *encoder) |
1464 | { |
1465 | struct drm_device *dev = encoder->base.dev; |
1466 | struct drm_i915_private *dev_priv = dev->dev_private; |
1467 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
1468 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
1469 | u32 temp; |
1470 | bool input1, input2; |
1471 | int i; |
1472 | bool success; |
1473 | |
1474 | temp = I915_READ(intel_sdvo->sdvo_reg); |
1475 | if ((temp & SDVO_ENABLE) == 0) { |
1476 | /* HW workaround for IBX, we need to move the port |
1477 | * to transcoder A before disabling it, so restore it here. */ |
1478 | if (HAS_PCH_IBX(dev)) |
1479 | temp |= SDVO_PIPE_SEL(intel_crtc->pipe); |
1480 | |
1481 | intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); |
1482 | } |
1483 | for (i = 0; i < 2; i++) |
1484 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
1485 | |
1486 | success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); |
1487 | /* Warn if the device reported failure to sync. |
1488 | * A lot of SDVO devices fail to notify of sync, but it's |
1489 | * a given it the status is a success, we succeeded. |
1490 | */ |
1491 | if (success && !input1) { |
1492 | DRM_DEBUG_KMS("First %s output reported failure to " |
1493 | "sync\n" , SDVO_NAME(intel_sdvo)); |
1494 | } |
1495 | |
1496 | if (0) |
1497 | intel_sdvo_set_encoder_power_state(intel_sdvo, |
1498 | DRM_MODE_DPMS_ON); |
1499 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); |
1500 | } |
1501 | |
1502 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
1503 | static void intel_sdvo_dpms(struct drm_connector *connector, int mode) |
1504 | { |
1505 | struct drm_crtc *crtc; |
1506 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
1507 | |
1508 | /* dvo supports only 2 dpms states. */ |
1509 | if (mode != DRM_MODE_DPMS_ON) |
1510 | mode = DRM_MODE_DPMS_OFF; |
1511 | |
1512 | if (mode == connector->dpms) |
1513 | return; |
1514 | |
1515 | connector->dpms = mode; |
1516 | |
1517 | /* Only need to change hw state when actually enabled */ |
1518 | crtc = intel_sdvo->base.base.crtc; |
1519 | if (!crtc) { |
1520 | intel_sdvo->base.connectors_active = false; |
1521 | return; |
1522 | } |
1523 | |
1524 | /* We set active outputs manually below in case pipe dpms doesn't change |
1525 | * due to cloning. */ |
1526 | if (mode != DRM_MODE_DPMS_ON) { |
1527 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
1528 | if (0) |
1529 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
1530 | |
1531 | intel_sdvo->base.connectors_active = false; |
1532 | |
1533 | intel_crtc_update_dpms(crtc); |
1534 | } else { |
1535 | intel_sdvo->base.connectors_active = true; |
1536 | |
1537 | intel_crtc_update_dpms(crtc); |
1538 | |
1539 | if (0) |
1540 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
1541 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); |
1542 | } |
1543 | |
1544 | intel_modeset_check_state(connector->dev); |
1545 | } |
1546 | |
1547 | static enum drm_mode_status |
1548 | intel_sdvo_mode_valid(struct drm_connector *connector, |
1549 | struct drm_display_mode *mode) |
1550 | { |
1551 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
1552 | |
1553 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
1554 | return MODE_NO_DBLESCAN; |
1555 | |
1556 | if (intel_sdvo->pixel_clock_min > mode->clock) |
1557 | return MODE_CLOCK_LOW; |
1558 | |
1559 | if (intel_sdvo->pixel_clock_max < mode->clock) |
1560 | return MODE_CLOCK_HIGH; |
1561 | |
1562 | if (intel_sdvo->is_lvds) { |
1563 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
1564 | return MODE_PANEL; |
1565 | |
1566 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
1567 | return MODE_PANEL; |
1568 | } |
1569 | |
1570 | return MODE_OK; |
1571 | } |
1572 | |
1573 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
1574 | { |
1575 | BUILD_BUG_ON(sizeof(*caps) != 8); |
1576 | if (!intel_sdvo_get_value(intel_sdvo, |
1577 | SDVO_CMD_GET_DEVICE_CAPS, |
1578 | caps, sizeof(*caps))) |
1579 | return false; |
1580 | |
1581 | DRM_DEBUG_KMS("SDVO capabilities:\n" |
1582 | " vendor_id: %d\n" |
1583 | " device_id: %d\n" |
1584 | " device_rev_id: %d\n" |
1585 | " sdvo_version_major: %d\n" |
1586 | " sdvo_version_minor: %d\n" |
1587 | " sdvo_inputs_mask: %d\n" |
1588 | " smooth_scaling: %d\n" |
1589 | " sharp_scaling: %d\n" |
1590 | " up_scaling: %d\n" |
1591 | " down_scaling: %d\n" |
1592 | " stall_support: %d\n" |
1593 | " output_flags: %d\n" , |
1594 | caps->vendor_id, |
1595 | caps->device_id, |
1596 | caps->device_rev_id, |
1597 | caps->sdvo_version_major, |
1598 | caps->sdvo_version_minor, |
1599 | caps->sdvo_inputs_mask, |
1600 | caps->smooth_scaling, |
1601 | caps->sharp_scaling, |
1602 | caps->up_scaling, |
1603 | caps->down_scaling, |
1604 | caps->stall_support, |
1605 | caps->output_flags); |
1606 | |
1607 | return true; |
1608 | } |
1609 | |
1610 | static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) |
1611 | { |
1612 | struct drm_device *dev = intel_sdvo->base.base.dev; |
1613 | uint16_t hotplug; |
1614 | |
1615 | /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise |
1616 | * on the line. */ |
1617 | if (IS_I945G(dev) || IS_I945GM(dev)) |
1618 | return 0; |
1619 | |
1620 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
1621 | &hotplug, sizeof(hotplug))) |
1622 | return 0; |
1623 | |
1624 | return hotplug; |
1625 | } |
1626 | |
1627 | static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) |
1628 | { |
1629 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
1630 | |
1631 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, |
1632 | &intel_sdvo->hotplug_active, 2); |
1633 | } |
1634 | |
1635 | static bool |
1636 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
1637 | { |
1638 | /* Is there more than one type of output? */ |
1639 | return hweight16(intel_sdvo->caps.output_flags) > 1; |
1640 | } |
1641 | |
1642 | static struct edid * |
1643 | intel_sdvo_get_edid(struct drm_connector *connector) |
1644 | { |
1645 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); |
1646 | return drm_get_edid(connector, &sdvo->ddc); |
1647 | } |
1648 | |
1649 | /* Mac mini hack -- use the same DDC as the analog connector */ |
1650 | static struct edid * |
1651 | intel_sdvo_get_analog_edid(struct drm_connector *connector) |
1652 | { |
1653 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
1654 | |
1655 | return drm_get_edid(connector, |
1656 | intel_gmbus_get_adapter(dev_priv, |
1657 | dev_priv->vbt.crt_ddc_pin)); |
1658 | } |
1659 | |
1660 | static enum drm_connector_status |
1661 | intel_sdvo_tmds_sink_detect(struct drm_connector *connector) |
1662 | { |
1663 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
1664 | enum drm_connector_status status; |
1665 | struct edid *edid; |
1666 | |
1667 | edid = intel_sdvo_get_edid(connector); |
1668 | |
1669 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
1670 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
1671 | |
1672 | /* |
1673 | * Don't use the 1 as the argument of DDC bus switch to get |
1674 | * the EDID. It is used for SDVO SPD ROM. |
1675 | */ |
1676 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
1677 | intel_sdvo->ddc_bus = ddc; |
1678 | edid = intel_sdvo_get_edid(connector); |
1679 | if (edid) |
1680 | break; |
1681 | } |
1682 | /* |
1683 | * If we found the EDID on the other bus, |
1684 | * assume that is the correct DDC bus. |
1685 | */ |
1686 | if (edid == NULL) |
1687 | intel_sdvo->ddc_bus = saved_ddc; |
1688 | } |
1689 | |
1690 | /* |
1691 | * When there is no edid and no monitor is connected with VGA |
1692 | * port, try to use the CRT ddc to read the EDID for DVI-connector. |
1693 | */ |
1694 | if (edid == NULL) |
1695 | edid = intel_sdvo_get_analog_edid(connector); |
1696 | |
1697 | status = connector_status_unknown; |
1698 | if (edid != NULL) { |
1699 | /* DDC bus is shared, match EDID to connector type */ |
1700 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
1701 | status = connector_status_connected; |
1702 | if (intel_sdvo->is_hdmi) { |
1703 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); |
1704 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); |
1705 | intel_sdvo->rgb_quant_range_selectable = |
1706 | drm_rgb_quant_range_selectable(edid); |
1707 | } |
1708 | } else |
1709 | status = connector_status_disconnected; |
1710 | kfree(edid); |
1711 | } |
1712 | |
1713 | if (status == connector_status_connected) { |
1714 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
1715 | if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) |
1716 | intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); |
1717 | } |
1718 | |
1719 | return status; |
1720 | } |
1721 | |
1722 | static bool |
1723 | intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, |
1724 | struct edid *edid) |
1725 | { |
1726 | bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); |
1727 | bool connector_is_digital = !!IS_DIGITAL(sdvo); |
1728 | |
1729 | DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n" , |
1730 | connector_is_digital, monitor_is_digital); |
1731 | return connector_is_digital == monitor_is_digital; |
1732 | } |
1733 | |
1734 | static enum drm_connector_status |
1735 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
1736 | { |
1737 | uint16_t response; |
1738 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
1739 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
1740 | enum drm_connector_status ret; |
1741 | |
1742 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n" , |
1743 | connector->base.id, drm_get_connector_name(connector)); |
1744 | |
1745 | if (!intel_sdvo_get_value(intel_sdvo, |
1746 | SDVO_CMD_GET_ATTACHED_DISPLAYS, |
1747 | &response, 2)) |
1748 | return connector_status_unknown; |
1749 | |
1750 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n" , |
1751 | response & 0xff, response >> 8, |
1752 | intel_sdvo_connector->output_flag); |
1753 | |
1754 | if (response == 0) |
1755 | return connector_status_disconnected; |
1756 | |
1757 | intel_sdvo->attached_output = response; |
1758 | |
1759 | intel_sdvo->has_hdmi_monitor = false; |
1760 | intel_sdvo->has_hdmi_audio = false; |
1761 | intel_sdvo->rgb_quant_range_selectable = false; |
1762 | |
1763 | if ((intel_sdvo_connector->output_flag & response) == 0) |
1764 | ret = connector_status_disconnected; |
1765 | else if (IS_TMDS(intel_sdvo_connector)) |
1766 | ret = intel_sdvo_tmds_sink_detect(connector); |
1767 | else { |
1768 | struct edid *edid; |
1769 | |
1770 | /* if we have an edid check it matches the connection */ |
1771 | edid = intel_sdvo_get_edid(connector); |
1772 | if (edid == NULL) |
1773 | edid = intel_sdvo_get_analog_edid(connector); |
1774 | if (edid != NULL) { |
1775 | if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, |
1776 | edid)) |
1777 | ret = connector_status_connected; |
1778 | else |
1779 | ret = connector_status_disconnected; |
1780 | |
1781 | kfree(edid); |
1782 | } else |
1783 | ret = connector_status_connected; |
1784 | } |
1785 | |
1786 | /* May update encoder flag for like clock for SDVO TV, etc.*/ |
1787 | if (ret == connector_status_connected) { |
1788 | intel_sdvo->is_tv = false; |
1789 | intel_sdvo->is_lvds = false; |
1790 | |
1791 | if (response & SDVO_TV_MASK) |
1792 | intel_sdvo->is_tv = true; |
1793 | if (response & SDVO_LVDS_MASK) |
1794 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
1795 | } |
1796 | |
1797 | return ret; |
1798 | } |
1799 | |
1800 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
1801 | { |
1802 | struct edid *edid; |
1803 | |
1804 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n" , |
1805 | connector->base.id, drm_get_connector_name(connector)); |
1806 | |
1807 | /* set the bus switch and get the modes */ |
1808 | edid = intel_sdvo_get_edid(connector); |
1809 | |
1810 | /* |
1811 | * Mac mini hack. On this device, the DVI-I connector shares one DDC |
1812 | * link between analog and digital outputs. So, if the regular SDVO |
1813 | * DDC fails, check to see if the analog output is disconnected, in |
1814 | * which case we'll look there for the digital DDC data. |
1815 | */ |
1816 | if (edid == NULL) |
1817 | edid = intel_sdvo_get_analog_edid(connector); |
1818 | |
1819 | if (edid != NULL) { |
1820 | if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), |
1821 | edid)) { |
1822 | drm_mode_connector_update_edid_property(connector, edid); |
1823 | drm_add_edid_modes(connector, edid); |
1824 | } |
1825 | |
1826 | kfree(edid); |
1827 | } |
1828 | } |
1829 | |
1830 | /* |
1831 | * Set of SDVO TV modes. |
1832 | * Note! This is in reply order (see loop in get_tv_modes). |
1833 | * XXX: all 60Hz refresh? |
1834 | */ |
1835 | static const struct drm_display_mode sdvo_tv_modes[] = { |
1836 | { DRM_MODE("320x200" , DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
1837 | 416, 0, 200, 201, 232, 233, 0, |
1838 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1839 | { DRM_MODE("320x240" , DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
1840 | 416, 0, 240, 241, 272, 273, 0, |
1841 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1842 | { DRM_MODE("400x300" , DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
1843 | 496, 0, 300, 301, 332, 333, 0, |
1844 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1845 | { DRM_MODE("640x350" , DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
1846 | 736, 0, 350, 351, 382, 383, 0, |
1847 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1848 | { DRM_MODE("640x400" , DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
1849 | 736, 0, 400, 401, 432, 433, 0, |
1850 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1851 | { DRM_MODE("640x480" , DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
1852 | 736, 0, 480, 481, 512, 513, 0, |
1853 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1854 | { DRM_MODE("704x480" , DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
1855 | 800, 0, 480, 481, 512, 513, 0, |
1856 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1857 | { DRM_MODE("704x576" , DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
1858 | 800, 0, 576, 577, 608, 609, 0, |
1859 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1860 | { DRM_MODE("720x350" , DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
1861 | 816, 0, 350, 351, 382, 383, 0, |
1862 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1863 | { DRM_MODE("720x400" , DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
1864 | 816, 0, 400, 401, 432, 433, 0, |
1865 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1866 | { DRM_MODE("720x480" , DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
1867 | 816, 0, 480, 481, 512, 513, 0, |
1868 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1869 | { DRM_MODE("720x540" , DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
1870 | 816, 0, 540, 541, 572, 573, 0, |
1871 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1872 | { DRM_MODE("720x576" , DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
1873 | 816, 0, 576, 577, 608, 609, 0, |
1874 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1875 | { DRM_MODE("768x576" , DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
1876 | 864, 0, 576, 577, 608, 609, 0, |
1877 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1878 | { DRM_MODE("800x600" , DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
1879 | 896, 0, 600, 601, 632, 633, 0, |
1880 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1881 | { DRM_MODE("832x624" , DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
1882 | 928, 0, 624, 625, 656, 657, 0, |
1883 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1884 | { DRM_MODE("920x766" , DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
1885 | 1016, 0, 766, 767, 798, 799, 0, |
1886 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1887 | { DRM_MODE("1024x768" , DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
1888 | 1120, 0, 768, 769, 800, 801, 0, |
1889 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1890 | { DRM_MODE("1280x1024" , DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
1891 | 1376, 0, 1024, 1025, 1056, 1057, 0, |
1892 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1893 | }; |
1894 | |
1895 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) |
1896 | { |
1897 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
1898 | struct intel_sdvo_sdtv_resolution_request tv_res; |
1899 | uint32_t reply = 0, format_map = 0; |
1900 | int i; |
1901 | |
1902 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n" , |
1903 | connector->base.id, drm_get_connector_name(connector)); |
1904 | |
1905 | /* Read the list of supported input resolutions for the selected TV |
1906 | * format. |
1907 | */ |
1908 | format_map = 1 << intel_sdvo->tv_format_index; |
1909 | memcpy(&tv_res, &format_map, |
1910 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
1911 | |
1912 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
1913 | return; |
1914 | |
1915 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
1916 | if (!intel_sdvo_write_cmd(intel_sdvo, |
1917 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, |
1918 | &tv_res, sizeof(tv_res))) |
1919 | return; |
1920 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) |
1921 | return; |
1922 | |
1923 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) |
1924 | if (reply & (1 << i)) { |
1925 | struct drm_display_mode *nmode; |
1926 | nmode = drm_mode_duplicate(connector->dev, |
1927 | &sdvo_tv_modes[i]); |
1928 | if (nmode) |
1929 | drm_mode_probed_add(connector, nmode); |
1930 | } |
1931 | } |
1932 | |
1933 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
1934 | { |
1935 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
1936 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
1937 | struct drm_display_mode *newmode; |
1938 | |
1939 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n" , |
1940 | connector->base.id, drm_get_connector_name(connector)); |
1941 | |
1942 | /* |
1943 | * Fetch modes from VBT. For SDVO prefer the VBT mode since some |
1944 | * SDVO->LVDS transcoders can't cope with the EDID mode. |
1945 | */ |
1946 | if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { |
1947 | newmode = drm_mode_duplicate(connector->dev, |
1948 | dev_priv->vbt.sdvo_lvds_vbt_mode); |
1949 | if (newmode != NULL) { |
1950 | /* Guarantee the mode is preferred */ |
1951 | newmode->type = (DRM_MODE_TYPE_PREFERRED | |
1952 | DRM_MODE_TYPE_DRIVER); |
1953 | drm_mode_probed_add(connector, newmode); |
1954 | } |
1955 | } |
1956 | |
1957 | /* |
1958 | * Attempt to get the mode list from DDC. |
1959 | * Assume that the preferred modes are |
1960 | * arranged in priority order. |
1961 | */ |
1962 | intel_ddc_get_modes(connector, &intel_sdvo->ddc); |
1963 | |
1964 | list_for_each_entry(newmode, &connector->probed_modes, head) { |
1965 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { |
1966 | intel_sdvo->sdvo_lvds_fixed_mode = |
1967 | drm_mode_duplicate(connector->dev, newmode); |
1968 | |
1969 | intel_sdvo->is_lvds = true; |
1970 | break; |
1971 | } |
1972 | } |
1973 | } |
1974 | |
1975 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
1976 | { |
1977 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
1978 | |
1979 | if (IS_TV(intel_sdvo_connector)) |
1980 | intel_sdvo_get_tv_modes(connector); |
1981 | else if (IS_LVDS(intel_sdvo_connector)) |
1982 | intel_sdvo_get_lvds_modes(connector); |
1983 | else |
1984 | intel_sdvo_get_ddc_modes(connector); |
1985 | |
1986 | return !list_empty(&connector->probed_modes); |
1987 | } |
1988 | |
1989 | static void |
1990 | intel_sdvo_destroy_enhance_property(struct drm_connector *connector) |
1991 | { |
1992 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
1993 | struct drm_device *dev = connector->dev; |
1994 | |
1995 | if (intel_sdvo_connector->left) |
1996 | drm_property_destroy(dev, intel_sdvo_connector->left); |
1997 | if (intel_sdvo_connector->right) |
1998 | drm_property_destroy(dev, intel_sdvo_connector->right); |
1999 | if (intel_sdvo_connector->top) |
2000 | drm_property_destroy(dev, intel_sdvo_connector->top); |
2001 | if (intel_sdvo_connector->bottom) |
2002 | drm_property_destroy(dev, intel_sdvo_connector->bottom); |
2003 | if (intel_sdvo_connector->hpos) |
2004 | drm_property_destroy(dev, intel_sdvo_connector->hpos); |
2005 | if (intel_sdvo_connector->vpos) |
2006 | drm_property_destroy(dev, intel_sdvo_connector->vpos); |
2007 | if (intel_sdvo_connector->saturation) |
2008 | drm_property_destroy(dev, intel_sdvo_connector->saturation); |
2009 | if (intel_sdvo_connector->contrast) |
2010 | drm_property_destroy(dev, intel_sdvo_connector->contrast); |
2011 | if (intel_sdvo_connector->hue) |
2012 | drm_property_destroy(dev, intel_sdvo_connector->hue); |
2013 | if (intel_sdvo_connector->sharpness) |
2014 | drm_property_destroy(dev, intel_sdvo_connector->sharpness); |
2015 | if (intel_sdvo_connector->flicker_filter) |
2016 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); |
2017 | if (intel_sdvo_connector->flicker_filter_2d) |
2018 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); |
2019 | if (intel_sdvo_connector->flicker_filter_adaptive) |
2020 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); |
2021 | if (intel_sdvo_connector->tv_luma_filter) |
2022 | drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); |
2023 | if (intel_sdvo_connector->tv_chroma_filter) |
2024 | drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); |
2025 | if (intel_sdvo_connector->dot_crawl) |
2026 | drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); |
2027 | if (intel_sdvo_connector->brightness) |
2028 | drm_property_destroy(dev, intel_sdvo_connector->brightness); |
2029 | } |
2030 | |
2031 | static void intel_sdvo_destroy(struct drm_connector *connector) |
2032 | { |
2033 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
2034 | |
2035 | if (intel_sdvo_connector->tv_format) |
2036 | drm_property_destroy(connector->dev, |
2037 | intel_sdvo_connector->tv_format); |
2038 | |
2039 | intel_sdvo_destroy_enhance_property(connector); |
2040 | drm_connector_cleanup(connector); |
2041 | kfree(intel_sdvo_connector); |
2042 | } |
2043 | |
2044 | static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) |
2045 | { |
2046 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
2047 | struct edid *edid; |
2048 | bool has_audio = false; |
2049 | |
2050 | if (!intel_sdvo->is_hdmi) |
2051 | return false; |
2052 | |
2053 | edid = intel_sdvo_get_edid(connector); |
2054 | if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) |
2055 | has_audio = drm_detect_monitor_audio(edid); |
2056 | kfree(edid); |
2057 | |
2058 | return has_audio; |
2059 | } |
2060 | |
2061 | static int |
2062 | intel_sdvo_set_property(struct drm_connector *connector, |
2063 | struct drm_property *property, |
2064 | uint64_t val) |
2065 | { |
2066 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
2067 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
2068 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
2069 | uint16_t temp_value; |
2070 | uint8_t cmd; |
2071 | int ret; |
2072 | |
2073 | ret = drm_object_property_set_value(&connector->base, property, val); |
2074 | if (ret) |
2075 | return ret; |
2076 | |
2077 | if (property == dev_priv->force_audio_property) { |
2078 | int i = val; |
2079 | bool has_audio; |
2080 | |
2081 | if (i == intel_sdvo_connector->force_audio) |
2082 | return 0; |
2083 | |
2084 | intel_sdvo_connector->force_audio = i; |
2085 | |
2086 | if (i == HDMI_AUDIO_AUTO) |
2087 | has_audio = intel_sdvo_detect_hdmi_audio(connector); |
2088 | else |
2089 | has_audio = (i == HDMI_AUDIO_ON); |
2090 | |
2091 | if (has_audio == intel_sdvo->has_hdmi_audio) |
2092 | return 0; |
2093 | |
2094 | intel_sdvo->has_hdmi_audio = has_audio; |
2095 | goto done; |
2096 | } |
2097 | |
2098 | if (property == dev_priv->broadcast_rgb_property) { |
2099 | bool old_auto = intel_sdvo->color_range_auto; |
2100 | uint32_t old_range = intel_sdvo->color_range; |
2101 | |
2102 | switch (val) { |
2103 | case INTEL_BROADCAST_RGB_AUTO: |
2104 | intel_sdvo->color_range_auto = true; |
2105 | break; |
2106 | case INTEL_BROADCAST_RGB_FULL: |
2107 | intel_sdvo->color_range_auto = false; |
2108 | intel_sdvo->color_range = 0; |
2109 | break; |
2110 | case INTEL_BROADCAST_RGB_LIMITED: |
2111 | intel_sdvo->color_range_auto = false; |
2112 | /* FIXME: this bit is only valid when using TMDS |
2113 | * encoding and 8 bit per color mode. */ |
2114 | intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; |
2115 | break; |
2116 | default: |
2117 | return -EINVAL; |
2118 | } |
2119 | |
2120 | if (old_auto == intel_sdvo->color_range_auto && |
2121 | old_range == intel_sdvo->color_range) |
2122 | return 0; |
2123 | |
2124 | goto done; |
2125 | } |
2126 | |
2127 | #define CHECK_PROPERTY(name, NAME) \ |
2128 | if (intel_sdvo_connector->name == property) { \ |
2129 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ |
2130 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ |
2131 | cmd = SDVO_CMD_SET_##NAME; \ |
2132 | intel_sdvo_connector->cur_##name = temp_value; \ |
2133 | goto set_value; \ |
2134 | } |
2135 | |
2136 | if (property == intel_sdvo_connector->tv_format) { |
2137 | if (val >= TV_FORMAT_NUM) |
2138 | return -EINVAL; |
2139 | |
2140 | if (intel_sdvo->tv_format_index == |
2141 | intel_sdvo_connector->tv_format_supported[val]) |
2142 | return 0; |
2143 | |
2144 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
2145 | goto done; |
2146 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
2147 | temp_value = val; |
2148 | if (intel_sdvo_connector->left == property) { |
2149 | drm_object_property_set_value(&connector->base, |
2150 | intel_sdvo_connector->right, val); |
2151 | if (intel_sdvo_connector->left_margin == temp_value) |
2152 | return 0; |
2153 | |
2154 | intel_sdvo_connector->left_margin = temp_value; |
2155 | intel_sdvo_connector->right_margin = temp_value; |
2156 | temp_value = intel_sdvo_connector->max_hscan - |
2157 | intel_sdvo_connector->left_margin; |
2158 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
2159 | goto set_value; |
2160 | } else if (intel_sdvo_connector->right == property) { |
2161 | drm_object_property_set_value(&connector->base, |
2162 | intel_sdvo_connector->left, val); |
2163 | if (intel_sdvo_connector->right_margin == temp_value) |
2164 | return 0; |
2165 | |
2166 | intel_sdvo_connector->left_margin = temp_value; |
2167 | intel_sdvo_connector->right_margin = temp_value; |
2168 | temp_value = intel_sdvo_connector->max_hscan - |
2169 | intel_sdvo_connector->left_margin; |
2170 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
2171 | goto set_value; |
2172 | } else if (intel_sdvo_connector->top == property) { |
2173 | drm_object_property_set_value(&connector->base, |
2174 | intel_sdvo_connector->bottom, val); |
2175 | if (intel_sdvo_connector->top_margin == temp_value) |
2176 | return 0; |
2177 | |
2178 | intel_sdvo_connector->top_margin = temp_value; |
2179 | intel_sdvo_connector->bottom_margin = temp_value; |
2180 | temp_value = intel_sdvo_connector->max_vscan - |
2181 | intel_sdvo_connector->top_margin; |
2182 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
2183 | goto set_value; |
2184 | } else if (intel_sdvo_connector->bottom == property) { |
2185 | drm_object_property_set_value(&connector->base, |
2186 | intel_sdvo_connector->top, val); |
2187 | if (intel_sdvo_connector->bottom_margin == temp_value) |
2188 | return 0; |
2189 | |
2190 | intel_sdvo_connector->top_margin = temp_value; |
2191 | intel_sdvo_connector->bottom_margin = temp_value; |
2192 | temp_value = intel_sdvo_connector->max_vscan - |
2193 | intel_sdvo_connector->top_margin; |
2194 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
2195 | goto set_value; |
2196 | } |
2197 | CHECK_PROPERTY(hpos, HPOS) |
2198 | CHECK_PROPERTY(vpos, VPOS) |
2199 | CHECK_PROPERTY(saturation, SATURATION) |
2200 | CHECK_PROPERTY(contrast, CONTRAST) |
2201 | CHECK_PROPERTY(hue, HUE) |
2202 | CHECK_PROPERTY(brightness, BRIGHTNESS) |
2203 | CHECK_PROPERTY(sharpness, SHARPNESS) |
2204 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) |
2205 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) |
2206 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) |
2207 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) |
2208 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) |
2209 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
2210 | } |
2211 | |
2212 | return -EINVAL; /* unknown property */ |
2213 | |
2214 | set_value: |
2215 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) |
2216 | return -EIO; |
2217 | |
2218 | |
2219 | done: |
2220 | if (intel_sdvo->base.base.crtc) |
2221 | intel_crtc_restore_mode(intel_sdvo->base.base.crtc); |
2222 | |
2223 | return 0; |
2224 | #undef CHECK_PROPERTY |
2225 | } |
2226 | |
2227 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
2228 | .dpms = intel_sdvo_dpms, |
2229 | .detect = intel_sdvo_detect, |
2230 | .fill_modes = drm_helper_probe_single_connector_modes, |
2231 | .set_property = intel_sdvo_set_property, |
2232 | .destroy = intel_sdvo_destroy, |
2233 | }; |
2234 | |
2235 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { |
2236 | .get_modes = intel_sdvo_get_modes, |
2237 | .mode_valid = intel_sdvo_mode_valid, |
2238 | .best_encoder = intel_best_encoder, |
2239 | }; |
2240 | |
2241 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
2242 | { |
2243 | struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); |
2244 | |
2245 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
2246 | drm_mode_destroy(encoder->dev, |
2247 | intel_sdvo->sdvo_lvds_fixed_mode); |
2248 | |
2249 | i2c_del_adapter(&intel_sdvo->ddc); |
2250 | intel_encoder_destroy(encoder); |
2251 | } |
2252 | |
2253 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { |
2254 | .destroy = intel_sdvo_enc_destroy, |
2255 | }; |
2256 | |
2257 | static void |
2258 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) |
2259 | { |
2260 | uint16_t mask = 0; |
2261 | unsigned int num_bits; |
2262 | |
2263 | /* Make a mask of outputs less than or equal to our own priority in the |
2264 | * list. |
2265 | */ |
2266 | switch (sdvo->controlled_output) { |
2267 | case SDVO_OUTPUT_LVDS1: |
2268 | mask |= SDVO_OUTPUT_LVDS1; |
2269 | case SDVO_OUTPUT_LVDS0: |
2270 | mask |= SDVO_OUTPUT_LVDS0; |
2271 | case SDVO_OUTPUT_TMDS1: |
2272 | mask |= SDVO_OUTPUT_TMDS1; |
2273 | case SDVO_OUTPUT_TMDS0: |
2274 | mask |= SDVO_OUTPUT_TMDS0; |
2275 | case SDVO_OUTPUT_RGB1: |
2276 | mask |= SDVO_OUTPUT_RGB1; |
2277 | case SDVO_OUTPUT_RGB0: |
2278 | mask |= SDVO_OUTPUT_RGB0; |
2279 | break; |
2280 | } |
2281 | |
2282 | /* Count bits to find what number we are in the priority list. */ |
2283 | mask &= sdvo->caps.output_flags; |
2284 | num_bits = hweight16(mask); |
2285 | /* If more than 3 outputs, default to DDC bus 3 for now. */ |
2286 | if (num_bits > 3) |
2287 | num_bits = 3; |
2288 | |
2289 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ |
2290 | sdvo->ddc_bus = 1 << num_bits; |
2291 | } |
2292 | |
2293 | /** |
2294 | * Choose the appropriate DDC bus for control bus switch command for this |
2295 | * SDVO output based on the controlled output. |
2296 | * |
2297 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS |
2298 | * outputs, then LVDS outputs. |
2299 | */ |
2300 | static void |
2301 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
2302 | struct intel_sdvo *sdvo, u32 reg) |
2303 | { |
2304 | struct sdvo_device_mapping *mapping; |
2305 | |
2306 | if (sdvo->is_sdvob) |
2307 | mapping = &(dev_priv->sdvo_mappings[0]); |
2308 | else |
2309 | mapping = &(dev_priv->sdvo_mappings[1]); |
2310 | |
2311 | if (mapping->initialized) |
2312 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); |
2313 | else |
2314 | intel_sdvo_guess_ddc_bus(sdvo); |
2315 | } |
2316 | |
2317 | static void |
2318 | intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, |
2319 | struct intel_sdvo *sdvo, u32 reg) |
2320 | { |
2321 | struct sdvo_device_mapping *mapping; |
2322 | u8 pin; |
2323 | |
2324 | if (sdvo->is_sdvob) |
2325 | mapping = &dev_priv->sdvo_mappings[0]; |
2326 | else |
2327 | mapping = &dev_priv->sdvo_mappings[1]; |
2328 | |
2329 | if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin)) |
2330 | pin = mapping->i2c_pin; |
2331 | else |
2332 | pin = GMBUS_PORT_DPB; |
2333 | |
2334 | sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); |
2335 | |
2336 | /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow |
2337 | * our code totally fails once we start using gmbus. Hence fall back to |
2338 | * bit banging for now. */ |
2339 | intel_gmbus_force_bit(sdvo->i2c, true); |
2340 | } |
2341 | |
2342 | /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ |
2343 | static void |
2344 | intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) |
2345 | { |
2346 | intel_gmbus_force_bit(sdvo->i2c, false); |
2347 | } |
2348 | |
2349 | static bool |
2350 | intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) |
2351 | { |
2352 | return intel_sdvo_check_supp_encode(intel_sdvo); |
2353 | } |
2354 | |
2355 | static u8 |
2356 | intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) |
2357 | { |
2358 | struct drm_i915_private *dev_priv = dev->dev_private; |
2359 | struct sdvo_device_mapping *my_mapping, *other_mapping; |
2360 | |
2361 | if (sdvo->is_sdvob) { |
2362 | my_mapping = &dev_priv->sdvo_mappings[0]; |
2363 | other_mapping = &dev_priv->sdvo_mappings[1]; |
2364 | } else { |
2365 | my_mapping = &dev_priv->sdvo_mappings[1]; |
2366 | other_mapping = &dev_priv->sdvo_mappings[0]; |
2367 | } |
2368 | |
2369 | /* If the BIOS described our SDVO device, take advantage of it. */ |
2370 | if (my_mapping->slave_addr) |
2371 | return my_mapping->slave_addr; |
2372 | |
2373 | /* If the BIOS only described a different SDVO device, use the |
2374 | * address that it isn't using. |
2375 | */ |
2376 | if (other_mapping->slave_addr) { |
2377 | if (other_mapping->slave_addr == 0x70) |
2378 | return 0x72; |
2379 | else |
2380 | return 0x70; |
2381 | } |
2382 | |
2383 | /* No SDVO device info is found for another DVO port, |
2384 | * so use mapping assumption we had before BIOS parsing. |
2385 | */ |
2386 | if (sdvo->is_sdvob) |
2387 | return 0x70; |
2388 | else |
2389 | return 0x72; |
2390 | } |
2391 | |
2392 | static void |
2393 | intel_sdvo_connector_unregister(struct intel_connector *intel_connector) |
2394 | { |
2395 | #ifndef __NetBSD__ |
2396 | struct drm_connector *drm_connector; |
2397 | struct intel_sdvo *sdvo_encoder; |
2398 | |
2399 | drm_connector = &intel_connector->base; |
2400 | sdvo_encoder = intel_attached_sdvo(&intel_connector->base); |
2401 | |
2402 | sysfs_remove_link(&drm_connector->kdev->kobj, |
2403 | sdvo_encoder->ddc.dev.kobj.name); |
2404 | #endif |
2405 | intel_connector_unregister(intel_connector); |
2406 | } |
2407 | |
2408 | static int |
2409 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
2410 | struct intel_sdvo *encoder) |
2411 | { |
2412 | struct drm_connector *drm_connector; |
2413 | int ret; |
2414 | |
2415 | drm_connector = &connector->base.base; |
2416 | ret = drm_connector_init(encoder->base.base.dev, |
2417 | drm_connector, |
2418 | &intel_sdvo_connector_funcs, |
2419 | connector->base.base.connector_type); |
2420 | if (ret < 0) |
2421 | return ret; |
2422 | |
2423 | drm_connector_helper_add(drm_connector, |
2424 | &intel_sdvo_connector_helper_funcs); |
2425 | |
2426 | connector->base.base.interlace_allowed = 1; |
2427 | connector->base.base.doublescan_allowed = 0; |
2428 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; |
2429 | connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; |
2430 | connector->base.unregister = intel_sdvo_connector_unregister; |
2431 | |
2432 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
2433 | ret = drm_sysfs_connector_add(drm_connector); |
2434 | if (ret < 0) |
2435 | goto err1; |
2436 | |
2437 | #ifndef __NetBSD__ |
2438 | ret = sysfs_create_link(&drm_connector->kdev->kobj, |
2439 | &encoder->ddc.dev.kobj, |
2440 | encoder->ddc.dev.kobj.name); |
2441 | if (ret < 0) |
2442 | goto err2; |
2443 | #endif |
2444 | |
2445 | return 0; |
2446 | |
2447 | #ifndef __NetBSD__ |
2448 | err2: |
2449 | drm_sysfs_connector_remove(drm_connector); |
2450 | #endif |
2451 | err1: |
2452 | drm_connector_cleanup(drm_connector); |
2453 | |
2454 | return ret; |
2455 | } |
2456 | |
2457 | static void |
2458 | intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, |
2459 | struct intel_sdvo_connector *connector) |
2460 | { |
2461 | struct drm_device *dev = connector->base.base.dev; |
2462 | |
2463 | intel_attach_force_audio_property(&connector->base.base); |
2464 | if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { |
2465 | intel_attach_broadcast_rgb_property(&connector->base.base); |
2466 | intel_sdvo->color_range_auto = true; |
2467 | } |
2468 | } |
2469 | |
2470 | static bool |
2471 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
2472 | { |
2473 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2474 | struct drm_connector *connector; |
2475 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
2476 | struct intel_connector *intel_connector; |
2477 | struct intel_sdvo_connector *intel_sdvo_connector; |
2478 | |
2479 | DRM_DEBUG_KMS("initialising DVI device %d\n" , device); |
2480 | |
2481 | intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); |
2482 | if (!intel_sdvo_connector) |
2483 | return false; |
2484 | |
2485 | if (device == 0) { |
2486 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
2487 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
2488 | } else if (device == 1) { |
2489 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
2490 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
2491 | } |
2492 | |
2493 | intel_connector = &intel_sdvo_connector->base; |
2494 | connector = &intel_connector->base; |
2495 | if (intel_sdvo_get_hotplug_support(intel_sdvo) & |
2496 | intel_sdvo_connector->output_flag) { |
2497 | intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; |
2498 | /* Some SDVO devices have one-shot hotplug interrupts. |
2499 | * Ensure that they get re-enabled when an interrupt happens. |
2500 | */ |
2501 | intel_encoder->hot_plug = intel_sdvo_enable_hotplug; |
2502 | intel_sdvo_enable_hotplug(intel_encoder); |
2503 | } else { |
2504 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; |
2505 | } |
2506 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
2507 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; |
2508 | |
2509 | if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { |
2510 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
2511 | intel_sdvo->is_hdmi = true; |
2512 | } |
2513 | |
2514 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2515 | kfree(intel_sdvo_connector); |
2516 | return false; |
2517 | } |
2518 | |
2519 | if (intel_sdvo->is_hdmi) |
2520 | intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); |
2521 | |
2522 | return true; |
2523 | } |
2524 | |
2525 | static bool |
2526 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
2527 | { |
2528 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2529 | struct drm_connector *connector; |
2530 | struct intel_connector *intel_connector; |
2531 | struct intel_sdvo_connector *intel_sdvo_connector; |
2532 | |
2533 | DRM_DEBUG_KMS("initialising TV type %d\n" , type); |
2534 | |
2535 | intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); |
2536 | if (!intel_sdvo_connector) |
2537 | return false; |
2538 | |
2539 | intel_connector = &intel_sdvo_connector->base; |
2540 | connector = &intel_connector->base; |
2541 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; |
2542 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; |
2543 | |
2544 | intel_sdvo->controlled_output |= type; |
2545 | intel_sdvo_connector->output_flag = type; |
2546 | |
2547 | intel_sdvo->is_tv = true; |
2548 | |
2549 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2550 | kfree(intel_sdvo_connector); |
2551 | return false; |
2552 | } |
2553 | |
2554 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
2555 | goto err; |
2556 | |
2557 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
2558 | goto err; |
2559 | |
2560 | return true; |
2561 | |
2562 | err: |
2563 | drm_sysfs_connector_remove(connector); |
2564 | intel_sdvo_destroy(connector); |
2565 | return false; |
2566 | } |
2567 | |
2568 | static bool |
2569 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
2570 | { |
2571 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2572 | struct drm_connector *connector; |
2573 | struct intel_connector *intel_connector; |
2574 | struct intel_sdvo_connector *intel_sdvo_connector; |
2575 | |
2576 | DRM_DEBUG_KMS("initialising analog device %d\n" , device); |
2577 | |
2578 | intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); |
2579 | if (!intel_sdvo_connector) |
2580 | return false; |
2581 | |
2582 | intel_connector = &intel_sdvo_connector->base; |
2583 | connector = &intel_connector->base; |
2584 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
2585 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
2586 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; |
2587 | |
2588 | if (device == 0) { |
2589 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; |
2590 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; |
2591 | } else if (device == 1) { |
2592 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; |
2593 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; |
2594 | } |
2595 | |
2596 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2597 | kfree(intel_sdvo_connector); |
2598 | return false; |
2599 | } |
2600 | |
2601 | return true; |
2602 | } |
2603 | |
2604 | static bool |
2605 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
2606 | { |
2607 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2608 | struct drm_connector *connector; |
2609 | struct intel_connector *intel_connector; |
2610 | struct intel_sdvo_connector *intel_sdvo_connector; |
2611 | |
2612 | DRM_DEBUG_KMS("initialising LVDS device %d\n" , device); |
2613 | |
2614 | intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); |
2615 | if (!intel_sdvo_connector) |
2616 | return false; |
2617 | |
2618 | intel_connector = &intel_sdvo_connector->base; |
2619 | connector = &intel_connector->base; |
2620 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
2621 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; |
2622 | |
2623 | if (device == 0) { |
2624 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; |
2625 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; |
2626 | } else if (device == 1) { |
2627 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; |
2628 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; |
2629 | } |
2630 | |
2631 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2632 | kfree(intel_sdvo_connector); |
2633 | return false; |
2634 | } |
2635 | |
2636 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
2637 | goto err; |
2638 | |
2639 | return true; |
2640 | |
2641 | err: |
2642 | drm_sysfs_connector_remove(connector); |
2643 | intel_sdvo_destroy(connector); |
2644 | return false; |
2645 | } |
2646 | |
2647 | static bool |
2648 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
2649 | { |
2650 | intel_sdvo->is_tv = false; |
2651 | intel_sdvo->is_lvds = false; |
2652 | |
2653 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
2654 | |
2655 | if (flags & SDVO_OUTPUT_TMDS0) |
2656 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
2657 | return false; |
2658 | |
2659 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) |
2660 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
2661 | return false; |
2662 | |
2663 | /* TV has no XXX1 function block */ |
2664 | if (flags & SDVO_OUTPUT_SVID0) |
2665 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
2666 | return false; |
2667 | |
2668 | if (flags & SDVO_OUTPUT_CVBS0) |
2669 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
2670 | return false; |
2671 | |
2672 | if (flags & SDVO_OUTPUT_YPRPB0) |
2673 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) |
2674 | return false; |
2675 | |
2676 | if (flags & SDVO_OUTPUT_RGB0) |
2677 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
2678 | return false; |
2679 | |
2680 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) |
2681 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
2682 | return false; |
2683 | |
2684 | if (flags & SDVO_OUTPUT_LVDS0) |
2685 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
2686 | return false; |
2687 | |
2688 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) |
2689 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
2690 | return false; |
2691 | |
2692 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
2693 | unsigned char bytes[2]; |
2694 | |
2695 | intel_sdvo->controlled_output = 0; |
2696 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); |
2697 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n" , |
2698 | SDVO_NAME(intel_sdvo), |
2699 | bytes[0], bytes[1]); |
2700 | return false; |
2701 | } |
2702 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
2703 | |
2704 | return true; |
2705 | } |
2706 | |
2707 | static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) |
2708 | { |
2709 | struct drm_device *dev = intel_sdvo->base.base.dev; |
2710 | struct drm_connector *connector, *tmp; |
2711 | |
2712 | list_for_each_entry_safe(connector, tmp, |
2713 | &dev->mode_config.connector_list, head) { |
2714 | if (intel_attached_encoder(connector) == &intel_sdvo->base) { |
2715 | drm_sysfs_connector_remove(connector); |
2716 | intel_sdvo_destroy(connector); |
2717 | } |
2718 | } |
2719 | } |
2720 | |
2721 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
2722 | struct intel_sdvo_connector *intel_sdvo_connector, |
2723 | int type) |
2724 | { |
2725 | struct drm_device *dev = intel_sdvo->base.base.dev; |
2726 | struct intel_sdvo_tv_format format; |
2727 | uint32_t format_map, i; |
2728 | |
2729 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
2730 | return false; |
2731 | |
2732 | BUILD_BUG_ON(sizeof(format) != 6); |
2733 | if (!intel_sdvo_get_value(intel_sdvo, |
2734 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, |
2735 | &format, sizeof(format))) |
2736 | return false; |
2737 | |
2738 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
2739 | |
2740 | if (format_map == 0) |
2741 | return false; |
2742 | |
2743 | intel_sdvo_connector->format_supported_num = 0; |
2744 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
2745 | if (format_map & (1 << i)) |
2746 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; |
2747 | |
2748 | |
2749 | intel_sdvo_connector->tv_format = |
2750 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
2751 | "mode" , intel_sdvo_connector->format_supported_num); |
2752 | if (!intel_sdvo_connector->tv_format) |
2753 | return false; |
2754 | |
2755 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
2756 | drm_property_add_enum( |
2757 | intel_sdvo_connector->tv_format, i, |
2758 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
2759 | |
2760 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
2761 | drm_object_attach_property(&intel_sdvo_connector->base.base.base, |
2762 | intel_sdvo_connector->tv_format, 0); |
2763 | return true; |
2764 | |
2765 | } |
2766 | |
2767 | #define ENHANCEMENT(name, NAME) do { \ |
2768 | if (enhancements.name) { \ |
2769 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ |
2770 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ |
2771 | return false; \ |
2772 | intel_sdvo_connector->max_##name = data_value[0]; \ |
2773 | intel_sdvo_connector->cur_##name = response; \ |
2774 | intel_sdvo_connector->name = \ |
2775 | drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ |
2776 | if (!intel_sdvo_connector->name) return false; \ |
2777 | drm_object_attach_property(&connector->base, \ |
2778 | intel_sdvo_connector->name, \ |
2779 | intel_sdvo_connector->cur_##name); \ |
2780 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ |
2781 | data_value[0], data_value[1], response); \ |
2782 | } \ |
2783 | } while (0) |
2784 | |
2785 | static bool |
2786 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, |
2787 | struct intel_sdvo_connector *intel_sdvo_connector, |
2788 | struct intel_sdvo_enhancements_reply enhancements) |
2789 | { |
2790 | struct drm_device *dev = intel_sdvo->base.base.dev; |
2791 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
2792 | uint16_t response, data_value[2]; |
2793 | |
2794 | /* when horizontal overscan is supported, Add the left/right property */ |
2795 | if (enhancements.overscan_h) { |
2796 | if (!intel_sdvo_get_value(intel_sdvo, |
2797 | SDVO_CMD_GET_MAX_OVERSCAN_H, |
2798 | &data_value, 4)) |
2799 | return false; |
2800 | |
2801 | if (!intel_sdvo_get_value(intel_sdvo, |
2802 | SDVO_CMD_GET_OVERSCAN_H, |
2803 | &response, 2)) |
2804 | return false; |
2805 | |
2806 | intel_sdvo_connector->max_hscan = data_value[0]; |
2807 | intel_sdvo_connector->left_margin = data_value[0] - response; |
2808 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; |
2809 | intel_sdvo_connector->left = |
2810 | drm_property_create_range(dev, 0, "left_margin" , 0, data_value[0]); |
2811 | if (!intel_sdvo_connector->left) |
2812 | return false; |
2813 | |
2814 | drm_object_attach_property(&connector->base, |
2815 | intel_sdvo_connector->left, |
2816 | intel_sdvo_connector->left_margin); |
2817 | |
2818 | intel_sdvo_connector->right = |
2819 | drm_property_create_range(dev, 0, "right_margin" , 0, data_value[0]); |
2820 | if (!intel_sdvo_connector->right) |
2821 | return false; |
2822 | |
2823 | drm_object_attach_property(&connector->base, |
2824 | intel_sdvo_connector->right, |
2825 | intel_sdvo_connector->right_margin); |
2826 | DRM_DEBUG_KMS("h_overscan: max %d, " |
2827 | "default %d, current %d\n" , |
2828 | data_value[0], data_value[1], response); |
2829 | } |
2830 | |
2831 | if (enhancements.overscan_v) { |
2832 | if (!intel_sdvo_get_value(intel_sdvo, |
2833 | SDVO_CMD_GET_MAX_OVERSCAN_V, |
2834 | &data_value, 4)) |
2835 | return false; |
2836 | |
2837 | if (!intel_sdvo_get_value(intel_sdvo, |
2838 | SDVO_CMD_GET_OVERSCAN_V, |
2839 | &response, 2)) |
2840 | return false; |
2841 | |
2842 | intel_sdvo_connector->max_vscan = data_value[0]; |
2843 | intel_sdvo_connector->top_margin = data_value[0] - response; |
2844 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; |
2845 | intel_sdvo_connector->top = |
2846 | drm_property_create_range(dev, 0, |
2847 | "top_margin" , 0, data_value[0]); |
2848 | if (!intel_sdvo_connector->top) |
2849 | return false; |
2850 | |
2851 | drm_object_attach_property(&connector->base, |
2852 | intel_sdvo_connector->top, |
2853 | intel_sdvo_connector->top_margin); |
2854 | |
2855 | intel_sdvo_connector->bottom = |
2856 | drm_property_create_range(dev, 0, |
2857 | "bottom_margin" , 0, data_value[0]); |
2858 | if (!intel_sdvo_connector->bottom) |
2859 | return false; |
2860 | |
2861 | drm_object_attach_property(&connector->base, |
2862 | intel_sdvo_connector->bottom, |
2863 | intel_sdvo_connector->bottom_margin); |
2864 | DRM_DEBUG_KMS("v_overscan: max %d, " |
2865 | "default %d, current %d\n" , |
2866 | data_value[0], data_value[1], response); |
2867 | } |
2868 | |
2869 | ENHANCEMENT(hpos, HPOS); |
2870 | ENHANCEMENT(vpos, VPOS); |
2871 | ENHANCEMENT(saturation, SATURATION); |
2872 | ENHANCEMENT(contrast, CONTRAST); |
2873 | ENHANCEMENT(hue, HUE); |
2874 | ENHANCEMENT(sharpness, SHARPNESS); |
2875 | ENHANCEMENT(brightness, BRIGHTNESS); |
2876 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); |
2877 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); |
2878 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); |
2879 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); |
2880 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); |
2881 | |
2882 | if (enhancements.dot_crawl) { |
2883 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) |
2884 | return false; |
2885 | |
2886 | intel_sdvo_connector->max_dot_crawl = 1; |
2887 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; |
2888 | intel_sdvo_connector->dot_crawl = |
2889 | drm_property_create_range(dev, 0, "dot_crawl" , 0, 1); |
2890 | if (!intel_sdvo_connector->dot_crawl) |
2891 | return false; |
2892 | |
2893 | drm_object_attach_property(&connector->base, |
2894 | intel_sdvo_connector->dot_crawl, |
2895 | intel_sdvo_connector->cur_dot_crawl); |
2896 | DRM_DEBUG_KMS("dot crawl: current %d\n" , response); |
2897 | } |
2898 | |
2899 | return true; |
2900 | } |
2901 | |
2902 | static bool |
2903 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, |
2904 | struct intel_sdvo_connector *intel_sdvo_connector, |
2905 | struct intel_sdvo_enhancements_reply enhancements) |
2906 | { |
2907 | struct drm_device *dev = intel_sdvo->base.base.dev; |
2908 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
2909 | uint16_t response, data_value[2]; |
2910 | |
2911 | ENHANCEMENT(brightness, BRIGHTNESS); |
2912 | |
2913 | return true; |
2914 | } |
2915 | #undef ENHANCEMENT |
2916 | |
2917 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
2918 | struct intel_sdvo_connector *intel_sdvo_connector) |
2919 | { |
2920 | union { |
2921 | struct intel_sdvo_enhancements_reply reply; |
2922 | uint16_t response; |
2923 | } enhancements; |
2924 | |
2925 | BUILD_BUG_ON(sizeof(enhancements) != 2); |
2926 | |
2927 | enhancements.response = 0; |
2928 | intel_sdvo_get_value(intel_sdvo, |
2929 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, |
2930 | &enhancements, sizeof(enhancements)); |
2931 | if (enhancements.response == 0) { |
2932 | DRM_DEBUG_KMS("No enhancement is supported\n" ); |
2933 | return true; |
2934 | } |
2935 | |
2936 | if (IS_TV(intel_sdvo_connector)) |
2937 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
2938 | else if (IS_LVDS(intel_sdvo_connector)) |
2939 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
2940 | else |
2941 | return true; |
2942 | } |
2943 | |
2944 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, |
2945 | struct i2c_msg *msgs, |
2946 | int num) |
2947 | { |
2948 | struct intel_sdvo *sdvo = adapter->algo_data; |
2949 | |
2950 | if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
2951 | return -EIO; |
2952 | |
2953 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); |
2954 | } |
2955 | |
2956 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) |
2957 | { |
2958 | struct intel_sdvo *sdvo = adapter->algo_data; |
2959 | return sdvo->i2c->algo->functionality(sdvo->i2c); |
2960 | } |
2961 | |
2962 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { |
2963 | .master_xfer = intel_sdvo_ddc_proxy_xfer, |
2964 | .functionality = intel_sdvo_ddc_proxy_func |
2965 | }; |
2966 | |
2967 | static bool |
2968 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, |
2969 | struct drm_device *dev) |
2970 | { |
2971 | sdvo->ddc.owner = THIS_MODULE; |
2972 | sdvo->ddc.class = I2C_CLASS_DDC; |
2973 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy" ); |
2974 | sdvo->ddc.dev.parent = dev->dev; |
2975 | sdvo->ddc.algo_data = sdvo; |
2976 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; |
2977 | |
2978 | return i2c_add_adapter(&sdvo->ddc) == 0; |
2979 | } |
2980 | |
2981 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) |
2982 | { |
2983 | struct drm_i915_private *dev_priv = dev->dev_private; |
2984 | struct intel_encoder *intel_encoder; |
2985 | struct intel_sdvo *intel_sdvo; |
2986 | int i; |
2987 | intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); |
2988 | if (!intel_sdvo) |
2989 | return false; |
2990 | |
2991 | intel_sdvo->sdvo_reg = sdvo_reg; |
2992 | intel_sdvo->is_sdvob = is_sdvob; |
2993 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; |
2994 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); |
2995 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) |
2996 | goto err_i2c_bus; |
2997 | |
2998 | /* encoder type will be decided later */ |
2999 | intel_encoder = &intel_sdvo->base; |
3000 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
3001 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); |
3002 | |
3003 | /* Read the regs to test if we can talk to the device */ |
3004 | for (i = 0; i < 0x40; i++) { |
3005 | u8 byte; |
3006 | |
3007 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { |
3008 | DRM_DEBUG_KMS("No SDVO device found on %s\n" , |
3009 | SDVO_NAME(intel_sdvo)); |
3010 | goto err; |
3011 | } |
3012 | } |
3013 | |
3014 | intel_encoder->compute_config = intel_sdvo_compute_config; |
3015 | intel_encoder->disable = intel_disable_sdvo; |
3016 | intel_encoder->mode_set = intel_sdvo_mode_set; |
3017 | intel_encoder->enable = intel_enable_sdvo; |
3018 | intel_encoder->get_hw_state = intel_sdvo_get_hw_state; |
3019 | intel_encoder->get_config = intel_sdvo_get_config; |
3020 | |
3021 | /* In default case sdvo lvds is false */ |
3022 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
3023 | goto err; |
3024 | |
3025 | if (intel_sdvo_output_setup(intel_sdvo, |
3026 | intel_sdvo->caps.output_flags) != true) { |
3027 | DRM_DEBUG_KMS("SDVO output failed to setup on %s\n" , |
3028 | SDVO_NAME(intel_sdvo)); |
3029 | /* Output_setup can leave behind connectors! */ |
3030 | goto err_output; |
3031 | } |
3032 | |
3033 | /* Only enable the hotplug irq if we need it, to work around noisy |
3034 | * hotplug lines. |
3035 | */ |
3036 | if (intel_sdvo->hotplug_active) { |
3037 | intel_encoder->hpd_pin = |
3038 | intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C; |
3039 | } |
3040 | |
3041 | /* |
3042 | * Cloning SDVO with anything is often impossible, since the SDVO |
3043 | * encoder can request a special input timing mode. And even if that's |
3044 | * not the case we have evidence that cloning a plain unscaled mode with |
3045 | * VGA doesn't really work. Furthermore the cloning flags are way too |
3046 | * simplistic anyway to express such constraints, so just give up on |
3047 | * cloning for SDVO encoders. |
3048 | */ |
3049 | intel_sdvo->base.cloneable = 0; |
3050 | |
3051 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); |
3052 | |
3053 | /* Set the input timing to the screen. Assume always input 0. */ |
3054 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
3055 | goto err_output; |
3056 | |
3057 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
3058 | &intel_sdvo->pixel_clock_min, |
3059 | &intel_sdvo->pixel_clock_max)) |
3060 | goto err_output; |
3061 | |
3062 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
3063 | "clock range %dMHz - %dMHz, " |
3064 | "input 1: %c, input 2: %c, " |
3065 | "output 1: %c, output 2: %c\n" , |
3066 | SDVO_NAME(intel_sdvo), |
3067 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, |
3068 | intel_sdvo->caps.device_rev_id, |
3069 | intel_sdvo->pixel_clock_min / 1000, |
3070 | intel_sdvo->pixel_clock_max / 1000, |
3071 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', |
3072 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', |
3073 | /* check currently supported outputs */ |
3074 | intel_sdvo->caps.output_flags & |
3075 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
3076 | intel_sdvo->caps.output_flags & |
3077 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
3078 | return true; |
3079 | |
3080 | err_output: |
3081 | intel_sdvo_output_cleanup(intel_sdvo); |
3082 | |
3083 | err: |
3084 | drm_encoder_cleanup(&intel_encoder->base); |
3085 | i2c_del_adapter(&intel_sdvo->ddc); |
3086 | err_i2c_bus: |
3087 | intel_sdvo_unselect_i2c_bus(intel_sdvo); |
3088 | kfree(intel_sdvo); |
3089 | |
3090 | return false; |
3091 | } |
3092 | |