1/*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $Id: ah.h,v 1.4 2011/03/07 11:25:42 cegger Exp $
18 */
19
20#ifndef _ATH_AH_H_
21#define _ATH_AH_H_
22/*
23 * Atheros Hardware Access Layer
24 *
25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal
26 * structure for use with the device. Hardware-related operations that
27 * follow must call back into the HAL through interface, supplying the
28 * reference as the first parameter.
29 */
30
31#include "ah_osdep.h"
32
33/*
34 * __ahdecl is analogous to _cdecl; it defines the calling
35 * convention used within the HAL. For most systems this
36 * can just default to be empty and the compiler will (should)
37 * use _cdecl. For systems where _cdecl is not compatible this
38 * must be defined. See linux/ah_osdep.h for an example.
39 */
40#ifndef __ahdecl
41#define __ahdecl
42#endif
43
44/*
45 * Status codes that may be returned by the HAL. Note that
46 * interfaces that return a status code set it only when an
47 * error occurs--i.e. you cannot check it for success.
48 */
49typedef enum {
50 HAL_OK = 0, /* No error */
51 HAL_ENXIO = 1, /* No hardware present */
52 HAL_ENOMEM = 2, /* Memory allocation failed */
53 HAL_EIO = 3, /* Hardware didn't respond as expected */
54 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
55 HAL_EEVERSION = 5, /* EEPROM version invalid */
56 HAL_EELOCKED = 6, /* EEPROM unreadable */
57 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
58 HAL_EEREAD = 8, /* EEPROM read problem */
59 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
60 HAL_EESIZE = 10, /* EEPROM size not supported */
61 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
62 HAL_EINVAL = 12, /* Invalid parameter to function */
63 HAL_ENOTSUPP = 13, /* Hardware revision not supported */
64 HAL_ESELFTEST = 14, /* Hardware self-test failed */
65 HAL_EINPROGRESS = 15, /* Operation incomplete */
66 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */
67 HAL_EEBADCC = 17, /* EEPROM invalid country code */
68} HAL_STATUS;
69
70typedef enum {
71 AH_FALSE = 0, /* NB: lots of code assumes false is zero */
72 AH_TRUE = 1,
73} HAL_BOOL;
74
75typedef enum {
76 HAL_CAP_REG_DMN = 0, /* current regulatory domain */
77 HAL_CAP_CIPHER = 1, /* hardware supports cipher */
78 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */
79 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
80 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */
81 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */
82 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */
83 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */
84 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */
85 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */
86 HAL_CAP_DIAG = 11, /* hardware diagnostic support */
87 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */
88 HAL_CAP_BURST = 13, /* hardware supports packet bursting */
89 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */
90 HAL_CAP_TXPOW = 15, /* global tx power limit */
91 HAL_CAP_TPC = 16, /* per-packet tx power control */
92 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */
93 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */
94 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */
95 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */
96 /* 21 was HAL_CAP_XR */
97 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */
98 /* 23 was HAL_CAP_CHAN_HALFRATE */
99 /* 24 was HAL_CAP_CHAN_QUARTERRATE */
100 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */
101 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
102 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
103 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
104 HAL_CAP_INTMIT = 29, /* interference mitigation */
105 HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */
106 HAL_CAP_HT = 31, /* hardware can support HT */
107 HAL_CAP_TX_CHAINMASK = 32, /* mask of TX chains supported */
108 HAL_CAP_RX_CHAINMASK = 33, /* mask of RX chains supported */
109 HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */
110 HAL_CAP_BB_HANG = 35, /* can baseband hang */
111 HAL_CAP_MAC_HANG = 36, /* can MAC hang */
112 HAL_CAP_INTRMASK = 37, /* bitmask of supported interupts */
113 HAL_CAP_BSSIDMATCH = 38, /* hardware has disable bssid match */
114} HAL_CAPABILITY_TYPE;
115
116/*
117 * "States" for setting the LED. These correspond to
118 * the possible 802.11 operational states and there may
119 * be a many-to-one mapping between these states and the
120 * actual hardware state for the LED's (i.e. the hardware
121 * may have fewer states).
122 */
123typedef enum {
124 HAL_LED_INIT = 0,
125 HAL_LED_SCAN = 1,
126 HAL_LED_AUTH = 2,
127 HAL_LED_ASSOC = 3,
128 HAL_LED_RUN = 4
129} HAL_LED_STATE;
130
131/*
132 * Transmit queue types/numbers. These are used to tag
133 * each transmit queue in the hardware and to identify a set
134 * of transmit queues for operations such as start/stop dma.
135 */
136typedef enum {
137 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */
138 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */
139 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */
140 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */
141 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */
142} HAL_TX_QUEUE;
143
144#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
145
146/*
147 * Transmit queue subtype. These map directly to
148 * WME Access Categories (except for UPSD). Refer
149 * to Table 5 of the WME spec.
150 */
151typedef enum {
152 HAL_WME_AC_BK = 0, /* background access category */
153 HAL_WME_AC_BE = 1, /* best effort access category*/
154 HAL_WME_AC_VI = 2, /* video access category */
155 HAL_WME_AC_VO = 3, /* voice access category */
156 HAL_WME_UPSD = 4, /* uplink power save */
157} HAL_TX_QUEUE_SUBTYPE;
158
159/*
160 * Transmit queue flags that control various
161 * operational parameters.
162 */
163typedef enum {
164 /*
165 * Per queue interrupt enables. When set the associated
166 * interrupt may be delivered for packets sent through
167 * the queue. Without these enabled no interrupts will
168 * be delivered for transmits through the queue.
169 */
170 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */
171 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */
172 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */
173 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */
174 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */
175 /*
176 * Enable hardware compression for packets sent through
177 * the queue. The compression buffer must be setup and
178 * packets must have a key entry marked in the tx descriptor.
179 */
180 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */
181 /*
182 * Disable queue when veol is hit or ready time expires.
183 * By default the queue is disabled only on reaching the
184 * physical end of queue (i.e. a null link ptr in the
185 * descriptor chain).
186 */
187 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
188 /*
189 * Schedule frames on delivery of a DBA (DMA Beacon Alert)
190 * event. Frames will be transmitted only when this timer
191 * fires, e.g to transmit a beacon in ap or adhoc modes.
192 */
193 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */
194 /*
195 * Each transmit queue has a counter that is incremented
196 * each time the queue is enabled and decremented when
197 * the list of frames to transmit is traversed (or when
198 * the ready time for the queue expires). This counter
199 * must be non-zero for frames to be scheduled for
200 * transmission. The following controls disable bumping
201 * this counter under certain conditions. Typically this
202 * is used to gate frames based on the contents of another
203 * queue (e.g. CAB traffic may only follow a beacon frame).
204 * These are meaningful only when frames are scheduled
205 * with a non-ASAP policy (e.g. DBA-gated).
206 */
207 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */
208 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */
209
210 /*
211 * Fragment burst backoff policy. Normally the no backoff
212 * is done after a successful transmission, the next fragment
213 * is sent at SIFS. If this flag is set backoff is done
214 * after each fragment, regardless whether it was ack'd or
215 * not, after the backoff count reaches zero a normal channel
216 * access procedure is done before the next transmit (i.e.
217 * wait AIFS instead of SIFS).
218 */
219 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
220 /*
221 * Disable post-tx backoff following each frame.
222 */
223 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */
224 /*
225 * DCU arbiter lockout control. This controls how
226 * lower priority tx queues are handled with respect to
227 * to a specific queue when multiple queues have frames
228 * to send. No lockout means lower priority queues arbitrate
229 * concurrently with this queue. Intra-frame lockout
230 * means lower priority queues are locked out until the
231 * current frame transmits (e.g. including backoffs and bursting).
232 * Global lockout means nothing lower can arbitrary so
233 * long as there is traffic activity on this queue (frames,
234 * backoff, etc).
235 */
236 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */
237 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */
238
239 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */
240 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */
241} HAL_TX_QUEUE_FLAGS;
242
243typedef struct {
244 uint32_t tqi_ver; /* hal TXQ version */
245 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */
246 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */
247 uint32_t tqi_priority; /* (not used) */
248 uint32_t tqi_aifs; /* aifs */
249 uint32_t tqi_cwmin; /* cwMin */
250 uint32_t tqi_cwmax; /* cwMax */
251 uint16_t tqi_shretry; /* rts retry limit */
252 uint16_t tqi_lgretry; /* long retry limit (not used)*/
253 uint32_t tqi_cbrPeriod; /* CBR period (us) */
254 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */
255 uint32_t tqi_burstTime; /* max burst duration (us) */
256 uint32_t tqi_readyTime; /* frame schedule time (us) */
257 uint32_t tqi_compBuf; /* comp buffer phys addr */
258} HAL_TXQ_INFO;
259
260#define HAL_TQI_NONVAL 0xffff
261
262/* token to use for aifs, cwmin, cwmax */
263#define HAL_TXQ_USEDEFAULT ((uint32_t) -1)
264
265/* compression definitions */
266#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */
267#define HAL_COMP_BUF_ALIGN_SIZE 512
268
269/*
270 * Transmit packet types. This belongs in ah_desc.h, but
271 * is here so we can give a proper type to various parameters
272 * (and not require everyone include the file).
273 *
274 * NB: These values are intentionally assigned for
275 * direct use when setting up h/w descriptors.
276 */
277typedef enum {
278 HAL_PKT_TYPE_NORMAL = 0,
279 HAL_PKT_TYPE_ATIM = 1,
280 HAL_PKT_TYPE_PSPOLL = 2,
281 HAL_PKT_TYPE_BEACON = 3,
282 HAL_PKT_TYPE_PROBE_RESP = 4,
283 HAL_PKT_TYPE_CHIRP = 5,
284 HAL_PKT_TYPE_GRP_POLL = 6,
285 HAL_PKT_TYPE_AMPDU = 7,
286} HAL_PKT_TYPE;
287
288/* Rx Filter Frame Types */
289typedef enum {
290 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
291 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
292 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
293 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
294 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
295 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
296 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
297 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
298 HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors */
299 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */
300 HAL_RX_FILTER_BSSID = 0x00000800, /* Disable BSSID match */
301} HAL_RX_FILTER;
302
303typedef enum {
304 HAL_PM_AWAKE = 0,
305 HAL_PM_FULL_SLEEP = 1,
306 HAL_PM_NETWORK_SLEEP = 2,
307 HAL_PM_UNDEFINED = 3
308} HAL_POWER_MODE;
309
310/*
311 * NOTE WELL:
312 * These are mapped to take advantage of the common locations for many of
313 * the bits on all of the currently supported MAC chips. This is to make
314 * the ISR as efficient as possible, while still abstracting HW differences.
315 * When new hardware breaks this commonality this enumerated type, as well
316 * as the HAL functions using it, must be modified. All values are directly
317 * mapped unless commented otherwise.
318 */
319typedef enum {
320 HAL_INT_RX = 0x00000001, /* Non-common mapping */
321 HAL_INT_RXDESC = 0x00000002,
322 HAL_INT_RXNOFRM = 0x00000008,
323 HAL_INT_RXEOL = 0x00000010,
324 HAL_INT_RXORN = 0x00000020,
325 HAL_INT_TX = 0x00000040, /* Non-common mapping */
326 HAL_INT_TXDESC = 0x00000080,
327 HAL_INT_TIM_TIMER=0x00000100,
328 HAL_INT_TXURN = 0x00000800,
329 HAL_INT_MIB = 0x00001000,
330 HAL_INT_RXPHY = 0x00004000,
331 HAL_INT_RXKCM = 0x00008000,
332 HAL_INT_SWBA = 0x00010000,
333 HAL_INT_BMISS = 0x00040000,
334 HAL_INT_BNR = 0x00100000,
335 HAL_INT_TIM = 0x00200000, /* Non-common mapping */
336 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */
337 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */
338 HAL_INT_GPIO = 0x01000000,
339 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
340 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
341 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
342 HAL_INT_CST = 0x10000000, /* Non-common mapping */
343 HAL_INT_GTT = 0x20000000, /* Non-common mapping */
344 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
345#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */
346 HAL_INT_BMISC = HAL_INT_TIM
347 | HAL_INT_DTIM
348 | HAL_INT_DTIMSYNC
349 | HAL_INT_CABEND
350 | HAL_INT_TBTT,
351
352 /* Interrupt bits that map directly to ISR/IMR bits */
353 HAL_INT_COMMON = HAL_INT_RXNOFRM
354 | HAL_INT_RXDESC
355 | HAL_INT_RXEOL
356 | HAL_INT_RXORN
357 | HAL_INT_TXURN
358 | HAL_INT_TXDESC
359 | HAL_INT_MIB
360 | HAL_INT_RXPHY
361 | HAL_INT_RXKCM
362 | HAL_INT_SWBA
363 | HAL_INT_BMISS
364 | HAL_INT_BNR
365 | HAL_INT_GPIO,
366} HAL_INT;
367
368typedef enum {
369 HAL_GPIO_MUX_OUTPUT = 0,
370 HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1,
371 HAL_GPIO_MUX_PCIE_POWER_LED = 2,
372 HAL_GPIO_MUX_TX_FRAME = 3,
373 HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4,
374 HAL_GPIO_MUX_MAC_NETWORK_LED = 5,
375 HAL_GPIO_MUX_MAC_POWER_LED = 6
376} HAL_GPIO_MUX_TYPE;
377
378typedef enum {
379 HAL_GPIO_INTR_LOW = 0,
380 HAL_GPIO_INTR_HIGH = 1,
381 HAL_GPIO_INTR_DISABLE = 2
382} HAL_GPIO_INTR_TYPE;
383
384typedef enum {
385 HAL_RFGAIN_INACTIVE = 0,
386 HAL_RFGAIN_READ_REQUESTED = 1,
387 HAL_RFGAIN_NEED_CHANGE = 2
388} HAL_RFGAIN;
389
390/*
391 * Channels are specified by frequency.
392 */
393typedef struct {
394 uint32_t channelFlags; /* see below */
395 uint16_t channel; /* setting in Mhz */
396 uint8_t privFlags;
397 int8_t maxRegTxPower; /* max regulatory tx power in dBm */
398 int8_t maxTxPower; /* max true tx power in 0.5 dBm */
399 int8_t minTxPower; /* min true tx power in 0.5 dBm */
400} HAL_CHANNEL;
401
402/* channelFlags */
403#define CHANNEL_CW_INT 0x00002 /* CW interference detected on channel */
404#define CHANNEL_TURBO 0x00010 /* Turbo Channel */
405#define CHANNEL_CCK 0x00020 /* CCK channel */
406#define CHANNEL_OFDM 0x00040 /* OFDM channel */
407#define CHANNEL_2GHZ 0x00080 /* 2 GHz spectrum channel */
408#define CHANNEL_5GHZ 0x00100 /* 5 GHz spectrum channel */
409#define CHANNEL_PASSIVE 0x00200 /* Only passive scan allowed in the channel */
410#define CHANNEL_DYN 0x00400 /* dynamic CCK-OFDM channel */
411#define CHANNEL_STURBO 0x02000 /* Static turbo, no 11a-only usage */
412#define CHANNEL_HALF 0x04000 /* Half rate channel */
413#define CHANNEL_QUARTER 0x08000 /* Quarter rate channel */
414#define CHANNEL_HT20 0x10000 /* 11n 20MHZ channel */
415#define CHANNEL_HT40PLUS 0x20000 /* 11n 40MHZ channel w/ ext chan above */
416#define CHANNEL_HT40MINUS 0x40000 /* 11n 40MHZ channel w/ ext chan below */
417
418/* privFlags */
419#define CHANNEL_INTERFERENCE 0x01 /* Software use: channel interference
420 used for as AR as well as RADAR
421 interference detection */
422#define CHANNEL_DFS 0x02 /* DFS required on channel */
423#define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */
424#define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked for DFS */
425
426#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
427#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
428#define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM)
429#ifdef notdef
430#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_DYN)
431#else
432#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
433#endif
434#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
435#define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO)
436#define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
437#define CHANNEL_108A CHANNEL_T
438#define CHANNEL_G_HT20 (CHANNEL_G|CHANNEL_HT20)
439#define CHANNEL_A_HT20 (CHANNEL_A|CHANNEL_HT20)
440#define CHANNEL_G_HT40PLUS (CHANNEL_G|CHANNEL_HT40PLUS)
441#define CHANNEL_G_HT40MINUS (CHANNEL_G|CHANNEL_HT40MINUS)
442#define CHANNEL_A_HT40PLUS (CHANNEL_A|CHANNEL_HT40PLUS)
443#define CHANNEL_A_HT40MINUS (CHANNEL_A|CHANNEL_HT40MINUS)
444#define CHANNEL_ALL \
445 (CHANNEL_OFDM | CHANNEL_CCK| CHANNEL_2GHZ | CHANNEL_5GHZ | \
446 CHANNEL_TURBO | CHANNEL_HT20 | CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)
447#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO)
448
449#define HAL_ANTENNA_MIN_MODE 0
450#define HAL_ANTENNA_FIXED_A 1
451#define HAL_ANTENNA_FIXED_B 2
452#define HAL_ANTENNA_MAX_MODE 3
453
454typedef struct {
455 uint32_t ackrcv_bad;
456 uint32_t rts_bad;
457 uint32_t rts_good;
458 uint32_t fcs_bad;
459 uint32_t beacons;
460} HAL_MIB_STATS;
461
462typedef uint16_t HAL_CTRY_CODE; /* country code */
463typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */
464
465enum {
466 CTRY_DEBUG = 0x1ff, /* debug country code */
467 CTRY_DEFAULT = 0 /* default country code */
468};
469
470enum {
471 HAL_MODE_11A = 0x001, /* 11a channels */
472 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
473 HAL_MODE_11B = 0x004, /* 11b channels */
474 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
475#ifdef notdef
476 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */
477#else
478 HAL_MODE_11G = 0x008, /* XXX historical */
479#endif
480 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */
481 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */
482 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */
483 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */
484 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */
485 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */
486 HAL_MODE_11NG_HT20 = 0x008000,
487 HAL_MODE_11NA_HT20 = 0x010000,
488 HAL_MODE_11NG_HT40PLUS = 0x020000,
489 HAL_MODE_11NG_HT40MINUS = 0x040000,
490 HAL_MODE_11NA_HT40PLUS = 0x080000,
491 HAL_MODE_11NA_HT40MINUS = 0x100000,
492 HAL_MODE_ALL = 0xffffff
493};
494
495typedef struct {
496 int rateCount; /* NB: for proper padding */
497 uint8_t rateCodeToIndex[144]; /* back mapping */
498 struct {
499 uint8_t valid; /* valid for rate control use */
500 uint8_t phy; /* CCK/OFDM/XR */
501 uint32_t rateKbps; /* transfer rate in kbs */
502 uint8_t rateCode; /* rate for h/w descriptors */
503 uint8_t shortPreamble; /* mask for enabling short
504 * preamble in CCK rate code */
505 uint8_t dot11Rate; /* value for supported rates
506 * info element of MLME */
507 uint8_t controlRate; /* index of next lower basic
508 * rate; used for dur. calcs */
509 uint16_t lpAckDuration; /* long preamble ACK duration */
510 uint16_t spAckDuration; /* short preamble ACK duration*/
511 } info[32];
512} HAL_RATE_TABLE;
513
514typedef struct {
515 u_int rs_count; /* number of valid entries */
516 uint8_t rs_rates[32]; /* rates */
517} HAL_RATE_SET;
518
519/*
520 * 802.11n specific structures and enums
521 */
522typedef enum {
523 HAL_CHAINTYPE_TX = 1, /* Tx chain type */
524 HAL_CHAINTYPE_RX = 2, /* RX chain type */
525} HAL_CHAIN_TYPE;
526
527typedef struct {
528 u_int Tries;
529 u_int Rate;
530 u_int PktDuration;
531 u_int ChSel;
532 u_int RateFlags;
533#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
534#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
535#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
536} HAL_11N_RATE_SERIES;
537
538typedef enum {
539 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */
540 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */
541} HAL_HT_MACMODE;
542
543typedef enum {
544 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */
545 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */
546} HAL_HT_PHYMODE;
547
548typedef enum {
549 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */
550 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */
551} HAL_HT_EXTPROTSPACING;
552
553
554typedef enum {
555 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */
556 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
557} HAL_HT_RXCLEAR;
558
559/*
560 * Antenna switch control. By default antenna selection
561 * enables multiple (2) antenna use. To force use of the
562 * A or B antenna only specify a fixed setting. Fixing
563 * the antenna will also disable any diversity support.
564 */
565typedef enum {
566 HAL_ANT_VARIABLE = 0, /* variable by programming */
567 HAL_ANT_FIXED_A = 1, /* fixed antenna A */
568 HAL_ANT_FIXED_B = 2, /* fixed antenna B */
569} HAL_ANT_SETTING;
570
571typedef enum {
572 HAL_M_STA = 1, /* infrastructure station */
573 HAL_M_IBSS = 0, /* IBSS (adhoc) station */
574 HAL_M_HOSTAP = 6, /* Software Access Point */
575 HAL_M_MONITOR = 8 /* Monitor mode */
576} HAL_OPMODE;
577
578typedef struct {
579 uint8_t kv_type; /* one of HAL_CIPHER */
580 uint8_t kv_pad;
581 uint16_t kv_len; /* length in bits */
582 uint8_t kv_val[16]; /* enough for 128-bit keys */
583 uint8_t kv_mic[8]; /* TKIP MIC key */
584 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */
585} HAL_KEYVAL;
586
587typedef enum {
588 HAL_CIPHER_WEP = 0,
589 HAL_CIPHER_AES_OCB = 1,
590 HAL_CIPHER_AES_CCM = 2,
591 HAL_CIPHER_CKIP = 3,
592 HAL_CIPHER_TKIP = 4,
593 HAL_CIPHER_CLR = 5, /* no encryption */
594
595 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */
596} HAL_CIPHER;
597
598enum {
599 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */
600 HAL_SLOT_TIME_9 = 9,
601 HAL_SLOT_TIME_20 = 20,
602};
603
604/*
605 * Per-station beacon timer state. Note that the specified
606 * beacon interval (given in TU's) can also include flags
607 * to force a TSF reset and to enable the beacon xmit logic.
608 * If bs_cfpmaxduration is non-zero the hardware is setup to
609 * coexist with a PCF-capable AP.
610 */
611typedef struct {
612 uint32_t bs_nexttbtt; /* next beacon in TU */
613 uint32_t bs_nextdtim; /* next DTIM in TU */
614 uint32_t bs_intval; /* beacon interval+flags */
615#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
616#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
617#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
618 uint32_t bs_dtimperiod;
619 uint16_t bs_cfpperiod; /* CFP period in TU */
620 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */
621 uint32_t bs_cfpnext; /* next CFP in TU */
622 uint16_t bs_timoffset; /* byte offset to TIM bitmap */
623 uint16_t bs_bmissthreshold; /* beacon miss threshold */
624 uint32_t bs_sleepduration; /* max sleep duration */
625} HAL_BEACON_STATE;
626
627/*
628 * Like HAL_BEACON_STATE but for non-station mode setup.
629 * NB: see above flag definitions for bt_intval.
630 */
631typedef struct {
632 uint32_t bt_intval; /* beacon interval+flags */
633 uint32_t bt_nexttbtt; /* next beacon in TU */
634 uint32_t bt_nextatim; /* next ATIM in TU */
635 uint32_t bt_nextdba; /* next DBA in 1/8th TU */
636 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */
637 uint32_t bt_flags; /* timer enables */
638#define HAL_BEACON_TBTT_EN 0x00000001
639#define HAL_BEACON_DBA_EN 0x00000002
640#define HAL_BEACON_SWBA_EN 0x00000004
641} HAL_BEACON_TIMERS;
642
643/*
644 * Per-node statistics maintained by the driver for use in
645 * optimizing signal quality and other operational aspects.
646 */
647typedef struct {
648 uint32_t ns_avgbrssi; /* average beacon rssi */
649 uint32_t ns_avgrssi; /* average data rssi */
650 uint32_t ns_avgtxrssi; /* average tx rssi */
651} HAL_NODE_STATS;
652
653#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
654
655struct ath_desc;
656struct ath_tx_status;
657struct ath_rx_status;
658
659/*
660 * Hardware Access Layer (HAL) API.
661 *
662 * Clients of the HAL call ath_hal_attach to obtain a reference to an
663 * ath_hal structure for use with the device. Hardware-related operations
664 * that follow must call back into the HAL through interface, supplying
665 * the reference as the first parameter. Note that before using the
666 * reference returned by ath_hal_attach the caller should verify the
667 * ABI version number.
668 */
669struct ath_hal {
670 uint32_t ah_magic; /* consistency check magic number */
671 uint32_t ah_abi; /* HAL ABI version */
672#define HAL_ABI_VERSION 0x08112800 /* YYMMDDnn */
673 uint16_t ah_devid; /* PCI device ID */
674 uint16_t ah_subvendorid; /* PCI subvendor ID */
675 HAL_SOFTC ah_sc; /* back pointer to driver/os state */
676 HAL_BUS_TAG ah_st; /* params for register r+w */
677 HAL_BUS_HANDLE ah_sh;
678 HAL_CTRY_CODE ah_countryCode;
679
680 uint32_t ah_macVersion; /* MAC version id */
681 uint16_t ah_macRev; /* MAC revision */
682 uint16_t ah_phyRev; /* PHY revision */
683 /* NB: when only one radio is present the rev is in 5Ghz */
684 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */
685 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */
686
687 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
688 u_int mode);
689 void __ahdecl(*ah_detach)(struct ath_hal*);
690
691 /* Reset functions */
692 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
693 HAL_CHANNEL *, HAL_BOOL bChannelChange,
694 HAL_STATUS *status);
695 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *);
696 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *);
697 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore);
698 void __ahdecl(*ah_disablePCIE)(struct ath_hal *);
699 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
700 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *,
701 HAL_BOOL *);
702 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, HAL_CHANNEL *,
703 u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
704 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, HAL_CHANNEL *);
705 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *,
706 HAL_CHANNEL *, uint16_t *);
707 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t);
708 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *,
709 HAL_CHANNEL *);
710
711 /* Transmit functions */
712 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
713 HAL_BOOL incTrigLevel);
714 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
715 const HAL_TXQ_INFO *qInfo);
716 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q,
717 const HAL_TXQ_INFO *qInfo);
718 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q,
719 HAL_TXQ_INFO *qInfo);
720 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
721 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
722 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int);
723 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp);
724 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q);
725 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int);
726 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int);
727 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
728 u_int pktLen, u_int hdrLen,
729 HAL_PKT_TYPE type, u_int txPower,
730 u_int txRate0, u_int txTries0,
731 u_int keyIx, u_int antMode, u_int flags,
732 u_int rtsctsRate, u_int rtsctsDuration,
733 u_int compicvLen, u_int compivLen,
734 u_int comp);
735 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*,
736 u_int txRate1, u_int txTries1,
737 u_int txRate2, u_int txTries2,
738 u_int txRate3, u_int txTries3);
739 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
740 u_int segLen, HAL_BOOL firstSeg,
741 HAL_BOOL lastSeg, const struct ath_desc *);
742 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *,
743 struct ath_desc *, struct ath_tx_status *);
744 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *);
745 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
746
747 /* Receive Functions */
748 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
749 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp);
750 void __ahdecl(*ah_enableReceive)(struct ath_hal*);
751 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
752 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
753 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
754 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
755 uint32_t filter0, uint32_t filter1);
756 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*,
757 uint32_t index);
758 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*,
759 uint32_t index);
760 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*);
761 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t);
762 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
763 uint32_t size, u_int flags);
764 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *,
765 struct ath_desc *, uint32_t phyAddr,
766 struct ath_desc *next, uint64_t tsf,
767 struct ath_rx_status *);
768 void __ahdecl(*ah_rxMonitor)(struct ath_hal *,
769 const HAL_NODE_STATS *, HAL_CHANNEL *);
770 void __ahdecl(*ah_procMibEvent)(struct ath_hal *,
771 const HAL_NODE_STATS *);
772
773 /* Misc Functions */
774 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
775 HAL_CAPABILITY_TYPE, uint32_t capability,
776 uint32_t *result);
777 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *,
778 HAL_CAPABILITY_TYPE, uint32_t capability,
779 uint32_t setting, HAL_STATUS *);
780 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request,
781 const void *args, uint32_t argsize,
782 void **result, uint32_t *resultsize);
783 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *);
784 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*);
785 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *);
786 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*);
787 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*,
788 uint16_t, HAL_STATUS *);
789 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
790 void __ahdecl(*ah_writeAssocid)(struct ath_hal*,
791 const uint8_t *bssid, uint16_t assocId);
792 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *,
793 uint32_t gpio, HAL_GPIO_MUX_TYPE);
794 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
795 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
796 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *,
797 uint32_t gpio, uint32_t val);
798 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
799 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
800 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
801 void __ahdecl(*ah_resetTsf)(struct ath_hal*);
802 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
803 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*,
804 HAL_MIB_STATS*);
805 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*);
806 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*);
807 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int);
808 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*);
809 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*,
810 HAL_ANT_SETTING);
811 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int);
812 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*);
813 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int);
814 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*);
815 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int);
816 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*);
817 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int);
818 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*);
819 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int);
820 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*);
821 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int);
822 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int);
823
824 /* Key Cache Functions */
825 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
826 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t);
827 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *,
828 uint16_t);
829 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*,
830 uint16_t, const HAL_KEYVAL *,
831 const uint8_t *, int);
832 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*,
833 uint16_t, const uint8_t *);
834
835 /* Power Management Functions */
836 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*,
837 HAL_POWER_MODE mode, int setChip);
838 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*);
839 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *);
840
841 /* Beacon Management Functions */
842 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*,
843 const HAL_BEACON_TIMERS *);
844 /* NB: deprecated, use ah_setBeaconTimers instead */
845 void __ahdecl(*ah_beaconInit)(struct ath_hal *,
846 uint32_t nexttbtt, uint32_t intval);
847 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*,
848 const HAL_BEACON_STATE *);
849 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*);
850
851 /* Interrupt functions */
852 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
853 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
854 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
855 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
856};
857
858/*
859 * Check the PCI vendor ID and device ID against Atheros' values
860 * and return a printable description for any Atheros hardware.
861 * AH_NULL is returned if the ID's do not describe Atheros hardware.
862 */
863extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid);
864
865/*
866 * Attach the HAL for use with the specified device. The device is
867 * defined by the PCI device ID. The caller provides an opaque pointer
868 * to an upper-layer data structure (HAL_SOFTC) that is stored in the
869 * HAL state block for later use. Hardware register accesses are done
870 * using the specified bus tag and handle. On successful return a
871 * reference to a state block is returned that must be supplied in all
872 * subsequent HAL calls. Storage associated with this reference is
873 * dynamically allocated and must be freed by calling the ah_detach
874 * method when the client is done. If the attach operation fails a
875 * null (AH_NULL) reference will be returned and a status code will
876 * be returned if the status parameter is non-zero.
877 */
878extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC,
879 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS* status);
880
881/*
882 * Return a list of channels available for use with the hardware.
883 * The list is based on what the hardware is capable of, the specified
884 * country code, the modeSelect mask, and whether or not outdoor
885 * channels are to be permitted.
886 *
887 * The channel list is returned in the supplied array. maxchans
888 * defines the maximum size of this array. nchans contains the actual
889 * number of channels returned. If a problem occurred or there were
890 * no channels that met the criteria then AH_FALSE is returned.
891 */
892extern HAL_BOOL __ahdecl ath_hal_init_channels(struct ath_hal *,
893 HAL_CHANNEL *chans, u_int maxchans, u_int *nchans,
894 uint8_t *regclassids, u_int maxregids, u_int *nregids,
895 HAL_CTRY_CODE cc, u_int modeSelect,
896 HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels);
897
898/*
899 * Calibrate noise floor data following a channel scan or similar.
900 * This must be called prior retrieving noise floor data.
901 */
902extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);
903
904/*
905 * Return bit mask of wireless modes supported by the hardware.
906 */
907extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*, HAL_CTRY_CODE);
908
909/*
910 * Calculate the transmit duration of a frame.
911 */
912extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
913 const HAL_RATE_TABLE *rates, uint32_t frameLen,
914 uint16_t rateix, HAL_BOOL shortPreamble);
915
916/*
917 * Return if device is public safety.
918 */
919extern HAL_BOOL __ahdecl ath_hal_ispublicsafetysku(struct ath_hal *);
920
921/*
922 * Return if device is operating in 900 MHz band.
923 */
924extern HAL_BOOL ath_hal_isgsmsku(struct ath_hal *);
925
926/*
927 * Convert between IEEE channel number and channel frequency
928 * using the specified channel flags; e.g. CHANNEL_2GHZ.
929 */
930extern int __ahdecl ath_hal_mhz2ieee(struct ath_hal *, u_int mhz, u_int flags);
931#endif /* _ATH_AH_H_ */
932