1/* $NetBSD: ahcisata_core.c,v 1.57 2016/06/03 10:34:03 jmcneill Exp $ */
2
3/*
4 * Copyright (c) 2006 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 */
27
28#include <sys/cdefs.h>
29__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.57 2016/06/03 10:34:03 jmcneill Exp $");
30
31#include <sys/types.h>
32#include <sys/malloc.h>
33#include <sys/param.h>
34#include <sys/kernel.h>
35#include <sys/systm.h>
36#include <sys/disklabel.h>
37#include <sys/proc.h>
38#include <sys/buf.h>
39
40#include <dev/ata/atareg.h>
41#include <dev/ata/satavar.h>
42#include <dev/ata/satareg.h>
43#include <dev/ata/satafisvar.h>
44#include <dev/ata/satafisreg.h>
45#include <dev/ata/satapmpreg.h>
46#include <dev/ic/ahcisatavar.h>
47#include <dev/ic/wdcreg.h>
48
49#include <dev/scsipi/scsi_all.h> /* for SCSI status */
50
51#include "atapibus.h"
52
53#ifdef AHCI_DEBUG
54int ahcidebug_mask = 0;
55#endif
56
57static void ahci_probe_drive(struct ata_channel *);
58static void ahci_setup_channel(struct ata_channel *);
59
60static int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *);
61static int ahci_do_reset_drive(struct ata_channel *, int, int, uint32_t *);
62static void ahci_reset_drive(struct ata_drive_datas *, int, uint32_t *);
63static void ahci_reset_channel(struct ata_channel *, int);
64static int ahci_exec_command(struct ata_drive_datas *, struct ata_command *);
65static int ahci_ata_addref(struct ata_drive_datas *);
66static void ahci_ata_delref(struct ata_drive_datas *);
67static void ahci_killpending(struct ata_drive_datas *);
68
69static void ahci_cmd_start(struct ata_channel *, struct ata_xfer *);
70static int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int);
71static void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int);
72static void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ;
73static void ahci_bio_start(struct ata_channel *, struct ata_xfer *);
74static int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int);
75static void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ;
76static void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int);
77static void ahci_channel_start(struct ahci_softc *, struct ata_channel *,
78 int, int);
79static void ahci_timeout(void *);
80static int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int);
81
82#if NATAPIBUS > 0
83static void ahci_atapibus_attach(struct atabus_softc *);
84static void ahci_atapi_kill_pending(struct scsipi_periph *);
85static void ahci_atapi_minphys(struct buf *);
86static void ahci_atapi_scsipi_request(struct scsipi_channel *,
87 scsipi_adapter_req_t, void *);
88static void ahci_atapi_start(struct ata_channel *, struct ata_xfer *);
89static int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int);
90static void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int);
91static void ahci_atapi_probe_device(struct atapibus_softc *, int);
92
93static const struct scsipi_bustype ahci_atapi_bustype = {
94 SCSIPI_BUSTYPE_ATAPI,
95 atapi_scsipi_cmd,
96 atapi_interpret_sense,
97 atapi_print_addr,
98 ahci_atapi_kill_pending,
99 NULL,
100};
101#endif /* NATAPIBUS */
102
103#define ATA_DELAY 10000 /* 10s for a drive I/O */
104#define ATA_RESET_DELAY 31000 /* 31s for a drive reset */
105#define AHCI_RST_WAIT (ATA_RESET_DELAY / 10)
106
107const struct ata_bustype ahci_ata_bustype = {
108 SCSIPI_BUSTYPE_ATA,
109 ahci_ata_bio,
110 ahci_reset_drive,
111 ahci_reset_channel,
112 ahci_exec_command,
113 ata_get_params,
114 ahci_ata_addref,
115 ahci_ata_delref,
116 ahci_killpending
117};
118
119static void ahci_intr_port(struct ahci_softc *, struct ahci_channel *);
120static void ahci_setup_port(struct ahci_softc *sc, int i);
121
122static void
123ahci_enable(struct ahci_softc *sc)
124{
125 uint32_t ghc;
126
127 ghc = AHCI_READ(sc, AHCI_GHC);
128 if (!(ghc & AHCI_GHC_AE)) {
129 ghc |= AHCI_GHC_AE;
130 AHCI_WRITE(sc, AHCI_GHC, ghc);
131 }
132}
133
134static int
135ahci_reset(struct ahci_softc *sc)
136{
137 int i;
138
139 /* reset controller */
140 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR);
141 /* wait up to 1s for reset to complete */
142 for (i = 0; i < 1000; i++) {
143 delay(1000);
144 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0)
145 break;
146 }
147 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) {
148 aprint_error("%s: reset failed\n", AHCINAME(sc));
149 return -1;
150 }
151 /* enable ahci mode */
152 ahci_enable(sc);
153
154 if (sc->sc_save_init_data) {
155 AHCI_WRITE(sc, AHCI_CAP, sc->sc_init_data.cap);
156 if (sc->sc_init_data.cap2)
157 AHCI_WRITE(sc, AHCI_CAP2, sc->sc_init_data.cap2);
158 AHCI_WRITE(sc, AHCI_PI, sc->sc_init_data.ports);
159 }
160
161 return 0;
162}
163
164static void
165ahci_setup_ports(struct ahci_softc *sc)
166{
167 int i, port;
168
169 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
170 if ((sc->sc_ahci_ports & (1 << i)) == 0)
171 continue;
172 if (port >= sc->sc_atac.atac_nchannels) {
173 aprint_error("%s: more ports than announced\n",
174 AHCINAME(sc));
175 break;
176 }
177 ahci_setup_port(sc, i);
178 }
179}
180
181static void
182ahci_reprobe_drives(struct ahci_softc *sc)
183{
184 int i, port;
185 struct ahci_channel *achp;
186 struct ata_channel *chp;
187
188 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
189 if ((sc->sc_ahci_ports & (1 << i)) == 0)
190 continue;
191 if (port >= sc->sc_atac.atac_nchannels) {
192 aprint_error("%s: more ports than announced\n",
193 AHCINAME(sc));
194 break;
195 }
196 achp = &sc->sc_channels[i];
197 chp = &achp->ata_channel;
198
199 ahci_probe_drive(chp);
200 }
201}
202
203static void
204ahci_setup_port(struct ahci_softc *sc, int i)
205{
206 struct ahci_channel *achp;
207
208 achp = &sc->sc_channels[i];
209
210 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh);
211 AHCI_WRITE(sc, AHCI_P_CLBU(i), (uint64_t)achp->ahcic_bus_cmdh>>32);
212 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis);
213 AHCI_WRITE(sc, AHCI_P_FBU(i), (uint64_t)achp->ahcic_bus_rfis>>32);
214}
215
216static void
217ahci_enable_intrs(struct ahci_softc *sc)
218{
219
220 /* clear interrupts */
221 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS));
222 /* enable interrupts */
223 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
224}
225
226void
227ahci_attach(struct ahci_softc *sc)
228{
229 uint32_t ahci_rev;
230 int i, j, port;
231 struct ahci_channel *achp;
232 struct ata_channel *chp;
233 int error;
234 int dmasize;
235 char buf[128];
236 void *cmdhp;
237 void *cmdtblp;
238
239 if (sc->sc_save_init_data) {
240 ahci_enable(sc);
241
242 sc->sc_init_data.cap = AHCI_READ(sc, AHCI_CAP);
243 sc->sc_init_data.ports = AHCI_READ(sc, AHCI_PI);
244
245 ahci_rev = AHCI_READ(sc, AHCI_VS);
246 if (AHCI_VS_MJR(ahci_rev) > 1 ||
247 (AHCI_VS_MJR(ahci_rev) == 1 && AHCI_VS_MNR(ahci_rev) >= 20)) {
248 sc->sc_init_data.cap2 = AHCI_READ(sc, AHCI_CAP2);
249 } else {
250 sc->sc_init_data.cap2 = 0;
251 }
252 if (sc->sc_init_data.ports == 0) {
253 sc->sc_init_data.ports = sc->sc_ahci_ports;
254 }
255 }
256
257 if (ahci_reset(sc) != 0)
258 return;
259
260 sc->sc_ahci_cap = AHCI_READ(sc, AHCI_CAP);
261 if (sc->sc_ahci_quirks & AHCI_QUIRK_BADPMP) {
262 aprint_verbose_dev(sc->sc_atac.atac_dev,
263 "ignoring broken port multiplier support\n");
264 sc->sc_ahci_cap &= ~AHCI_CAP_SPM;
265 }
266 sc->sc_atac.atac_nchannels = (sc->sc_ahci_cap & AHCI_CAP_NPMASK) + 1;
267 sc->sc_ncmds = ((sc->sc_ahci_cap & AHCI_CAP_NCS) >> 8) + 1;
268 ahci_rev = AHCI_READ(sc, AHCI_VS);
269 snprintb(buf, sizeof(buf), "\177\020"
270 /* "f\000\005NP\0" */
271 "b\005SXS\0"
272 "b\006EMS\0"
273 "b\007CCCS\0"
274 /* "f\010\005NCS\0" */
275 "b\015PSC\0"
276 "b\016SSC\0"
277 "b\017PMD\0"
278 "b\020FBSS\0"
279 "b\021SPM\0"
280 "b\022SAM\0"
281 "b\023SNZO\0"
282 "f\024\003ISS\0"
283 "=\001Gen1\0"
284 "=\002Gen2\0"
285 "=\003Gen3\0"
286 "b\030SCLO\0"
287 "b\031SAL\0"
288 "b\032SALP\0"
289 "b\033SSS\0"
290 "b\034SMPS\0"
291 "b\035SSNTF\0"
292 "b\036SNCQ\0"
293 "b\037S64A\0"
294 "\0", sc->sc_ahci_cap);
295 aprint_normal_dev(sc->sc_atac.atac_dev, "AHCI revision %u.%u"
296 ", %d port%s, %d slot%s, CAP %s\n",
297 AHCI_VS_MJR(ahci_rev), AHCI_VS_MNR(ahci_rev),
298 sc->sc_atac.atac_nchannels,
299 (sc->sc_atac.atac_nchannels == 1 ? "" : "s"),
300 sc->sc_ncmds, (sc->sc_ncmds == 1 ? "" : "s"), buf);
301
302 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA;
303 sc->sc_atac.atac_cap |= sc->sc_atac_capflags;
304 sc->sc_atac.atac_pio_cap = 4;
305 sc->sc_atac.atac_dma_cap = 2;
306 sc->sc_atac.atac_udma_cap = 6;
307 sc->sc_atac.atac_channels = sc->sc_chanarray;
308 sc->sc_atac.atac_probe = ahci_probe_drive;
309 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype;
310 sc->sc_atac.atac_set_modes = ahci_setup_channel;
311#if NATAPIBUS > 0
312 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach;
313#endif
314
315 dmasize =
316 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels;
317 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0,
318 &sc->sc_cmd_hdr_seg, 1, &sc->sc_cmd_hdr_nseg, BUS_DMA_NOWAIT);
319 if (error) {
320 aprint_error("%s: unable to allocate command header memory"
321 ", error=%d\n", AHCINAME(sc), error);
322 return;
323 }
324 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmd_hdr_seg,
325 sc->sc_cmd_hdr_nseg, dmasize,
326 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
327 if (error) {
328 aprint_error("%s: unable to map command header memory"
329 ", error=%d\n", AHCINAME(sc), error);
330 return;
331 }
332 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0,
333 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd);
334 if (error) {
335 aprint_error("%s: unable to create command header map"
336 ", error=%d\n", AHCINAME(sc), error);
337 return;
338 }
339 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd,
340 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT);
341 if (error) {
342 aprint_error("%s: unable to load command header map"
343 ", error=%d\n", AHCINAME(sc), error);
344 return;
345 }
346 sc->sc_cmd_hdr = cmdhp;
347
348 ahci_enable_intrs(sc);
349
350 if (sc->sc_ahci_ports == 0) {
351 sc->sc_ahci_ports = AHCI_READ(sc, AHCI_PI);
352 AHCIDEBUG_PRINT(("active ports %#x\n", sc->sc_ahci_ports),
353 DEBUG_PROBE);
354 }
355 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
356 if ((sc->sc_ahci_ports & (1 << i)) == 0)
357 continue;
358 if (port >= sc->sc_atac.atac_nchannels) {
359 aprint_error("%s: more ports than announced\n",
360 AHCINAME(sc));
361 break;
362 }
363 achp = &sc->sc_channels[i];
364 chp = &achp->ata_channel;
365 sc->sc_chanarray[i] = chp;
366 chp->ch_channel = i;
367 chp->ch_atac = &sc->sc_atac;
368 chp->ch_queue = malloc(sizeof(struct ata_queue),
369 M_DEVBUF, M_NOWAIT|M_ZERO);
370 if (chp->ch_queue == NULL) {
371 aprint_error("%s port %d: can't allocate memory for "
372 "command queue", AHCINAME(sc), i);
373 break;
374 }
375 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds;
376 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0,
377 &achp->ahcic_cmd_tbl_seg, 1, &achp->ahcic_cmd_tbl_nseg,
378 BUS_DMA_NOWAIT);
379 if (error) {
380 aprint_error("%s: unable to allocate command table "
381 "memory, error=%d\n", AHCINAME(sc), error);
382 break;
383 }
384 error = bus_dmamem_map(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg,
385 achp->ahcic_cmd_tbl_nseg, dmasize,
386 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
387 if (error) {
388 aprint_error("%s: unable to map command table memory"
389 ", error=%d\n", AHCINAME(sc), error);
390 break;
391 }
392 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0,
393 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld);
394 if (error) {
395 aprint_error("%s: unable to create command table map"
396 ", error=%d\n", AHCINAME(sc), error);
397 break;
398 }
399 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld,
400 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT);
401 if (error) {
402 aprint_error("%s: unable to load command table map"
403 ", error=%d\n", AHCINAME(sc), error);
404 break;
405 }
406 achp->ahcic_cmdh = (struct ahci_cmd_header *)
407 ((char *)cmdhp + AHCI_CMDH_SIZE * port);
408 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr +
409 AHCI_CMDH_SIZE * port;
410 achp->ahcic_rfis = (struct ahci_r_fis *)
411 ((char *)cmdhp +
412 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
413 AHCI_RFIS_SIZE * port);
414 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr +
415 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
416 AHCI_RFIS_SIZE * port;
417 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%" PRIx64 ") "
418 "rfis %p (0x%" PRIx64 ")\n", i,
419 achp->ahcic_cmdh, (uint64_t)achp->ahcic_bus_cmdh,
420 achp->ahcic_rfis, (uint64_t)achp->ahcic_bus_rfis),
421 DEBUG_PROBE);
422
423 for (j = 0; j < sc->sc_ncmds; j++) {
424 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *)
425 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j);
426 achp->ahcic_bus_cmd_tbl[j] =
427 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr +
428 AHCI_CMDTBL_SIZE * j;
429 achp->ahcic_cmdh[j].cmdh_cmdtba =
430 htole64(achp->ahcic_bus_cmd_tbl[j]);
431 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%" PRIx64 ")\n", i, j,
432 achp->ahcic_cmd_tbl[j],
433 (uint64_t)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE);
434 /* The xfer DMA map */
435 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS,
436 AHCI_NPRD, 0x400000 /* 4MB */, 0,
437 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
438 &achp->ahcic_datad[j]);
439 if (error) {
440 aprint_error("%s: couldn't alloc xfer DMA map, "
441 "error=%d\n", AHCINAME(sc), error);
442 goto end;
443 }
444 }
445 ahci_setup_port(sc, i);
446 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
447 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) {
448 aprint_error("%s: couldn't map channel %d "
449 "sata_status regs\n", AHCINAME(sc), i);
450 break;
451 }
452 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
453 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) {
454 aprint_error("%s: couldn't map channel %d "
455 "sata_control regs\n", AHCINAME(sc), i);
456 break;
457 }
458 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
459 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) {
460 aprint_error("%s: couldn't map channel %d "
461 "sata_error regs\n", AHCINAME(sc), i);
462 break;
463 }
464 ata_channel_attach(chp);
465 port++;
466end:
467 continue;
468 }
469}
470
471int
472ahci_detach(struct ahci_softc *sc, int flags)
473{
474 struct atac_softc *atac;
475 struct ahci_channel *achp;
476 struct ata_channel *chp;
477 struct scsipi_adapter *adapt;
478 int i, j;
479 int error;
480
481 atac = &sc->sc_atac;
482 adapt = &atac->atac_atapi_adapter._generic;
483
484 for (i = 0; i < AHCI_MAX_PORTS; i++) {
485 achp = &sc->sc_channels[i];
486 chp = &achp->ata_channel;
487
488 if ((sc->sc_ahci_ports & (1 << i)) == 0)
489 continue;
490 if (i >= sc->sc_atac.atac_nchannels) {
491 aprint_error("%s: more ports than announced\n",
492 AHCINAME(sc));
493 break;
494 }
495
496 if (chp->atabus == NULL)
497 continue;
498 if ((error = config_detach(chp->atabus, flags)) != 0)
499 return error;
500
501 for (j = 0; j < sc->sc_ncmds; j++)
502 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_datad[j]);
503
504 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_cmd_tbld);
505 bus_dmamap_destroy(sc->sc_dmat, achp->ahcic_cmd_tbld);
506 bus_dmamem_unmap(sc->sc_dmat, achp->ahcic_cmd_tbl[0],
507 AHCI_CMDTBL_SIZE * sc->sc_ncmds);
508 bus_dmamem_free(sc->sc_dmat, &achp->ahcic_cmd_tbl_seg,
509 achp->ahcic_cmd_tbl_nseg);
510
511 free(chp->ch_queue, M_DEVBUF);
512 chp->atabus = NULL;
513 }
514
515 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmd_hdrd);
516 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_hdrd);
517 bus_dmamem_unmap(sc->sc_dmat, sc->sc_cmd_hdr,
518 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels);
519 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmd_hdr_seg, sc->sc_cmd_hdr_nseg);
520
521 if (adapt->adapt_refcnt != 0)
522 return EBUSY;
523
524 return 0;
525}
526
527void
528ahci_resume(struct ahci_softc *sc)
529{
530 ahci_reset(sc);
531 ahci_setup_ports(sc);
532 ahci_reprobe_drives(sc);
533 ahci_enable_intrs(sc);
534}
535
536int
537ahci_intr(void *v)
538{
539 struct ahci_softc *sc = v;
540 uint32_t is;
541 int i, r = 0;
542
543 while ((is = AHCI_READ(sc, AHCI_IS))) {
544 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is),
545 DEBUG_INTR);
546 r = 1;
547 AHCI_WRITE(sc, AHCI_IS, is);
548 for (i = 0; i < AHCI_MAX_PORTS; i++)
549 if (is & (1 << i))
550 ahci_intr_port(sc, &sc->sc_channels[i]);
551 }
552 return r;
553}
554
555static void
556ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp)
557{
558 uint32_t is, tfd;
559 struct ata_channel *chp = &achp->ata_channel;
560 struct ata_xfer *xfer = chp->ch_queue->active_xfer;
561 int slot;
562
563 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
564 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is);
565 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc),
566 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
567 DEBUG_INTR);
568
569 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS |
570 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) {
571 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))
572 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT;
573 if ((achp->ahcic_cmds_active & (1 << slot)) == 0)
574 return;
575 /* stop channel */
576 ahci_channel_stop(sc, chp, 0);
577 if (slot != 0) {
578 printf("ahci_intr_port: slot %d\n", slot);
579 panic("ahci_intr_port");
580 }
581 if (is & AHCI_P_IX_TFES) {
582 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
583 chp->ch_error =
584 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT;
585 chp->ch_status = (tfd & 0xff);
586 } else {
587 /* emulate a CRC error */
588 chp->ch_error = WDCE_CRC;
589 chp->ch_status = WDCS_ERR;
590 }
591 if (is & AHCI_P_IX_IFS) {
592 aprint_error("%s port %d: SERR 0x%x\n",
593 AHCINAME(sc), chp->ch_channel,
594 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel)));
595 }
596 xfer->c_intr(chp, xfer, is);
597 /* if channel has not been restarted, do it now */
598 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR)
599 == 0)
600 ahci_channel_start(sc, chp, 0, 0);
601 } else {
602 slot = 0; /* XXX */
603 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
604 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n",
605 chp->ch_channel, is, achp->ahcic_cmds_active,
606 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR);
607 if ((achp->ahcic_cmds_active & (1 << slot)) == 0)
608 return;
609 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot))
610 == 0) {
611 xfer->c_intr(chp, xfer, 0);
612 }
613 }
614}
615
616static void
617ahci_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp)
618{
619 struct ata_channel *chp = drvp->chnl_softc;
620 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
621 AHCI_WRITE(sc, AHCI_GHC,
622 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
623 ahci_channel_stop(sc, chp, flags);
624 if (ahci_do_reset_drive(chp, drvp->drive, flags, sigp) != 0)
625 ata_reset_channel(chp, flags);
626 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
627 return;
628}
629
630/* return error code from ata_bio */
631static int
632ahci_exec_fis(struct ata_channel *chp, int timeout, int flags)
633{
634 struct ahci_channel *achp = (struct ahci_channel *)chp;
635 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
636 int i;
637 uint32_t is;
638
639 /*
640 * Base timeout is specified in ms.
641 * If we are allowed to sleep, wait a tick each round.
642 * Otherwise delay for 10ms on each round.
643 */
644 if (flags & AT_WAIT)
645 timeout = MAX(1, mstohz(timeout));
646 else
647 timeout = timeout / 10;
648
649 AHCI_CMDH_SYNC(sc, achp, 0, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
650 /* start command */
651 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << 0);
652 for (i = 0; i < timeout; i++) {
653 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & 1 << 0) == 0)
654 return 0;
655 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
656 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS |
657 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) {
658 if ((is & (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) ==
659 (AHCI_P_IX_DHRS|AHCI_P_IX_TFES)) {
660 /*
661 * we got the D2H FIS anyway,
662 * assume sig is valid.
663 * channel is restarted later
664 */
665 return ERROR;
666 }
667 aprint_debug("%s channel %d: error 0x%x sending FIS\n",
668 AHCINAME(sc), chp->ch_channel, is);
669 return ERR_DF;
670 }
671 if (flags & AT_WAIT)
672 tsleep(&sc, PRIBIO, "ahcifis", 1);
673 else
674 delay(10000);
675 }
676
677 aprint_debug("%s channel %d: timeout sending FIS\n",
678 AHCINAME(sc), chp->ch_channel);
679 return TIMEOUT;
680}
681
682static int
683ahci_do_reset_drive(struct ata_channel *chp, int drive, int flags,
684 uint32_t *sigp)
685{
686 struct ahci_channel *achp = (struct ahci_channel *)chp;
687 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
688 struct ahci_cmd_tbl *cmd_tbl;
689 struct ahci_cmd_header *cmd_h;
690 int i;
691 uint32_t sig;
692
693 KASSERT((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) == 0);
694again:
695 /* clear port interrupt register */
696 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
697 /* clear SErrors and start operations */
698 if ((sc->sc_ahci_cap & AHCI_CAP_CLO) == AHCI_CAP_CLO) {
699 /*
700 * issue a command list override to clear BSY.
701 * This is needed if there's a PMP with no drive
702 * on port 0
703 */
704 ahci_channel_start(sc, chp, flags, 1);
705 } else {
706 ahci_channel_start(sc, chp, flags, 0);
707 }
708 if (drive > 0) {
709 KASSERT(sc->sc_ahci_cap & AHCI_CAP_SPM);
710 }
711
712 if (sc->sc_ahci_quirks & AHCI_QUIRK_SKIP_RESET)
713 goto skip_reset;
714
715 /* polled command, assume interrupts are disabled */
716 /* use slot 0 to send reset, the channel is idle */
717 cmd_h = &achp->ahcic_cmdh[0];
718 cmd_tbl = achp->ahcic_cmd_tbl[0];
719 cmd_h->cmdh_flags = htole16(AHCI_CMDH_F_RST | AHCI_CMDH_F_CBSY |
720 RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT));
721 cmd_h->cmdh_prdbc = 0;
722 memset(cmd_tbl->cmdt_cfis, 0, 64);
723 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE;
724 cmd_tbl->cmdt_cfis[rhd_c] = drive;
725 cmd_tbl->cmdt_cfis[rhd_control] = WDCTL_RST;
726 switch(ahci_exec_fis(chp, 100, flags)) {
727 case ERR_DF:
728 case TIMEOUT:
729 aprint_error("%s channel %d: setting WDCTL_RST failed "
730 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive);
731 if (sigp)
732 *sigp = 0xffffffff;
733 goto end;
734 default:
735 break;
736 }
737 cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 |
738 (drive << AHCI_CMDH_F_PMP_SHIFT));
739 cmd_h->cmdh_prdbc = 0;
740 memset(cmd_tbl->cmdt_cfis, 0, 64);
741 cmd_tbl->cmdt_cfis[fis_type] = RHD_FISTYPE;
742 cmd_tbl->cmdt_cfis[rhd_c] = drive;
743 cmd_tbl->cmdt_cfis[rhd_control] = 0;
744 switch(ahci_exec_fis(chp, 310, flags)) {
745 case ERR_DF:
746 case TIMEOUT:
747 if ((sc->sc_ahci_quirks & AHCI_QUIRK_BADPMPRESET) != 0 &&
748 drive == PMP_PORT_CTL) {
749 /*
750 * some controllers fails to reset when
751 * targeting a PMP but a single drive is attached.
752 * try again with port 0
753 */
754 drive = 0;
755 ahci_channel_stop(sc, chp, flags);
756 goto again;
757 }
758 aprint_error("%s channel %d: clearing WDCTL_RST failed "
759 "for drive %d\n", AHCINAME(sc), chp->ch_channel, drive);
760 if (sigp)
761 *sigp = 0xffffffff;
762 goto end;
763 default:
764 break;
765 }
766
767skip_reset:
768 /*
769 * wait 31s for BSY to clear
770 * This should not be needed, but some controllers clear the
771 * command slot before receiving the D2H FIS ...
772 */
773 for (i = 0; i < AHCI_RST_WAIT; i++) {
774 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
775 if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0)
776 break;
777 if (flags & AT_WAIT)
778 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10));
779 else
780 delay(10000);
781 }
782 if (i == AHCI_RST_WAIT) {
783 aprint_error("%s: BSY never cleared, TD 0x%x\n",
784 AHCINAME(sc), sig);
785 if (sigp)
786 *sigp = 0xffffffff;
787 goto end;
788 }
789 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10),
790 DEBUG_PROBE);
791 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel));
792 if (sigp)
793 *sigp = sig;
794 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n",
795 AHCINAME(sc), chp->ch_channel, sig,
796 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE);
797end:
798 ahci_channel_stop(sc, chp, flags);
799 if (flags & AT_WAIT)
800 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500));
801 else
802 delay(500000);
803 /* clear port interrupt register */
804 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
805 ahci_channel_start(sc, chp, flags,
806 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0);
807 return 0;
808}
809
810static void
811ahci_reset_channel(struct ata_channel *chp, int flags)
812{
813 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
814 struct ahci_channel *achp = (struct ahci_channel *)chp;
815 int i, tfd;
816
817 ahci_channel_stop(sc, chp, flags);
818 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
819 achp->ahcic_sstatus, flags) != SStatus_DET_DEV) {
820 printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel);
821 /* XXX and then ? */
822 }
823 if (chp->ch_queue->active_xfer) {
824 chp->ch_queue->active_xfer->c_kill_xfer(chp,
825 chp->ch_queue->active_xfer, KILL_RESET);
826 }
827 ata_delay(500, "ahcirst", flags);
828 /* clear port interrupt register */
829 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
830 /* clear SErrors and start operations */
831 ahci_channel_start(sc, chp, flags,
832 (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0);
833 /* wait 31s for BSY to clear */
834 for (i = 0; i <AHCI_RST_WAIT; i++) {
835 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
836 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT)
837 & WDCS_BSY) == 0)
838 break;
839 ata_delay(10, "ahcid2h", flags);
840 }
841 if (i == AHCI_RST_WAIT)
842 aprint_error("%s: BSY never cleared, TD 0x%x\n",
843 AHCINAME(sc), tfd);
844 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10),
845 DEBUG_PROBE);
846 /* clear port interrupt register */
847 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
848
849 return;
850}
851
852static int
853ahci_ata_addref(struct ata_drive_datas *drvp)
854{
855 return 0;
856}
857
858static void
859ahci_ata_delref(struct ata_drive_datas *drvp)
860{
861 return;
862}
863
864static void
865ahci_killpending(struct ata_drive_datas *drvp)
866{
867 return;
868}
869
870static void
871ahci_probe_drive(struct ata_channel *chp)
872{
873 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
874 struct ahci_channel *achp = (struct ahci_channel *)chp;
875 uint32_t sig;
876
877 /* bring interface up, accept FISs, power up and spin up device */
878 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
879 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE |
880 AHCI_P_CMD_POD | AHCI_P_CMD_SUD);
881 /* reset the PHY and bring online */
882 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
883 achp->ahcic_sstatus, AT_WAIT)) {
884 case SStatus_DET_DEV:
885 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500));
886 if (sc->sc_ahci_cap & AHCI_CAP_SPM) {
887 ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT, &sig);
888 } else {
889 ahci_do_reset_drive(chp, 0, AT_WAIT, &sig);
890 }
891 sata_interpret_sig(chp, 0, sig);
892 /* if we have a PMP attached, inform the controller */
893 if (chp->ch_ndrives > PMP_PORT_CTL &&
894 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) {
895 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
896 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) |
897 AHCI_P_CMD_PMA);
898 }
899 /* clear port interrupt register */
900 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
901
902 /* and enable interrupts */
903 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel),
904 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS |
905 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS |
906 AHCI_P_IX_PSS | AHCI_P_IX_DHRS);
907 /* wait 500ms before actually starting operations */
908 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500));
909 break;
910
911 default:
912 break;
913 }
914}
915
916static void
917ahci_setup_channel(struct ata_channel *chp)
918{
919 return;
920}
921
922static int
923ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c)
924{
925 struct ata_channel *chp = drvp->chnl_softc;
926 struct ata_xfer *xfer;
927 int ret;
928 int s;
929
930 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
931 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n",
932 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
933 DEBUG_XFERS);
934 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP :
935 ATAXF_NOSLEEP);
936 if (xfer == NULL) {
937 return ATACMD_TRY_AGAIN;
938 }
939 if (ata_c->flags & AT_POLL)
940 xfer->c_flags |= C_POLL;
941 if (ata_c->flags & AT_WAIT)
942 xfer->c_flags |= C_WAIT;
943 xfer->c_drive = drvp->drive;
944 xfer->c_databuf = ata_c->data;
945 xfer->c_bcount = ata_c->bcount;
946 xfer->c_cmd = ata_c;
947 xfer->c_start = ahci_cmd_start;
948 xfer->c_intr = ahci_cmd_complete;
949 xfer->c_kill_xfer = ahci_cmd_kill_xfer;
950 s = splbio();
951 ata_exec_xfer(chp, xfer);
952#ifdef DIAGNOSTIC
953 if ((ata_c->flags & AT_POLL) != 0 &&
954 (ata_c->flags & AT_DONE) == 0)
955 panic("ahci_exec_command: polled command not done");
956#endif
957 if (ata_c->flags & AT_DONE) {
958 ret = ATACMD_COMPLETE;
959 } else {
960 if (ata_c->flags & AT_WAIT) {
961 while ((ata_c->flags & AT_DONE) == 0) {
962 tsleep(ata_c, PRIBIO, "ahcicmd", 0);
963 }
964 ret = ATACMD_COMPLETE;
965 } else {
966 ret = ATACMD_QUEUED;
967 }
968 }
969 splx(s);
970 return ret;
971}
972
973static void
974ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer)
975{
976 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
977 struct ahci_channel *achp = (struct ahci_channel *)chp;
978 struct ata_command *ata_c = xfer->c_cmd;
979 int slot = 0 /* XXX slot */;
980 struct ahci_cmd_tbl *cmd_tbl;
981 struct ahci_cmd_header *cmd_h;
982 int i;
983 int channel = chp->ch_channel;
984
985 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x timo %d\n",
986 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)), ata_c->timeout),
987 DEBUG_XFERS);
988
989 cmd_tbl = achp->ahcic_cmd_tbl[slot];
990 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
991 cmd_tbl), DEBUG_XFERS);
992
993 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis);
994 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive;
995
996 cmd_h = &achp->ahcic_cmdh[slot];
997 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
998 chp->ch_channel, cmd_h), DEBUG_XFERS);
999 if (ahci_dma_setup(chp, slot,
1000 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ?
1001 ata_c->data : NULL,
1002 ata_c->bcount,
1003 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) {
1004 ata_c->flags |= AT_DF;
1005 ahci_cmd_complete(chp, xfer, slot);
1006 return;
1007 }
1008 cmd_h->cmdh_flags = htole16(
1009 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) |
1010 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT));
1011 cmd_h->cmdh_prdbc = 0;
1012 AHCI_CMDH_SYNC(sc, achp, slot,
1013 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1014
1015 if (ata_c->flags & AT_POLL) {
1016 /* polled command, disable interrupts */
1017 AHCI_WRITE(sc, AHCI_GHC,
1018 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
1019 }
1020 chp->ch_flags |= ATACH_IRQ_WAIT;
1021 chp->ch_status = 0;
1022 /* start command */
1023 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
1024 /* and says we started this command */
1025 achp->ahcic_cmds_active |= 1 << slot;
1026
1027 if ((ata_c->flags & AT_POLL) == 0) {
1028 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
1029 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout),
1030 ahci_timeout, chp);
1031 return;
1032 }
1033 /*
1034 * Polled command.
1035 */
1036 for (i = 0; i < ata_c->timeout / 10; i++) {
1037 if (ata_c->flags & AT_DONE)
1038 break;
1039 ahci_intr_port(sc, achp);
1040 if (ata_c->flags & AT_WAIT)
1041 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10));
1042 else
1043 delay(10000);
1044 }
1045 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
1046 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
1047 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
1048 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
1049 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
1050 DEBUG_XFERS);
1051 if ((ata_c->flags & AT_DONE) == 0) {
1052 ata_c->flags |= AT_TIMEOU;
1053 ahci_cmd_complete(chp, xfer, slot);
1054 }
1055 /* reenable interrupts */
1056 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
1057}
1058
1059static void
1060ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
1061{
1062 struct ata_command *ata_c = xfer->c_cmd;
1063 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel),
1064 DEBUG_FUNCS);
1065
1066 switch (reason) {
1067 case KILL_GONE:
1068 ata_c->flags |= AT_GONE;
1069 break;
1070 case KILL_RESET:
1071 ata_c->flags |= AT_RESET;
1072 break;
1073 default:
1074 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason);
1075 panic("ahci_cmd_kill_xfer");
1076 }
1077 ahci_cmd_done(chp, xfer, 0 /* XXX slot */);
1078}
1079
1080static int
1081ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is)
1082{
1083 int slot = 0; /* XXX slot */
1084 struct ata_command *ata_c = xfer->c_cmd;
1085 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1086 struct ahci_channel *achp = (struct ahci_channel *)chp;
1087
1088 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n",
1089 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)),
1090 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
1091 DEBUG_FUNCS);
1092 chp->ch_flags &= ~ATACH_IRQ_WAIT;
1093 if (xfer->c_flags & C_TIMEOU) {
1094 ata_c->flags |= AT_TIMEOU;
1095 } else
1096 callout_stop(&chp->ch_callout);
1097
1098 chp->ch_queue->active_xfer = NULL;
1099
1100 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) {
1101 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE);
1102 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN;
1103 wakeup(&chp->ch_queue->active_xfer);
1104 return 0;
1105 }
1106
1107 if (chp->ch_status & WDCS_BSY) {
1108 ata_c->flags |= AT_TIMEOU;
1109 } else if (chp->ch_status & WDCS_ERR) {
1110 ata_c->r_error = chp->ch_error;
1111 ata_c->flags |= AT_ERROR;
1112 }
1113
1114 if (ata_c->flags & AT_READREG)
1115 satafis_rdh_cmd_readreg(ata_c, achp->ahcic_rfis->rfis_rfis);
1116
1117 ahci_cmd_done(chp, xfer, slot);
1118 return 0;
1119}
1120
1121static void
1122ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot)
1123{
1124 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1125 struct ahci_channel *achp = (struct ahci_channel *)chp;
1126 struct ata_command *ata_c = xfer->c_cmd;
1127 uint16_t *idwordbuf;
1128 int i;
1129
1130 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d (status %#x) flags %#x/%#x\n",
1131 chp->ch_channel, chp->ch_status, xfer->c_flags, ata_c->flags), DEBUG_FUNCS);
1132
1133 /* this comamnd is not active any more */
1134 achp->ahcic_cmds_active &= ~(1 << slot);
1135
1136 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) {
1137 bus_dmamap_t map = achp->ahcic_datad[slot];
1138 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1139 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD :
1140 BUS_DMASYNC_POSTWRITE);
1141 bus_dmamap_unload(sc->sc_dmat, map);
1142 }
1143
1144 AHCI_CMDH_SYNC(sc, achp, slot,
1145 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1146
1147 /* ata(4) expects IDENTIFY data to be in host endianess */
1148 if (ata_c->r_command == WDCC_IDENTIFY ||
1149 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) {
1150 idwordbuf = xfer->c_databuf;
1151 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) {
1152 idwordbuf[i] = le16toh(idwordbuf[i]);
1153 }
1154 }
1155
1156 ata_c->flags |= AT_DONE;
1157 if (achp->ahcic_cmdh[slot].cmdh_prdbc)
1158 ata_c->flags |= AT_XFDONE;
1159
1160 ata_free_xfer(chp, xfer);
1161 if (ata_c->flags & AT_WAIT)
1162 wakeup(ata_c);
1163 else if (ata_c->callback)
1164 ata_c->callback(ata_c->callback_arg);
1165 atastart(chp);
1166 return;
1167}
1168
1169static int
1170ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio)
1171{
1172 struct ata_channel *chp = drvp->chnl_softc;
1173 struct ata_xfer *xfer;
1174
1175 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1176 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n",
1177 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
1178 DEBUG_XFERS);
1179 xfer = ata_get_xfer(ATAXF_NOSLEEP);
1180 if (xfer == NULL) {
1181 return ATACMD_TRY_AGAIN;
1182 }
1183 if (ata_bio->flags & ATA_POLL)
1184 xfer->c_flags |= C_POLL;
1185 xfer->c_drive = drvp->drive;
1186 xfer->c_cmd = ata_bio;
1187 xfer->c_databuf = ata_bio->databuf;
1188 xfer->c_bcount = ata_bio->bcount;
1189 xfer->c_start = ahci_bio_start;
1190 xfer->c_intr = ahci_bio_complete;
1191 xfer->c_kill_xfer = ahci_bio_kill_xfer;
1192 ata_exec_xfer(chp, xfer);
1193 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED;
1194}
1195
1196static void
1197ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer)
1198{
1199 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1200 struct ahci_channel *achp = (struct ahci_channel *)chp;
1201 struct ata_bio *ata_bio = xfer->c_cmd;
1202 int slot = 0 /* XXX slot */;
1203 struct ahci_cmd_tbl *cmd_tbl;
1204 struct ahci_cmd_header *cmd_h;
1205 int i;
1206 int channel = chp->ch_channel;
1207
1208 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n",
1209 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
1210
1211 cmd_tbl = achp->ahcic_cmd_tbl[slot];
1212 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
1213 cmd_tbl), DEBUG_XFERS);
1214
1215 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis);
1216 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive;
1217
1218 cmd_h = &achp->ahcic_cmdh[slot];
1219 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
1220 chp->ch_channel, cmd_h), DEBUG_XFERS);
1221 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount,
1222 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) {
1223 ata_bio->error = ERR_DMA;
1224 ata_bio->r_error = 0;
1225 ahci_bio_complete(chp, xfer, slot);
1226 return;
1227 }
1228 cmd_h->cmdh_flags = htole16(
1229 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) |
1230 RHD_FISLEN / 4 | (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT));
1231 cmd_h->cmdh_prdbc = 0;
1232 AHCI_CMDH_SYNC(sc, achp, slot,
1233 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1234
1235 if (xfer->c_flags & C_POLL) {
1236 /* polled command, disable interrupts */
1237 AHCI_WRITE(sc, AHCI_GHC,
1238 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
1239 }
1240 chp->ch_flags |= ATACH_IRQ_WAIT;
1241 chp->ch_status = 0;
1242 /* start command */
1243 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
1244 /* and says we started this command */
1245 achp->ahcic_cmds_active |= 1 << slot;
1246
1247 if ((xfer->c_flags & C_POLL) == 0) {
1248 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
1249 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY),
1250 ahci_timeout, chp);
1251 return;
1252 }
1253 /*
1254 * Polled command.
1255 */
1256 for (i = 0; i < ATA_DELAY * 10; i++) {
1257 if (ata_bio->flags & ATA_ITSDONE)
1258 break;
1259 ahci_intr_port(sc, achp);
1260 delay(100);
1261 }
1262 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
1263 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
1264 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
1265 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
1266 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
1267 DEBUG_XFERS);
1268 if ((ata_bio->flags & ATA_ITSDONE) == 0) {
1269 ata_bio->error = TIMEOUT;
1270 ahci_bio_complete(chp, xfer, slot);
1271 }
1272 /* reenable interrupts */
1273 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
1274}
1275
1276static void
1277ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
1278{
1279 int slot = 0; /* XXX slot */
1280 int drive = xfer->c_drive;
1281 struct ata_bio *ata_bio = xfer->c_cmd;
1282 struct ahci_channel *achp = (struct ahci_channel *)chp;
1283 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel),
1284 DEBUG_FUNCS);
1285
1286 achp->ahcic_cmds_active &= ~(1 << slot);
1287 ata_free_xfer(chp, xfer);
1288 ata_bio->flags |= ATA_ITSDONE;
1289 switch (reason) {
1290 case KILL_GONE:
1291 ata_bio->error = ERR_NODEV;
1292 break;
1293 case KILL_RESET:
1294 ata_bio->error = ERR_RESET;
1295 break;
1296 default:
1297 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason);
1298 panic("ahci_bio_kill_xfer");
1299 }
1300 ata_bio->r_error = WDCE_ABRT;
1301 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
1302}
1303
1304static int
1305ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is)
1306{
1307 int slot = 0; /* XXX slot */
1308 struct ata_bio *ata_bio = xfer->c_cmd;
1309 int drive = xfer->c_drive;
1310 struct ahci_channel *achp = (struct ahci_channel *)chp;
1311 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1312
1313 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel),
1314 DEBUG_FUNCS);
1315
1316 achp->ahcic_cmds_active &= ~(1 << slot);
1317 chp->ch_flags &= ~ATACH_IRQ_WAIT;
1318 if (xfer->c_flags & C_TIMEOU) {
1319 ata_bio->error = TIMEOUT;
1320 } else {
1321 callout_stop(&chp->ch_callout);
1322 ata_bio->error = NOERROR;
1323 }
1324
1325 chp->ch_queue->active_xfer = NULL;
1326 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
1327 achp->ahcic_datad[slot]->dm_mapsize,
1328 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD :
1329 BUS_DMASYNC_POSTWRITE);
1330 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]);
1331
1332 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) {
1333 ahci_bio_kill_xfer(chp, xfer, KILL_GONE);
1334 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN;
1335 wakeup(&chp->ch_queue->active_xfer);
1336 return 0;
1337 }
1338 ata_free_xfer(chp, xfer);
1339 ata_bio->flags |= ATA_ITSDONE;
1340 if (chp->ch_status & WDCS_DWF) {
1341 ata_bio->error = ERR_DF;
1342 } else if (chp->ch_status & WDCS_ERR) {
1343 ata_bio->error = ERROR;
1344 ata_bio->r_error = chp->ch_error;
1345 } else if (chp->ch_status & WDCS_CORR)
1346 ata_bio->flags |= ATA_CORR;
1347
1348 AHCI_CMDH_SYNC(sc, achp, slot,
1349 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1350 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld",
1351 ata_bio->bcount), DEBUG_XFERS);
1352 /*
1353 * if it was a write, complete data buffer may have been transfered
1354 * before error detection; in this case don't use cmdh_prdbc
1355 * as it won't reflect what was written to media. Assume nothing
1356 * was transfered and leave bcount as-is.
1357 */
1358 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR)
1359 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc);
1360 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS);
1361 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
1362 atastart(chp);
1363 return 0;
1364}
1365
1366static void
1367ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags)
1368{
1369 int i;
1370 /* stop channel */
1371 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
1372 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST);
1373 /* wait 1s for channel to stop */
1374 for (i = 0; i <100; i++) {
1375 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR)
1376 == 0)
1377 break;
1378 if (flags & AT_WAIT)
1379 tsleep(&sc, PRIBIO, "ahcistop", mstohz(10));
1380 else
1381 delay(10000);
1382 }
1383 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) {
1384 printf("%s: channel wouldn't stop\n", AHCINAME(sc));
1385 /* XXX controller reset ? */
1386 return;
1387 }
1388
1389 if (sc->sc_channel_stop)
1390 sc->sc_channel_stop(sc, chp);
1391}
1392
1393static void
1394ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp,
1395 int flags, int clo)
1396{
1397 int i;
1398 uint32_t p_cmd;
1399 /* clear error */
1400 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel),
1401 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel)));
1402
1403 if (clo) {
1404 /* issue command list override */
1405 KASSERT(sc->sc_ahci_cap & AHCI_CAP_CLO);
1406 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
1407 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) | AHCI_P_CMD_CLO);
1408 /* wait 1s for AHCI_CAP_CLO to clear */
1409 for (i = 0; i <100; i++) {
1410 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) &
1411 AHCI_P_CMD_CLO) == 0)
1412 break;
1413 if (flags & AT_WAIT)
1414 tsleep(&sc, PRIBIO, "ahciclo", mstohz(10));
1415 else
1416 delay(10000);
1417 }
1418 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CLO) {
1419 printf("%s: channel wouldn't CLO\n", AHCINAME(sc));
1420 /* XXX controller reset ? */
1421 return;
1422 }
1423 }
1424
1425 if (sc->sc_channel_start)
1426 sc->sc_channel_start(sc, chp);
1427
1428 /* and start controller */
1429 p_cmd = AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
1430 AHCI_P_CMD_FRE | AHCI_P_CMD_ST;
1431 if (chp->ch_ndrives > PMP_PORT_CTL &&
1432 chp->ch_drive[PMP_PORT_CTL].drive_type == ATA_DRIVET_PM) {
1433 p_cmd |= AHCI_P_CMD_PMA;
1434 }
1435 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), p_cmd);
1436}
1437
1438static void
1439ahci_timeout(void *v)
1440{
1441 struct ata_channel *chp = (struct ata_channel *)v;
1442 struct ata_xfer *xfer = chp->ch_queue->active_xfer;
1443#ifdef AHCI_DEBUG
1444 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1445#endif
1446 int s = splbio();
1447 AHCIDEBUG_PRINT(("ahci_timeout xfer %p intr %#x ghc %08x is %08x\n", xfer, AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)), AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS)), DEBUG_INTR);
1448
1449 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) {
1450 xfer->c_flags |= C_TIMEOU;
1451 xfer->c_intr(chp, xfer, 0);
1452 }
1453 splx(s);
1454}
1455
1456static int
1457ahci_dma_setup(struct ata_channel *chp, int slot, void *data,
1458 size_t count, int op)
1459{
1460 int error, seg;
1461 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1462 struct ahci_channel *achp = (struct ahci_channel *)chp;
1463 struct ahci_cmd_tbl *cmd_tbl;
1464 struct ahci_cmd_header *cmd_h;
1465
1466 cmd_h = &achp->ahcic_cmdh[slot];
1467 cmd_tbl = achp->ahcic_cmd_tbl[slot];
1468
1469 if (data == NULL) {
1470 cmd_h->cmdh_prdtl = 0;
1471 goto end;
1472 }
1473
1474 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot],
1475 data, count, NULL,
1476 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op);
1477 if (error) {
1478 printf("%s port %d: failed to load xfer: %d\n",
1479 AHCINAME(sc), chp->ch_channel, error);
1480 return error;
1481 }
1482 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
1483 achp->ahcic_datad[slot]->dm_mapsize,
1484 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1485 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) {
1486 cmd_tbl->cmdt_prd[seg].prd_dba = htole64(
1487 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr);
1488 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32(
1489 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1);
1490 }
1491 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC);
1492 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs);
1493end:
1494 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE);
1495 return 0;
1496}
1497
1498#if NATAPIBUS > 0
1499static void
1500ahci_atapibus_attach(struct atabus_softc * ata_sc)
1501{
1502 struct ata_channel *chp = ata_sc->sc_chan;
1503 struct atac_softc *atac = chp->ch_atac;
1504 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
1505 struct scsipi_channel *chan = &chp->ch_atapi_channel;
1506 /*
1507 * Fill in the scsipi_adapter.
1508 */
1509 adapt->adapt_dev = atac->atac_dev;
1510 adapt->adapt_nchannels = atac->atac_nchannels;
1511 adapt->adapt_request = ahci_atapi_scsipi_request;
1512 adapt->adapt_minphys = ahci_atapi_minphys;
1513 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device;
1514
1515 /*
1516 * Fill in the scsipi_channel.
1517 */
1518 memset(chan, 0, sizeof(*chan));
1519 chan->chan_adapter = adapt;
1520 chan->chan_bustype = &ahci_atapi_bustype;
1521 chan->chan_channel = chp->ch_channel;
1522 chan->chan_flags = SCSIPI_CHAN_OPENINGS;
1523 chan->chan_openings = 1;
1524 chan->chan_max_periph = 1;
1525 chan->chan_ntargets = 1;
1526 chan->chan_nluns = 1;
1527 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan,
1528 atapiprint);
1529}
1530
1531static void
1532ahci_atapi_minphys(struct buf *bp)
1533{
1534 if (bp->b_bcount > MAXPHYS)
1535 bp->b_bcount = MAXPHYS;
1536 minphys(bp);
1537}
1538
1539/*
1540 * Kill off all pending xfers for a periph.
1541 *
1542 * Must be called at splbio().
1543 */
1544static void
1545ahci_atapi_kill_pending(struct scsipi_periph *periph)
1546{
1547 struct atac_softc *atac =
1548 device_private(periph->periph_channel->chan_adapter->adapt_dev);
1549 struct ata_channel *chp =
1550 atac->atac_channels[periph->periph_channel->chan_channel];
1551
1552 ata_kill_pending(&chp->ch_drive[periph->periph_target]);
1553}
1554
1555static void
1556ahci_atapi_scsipi_request(struct scsipi_channel *chan,
1557 scsipi_adapter_req_t req, void *arg)
1558{
1559 struct scsipi_adapter *adapt = chan->chan_adapter;
1560 struct scsipi_periph *periph;
1561 struct scsipi_xfer *sc_xfer;
1562 struct ahci_softc *sc = device_private(adapt->adapt_dev);
1563 struct atac_softc *atac = &sc->sc_atac;
1564 struct ata_xfer *xfer;
1565 int channel = chan->chan_channel;
1566 int drive, s;
1567
1568 switch (req) {
1569 case ADAPTER_REQ_RUN_XFER:
1570 sc_xfer = arg;
1571 periph = sc_xfer->xs_periph;
1572 drive = periph->periph_target;
1573 if (!device_is_active(atac->atac_dev)) {
1574 sc_xfer->error = XS_DRIVER_STUFFUP;
1575 scsipi_done(sc_xfer);
1576 return;
1577 }
1578 xfer = ata_get_xfer(ATAXF_NOSLEEP);
1579 if (xfer == NULL) {
1580 sc_xfer->error = XS_RESOURCE_SHORTAGE;
1581 scsipi_done(sc_xfer);
1582 return;
1583 }
1584
1585 if (sc_xfer->xs_control & XS_CTL_POLL)
1586 xfer->c_flags |= C_POLL;
1587 xfer->c_drive = drive;
1588 xfer->c_flags |= C_ATAPI;
1589 xfer->c_cmd = sc_xfer;
1590 xfer->c_databuf = sc_xfer->data;
1591 xfer->c_bcount = sc_xfer->datalen;
1592 xfer->c_start = ahci_atapi_start;
1593 xfer->c_intr = ahci_atapi_complete;
1594 xfer->c_kill_xfer = ahci_atapi_kill_xfer;
1595 xfer->c_dscpoll = 0;
1596 s = splbio();
1597 ata_exec_xfer(atac->atac_channels[channel], xfer);
1598#ifdef DIAGNOSTIC
1599 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 &&
1600 (sc_xfer->xs_status & XS_STS_DONE) == 0)
1601 panic("ahci_atapi_scsipi_request: polled command "
1602 "not done");
1603#endif
1604 splx(s);
1605 return;
1606 default:
1607 /* Not supported, nothing to do. */
1608 ;
1609 }
1610}
1611
1612static void
1613ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer)
1614{
1615 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1616 struct ahci_channel *achp = (struct ahci_channel *)chp;
1617 struct scsipi_xfer *sc_xfer = xfer->c_cmd;
1618 int slot = 0 /* XXX slot */;
1619 struct ahci_cmd_tbl *cmd_tbl;
1620 struct ahci_cmd_header *cmd_h;
1621 int i;
1622 int channel = chp->ch_channel;
1623
1624 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n",
1625 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
1626
1627 cmd_tbl = achp->ahcic_cmd_tbl[slot];
1628 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
1629 cmd_tbl), DEBUG_XFERS);
1630
1631 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis);
1632 cmd_tbl->cmdt_cfis[rhd_c] |= xfer->c_drive;
1633 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd));
1634 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen);
1635
1636 cmd_h = &achp->ahcic_cmdh[slot];
1637 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
1638 chp->ch_channel, cmd_h), DEBUG_XFERS);
1639 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL,
1640 sc_xfer->datalen,
1641 (sc_xfer->xs_control & XS_CTL_DATA_IN) ?
1642 BUS_DMA_READ : BUS_DMA_WRITE)) {
1643 sc_xfer->error = XS_DRIVER_STUFFUP;
1644 ahci_atapi_complete(chp, xfer, slot);
1645 return;
1646 }
1647 cmd_h->cmdh_flags = htole16(
1648 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) |
1649 RHD_FISLEN / 4 | AHCI_CMDH_F_A |
1650 (xfer->c_drive << AHCI_CMDH_F_PMP_SHIFT));
1651 cmd_h->cmdh_prdbc = 0;
1652 AHCI_CMDH_SYNC(sc, achp, slot,
1653 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1654
1655 if (xfer->c_flags & C_POLL) {
1656 /* polled command, disable interrupts */
1657 AHCI_WRITE(sc, AHCI_GHC,
1658 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
1659 }
1660 chp->ch_flags |= ATACH_IRQ_WAIT;
1661 chp->ch_status = 0;
1662 /* start command */
1663 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
1664 /* and says we started this command */
1665 achp->ahcic_cmds_active |= 1 << slot;
1666
1667 if ((xfer->c_flags & C_POLL) == 0) {
1668 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
1669 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout),
1670 ahci_timeout, chp);
1671 return;
1672 }
1673 /*
1674 * Polled command.
1675 */
1676 for (i = 0; i < ATA_DELAY / 10; i++) {
1677 if (sc_xfer->xs_status & XS_STS_DONE)
1678 break;
1679 ahci_intr_port(sc, achp);
1680 delay(10000);
1681 }
1682 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
1683 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
1684 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
1685 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
1686 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
1687 DEBUG_XFERS);
1688 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) {
1689 sc_xfer->error = XS_TIMEOUT;
1690 ahci_atapi_complete(chp, xfer, slot);
1691 }
1692 /* reenable interrupts */
1693 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
1694}
1695
1696static int
1697ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq)
1698{
1699 int slot = 0; /* XXX slot */
1700 struct scsipi_xfer *sc_xfer = xfer->c_cmd;
1701 int drive = xfer->c_drive;
1702 struct ahci_channel *achp = (struct ahci_channel *)chp;
1703 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1704
1705 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel),
1706 DEBUG_FUNCS);
1707
1708 achp->ahcic_cmds_active &= ~(1 << slot);
1709 chp->ch_flags &= ~ATACH_IRQ_WAIT;
1710 if (xfer->c_flags & C_TIMEOU) {
1711 sc_xfer->error = XS_TIMEOUT;
1712 } else {
1713 callout_stop(&chp->ch_callout);
1714 sc_xfer->error = 0;
1715 }
1716
1717 chp->ch_queue->active_xfer = NULL;
1718 if (xfer->c_bcount > 0) {
1719 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
1720 achp->ahcic_datad[slot]->dm_mapsize,
1721 (sc_xfer->xs_control & XS_CTL_DATA_IN) ?
1722 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1723 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]);
1724 }
1725
1726 if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) {
1727 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE);
1728 chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN;
1729 wakeup(&chp->ch_queue->active_xfer);
1730 return 0;
1731 }
1732 ata_free_xfer(chp, xfer);
1733
1734 AHCI_CMDH_SYNC(sc, achp, slot,
1735 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1736 sc_xfer->resid = sc_xfer->datalen;
1737 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc);
1738 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n",
1739 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS);
1740 if (chp->ch_status & WDCS_ERR &&
1741 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 ||
1742 sc_xfer->resid == sc_xfer->datalen)) {
1743 sc_xfer->error = XS_SHORTSENSE;
1744 sc_xfer->sense.atapi_sense = chp->ch_error;
1745 if ((sc_xfer->xs_periph->periph_quirks &
1746 PQUIRK_NOSENSE) == 0) {
1747 /* ask scsipi to send a REQUEST_SENSE */
1748 sc_xfer->error = XS_BUSY;
1749 sc_xfer->status = SCSI_CHECK;
1750 }
1751 }
1752 scsipi_done(sc_xfer);
1753 atastart(chp);
1754 return 0;
1755}
1756
1757static void
1758ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
1759{
1760 struct scsipi_xfer *sc_xfer = xfer->c_cmd;
1761 struct ahci_channel *achp = (struct ahci_channel *)chp;
1762 int slot = 0; /* XXX slot */
1763
1764 achp->ahcic_cmds_active &= ~(1 << slot);
1765
1766 /* remove this command from xfer queue */
1767 switch (reason) {
1768 case KILL_GONE:
1769 sc_xfer->error = XS_DRIVER_STUFFUP;
1770 break;
1771 case KILL_RESET:
1772 sc_xfer->error = XS_RESET;
1773 break;
1774 default:
1775 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason);
1776 panic("ahci_ata_atapi_kill_xfer");
1777 }
1778 ata_free_xfer(chp, xfer);
1779 scsipi_done(sc_xfer);
1780}
1781
1782static void
1783ahci_atapi_probe_device(struct atapibus_softc *sc, int target)
1784{
1785 struct scsipi_channel *chan = sc->sc_channel;
1786 struct scsipi_periph *periph;
1787 struct ataparams ids;
1788 struct ataparams *id = &ids;
1789 struct ahci_softc *ahcic =
1790 device_private(chan->chan_adapter->adapt_dev);
1791 struct atac_softc *atac = &ahcic->sc_atac;
1792 struct ata_channel *chp = atac->atac_channels[chan->chan_channel];
1793 struct ata_drive_datas *drvp = &chp->ch_drive[target];
1794 struct scsipibus_attach_args sa;
1795 char serial_number[21], model[41], firmware_revision[9];
1796 int s;
1797
1798 /* skip if already attached */
1799 if (scsipi_lookup_periph(chan, target, 0) != NULL)
1800 return;
1801
1802 /* if no ATAPI device detected at attach time, skip */
1803 if (drvp->drive_type != ATA_DRIVET_ATAPI) {
1804 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d "
1805 "not present\n", target), DEBUG_PROBE);
1806 return;
1807 }
1808
1809 /* Some ATAPI devices need a bit more time after software reset. */
1810 delay(5000);
1811 if (ata_get_params(drvp, AT_WAIT, id) == 0) {
1812#ifdef ATAPI_DEBUG_PROBE
1813 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n",
1814 AHCINAME(ahcic), target,
1815 id->atap_config & ATAPI_CFG_CMD_MASK,
1816 id->atap_config & ATAPI_CFG_DRQ_MASK);
1817#endif
1818 periph = scsipi_alloc_periph(M_NOWAIT);
1819 if (periph == NULL) {
1820 aprint_error_dev(sc->sc_dev,
1821 "unable to allocate periph for drive %d\n",
1822 target);
1823 return;
1824 }
1825 periph->periph_dev = NULL;
1826 periph->periph_channel = chan;
1827 periph->periph_switch = &atapi_probe_periphsw;
1828 periph->periph_target = target;
1829 periph->periph_lun = 0;
1830 periph->periph_quirks = PQUIRK_ONLYBIG;
1831
1832#ifdef SCSIPI_DEBUG
1833 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI &&
1834 SCSIPI_DEBUG_TARGET == target)
1835 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS;
1836#endif
1837 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config);
1838 if (id->atap_config & ATAPI_CFG_REMOV)
1839 periph->periph_flags |= PERIPH_REMOVABLE;
1840 if (periph->periph_type == T_SEQUENTIAL) {
1841 s = splbio();
1842 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW;
1843 splx(s);
1844 }
1845
1846 sa.sa_periph = periph;
1847 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config);
1848 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ?
1849 T_REMOV : T_FIXED;
1850 strnvisx(model, sizeof(model), id->atap_model, 40,
1851 VIS_TRIM|VIS_SAFE|VIS_OCTAL);
1852 strnvisx(serial_number, sizeof(serial_number), id->atap_serial,
1853 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL);
1854 strnvisx(firmware_revision, sizeof(firmware_revision),
1855 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL);
1856 sa.sa_inqbuf.vendor = model;
1857 sa.sa_inqbuf.product = serial_number;
1858 sa.sa_inqbuf.revision = firmware_revision;
1859
1860 /*
1861 * Determine the operating mode capabilities of the device.
1862 */
1863 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16)
1864 periph->periph_cap |= PERIPH_CAP_CMD16;
1865 /* XXX This is gross. */
1866 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK);
1867
1868 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa);
1869
1870 if (drvp->drv_softc)
1871 ata_probe_caps(drvp);
1872 else {
1873 s = splbio();
1874 drvp->drive_type = ATA_DRIVET_NONE;
1875 splx(s);
1876 }
1877 } else {
1878 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE "
1879 "failed for drive %s:%d:%d: error 0x%x\n",
1880 AHCINAME(ahcic), chp->ch_channel, target,
1881 chp->ch_error), DEBUG_PROBE);
1882 s = splbio();
1883 drvp->drive_type = ATA_DRIVET_NONE;
1884 splx(s);
1885 }
1886}
1887#endif /* NATAPIBUS */
1888