1 | /* $NetBSD: nouveau_subdev_clock_nve0.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2013 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_clock_nve0.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $" ); |
29 | |
30 | #include <subdev/clock.h> |
31 | #include <subdev/timer.h> |
32 | #include <subdev/bios.h> |
33 | #include <subdev/bios/pll.h> |
34 | |
35 | #include "pll.h" |
36 | |
37 | struct nve0_clock_info { |
38 | u32 freq; |
39 | u32 ssel; |
40 | u32 mdiv; |
41 | u32 dsrc; |
42 | u32 ddiv; |
43 | u32 coef; |
44 | }; |
45 | |
46 | struct nve0_clock_priv { |
47 | struct nouveau_clock base; |
48 | struct nve0_clock_info eng[16]; |
49 | }; |
50 | |
51 | static u32 read_div(struct nve0_clock_priv *, int, u32, u32); |
52 | static u32 read_pll(struct nve0_clock_priv *, u32); |
53 | |
54 | static u32 |
55 | read_vco(struct nve0_clock_priv *priv, u32 dsrc) |
56 | { |
57 | u32 ssrc = nv_rd32(priv, dsrc); |
58 | if (!(ssrc & 0x00000100)) |
59 | return read_pll(priv, 0x00e800); |
60 | return read_pll(priv, 0x00e820); |
61 | } |
62 | |
63 | static u32 |
64 | read_pll(struct nve0_clock_priv *priv, u32 pll) |
65 | { |
66 | u32 ctrl = nv_rd32(priv, pll + 0x00); |
67 | u32 coef = nv_rd32(priv, pll + 0x04); |
68 | u32 P = (coef & 0x003f0000) >> 16; |
69 | u32 N = (coef & 0x0000ff00) >> 8; |
70 | u32 M = (coef & 0x000000ff) >> 0; |
71 | u32 sclk; |
72 | u16 fN = 0xf000; |
73 | |
74 | if (!(ctrl & 0x00000001)) |
75 | return 0; |
76 | |
77 | switch (pll) { |
78 | case 0x00e800: |
79 | case 0x00e820: |
80 | sclk = nv_device(priv)->crystal; |
81 | P = 1; |
82 | break; |
83 | case 0x132000: |
84 | sclk = read_pll(priv, 0x132020); |
85 | P = (coef & 0x10000000) ? 2 : 1; |
86 | break; |
87 | case 0x132020: |
88 | sclk = read_div(priv, 0, 0x137320, 0x137330); |
89 | fN = nv_rd32(priv, pll + 0x10) >> 16; |
90 | break; |
91 | case 0x137000: |
92 | case 0x137020: |
93 | case 0x137040: |
94 | case 0x1370e0: |
95 | sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140); |
96 | break; |
97 | default: |
98 | return 0; |
99 | } |
100 | |
101 | if (P == 0) |
102 | P = 1; |
103 | |
104 | sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13); |
105 | return sclk / (M * P); |
106 | } |
107 | |
108 | static u32 |
109 | read_div(struct nve0_clock_priv *priv, int doff, u32 dsrc, u32 dctl) |
110 | { |
111 | u32 ssrc = nv_rd32(priv, dsrc + (doff * 4)); |
112 | u32 sctl = nv_rd32(priv, dctl + (doff * 4)); |
113 | |
114 | switch (ssrc & 0x00000003) { |
115 | case 0: |
116 | if ((ssrc & 0x00030000) != 0x00030000) |
117 | return nv_device(priv)->crystal; |
118 | return 108000; |
119 | case 2: |
120 | return 100000; |
121 | case 3: |
122 | if (sctl & 0x80000000) { |
123 | u32 sclk = read_vco(priv, dsrc + (doff * 4)); |
124 | u32 sdiv = (sctl & 0x0000003f) + 2; |
125 | return (sclk * 2) / sdiv; |
126 | } |
127 | |
128 | return read_vco(priv, dsrc + (doff * 4)); |
129 | default: |
130 | return 0; |
131 | } |
132 | } |
133 | |
134 | static u32 |
135 | read_mem(struct nve0_clock_priv *priv) |
136 | { |
137 | switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) { |
138 | case 1: return read_pll(priv, 0x132020); |
139 | case 2: return read_pll(priv, 0x132000); |
140 | default: |
141 | return 0; |
142 | } |
143 | } |
144 | |
145 | static u32 |
146 | read_clk(struct nve0_clock_priv *priv, int clk) |
147 | { |
148 | u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); |
149 | u32 sclk, sdiv; |
150 | |
151 | if (clk < 7) { |
152 | u32 ssel = nv_rd32(priv, 0x137100); |
153 | if (ssel & (1 << clk)) { |
154 | sclk = read_pll(priv, 0x137000 + (clk * 0x20)); |
155 | sdiv = 1; |
156 | } else { |
157 | sclk = read_div(priv, clk, 0x137160, 0x1371d0); |
158 | sdiv = 0; |
159 | } |
160 | } else { |
161 | u32 ssrc = nv_rd32(priv, 0x137160 + (clk * 0x04)); |
162 | if ((ssrc & 0x00000003) == 0x00000003) { |
163 | sclk = read_div(priv, clk, 0x137160, 0x1371d0); |
164 | if (ssrc & 0x00000100) { |
165 | if (ssrc & 0x40000000) |
166 | sclk = read_pll(priv, 0x1370e0); |
167 | sdiv = 1; |
168 | } else { |
169 | sdiv = 0; |
170 | } |
171 | } else { |
172 | sclk = read_div(priv, clk, 0x137160, 0x1371d0); |
173 | sdiv = 0; |
174 | } |
175 | } |
176 | |
177 | if (sctl & 0x80000000) { |
178 | if (sdiv) |
179 | sdiv = ((sctl & 0x00003f00) >> 8) + 2; |
180 | else |
181 | sdiv = ((sctl & 0x0000003f) >> 0) + 2; |
182 | return (sclk * 2) / sdiv; |
183 | } |
184 | |
185 | return sclk; |
186 | } |
187 | |
188 | static int |
189 | nve0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) |
190 | { |
191 | struct nouveau_device *device = nv_device(clk); |
192 | struct nve0_clock_priv *priv = (void *)clk; |
193 | |
194 | switch (src) { |
195 | case nv_clk_src_crystal: |
196 | return device->crystal; |
197 | case nv_clk_src_href: |
198 | return 100000; |
199 | case nv_clk_src_mem: |
200 | return read_mem(priv); |
201 | case nv_clk_src_gpc: |
202 | return read_clk(priv, 0x00); |
203 | case nv_clk_src_rop: |
204 | return read_clk(priv, 0x01); |
205 | case nv_clk_src_hubk07: |
206 | return read_clk(priv, 0x02); |
207 | case nv_clk_src_hubk06: |
208 | return read_clk(priv, 0x07); |
209 | case nv_clk_src_hubk01: |
210 | return read_clk(priv, 0x08); |
211 | case nv_clk_src_daemon: |
212 | return read_clk(priv, 0x0c); |
213 | case nv_clk_src_vdec: |
214 | return read_clk(priv, 0x0e); |
215 | default: |
216 | nv_error(clk, "invalid clock source %d\n" , src); |
217 | return -EINVAL; |
218 | } |
219 | } |
220 | |
221 | static u32 |
222 | calc_div(struct nve0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) |
223 | { |
224 | u32 div = min((ref * 2) / freq, (u32)65); |
225 | if (div < 2) |
226 | div = 2; |
227 | |
228 | *ddiv = div - 2; |
229 | return (ref * 2) / div; |
230 | } |
231 | |
232 | static u32 |
233 | calc_src(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) |
234 | { |
235 | u32 sclk; |
236 | |
237 | /* use one of the fixed frequencies if possible */ |
238 | *ddiv = 0x00000000; |
239 | switch (freq) { |
240 | case 27000: |
241 | case 108000: |
242 | *dsrc = 0x00000000; |
243 | if (freq == 108000) |
244 | *dsrc |= 0x00030000; |
245 | return freq; |
246 | case 100000: |
247 | *dsrc = 0x00000002; |
248 | return freq; |
249 | default: |
250 | *dsrc = 0x00000003; |
251 | break; |
252 | } |
253 | |
254 | /* otherwise, calculate the closest divider */ |
255 | sclk = read_vco(priv, 0x137160 + (clk * 4)); |
256 | if (clk < 7) |
257 | sclk = calc_div(priv, clk, sclk, freq, ddiv); |
258 | return sclk; |
259 | } |
260 | |
261 | static u32 |
262 | calc_pll(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *coef) |
263 | { |
264 | struct nouveau_bios *bios = nouveau_bios(priv); |
265 | struct nvbios_pll limits; |
266 | int N, M, P, ret; |
267 | |
268 | ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits); |
269 | if (ret) |
270 | return 0; |
271 | |
272 | limits.refclk = read_div(priv, clk, 0x137120, 0x137140); |
273 | if (!limits.refclk) |
274 | return 0; |
275 | |
276 | ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P); |
277 | if (ret <= 0) |
278 | return 0; |
279 | |
280 | *coef = (P << 16) | (N << 8) | M; |
281 | return ret; |
282 | } |
283 | |
284 | static int |
285 | calc_clk(struct nve0_clock_priv *priv, |
286 | struct nouveau_cstate *cstate, int clk, int dom) |
287 | { |
288 | struct nve0_clock_info *info = &priv->eng[clk]; |
289 | u32 freq = cstate->domain[dom]; |
290 | u32 src0, div0, div1D, div1P = 0; |
291 | u32 clk0, clk1 = 0; |
292 | |
293 | /* invalid clock domain */ |
294 | if (!freq) |
295 | return 0; |
296 | |
297 | /* first possible path, using only dividers */ |
298 | clk0 = calc_src(priv, clk, freq, &src0, &div0); |
299 | clk0 = calc_div(priv, clk, clk0, freq, &div1D); |
300 | |
301 | /* see if we can get any closer using PLLs */ |
302 | if (clk0 != freq && (0x0000ff87 & (1 << clk))) { |
303 | if (clk <= 7) |
304 | clk1 = calc_pll(priv, clk, freq, &info->coef); |
305 | else |
306 | clk1 = cstate->domain[nv_clk_src_hubk06]; |
307 | clk1 = calc_div(priv, clk, clk1, freq, &div1P); |
308 | } |
309 | |
310 | /* select the method which gets closest to target freq */ |
311 | if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { |
312 | info->dsrc = src0; |
313 | if (div0) { |
314 | info->ddiv |= 0x80000000; |
315 | info->ddiv |= div0 << 8; |
316 | info->ddiv |= div0; |
317 | } |
318 | if (div1D) { |
319 | info->mdiv |= 0x80000000; |
320 | info->mdiv |= div1D; |
321 | } |
322 | info->ssel = 0; |
323 | info->freq = clk0; |
324 | } else { |
325 | if (div1P) { |
326 | info->mdiv |= 0x80000000; |
327 | info->mdiv |= div1P << 8; |
328 | } |
329 | info->ssel = (1 << clk); |
330 | info->dsrc = 0x40000100; |
331 | info->freq = clk1; |
332 | } |
333 | |
334 | return 0; |
335 | } |
336 | |
337 | static int |
338 | nve0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) |
339 | { |
340 | struct nve0_clock_priv *priv = (void *)clk; |
341 | int ret; |
342 | |
343 | if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) || |
344 | (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) || |
345 | (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) || |
346 | (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) || |
347 | (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) || |
348 | (ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) || |
349 | (ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec))) |
350 | return ret; |
351 | |
352 | return 0; |
353 | } |
354 | |
355 | static void |
356 | nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk) |
357 | { |
358 | struct nve0_clock_info *info = &priv->eng[clk]; |
359 | if (!info->ssel) { |
360 | nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv); |
361 | nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); |
362 | } |
363 | } |
364 | |
365 | static void |
366 | nve0_clock_prog_1_0(struct nve0_clock_priv *priv, int clk) |
367 | { |
368 | nv_mask(priv, 0x137100, (1 << clk), 0x00000000); |
369 | nv_wait(priv, 0x137100, (1 << clk), 0x00000000); |
370 | } |
371 | |
372 | static void |
373 | nve0_clock_prog_1_1(struct nve0_clock_priv *priv, int clk) |
374 | { |
375 | nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000); |
376 | } |
377 | |
378 | static void |
379 | nve0_clock_prog_2(struct nve0_clock_priv *priv, int clk) |
380 | { |
381 | struct nve0_clock_info *info = &priv->eng[clk]; |
382 | const u32 addr = 0x137000 + (clk * 0x20); |
383 | nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000); |
384 | nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000); |
385 | if (info->coef) { |
386 | nv_wr32(priv, addr + 0x04, info->coef); |
387 | nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001); |
388 | nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000); |
389 | nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004); |
390 | } |
391 | } |
392 | |
393 | static void |
394 | nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk) |
395 | { |
396 | struct nve0_clock_info *info = &priv->eng[clk]; |
397 | nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); |
398 | } |
399 | |
400 | static void |
401 | nve0_clock_prog_4_0(struct nve0_clock_priv *priv, int clk) |
402 | { |
403 | struct nve0_clock_info *info = &priv->eng[clk]; |
404 | if (info->ssel) { |
405 | nv_mask(priv, 0x137100, (1 << clk), info->ssel); |
406 | nv_wait(priv, 0x137100, (1 << clk), info->ssel); |
407 | } |
408 | } |
409 | |
410 | static void |
411 | nve0_clock_prog_4_1(struct nve0_clock_priv *priv, int clk) |
412 | { |
413 | struct nve0_clock_info *info = &priv->eng[clk]; |
414 | if (info->ssel) { |
415 | nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000); |
416 | nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100); |
417 | } |
418 | } |
419 | |
420 | static int |
421 | nve0_clock_prog(struct nouveau_clock *clk) |
422 | { |
423 | struct nve0_clock_priv *priv = (void *)clk; |
424 | struct { |
425 | u32 mask; |
426 | void (*exec)(struct nve0_clock_priv *, int); |
427 | } stage[] = { |
428 | { 0x007f, nve0_clock_prog_0 }, /* div programming */ |
429 | { 0x007f, nve0_clock_prog_1_0 }, /* select div mode */ |
430 | { 0xff80, nve0_clock_prog_1_1 }, |
431 | { 0x00ff, nve0_clock_prog_2 }, /* (maybe) program pll */ |
432 | { 0xff80, nve0_clock_prog_3 }, /* final divider */ |
433 | { 0x007f, nve0_clock_prog_4_0 }, /* (maybe) select pll mode */ |
434 | { 0xff80, nve0_clock_prog_4_1 }, |
435 | }; |
436 | int i, j; |
437 | |
438 | for (i = 0; i < ARRAY_SIZE(stage); i++) { |
439 | for (j = 0; j < ARRAY_SIZE(priv->eng); j++) { |
440 | if (!(stage[i].mask & (1 << j))) |
441 | continue; |
442 | if (!priv->eng[j].freq) |
443 | continue; |
444 | stage[i].exec(priv, j); |
445 | } |
446 | } |
447 | |
448 | return 0; |
449 | } |
450 | |
451 | static void |
452 | nve0_clock_tidy(struct nouveau_clock *clk) |
453 | { |
454 | struct nve0_clock_priv *priv = (void *)clk; |
455 | memset(priv->eng, 0x00, sizeof(priv->eng)); |
456 | } |
457 | |
458 | static struct nouveau_clocks |
459 | nve0_domain[] = { |
460 | { nv_clk_src_crystal, 0xff }, |
461 | { nv_clk_src_href , 0xff }, |
462 | { nv_clk_src_gpc , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core" , 2000 }, |
463 | { nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE }, |
464 | { nv_clk_src_rop , 0x02, NVKM_CLK_DOM_FLAG_CORE }, |
465 | { nv_clk_src_mem , 0x03, 0, "memory" , 500 }, |
466 | { nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE }, |
467 | { nv_clk_src_hubk01 , 0x05 }, |
468 | { nv_clk_src_vdec , 0x06 }, |
469 | { nv_clk_src_daemon , 0x07 }, |
470 | { nv_clk_src_max } |
471 | }; |
472 | |
473 | static int |
474 | nve0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
475 | struct nouveau_oclass *oclass, void *data, u32 size, |
476 | struct nouveau_object **pobject) |
477 | { |
478 | struct nve0_clock_priv *priv; |
479 | int ret; |
480 | |
481 | ret = nouveau_clock_create(parent, engine, oclass, nve0_domain, &priv); |
482 | *pobject = nv_object(priv); |
483 | if (ret) |
484 | return ret; |
485 | |
486 | priv->base.read = nve0_clock_read; |
487 | priv->base.calc = nve0_clock_calc; |
488 | priv->base.prog = nve0_clock_prog; |
489 | priv->base.tidy = nve0_clock_tidy; |
490 | return 0; |
491 | } |
492 | |
493 | struct nouveau_oclass |
494 | nve0_clock_oclass = { |
495 | .handle = NV_SUBDEV(CLOCK, 0xe0), |
496 | .ofuncs = &(struct nouveau_ofuncs) { |
497 | .ctor = nve0_clock_ctor, |
498 | .dtor = _nouveau_clock_dtor, |
499 | .init = _nouveau_clock_init, |
500 | .fini = _nouveau_clock_fini, |
501 | }, |
502 | }; |
503 | |