1 | /* $NetBSD: ubsecvar.h,v 1.10 2015/04/13 15:43:43 riastradh Exp $ */ |
2 | /* $OpenBSD: ubsecvar.h,v 1.38 2009/03/27 13:31:30 reyk Exp $ */ |
3 | |
4 | /* |
5 | * Copyright (c) 2000 Theo de Raadt |
6 | * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) |
7 | * |
8 | * Redistribution and use in source and binary forms, with or without |
9 | * modification, are permitted provided that the following conditions |
10 | * are met: |
11 | * |
12 | * 1. Redistributions of source code must retain the above copyright |
13 | * notice, this list of conditions and the following disclaimer. |
14 | * 2. Redistributions in binary form must reproduce the above copyright |
15 | * notice, this list of conditions and the following disclaimer in the |
16 | * documentation and/or other materials provided with the distribution. |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | * |
29 | * Effort sponsored in part by the Defense Advanced Research Projects |
30 | * Agency (DARPA) and Air Force Research Laboratory, Air Force |
31 | * Materiel Command, USAF, under agreement number F30602-01-2-0537. |
32 | * |
33 | */ |
34 | |
35 | #ifndef _DEV_PCI_UBSECVAR_H |
36 | #define _DEV_PCI_UBSECVAR_H |
37 | |
38 | #include <sys/types.h> |
39 | #include <sys/rndsource.h> |
40 | |
41 | /* Maximum queue length */ |
42 | #ifndef UBS_MAX_NQUEUE |
43 | #define UBS_MAX_NQUEUE 60 |
44 | #endif |
45 | |
46 | #define UBS_MAX_SCATTER 64 /* Maximum scatter/gather depth */ |
47 | |
48 | #ifndef UBS_MAX_AGGR |
49 | #define UBS_MAX_AGGR 17 /* Maximum aggregation count */ |
50 | #endif |
51 | |
52 | #ifndef UBS_MIN_AGGR |
53 | #define UBS_MIN_AGGR 5 /* < 5827, Maximum aggregation count */ |
54 | #endif |
55 | |
56 | #define UBSEC_CARD(sid) (((sid) & 0xf0000000) >> 28) |
57 | #define UBSEC_SESSION(sid) ( (sid) & 0x0fffffff) |
58 | #define UBSEC_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) |
59 | |
60 | #define UBS_DEF_RTY 0xff /* PCI Retry Timeout */ |
61 | #define UBS_DEF_TOUT 0xff /* PCI TRDY Timeout */ |
62 | #define UBS_DEF_CACHELINE 0x01 /* Cache Line setting */ |
63 | |
64 | struct ubsec_dma_alloc { |
65 | u_int32_t dma_paddr; |
66 | void * dma_vaddr; |
67 | bus_dmamap_t dma_map; |
68 | bus_dma_segment_t dma_seg; |
69 | bus_size_t dma_size; |
70 | int dma_nseg; |
71 | }; |
72 | |
73 | struct ubsec_q2 { |
74 | SIMPLEQ_ENTRY(ubsec_q2) q_next; |
75 | struct ubsec_dma_alloc q_mcr; |
76 | struct ubsec_dma_alloc q_ctx; |
77 | u_int q_type; |
78 | }; |
79 | |
80 | struct ubsec_q2_rng { |
81 | struct ubsec_q2 rng_q; |
82 | struct ubsec_dma_alloc rng_buf; |
83 | int rng_used; |
84 | }; |
85 | |
86 | /* C = (M ^ E) mod N */ |
87 | #define UBS_MODEXP_PAR_M 0 |
88 | #define UBS_MODEXP_PAR_E 1 |
89 | #define UBS_MODEXP_PAR_N 2 |
90 | struct ubsec_q2_modexp { |
91 | struct ubsec_q2 me_q; |
92 | struct cryptkop * me_krp; |
93 | struct ubsec_dma_alloc me_M; |
94 | struct ubsec_dma_alloc me_E; |
95 | struct ubsec_dma_alloc me_C; |
96 | struct ubsec_dma_alloc me_epb; |
97 | int me_modbits; |
98 | int me_shiftbits; |
99 | int me_normbits; |
100 | }; |
101 | |
102 | #define UBS_RSAPRIV_PAR_P 0 |
103 | #define UBS_RSAPRIV_PAR_Q 1 |
104 | #define UBS_RSAPRIV_PAR_DP 2 |
105 | #define UBS_RSAPRIV_PAR_DQ 3 |
106 | #define UBS_RSAPRIV_PAR_PINV 4 |
107 | #define UBS_RSAPRIV_PAR_MSGIN 5 |
108 | #define UBS_RSAPRIV_PAR_MSGOUT 6 |
109 | struct ubsec_q2_rsapriv { |
110 | struct ubsec_q2 rpr_q; |
111 | struct cryptkop * rpr_krp; |
112 | struct ubsec_dma_alloc rpr_msgin; |
113 | struct ubsec_dma_alloc rpr_msgout; |
114 | }; |
115 | |
116 | #define UBSEC_RNG_BUFSIZ 16 /* measured in 32bit words */ |
117 | |
118 | struct ubsec_dmachunk { |
119 | struct ubsec_mcr d_mcr; |
120 | struct ubsec_mcr_add d_mcradd[UBS_MAX_AGGR-1]; |
121 | struct ubsec_pktbuf d_sbuf[UBS_MAX_SCATTER-1]; |
122 | struct ubsec_pktbuf d_dbuf[UBS_MAX_SCATTER-1]; |
123 | u_int32_t d_macbuf[5]; |
124 | union { |
125 | struct ubsec_pktctx_aes256 ctx_aes256; |
126 | struct ubsec_pktctx_aes192 ctx_aes192; |
127 | struct ubsec_pktctx_aes128 ctx_aes128; |
128 | struct ubsec_pktctx_3des ctx_3des; |
129 | struct ubsec_pktctx ctx; |
130 | } d_ctx; |
131 | }; |
132 | |
133 | struct ubsec_dma { |
134 | SIMPLEQ_ENTRY(ubsec_dma) d_next; |
135 | struct ubsec_dmachunk *d_dma; |
136 | struct ubsec_dma_alloc d_alloc; |
137 | }; |
138 | |
139 | #define UBS_FLAGS_KEY 0x01 /* has key accelerator */ |
140 | #define UBS_FLAGS_LONGCTX 0x02 /* uses long ipsec ctx */ |
141 | #define UBS_FLAGS_BIGKEY 0x04 /* 2048bit keys */ |
142 | #define UBS_FLAGS_HWNORM 0x08 /* hardware normalization */ |
143 | #define UBS_FLAGS_RNG 0x10 /* hardware rng */ |
144 | #define UBS_FLAGS_AES 0x20 /* supports AES */ |
145 | #define UBS_FLAGS_MULTIMCR 0x40 /* 5827+ with 4 MCRs */ |
146 | #define UBS_FLAGS_RNG4 0x80 /* 5827+ RNG on MCR4 */ |
147 | |
148 | struct ubsec_q { |
149 | SIMPLEQ_ENTRY(ubsec_q) q_next; |
150 | int q_nstacked_mcrs; |
151 | struct ubsec_q *q_stacked_mcr[UBS_MAX_AGGR-1]; |
152 | struct cryptop *q_crp; |
153 | struct ubsec_dma *q_dma; |
154 | |
155 | struct mbuf *q_src_m, *q_dst_m; |
156 | struct uio *q_src_io, *q_dst_io; |
157 | |
158 | int q_sesn; |
159 | int q_flags; |
160 | |
161 | bus_dmamap_t q_dst_map; |
162 | bus_dmamap_t q_src_map; /* cached src_map */ |
163 | bus_dmamap_t q_cached_dst_map; /* cached dst_map */ |
164 | }; |
165 | |
166 | struct ubsec_softc { |
167 | device_t sc_dev; /* generic device */ |
168 | void *sc_ih; /* interrupt handler cookie */ |
169 | kmutex_t sc_mtx; |
170 | pci_chipset_tag_t sc_pct; /* pci chipset tag */ |
171 | bus_space_handle_t sc_sh; /* memory handle */ |
172 | bus_space_tag_t sc_st; /* memory tag */ |
173 | bus_dma_tag_t sc_dmat; /* dma tag */ |
174 | int sc_flags; /* device specific flags */ |
175 | int sc_suspended; |
176 | int sc_needwakeup; /* notify crypto layer */ |
177 | u_int32_t sc_statmask; /* interrupt status mask */ |
178 | int32_t sc_cid; /* crypto tag */ |
179 | int sc_maxaggr; /* max pkt aggregation */ |
180 | SIMPLEQ_HEAD(,ubsec_q) sc_queue; /* packet queue, mcr1 */ |
181 | int sc_nqueue; /* count enqueued, mcr1 */ |
182 | SIMPLEQ_HEAD(,ubsec_q) sc_qchip; /* on chip, mcr1 */ |
183 | int sc_nqchip; /* count on chip, mcr1 */ |
184 | SIMPLEQ_HEAD(,ubsec_q) sc_freequeue; /* list of free queue elements */ |
185 | SIMPLEQ_HEAD(,ubsec_q2) sc_queue2; /* packet queue, mcr2 */ |
186 | int sc_nqueue2; /* count enqueued, mcr2 */ |
187 | SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2; /* on chip, mcr2 */ |
188 | SIMPLEQ_HEAD(,ubsec_q2) sc_queue4; /* packet queue, mcr4 */ |
189 | int sc_nqueue4; /* count enqueued, mcr4 */ |
190 | SIMPLEQ_HEAD(,ubsec_q2) sc_qchip4; /* on chip, mcr4 */ |
191 | int sc_nsessions; /* # of sessions */ |
192 | struct ubsec_session *sc_sessions; /* sessions */ |
193 | struct callout sc_rngto; /* rng timeout */ |
194 | int sc_rnghz; /* rng poll time */ |
195 | struct ubsec_q2_rng sc_rng; |
196 | krndsource_t sc_rnd_source; |
197 | int sc_rng_need; /* how many bytes wanted */ |
198 | struct ubsec_dma sc_dmaa[UBS_MAX_NQUEUE]; |
199 | struct ubsec_q *sc_queuea[UBS_MAX_NQUEUE]; |
200 | SIMPLEQ_HEAD(,ubsec_q2) sc_q2free; /* free list */ |
201 | bus_size_t sc_memsize; /* size mapped by sc_sh */ |
202 | }; |
203 | |
204 | #define UBSEC_QFLAGS_COPYOUTIV 0x1 |
205 | |
206 | struct ubsec_session { |
207 | u_int32_t ses_used; |
208 | u_int32_t ses_key[8]; /* 3DES/AES key */ |
209 | u_int32_t ses_hminner[5]; /* hmac inner state */ |
210 | u_int32_t ses_hmouter[5]; /* hmac outer state */ |
211 | u_int32_t ses_iv[4]; /* [3]DES iv or AES iv/icv */ |
212 | }; |
213 | |
214 | struct ubsec_stats { |
215 | u_int64_t hst_ibytes; |
216 | u_int64_t hst_obytes; |
217 | u_int32_t hst_ipackets; |
218 | u_int32_t hst_opackets; |
219 | u_int32_t hst_invalid; /* invalid argument */ |
220 | u_int32_t hst_badsession; /* invalid session id */ |
221 | u_int32_t hst_badflags; /* flags indicate !(mbuf | uio) */ |
222 | u_int32_t hst_nodesc; /* op submitted w/o descriptors */ |
223 | u_int32_t hst_badalg; /* unsupported algorithm */ |
224 | |
225 | u_int32_t hst_nomem; |
226 | u_int32_t hst_queuefull; |
227 | u_int32_t hst_dmaerr; |
228 | u_int32_t hst_mcrerr; |
229 | u_int32_t hst_nodmafree; |
230 | |
231 | u_int32_t hst_lenmismatch; /* enc/auth lengths different */ |
232 | u_int32_t hst_skipmismatch; /* enc part begins before auth part */ |
233 | u_int32_t hst_iovmisaligned; /* iov op not aligned */ |
234 | u_int32_t hst_noirq; /* IRQ for no reason */ |
235 | u_int32_t hst_unaligned; /* unaligned src caused copy */ |
236 | u_int32_t hst_nomap; /* bus_dmamap_create failed */ |
237 | u_int32_t hst_noload; /* bus_dmamap_load_* failed */ |
238 | u_int32_t hst_nombuf; /* MGET* failed */ |
239 | u_int32_t hst_nomcl; /* MCLGET* failed */ |
240 | u_int32_t hst_totbatch; /* ops submitted w/o interrupt */ |
241 | u_int32_t hst_maxbatch; /* max ops submitted together */ |
242 | u_int32_t hst_maxqueue; /* max ops queued for submission */ |
243 | u_int32_t hst_maxqchip; /* max mcr1 ops out for processing */ |
244 | u_int32_t hst_mcr1full; /* MCR1 too busy to take ops */ |
245 | u_int32_t hst_rng; /* RNG requests */ |
246 | u_int32_t hst_modexp; /* MOD EXP requests */ |
247 | u_int32_t hst_modexpcrt; /* MOD EXP CRT requests */ |
248 | }; |
249 | |
250 | #endif /* _DEV_PCI_UBSECVAR_H */ |
251 | |