1/* $NetBSD: nouveau_subdev_clock_nva3.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $ */
2
3/*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26
27#include <sys/cdefs.h>
28__KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_clock_nva3.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $");
29
30#include <subdev/bios.h>
31#include <subdev/bios/pll.h>
32#include <subdev/timer.h>
33
34#include "pll.h"
35
36#include "nva3.h"
37
38struct nva3_clock_priv {
39 struct nouveau_clock base;
40 struct nva3_clock_info eng[nv_clk_src_max];
41};
42
43static u32 read_clk(struct nva3_clock_priv *, int, bool);
44static u32 read_pll(struct nva3_clock_priv *, int, u32);
45
46static u32
47read_vco(struct nva3_clock_priv *priv, int clk)
48{
49 u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
50 if ((sctl & 0x00000030) != 0x00000030)
51 return read_pll(priv, 0x41, 0x00e820);
52 return read_pll(priv, 0x42, 0x00e8a0);
53}
54
55static u32
56read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
57{
58 u32 sctl, sdiv, sclk;
59
60 /* refclk for the 0xe8xx plls is a fixed frequency */
61 if (clk >= 0x40) {
62 if (nv_device(priv)->chipset == 0xaf) {
63 /* no joke.. seriously.. sigh.. */
64 return nv_rd32(priv, 0x00471c) * 1000;
65 }
66
67 return nv_device(priv)->crystal;
68 }
69
70 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
71 if (!ignore_en && !(sctl & 0x00000100))
72 return 0;
73
74 switch (sctl & 0x00003000) {
75 case 0x00000000:
76 return nv_device(priv)->crystal;
77 case 0x00002000:
78 if (sctl & 0x00000040)
79 return 108000;
80 return 100000;
81 case 0x00003000:
82 sclk = read_vco(priv, clk);
83 sdiv = ((sctl & 0x003f0000) >> 16) + 2;
84 return (sclk * 2) / sdiv;
85 default:
86 return 0;
87 }
88}
89
90static u32
91read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
92{
93 u32 ctrl = nv_rd32(priv, pll + 0);
94 u32 sclk = 0, P = 1, N = 1, M = 1;
95
96 if (!(ctrl & 0x00000008)) {
97 if (ctrl & 0x00000001) {
98 u32 coef = nv_rd32(priv, pll + 4);
99 M = (coef & 0x000000ff) >> 0;
100 N = (coef & 0x0000ff00) >> 8;
101 P = (coef & 0x003f0000) >> 16;
102
103 /* no post-divider on these.. */
104 if ((pll & 0x00ff00) == 0x00e800)
105 P = 1;
106
107 sclk = read_clk(priv, 0x00 + clk, false);
108 }
109 } else {
110 sclk = read_clk(priv, 0x10 + clk, false);
111 }
112
113 if (M * P)
114 return sclk * N / (M * P);
115 return 0;
116}
117
118static int
119nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
120{
121 struct nva3_clock_priv *priv = (void *)clk;
122
123 switch (src) {
124 case nv_clk_src_crystal:
125 return nv_device(priv)->crystal;
126 case nv_clk_src_href:
127 return 100000;
128 case nv_clk_src_core:
129 return read_pll(priv, 0x00, 0x4200);
130 case nv_clk_src_shader:
131 return read_pll(priv, 0x01, 0x4220);
132 case nv_clk_src_mem:
133 return read_pll(priv, 0x02, 0x4000);
134 case nv_clk_src_disp:
135 return read_clk(priv, 0x20, false);
136 case nv_clk_src_vdec:
137 return read_clk(priv, 0x21, false);
138 case nv_clk_src_daemon:
139 return read_clk(priv, 0x25, false);
140 default:
141 nv_error(clk, "invalid clock source %d\n", src);
142 return -EINVAL;
143 }
144}
145
146int
147nva3_clock_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
148 struct nva3_clock_info *info)
149{
150 struct nouveau_bios *bios = nouveau_bios(clock);
151 struct nva3_clock_priv *priv = (void *)clock;
152 struct nvbios_pll limits;
153 u32 oclk, sclk, sdiv;
154 int P, N, M, diff;
155 int ret;
156
157 info->pll = 0;
158 info->clk = 0;
159
160 switch (khz) {
161 case 27000:
162 info->clk = 0x00000100;
163 return khz;
164 case 100000:
165 info->clk = 0x00002100;
166 return khz;
167 case 108000:
168 info->clk = 0x00002140;
169 return khz;
170 default:
171 sclk = read_vco(priv, clk);
172 sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
173 /* if the clock has a PLL attached, and we can get a within
174 * [-2, 3) MHz of a divider, we'll disable the PLL and use
175 * the divider instead.
176 *
177 * divider can go as low as 2, limited here because NVIDIA
178 * and the VBIOS on my NVA8 seem to prefer using the PLL
179 * for 810MHz - is there a good reason?
180 */
181 if (sdiv > 4) {
182 oclk = (sclk * 2) / sdiv;
183 diff = khz - oclk;
184 if (!pll || (diff >= -2000 && diff < 3000)) {
185 info->clk = (((sdiv - 2) << 16) | 0x00003100);
186 return oclk;
187 }
188 }
189
190 if (!pll)
191 return -ERANGE;
192 break;
193 }
194
195 ret = nvbios_pll_parse(bios, pll, &limits);
196 if (ret)
197 return ret;
198
199 limits.refclk = read_clk(priv, clk - 0x10, true);
200 if (!limits.refclk)
201 return -EINVAL;
202
203 ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
204 if (ret >= 0) {
205 info->clk = nv_rd32(priv, 0x4120 + (clk * 4));
206 info->pll = (P << 16) | (N << 8) | M;
207 }
208
209 return ret ? ret : -ERANGE;
210}
211
212static int
213calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate,
214 int clk, u32 pll, int idx)
215{
216 int ret = nva3_clock_info(&priv->base, clk, pll, cstate->domain[idx],
217 &priv->eng[idx]);
218 if (ret >= 0)
219 return 0;
220 return ret;
221}
222
223static void
224prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
225{
226 struct nva3_clock_info *info = &priv->eng[idx];
227 const u32 src0 = 0x004120 + (clk * 4);
228 const u32 src1 = 0x004160 + (clk * 4);
229 const u32 ctrl = pll + 0;
230 const u32 coef = pll + 4;
231
232 if (info->pll) {
233 nv_mask(priv, src0, 0x00000101, 0x00000101);
234 nv_wr32(priv, coef, info->pll);
235 nv_mask(priv, ctrl, 0x00000015, 0x00000015);
236 nv_mask(priv, ctrl, 0x00000010, 0x00000000);
237 nv_wait(priv, ctrl, 0x00020000, 0x00020000);
238 nv_mask(priv, ctrl, 0x00000010, 0x00000010);
239 nv_mask(priv, ctrl, 0x00000008, 0x00000000);
240 nv_mask(priv, src1, 0x00000100, 0x00000000);
241 nv_mask(priv, src1, 0x00000001, 0x00000000);
242 } else {
243 nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk);
244 nv_mask(priv, ctrl, 0x00000018, 0x00000018);
245 udelay(20);
246 nv_mask(priv, ctrl, 0x00000001, 0x00000000);
247 nv_mask(priv, src0, 0x00000100, 0x00000000);
248 nv_mask(priv, src0, 0x00000001, 0x00000000);
249 }
250}
251
252static void
253prog_clk(struct nva3_clock_priv *priv, int clk, int idx)
254{
255 struct nva3_clock_info *info = &priv->eng[idx];
256 nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk);
257}
258
259static int
260nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
261{
262 struct nva3_clock_priv *priv = (void *)clk;
263 int ret;
264
265 if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
266 (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) ||
267 (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) ||
268 (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)))
269 return ret;
270
271 return 0;
272}
273
274static int
275nva3_clock_prog(struct nouveau_clock *clk)
276{
277 struct nva3_clock_priv *priv = (void *)clk;
278 prog_pll(priv, 0x00, 0x004200, nv_clk_src_core);
279 prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
280 prog_clk(priv, 0x20, nv_clk_src_disp);
281 prog_clk(priv, 0x21, nv_clk_src_vdec);
282 return 0;
283}
284
285static void
286nva3_clock_tidy(struct nouveau_clock *clk)
287{
288}
289
290static struct nouveau_clocks
291nva3_domain[] = {
292 { nv_clk_src_crystal, 0xff },
293 { nv_clk_src_href , 0xff },
294 { nv_clk_src_core , 0x00, 0, "core", 1000 },
295 { nv_clk_src_shader , 0x01, 0, "shader", 1000 },
296 { nv_clk_src_mem , 0x02, 0, "memory", 1000 },
297 { nv_clk_src_vdec , 0x03 },
298 { nv_clk_src_disp , 0x04 },
299 { nv_clk_src_max }
300};
301
302static int
303nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
304 struct nouveau_oclass *oclass, void *data, u32 size,
305 struct nouveau_object **pobject)
306{
307 struct nva3_clock_priv *priv;
308 int ret;
309
310 ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, &priv);
311 *pobject = nv_object(priv);
312 if (ret)
313 return ret;
314
315 priv->base.read = nva3_clock_read;
316 priv->base.calc = nva3_clock_calc;
317 priv->base.prog = nva3_clock_prog;
318 priv->base.tidy = nva3_clock_tidy;
319 return 0;
320}
321
322struct nouveau_oclass
323nva3_clock_oclass = {
324 .handle = NV_SUBDEV(CLOCK, 0xa3),
325 .ofuncs = &(struct nouveau_ofuncs) {
326 .ctor = nva3_clock_ctor,
327 .dtor = _nouveau_clock_dtor,
328 .init = _nouveau_clock_init,
329 .fini = _nouveau_clock_fini,
330 },
331};
332