1/* $NetBSD: arn5008reg.h,v 1.1 2013/03/30 02:53:00 christos Exp $ */
2/* $OpenBSD: ar5008reg.h,v 1.3 2010/12/31 17:50:48 damien Exp $ */
3
4/*-
5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
6 * Copyright (c) 2008-2009 Atheros Communications Inc.
7 *
8 * Permission to use, copy, modify, and/or distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21#ifndef _ARN5008REG_H_
22#define _ARN5008REG_H_
23
24/*
25 * MAC registers.
26 */
27#define AR_ISR_S2_S 0x00cc
28#define AR_ISR_S3_S 0x00d0
29#define AR_ISR_S4_S 0x00d4
30#define AR_ISR_S5_S 0x00d8
31#define AR_GPIO_IN_OUT 0x4048
32#define AR_GPIO_OE_OUT 0x404c
33#define AR_GPIO_INTR_POL 0x4050
34#define AR_GPIO_INPUT_EN_VAL 0x4054
35#define AR_GPIO_INPUT_MUX1 0x4058
36#define AR_GPIO_INPUT_MUX2 0x405c
37#define AR_GPIO_OUTPUT_MUX(i) (0x4060 + (i) * 4)
38#define AR_INPUT_STATE 0x406c
39#define AR_EEPROM_STATUS_DATA 0x407c
40#define AR_OBS 0x4080
41#define AR_GPIO_PDPU 0x4088
42#define AR_PCIE_MSI 0x4094
43
44/*
45 * Analog registers.
46 */
47#define AR_IS_ANALOG_REG(reg) ((reg) >= 0x7800 && (reg) <= 0x78b4)
48#define AR_AN_RF2G1_CH0 0x7810
49#define AR_AN_RF5G1_CH0 0x7818
50#define AR_AN_RF2G1_CH1 0x7834
51#define AR_AN_RF5G1_CH1 0x783c
52#define AR_AN_SYNTH9 0x7868
53#define AR_AN_TOP1 0x7890
54#define AR_AN_TOP2 0x7894
55
56/*
57 * PHY registers.
58 */
59#define AR_PHY_BASE 0x9800
60#define AR_PHY(i) (AR_PHY_BASE + (i) * 4)
61#define AR_PHY_TEST 0x9800
62#define AR_PHY_TURBO 0x9804
63#define AR_PHY_TEST2 0x9808
64#define AR_PHY_TIMING2 0x9810
65#define AR_PHY_TIMING3 0x9814
66#define AR_PHY_CHIP_ID 0x9818
67#define AR_PHY_ACTIVE 0x981c
68#define AR_PHY_RF_CTL2 0x9824
69#define AR_PHY_RF_CTL3 0x9828
70#define AR_PHY_ADC_CTL 0x982c
71#define AR_PHY_ADC_SERIAL_CTL 0x9830
72#define AR_PHY_RF_CTL4 0x9834
73#define AR_PHY_TSTDAC_CONST 0x983c
74#define AR_PHY_SETTLING 0x9844
75#define AR_PHY_RXGAIN 0x9848
76#define AR_PHY_DESIRED_SZ 0x9850
77#define AR_PHY_FIND_SIG 0x9858
78#define AR_PHY_AGC_CTL1 0x985c
79#define AR_PHY_AGC_CONTROL 0x9860
80#define AR_PHY_CCA(i) (0x9864 + (i) * 0x1000)
81#define AR_PHY_SFCORR 0x9868
82#define AR_PHY_SFCORR_LOW 0x986c
83#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
84#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
85#define AR_PHY_SLEEP_SCAL 0x9878
86#define AR_PHY_PLL_CTL 0x987c
87#define AR_PHY_BIN_MASK_1 0x9900
88#define AR_PHY_BIN_MASK_2 0x9904
89#define AR_PHY_BIN_MASK_3 0x9908
90#define AR_PHY_MASK_CTL 0x990c
91#define AR_PHY_RX_DELAY 0x9914
92#define AR_PHY_SEARCH_START_DELAY 0x9918
93#define AR_PHY_TIMING_CTRL4_0 0x9920
94#define AR_PHY_TIMING_CTRL4(i) (0x9920 + (i) * 0x1000)
95#define AR_PHY_TIMING5 0x9924
96#define AR_PHY_POWER_TX_RATE1 0x9934
97#define AR_PHY_POWER_TX_RATE2 0x9938
98#define AR_PHY_POWER_TX_RATE_MAX 0x993c
99#define AR_PHY_RADAR_EXT 0x9940
100#define AR_PHY_FRAME_CTL 0x9944
101#define AR_PHY_SPUR_REG 0x994c
102#define AR_PHY_RADAR_0 0x9954
103#define AR_PHY_RADAR_1 0x9958
104#define AR_PHY_SWITCH_CHAIN_0 0x9960
105#define AR_PHY_SWITCH_COM 0x9964
106#define AR_PHY_SIGMA_DELTA 0x996c
107#define AR_PHY_RESTART 0x9970
108#define AR_PHY_RFBUS_REQ 0x997c
109#define AR_PHY_TIMING7 0x9980
110#define AR_PHY_TIMING8 0x9984
111#define AR_PHY_BIN_MASK2_1 0x9988
112#define AR_PHY_BIN_MASK2_2 0x998c
113#define AR_PHY_BIN_MASK2_3 0x9990
114#define AR_PHY_BIN_MASK2_4 0x9994
115#define AR_PHY_TIMING9 0x9998
116#define AR_PHY_TIMING10 0x999c
117#define AR_PHY_TIMING11 0x99a0
118#define AR_PHY_RX_CHAINMASK 0x99a4
119#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
120#define AR_PHY_NEW_ADC_DC_GAIN_CORR(i) (0x99b4 + (i) * 0x1000)
121#define AR_PHY_EXT_CCA0 0x99b8
122#define AR_PHY_EXT_CCA(i) (0x99bc + (i) * 0x1000)
123#define AR_PHY_SFCORR_EXT 0x99c0
124#define AR_PHY_HALFGI 0x99d0
125#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
126#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
127#define AR_PHY_CHAN_INFO_MEMORY 0x99dc
128#define AR_PHY_HEAVY_CLIP_ENABLE 0x99e0
129#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99ec
130#define AR_PHY_CALMODE 0x99f0
131#define AR_PHY_REFCLKDLY 0x99f4
132#define AR_PHY_REFCLKPD 0x99f8
133#define AR_PHY_BB_RFGAIN(i) (0x9a00 + (i) * 4)
134#define AR_PHY_CAL_MEAS_0(i) (0x9c10 + (i) * 0x1000)
135#define AR_PHY_CAL_MEAS_1(i) (0x9c14 + (i) * 0x1000)
136#define AR_PHY_CAL_MEAS_2(i) (0x9c18 + (i) * 0x1000)
137#define AR_PHY_CAL_MEAS_3(i) (0x9c1c + (i) * 0x1000)
138#define AR_PHY_CURRENT_RSSI 0x9c1c
139#define AR_PHY_RFBUS_GRANT 0x9c20
140#define AR9280_PHY_CURRENT_RSSI 0x9c3c
141#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9cf4
142#define AR_PHY_CHAN_INFO_GAIN 0x9cfc
143#define AR_PHY_MODE 0xa200
144#define AR_PHY_CCK_TX_CTRL 0xa204
145#define AR_PHY_CCK_DETECT 0xa208
146#define AR_PHY_GAIN_2GHZ 0xa20c
147#define AR_PHY_CCK_RXCTRL4 0xa21c
148#define AR_PHY_DAG_CTRLCCK 0xa228
149#define AR_PHY_FORCE_CLKEN_CCK 0xa22c
150#define AR_PHY_POWER_TX_RATE3 0xa234
151#define AR_PHY_POWER_TX_RATE4 0xa238
152#define AR_PHY_SCRM_SEQ_XR 0xa23c
153#define AR_PHY_HEADER_DETECT_XR 0xa240
154#define AR_PHY_CHIRP_DETECTED_XR 0xa244
155#define AR_PHY_BLUETOOTH 0xa254
156#define AR_PHY_TPCRG1 0xa258
157#define AR_PHY_TX_PWRCTRL4 0xa264
158#define AR_PHY_ANALOG_SWAP 0xa268
159#define AR_PHY_TPCRG5 0xa26c
160#define AR_PHY_TX_PWRCTRL6_0 0xa270
161#define AR_PHY_TX_PWRCTRL7 0xa274
162#define AR_PHY_TX_PWRCTRL9 0xa27c
163#define AR_PHY_PDADC_TBL_BASE 0xa280
164#define AR_PHY_TX_GAIN_TBL(i) (0xa300 + (i) * 4)
165#define AR_PHY_CL_CAL_CTL 0xa358
166#define AR_PHY_CLC_TBL(i) (0xa35c + (i) * 4)
167#define AR_PHY_POWER_TX_RATE5 0xa38c
168#define AR_PHY_POWER_TX_RATE6 0xa390
169#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
170#define AR_PHY_CAL_CHAINMASK 0xa39c
171#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
172#define AR_PHY_VIT_MASK2_M_31_45 0xa3a4
173#define AR_PHY_VIT_MASK2_M_16_30 0xa3a8
174#define AR_PHY_VIT_MASK2_M_00_15 0xa3ac
175#define AR_PHY_PILOT_MASK_01_30 0xa3b0
176#define AR_PHY_PILOT_MASK_31_60 0xa3b4
177#define AR_PHY_VIT_MASK2_P_15_01 0xa3b8
178#define AR_PHY_VIT_MASK2_P_30_16 0xa3bc
179#define AR_PHY_VIT_MASK2_P_45_31 0xa3c0
180#define AR_PHY_VIT_MASK2_P_61_46 0xa3c4
181#define AR_PHY_POWER_TX_SUB 0xa3c8
182#define AR_PHY_POWER_TX_RATE7 0xa3cc
183#define AR_PHY_POWER_TX_RATE8 0xa3d0
184#define AR_PHY_POWER_TX_RATE9 0xa3d4
185#define AR_PHY_XPA_CFG 0xa3d8
186#define AR_PHY_TX_PWRCTRL6_1 0xb270
187#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
188
189/*
190 * AR7010 registers.
191 */
192#define AR7010_GPIO_OE 0x52000
193#define AR7010_GPIO_IN 0x52004
194#define AR7010_GPIO_OUT 0x52008
195
196
197/* Bits for AR_AN_RF2G1_CH0. */
198#define AR_AN_RF2G1_CH0_OB_M 0x03800000
199#define AR_AN_RF2G1_CH0_OB_S 23
200#define AR_AN_RF2G1_CH0_DB_M 0x1c000000
201#define AR_AN_RF2G1_CH0_DB_S 26
202
203/* Bits for AR_AN_RF5G1_CH0. */
204#define AR_AN_RF5G1_CH0_OB5_M 0x00070000
205#define AR_AN_RF5G1_CH0_OB5_S 16
206#define AR_AN_RF5G1_CH0_DB5_M 0x00380000
207#define AR_AN_RF5G1_CH0_DB5_S 19
208
209/* Bits for AR_AN_RF2G1_CH1. */
210#define AR_AN_RF2G1_CH1_OB_M 0x03800000
211#define AR_AN_RF2G1_CH1_OB_S 23
212#define AR_AN_RF2G1_CH1_DB_M 0x1c000000
213#define AR_AN_RF2G1_CH1_DB_S 26
214
215/* Bits for AR_AN_RF5G1_CH1. */
216#define AR_AN_RF5G1_CH1_OB5_M 0x00070000
217#define AR_AN_RF5G1_CH1_OB5_S 16
218#define AR_AN_RF5G1_CH1_DB5_M 0x00380000
219#define AR_AN_RF5G1_CH1_DB5_S 19
220
221/* Bits for AR_AN_SYNTH9. */
222#define AR_AN_SYNTH9_REFDIVA_M 0xf8000000
223#define AR_AN_SYNTH9_REFDIVA_S 27
224
225/* Bits for AR_AN_TOP1. */
226#define AR_AN_TOP1_DACLPMODE 0x00040000
227
228/* Bits for AR_AN_TOP2. */
229#define AR_AN_TOP2_XPABIAS_LVL_M 0xc0000000
230#define AR_AN_TOP2_XPABIAS_LVL_S 30
231#define AR_AN_TOP2_LOCALBIAS 0x00200000
232#define AR_AN_TOP2_PWDCLKIND 0x00400000
233
234/* Bits for AR_PHY_TEST. */
235#define AR_PHY_TEST_RFSILENT_BB 0x00002000
236#define AR_PHY_TEST_AGC_CLR 0x10000000
237
238/* Bits for AR_PHY_TURBO. */
239#define AR_PHY_FC_TURBO_MODE 0x00000001
240#define AR_PHY_FC_TURBO_SHORT 0x00000002
241#define AR_PHY_FC_DYN2040_EN 0x00000004
242#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
243#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
244#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
245#define AR_PHY_FC_HT_EN 0x00000040
246#define AR_PHY_FC_SHORT_GI_40 0x00000080
247#define AR_PHY_FC_WALSH 0x00000100
248#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
249#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
250
251/* Bits for AR_PHY_TIMING3. */
252#define AR_PHY_TIMING3_DSC_MAN_M 0xfffe0000
253#define AR_PHY_TIMING3_DSC_MAN_S 17
254#define AR_PHY_TIMING3_DSC_EXP_M 0x0001e000
255#define AR_PHY_TIMING3_DSC_EXP_S 13
256
257/* Bits for AR_PHY_CHIP_ID. */
258#define AR_PHY_CHIP_ID_REV_0 0x00000080
259#define AR_PHY_CHIP_ID_REV_1 0x00000081
260#define AR_PHY_CHIP_ID_9160_REV_0 0x000000b0
261
262/* Bits for AR_PHY_ACTIVE. */
263#define AR_PHY_ACTIVE_EN 0x00000001
264#define AR_PHY_ACTIVE_DIS 0x00000000
265
266/* Bits for AR_PHY_RF_CTL2. */
267#define AR_PHY_TX_END_DATA_START_M 0x000000ff
268#define AR_PHY_TX_END_DATA_START_S 0
269#define AR_PHY_TX_END_PA_ON_M 0x0000ff00
270#define AR_PHY_TX_END_PA_ON_S 8
271
272/* Bits for AR_PHY_RF_CTL3. */
273#define AR_PHY_TX_END_TO_A2_RX_ON_M 0x00ff0000
274#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
275
276/* Bits for AR_PHY_ADC_CTL. */
277#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_M 0x00000003
278#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
279#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
280#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
281#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
282#define AR_PHY_ADC_CTL_ON_INBUFGAIN_M 0x00030000
283#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
284
285/* Bits for AR_PHY_ADC_SERIAL_CTL. */
286#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
287#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
288
289/* Bits for AR_PHY_RF_CTL4. */
290#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_M 0xff000000
291#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
292#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_M 0x00ff0000
293#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
294#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_M 0x0000ff00
295#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
296#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_M 0x000000ff
297#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
298
299/* Bits for AR_PHY_SETTLING. */
300#define AR_PHY_SETTLING_SWITCH_M 0x00003f80
301#define AR_PHY_SETTLING_SWITCH_S 7
302
303/* Bits for AR_PHY_RXGAIN. */
304#define AR_PHY_RXGAIN_TXRX_ATTEN_M 0x0003f000
305#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
306#define AR_PHY_RXGAIN_TXRX_RF_MAX_M 0x007c0000
307#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
308#define AR9280_PHY_RXGAIN_TXRX_ATTEN_M 0x00003f80
309#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
310#define AR9280_PHY_RXGAIN_TXRX_MARGIN_M 0x001fc000
311#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
312
313/* Bits for AR_PHY_DESIRED_SZ. */
314#define AR_PHY_DESIRED_SZ_ADC_M 0x000000ff
315#define AR_PHY_DESIRED_SZ_ADC_S 0
316#define AR_PHY_DESIRED_SZ_PGA_M 0x0000ff00
317#define AR_PHY_DESIRED_SZ_PGA_S 8
318#define AR_PHY_DESIRED_SZ_TOT_DES_M 0x0ff00000
319#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
320
321/* Bits for AR_PHY_FIND_SIG. */
322#define AR_PHY_FIND_SIG_FIRSTEP_M 0x0003f000
323#define AR_PHY_FIND_SIG_FIRSTEP_S 12
324#define AR_PHY_FIND_SIG_FIRPWR_M 0x03fc0000
325#define AR_PHY_FIND_SIG_FIRPWR_S 18
326
327/* Bits for AR_PHY_AGC_CTL1. */
328#define AR_PHY_AGC_CTL1_COARSE_LOW_M 0x00007f80
329#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
330#define AR_PHY_AGC_CTL1_COARSE_HIGH_M 0x003f8000
331#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
332
333/* Bits for AR_PHY_AGC_CONTROL. */
334#define AR_PHY_AGC_CONTROL_CAL 0x00000001
335#define AR_PHY_AGC_CONTROL_NF 0x00000002
336#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
337#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
338#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
339
340/* Bits for AR_PHY_CCA. */
341#define AR_PHY_MAXCCA_PWR_M 0x000001ff
342#define AR_PHY_MAXCCA_PWR_S 0
343#define AR_PHY_CCA_THRESH62_M 0x0007f000
344#define AR_PHY_CCA_THRESH62_S 12
345#define AR_PHY_MINCCA_PWR_M 0x0ff80000
346#define AR_PHY_MINCCA_PWR_S 19
347#define AR9280_PHY_CCA_THRESH62_M 0x000ff000
348#define AR9280_PHY_CCA_THRESH62_S 12
349#define AR9280_PHY_MINCCA_PWR_M 0x1ff00000
350#define AR9280_PHY_MINCCA_PWR_S 20
351
352/* Bits for AR_PHY_SFCORR_LOW. */
353#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
354#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_M 0x00003f00
355#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
356#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_M 0x001fc000
357#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
358#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_M 0x0fe00000
359#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
360
361/* Bits for AR_PHY_SFCORR. */
362#define AR_PHY_SFCORR_M2COUNT_THR_M 0x0000001f
363#define AR_PHY_SFCORR_M2COUNT_THR_S 0
364#define AR_PHY_SFCORR_M1_THRESH_M 0x00fe0000
365#define AR_PHY_SFCORR_M1_THRESH_S 17
366#define AR_PHY_SFCORR_M2_THRESH_M 0x7f000000
367#define AR_PHY_SFCORR_M2_THRESH_S 24
368
369/* Bits for AR_PHY_RX_DELAY. */
370#define AR_PHY_RX_DELAY_DELAY_M 0x00003fff
371#define AR_PHY_RX_DELAY_DELAY_S 0
372
373/* Bits for AR_PHY_TIMING_CTRL4_0. */
374#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_M 0x0000001f
375#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
376#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_M 0x000007e0
377#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
378#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x00000800
379#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_M 0x0000f000
380#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
381#define AR_PHY_TIMING_CTRL4_DO_CAL 0x00010000
382#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
383#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
384#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
385#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
386
387/* Bits for AR_PHY_TIMING5. */
388#define AR_PHY_TIMING5_CYCPWR_THR1_M 0x000000fe
389#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
390
391/* Bits for AR_PHY_POWER_TX_RATE_MAX. */
392#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
393
394/* Bits for AR_PHY_FRAME_CTL. */
395#define AR_PHY_FRAME_CTL_TX_CLIP_M 0x00000038
396#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
397
398/* Bits for AR_PHY_TXPWRADJ. */
399#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_M 0x00000fc0
400#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
401#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_M 0x00fc0000
402#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
403
404/* Bits for AR_PHY_RADAR_EXT. */
405#define AR_PHY_RADAR_EXT_ENA 0x00004000
406
407/* Bits for AR_PHY_RADAR_0. */
408#define AR_PHY_RADAR_0_ENA 0x00000001
409#define AR_PHY_RADAR_0_INBAND_M 0x0000003e
410#define AR_PHY_RADAR_0_INBAND_S 1
411#define AR_PHY_RADAR_0_PRSSI_M 0x00000fc0
412#define AR_PHY_RADAR_0_PRSSI_S 6
413#define AR_PHY_RADAR_0_HEIGHT_M 0x0003f000
414#define AR_PHY_RADAR_0_HEIGHT_S 12
415#define AR_PHY_RADAR_0_RRSSI_M 0x00fc0000
416#define AR_PHY_RADAR_0_RRSSI_S 18
417#define AR_PHY_RADAR_0_FIRPWR_M 0x7f000000
418#define AR_PHY_RADAR_0_FIRPWR_S 24
419#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
420
421/* Bits for AR_PHY_RADAR_1. */
422#define AR_PHY_RADAR_1_MAXLEN_M 0x000000ff
423#define AR_PHY_RADAR_1_MAXLEN_S 0
424#define AR_PHY_RADAR_1_RELSTEP_THRESH_M 0x00001f00
425#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
426#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
427#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
428#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
429#define AR_PHY_RADAR_1_RELPWR_THRESH_M 0x003f0000
430#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
431#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
432#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
433
434/* Bits for AR_PHY_SIGMA_DELTA. */
435#define AR_PHY_SIGMA_DELTA_ADC_SEL_M 0x00000003
436#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
437#define AR_PHY_SIGMA_DELTA_FILT2_M 0x000000f8
438#define AR_PHY_SIGMA_DELTA_FILT2_S 3
439#define AR_PHY_SIGMA_DELTA_FILT1_M 0x00001f00
440#define AR_PHY_SIGMA_DELTA_FILT1_S 8
441#define AR_PHY_SIGMA_DELTA_ADC_CLIP_M 0x01ffe000
442#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
443
444/* Bits for AR_PHY_RESTART. */
445#define AR_PHY_RESTART_DIV_GC_M 0x001c0000
446#define AR_PHY_RESTART_DIV_GC_S 18
447
448/* Bits for AR_PHY_RFBUS_REQ. */
449#define AR_PHY_RFBUS_REQ_EN 0x00000001
450
451/* Bits for AR_PHY_TIMING11. */
452#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_M 0x000fffff
453#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
454#define AR_PHY_TIMING11_SPUR_FREQ_SD_M 0x3ff00000
455#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
456#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
457#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
458
459/* Bits for AR_PHY_NEW_ADC_DC_GAIN_CORR(). */
460#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
461#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
462
463/* Bits for AR_PHY_EXT_CCA0. */
464#define AR_PHY_EXT_CCA0_THRESH62_M 0x000000ff
465#define AR_PHY_EXT_CCA0_THRESH62_S 0
466
467/* Bits for AR_PHY_EXT_CCA. */
468#define AR_PHY_EXT_MAXCCA_PWR_M 0x000001ff
469#define AR_PHY_EXT_MAXCCA_PWR_S 0
470#define AR_PHY_EXT_CCA_CYCPWR_THR1_M 0x0000fe00
471#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
472#define AR_PHY_EXT_CCA_THRESH62_M 0x007f0000
473#define AR_PHY_EXT_CCA_THRESH62_S 16
474#define AR_PHY_EXT_MINCCA_PWR_M 0xff800000
475#define AR_PHY_EXT_MINCCA_PWR_S 23
476#define AR9280_PHY_EXT_MINCCA_PWR_M 0x01ff0000
477#define AR9280_PHY_EXT_MINCCA_PWR_S 16
478
479/* Bits for AR_PHY_SFCORR_EXT. */
480#define AR_PHY_SFCORR_EXT_M1_THRESH_M 0x0000007f
481#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
482#define AR_PHY_SFCORR_EXT_M2_THRESH_M 0x00003f80
483#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
484#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_M 0x001fc000
485#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
486#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_M 0x0fe00000
487#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
488#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_M 0xf0000000
489#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
490
491/* Bits for AR_PHY_HALFGI. */
492#define AR_PHY_HALFGI_DSC_EXP_M 0x0000000f
493#define AR_PHY_HALFGI_DSC_EXP_S 0
494#define AR_PHY_HALFGI_DSC_MAN_M 0x0007fff0
495#define AR_PHY_HALFGI_DSC_MAN_S 4
496
497/* Bits for AR_PHY_CHAN_INFO_MEMORY. */
498#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x00000001
499
500/* Bits for AR_PHY_HEAVY_CLIP_FACTOR_RIFS. */
501#define AR_PHY_RIFS_INIT_DELAY_M 0x03ff0000
502#define AR_PHY_RIFS_INIT_DELAY_S 16
503
504/* Bits for AR_PHY_CALMODE. */
505#define AR_PHY_CALMODE_IQ 0x00000000
506#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
507#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
508#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
509
510/* Bits for AR_PHY_RFBUS_GRANT. */
511#define AR_PHY_RFBUS_GRANT_EN 0x00000001
512
513/* Bits for AR_PHY_CHAN_INFO_GAIN_DIFF. */
514#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
515
516/* Bits for AR_PHY_MODE. */
517#define AR_PHY_MODE_ASYNCFIFO 0x00000080
518#define AR_PHY_MODE_AR2133 0x00000008
519#define AR_PHY_MODE_AR5111 0x00000000
520#define AR_PHY_MODE_AR5112 0x00000008
521#define AR_PHY_MODE_DYNAMIC 0x00000004
522#define AR_PHY_MODE_RF2GHZ 0x00000002
523#define AR_PHY_MODE_RF5GHZ 0x00000000
524#define AR_PHY_MODE_CCK 0x00000001
525#define AR_PHY_MODE_OFDM 0x00000000
526#define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
527
528/* Bits for AR_PHY_CCK_TX_CTRL. */
529#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_M 0x0000000c
530#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
531#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
532
533/* Bits for AR_PHY_CCK_DETECT. */
534#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_M 0x0000003f
535#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
536#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_M 0x00001fc0
537#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
538#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x00002000
539
540/* Bits for AR_PHY_GAIN_2GHZ. */
541#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_M 0x0000003f
542#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
543#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_M 0x0000001f
544#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
545#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_M 0x00000fc0
546#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
547#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_M 0x00003c00
548#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
549#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_M 0x0001f000
550#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
551#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_M 0x003e0000
552#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
553#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_M 0x00fc0000
554#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
555
556/* Bit for AR_PHY_CCK_RXCTRL4. */
557#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_M 0x01f80000
558#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
559
560/* Bits for AR_PHY_DAG_CTRLCCK. */
561#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
562#define AR_PHY_DAG_CTRLCCK_RSSI_THR_M 0x0001fc00
563#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
564
565/* Bits for AR_PHY_FORCE_CLKEN_CCK. */
566#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
567
568/* Bits for AR_PHY_TPCRG1. */
569#define AR_PHY_TPCRG1_NUM_PD_GAIN_M 0x0000c000
570#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
571#define AR_PHY_TPCRG1_PD_GAIN_1_M 0x00030000
572#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
573#define AR_PHY_TPCRG1_PD_GAIN_2_M 0x000c0000
574#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
575#define AR_PHY_TPCRG1_PD_GAIN_3_M 0x00300000
576#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
577#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
578
579/* Bits for AR_PHY_TX_PWRCTRL4. */
580#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
581#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_M 0x000001fe
582#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
583
584/* Bits for AR_PHY_TX_PWRCTRL6_[01]. */
585#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_M 0x03000000
586#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
587
588/* Bits for AR_PHY_TX_PWRCTRL7. */
589#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_M 0x0007e000
590#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13
591#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_M 0x01f80000
592#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
593
594/* Bits for AR_PHY_TX_PWRCTRL9. */
595#define AR_PHY_TX_DESIRED_SCALE_CCK_M 0x00007c00
596#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 /* XXX should be 9? */
597#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
598
599/* Bits for AR_PHY_TX_GAIN_TBL. */
600#define AR_PHY_TX_GAIN_CLC_M 0x0000001e
601#define AR_PHY_TX_GAIN_CLC_S 1
602#define AR_PHY_TX_GAIN_M 0x0007f000
603#define AR_PHY_TX_GAIN_S 12
604
605/* Bits for AR_PHY_SPUR_REG. */
606#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_M 0x0000007f
607#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
608#define AR_SPUR_RSSI_THRESH 40
609#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x00000100
610#define AR_PHY_SPUR_REG_MASK_RATE_SELECT 0x0001fe00
611#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x00020000
612#define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03fc0000
613
614/* Bits for AR_PHY_ANALOG_SWAP. */
615#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
616
617/* Bits for AR_PHY_TPCRG5. */
618#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_M 0x0000000f
619#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
620#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_M 0x000003f0
621#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
622#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_M 0x0000fc00
623#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
624#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_M 0x003f0000
625#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
626#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_M 0x0fc00000
627#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
628
629/* Bits for AR_PHY_CL_CAL_CTL. */
630#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
631#define AR_PHY_CL_CAL_ENABLE 0x00000002
632
633/* Bits for AR_PHY_CLC_TBL. */
634#define AR_PHY_CLC_Q0_M 0x0000ffd0
635#define AR_PHY_CLC_Q0_S 5
636#define AR_PHY_CLC_I0_M 0x07ff0000
637#define AR_PHY_CLC_I0_S 16
638
639/* Bits for AR_PHY_XPA_CFG. */
640#define AR_PHY_FORCE_XPA_CFG 0x000000001
641
642/* Bits for AR_PHY_CH[01]_TX_PWRCTRL11. */
643#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_M 0x0000fc00
644#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
645#define AR_PHY_TX_PWRCTRL_OLPC_PWR_M 0x00ff0000
646#define AR_PHY_TX_PWRCTRL_OLPC_PWR_S 16
647
648/* Bits for AR_PHY_NEW_ADC_DC_GAIN_CORR. */
649#define AR_PHY_NEW_ADC_DC_GAIN_QGAIN_M 0x0000003f
650#define AR_PHY_NEW_ADC_DC_GAIN_QGAIN_S 0
651#define AR_PHY_NEW_ADC_DC_GAIN_IGAIN_M 0x00000fc0
652#define AR_PHY_NEW_ADC_DC_GAIN_IGAIN_S 6
653#define AR_PHY_NEW_ADC_DC_GAIN_QDC_M 0x001ff000
654#define AR_PHY_NEW_ADC_DC_GAIN_QDC_S 12
655#define AR_PHY_NEW_ADC_DC_GAIN_IDC_M 0x3fe00000
656#define AR_PHY_NEW_ADC_DC_GAIN_IDC_S 21
657
658/* Bits for AR_PHY(0x37). */
659#define AR5416_BMODE_SYNTH 0x00000002
660#define AR5416_AMODE_REFSEL_M 0x0000000c
661#define AR5416_AMODE_REFSEL_S 2
662
663
664#define AR5008_MAX_SCATTER 16 /* NB: not a hardware limit. */
665
666/*
667 * Tx DMA descriptor.
668 */
669struct ar_tx_desc {
670 uint32_t ds_link;
671 uint32_t ds_data;
672 uint32_t ds_ctl0;
673 uint32_t ds_ctl1;
674 uint32_t ds_ctl2;
675 uint32_t ds_ctl3;
676 uint32_t ds_ctl4;
677 uint32_t ds_ctl5;
678 uint32_t ds_ctl6;
679 uint32_t ds_ctl7;
680 uint32_t ds_ctl8;
681 uint32_t ds_ctl9;
682 uint32_t ds_ctl10;
683 uint32_t ds_ctl11;
684 uint32_t ds_status0;
685 uint32_t ds_status1;
686 uint32_t ds_tstamp;
687 uint32_t ds_ba_bitmap_lo;
688 uint32_t ds_ba_bitmap_hi;
689 uint32_t ds_evm0;
690 uint32_t ds_evm1;
691 uint32_t ds_evm2;
692 uint32_t ds_status8;
693 uint32_t ds_status9;
694 /*
695 * Padding to make Tx descriptors 128 bytes such that they will
696 * not cross a 4KB boundary.
697 */
698 uint32_t pad[8];
699} __packed __attribute__((aligned(4)));
700
701/* Bits for ds_ctl0. */
702#define AR_TXC0_FRAME_LEN_M 0x00000fff
703#define AR_TXC0_FRAME_LEN_S 0
704#define AR_TXC0_VIRT_MORE_FRAG 0x00001000
705#define AR_TXC0_XMIT_POWER_M 0x003f0000
706#define AR_TXC0_XMIT_POWER_S 16
707#define AR_TXC0_RTS_ENABLE 0x00400000
708#define AR_TXC0_VEOL 0x00800000
709#define AR_TXC0_CLR_DEST_MASK 0x01000000
710#define AR_TXC0_INTR_REQ 0x20000000
711#define AR_TXC0_DEST_IDX_VALID 0x40000000
712#define AR_TXC0_CTS_ENABLE 0x80000000
713
714/* Bits for ds_ctl1. */
715#define AR_TXC1_BUF_LEN_M 0x00000fff
716#define AR_TXC1_BUF_LEN_S 0
717#define AR_TXC1_MORE 0x00001000
718#define AR_TXC1_DEST_IDX_M 0x000fe000
719#define AR_TXC1_DEST_IDX_S 13
720#define AR_TXC1_FRAME_TYPE_M 0x00f00000
721#define AR_TXC1_FRAME_TYPE_S 20
722#define AR_FRAME_TYPE_NORMAL 0
723#define AR_FRAME_TYPE_ATIM 1
724#define AR_FRAME_TYPE_PSPOLL 2
725#define AR_FRAME_TYPE_BEACON 3
726#define AR_FRAME_TYPE_PROBE_RESP 4
727#define AR_TXC1_NO_ACK 0x01000000
728#define AR_TXC1_INSERT_TS 0x02000000
729#define AR_TXC1_EXT_ONLY 0x08000000
730#define AR_TXC1_EXT_AND_CTL 0x10000000
731#define AR_TXC1_MORE_AGGR 0x20000000
732#define AR_TXC1_IS_AGGR 0x40000000
733
734/* Bits for ds_ctl2. */
735#define AR_TXC2_BURST_DUR_M 0x00007fff
736#define AR_TXC2_BURST_DUR_S 0
737#define AR_TXC2_DUR_UPDATE_ENA 0x00008000
738#define AR_TXC2_XMIT_DATA_TRIES0_M 0x000f0000
739#define AR_TXC2_XMIT_DATA_TRIES0_S 16
740#define AR_TXC2_XMIT_DATA_TRIES1_M 0x00f00000
741#define AR_TXC2_XMIT_DATA_TRIES1_S 20
742#define AR_TXC2_XMIT_DATA_TRIES2_M 0x0f000000
743#define AR_TXC2_XMIT_DATA_TRIES2_S 24
744#define AR_TXC2_XMIT_DATA_TRIES3_M 0xf0000000
745#define AR_TXC2_XMIT_DATA_TRIES3_S 28
746
747/* Bits for ds_ctl3. */
748#define AR_TXC3_XMIT_RATE0_M 0x000000ff
749#define AR_TXC3_XMIT_RATE0_S 0
750#define AR_TXC3_XMIT_RATE1_M 0x0000ff00
751#define AR_TXC3_XMIT_RATE1_S 8
752#define AR_TXC3_XMIT_RATE2_M 0x00ff0000
753#define AR_TXC3_XMIT_RATE2_S 16
754#define AR_TXC3_XMIT_RATE3_M 0xff000000
755#define AR_TXC3_XMIT_RATE3_S 24
756
757/* Bits for ds_ctl4. */
758#define AR_TXC4_PACKET_DUR0_M 0x00007fff
759#define AR_TXC4_PACKET_DUR0_S 0
760#define AR_TXC4_RTSCTS_QUAL0 0x00008000
761#define AR_TXC4_PACKET_DUR1_M 0x7fff0000
762#define AR_TXC4_PACKET_DUR1_S 16
763#define AR_TXC4_RTSCTS_QUAL1 0x80000000
764/* Shortcut. */
765#define AR_TXC4_RTSCTS_QUAL01 \
766 (AR_TXC4_RTSCTS_QUAL0 | AR_TXC4_RTSCTS_QUAL1)
767
768/* Bits for ds_ctl5. */
769#define AR_TXC5_PACKET_DUR2_M 0x00007fff
770#define AR_TXC5_PACKET_DUR2_S 0
771#define AR_TXC5_RTSCTS_QUAL2 0x00008000
772#define AR_TXC5_PACKET_DUR3_M 0x7fff0000
773#define AR_TXC5_PACKET_DUR3_S 16
774#define AR_TXC5_RTSCTS_QUAL3 0x80000000
775/* Shortcut. */
776#define AR_TXC5_RTSCTS_QUAL23 \
777 (AR_TXC5_RTSCTS_QUAL2 | AR_TXC5_RTSCTS_QUAL3)
778
779/* Bits for ds_ctl6. */
780#define AR_TXC6_AGGR_LEN_M 0x0000ffff
781#define AR_TXC6_AGGR_LEN_S 0
782#define AR_TXC6_PAD_DELIM_M 0x03fc0000
783#define AR_TXC6_PAD_DELIM_S 18
784#define AR_TXC6_ENCR_TYPE_M 0x0c000000
785#define AR_TXC6_ENCR_TYPE_S 26
786#define AR_ENCR_TYPE_CLEAR 0
787#define AR_ENCR_TYPE_WEP 1
788#define AR_ENCR_TYPE_AES 2
789#define AR_ENCR_TYPE_TKIP 3
790
791/* Bits for ds_ctl7. */
792#define AR_TXC7_2040_0 0x00000001
793#define AR_TXC7_GI0 0x00000002
794#define AR_TXC7_CHAIN_SEL0_M 0x0000001c
795#define AR_TXC7_CHAIN_SEL0_S 2
796#define AR_TXC7_2040_1 0x00000020
797#define AR_TXC7_GI1 0x00000040
798#define AR_TXC7_CHAIN_SEL1_M 0x00000380
799#define AR_TXC7_CHAIN_SEL1_S 7
800#define AR_TXC7_2040_2 0x00000400
801#define AR_TXC7_GI2 0x00000800
802#define AR_TXC7_CHAIN_SEL2_M 0x00007000
803#define AR_TXC7_CHAIN_SEL2_S 12
804#define AR_TXC7_2040_3 0x00008000
805#define AR_TXC7_GI3 0x00010000
806#define AR_TXC7_CHAIN_SEL3_M 0x000e0000
807#define AR_TXC7_CHAIN_SEL3_S 17
808#define AR_TXC7_RTSCTS_RATE_M 0x0ff00000
809#define AR_TXC7_RTSCTS_RATE_S 20
810/* Shortcuts. */
811#define AR_TXC7_2040_0123 \
812 (AR_TXC7_2040_0 | AR_TXC7_2040_1 | AR_TXC7_2040_2 | AR_TXC7_2040_3)
813#define AR_TXC7_GI0123 \
814 (AR_TXC7_GI0 | AR_TXC7_GI1 | AR_TXC7_GI2 | AR_TXC7_GI3)
815
816/* Bits for ds_status0. */
817#define AR_TXS0_RSSI_ANT0(i) (((x) >> ((i) * 8)) & 0xff)
818#define AR_TXS0_BA_STATUS 0x40000000
819
820/* Bits for ds_status1. */
821#define AR_TXS1_FRM_XMIT_OK 0x00000001
822#define AR_TXS1_EXCESSIVE_RETRIES 0x00000002
823#define AR_TXS1_FIFO_UNDERRUN 0x00000004
824#define AR_TXS1_FILTERED 0x00000008
825#define AR_TXS1_RTS_FAIL_CNT_M 0x000000f0
826#define AR_TXS1_RTS_FAIL_CNT_S 4
827#define AR_TXS1_DATA_FAIL_CNT_M 0x00000f00
828#define AR_TXS1_DATA_FAIL_CNT_S 8
829#define AR_TXS1_VIRT_RETRY_CNT_M 0x0000f000
830#define AR_TXS1_VIRT_RETRY_CNT_S 12
831#define AR_TXS1_TX_DELIM_UNDERRUN 0x00010000
832#define AR_TXS1_TX_DATA_UNDERRUN 0x00020000
833#define AR_TXS1_DESC_CFG_ERR 0x00040000
834#define AR_TXS1_TX_TIMER_EXPIRED 0x00080000
835/* Shortcut. */
836#define AR_TXS1_UNDERRUN \
837 (AR_TXS1_FIFO_UNDERRUN | \
838 AR_TXS1_TX_DELIM_UNDERRUN | \
839 AR_TXS1_TX_DATA_UNDERRUN)
840
841/* Bits for ds_status9. */
842#define AR_TXS9_DONE 0x00000001
843#define AR_TXS9_SEQNUM_M 0x00001ffe
844#define AR_TXS9_SEQNUM_S 1
845#define AR_TXS9_TXOP_EXCEEDED 0x00020000
846#define AR_TXS9_FINAL_IDX_M 0x00600000
847#define AR_TXS9_FINAL_IDX_S 21
848#define AR_TXS9_POWER_MGMT 0x02000000
849
850/*
851 * Rx DMA descriptor.
852 */
853struct ar_rx_desc {
854 uint32_t ds_link;
855 uint32_t ds_data;
856 uint32_t ds_ctl0;
857 uint32_t ds_ctl1;
858 uint32_t ds_status0;
859 uint32_t ds_status1;
860 uint32_t ds_status2;
861 uint32_t ds_status3;
862 uint32_t ds_status4;
863 uint32_t ds_status5;
864 uint32_t ds_status6;
865 uint32_t ds_status7;
866 uint32_t ds_status8;
867 /*
868 * Padding to make Rx descriptors 64 bytes such that they will
869 * not cross a 4KB boundary.
870 */
871 uint32_t pad[3];
872} __packed __attribute__((aligned(4)));
873
874/* Bits for ds_ctl1. */
875#define AR_RXC1_BUF_LEN_M 0x00000fff
876#define AR_RXC1_BUF_LEN_S 0
877#define AR_RXC1_INTR_REQ 0x00002000
878
879/* Bits for ds_ctl2. */
880#define AR_RXS0_RSSI_ANT00(x) (((x) >> 0) & 0xff)
881#define AR_RXS0_RSSI_ANT01(x) (((x) >> 8) & 0xff)
882#define AR_RXS0_RSSI_ANT02(x) (((x) >> 16) & 0xff)
883#define AR_RXS0_RATE_M 0xff000000
884#define AR_RXS0_RATE_S 24
885
886/* Bits for ds_status1. */
887#define AR_RXS1_DATA_LEN_M 0x00000fff
888#define AR_RXS1_DATA_LEN_S 0
889#define AR_RXS1_MORE 0x00001000
890
891/* Bits for ds_status3. */
892#define AR_RXS3_GI 0x00000001
893#define AR_RXS3_2040 0x00000002
894#define AR_RXS3_PARALLEL_40 0x00000004
895#define AR_RXS3_ANTENNA_M 0xffffff00
896#define AR_RXS3_ANTENNA_S 8
897#define AR_RXS3_RATE_M 0x000003fc
898#define AR_RXS3_RATE_S 2
899
900/* Bits for ds_status4. */
901#define AR_RXS4_RSSI_COMBINED_M 0xff000000
902#define AR_RXS4_RSSI_COMBINED_S 24
903
904/* Bits for ds_status8. */
905#define AR_RXS8_DONE 0x00000001
906#define AR_RXS8_FRAME_OK 0x00000002
907#define AR_RXS8_CRC_ERR 0x00000004
908#define AR_RXS8_DECRYPT_CRC_ERR 0x00000008
909#define AR_RXS8_PHY_ERR 0x00000010
910#define AR_RXS8_MICHAEL_ERR 0x00000020
911#define AR_RXS8_PRE_DELIM_CRC_ERR 0x00000040
912#define AR_RXS8_PHY_ERR_CODE_M 0x0000ff00
913#define AR_RXS8_PHY_ERR_CODE_S 8
914#define AR_RXS8_KEY_IDX_VALID 0x00000100
915#define AR_RXS8_KEY_IDX_M 0x0000fe00
916#define AR_RXS8_KEY_IDX_S 9
917#define AR_RXS8_POST_DELIM_CRC_ERR 0x00040000
918#define AR_RXS8_DECRYPT_BUSY_ERR 0x40000000
919
920#define AR_MAX_PWR_RANGE_IN_HALF_DB 64
921#define AR9285_PD_GAIN_BOUNDARY_DEFAULT 58
922
923/*
924 * AR5008 family common ROM header.
925 */
926#define AR_EEPROM_MAGIC_OFFSET 0x0000
927#if BYTE_ORDER == BIG_ENDIAN
928#define AR_EEPROM_MAGIC 0x5aa5
929#else
930#define AR_EEPROM_MAGIC 0xa55a
931#endif
932
933#define AR_NO_SPUR 0x8000
934#define AR_NUM_PDADC_VALUES 128
935
936struct ar_base_eep_header {
937 uint16_t length;
938 uint16_t checksum;
939 uint16_t version;
940#define AR_EEP_VER 0xe
941#define AR_EEP_VER_MINOR_MASK 0x0fff
942#define AR_EEP_MINOR_VER_2 2
943#define AR_EEP_MINOR_VER_3 3
944#define AR_EEP_MINOR_VER_7 7
945#define AR_EEP_MINOR_VER_9 9
946#define AR_EEP_MINOR_VER_10 10
947#define AR_EEP_MINOR_VER_16 16
948#define AR_EEP_MINOR_VER_17 17
949#define AR_EEP_MINOR_VER_19 19
950#define AR_EEP_MINOR_VER_20 20
951#define AR_EEP_MINOR_VER_21 21
952#define AR_EEP_MINOR_VER_22 22
953
954 uint8_t opCapFlags;
955#define AR_OPFLAGS_11A 0x01
956#define AR_OPFLAGS_11G 0x02
957#define AR_OPFLAGS_11N_5G40 0x04
958#define AR_OPFLAGS_11N_2G40 0x08
959#define AR_OPFLAGS_11N_5G20 0x10
960#define AR_OPFLAGS_11N_2G20 0x20
961/* Shortcut. */
962#define AR_OPFLAGS_11N 0x3c
963
964 uint8_t eepMisc;
965 uint16_t regDmn[2];
966 uint8_t macAddr[6];
967 uint8_t rxMask;
968 uint8_t txMask;
969 uint16_t rfSilent;
970#define AR_EEP_RFSILENT_ENABLED 0x0001
971#define AR_EEP_RFSILENT_GPIO_SEL_M 0x001c
972#define AR_EEP_RFSILENT_GPIO_SEL_S 2
973#define AR_EEP_RFSILENT_POLARITY 0x0002
974
975 uint16_t blueToothOptions;
976 uint16_t deviceCap;
977#define AR_EEP_DEVCAP_COMPRESS_DIS 0x0001
978#define AR_EEP_DEVCAP_AES_DIS 0x0002
979#define AR_EEP_DEVCAP_FASTFRAME_DIS 0x0004
980#define AR_EEP_DEVCAP_BURST_DIS 0x0008
981#define AR_EEP_DEVCAP_MAXQCU_M 0x01f0
982#define AR_EEP_DEVCAP_MAXQCU_S 4
983#define AR_EEP_DEVCAP_HEAVY_CLIP_EN 0x0200
984#define AR_EEP_DEVCAP_KC_ENTRIES_M 0xf000
985#define AR_EEP_DEVCAP_KC_ENTRIES_S 12
986
987 uint32_t binBuildNumber;
988 uint8_t deviceType;
989} __packed;
990
991#define AR_EEP_TXGAIN_ORIGINAL 0
992#define AR_EEP_TXGAIN_HIGH_POWER 1
993
994#define AR_EEPROM_MODAL_SPURS 5
995
996struct ar_spur_chan {
997 uint16_t spurChan;
998 uint8_t spurRangeLow;
999 uint8_t spurRangeHigh;
1000} __packed;
1001
1002struct ar_cal_data_per_freq_olpc {
1003 uint8_t pwrPdg[2][5];
1004 uint8_t vpdPdg[2][5];
1005 uint8_t pcdac[2][5];
1006 uint8_t empty[2][5];
1007} __packed;
1008
1009struct ar_cal_target_power_leg {
1010 uint8_t bChannel;
1011 uint8_t tPow2x[4];
1012} __packed;
1013
1014struct ar_cal_target_power_ht {
1015 uint8_t bChannel;
1016 uint8_t tPow2x[8];
1017} __packed;
1018
1019struct ar_cal_ctl_edges {
1020 uint8_t bChannel;
1021 uint8_t tPowerFlag;
1022#define AR_CAL_CTL_EDGES_POWER_M 0x3f
1023#define AR_CAL_CTL_EDGES_POWER_S 0
1024#define AR_CAL_CTL_EDGES_FLAG_M 0xc0
1025#define AR_CAL_CTL_EDGES_FLAG_S 6
1026} __packed;
1027
1028#endif /* _ARN5008REG_H_ */
1029