1 | /* $NetBSD: elink3reg.h,v 1.31 2006/11/05 05:57:53 itohy Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1995 Herb Peyerl <hpeyerl@beer.org> |
5 | * All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * 3. All advertising materials mentioning features or use of this software |
16 | * must display the following acknowledgement: |
17 | * This product includes software developed by Herb Peyerl. |
18 | * 4. The name of Herb Peyerl may not be used to endorse or promote products |
19 | * derived from this software without specific prior written permission. |
20 | * |
21 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
22 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
23 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
24 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
25 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
26 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
30 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
31 | * |
32 | */ |
33 | |
34 | /* |
35 | * These define the EEPROM data structure. They are used in the probe |
36 | * function to verify the existence of the adapter after having sent |
37 | * the ID_Sequence. |
38 | */ |
39 | #define EEPROM_NODE_ADDR_0 0x0 /* Word */ |
40 | #define EEPROM_NODE_ADDR_1 0x1 /* Word */ |
41 | #define EEPROM_NODE_ADDR_2 0x2 /* Word */ |
42 | #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ |
43 | #define EEPROM_MFG_DATE 0x4 /* Manufacturing date */ |
44 | #define EEPROM_MFG_DIVSION 0x5 /* Manufacturing division */ |
45 | #define EEPROM_MFG_PRODUCT 0x6 /* Product code */ |
46 | #define EEPROM_MFG_ID 0x7 /* 0x6d50 */ |
47 | #define EEPROM_ADDR_CFG 0x8 /* Base addr */ |
48 | #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ |
49 | #define EEPROM_OEM_ADDR0 0xa |
50 | #define EEPROM_OEM_ADDR1 0xb |
51 | #define EEPROM_OEM_ADDR2 0xc |
52 | #define EEPROM_SOFTINFO 0xd |
53 | #define EEPROM_COMPAT 0xe |
54 | #define EEPROM_SOFTINFO2 0xf |
55 | #define EEPROM_CAP 0x10 |
56 | #define EEPROM_CONFIG_LOW 0x12 |
57 | #define EEPROM_CONFIG_HIGH 0x13 |
58 | #define EEPROM_SSI 0x14 |
59 | #define EEPROM_CHECKSUM_EL3 0x17 |
60 | |
61 | /* |
62 | * These are the registers for the 3Com 3c509 and their bit patterns when |
63 | * applicable. They have been taken out of the "EtherLink III Parallel |
64 | * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual |
65 | * from 3com. |
66 | */ |
67 | #define ELINK_COMMAND 0x0e /* Write. BASE+0x0e is always a command reg. */ |
68 | #define ELINK_STATUS 0x0e /* Read. BASE+0x0e is always status reg. */ |
69 | #define ELINK_WINDOW 0x0f /* Read. BASE+0x0f is always window reg. */ |
70 | |
71 | /* |
72 | * Corkscrew ISA Bridge ASIC registers. |
73 | */ |
74 | #define CORK_ASIC_DCR 0x2000 |
75 | #define CORK_ASIC_RCR 0x2002 |
76 | #define CORK_ASIC_ROM_PAGE 0x2004 /* 8-bit */ |
77 | #define CORK_ASIC_MCR 0x2006 /* 8-bit */ |
78 | #define CORK_ASIC_DEBUG 0x2008 /* 8-bit */ |
79 | #define CORK_ASIC_EEPROM_COMMAND 0x200a |
80 | #define CORK_ASIC_EEPROM_DATA 0x200c |
81 | |
82 | /* |
83 | * Corkscrew DMA Control Register. |
84 | */ |
85 | #define DCR_CHRDYWAIT_40ns (0 << 13) |
86 | #define DCR_CHRDYWAIT_80ns (1 << 13) |
87 | #define DCR_CHRDYWAIT_120ns (2 << 13) |
88 | #define DCR_CHRDYWAIT_160ns (3 << 13) |
89 | #define DCR_RECOVWAIT_80ns (0 << 11) |
90 | #define DCR_RECOVWAIT_120ns (1 << 11) |
91 | #define DCR_RECOVWAIT_160ns (2 << 11) |
92 | #define DCR_RECOVWAIT_200ns (3 << 11) |
93 | #define DCR_CMDWIDTH(x) ((x) << 8) /* base 40ns, 40ns increments */ |
94 | #define DCR_BURSTLEN(x) ((x) << 3) |
95 | #define DCR_DRQSELECT(x) ((x) << 0) /* 3, 5, 6, 7 valid */ |
96 | |
97 | /* |
98 | * Corkscrew Debug register. |
99 | */ |
100 | #define DEBUG_PCIBUSFAULT (1U << 0) |
101 | #define DEBUG_ISABUSFAULT (1U << 1) |
102 | |
103 | /* |
104 | * Corkscrew EEPROM Command register. |
105 | */ |
106 | #define CORK_EEPROM_BUSY (1U << 9) |
107 | #define CORK_EEPROM_CMD_READ (1U << 7) /* Same as 3c509 */ |
108 | |
109 | /* |
110 | * Corkscrew Master Control register. |
111 | */ |
112 | #define MCR_PCI_CONFIG (1U << 0) |
113 | #define MCR_WRITE_BUFFER (1U << 1) |
114 | #define MCR_READ_PREFETCH (1U << 2) |
115 | |
116 | /* |
117 | * Window 0 registers. Setup. |
118 | */ |
119 | /* Write */ |
120 | #define ELINK_W0_EEPROM_DATA 0x0c |
121 | #define ELINK_W0_EEPROM_COMMAND 0x0a |
122 | #define ELINK_W0_RESOURCE_CFG 0x08 |
123 | #define ELINK_W0_ADDRESS_CFG 0x06 |
124 | #define ELINK_W0_CONFIG_CTRL 0x04 |
125 | /* Read */ |
126 | #define ELINK_W0_PRODUCT_ID 0x02 |
127 | #define ELINK_W0_MFG_ID 0x00 |
128 | |
129 | /* |
130 | * Window 1 registers. Operating Set. |
131 | */ |
132 | /* Write */ |
133 | #define ELINK_W1_TX_PIO_WR_2 0x02 |
134 | #define ELINK_W1_TX_PIO_WR_1 0x00 |
135 | /* Read */ |
136 | #define ELINK_W1_FREE_TX 0x0c |
137 | #define ELINK_W1_TX_STATUS 0x0a |
138 | #define ELINK_W1_RX_STATUS 0x08 |
139 | #define ELINK_W1_RX_ERRORS 0x04 |
140 | #define ELINK_W1_RX_PIO_RD_2 0x02 |
141 | #define ELINK_W1_RX_PIO_RD_1 0x00 |
142 | /* |
143 | * Special registers used by the RoadRunner. These are used to program |
144 | * a FIFO buffer to reduce the PCMCIA->PCI bridge latency during PIO. |
145 | */ |
146 | #define ELINK_W1_RUNNER_RDCTL 0x16 |
147 | #define ELINK_W1_RUNNER_WRCTL 0x1c |
148 | |
149 | /* |
150 | * Window 2 registers. Station Address Setup/Read |
151 | */ |
152 | /* Read/Write */ |
153 | #define ELINK_W2_RECVMASK_0 0x06 |
154 | #define ELINK_W2_ADDR_5 0x05 |
155 | #define ELINK_W2_ADDR_4 0x04 |
156 | #define ELINK_W2_ADDR_3 0x03 |
157 | #define ELINK_W2_ADDR_2 0x02 |
158 | #define ELINK_W2_ADDR_1 0x01 |
159 | #define ELINK_W2_ADDR_0 0x00 |
160 | |
161 | /* |
162 | * Window 3 registers. Configuration and FIFO Management. |
163 | */ |
164 | /* Read */ |
165 | #define ELINK_W3_FREE_TX 0x0c |
166 | #define ELINK_W3_FREE_RX 0x0a |
167 | /* Read/Write, at least on busmastering cards. */ |
168 | #define ELINK_W3_INTERNAL_CONFIG 0x00 /* 32 bits */ |
169 | #define ELINK_W3_OTHER_INT 0x04 /* 8 bits */ |
170 | #define ELINK_W3_PIO_RESERVED 0x05 /* 8 bits */ |
171 | #define ELINK_W3_MAC_CONTROL 0x06 /* 16 bits */ |
172 | #define ELINK_W3_RESET_OPTIONS 0x08 /* 16 bits */ |
173 | |
174 | /* |
175 | * Window 4 registers. Diagnostics. |
176 | */ |
177 | /* Read/Write */ |
178 | #define ELINK_W4_MEDIA_TYPE 0x0a |
179 | #define ELINK_W4_CTRLR_STATUS 0x08 |
180 | #define ELINK_W4_NET_DIAG 0x06 |
181 | #define ELINK_W4_FIFO_DIAG 0x04 |
182 | #define ELINK_W4_HOST_DIAG 0x02 |
183 | #define ELINK_W4_TX_DIAG 0x00 |
184 | |
185 | /* |
186 | * Window 4 offset 8 is the PHY Management register on the |
187 | * 3c90x. |
188 | */ |
189 | #define ELINK_W4_BOOM_PHYSMGMT 0x08 |
190 | #define PHYSMGMT_CLK 0x0001 |
191 | #define PHYSMGMT_DATA 0x0002 |
192 | #define PHYSMGMT_DIR 0x0004 |
193 | |
194 | |
195 | /* |
196 | * Window 5 Registers. Results and Internal status. |
197 | */ |
198 | /* Read */ |
199 | #define ELINK_W5_READ_0_MASK 0x0c |
200 | #define ELINK_W5_INTR_MASK 0x0a |
201 | #define ELINK_W5_RX_FILTER 0x08 |
202 | #define ELINK_W5_RX_EARLY_THRESH 0x06 |
203 | #define ELINK_W5_TX_AVAIL_THRESH 0x02 |
204 | #define ELINK_W5_TX_START_THRESH 0x00 |
205 | |
206 | /* |
207 | * Window 6 registers. Statistics. |
208 | */ |
209 | /* Read/Write */ |
210 | #define TX_TOTAL_OK 0x0c |
211 | #define RX_TOTAL_OK 0x0a |
212 | #define UPPER_FRAMES_OK 0x09 |
213 | #define TX_DEFERRALS 0x08 |
214 | #define RX_FRAMES_OK 0x07 |
215 | #define TX_FRAMES_OK 0x06 |
216 | #define RX_OVERRUNS 0x05 |
217 | #define TX_COLLISIONS 0x04 |
218 | #define TX_AFTER_1_COLLISION 0x03 |
219 | #define TX_AFTER_X_COLLISIONS 0x02 |
220 | #define TX_NO_SQE 0x01 |
221 | #define TX_CD_LOST 0x00 |
222 | |
223 | /* |
224 | * Window 7 registers. |
225 | * Address and length for a single bus-master DMA transfer. |
226 | * Unused for elink3 cards. |
227 | */ |
228 | #define ELINK_W7_MASTER_ADDRES 0x00 |
229 | #define ELINK_W7_RX_ERROR 0x04 |
230 | #define ELINK_W7_MASTER_LEN 0x06 |
231 | #define ELINK_W7_RX_STATUS 0x08 |
232 | #define ELINK_W7_MASTER_STATUS 0x0c |
233 | |
234 | /* |
235 | * Register definitions. |
236 | */ |
237 | |
238 | /* |
239 | * Command register. All windows. |
240 | * |
241 | * 16 bit register. |
242 | * 15-11: 5-bit code for command to be executed. |
243 | * 10-0: 11-bit arg if any. For commands with no args; |
244 | * this can be set to anything. |
245 | */ |
246 | /* Wait at least 1ms after issuing */ |
247 | #define GLOBAL_RESET (u_int16_t) 0x0000 |
248 | #define WINDOW_SELECT (u_int16_t) (0x01<<11) |
249 | /* |
250 | * Read ADDR_CFG reg to determine whether this is needed. If so; wait 800 |
251 | * uSec before using transceiver. |
252 | */ |
253 | #define START_TRANSCEIVER (u_int16_t) (0x02<<11) |
254 | /* state disabled on power-up */ |
255 | #define RX_DISABLE (u_int16_t) (0x03<<11) |
256 | #define RX_ENABLE (u_int16_t) (0x04<<11) |
257 | #define RX_RESET (u_int16_t) (0x05<<11) |
258 | #define RX_DISCARD_TOP_PACK (u_int16_t) (0x08<<11) |
259 | #define TX_ENABLE (u_int16_t) (0x09<<11) |
260 | #define TX_DISABLE (u_int16_t) (0x0a<<11) |
261 | #define TX_RESET (u_int16_t) (0x0b<<11) |
262 | #define REQ_INTR (u_int16_t) (0x0c<<11) |
263 | #define ACK_INTR (u_int16_t) (0x0d<<11) |
264 | #define SET_INTR_MASK (u_int16_t) (0x0e<<11) |
265 | /* busmastering-cards only? */ |
266 | #define STATUS_ENABLE (u_int16_t) (0x0f<<11) |
267 | #define SET_RD_0_MASK (u_int16_t) (0x0f<<11) |
268 | |
269 | #define SET_RX_FILTER (u_int16_t) (0x10<<11) |
270 | # define FIL_INDIVIDUAL (u_int16_t) (0x01) |
271 | # define FIL_MULTICAST (u_int16_t) (0x02) |
272 | # define FIL_BRDCST (u_int16_t) (0x04) |
273 | # define FIL_PROMISC (u_int16_t) (0x08) |
274 | |
275 | #define SET_RX_EARLY_THRESH (u_int16_t) (0x11<<11) |
276 | #define SET_TX_AVAIL_THRESH (u_int16_t) (0x12<<11) |
277 | #define SET_TX_START_THRESH (u_int16_t) (0x13<<11) |
278 | #define START_DMA (u_int16_t) (0x14<<11) /* busmaster-only */ |
279 | # define START_DMA_TX (START_DMA | 0x0)) /* busmaster-only */ |
280 | # define START_DMA_RX (START_DMA | 0x1) /* busmaster-only */ |
281 | #define STATS_ENABLE (u_int16_t) (0x15<<11) |
282 | #define STATS_DISABLE (u_int16_t) (0x16<<11) |
283 | #define STOP_TRANSCEIVER (u_int16_t) (0x17<<11) |
284 | |
285 | /* Only on adapters that support power management: */ |
286 | #define POWERUP (u_int16_t) (0x1b<<11) |
287 | #define POWERDOWN (u_int16_t) (0x1c<<11) |
288 | #define POWERAUTO (u_int16_t) (0x1d<<11) |
289 | |
290 | |
291 | |
292 | /* |
293 | * Command parameter that disables threshold interrupts |
294 | * PIO (3c509) cards use 2044. The fifo word-oriented and 2044--2047 work. |
295 | * "busmastering" cards need 8188. |
296 | * The implicit two-bit upshift done by busmastering cards means |
297 | * a value of 2047 disables threshold interrupts on both. |
298 | */ |
299 | #define ELINK_THRESH_DISABLE 2047 |
300 | |
301 | |
302 | /* |
303 | * Status register. All windows. |
304 | * |
305 | * 15-13: Window number(0-7). |
306 | * 12: Command_in_progress. |
307 | * 11: reserved / DMA in progress on busmaster cards. |
308 | * 10: reserved. |
309 | * 9: reserved. |
310 | * 8: reserved / DMA done on busmaster cards. |
311 | * 7: Update Statistics. |
312 | * 6: Interrupt Requested. |
313 | * 5: RX Early. |
314 | * 4: RX Complete. |
315 | * 3: TX Available. |
316 | * 2: TX Complete. |
317 | * 1: Adapter Failure. |
318 | * 0: Interrupt Latch. |
319 | */ |
320 | #define INTR_LATCH (u_int16_t) (0x0001) |
321 | #define CARD_FAILURE (u_int16_t) (0x0002) |
322 | #define TX_COMPLETE (u_int16_t) (0x0004) |
323 | #define TX_AVAIL (u_int16_t) (0x0008) |
324 | #define RX_COMPLETE (u_int16_t) (0x0010) |
325 | #define RX_EARLY (u_int16_t) (0x0020) |
326 | #define INT_RQD (u_int16_t) (0x0040) |
327 | #define UPD_STATS (u_int16_t) (0x0080) |
328 | #define DMA_DONE (u_int16_t) (0x0100) /* DMA cards only */ |
329 | #define DMA_IN_PROGRESS (u_int16_t) (0x0800) /* DMA cards only */ |
330 | #define COMMAND_IN_PROGRESS (u_int16_t) (0x1000) |
331 | |
332 | #define ALL_INTERRUPTS (CARD_FAILURE | TX_COMPLETE | TX_AVAIL | RX_COMPLETE | \ |
333 | RX_EARLY | INT_RQD | UPD_STATS) |
334 | |
335 | #define WATCHED_INTERRUPTS (CARD_FAILURE | TX_COMPLETE | RX_COMPLETE | TX_AVAIL) |
336 | |
337 | /* |
338 | * FIFO Registers. RX Status. |
339 | * |
340 | * 15: Incomplete or FIFO empty. |
341 | * 14: 1: Error in RX Packet 0: Incomplete or no error. |
342 | * 14-11: Type of error. [14-11] |
343 | * 1000 = Overrun. |
344 | * 1011 = Run Packet Error. |
345 | * 1100 = Alignment Error. |
346 | * 1101 = CRC Error. |
347 | * 1001 = Oversize Packet Error (>1514 bytes) |
348 | * 0010 = Dribble Bits. |
349 | * (all other error codes, no errors.) |
350 | * |
351 | * 10-0: RX Bytes (0-1514) |
352 | */ |
353 | #define ERR_INCOMPLETE (u_int16_t) (0x8000) |
354 | #define ERR_RX (u_int16_t) (0x4000) |
355 | #define ERR_MASK (u_int16_t) (0x7800) |
356 | #define ERR_OVERRUN (u_int16_t) (0x4000) |
357 | #define ERR_RUNT (u_int16_t) (0x5800) |
358 | #define ERR_ALIGNMENT (u_int16_t) (0x6000) |
359 | #define ERR_CRC (u_int16_t) (0x6800) |
360 | #define ERR_OVERSIZE (u_int16_t) (0x4800) |
361 | #define ERR_DRIBBLE (u_int16_t) (0x1000) |
362 | |
363 | /* |
364 | * TX Status |
365 | * |
366 | * Reports the transmit status of a completed transmission. Writing this |
367 | * register pops the transmit completion stack. |
368 | * |
369 | * Window 1/Port 0x0b. |
370 | * |
371 | * 7: Complete |
372 | * 6: Interrupt on successful transmission requested. |
373 | * 5: Jabber Error (TP Only, TX Reset required. ) |
374 | * 4: Underrun (TX Reset required. ) |
375 | * 3: Maximum Collisions. |
376 | * 2: TX Status Overflow. |
377 | * 1-0: Undefined. |
378 | * |
379 | */ |
380 | #define TXS_COMPLETE 0x8000 |
381 | #define TXS_INTR_REQ 0x4000 |
382 | #define TXS_JABBER 0x2000 |
383 | #define TXS_UNDERRUN 0x1000 |
384 | #define TXS_MAX_COLLISION 0x0800 |
385 | #define TXS_STATUS_OVERFLOW 0x0400 |
386 | #define TXS_RECLAIM 0x0200 |
387 | #define TXS_TIMER 0x00ff |
388 | |
389 | /* |
390 | * RX status |
391 | * Window 1/Port 0x08. |
392 | */ |
393 | #define RX_BYTES_MASK (u_int16_t) (0x07ff) |
394 | |
395 | /* |
396 | * Internal Config and MAC control (Window 3) |
397 | * Window 3 / Port 0: 32-bit internal config register: |
398 | * bits 0-2: fifo buffer ram size |
399 | * 3: ram width (word/byte) (ro) |
400 | * 4-5: ram speed |
401 | * 6-7: rom size |
402 | * 8-15: reserved |
403 | * |
404 | * 16-17: ram split (5:3, 3:1, or 1:1). |
405 | * 18-19: reserved |
406 | * 20-22: selected media type |
407 | * 21: unused |
408 | * 24: (nonvolatile) driver should autoselect media |
409 | * 25-31: reserved |
410 | * |
411 | * The low-order 16 bits should generally not be changed by software. |
412 | * Offsets defined for two 16-bit words, to help out 16-bit busses. |
413 | */ |
414 | #define CONFIG_RAMSIZE (u_int16_t) 0x0007 |
415 | #define CONFIG_RAMSIZE_SHIFT 0 |
416 | |
417 | #define CONFIG_RAMWIDTH (u_int16_t) 0x0008 |
418 | #define CONFIG_RAMWIDTH_SHIFT 3 |
419 | |
420 | #define CONFIG_RAMSPEED (u_int16_t) 0x0030 |
421 | #define CONFIG_RAMSPEED_SHIFT 4 |
422 | #define CONFIG_ROMSIZE (u_int16_t) 0x00c0 |
423 | #define CONFIG_ROMSIZE_SHIFT 6 |
424 | |
425 | /* Window 3/port 2 */ |
426 | #define CONFIG_RAMSPLIT (u_int16_t) 0x0003 |
427 | #define CONFIG_RAMSPLIT_SHIFT 0 |
428 | #define CONFIG_MEDIAMASK (u_int16_t) 0x0070 |
429 | #define CONFIG_MEDIAMASK_SHIFT 4 |
430 | |
431 | #define CONFIG_AUTOSELECT (u_int16_t) 0x0100 |
432 | #define CONFIG_AUTOSELECT_SHIFT 8 |
433 | |
434 | /* |
435 | * MAC_CONTROL (Window 3) |
436 | */ |
437 | #define MAC_CONTROL_FDX 0x20 /* full-duplex mode */ |
438 | |
439 | |
440 | /* Active media in INTERNAL_CONFIG media bits */ |
441 | |
442 | #define ELINKMEDIA_10BASE_T (u_int16_t) 0x00 |
443 | #define ELINKMEDIA_AUI (u_int16_t) 0x01 |
444 | #define ELINKMEDIA_RESV1 (u_int16_t) 0x02 |
445 | #define ELINKMEDIA_10BASE_2 (u_int16_t) 0x03 |
446 | #define ELINKMEDIA_100BASE_TX (u_int16_t) 0x04 |
447 | #define ELINKMEDIA_100BASE_FX (u_int16_t) 0x05 |
448 | #define ELINKMEDIA_MII (u_int16_t) 0x06 |
449 | #define ELINKMEDIA_100BASE_T4 (u_int16_t) 0x07 |
450 | |
451 | |
452 | /* |
453 | * RESET_OPTIONS (Window 3, on Demon/Vortex/Boomerang only) |
454 | * also mapped to PCI configuration space on PCI adaptors. |
455 | * |
456 | * (same register as Vortex ELINK_W3_RESET_OPTIONS, mapped to pci-config space) |
457 | */ |
458 | #define ELINK_PCI_100BASE_T4 (1<<0) |
459 | #define ELINK_PCI_100BASE_TX (1<<1) |
460 | #define ELINK_PCI_100BASE_FX (1<<2) |
461 | #define ELINK_PCI_10BASE_T (1<<3) |
462 | #define ELINK_PCI_BNC (1<<4) |
463 | #define ELINK_PCI_AUI (1<<5) |
464 | #define ELINK_PCI_100BASE_MII (1<<6) |
465 | #define ELINK_PCI_INTERNAL_VCO (1<<8) |
466 | |
467 | #define ELINK_PCI_MEDIAMASK (ELINK_PCI_100BASE_T4|ELINK_PCI_100BASE_TX| \ |
468 | ELINK_PCI_100BASE_FX|ELINK_PCI_10BASE_T| \ |
469 | ELINK_PCI_BNC|ELINK_PCI_AUI| \ |
470 | ELINK_PCI_100BASE_MII) |
471 | |
472 | #define ELINK_RUNNER_MII_RESET 0x4000 |
473 | #define ELINK_RUNNER_ENABLE_MII 0x8000 |
474 | |
475 | /* |
476 | * FIFO Status (Window 4) |
477 | * |
478 | * Supports FIFO diagnostics |
479 | * |
480 | * Window 4/Port 0x04.1 |
481 | * |
482 | * 15: 1=RX receiving (RO). Set when a packet is being received |
483 | * into the RX FIFO. |
484 | * 14: Reserved |
485 | * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. |
486 | * Requires RX Reset or Global Reset command to recover. |
487 | * It is generated when you read past the end of a packet - |
488 | * reading past what has been received so far will give bad |
489 | * data. |
490 | * 12: 1=RX status overrun (RO). Set when there are already 8 |
491 | * packets in the RX FIFO. While this bit is set, no additional |
492 | * packets are received. Requires no action on the part of |
493 | * the host. The condition is cleared once a packet has been |
494 | * read out of the RX FIFO. |
495 | * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there |
496 | * may not be an overrun packet yet). While this bit is set, |
497 | * no additional packets will be received (some additional |
498 | * bytes can still be pending between the wire and the RX |
499 | * FIFO). Requires no action on the part of the host. The |
500 | * condition is cleared once a few bytes have been read out |
501 | * from the RX FIFO. |
502 | * 10: 1=TX overrun (RO). Generates adapter failure interrupt. |
503 | * Requires TX Reset or Global Reset command to recover. |
504 | * Disables Transmitter. |
505 | * 9-8: Unassigned. |
506 | * 7-0: Built in self test bits for the RX and TX FIFO's. |
507 | */ |
508 | #define FIFOS_RX_RECEIVING (u_int16_t) 0x8000 |
509 | #define FIFOS_RX_UNDERRUN (u_int16_t) 0x2000 |
510 | #define FIFOS_RX_STATUS_OVERRUN (u_int16_t) 0x1000 |
511 | #define FIFOS_RX_OVERRUN (u_int16_t) 0x0800 |
512 | #define FIFOS_TX_OVERRUN (u_int16_t) 0x0400 |
513 | |
514 | /* |
515 | * ISA/eisa CONFIG_CNTRL media-present bits. |
516 | */ |
517 | #define ELINK_W0_CC_AUI (1<<13) |
518 | #define ELINK_W0_CC_BNC (1<<12) |
519 | #define ELINK_W0_CC_UTP (1<<9) |
520 | #define ELINK_W0_CC_MEDIAMASK (ELINK_W0_CC_AUI|ELINK_W0_CC_BNC| \ |
521 | ELINK_W0_CC_UTP) |
522 | |
523 | /* EEPROM state flags/commands */ |
524 | #define EEPROM_BUSY (1<<15) |
525 | #define EEPROM_TST_MODE (1<<14) |
526 | |
527 | #define READ_EEPROM (1<<7) |
528 | |
529 | /* For the RoadRunner chips... */ |
530 | #define WRITE_EEPROM_RR 0x100 |
531 | #define READ_EEPROM_RR 0x200 |
532 | #define ERASE_EEPROM_RR 0x300 |
533 | |
534 | /* window 4, MEDIA_STATUS bits */ |
535 | #define SQE_ENABLE 0x08 /* Enables SQE on AUI ports */ |
536 | #define JABBER_GUARD_ENABLE 0x40 |
537 | #define LINKBEAT_ENABLE 0x80 |
538 | #define DISABLE_UTP 0x0 |
539 | #define LINKBEAT_DETECT 0x800 |
540 | |
541 | /* |
542 | * Misc defines for various things. |
543 | */ |
544 | #define TAG_ADAPTER 0xd0 |
545 | #define ACTIVATE_ADAPTER_TO_CONFIG 0xff |
546 | #define ENABLE_DRQ_IRQ 0x0001 |
547 | #define MFG_ID 0x506d /* `TCM' */ |
548 | #define PROD_ID_3C509 0x5090 /* 509[0-f] */ |
549 | #define GO_WINDOW(x) bus_space_write_2(sc->sc_iot, \ |
550 | sc->sc_ioh, ELINK_COMMAND, WINDOW_SELECT|x) |
551 | |
552 | |
553 | /* Used to probe for large-packet support. */ |
554 | #define ELINK_LARGEWIN_PROBE ELINK_THRESH_DISABLE |
555 | #define ELINK_LARGEWIN_MASK 0xffc |
556 | |