1 | /* $NetBSD: pciide_i31244_reg.h,v 1.3 2005/12/11 12:22:50 christos Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 2002 Wasabi Systems, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * Written by Jason R. Thorpe for Wasabi Systems, Inc. |
8 | * |
9 | * Redistribution and use in source and binary forms, with or without |
10 | * modification, are permitted provided that the following conditions |
11 | * are met: |
12 | * 1. Redistributions of source code must retain the above copyright |
13 | * notice, this list of conditions and the following disclaimer. |
14 | * 2. Redistributions in binary form must reproduce the above copyright |
15 | * notice, this list of conditions and the following disclaimer in the |
16 | * documentation and/or other materials provided with the distribution. |
17 | * 3. All advertising materials mentioning features or use of this software |
18 | * must display the following acknowledgement: |
19 | * This product includes software developed for the NetBSD Project by |
20 | * Wasabi Systems, Inc. |
21 | * 4. The name of Wasabi Systems, Inc. may not be used to endorse |
22 | * or promote products derived from this software without specific prior |
23 | * written permission. |
24 | * |
25 | * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND |
26 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
27 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC |
29 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
30 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
31 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
32 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
33 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
34 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
35 | * POSSIBILITY OF SUCH DAMAGE. |
36 | */ |
37 | |
38 | #ifndef _DEV_PCI_PCIIDE_I31244_REG_H_ |
39 | #define _DEV_PCI_PCIIDE_I31244_REG_H_ |
40 | |
41 | /* |
42 | * Register definitions for the Intel i31244 Serial ATA Controller. |
43 | */ |
44 | |
45 | /* |
46 | * In DPA mode, the i31244 has a single 64-bit BAR. |
47 | */ |
48 | #define ARTISEA_PCI_DPA_BASE PCI_MAPREG_START |
49 | |
50 | /* |
51 | * Extended Control and Status Register 0 |
52 | */ |
53 | #define ARTISEA_PCI_SUECSR0 0x98 |
54 | #define SUECSR0_LED0_ONLY (1U << 28) /* activity on LED0 only */ |
55 | #define SUECSR0_SFSS (1U << 16) /* Superset Features |
56 | Secondary Select */ |
57 | |
58 | #define ARTISEA_PCI_SUDCSCR 0xa0 |
59 | #define SUDCSCR_DMA_WCAE 0x02 /* Write cache align enable */ |
60 | #define SUDCSCR_DMA_RCAE 0x01 /* Read cache align enable */ |
61 | |
62 | /* |
63 | * DPA mode shared registers. |
64 | */ |
65 | #define ARTISEA_SUPDIPR 0x00 /* DPA interrupt pending register */ |
66 | #define SUPDIPR_PORTSHIFT(x) ((x) * 8) |
67 | #define SUPDIPR_PHY_CS (1U << 0) /* PHY change state */ |
68 | #define SUPDIPR_PHY_RDY (1U << 1) /* PHY ready */ |
69 | #define SUPDIPR_FIFO_ERR (1U << 2) /* FIFO error */ |
70 | #define SUPDIPR_ERR_RCVD (1U << 3) /* ERR received */ |
71 | #define SUPDIPR_U_FIS_R (1U << 4) /* unrecog. FIS reception */ |
72 | #define SUPDIPR_DATA_I (1U << 5) /* data integrity */ |
73 | #define SUPDIPR_CRC_ED (1U << 6) /* CRC error detected */ |
74 | #define SUPDIPR_IDE (1U << 7) /* IDE interrupt */ |
75 | |
76 | #define ARTISEA_SUPDIMR 0x04 /* DPA interrupt mask register */ |
77 | /* See SUPDIPR bits. */ |
78 | |
79 | /* |
80 | * DPA mode offset to per-port registers. |
81 | */ |
82 | #define ARTISEA_DPA_PORT_BASE(x) (((x) + 1) * 0x200) |
83 | |
84 | /* |
85 | * DPA mode per-port registers. |
86 | */ |
87 | #define ARTISEA_SUPDDR 0x00 /* DPA data port register */ |
88 | /* ATA/ATAPI compatible */ |
89 | |
90 | #define ARTISEA_SUPDER 0x04 /* DPA error register */ |
91 | /* ATA/ATAPI compatible */ |
92 | |
93 | #define ARTISEA_SUPDFR 0x06 /* DPA features register */ |
94 | /* ATA/ATAPI compatible */ |
95 | |
96 | #define ARTISEA_SUPDCSR 0x08 /* DPA sector count register */ |
97 | /* ATA/ATAPI compatible */ |
98 | |
99 | #define ARTISEA_SUPDSNR 0x0c /* DPA sector number register */ |
100 | /* ATA/ATAPI compatible */ |
101 | |
102 | #define ARTISEA_SUPDCLR 0x10 /* DPA cylinder low register */ |
103 | /* ATA/ATAPI compatible */ |
104 | |
105 | #define ARTISEA_SUPDCHR 0x14 /* DPA cylinder high register */ |
106 | /* ATA/ATAPI compatible */ |
107 | |
108 | #define ARTISEA_SUPDDHR 0x18 /* DPA device/head register */ |
109 | /* ATA/ATAPI compatible */ |
110 | |
111 | #define ARTISEA_SUPDSR 0x1c /* DPA status register */ |
112 | /* ATA/ATAPI compatible */ |
113 | |
114 | #define ARTISEA_SUPDCR 0x1d /* DPA command register */ |
115 | /* ATA/ATAPI compatible */ |
116 | |
117 | #define ARTISEA_SUPDASR 0x28 /* DPA alt. status register */ |
118 | /* ATA/ATAPI compatible */ |
119 | |
120 | #define ARTISEA_SUPDDCTLR 0x29 /* DPA device control register */ |
121 | /* ATA/ATAPI compatible */ |
122 | |
123 | #define ARTISEA_SUPDUDDTPR 0x64 /* DPA upper DMA desc. table pointer */ |
124 | |
125 | #define ARTISEA_SUPDUDDPR 0x6c /* DPA upper DMA data buffer pointer */ |
126 | |
127 | #define ARTISEA_SUPDDCMDR 0x70 /* DPA DMA command register */ |
128 | /* Almost compatible with PCI IDE, but not quite. */ |
129 | #define SUPDDCMDR_START (1U << 0) /* start DMA transfer (c) */ |
130 | #define SUPDDCMDR_WRITE (1U << 3) /* write *to memory* (c) */ |
131 | #define SUPDDCMDR_DP_DMA_ACT (1U << 8) /* first party DMA active */ |
132 | #define SUPDDCMDR_FP_DMA_DIR (1U << 9) /* 1 = host->device */ |
133 | |
134 | #define ARTISEA_SUPDDSR 0x72 /* DPA DMA status register */ |
135 | /* PCI IDE compatible */ |
136 | |
137 | #define ARTISEA_SUPDDDTPR 0x74 /* DPA DMA desc. table pointer */ |
138 | |
139 | #define ARTISEA_SUPERSET_DPA_OFF 0x100 /* offset to Superset regs: DPA mode */ |
140 | |
141 | #define ARTISEA_SUPDSSSR 0x000 /* DPA SATA SStatus register */ |
142 | #define SUPDSSSR_IPM_NP (0 << 8) /* device not present */ |
143 | #define SUPDSSSR_IPM_ACT (1U << 8) /* active state */ |
144 | #define SUPDSSSR_IPM_PARTIAL (2U << 8) /* partial power mgmt */ |
145 | #define SUPDSSSR_IPM_SLUMBER (6U << 8) /* slumber power mgmt */ |
146 | #define SUPDSSSR_SPD_NP (0 << 4) /* device not present */ |
147 | #define SUPDSSSR_SPD_G1 (1U << 4) /* Generation 1 speed */ |
148 | #define SUPDSSSR_DET_NP (0 << 0) /* device not present */ |
149 | #define SUPDSSSR_DET_PHY_CNE (1U << 0) /* PHY comm. not established */ |
150 | #define SUPDSSSR_DET_PHY_CE (3U << 0) /* PHY comm. established */ |
151 | #define SUPDSSSR_DET_PHY_LOOP (4U << 0) /* loopback mode */ |
152 | |
153 | #define ARTISEA_SUPDSSER 0x004 /* DPA SATA SError register */ |
154 | #define SUPDSSER_DIAG_F (1U << 25) /* invalid FIS type */ |
155 | #define SUPDSSER_DIAG_T (1U << 24) /* not implemented */ |
156 | #define SUPDSSER_DIAG_S (1U << 23) /* not implemented */ |
157 | #define SUPDSSER_DIAG_H (1U << 22) /* handshake error */ |
158 | #define SUPDSSER_DIAG_C (1U << 21) /* CRC error */ |
159 | #define SUPDSSER_DIAG_D (1U << 20) /* disparity error */ |
160 | #define SUPDSSER_DIAG_B (1U << 19) /* not implemented */ |
161 | #define SUPDSSER_DIAG_W (1U << 18) /* comm wake */ |
162 | #define SUPDSSER_DIAG_I (1U << 17) /* not implemented */ |
163 | #define SUPDSSER_DIAG_N (1U << 16) /* PHY RDY state change */ |
164 | #define SUPDSSER_ERR_E (1U << 11) /* internal error */ |
165 | #define SUPDSSER_ERR_P (1U << 10) /* protocol error */ |
166 | #define SUPDSSER_ERR_C (1U << 9) /* non-recovered comm. */ |
167 | #define SUPDSSER_ERR_T (1U << 8) /* non-recovered TDIE */ |
168 | #define SUPDSSER_ERR_M (1U << 1) /* recovered comm. */ |
169 | #define SUPDSSER_ERR_I (1U << 0) /* not implemented */ |
170 | |
171 | #define ARTISEA_SUPDSSCR 0x008 /* DPA SATA SControl register */ |
172 | #define SUPDSSCR_IPM_ANY (0 << 8) /* no IPM mode restrictions */ |
173 | #define SUPDSSCR_IPM_NO_PARTIAL (1U << 8) /* no PARTIAL mode */ |
174 | #define SUPDSSCR_IPM_NO_SLUMBER (2U << 8) /* no SLUMBER mode */ |
175 | #define SUPDSSCR_IPM_NONE (3U << 8) /* no PM allowed */ |
176 | #define SUPDSSCR_SPD_ANY (0 << 4) /* no speed restrictions */ |
177 | #define SUPDSSCR_SPD_G1 (1U << 4) /* <= Generation 1 */ |
178 | #define SUPDSSCR_DET_NORM (0 << 0) /* normal operation */ |
179 | #define SUPDSSCR_DET_INIT (1U << 0) /* comm. init */ |
180 | #define SUPDSSCR_DET_DISABLE (4U << 0) /* disable interface */ |
181 | |
182 | #define ARTISEA_SUPDSDBR 0x00c /* DPA Set Device Bits register */ |
183 | |
184 | #define ARTISEA_SUPDPFR 0x040 /* DPA PHY feature register */ |
185 | #define SUPDPFR_SSCEN (1U << 16) /* SSC enable */ |
186 | #define SUPDPFR_FVS (1U << 14) /* full voltage swing */ |
187 | |
188 | #define ARTISEA_SUPDBFCSR 0x044 /* DPA BIST FIS ctrl/stat register */ |
189 | #define SUPDBFCSR_PAT_D21_5 (0 << 30) /* D21.5s */ |
190 | #define SUPDBFCSR_PAT_D24_3 (1U << 30) /* D24.3s */ |
191 | #define SUPDBFCSR_PAT_D10_2 (2U << 30) /* D10.2 / K28.5 */ |
192 | #define SUPDBFCSR_PAT_COUNT (3U << 30) /* counting */ |
193 | #define SUPDBFCSR_CS_D21_5 (0 << 28) |
194 | #define SUPDBFCSR_CS_D24_3 (1U << 28) |
195 | #define SUPDBFCSR_CS_D10_2 (2U << 28) |
196 | #define SUPDBFCSR_CS_COUNT (3U << 30) |
197 | #define SUPDBFCSR_CLEAR_ERRS (1U << 25) /* clear errors/frames */ |
198 | #define SUPDBFCSR_CE (1U << 24) /* BIST check enable */ |
199 | #define SUPDBFCSR_PE (1U << 23) /* BIST pattern enable */ |
200 | #define SUPDBFCSR_K28_5 ((1U << 16) | \ |
201 | (1U << 8) /* send K28.5s */ |
202 | #define SUPDBFCSR_BIST_ACT_RX (1U << 15) /* BIST Act. FIS was rx'd */ |
203 | #define SUPDBFCSR_BIST_ACT_RX_TO (1U << 14) /* ...with transmit-only */ |
204 | #define SUPDBFCSR_BIST_ACT_RX_AB (1U << 13) /* ...with align-bypass */ |
205 | #define SUPDBFCSR_BIST_ACT_RX_SB (1U << 12) /* ...with scrambling-bypass */ |
206 | #define SUPDBFCSR_BIST_ACT_RX_RT (1U << 11) /* ...with retimed */ |
207 | #define SUPDBFCSR_BIST_ACT_RX_P (1U << 10) /* ...with primitive */ |
208 | #define SUPDBFCSR_BIST_ACT_RX_AFEL (1U << 9) /* ...with AFE loopback */ |
209 | #define SUPDBFCSR_BIST_ACT_TX (1U << 7) /* send BIST Act. FIS */ |
210 | #define SUPDBFCSR_BIST_ACT_TX_TO (1U << 6) /* ...with transmit-only */ |
211 | #define SUPDBFCSR_BIST_ACT_TX_AB (1U << 5) /* ...with align-bypass */ |
212 | #define SUPDBFCSR_BIST_ACT_TX_SB (1U << 4) /* ...with scrambling-bypass */ |
213 | #define SUPDBFCSR_BIST_ACT_TX_RT (1U << 3) /* ...with retimed */ |
214 | #define SUPDBFCSR_BIST_ACT_TX_P (1U << 2) /* ...with primitive */ |
215 | #define SUPDBFCSR_BIST_ACT_TX_AFEL (1U << 1) /* ...with AFE loopback */ |
216 | #define SUPDBFCSR_INIT_NE_TO (1U << 0) /* init. near-end tx-only */ |
217 | |
218 | #define ARTISEA_SUPDBER 0x048 /* DPA BIST errors register */ |
219 | |
220 | #define ARTISEA_SUPDBFR 0x04c /* DPA BIST frames register */ |
221 | |
222 | #define ARTISEA_SUPDHBDLR 0x050 /* DPA Host BIST data low register */ |
223 | |
224 | #define ARTISEA_SUPDHBDHR 0x054 /* DPA Host BIST data high register */ |
225 | |
226 | #define ARTISEA_SUPDDBDLR 0x058 /* DPA Device BIST data low */ |
227 | |
228 | #define ARTISEA_SUPDDBDHR 0x05c /* DPA Device BIST data high */ |
229 | |
230 | #define ARTISEA_SUPDDSFCSR 0x068 /* DPA DMA setup FIS ctrl/stat */ |
231 | #define SUPDDSFCSR_DIR (1U << 31) /* First Party setup FIS |
232 | word 0 direction bit |
233 | (1 == tx -> rx) */ |
234 | #define SUPDDSFCSR_INTR (1U << 30) /* rcvd's First Party setup |
235 | FIS with I bit set */ |
236 | #define SUPDDSFCSR_START_SETUP (1U << 28) /* send DMA setup FIS */ |
237 | #define SUPDDSFCSR_EN_FP_AP (1U << 27) /* enab. FP DMA auto-process */ |
238 | #define SUPDDSFCSR_ABORT_TSM (1U << 24) /* abort xport/link SMs */ |
239 | |
240 | #define ARTISEA_SUPDHDBILR 0x06c /* DPA Host DMA Buff. Id low */ |
241 | |
242 | #define ARTISEA_SUPDHDBIHR 0x070 /* DPA Host DMA Buff. Id high */ |
243 | |
244 | #define ARTISEA_SUPDHRDR0 0x074 /* DPA Host Resvd. DWORD 0 */ |
245 | |
246 | #define ARTISEA_SUPDHDBOR 0x078 /* DPA Host DMA Buff. offset */ |
247 | |
248 | #define ARTISEA_SUPDHDTCR 0x07c /* DPA Host DMA xfer count */ |
249 | |
250 | #define ARTISEA_SUPDHRDR1 0x080 /* DPA Host Resvd. DWORD 1 */ |
251 | |
252 | #define ARTISEA_SUPDDDBILR 0x084 /* DPA Device DMA Buff. Id low */ |
253 | |
254 | #define ARTISEA_SUPDDDBIHR 0x088 /* DPA Device DMA Buff. Id high */ |
255 | |
256 | #define ARTISEA_SUPDDRDR0 0x08c /* DPA Device Resvd. DWORD 0 */ |
257 | |
258 | #define ARTISEA_SUPDDDBOR 0x090 /* DPA Device DMA Buff. offset */ |
259 | |
260 | #define ARTISEA_SUPDDTCR 0x094 /* DPA Device DMA xfer count */ |
261 | |
262 | #define ARTISEA_SUPDDRDR1 0x09c /* DPA Device Resvd. DWORD 1 */ |
263 | |
264 | #endif /* _DEV_PCI_PCIIDE_I31244_REG_H_ */ |
265 | |