1 | /* $NetBSD: nouveau_engine_dmaobj_nv50.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_dmaobj_nv50.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $" ); |
29 | |
30 | #include <core/gpuobj.h> |
31 | #include <core/class.h> |
32 | |
33 | #include <subdev/fb.h> |
34 | #include <engine/dmaobj.h> |
35 | |
36 | struct nv50_dmaeng_priv { |
37 | struct nouveau_dmaeng base; |
38 | }; |
39 | |
40 | static int |
41 | nv50_dmaobj_bind(struct nouveau_dmaeng *dmaeng, |
42 | struct nouveau_object *parent, |
43 | struct nouveau_dmaobj *dmaobj, |
44 | struct nouveau_gpuobj **pgpuobj) |
45 | { |
46 | u32 flags0 = nv_mclass(dmaobj); |
47 | u32 flags5 = 0x00000000; |
48 | int ret; |
49 | |
50 | if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { |
51 | switch (nv_mclass(parent->parent)) { |
52 | case NV50_CHANNEL_DMA_CLASS: |
53 | case NV84_CHANNEL_DMA_CLASS: |
54 | case NV50_CHANNEL_IND_CLASS: |
55 | case NV84_CHANNEL_IND_CLASS: |
56 | case NV50_DISP_MAST_CLASS: |
57 | case NV84_DISP_MAST_CLASS: |
58 | case NV94_DISP_MAST_CLASS: |
59 | case NVA0_DISP_MAST_CLASS: |
60 | case NVA3_DISP_MAST_CLASS: |
61 | case NV50_DISP_SYNC_CLASS: |
62 | case NV84_DISP_SYNC_CLASS: |
63 | case NV94_DISP_SYNC_CLASS: |
64 | case NVA0_DISP_SYNC_CLASS: |
65 | case NVA3_DISP_SYNC_CLASS: |
66 | case NV50_DISP_OVLY_CLASS: |
67 | case NV84_DISP_OVLY_CLASS: |
68 | case NV94_DISP_OVLY_CLASS: |
69 | case NVA0_DISP_OVLY_CLASS: |
70 | case NVA3_DISP_OVLY_CLASS: |
71 | break; |
72 | default: |
73 | return -EINVAL; |
74 | } |
75 | } |
76 | |
77 | if (!(dmaobj->conf0 & NV50_DMA_CONF0_ENABLE)) { |
78 | if (dmaobj->target == NV_MEM_TARGET_VM) { |
79 | dmaobj->conf0 = NV50_DMA_CONF0_PRIV_VM; |
80 | dmaobj->conf0 |= NV50_DMA_CONF0_PART_VM; |
81 | dmaobj->conf0 |= NV50_DMA_CONF0_COMP_VM; |
82 | dmaobj->conf0 |= NV50_DMA_CONF0_TYPE_VM; |
83 | } else { |
84 | dmaobj->conf0 = NV50_DMA_CONF0_PRIV_US; |
85 | dmaobj->conf0 |= NV50_DMA_CONF0_PART_256; |
86 | dmaobj->conf0 |= NV50_DMA_CONF0_COMP_NONE; |
87 | dmaobj->conf0 |= NV50_DMA_CONF0_TYPE_LINEAR; |
88 | } |
89 | } |
90 | |
91 | flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_COMP) << 22; |
92 | flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_TYPE) << 22; |
93 | flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_PRIV); |
94 | flags5 |= (dmaobj->conf0 & NV50_DMA_CONF0_PART); |
95 | |
96 | switch (dmaobj->target) { |
97 | case NV_MEM_TARGET_VM: |
98 | flags0 |= 0x00000000; |
99 | break; |
100 | case NV_MEM_TARGET_VRAM: |
101 | flags0 |= 0x00010000; |
102 | break; |
103 | case NV_MEM_TARGET_PCI: |
104 | flags0 |= 0x00020000; |
105 | break; |
106 | case NV_MEM_TARGET_PCI_NOSNOOP: |
107 | flags0 |= 0x00030000; |
108 | break; |
109 | default: |
110 | return -EINVAL; |
111 | } |
112 | |
113 | switch (dmaobj->access) { |
114 | case NV_MEM_ACCESS_VM: |
115 | break; |
116 | case NV_MEM_ACCESS_RO: |
117 | flags0 |= 0x00040000; |
118 | break; |
119 | case NV_MEM_ACCESS_WO: |
120 | case NV_MEM_ACCESS_RW: |
121 | flags0 |= 0x00080000; |
122 | break; |
123 | } |
124 | |
125 | ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); |
126 | if (ret == 0) { |
127 | nv_wo32(*pgpuobj, 0x00, flags0); |
128 | nv_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->limit)); |
129 | nv_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->start)); |
130 | nv_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->limit) << 24 | |
131 | upper_32_bits(dmaobj->start)); |
132 | nv_wo32(*pgpuobj, 0x10, 0x00000000); |
133 | nv_wo32(*pgpuobj, 0x14, flags5); |
134 | } |
135 | |
136 | return ret; |
137 | } |
138 | |
139 | static int |
140 | nv50_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
141 | struct nouveau_oclass *oclass, void *data, u32 size, |
142 | struct nouveau_object **pobject) |
143 | { |
144 | struct nv50_dmaeng_priv *priv; |
145 | int ret; |
146 | |
147 | ret = nouveau_dmaeng_create(parent, engine, oclass, &priv); |
148 | *pobject = nv_object(priv); |
149 | if (ret) |
150 | return ret; |
151 | |
152 | nv_engine(priv)->sclass = nouveau_dmaobj_sclass; |
153 | priv->base.bind = nv50_dmaobj_bind; |
154 | return 0; |
155 | } |
156 | |
157 | struct nouveau_oclass |
158 | nv50_dmaeng_oclass = { |
159 | .handle = NV_ENGINE(DMAOBJ, 0x50), |
160 | .ofuncs = &(struct nouveau_ofuncs) { |
161 | .ctor = nv50_dmaeng_ctor, |
162 | .dtor = _nouveau_dmaeng_dtor, |
163 | .init = _nouveau_dmaeng_init, |
164 | .fini = _nouveau_dmaeng_fini, |
165 | }, |
166 | }; |
167 | |