1 | /* |
2 | * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting |
3 | * Copyright (c) 2002-2008 Atheros Communications, Inc. |
4 | * |
5 | * Permission to use, copy, modify, and/or distribute this software for any |
6 | * purpose with or without fee is hereby granted, provided that the above |
7 | * copyright notice and this permission notice appear in all copies. |
8 | * |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
16 | * |
17 | * $Id: ar5416reg.h,v 1.5 2011/08/01 10:21:32 jmcneill Exp $ |
18 | */ |
19 | #ifndef _DEV_ATH_AR5416REG_H |
20 | #define _DEV_ATH_AR5416REG_H |
21 | |
22 | #include "ar5212/ar5212reg.h" |
23 | |
24 | /* |
25 | * Register added starting with the AR5416 |
26 | */ |
27 | #define AR_MIRT 0x0020 /* interrupt rate threshold */ |
28 | #define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ |
29 | #define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ |
30 | #define AR_GTXTO 0x0064 /* global transmit timeout */ |
31 | #define AR_GTTM 0x0068 /* global transmit timeout mode */ |
32 | #define AR_CST 0x006C /* carrier sense timeout */ |
33 | #define AR_MAC_LED 0x1f04 /* LED control */ |
34 | #define AR_WA 0x4004 /* PCIE work-arounds */ |
35 | #define AR_PCIE_PM_CTRL 0x4014 |
36 | #define AR_AHB_MODE 0x4024 /* AHB mode for dma */ |
37 | #define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ |
38 | #define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ |
39 | #define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ |
40 | #define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ |
41 | #define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ |
42 | #define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ |
43 | #define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ |
44 | #define AR5416_PCIE_SERDES 0x4040 |
45 | #define AR5416_PCIE_SERDES2 0x4044 |
46 | #define AR_GPIO_IN_OUT 0x4048 /* GPIO input/output register */ |
47 | #define AR_GPIO_OE_OUT 0x404c /* GPIO output enable register */ |
48 | #define AR_GPIO_INTR_POL 0x4050 /* GPIO interrupt polarity */ |
49 | #define AR_GPIO_INPUT_EN_VAL 0x4054 /* GPIO input enable and value */ |
50 | #define AR_GPIO_INPUT_MUX1 0x4058 |
51 | #define AR_GPIO_INPUT_MUX2 0x405c |
52 | #define AR_GPIO_OUTPUT_MUX1 0x4060 |
53 | #define AR_GPIO_OUTPUT_MUX2 0x4064 |
54 | #define AR_GPIO_OUTPUT_MUX3 0x4068 |
55 | #define AR_EEPROM_STATUS_DATA 0x407c |
56 | #define AR_OBS 0x4080 |
57 | #define AR_RTC_RC 0x7000 /* reset control */ |
58 | #define AR_RTC_PLL_CONTROL 0x7014 |
59 | #define AR_RTC_RESET 0x7040 /* RTC reset register */ |
60 | #define AR_RTC_STATUS 0x7044 /* system sleep status */ |
61 | #define AR_RTC_SLEEP_CLK 0x7048 |
62 | #define AR_RTC_FORCE_WAKE 0x704c /* control MAC force wake */ |
63 | #define AR_RTC_INTR_CAUSE 0x7050 /* RTC interrupt cause/clear */ |
64 | #define AR_RTC_INTR_ENABLE 0x7054 /* RTC interrupt enable */ |
65 | #define AR_RTC_INTR_MASK 0x7058 /* RTC interrupt mask */ |
66 | /* AR9280: rf long shift registers */ |
67 | #define AR_AN_RF2G1_CH0 0x7810 |
68 | #define AR_AN_RF5G1_CH0 0x7818 |
69 | #define AR_AN_RF2G1_CH1 0x7834 |
70 | #define AR_AN_RF5G1_CH1 0x783C |
71 | #define AR_AN_TOP2 0x7894 |
72 | #define AR_AN_SYNTH9 0x7868 |
73 | #define AR9285_AN_RF2G1 0x7820 |
74 | #define AR9285_AN_RF2G2 0x7824 |
75 | #define AR9285_AN_RF2G3 0x7828 |
76 | #define AR9285_AN_RF2G4 0x782C |
77 | #define AR9285_AN_RF2G6 0x7834 |
78 | #define AR9285_AN_RF2G7 0x7838 |
79 | #define AR9285_AN_RF2G8 0x783C |
80 | #define AR9285_AN_RF2G9 0x7840 |
81 | #define AR9285_AN_RXTXBB1 0x7854 |
82 | #define AR9285_AN_TOP2 0x7868 |
83 | #define AR9285_AN_TOP3 0x786c |
84 | #define AR9285_AN_TOP4 0x7870 |
85 | #define AR9285_AN_TOP4_DEFAULT 0x10142c00 |
86 | |
87 | #define AR_RESET_TSF 0x8020 |
88 | #define AR_RXFIFO_CFG 0x8114 |
89 | #define AR_PHY_ERR_1 0x812c |
90 | #define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ |
91 | #define AR_PHY_ERR_2 0x8134 |
92 | #define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ |
93 | #define AR_TSFOOR_THRESHOLD 0x813c |
94 | #define AR_PHY_ERR_3 0x8168 |
95 | #define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */ |
96 | #define AR_TXOP_X 0x81ec /* txop for legacy non-qos */ |
97 | #define AR_TXOP_0_3 0x81f0 /* txop for various tid's */ |
98 | #define AR_TXOP_4_7 0x81f4 |
99 | #define AR_TXOP_8_11 0x81f8 |
100 | #define AR_TXOP_12_15 0x81fc |
101 | /* generic timers based on tsf - all uS */ |
102 | #define AR_NEXT_TBTT 0x8200 |
103 | #define AR_NEXT_DBA 0x8204 |
104 | #define AR_NEXT_SWBA 0x8208 |
105 | #define AR_NEXT_CFP 0x8208 |
106 | #define AR_NEXT_HCF 0x820C |
107 | #define AR_NEXT_TIM 0x8210 |
108 | #define AR_NEXT_DTIM 0x8214 |
109 | #define AR_NEXT_QUIET 0x8218 |
110 | #define AR_NEXT_NDP 0x821C |
111 | #define AR5416_BEACON_PERIOD 0x8220 |
112 | #define AR_DBA_PERIOD 0x8224 |
113 | #define AR_SWBA_PERIOD 0x8228 |
114 | #define AR_HCF_PERIOD 0x822C |
115 | #define AR_TIM_PERIOD 0x8230 |
116 | #define AR_DTIM_PERIOD 0x8234 |
117 | #define AR_QUIET_PERIOD 0x8238 |
118 | #define AR_NDP_PERIOD 0x823C |
119 | #define AR_TIMER_MODE 0x8240 |
120 | #define AR_SLP32_MODE 0x8244 |
121 | #define AR_SLP32_WAKE 0x8248 |
122 | #define AR_SLP32_INC 0x824c |
123 | #define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */ |
124 | #define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */ |
125 | #define AR_SLP_MIB_CTRL 0x8258 |
126 | #define AR_2040_MODE 0x8318 |
127 | #define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ |
128 | #define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ |
129 | #define AR_PCU_TXBUF_CTRL 0x8340 |
130 | #define AR_PCU_MISC_MODE2 0x8344 |
131 | |
132 | /* DMA & PCI Registers in PCI space (usable during sleep)*/ |
133 | #define AR_RC_AHB 0x00000001 /* AHB reset */ |
134 | #define AR_RC_APB 0x00000002 /* APB reset */ |
135 | #define AR_RC_HOSTIF 0x00000100 /* host interface reset */ |
136 | |
137 | #define AR_MIRT_VAL 0x0000ffff /* in uS */ |
138 | #define AR_MIRT_VAL_S 16 |
139 | |
140 | #define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */ |
141 | #define AR_TIMT_LAST_S 0 |
142 | #define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */ |
143 | #define AR_TIMT_FIRST_S 16 |
144 | |
145 | #define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */ |
146 | #define AR_RIMT_LAST_S 0 |
147 | #define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */ |
148 | #define AR_RIMT_FIRST_S 16 |
149 | |
150 | #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) |
151 | #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) |
152 | #define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit |
153 | |
154 | #define AR_GTTM_USEC 0x00000001 // usec strobe |
155 | #define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle |
156 | #define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low |
157 | #define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe |
158 | |
159 | #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) |
160 | #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) |
161 | #define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit |
162 | |
163 | /* MAC tx DMA size config */ |
164 | #define AR_TXCFG_DMASZ_MASK 0x00000003 |
165 | #define AR_TXCFG_DMASZ_4B 0 |
166 | #define AR_TXCFG_DMASZ_8B 1 |
167 | #define AR_TXCFG_DMASZ_16B 2 |
168 | #define AR_TXCFG_DMASZ_32B 3 |
169 | #define AR_TXCFG_DMASZ_64B 4 |
170 | #define AR_TXCFG_DMASZ_128B 5 |
171 | #define AR_TXCFG_DMASZ_256B 6 |
172 | #define AR_TXCFG_DMASZ_512B 7 |
173 | #define AR_TXCFG_ATIM_TXPOLICY 0x00000800 |
174 | |
175 | /* MAC rx DMA size config */ |
176 | #define AR_RXCFG_DMASZ_MASK 0x00000007 |
177 | #define AR_RXCFG_DMASZ_4B 0 |
178 | #define AR_RXCFG_DMASZ_8B 1 |
179 | #define AR_RXCFG_DMASZ_16B 2 |
180 | #define AR_RXCFG_DMASZ_32B 3 |
181 | #define AR_RXCFG_DMASZ_64B 4 |
182 | #define AR_RXCFG_DMASZ_128B 5 |
183 | #define AR_RXCFG_DMASZ_256B 6 |
184 | #define AR_RXCFG_DMASZ_512B 7 |
185 | |
186 | /* MAC Led registers */ |
187 | #define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ |
188 | #define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ |
189 | #define AR_MAC_LED_MODE 0x00000380 /* LED mode select */ |
190 | #define AR_MAC_LED_MODE_S 7 |
191 | #define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ |
192 | #define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ |
193 | #define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ |
194 | #define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ |
195 | #define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ |
196 | #define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ |
197 | #define AR_MAC_LED_ASSOC 0x00000c00 |
198 | #define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */ |
199 | #define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */ |
200 | #define AR_MAC_LED_ASSOC_PEND 0x00000800 /* STA is trying to associate */ |
201 | #define AR_MAC_LED_ASSOC_S 10 |
202 | |
203 | #define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */ |
204 | #define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */ |
205 | #define AR_WA_ANALOG_SHIFT 0x00100000 |
206 | #define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */ |
207 | |
208 | #define AR_WA_DEFAULT 0x0000073f |
209 | #define AR9280_WA_DEFAULT 0x0040073f |
210 | #define AR9285_WA_DEFAULT 0x004a05cb |
211 | |
212 | #define AR_PCIE_PM_CTRL_ENA 0x00080000 |
213 | |
214 | #define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ |
215 | #define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ |
216 | #define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ |
217 | #define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ |
218 | #define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ |
219 | #define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ |
220 | #define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ |
221 | #define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ |
222 | |
223 | /* MAC PCU Registers */ |
224 | #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */ |
225 | |
226 | /* Extended PCU DIAG_SW control fields */ |
227 | #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */ |
228 | #define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */ |
229 | #define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */ |
230 | #define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */ |
231 | #define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */ |
232 | #define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */ |
233 | |
234 | #define AR_TXOP_X_VAL 0x000000FF |
235 | |
236 | #define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/ |
237 | |
238 | /* Interrupts */ |
239 | #define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ |
240 | #define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ |
241 | #define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */ |
242 | #define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */ |
243 | |
244 | #define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ |
245 | #define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ |
246 | #define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ |
247 | |
248 | #define AR_ISR_S5 0x0098 |
249 | #define AR_ISR_S5_S 0x00d8 |
250 | #define AR_ISR_S5_TIM_TIMER 0x00000010 |
251 | |
252 | #define AR_INTR_SPURIOUS 0xffffffff |
253 | #define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ |
254 | #define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ |
255 | #define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */ |
256 | #define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */ |
257 | #define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */ |
258 | |
259 | /* Interrupt Mask Registers */ |
260 | #define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ |
261 | #define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ |
262 | #define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */ |
263 | #define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */ |
264 | |
265 | #define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */ |
266 | #define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */ |
267 | |
268 | /* synchronous interrupt signals */ |
269 | #define AR_INTR_SYNC_RTC_IRQ 0x00000001 |
270 | #define AR_INTR_SYNC_MAC_IRQ 0x00000002 |
271 | #define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 |
272 | #define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 |
273 | #define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 |
274 | #define AR_INTR_SYNC_HOST1_FATAL 0x00000020 |
275 | #define AR_INTR_SYNC_HOST1_PERR 0x00000040 |
276 | #define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 |
277 | #define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 |
278 | #define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 |
279 | #define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 |
280 | #define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 |
281 | #define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 |
282 | #define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 |
283 | #define AR_INTR_SYNC_PM_ACCESS 0x00004000 |
284 | #define AR_INTR_SYNC_MAC_AWAKE 0x00008000 |
285 | #define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 |
286 | #define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 |
287 | #define AR_INTR_SYNC_ALL 0x0003FFFF |
288 | |
289 | /* default synchronous interrupt signals enabled */ |
290 | #define AR_INTR_SYNC_DEFAULT \ |
291 | (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \ |
292 | AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ |
293 | AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ |
294 | AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \ |
295 | AR_INTR_SYNC_MAC_SLEEP_ACCESS) |
296 | |
297 | #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 |
298 | #define AR_INTR_SYNC_MASK_GPIO_S 18 |
299 | |
300 | #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 |
301 | #define AR_INTR_SYNC_ENABLE_GPIO_S 18 |
302 | |
303 | #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 /* async int mask */ |
304 | #define AR_INTR_ASYNC_MASK_GPIO_S 18 |
305 | |
306 | #define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 /* GPIO interrupts */ |
307 | #define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO) |
308 | |
309 | #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 /* enable interrupts */ |
310 | #define AR_INTR_ASYNC_ENABLE_GPIO_S 18 |
311 | |
312 | /* RTC registers */ |
313 | #define AR_RTC_RC_M 0x00000003 |
314 | #define AR_RTC_RC_MAC_WARM 0x00000001 |
315 | #define AR_RTC_RC_MAC_COLD 0x00000002 |
316 | #define AR_RTC_PLL_DIV 0x0000001f |
317 | #define AR_RTC_PLL_DIV_S 0 |
318 | #define AR_RTC_PLL_DIV2 0x00000020 |
319 | #define AR_RTC_PLL_REFDIV_5 0x000000c0 |
320 | |
321 | #define AR_RTC_SOWL_PLL_DIV 0x000003ff |
322 | #define AR_RTC_SOWL_PLL_DIV_S 0 |
323 | #define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 |
324 | #define AR_RTC_SOWL_PLL_REFDIV_S 10 |
325 | #define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 |
326 | #define AR_RTC_SOWL_PLL_CLKSEL_S 14 |
327 | |
328 | #define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ |
329 | |
330 | #define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */ |
331 | #define AR_RTC_STATUS_M 0x0000003f /* RTC Status */ |
332 | #define AR_RTC_STATUS_SHUTDOWN 0x00000001 |
333 | #define AR_RTC_STATUS_ON 0x00000002 |
334 | #define AR_RTC_STATUS_SLEEP 0x00000004 |
335 | #define AR_RTC_STATUS_WAKEUP 0x00000008 |
336 | #define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */ |
337 | #define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */ |
338 | |
339 | #define AR_RTC_SLEEP_DERIVED_CLK 0x2 |
340 | |
341 | #define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ |
342 | #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ |
343 | |
344 | #define AR_RTC_PLL_CLKSEL 0x00000300 |
345 | #define AR_RTC_PLL_CLKSEL_S 8 |
346 | |
347 | /* AR9280: rf long shift registers */ |
348 | #define AR_AN_RF2G1_CH0_OB 0x03800000 |
349 | #define AR_AN_RF2G1_CH0_OB_S 23 |
350 | #define AR_AN_RF2G1_CH0_DB 0x1C000000 |
351 | #define AR_AN_RF2G1_CH0_DB_S 26 |
352 | |
353 | #define AR_AN_RF5G1_CH0_OB5 0x00070000 |
354 | #define AR_AN_RF5G1_CH0_OB5_S 16 |
355 | #define AR_AN_RF5G1_CH0_DB5 0x00380000 |
356 | #define AR_AN_RF5G1_CH0_DB5_S 19 |
357 | |
358 | #define AR_AN_RF2G1_CH1_OB 0x03800000 |
359 | #define AR_AN_RF2G1_CH1_OB_S 23 |
360 | #define AR_AN_RF2G1_CH1_DB 0x1C000000 |
361 | #define AR_AN_RF2G1_CH1_DB_S 26 |
362 | |
363 | #define AR_AN_RF5G1_CH1_OB5 0x00070000 |
364 | #define AR_AN_RF5G1_CH1_OB5_S 16 |
365 | #define AR_AN_RF5G1_CH1_DB5 0x00380000 |
366 | #define AR_AN_RF5G1_CH1_DB5_S 19 |
367 | |
368 | #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 |
369 | #define AR_AN_TOP2_XPABIAS_LVL_S 30 |
370 | #define AR_AN_TOP2_LOCALBIAS 0x00200000 |
371 | #define AR_AN_TOP2_LOCALBIAS_S 21 |
372 | #define AR_AN_TOP2_PWDCLKIND 0x00400000 |
373 | #define AR_AN_TOP2_PWDCLKIND_S 22 |
374 | |
375 | #define AR_AN_SYNTH9_REFDIVA 0xf8000000 |
376 | #define AR_AN_SYNTH9_REFDIVA_S 27 |
377 | |
378 | /* AR9285 Analog registers */ |
379 | #define AR9285_AN_RF2G1_ENPACAL 0x00000800 |
380 | #define AR9285_AN_RF2G1_ENPACAL_S 11 |
381 | #define AR9285_AN_RF2G1_PDPADRV1 0x02000000 |
382 | #define AR9285_AN_RF2G1_PDPADRV1_S 25 |
383 | #define AR9285_AN_RF2G1_PDPADRV2 0x01000000 |
384 | #define AR9285_AN_RF2G1_PDPADRV2_S 24 |
385 | #define AR9285_AN_RF2G1_PDPAOUT 0x00800000 |
386 | #define AR9285_AN_RF2G1_PDPAOUT_S 23 |
387 | |
388 | #define AR9285_AN_RF2G2_OFFCAL 0x00001000 |
389 | #define AR9285_AN_RF2G2_OFFCAL_S 12 |
390 | |
391 | #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 |
392 | #define AR9285_AN_RF2G3_PDVCCOMP_S 25 |
393 | #define AR9285_AN_RF2G3_OB_0 0x00E00000 |
394 | #define AR9285_AN_RF2G3_OB_0_S 21 |
395 | #define AR9285_AN_RF2G3_OB_1 0x001C0000 |
396 | #define AR9285_AN_RF2G3_OB_1_S 18 |
397 | #define AR9285_AN_RF2G3_OB_2 0x00038000 |
398 | #define AR9285_AN_RF2G3_OB_2_S 15 |
399 | #define AR9285_AN_RF2G3_OB_3 0x00007000 |
400 | #define AR9285_AN_RF2G3_OB_3_S 12 |
401 | #define AR9285_AN_RF2G3_OB_4 0x00000E00 |
402 | #define AR9285_AN_RF2G3_OB_4_S 9 |
403 | |
404 | #define AR9285_AN_RF2G3_DB1_0 0x000001C0 |
405 | #define AR9285_AN_RF2G3_DB1_0_S 6 |
406 | #define AR9285_AN_RF2G3_DB1_1 0x00000038 |
407 | #define AR9285_AN_RF2G3_DB1_1_S 3 |
408 | #define AR9285_AN_RF2G3_DB1_2 0x00000007 |
409 | #define AR9285_AN_RF2G3_DB1_2_S 0 |
410 | |
411 | #define AR9285_AN_RF2G4_DB1_3 0xE0000000 |
412 | #define AR9285_AN_RF2G4_DB1_3_S 29 |
413 | #define AR9285_AN_RF2G4_DB1_4 0x1C000000 |
414 | #define AR9285_AN_RF2G4_DB1_4_S 26 |
415 | |
416 | #define AR9285_AN_RF2G4_DB2_0 0x03800000 |
417 | #define AR9285_AN_RF2G4_DB2_0_S 23 |
418 | #define AR9285_AN_RF2G4_DB2_1 0x00700000 |
419 | #define AR9285_AN_RF2G4_DB2_1_S 20 |
420 | #define AR9285_AN_RF2G4_DB2_2 0x000E0000 |
421 | #define AR9285_AN_RF2G4_DB2_2_S 17 |
422 | #define AR9285_AN_RF2G4_DB2_3 0x0001C000 |
423 | #define AR9285_AN_RF2G4_DB2_3_S 14 |
424 | #define AR9285_AN_RF2G4_DB2_4 0x00003800 |
425 | #define AR9285_AN_RF2G4_DB2_4_S 11 |
426 | |
427 | #define AR9285_AN_RF2G6_CCOMP 0x00007800 |
428 | #define AR9285_AN_RF2G6_CCOMP_S 11 |
429 | #define AR9285_AN_RF2G6_OFFS 0x03f00000 |
430 | #define AR9285_AN_RF2G6_OFFS_S 20 |
431 | |
432 | #define AR9271_AN_RF2G6_OFFS 0x07f00000 |
433 | #define AR9271_AN_RF2G6_OFFS_S 20 |
434 | |
435 | #define AR9285_AN_RF2G7_PWDDB 0x00000002 |
436 | #define AR9285_AN_RF2G7_PWDDB_S 1 |
437 | #define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000 |
438 | #define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29 |
439 | |
440 | #define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000 |
441 | #define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14 |
442 | |
443 | #define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020 |
444 | #define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5 |
445 | #define AR9285_AN_RXTXBB1_PDV2I 0x00000080 |
446 | #define AR9285_AN_RXTXBB1_PDV2I_S 7 |
447 | #define AR9285_AN_RXTXBB1_PDDACIF 0x00000100 |
448 | #define AR9285_AN_RXTXBB1_PDDACIF_S 8 |
449 | #define AR9285_AN_RXTXBB1_SPARE9 0x00000001 |
450 | #define AR9285_AN_RXTXBB1_SPARE9_S 0 |
451 | |
452 | #define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C |
453 | #define AR9285_AN_TOP3_XPABIAS_LVL_S 2 |
454 | #define AR9285_AN_TOP3_PWDDAC 0x00800000 |
455 | #define AR9285_AN_TOP3_PWDDAC_S 23 |
456 | |
457 | /* Sleep control */ |
458 | #define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ |
459 | #define AR5416_SLEEP1_CAB_TIMEOUT_S 22 |
460 | |
461 | #define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ |
462 | #define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 |
463 | |
464 | /* Sleep Registers */ |
465 | #define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */ |
466 | #define AR_SLP32_ENA 0x00100000 |
467 | #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */ |
468 | |
469 | #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */ |
470 | |
471 | #define AR_SLP32_TST_INC 0x000FFFFF |
472 | |
473 | #define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */ |
474 | #define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */ |
475 | |
476 | #define AR_TIMER_MODE_TBTT 0x00000001 |
477 | #define AR_TIMER_MODE_DBA 0x00000002 |
478 | #define AR_TIMER_MODE_SWBA 0x00000004 |
479 | #define AR_TIMER_MODE_HCF 0x00000008 |
480 | #define AR_TIMER_MODE_TIM 0x00000010 |
481 | #define AR_TIMER_MODE_DTIM 0x00000020 |
482 | #define AR_TIMER_MODE_QUIET 0x00000040 |
483 | #define AR_TIMER_MODE_NDP 0x00000080 |
484 | #define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700 |
485 | #define AR_TIMER_MODE_OVERFLOW_INDEX_S 8 |
486 | #define AR_TIMER_MODE_THRESH 0xFFFFF000 |
487 | #define AR_TIMER_MODE_THRESH_S 12 |
488 | |
489 | /* PCU Misc modes */ |
490 | #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */ |
491 | #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */ |
492 | #define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */ |
493 | #define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */ |
494 | #define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */ |
495 | #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */ |
496 | #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */ |
497 | #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */ |
498 | #define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */ |
499 | #define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit upto tbtt+20 uS */ |
500 | #define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ |
501 | #define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ |
502 | |
503 | #define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 |
504 | |
505 | /* GPIO Interrupt */ |
506 | #define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ |
507 | #define AR_INTR_GPIO_S 20 |
508 | |
509 | #define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */ |
510 | #define AR_GPIO_OUT_VAL 0x000FFC00 |
511 | #define AR_GPIO_OUT_VAL_S 10 |
512 | #define AR_GPIO_INTR_CTRL 0x3FF00000 |
513 | #define AR_GPIO_INTR_CTRL_S 20 |
514 | |
515 | #define AR_GPIO_IN_VAL 0x0FFFC000 /* pre-9280 */ |
516 | #define AR_GPIO_IN_VAL_S 14 |
517 | #define AR928X_GPIO_IN_VAL 0x000FFC00 |
518 | #define AR928X_GPIO_IN_VAL_S 10 |
519 | #define AR9285_GPIO_IN_VAL 0x00FFF000 |
520 | #define AR9285_GPIO_IN_VAL_S 12 |
521 | |
522 | #define AR_GPIO_OE_OUT_DRV 0x3 /* 2 bit mask shifted by 2*bitpos */ |
523 | #define AR_GPIO_OE_OUT_DRV_NO 0x0 /* tristate */ |
524 | #define AR_GPIO_OE_OUT_DRV_LOW 0x1 /* drive if low */ |
525 | #define AR_GPIO_OE_OUT_DRV_HI 0x2 /* drive if high */ |
526 | #define AR_GPIO_OE_OUT_DRV_ALL 0x3 /* drive always */ |
527 | |
528 | #define AR_GPIO_INTR_POL_VAL 0x1FFF |
529 | #define AR_GPIO_INTR_POL_VAL_S 0 |
530 | |
531 | #define AR_GPIO_JTAG_DISABLE 0x00020000 |
532 | |
533 | #define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ |
534 | |
535 | #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF |
536 | #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 |
537 | #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 |
538 | |
539 | /* Eeprom defines */ |
540 | #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff |
541 | #define AR_EEPROM_STATUS_DATA_VAL_S 0 |
542 | #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 |
543 | #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 |
544 | #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 |
545 | #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 |
546 | |
547 | #define AR_SREV_REVISION_OWL_10 0x08 |
548 | #define AR_SREV_REVISION_OWL_20 0x09 |
549 | #define AR_SREV_REVISION_OWL_22 0x0a |
550 | |
551 | #define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ |
552 | #define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ |
553 | #define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ |
554 | #define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ |
555 | |
556 | /* Test macro for owl 1.0 */ |
557 | #define IS_5416V1(_ah) ((_ah)->ah_macRev == AR_SREV_REVISION_OWL_10) |
558 | #define IS_5416V2(_ah) ((_ah)->ah_macRev >= AR_SREV_REVISION_OWL_20) |
559 | #define IS_5416V2_2(_ah) ((_ah)->ah_macRev == AR_SREV_REVISION_OWL_22) |
560 | |
561 | /* Expanded Mac Silicon Rev (16 bits starting with Sowl) */ |
562 | #define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */ |
563 | #define AR_XSREV_ID_S 0 |
564 | #define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */ |
565 | #define AR_XSREV_VERSION_S 18 |
566 | #define AR_XSREV_TYPE 0x0003F000 /* Chip type */ |
567 | #define AR_XSREV_TYPE_S 12 |
568 | #define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains, |
569 | * 0:2 chains) */ |
570 | #define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */ |
571 | #define AR_XSREV_REVISION 0x00000F00 |
572 | #define AR_XSREV_REVISION_S 8 |
573 | |
574 | #define AR_XSREV_VERSION_OWL_PCI 0x0D |
575 | #define AR_XSREV_VERSION_OWL_PCIE 0x0C |
576 | #define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */ |
577 | #define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ |
578 | #define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */ |
579 | #define AR_XSREV_VERSION_SOWL 0x40 |
580 | #define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ |
581 | #define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ |
582 | #define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */ |
583 | #define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ |
584 | #define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ |
585 | #define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ |
586 | #define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */ |
587 | #define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */ |
588 | #define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */ |
589 | #define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */ |
590 | |
591 | #define AR_SREV_OWL_20_OR_LATER(_ah) \ |
592 | (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \ |
593 | AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_20) |
594 | #define AR_SREV_OWL_22_OR_LATER(_ah) \ |
595 | (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \ |
596 | AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_22) |
597 | |
598 | #define AR_SREV_SOWL(_ah) \ |
599 | (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL) |
600 | #define AR_SREV_SOWL_10_OR_LATER(_ah) \ |
601 | (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL) |
602 | #define AR_SREV_SOWL_11(_ah) \ |
603 | (AR_SREV_SOWL(_ah) && \ |
604 | AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11) |
605 | |
606 | #define AR_SREV_MERLIN(_ah) \ |
607 | (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN) |
608 | #define AR_SREV_MERLIN_10_OR_LATER(_ah) \ |
609 | (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) |
610 | #define AR_SREV_MERLIN_20(_ah) \ |
611 | (AR_SREV_MERLIN(_ah) && \ |
612 | AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20) |
613 | #define AR_SREV_MERLIN_20_OR_LATER(_ah) \ |
614 | ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN) || \ |
615 | (AR_SREV_MERLIN((_ah)) && \ |
616 | AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)) |
617 | |
618 | #define AR_SREV_KITE(_ah) \ |
619 | (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) |
620 | #define AR_SREV_KITE_10_OR_LATER(_ah) \ |
621 | (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE) |
622 | #define AR_SREV_KITE_11(_ah) \ |
623 | (AR_SREV_KITE(ah) && \ |
624 | AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11) |
625 | #define AR_SREV_KITE_11_OR_LATER(_ah) \ |
626 | (AR_SREV_KITE_11(_ah) || \ |
627 | AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11) |
628 | #define AR_SREV_KITE_12(_ah) \ |
629 | (AR_SREV_KITE(ah) && \ |
630 | AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12) |
631 | #define AR_SREV_KITE_12_OR_LATER(_ah) \ |
632 | (AR_SREV_KITE_12(_ah) || \ |
633 | AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12) |
634 | #endif /* _DEV_ATH_AR5416REG_H */ |
635 | |