1/* $NetBSD: nouveau_engine_graph_nv30.c,v 1.1.1.1 2014/08/06 12:36:26 riastradh Exp $ */
2
3#include <sys/cdefs.h>
4__KERNEL_RCSID(0, "$NetBSD: nouveau_engine_graph_nv30.c,v 1.1.1.1 2014/08/06 12:36:26 riastradh Exp $");
5
6#include <core/os.h>
7#include <core/class.h>
8#include <core/engctx.h>
9#include <core/enum.h>
10
11#include <subdev/timer.h>
12#include <subdev/fb.h>
13
14#include <engine/graph.h>
15
16#include "nv20.h"
17#include "regs.h"
18
19/*******************************************************************************
20 * Graphics object classes
21 ******************************************************************************/
22
23static struct nouveau_oclass
24nv30_graph_sclass[] = {
25 { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
26 { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
27 { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
28 { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
29 { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
30 { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
31 { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
32 { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
33 { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
34 { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
35 { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
36 { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
37 { 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */
38 { 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */
39 { 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */
40 { 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */
41 { 0x0397, &nv04_graph_ofuncs, NULL }, /* rankine */
42 {},
43};
44
45/*******************************************************************************
46 * PGRAPH context
47 ******************************************************************************/
48
49static int
50nv30_graph_context_ctor(struct nouveau_object *parent,
51 struct nouveau_object *engine,
52 struct nouveau_oclass *oclass, void *data, u32 size,
53 struct nouveau_object **pobject)
54{
55 struct nv20_graph_chan *chan;
56 int ret, i;
57
58 ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x5f48,
59 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
60 *pobject = nv_object(chan);
61 if (ret)
62 return ret;
63
64 chan->chid = nouveau_fifo_chan(parent)->chid;
65
66 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
67 nv_wo32(chan, 0x0410, 0x00000101);
68 nv_wo32(chan, 0x0424, 0x00000111);
69 nv_wo32(chan, 0x0428, 0x00000060);
70 nv_wo32(chan, 0x0444, 0x00000080);
71 nv_wo32(chan, 0x0448, 0xffff0000);
72 nv_wo32(chan, 0x044c, 0x00000001);
73 nv_wo32(chan, 0x0460, 0x44400000);
74 nv_wo32(chan, 0x048c, 0xffff0000);
75 for (i = 0x04e0; i < 0x04e8; i += 4)
76 nv_wo32(chan, i, 0x0fff0000);
77 nv_wo32(chan, 0x04ec, 0x00011100);
78 for (i = 0x0508; i < 0x0548; i += 4)
79 nv_wo32(chan, i, 0x07ff0000);
80 nv_wo32(chan, 0x0550, 0x4b7fffff);
81 nv_wo32(chan, 0x058c, 0x00000080);
82 nv_wo32(chan, 0x0590, 0x30201000);
83 nv_wo32(chan, 0x0594, 0x70605040);
84 nv_wo32(chan, 0x0598, 0xb8a89888);
85 nv_wo32(chan, 0x059c, 0xf8e8d8c8);
86 nv_wo32(chan, 0x05b0, 0xb0000000);
87 for (i = 0x0600; i < 0x0640; i += 4)
88 nv_wo32(chan, i, 0x00010588);
89 for (i = 0x0640; i < 0x0680; i += 4)
90 nv_wo32(chan, i, 0x00030303);
91 for (i = 0x06c0; i < 0x0700; i += 4)
92 nv_wo32(chan, i, 0x0008aae4);
93 for (i = 0x0700; i < 0x0740; i += 4)
94 nv_wo32(chan, i, 0x01012000);
95 for (i = 0x0740; i < 0x0780; i += 4)
96 nv_wo32(chan, i, 0x00080008);
97 nv_wo32(chan, 0x085c, 0x00040000);
98 nv_wo32(chan, 0x0860, 0x00010000);
99 for (i = 0x0864; i < 0x0874; i += 4)
100 nv_wo32(chan, i, 0x00040004);
101 for (i = 0x1f18; i <= 0x3088 ; i += 16) {
102 nv_wo32(chan, i + 0, 0x10700ff9);
103 nv_wo32(chan, i + 1, 0x0436086c);
104 nv_wo32(chan, i + 2, 0x000c001b);
105 }
106 for (i = 0x30b8; i < 0x30c8; i += 4)
107 nv_wo32(chan, i, 0x0000ffff);
108 nv_wo32(chan, 0x344c, 0x3f800000);
109 nv_wo32(chan, 0x3808, 0x3f800000);
110 nv_wo32(chan, 0x381c, 0x3f800000);
111 nv_wo32(chan, 0x3848, 0x40000000);
112 nv_wo32(chan, 0x384c, 0x3f800000);
113 nv_wo32(chan, 0x3850, 0x3f000000);
114 nv_wo32(chan, 0x3858, 0x40000000);
115 nv_wo32(chan, 0x385c, 0x3f800000);
116 nv_wo32(chan, 0x3864, 0xbf800000);
117 nv_wo32(chan, 0x386c, 0xbf800000);
118 return 0;
119}
120
121static struct nouveau_oclass
122nv30_graph_cclass = {
123 .handle = NV_ENGCTX(GR, 0x30),
124 .ofuncs = &(struct nouveau_ofuncs) {
125 .ctor = nv30_graph_context_ctor,
126 .dtor = _nouveau_graph_context_dtor,
127 .init = nv20_graph_context_init,
128 .fini = nv20_graph_context_fini,
129 .rd32 = _nouveau_graph_context_rd32,
130 .wr32 = _nouveau_graph_context_wr32,
131 },
132};
133
134/*******************************************************************************
135 * PGRAPH engine/subdev functions
136 ******************************************************************************/
137
138static int
139nv30_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
140 struct nouveau_oclass *oclass, void *data, u32 size,
141 struct nouveau_object **pobject)
142{
143 struct nv20_graph_priv *priv;
144 int ret;
145
146 ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
147 *pobject = nv_object(priv);
148 if (ret)
149 return ret;
150
151 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
152 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
153 if (ret)
154 return ret;
155
156 nv_subdev(priv)->unit = 0x00001000;
157 nv_subdev(priv)->intr = nv20_graph_intr;
158 nv_engine(priv)->cclass = &nv30_graph_cclass;
159 nv_engine(priv)->sclass = nv30_graph_sclass;
160 nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
161 return 0;
162}
163
164int
165nv30_graph_init(struct nouveau_object *object)
166{
167 struct nouveau_engine *engine = nv_engine(object);
168 struct nv20_graph_priv *priv = (void *)engine;
169 struct nouveau_fb *pfb = nouveau_fb(object);
170 int ret, i;
171
172 ret = nouveau_graph_init(&priv->base);
173 if (ret)
174 return ret;
175
176 nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);
177
178 nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
179 nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
180
181 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
182 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
183 nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
184 nv_wr32(priv, 0x400890, 0x01b463ff);
185 nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
186 nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
187 nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
188 nv_wr32(priv, 0x400B80, 0x1003d888);
189 nv_wr32(priv, 0x400B84, 0x0c000000);
190 nv_wr32(priv, 0x400098, 0x00000000);
191 nv_wr32(priv, 0x40009C, 0x0005ad00);
192 nv_wr32(priv, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
193 nv_wr32(priv, 0x4000a0, 0x00000000);
194 nv_wr32(priv, 0x4000a4, 0x00000008);
195 nv_wr32(priv, 0x4008a8, 0xb784a400);
196 nv_wr32(priv, 0x400ba0, 0x002f8685);
197 nv_wr32(priv, 0x400ba4, 0x00231f3f);
198 nv_wr32(priv, 0x4008a4, 0x40000020);
199
200 if (nv_device(priv)->chipset == 0x34) {
201 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
202 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00200201);
203 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
204 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000008);
205 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
206 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000032);
207 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
208 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000002);
209 }
210
211 nv_wr32(priv, 0x4000c0, 0x00000016);
212
213 /* Turn all the tiling regions off. */
214 for (i = 0; i < pfb->tile.regions; i++)
215 engine->tile_prog(engine, i);
216
217 nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
218 nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF);
219 nv_wr32(priv, 0x0040075c , 0x00000001);
220
221 /* begin RAM config */
222 /* vramsz = pci_resource_len(priv->dev->pdev, 0) - 1; */
223 nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
224 nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
225 if (nv_device(priv)->chipset != 0x34) {
226 nv_wr32(priv, 0x400750, 0x00EA0000);
227 nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100200));
228 nv_wr32(priv, 0x400750, 0x00EA0004);
229 nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100204));
230 }
231 return 0;
232}
233
234struct nouveau_oclass
235nv30_graph_oclass = {
236 .handle = NV_ENGINE(GR, 0x30),
237 .ofuncs = &(struct nouveau_ofuncs) {
238 .ctor = nv30_graph_ctor,
239 .dtor = nv20_graph_dtor,
240 .init = nv30_graph_init,
241 .fini = _nouveau_graph_fini,
242 },
243};
244