1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "drmP.h"
25#include "radeon.h"
26#include "cikd.h"
27#include "r600_dpm.h"
28#include "kv_dpm.h"
29#include "radeon_asic.h"
30#include <linux/seq_file.h>
31
32#define KV_MAX_DEEPSLEEP_DIVIDER_ID 5
33#define KV_MINIMUM_ENGINE_CLOCK 800
34#define SMC_RAM_END 0x40000
35
36static void kv_init_graphics_levels(struct radeon_device *rdev);
37static int kv_calculate_ds_divider(struct radeon_device *rdev);
38static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
39static int kv_calculate_dpm_settings(struct radeon_device *rdev);
40static void kv_enable_new_levels(struct radeon_device *rdev);
41static void kv_program_nbps_index_settings(struct radeon_device *rdev,
42 struct radeon_ps *new_rps);
43static int kv_set_enabled_level(struct radeon_device *rdev, u32 level);
44static int kv_set_enabled_levels(struct radeon_device *rdev);
45static int kv_force_dpm_highest(struct radeon_device *rdev);
46static int kv_force_dpm_lowest(struct radeon_device *rdev);
47static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
48 struct radeon_ps *new_rps,
49 struct radeon_ps *old_rps);
50static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
51 int min_temp, int max_temp);
52static int kv_init_fps_limits(struct radeon_device *rdev);
53
54void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
55static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate);
56static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate);
57static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate);
58
59extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
60extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
61extern void cik_update_cg(struct radeon_device *rdev,
62 u32 block, bool enable);
63
64static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
65{
66 { 0, 4, 1 },
67 { 1, 4, 1 },
68 { 2, 5, 1 },
69 { 3, 4, 2 },
70 { 4, 1, 1 },
71 { 5, 5, 2 },
72 { 6, 6, 1 },
73 { 7, 9, 2 },
74 { 0xffffffff }
75};
76
77static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
78{
79 { 0, 4, 1 },
80 { 0xffffffff }
81};
82
83static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
84{
85 { 0, 4, 1 },
86 { 0xffffffff }
87};
88
89static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
90{
91 { 0, 4, 1 },
92 { 0xffffffff }
93};
94
95static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
96{
97 { 0, 4, 1 },
98 { 0xffffffff }
99};
100
101static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
102{
103 { 0, 4, 1 },
104 { 1, 4, 1 },
105 { 2, 5, 1 },
106 { 3, 4, 1 },
107 { 4, 1, 1 },
108 { 5, 5, 1 },
109 { 6, 6, 1 },
110 { 7, 9, 1 },
111 { 8, 4, 1 },
112 { 9, 2, 1 },
113 { 10, 3, 1 },
114 { 11, 6, 1 },
115 { 12, 8, 2 },
116 { 13, 1, 1 },
117 { 14, 2, 1 },
118 { 15, 3, 1 },
119 { 16, 1, 1 },
120 { 17, 4, 1 },
121 { 18, 3, 1 },
122 { 19, 1, 1 },
123 { 20, 8, 1 },
124 { 21, 5, 1 },
125 { 22, 1, 1 },
126 { 23, 1, 1 },
127 { 24, 4, 1 },
128 { 27, 6, 1 },
129 { 28, 1, 1 },
130 { 0xffffffff }
131};
132
133static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
134{
135 { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
136};
137
138static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
139{
140 { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
141};
142
143static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
144{
145 { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
146};
147
148static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
149{
150 { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
151};
152
153static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
154{
155 { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
156};
157
158static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
159{
160 { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
161};
162
163static const struct kv_pt_config_reg didt_config_kv[] =
164{
165 { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
166 { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
167 { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
168 { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
169 { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
170 { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
171 { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
172 { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
173 { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
174 { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
175 { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
176 { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
177 { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
178 { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
179 { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
180 { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
181 { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
182 { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
183 { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
184 { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
185 { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
186 { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
187 { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
188 { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
189 { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
190 { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
191 { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
192 { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
193 { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
194 { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
195 { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
196 { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
197 { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
198 { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
199 { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
200 { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
201 { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
202 { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
203 { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
204 { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
205 { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
206 { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
207 { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
208 { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
209 { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
210 { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
211 { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
212 { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
213 { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
214 { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
215 { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
216 { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
217 { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
218 { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
219 { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
220 { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
221 { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
222 { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
223 { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
224 { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
225 { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
226 { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
227 { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
228 { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
229 { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
230 { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
231 { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
232 { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
233 { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
234 { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
235 { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
236 { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
237 { 0xFFFFFFFF }
238};
239
240static struct kv_ps *kv_get_ps(struct radeon_ps *rps)
241{
242 struct kv_ps *ps = rps->ps_priv;
243
244 return ps;
245}
246
247static struct kv_power_info *kv_get_pi(struct radeon_device *rdev)
248{
249 struct kv_power_info *pi = rdev->pm.dpm.priv;
250
251 return pi;
252}
253
254#if 0
255static void kv_program_local_cac_table(struct radeon_device *rdev,
256 const struct kv_lcac_config_values *local_cac_table,
257 const struct kv_lcac_config_reg *local_cac_reg)
258{
259 u32 i, count, data;
260 const struct kv_lcac_config_values *values = local_cac_table;
261
262 while (values->block_id != 0xffffffff) {
263 count = values->signal_id;
264 for (i = 0; i < count; i++) {
265 data = ((values->block_id << local_cac_reg->block_shift) &
266 local_cac_reg->block_mask);
267 data |= ((i << local_cac_reg->signal_shift) &
268 local_cac_reg->signal_mask);
269 data |= ((values->t << local_cac_reg->t_shift) &
270 local_cac_reg->t_mask);
271 data |= ((1 << local_cac_reg->enable_shift) &
272 local_cac_reg->enable_mask);
273 WREG32_SMC(local_cac_reg->cntl, data);
274 }
275 values++;
276 }
277}
278#endif
279
280static int kv_program_pt_config_registers(struct radeon_device *rdev,
281 const struct kv_pt_config_reg *cac_config_regs)
282{
283 const struct kv_pt_config_reg *config_regs = cac_config_regs;
284 u32 data;
285 u32 cache = 0;
286
287 if (config_regs == NULL)
288 return -EINVAL;
289
290 while (config_regs->offset != 0xFFFFFFFF) {
291 if (config_regs->type == KV_CONFIGREG_CACHE) {
292 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
293 } else {
294 switch (config_regs->type) {
295 case KV_CONFIGREG_SMC_IND:
296 data = RREG32_SMC(config_regs->offset);
297 break;
298 case KV_CONFIGREG_DIDT_IND:
299 data = RREG32_DIDT(config_regs->offset);
300 break;
301 default:
302 data = RREG32(config_regs->offset << 2);
303 break;
304 }
305
306 data &= ~config_regs->mask;
307 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
308 data |= cache;
309 cache = 0;
310
311 switch (config_regs->type) {
312 case KV_CONFIGREG_SMC_IND:
313 WREG32_SMC(config_regs->offset, data);
314 break;
315 case KV_CONFIGREG_DIDT_IND:
316 WREG32_DIDT(config_regs->offset, data);
317 break;
318 default:
319 WREG32(config_regs->offset << 2, data);
320 break;
321 }
322 }
323 config_regs++;
324 }
325
326 return 0;
327}
328
329static void kv_do_enable_didt(struct radeon_device *rdev, bool enable)
330{
331 struct kv_power_info *pi = kv_get_pi(rdev);
332 u32 data;
333
334 if (pi->caps_sq_ramping) {
335 data = RREG32_DIDT(DIDT_SQ_CTRL0);
336 if (enable)
337 data |= DIDT_CTRL_EN;
338 else
339 data &= ~DIDT_CTRL_EN;
340 WREG32_DIDT(DIDT_SQ_CTRL0, data);
341 }
342
343 if (pi->caps_db_ramping) {
344 data = RREG32_DIDT(DIDT_DB_CTRL0);
345 if (enable)
346 data |= DIDT_CTRL_EN;
347 else
348 data &= ~DIDT_CTRL_EN;
349 WREG32_DIDT(DIDT_DB_CTRL0, data);
350 }
351
352 if (pi->caps_td_ramping) {
353 data = RREG32_DIDT(DIDT_TD_CTRL0);
354 if (enable)
355 data |= DIDT_CTRL_EN;
356 else
357 data &= ~DIDT_CTRL_EN;
358 WREG32_DIDT(DIDT_TD_CTRL0, data);
359 }
360
361 if (pi->caps_tcp_ramping) {
362 data = RREG32_DIDT(DIDT_TCP_CTRL0);
363 if (enable)
364 data |= DIDT_CTRL_EN;
365 else
366 data &= ~DIDT_CTRL_EN;
367 WREG32_DIDT(DIDT_TCP_CTRL0, data);
368 }
369}
370
371static int kv_enable_didt(struct radeon_device *rdev, bool enable)
372{
373 struct kv_power_info *pi = kv_get_pi(rdev);
374 int ret;
375
376 if (pi->caps_sq_ramping ||
377 pi->caps_db_ramping ||
378 pi->caps_td_ramping ||
379 pi->caps_tcp_ramping) {
380 cik_enter_rlc_safe_mode(rdev);
381
382 if (enable) {
383 ret = kv_program_pt_config_registers(rdev, didt_config_kv);
384 if (ret) {
385 cik_exit_rlc_safe_mode(rdev);
386 return ret;
387 }
388 }
389
390 kv_do_enable_didt(rdev, enable);
391
392 cik_exit_rlc_safe_mode(rdev);
393 }
394
395 return 0;
396}
397
398#if 0
399static void kv_initialize_hardware_cac_manager(struct radeon_device *rdev)
400{
401 struct kv_power_info *pi = kv_get_pi(rdev);
402
403 if (pi->caps_cac) {
404 WREG32_SMC(LCAC_SX0_OVR_SEL, 0);
405 WREG32_SMC(LCAC_SX0_OVR_VAL, 0);
406 kv_program_local_cac_table(rdev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
407
408 WREG32_SMC(LCAC_MC0_OVR_SEL, 0);
409 WREG32_SMC(LCAC_MC0_OVR_VAL, 0);
410 kv_program_local_cac_table(rdev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
411
412 WREG32_SMC(LCAC_MC1_OVR_SEL, 0);
413 WREG32_SMC(LCAC_MC1_OVR_VAL, 0);
414 kv_program_local_cac_table(rdev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
415
416 WREG32_SMC(LCAC_MC2_OVR_SEL, 0);
417 WREG32_SMC(LCAC_MC2_OVR_VAL, 0);
418 kv_program_local_cac_table(rdev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
419
420 WREG32_SMC(LCAC_MC3_OVR_SEL, 0);
421 WREG32_SMC(LCAC_MC3_OVR_VAL, 0);
422 kv_program_local_cac_table(rdev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
423
424 WREG32_SMC(LCAC_CPL_OVR_SEL, 0);
425 WREG32_SMC(LCAC_CPL_OVR_VAL, 0);
426 kv_program_local_cac_table(rdev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
427 }
428}
429#endif
430
431static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable)
432{
433 struct kv_power_info *pi = kv_get_pi(rdev);
434 int ret = 0;
435
436 if (pi->caps_cac) {
437 if (enable) {
438 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableCac);
439 if (ret)
440 pi->cac_enabled = false;
441 else
442 pi->cac_enabled = true;
443 } else if (pi->cac_enabled) {
444 kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableCac);
445 pi->cac_enabled = false;
446 }
447 }
448
449 return ret;
450}
451
452static int kv_process_firmware_header(struct radeon_device *rdev)
453{
454 struct kv_power_info *pi = kv_get_pi(rdev);
455 u32 tmp;
456 int ret;
457
458 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
459 offsetof(SMU7_Firmware_Header, DpmTable),
460 &tmp, pi->sram_end);
461
462 if (ret == 0)
463 pi->dpm_table_start = tmp;
464
465 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
466 offsetof(SMU7_Firmware_Header, SoftRegisters),
467 &tmp, pi->sram_end);
468
469 if (ret == 0)
470 pi->soft_regs_start = tmp;
471
472 return ret;
473}
474
475static int kv_enable_dpm_voltage_scaling(struct radeon_device *rdev)
476{
477 struct kv_power_info *pi = kv_get_pi(rdev);
478 int ret;
479
480 pi->graphics_voltage_change_enable = 1;
481
482 ret = kv_copy_bytes_to_smc(rdev,
483 pi->dpm_table_start +
484 offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
485 &pi->graphics_voltage_change_enable,
486 sizeof(u8), pi->sram_end);
487
488 return ret;
489}
490
491static int kv_set_dpm_interval(struct radeon_device *rdev)
492{
493 struct kv_power_info *pi = kv_get_pi(rdev);
494 int ret;
495
496 pi->graphics_interval = 1;
497
498 ret = kv_copy_bytes_to_smc(rdev,
499 pi->dpm_table_start +
500 offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
501 &pi->graphics_interval,
502 sizeof(u8), pi->sram_end);
503
504 return ret;
505}
506
507static int kv_set_dpm_boot_state(struct radeon_device *rdev)
508{
509 struct kv_power_info *pi = kv_get_pi(rdev);
510 int ret;
511
512 ret = kv_copy_bytes_to_smc(rdev,
513 pi->dpm_table_start +
514 offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
515 &pi->graphics_boot_level,
516 sizeof(u8), pi->sram_end);
517
518 return ret;
519}
520
521static void kv_program_vc(struct radeon_device *rdev)
522{
523 WREG32_SMC(CG_FTV_0, 0x3FFFC100);
524}
525
526static void kv_clear_vc(struct radeon_device *rdev)
527{
528 WREG32_SMC(CG_FTV_0, 0);
529}
530
531static int kv_set_divider_value(struct radeon_device *rdev,
532 u32 index, u32 sclk)
533{
534 struct kv_power_info *pi = kv_get_pi(rdev);
535 struct atom_clock_dividers dividers;
536 int ret;
537
538 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
539 sclk, false, &dividers);
540 if (ret)
541 return ret;
542
543 pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
544 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
545
546 return 0;
547}
548
549static u32 kv_convert_vid2_to_vid7(struct radeon_device *rdev,
550 struct sumo_vid_mapping_table *vid_mapping_table,
551 u32 vid_2bit)
552{
553 struct radeon_clock_voltage_dependency_table *vddc_sclk_table =
554 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
555 u32 i;
556
557 if (vddc_sclk_table && vddc_sclk_table->count) {
558 if (vid_2bit < vddc_sclk_table->count)
559 return vddc_sclk_table->entries[vid_2bit].v;
560 else
561 return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
562 } else {
563 for (i = 0; i < vid_mapping_table->num_entries; i++) {
564 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
565 return vid_mapping_table->entries[i].vid_7bit;
566 }
567 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
568 }
569}
570
571static u32 kv_convert_vid7_to_vid2(struct radeon_device *rdev,
572 struct sumo_vid_mapping_table *vid_mapping_table,
573 u32 vid_7bit)
574{
575 struct radeon_clock_voltage_dependency_table *vddc_sclk_table =
576 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
577 u32 i;
578
579 if (vddc_sclk_table && vddc_sclk_table->count) {
580 for (i = 0; i < vddc_sclk_table->count; i++) {
581 if (vddc_sclk_table->entries[i].v == vid_7bit)
582 return i;
583 }
584 return vddc_sclk_table->count - 1;
585 } else {
586 for (i = 0; i < vid_mapping_table->num_entries; i++) {
587 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
588 return vid_mapping_table->entries[i].vid_2bit;
589 }
590
591 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
592 }
593}
594
595static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev,
596 u16 voltage)
597{
598 return 6200 - (voltage * 25);
599}
600
601static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev,
602 u32 vid_2bit)
603{
604 struct kv_power_info *pi = kv_get_pi(rdev);
605 u32 vid_8bit = kv_convert_vid2_to_vid7(rdev,
606 &pi->sys_info.vid_mapping_table,
607 vid_2bit);
608
609 return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit);
610}
611
612
613static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
614{
615 struct kv_power_info *pi = kv_get_pi(rdev);
616
617 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
618 pi->graphics_level[index].MinVddNb =
619 cpu_to_be32(kv_convert_2bit_index_to_voltage(rdev, vid));
620
621 return 0;
622}
623
624static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at)
625{
626 struct kv_power_info *pi = kv_get_pi(rdev);
627
628 pi->graphics_level[index].AT = cpu_to_be16((u16)at);
629
630 return 0;
631}
632
633static void kv_dpm_power_level_enable(struct radeon_device *rdev,
634 u32 index, bool enable)
635{
636 struct kv_power_info *pi = kv_get_pi(rdev);
637
638 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
639}
640
641static void kv_start_dpm(struct radeon_device *rdev)
642{
643 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
644
645 tmp |= GLOBAL_PWRMGT_EN;
646 WREG32_SMC(GENERAL_PWRMGT, tmp);
647
648 kv_smc_dpm_enable(rdev, true);
649}
650
651static void kv_stop_dpm(struct radeon_device *rdev)
652{
653 kv_smc_dpm_enable(rdev, false);
654}
655
656static void kv_start_am(struct radeon_device *rdev)
657{
658 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
659
660 sclk_pwrmgt_cntl &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
661 sclk_pwrmgt_cntl |= DYNAMIC_PM_EN;
662
663 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
664}
665
666static void kv_reset_am(struct radeon_device *rdev)
667{
668 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
669
670 sclk_pwrmgt_cntl |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
671
672 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
673}
674
675static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze)
676{
677 return kv_notify_message_to_smu(rdev, freeze ?
678 PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
679}
680
681static int kv_force_lowest_valid(struct radeon_device *rdev)
682{
683 return kv_force_dpm_lowest(rdev);
684}
685
686static int kv_unforce_levels(struct radeon_device *rdev)
687{
688 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
689 return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
690 else
691 return kv_set_enabled_levels(rdev);
692}
693
694static int kv_update_sclk_t(struct radeon_device *rdev)
695{
696 struct kv_power_info *pi = kv_get_pi(rdev);
697 u32 low_sclk_interrupt_t = 0;
698 int ret = 0;
699
700 if (pi->caps_sclk_throttle_low_notification) {
701 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
702
703 ret = kv_copy_bytes_to_smc(rdev,
704 pi->dpm_table_start +
705 offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
706 (u8 *)&low_sclk_interrupt_t,
707 sizeof(u32), pi->sram_end);
708 }
709 return ret;
710}
711
712static int kv_program_bootup_state(struct radeon_device *rdev)
713{
714 struct kv_power_info *pi = kv_get_pi(rdev);
715 u32 i;
716 struct radeon_clock_voltage_dependency_table *table =
717 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
718
719 if (table && table->count) {
720 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
721 if (table->entries[i].clk == pi->boot_pl.sclk)
722 break;
723 }
724
725 pi->graphics_boot_level = (u8)i;
726 kv_dpm_power_level_enable(rdev, i, true);
727 } else {
728 struct sumo_sclk_voltage_mapping_table *table =
729 &pi->sys_info.sclk_voltage_mapping_table;
730
731 if (table->num_max_dpm_entries == 0)
732 return -EINVAL;
733
734 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
735 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
736 break;
737 }
738
739 pi->graphics_boot_level = (u8)i;
740 kv_dpm_power_level_enable(rdev, i, true);
741 }
742 return 0;
743}
744
745static int kv_enable_auto_thermal_throttling(struct radeon_device *rdev)
746{
747 struct kv_power_info *pi = kv_get_pi(rdev);
748 int ret;
749
750 pi->graphics_therm_throttle_enable = 1;
751
752 ret = kv_copy_bytes_to_smc(rdev,
753 pi->dpm_table_start +
754 offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
755 &pi->graphics_therm_throttle_enable,
756 sizeof(u8), pi->sram_end);
757
758 return ret;
759}
760
761static int kv_upload_dpm_settings(struct radeon_device *rdev)
762{
763 struct kv_power_info *pi = kv_get_pi(rdev);
764 int ret;
765
766 ret = kv_copy_bytes_to_smc(rdev,
767 pi->dpm_table_start +
768 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
769 (u8 *)&pi->graphics_level,
770 sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
771 pi->sram_end);
772
773 if (ret)
774 return ret;
775
776 ret = kv_copy_bytes_to_smc(rdev,
777 pi->dpm_table_start +
778 offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
779 &pi->graphics_dpm_level_count,
780 sizeof(u8), pi->sram_end);
781
782 return ret;
783}
784
785static u32 kv_get_clock_difference(u32 a, u32 b)
786{
787 return (a >= b) ? a - b : b - a;
788}
789
790static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk)
791{
792 struct kv_power_info *pi = kv_get_pi(rdev);
793 u32 value;
794
795 if (pi->caps_enable_dfs_bypass) {
796 if (kv_get_clock_difference(clk, 40000) < 200)
797 value = 3;
798 else if (kv_get_clock_difference(clk, 30000) < 200)
799 value = 2;
800 else if (kv_get_clock_difference(clk, 20000) < 200)
801 value = 7;
802 else if (kv_get_clock_difference(clk, 15000) < 200)
803 value = 6;
804 else if (kv_get_clock_difference(clk, 10000) < 200)
805 value = 8;
806 else
807 value = 0;
808 } else {
809 value = 0;
810 }
811
812 return value;
813}
814
815static int kv_populate_uvd_table(struct radeon_device *rdev)
816{
817 struct kv_power_info *pi = kv_get_pi(rdev);
818 struct radeon_uvd_clock_voltage_dependency_table *table =
819 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
820 struct atom_clock_dividers dividers;
821 int ret;
822 u32 i;
823
824 if (table == NULL || table->count == 0)
825 return 0;
826
827 pi->uvd_level_count = 0;
828 for (i = 0; i < table->count; i++) {
829 if (pi->high_voltage_t &&
830 (pi->high_voltage_t < table->entries[i].v))
831 break;
832
833 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
834 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
835 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
836
837 pi->uvd_level[i].VClkBypassCntl =
838 (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);
839 pi->uvd_level[i].DClkBypassCntl =
840 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);
841
842 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
843 table->entries[i].vclk, false, &dividers);
844 if (ret)
845 return ret;
846 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
847
848 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
849 table->entries[i].dclk, false, &dividers);
850 if (ret)
851 return ret;
852 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
853
854 pi->uvd_level_count++;
855 }
856
857 ret = kv_copy_bytes_to_smc(rdev,
858 pi->dpm_table_start +
859 offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
860 (u8 *)&pi->uvd_level_count,
861 sizeof(u8), pi->sram_end);
862 if (ret)
863 return ret;
864
865 pi->uvd_interval = 1;
866
867 ret = kv_copy_bytes_to_smc(rdev,
868 pi->dpm_table_start +
869 offsetof(SMU7_Fusion_DpmTable, UVDInterval),
870 &pi->uvd_interval,
871 sizeof(u8), pi->sram_end);
872 if (ret)
873 return ret;
874
875 ret = kv_copy_bytes_to_smc(rdev,
876 pi->dpm_table_start +
877 offsetof(SMU7_Fusion_DpmTable, UvdLevel),
878 (u8 *)&pi->uvd_level,
879 sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
880 pi->sram_end);
881
882 return ret;
883
884}
885
886static int kv_populate_vce_table(struct radeon_device *rdev)
887{
888 struct kv_power_info *pi = kv_get_pi(rdev);
889 int ret;
890 u32 i;
891 struct radeon_vce_clock_voltage_dependency_table *table =
892 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
893 struct atom_clock_dividers dividers;
894
895 if (table == NULL || table->count == 0)
896 return 0;
897
898 pi->vce_level_count = 0;
899 for (i = 0; i < table->count; i++) {
900 if (pi->high_voltage_t &&
901 pi->high_voltage_t < table->entries[i].v)
902 break;
903
904 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
905 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
906
907 pi->vce_level[i].ClkBypassCntl =
908 (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);
909
910 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
911 table->entries[i].evclk, false, &dividers);
912 if (ret)
913 return ret;
914 pi->vce_level[i].Divider = (u8)dividers.post_div;
915
916 pi->vce_level_count++;
917 }
918
919 ret = kv_copy_bytes_to_smc(rdev,
920 pi->dpm_table_start +
921 offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
922 (u8 *)&pi->vce_level_count,
923 sizeof(u8),
924 pi->sram_end);
925 if (ret)
926 return ret;
927
928 pi->vce_interval = 1;
929
930 ret = kv_copy_bytes_to_smc(rdev,
931 pi->dpm_table_start +
932 offsetof(SMU7_Fusion_DpmTable, VCEInterval),
933 (u8 *)&pi->vce_interval,
934 sizeof(u8),
935 pi->sram_end);
936 if (ret)
937 return ret;
938
939 ret = kv_copy_bytes_to_smc(rdev,
940 pi->dpm_table_start +
941 offsetof(SMU7_Fusion_DpmTable, VceLevel),
942 (u8 *)&pi->vce_level,
943 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
944 pi->sram_end);
945
946 return ret;
947}
948
949static int kv_populate_samu_table(struct radeon_device *rdev)
950{
951 struct kv_power_info *pi = kv_get_pi(rdev);
952 struct radeon_clock_voltage_dependency_table *table =
953 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
954 struct atom_clock_dividers dividers;
955 int ret;
956 u32 i;
957
958 if (table == NULL || table->count == 0)
959 return 0;
960
961 pi->samu_level_count = 0;
962 for (i = 0; i < table->count; i++) {
963 if (pi->high_voltage_t &&
964 pi->high_voltage_t < table->entries[i].v)
965 break;
966
967 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
968 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
969
970 pi->samu_level[i].ClkBypassCntl =
971 (u8)kv_get_clk_bypass(rdev, table->entries[i].clk);
972
973 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
974 table->entries[i].clk, false, &dividers);
975 if (ret)
976 return ret;
977 pi->samu_level[i].Divider = (u8)dividers.post_div;
978
979 pi->samu_level_count++;
980 }
981
982 ret = kv_copy_bytes_to_smc(rdev,
983 pi->dpm_table_start +
984 offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
985 (u8 *)&pi->samu_level_count,
986 sizeof(u8),
987 pi->sram_end);
988 if (ret)
989 return ret;
990
991 pi->samu_interval = 1;
992
993 ret = kv_copy_bytes_to_smc(rdev,
994 pi->dpm_table_start +
995 offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
996 (u8 *)&pi->samu_interval,
997 sizeof(u8),
998 pi->sram_end);
999 if (ret)
1000 return ret;
1001
1002 ret = kv_copy_bytes_to_smc(rdev,
1003 pi->dpm_table_start +
1004 offsetof(SMU7_Fusion_DpmTable, SamuLevel),
1005 (u8 *)&pi->samu_level,
1006 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
1007 pi->sram_end);
1008 if (ret)
1009 return ret;
1010
1011 return ret;
1012}
1013
1014
1015static int kv_populate_acp_table(struct radeon_device *rdev)
1016{
1017 struct kv_power_info *pi = kv_get_pi(rdev);
1018 struct radeon_clock_voltage_dependency_table *table =
1019 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1020 struct atom_clock_dividers dividers;
1021 int ret;
1022 u32 i;
1023
1024 if (table == NULL || table->count == 0)
1025 return 0;
1026
1027 pi->acp_level_count = 0;
1028 for (i = 0; i < table->count; i++) {
1029 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1030 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1031
1032 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1033 table->entries[i].clk, false, &dividers);
1034 if (ret)
1035 return ret;
1036 pi->acp_level[i].Divider = (u8)dividers.post_div;
1037
1038 pi->acp_level_count++;
1039 }
1040
1041 ret = kv_copy_bytes_to_smc(rdev,
1042 pi->dpm_table_start +
1043 offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
1044 (u8 *)&pi->acp_level_count,
1045 sizeof(u8),
1046 pi->sram_end);
1047 if (ret)
1048 return ret;
1049
1050 pi->acp_interval = 1;
1051
1052 ret = kv_copy_bytes_to_smc(rdev,
1053 pi->dpm_table_start +
1054 offsetof(SMU7_Fusion_DpmTable, ACPInterval),
1055 (u8 *)&pi->acp_interval,
1056 sizeof(u8),
1057 pi->sram_end);
1058 if (ret)
1059 return ret;
1060
1061 ret = kv_copy_bytes_to_smc(rdev,
1062 pi->dpm_table_start +
1063 offsetof(SMU7_Fusion_DpmTable, AcpLevel),
1064 (u8 *)&pi->acp_level,
1065 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
1066 pi->sram_end);
1067 if (ret)
1068 return ret;
1069
1070 return ret;
1071}
1072
1073static void kv_calculate_dfs_bypass_settings(struct radeon_device *rdev)
1074{
1075 struct kv_power_info *pi = kv_get_pi(rdev);
1076 u32 i;
1077 struct radeon_clock_voltage_dependency_table *table =
1078 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1079
1080 if (table && table->count) {
1081 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1082 if (pi->caps_enable_dfs_bypass) {
1083 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1084 pi->graphics_level[i].ClkBypassCntl = 3;
1085 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1086 pi->graphics_level[i].ClkBypassCntl = 2;
1087 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1088 pi->graphics_level[i].ClkBypassCntl = 7;
1089 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
1090 pi->graphics_level[i].ClkBypassCntl = 6;
1091 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
1092 pi->graphics_level[i].ClkBypassCntl = 8;
1093 else
1094 pi->graphics_level[i].ClkBypassCntl = 0;
1095 } else {
1096 pi->graphics_level[i].ClkBypassCntl = 0;
1097 }
1098 }
1099 } else {
1100 struct sumo_sclk_voltage_mapping_table *table =
1101 &pi->sys_info.sclk_voltage_mapping_table;
1102 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1103 if (pi->caps_enable_dfs_bypass) {
1104 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1105 pi->graphics_level[i].ClkBypassCntl = 3;
1106 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1107 pi->graphics_level[i].ClkBypassCntl = 2;
1108 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1109 pi->graphics_level[i].ClkBypassCntl = 7;
1110 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1111 pi->graphics_level[i].ClkBypassCntl = 6;
1112 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1113 pi->graphics_level[i].ClkBypassCntl = 8;
1114 else
1115 pi->graphics_level[i].ClkBypassCntl = 0;
1116 } else {
1117 pi->graphics_level[i].ClkBypassCntl = 0;
1118 }
1119 }
1120 }
1121}
1122
1123static int kv_enable_ulv(struct radeon_device *rdev, bool enable)
1124{
1125 return kv_notify_message_to_smu(rdev, enable ?
1126 PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1127}
1128
1129static void kv_reset_acp_boot_level(struct radeon_device *rdev)
1130{
1131 struct kv_power_info *pi = kv_get_pi(rdev);
1132
1133 pi->acp_boot_level = 0xff;
1134}
1135
1136static void kv_update_current_ps(struct radeon_device *rdev,
1137 struct radeon_ps *rps)
1138{
1139 struct kv_ps *new_ps = kv_get_ps(rps);
1140 struct kv_power_info *pi = kv_get_pi(rdev);
1141
1142 pi->current_rps = *rps;
1143 pi->current_ps = *new_ps;
1144 pi->current_rps.ps_priv = &pi->current_ps;
1145}
1146
1147static void kv_update_requested_ps(struct radeon_device *rdev,
1148 struct radeon_ps *rps)
1149{
1150 struct kv_ps *new_ps = kv_get_ps(rps);
1151 struct kv_power_info *pi = kv_get_pi(rdev);
1152
1153 pi->requested_rps = *rps;
1154 pi->requested_ps = *new_ps;
1155 pi->requested_rps.ps_priv = &pi->requested_ps;
1156}
1157
1158void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
1159{
1160 struct kv_power_info *pi = kv_get_pi(rdev);
1161 int ret;
1162
1163 if (pi->bapm_enable) {
1164 ret = kv_smc_bapm_enable(rdev, enable);
1165 if (ret)
1166 DRM_ERROR("kv_smc_bapm_enable failed\n");
1167 }
1168}
1169
1170int kv_dpm_enable(struct radeon_device *rdev)
1171{
1172 struct kv_power_info *pi = kv_get_pi(rdev);
1173 int ret;
1174
1175 ret = kv_process_firmware_header(rdev);
1176 if (ret) {
1177 DRM_ERROR("kv_process_firmware_header failed\n");
1178 return ret;
1179 }
1180 kv_init_fps_limits(rdev);
1181 kv_init_graphics_levels(rdev);
1182 ret = kv_program_bootup_state(rdev);
1183 if (ret) {
1184 DRM_ERROR("kv_program_bootup_state failed\n");
1185 return ret;
1186 }
1187 kv_calculate_dfs_bypass_settings(rdev);
1188 ret = kv_upload_dpm_settings(rdev);
1189 if (ret) {
1190 DRM_ERROR("kv_upload_dpm_settings failed\n");
1191 return ret;
1192 }
1193 ret = kv_populate_uvd_table(rdev);
1194 if (ret) {
1195 DRM_ERROR("kv_populate_uvd_table failed\n");
1196 return ret;
1197 }
1198 ret = kv_populate_vce_table(rdev);
1199 if (ret) {
1200 DRM_ERROR("kv_populate_vce_table failed\n");
1201 return ret;
1202 }
1203 ret = kv_populate_samu_table(rdev);
1204 if (ret) {
1205 DRM_ERROR("kv_populate_samu_table failed\n");
1206 return ret;
1207 }
1208 ret = kv_populate_acp_table(rdev);
1209 if (ret) {
1210 DRM_ERROR("kv_populate_acp_table failed\n");
1211 return ret;
1212 }
1213 kv_program_vc(rdev);
1214#if 0
1215 kv_initialize_hardware_cac_manager(rdev);
1216#endif
1217 kv_start_am(rdev);
1218 if (pi->enable_auto_thermal_throttling) {
1219 ret = kv_enable_auto_thermal_throttling(rdev);
1220 if (ret) {
1221 DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1222 return ret;
1223 }
1224 }
1225 ret = kv_enable_dpm_voltage_scaling(rdev);
1226 if (ret) {
1227 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1228 return ret;
1229 }
1230 ret = kv_set_dpm_interval(rdev);
1231 if (ret) {
1232 DRM_ERROR("kv_set_dpm_interval failed\n");
1233 return ret;
1234 }
1235 ret = kv_set_dpm_boot_state(rdev);
1236 if (ret) {
1237 DRM_ERROR("kv_set_dpm_boot_state failed\n");
1238 return ret;
1239 }
1240 ret = kv_enable_ulv(rdev, true);
1241 if (ret) {
1242 DRM_ERROR("kv_enable_ulv failed\n");
1243 return ret;
1244 }
1245 kv_start_dpm(rdev);
1246 ret = kv_enable_didt(rdev, true);
1247 if (ret) {
1248 DRM_ERROR("kv_enable_didt failed\n");
1249 return ret;
1250 }
1251 ret = kv_enable_smc_cac(rdev, true);
1252 if (ret) {
1253 DRM_ERROR("kv_enable_smc_cac failed\n");
1254 return ret;
1255 }
1256
1257 kv_reset_acp_boot_level(rdev);
1258
1259 ret = kv_smc_bapm_enable(rdev, false);
1260 if (ret) {
1261 DRM_ERROR("kv_smc_bapm_enable failed\n");
1262 return ret;
1263 }
1264
1265 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1266
1267 return ret;
1268}
1269
1270int kv_dpm_late_enable(struct radeon_device *rdev)
1271{
1272 int ret = 0;
1273
1274 if (rdev->irq.installed &&
1275 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1276 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1277 if (ret) {
1278 DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1279 return ret;
1280 }
1281 rdev->irq.dpm_thermal = true;
1282 radeon_irq_set(rdev);
1283 }
1284
1285 /* powerdown unused blocks for now */
1286 kv_dpm_powergate_acp(rdev, true);
1287 kv_dpm_powergate_samu(rdev, true);
1288 kv_dpm_powergate_vce(rdev, true);
1289 kv_dpm_powergate_uvd(rdev, true);
1290
1291 return ret;
1292}
1293
1294void kv_dpm_disable(struct radeon_device *rdev)
1295{
1296 kv_smc_bapm_enable(rdev, false);
1297
1298 /* powerup blocks */
1299 kv_dpm_powergate_acp(rdev, false);
1300 kv_dpm_powergate_samu(rdev, false);
1301 kv_dpm_powergate_vce(rdev, false);
1302 kv_dpm_powergate_uvd(rdev, false);
1303
1304 kv_enable_smc_cac(rdev, false);
1305 kv_enable_didt(rdev, false);
1306 kv_clear_vc(rdev);
1307 kv_stop_dpm(rdev);
1308 kv_enable_ulv(rdev, false);
1309 kv_reset_am(rdev);
1310
1311 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1312}
1313
1314#if 0
1315static int kv_write_smc_soft_register(struct radeon_device *rdev,
1316 u16 reg_offset, u32 value)
1317{
1318 struct kv_power_info *pi = kv_get_pi(rdev);
1319
1320 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1321 (u8 *)&value, sizeof(u16), pi->sram_end);
1322}
1323
1324static int kv_read_smc_soft_register(struct radeon_device *rdev,
1325 u16 reg_offset, u32 *value)
1326{
1327 struct kv_power_info *pi = kv_get_pi(rdev);
1328
1329 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
1330 value, pi->sram_end);
1331}
1332#endif
1333
1334static void kv_init_sclk_t(struct radeon_device *rdev)
1335{
1336 struct kv_power_info *pi = kv_get_pi(rdev);
1337
1338 pi->low_sclk_interrupt_t = 0;
1339}
1340
1341static int kv_init_fps_limits(struct radeon_device *rdev)
1342{
1343 struct kv_power_info *pi = kv_get_pi(rdev);
1344 int ret = 0;
1345
1346 if (pi->caps_fps) {
1347 u16 tmp;
1348
1349 tmp = 45;
1350 pi->fps_high_t = cpu_to_be16(tmp);
1351 ret = kv_copy_bytes_to_smc(rdev,
1352 pi->dpm_table_start +
1353 offsetof(SMU7_Fusion_DpmTable, FpsHighT),
1354 (u8 *)&pi->fps_high_t,
1355 sizeof(u16), pi->sram_end);
1356
1357 tmp = 30;
1358 pi->fps_low_t = cpu_to_be16(tmp);
1359
1360 ret = kv_copy_bytes_to_smc(rdev,
1361 pi->dpm_table_start +
1362 offsetof(SMU7_Fusion_DpmTable, FpsLowT),
1363 (u8 *)&pi->fps_low_t,
1364 sizeof(u16), pi->sram_end);
1365
1366 }
1367 return ret;
1368}
1369
1370static void kv_init_powergate_state(struct radeon_device *rdev)
1371{
1372 struct kv_power_info *pi = kv_get_pi(rdev);
1373
1374 pi->uvd_power_gated = false;
1375 pi->vce_power_gated = false;
1376 pi->samu_power_gated = false;
1377 pi->acp_power_gated = false;
1378
1379}
1380
1381static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
1382{
1383 return kv_notify_message_to_smu(rdev, enable ?
1384 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
1385}
1386
1387static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable)
1388{
1389 return kv_notify_message_to_smu(rdev, enable ?
1390 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
1391}
1392
1393static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable)
1394{
1395 return kv_notify_message_to_smu(rdev, enable ?
1396 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
1397}
1398
1399static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable)
1400{
1401 return kv_notify_message_to_smu(rdev, enable ?
1402 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
1403}
1404
1405static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
1406{
1407 struct kv_power_info *pi = kv_get_pi(rdev);
1408 struct radeon_uvd_clock_voltage_dependency_table *table =
1409 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1410 int ret;
1411 u32 mask;
1412
1413 if (!gate) {
1414 if (table->count)
1415 pi->uvd_boot_level = table->count - 1;
1416 else
1417 pi->uvd_boot_level = 0;
1418
1419 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
1420 mask = 1 << pi->uvd_boot_level;
1421 } else {
1422 mask = 0x1f;
1423 }
1424
1425 ret = kv_copy_bytes_to_smc(rdev,
1426 pi->dpm_table_start +
1427 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
1428 (uint8_t *)&pi->uvd_boot_level,
1429 sizeof(u8), pi->sram_end);
1430 if (ret)
1431 return ret;
1432
1433 kv_send_msg_to_smc_with_parameter(rdev,
1434 PPSMC_MSG_UVDDPM_SetEnabledMask,
1435 mask);
1436 }
1437
1438 return kv_enable_uvd_dpm(rdev, !gate);
1439}
1440
1441static u8 kv_get_vce_boot_level(struct radeon_device *rdev)
1442{
1443 u8 i;
1444 struct radeon_vce_clock_voltage_dependency_table *table =
1445 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1446
1447 for (i = 0; i < table->count; i++) {
1448#if 0 /* XXX Upstream has changed this to make sense. */
1449 if (table->entries[i].evclk >= 0) /* XXX */
1450 break;
1451#endif
1452 }
1453
1454 return i;
1455}
1456
1457static int kv_update_vce_dpm(struct radeon_device *rdev,
1458 struct radeon_ps *radeon_new_state,
1459 struct radeon_ps *radeon_current_state)
1460{
1461 struct kv_power_info *pi = kv_get_pi(rdev);
1462 struct radeon_vce_clock_voltage_dependency_table *table =
1463 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1464 int ret;
1465
1466 if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) {
1467 kv_dpm_powergate_vce(rdev, false);
1468 /* turn the clocks on when encoding */
1469 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
1470 if (pi->caps_stable_p_state)
1471 pi->vce_boot_level = table->count - 1;
1472 else
1473 pi->vce_boot_level = kv_get_vce_boot_level(rdev);
1474
1475 ret = kv_copy_bytes_to_smc(rdev,
1476 pi->dpm_table_start +
1477 offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
1478 (u8 *)&pi->vce_boot_level,
1479 sizeof(u8),
1480 pi->sram_end);
1481 if (ret)
1482 return ret;
1483
1484 if (pi->caps_stable_p_state)
1485 kv_send_msg_to_smc_with_parameter(rdev,
1486 PPSMC_MSG_VCEDPM_SetEnabledMask,
1487 (1 << pi->vce_boot_level));
1488
1489 kv_enable_vce_dpm(rdev, true);
1490 } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) {
1491 kv_enable_vce_dpm(rdev, false);
1492 /* turn the clocks off when not encoding */
1493 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
1494 kv_dpm_powergate_vce(rdev, true);
1495 }
1496
1497 return 0;
1498}
1499
1500static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate)
1501{
1502 struct kv_power_info *pi = kv_get_pi(rdev);
1503 struct radeon_clock_voltage_dependency_table *table =
1504 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1505 int ret;
1506
1507 if (!gate) {
1508 if (pi->caps_stable_p_state)
1509 pi->samu_boot_level = table->count - 1;
1510 else
1511 pi->samu_boot_level = 0;
1512
1513 ret = kv_copy_bytes_to_smc(rdev,
1514 pi->dpm_table_start +
1515 offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
1516 (u8 *)&pi->samu_boot_level,
1517 sizeof(u8),
1518 pi->sram_end);
1519 if (ret)
1520 return ret;
1521
1522 if (pi->caps_stable_p_state)
1523 kv_send_msg_to_smc_with_parameter(rdev,
1524 PPSMC_MSG_SAMUDPM_SetEnabledMask,
1525 (1 << pi->samu_boot_level));
1526 }
1527
1528 return kv_enable_samu_dpm(rdev, !gate);
1529}
1530
1531static u8 kv_get_acp_boot_level(struct radeon_device *rdev)
1532{
1533 u8 i;
1534 struct radeon_clock_voltage_dependency_table *table =
1535 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1536
1537 for (i = 0; i < table->count; i++) {
1538#if 0 /* XXX Upstream has changed this to make sense. */
1539 if (table->entries[i].clk >= 0) /* XXX */
1540 break;
1541#endif
1542 }
1543
1544 if (i >= table->count)
1545 i = table->count - 1;
1546
1547 return i;
1548}
1549
1550static void kv_update_acp_boot_level(struct radeon_device *rdev)
1551{
1552 struct kv_power_info *pi = kv_get_pi(rdev);
1553 u8 acp_boot_level;
1554
1555 if (!pi->caps_stable_p_state) {
1556 acp_boot_level = kv_get_acp_boot_level(rdev);
1557 if (acp_boot_level != pi->acp_boot_level) {
1558 pi->acp_boot_level = acp_boot_level;
1559 kv_send_msg_to_smc_with_parameter(rdev,
1560 PPSMC_MSG_ACPDPM_SetEnabledMask,
1561 (1 << pi->acp_boot_level));
1562 }
1563 }
1564}
1565
1566static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
1567{
1568 struct kv_power_info *pi = kv_get_pi(rdev);
1569 struct radeon_clock_voltage_dependency_table *table =
1570 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1571 int ret;
1572
1573 if (!gate) {
1574 if (pi->caps_stable_p_state)
1575 pi->acp_boot_level = table->count - 1;
1576 else
1577 pi->acp_boot_level = kv_get_acp_boot_level(rdev);
1578
1579 ret = kv_copy_bytes_to_smc(rdev,
1580 pi->dpm_table_start +
1581 offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
1582 (u8 *)&pi->acp_boot_level,
1583 sizeof(u8),
1584 pi->sram_end);
1585 if (ret)
1586 return ret;
1587
1588 if (pi->caps_stable_p_state)
1589 kv_send_msg_to_smc_with_parameter(rdev,
1590 PPSMC_MSG_ACPDPM_SetEnabledMask,
1591 (1 << pi->acp_boot_level));
1592 }
1593
1594 return kv_enable_acp_dpm(rdev, !gate);
1595}
1596
1597void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
1598{
1599 struct kv_power_info *pi = kv_get_pi(rdev);
1600
1601 if (pi->uvd_power_gated == gate)
1602 return;
1603
1604 pi->uvd_power_gated = gate;
1605
1606 if (gate) {
1607 if (pi->caps_uvd_pg) {
1608 uvd_v1_0_stop(rdev);
1609 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
1610 }
1611 kv_update_uvd_dpm(rdev, gate);
1612 if (pi->caps_uvd_pg)
1613 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerOFF);
1614 } else {
1615 if (pi->caps_uvd_pg) {
1616 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerON);
1617 uvd_v4_2_resume(rdev);
1618 uvd_v1_0_start(rdev);
1619 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
1620 }
1621 kv_update_uvd_dpm(rdev, gate);
1622 }
1623}
1624
1625static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate)
1626{
1627 struct kv_power_info *pi = kv_get_pi(rdev);
1628
1629 if (pi->vce_power_gated == gate)
1630 return;
1631
1632 pi->vce_power_gated = gate;
1633
1634 if (gate) {
1635 if (pi->caps_vce_pg) {
1636 /* XXX do we need a vce_v1_0_stop() ? */
1637 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF);
1638 }
1639 } else {
1640 if (pi->caps_vce_pg) {
1641 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON);
1642 vce_v2_0_resume(rdev);
1643 vce_v1_0_start(rdev);
1644 }
1645 }
1646}
1647
1648static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate)
1649{
1650 struct kv_power_info *pi = kv_get_pi(rdev);
1651
1652 if (pi->samu_power_gated == gate)
1653 return;
1654
1655 pi->samu_power_gated = gate;
1656
1657 if (gate) {
1658 kv_update_samu_dpm(rdev, true);
1659 if (pi->caps_samu_pg)
1660 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerOFF);
1661 } else {
1662 if (pi->caps_samu_pg)
1663 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerON);
1664 kv_update_samu_dpm(rdev, false);
1665 }
1666}
1667
1668static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate)
1669{
1670 struct kv_power_info *pi = kv_get_pi(rdev);
1671
1672 if (pi->acp_power_gated == gate)
1673 return;
1674
1675 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
1676 return;
1677
1678 pi->acp_power_gated = gate;
1679
1680 if (gate) {
1681 kv_update_acp_dpm(rdev, true);
1682 if (pi->caps_acp_pg)
1683 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerOFF);
1684 } else {
1685 if (pi->caps_acp_pg)
1686 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerON);
1687 kv_update_acp_dpm(rdev, false);
1688 }
1689}
1690
1691static void kv_set_valid_clock_range(struct radeon_device *rdev,
1692 struct radeon_ps *new_rps)
1693{
1694 struct kv_ps *new_ps = kv_get_ps(new_rps);
1695 struct kv_power_info *pi = kv_get_pi(rdev);
1696 u32 i;
1697 struct radeon_clock_voltage_dependency_table *table =
1698 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1699
1700 if (table && table->count) {
1701 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1702 if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1703 (i == (pi->graphics_dpm_level_count - 1))) {
1704 pi->lowest_valid = i;
1705 break;
1706 }
1707 }
1708
1709 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1710 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1711 break;
1712 }
1713 pi->highest_valid = i;
1714
1715 if (pi->lowest_valid > pi->highest_valid) {
1716 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1717 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1718 pi->highest_valid = pi->lowest_valid;
1719 else
1720 pi->lowest_valid = pi->highest_valid;
1721 }
1722 } else {
1723 struct sumo_sclk_voltage_mapping_table *table =
1724 &pi->sys_info.sclk_voltage_mapping_table;
1725
1726 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1727 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1728 i == (int)(pi->graphics_dpm_level_count - 1)) {
1729 pi->lowest_valid = i;
1730 break;
1731 }
1732 }
1733
1734 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1735 if (table->entries[i].sclk_frequency <=
1736 new_ps->levels[new_ps->num_levels - 1].sclk)
1737 break;
1738 }
1739 pi->highest_valid = i;
1740
1741 if (pi->lowest_valid > pi->highest_valid) {
1742 if ((new_ps->levels[0].sclk -
1743 table->entries[pi->highest_valid].sclk_frequency) >
1744 (table->entries[pi->lowest_valid].sclk_frequency -
1745 new_ps->levels[new_ps->num_levels -1].sclk))
1746 pi->highest_valid = pi->lowest_valid;
1747 else
1748 pi->lowest_valid = pi->highest_valid;
1749 }
1750 }
1751}
1752
1753static int kv_update_dfs_bypass_settings(struct radeon_device *rdev,
1754 struct radeon_ps *new_rps)
1755{
1756 struct kv_ps *new_ps = kv_get_ps(new_rps);
1757 struct kv_power_info *pi = kv_get_pi(rdev);
1758 int ret = 0;
1759 u8 clk_bypass_cntl;
1760
1761 if (pi->caps_enable_dfs_bypass) {
1762 clk_bypass_cntl = new_ps->need_dfs_bypass ?
1763 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1764 ret = kv_copy_bytes_to_smc(rdev,
1765 (pi->dpm_table_start +
1766 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
1767 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1768 offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
1769 &clk_bypass_cntl,
1770 sizeof(u8), pi->sram_end);
1771 }
1772
1773 return ret;
1774}
1775
1776static int kv_enable_nb_dpm(struct radeon_device *rdev)
1777{
1778 struct kv_power_info *pi = kv_get_pi(rdev);
1779 int ret = 0;
1780
1781 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1782 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
1783 if (ret == 0)
1784 pi->nb_dpm_enabled = true;
1785 }
1786
1787 return ret;
1788}
1789
1790int kv_dpm_force_performance_level(struct radeon_device *rdev,
1791 enum radeon_dpm_forced_level level)
1792{
1793 int ret;
1794
1795 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1796 ret = kv_force_dpm_highest(rdev);
1797 if (ret)
1798 return ret;
1799 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1800 ret = kv_force_dpm_lowest(rdev);
1801 if (ret)
1802 return ret;
1803 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
1804 ret = kv_unforce_levels(rdev);
1805 if (ret)
1806 return ret;
1807 }
1808
1809 rdev->pm.dpm.forced_level = level;
1810
1811 return 0;
1812}
1813
1814int kv_dpm_pre_set_power_state(struct radeon_device *rdev)
1815{
1816 struct kv_power_info *pi = kv_get_pi(rdev);
1817 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1818 struct radeon_ps *new_ps = &requested_ps;
1819
1820 kv_update_requested_ps(rdev, new_ps);
1821
1822 kv_apply_state_adjust_rules(rdev,
1823 &pi->requested_rps,
1824 &pi->current_rps);
1825
1826 return 0;
1827}
1828
1829int kv_dpm_set_power_state(struct radeon_device *rdev)
1830{
1831 struct kv_power_info *pi = kv_get_pi(rdev);
1832 struct radeon_ps *new_ps = &pi->requested_rps;
1833 struct radeon_ps *old_ps = &pi->current_rps;
1834 int ret;
1835
1836 if (pi->bapm_enable) {
1837 ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power);
1838 if (ret) {
1839 DRM_ERROR("kv_smc_bapm_enable failed\n");
1840 return ret;
1841 }
1842 }
1843
1844 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
1845 if (pi->enable_dpm) {
1846 kv_set_valid_clock_range(rdev, new_ps);
1847 kv_update_dfs_bypass_settings(rdev, new_ps);
1848 ret = kv_calculate_ds_divider(rdev);
1849 if (ret) {
1850 DRM_ERROR("kv_calculate_ds_divider failed\n");
1851 return ret;
1852 }
1853 kv_calculate_nbps_level_settings(rdev);
1854 kv_calculate_dpm_settings(rdev);
1855 kv_force_lowest_valid(rdev);
1856 kv_enable_new_levels(rdev);
1857 kv_upload_dpm_settings(rdev);
1858 kv_program_nbps_index_settings(rdev, new_ps);
1859 kv_unforce_levels(rdev);
1860 kv_set_enabled_levels(rdev);
1861 kv_force_lowest_valid(rdev);
1862 kv_unforce_levels(rdev);
1863
1864 ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1865 if (ret) {
1866 DRM_ERROR("kv_update_vce_dpm failed\n");
1867 return ret;
1868 }
1869 kv_update_sclk_t(rdev);
1870 if (rdev->family == CHIP_MULLINS)
1871 kv_enable_nb_dpm(rdev);
1872 }
1873 } else {
1874 if (pi->enable_dpm) {
1875 kv_set_valid_clock_range(rdev, new_ps);
1876 kv_update_dfs_bypass_settings(rdev, new_ps);
1877 ret = kv_calculate_ds_divider(rdev);
1878 if (ret) {
1879 DRM_ERROR("kv_calculate_ds_divider failed\n");
1880 return ret;
1881 }
1882 kv_calculate_nbps_level_settings(rdev);
1883 kv_calculate_dpm_settings(rdev);
1884 kv_freeze_sclk_dpm(rdev, true);
1885 kv_upload_dpm_settings(rdev);
1886 kv_program_nbps_index_settings(rdev, new_ps);
1887 kv_freeze_sclk_dpm(rdev, false);
1888 kv_set_enabled_levels(rdev);
1889 ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1890 if (ret) {
1891 DRM_ERROR("kv_update_vce_dpm failed\n");
1892 return ret;
1893 }
1894 kv_update_acp_boot_level(rdev);
1895 kv_update_sclk_t(rdev);
1896 kv_enable_nb_dpm(rdev);
1897 }
1898 }
1899
1900 return 0;
1901}
1902
1903void kv_dpm_post_set_power_state(struct radeon_device *rdev)
1904{
1905 struct kv_power_info *pi = kv_get_pi(rdev);
1906 struct radeon_ps *new_ps = &pi->requested_rps;
1907
1908 kv_update_current_ps(rdev, new_ps);
1909}
1910
1911void kv_dpm_setup_asic(struct radeon_device *rdev)
1912{
1913 sumo_take_smu_control(rdev, true);
1914 kv_init_powergate_state(rdev);
1915 kv_init_sclk_t(rdev);
1916}
1917
1918void kv_dpm_reset_asic(struct radeon_device *rdev)
1919{
1920 struct kv_power_info *pi = kv_get_pi(rdev);
1921
1922 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
1923 kv_force_lowest_valid(rdev);
1924 kv_init_graphics_levels(rdev);
1925 kv_program_bootup_state(rdev);
1926 kv_upload_dpm_settings(rdev);
1927 kv_force_lowest_valid(rdev);
1928 kv_unforce_levels(rdev);
1929 } else {
1930 kv_init_graphics_levels(rdev);
1931 kv_program_bootup_state(rdev);
1932 kv_freeze_sclk_dpm(rdev, true);
1933 kv_upload_dpm_settings(rdev);
1934 kv_freeze_sclk_dpm(rdev, false);
1935 kv_set_enabled_level(rdev, pi->graphics_boot_level);
1936 }
1937}
1938
1939//XXX use sumo_dpm_display_configuration_changed
1940
1941static void kv_construct_max_power_limits_table(struct radeon_device *rdev,
1942 struct radeon_clock_and_voltage_limits *table)
1943{
1944 struct kv_power_info *pi = kv_get_pi(rdev);
1945
1946 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
1947 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
1948 table->sclk =
1949 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
1950 table->vddc =
1951 kv_convert_2bit_index_to_voltage(rdev,
1952 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
1953 }
1954
1955 table->mclk = pi->sys_info.nbp_memory_clock[0];
1956}
1957
1958static void kv_patch_voltage_values(struct radeon_device *rdev)
1959{
1960 int i;
1961 struct radeon_uvd_clock_voltage_dependency_table *uvd_table =
1962 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1963 struct radeon_vce_clock_voltage_dependency_table *vce_table =
1964 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1965 struct radeon_clock_voltage_dependency_table *samu_table =
1966 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1967 struct radeon_clock_voltage_dependency_table *acp_table =
1968 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1969
1970 if (uvd_table->count) {
1971 for (i = 0; i < uvd_table->count; i++)
1972 uvd_table->entries[i].v =
1973 kv_convert_8bit_index_to_voltage(rdev,
1974 uvd_table->entries[i].v);
1975 }
1976
1977 if (vce_table->count) {
1978 for (i = 0; i < vce_table->count; i++)
1979 vce_table->entries[i].v =
1980 kv_convert_8bit_index_to_voltage(rdev,
1981 vce_table->entries[i].v);
1982 }
1983
1984 if (samu_table->count) {
1985 for (i = 0; i < samu_table->count; i++)
1986 samu_table->entries[i].v =
1987 kv_convert_8bit_index_to_voltage(rdev,
1988 samu_table->entries[i].v);
1989 }
1990
1991 if (acp_table->count) {
1992 for (i = 0; i < acp_table->count; i++)
1993 acp_table->entries[i].v =
1994 kv_convert_8bit_index_to_voltage(rdev,
1995 acp_table->entries[i].v);
1996 }
1997
1998}
1999
2000static void kv_construct_boot_state(struct radeon_device *rdev)
2001{
2002 struct kv_power_info *pi = kv_get_pi(rdev);
2003
2004 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
2005 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
2006 pi->boot_pl.ds_divider_index = 0;
2007 pi->boot_pl.ss_divider_index = 0;
2008 pi->boot_pl.allow_gnb_slow = 1;
2009 pi->boot_pl.force_nbp_state = 0;
2010 pi->boot_pl.display_wm = 0;
2011 pi->boot_pl.vce_wm = 0;
2012}
2013
2014static int kv_force_dpm_highest(struct radeon_device *rdev)
2015{
2016 int ret;
2017 u32 enable_mask, i;
2018
2019 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
2020 if (ret)
2021 return ret;
2022
2023 for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
2024 if (enable_mask & (1 << i))
2025 break;
2026 }
2027
2028 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2029 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
2030 else
2031 return kv_set_enabled_level(rdev, i);
2032}
2033
2034static int kv_force_dpm_lowest(struct radeon_device *rdev)
2035{
2036 int ret;
2037 u32 enable_mask, i;
2038
2039 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
2040 if (ret)
2041 return ret;
2042
2043 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2044 if (enable_mask & (1 << i))
2045 break;
2046 }
2047
2048 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2049 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
2050 else
2051 return kv_set_enabled_level(rdev, i);
2052}
2053
2054static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2055 u32 sclk, u32 min_sclk_in_sr)
2056{
2057 struct kv_power_info *pi = kv_get_pi(rdev);
2058 u32 i;
2059 u32 temp;
2060 u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ?
2061 min_sclk_in_sr : KV_MINIMUM_ENGINE_CLOCK;
2062
2063 if (sclk < min)
2064 return 0;
2065
2066 if (!pi->caps_sclk_ds)
2067 return 0;
2068
2069 for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
2070 temp = sclk / sumo_get_sleep_divider_from_id(i);
2071 if (temp >= min)
2072 break;
2073 }
2074
2075 return (u8)i;
2076}
2077
2078static int kv_get_high_voltage_limit(struct radeon_device *rdev, int *limit)
2079{
2080 struct kv_power_info *pi = kv_get_pi(rdev);
2081 struct radeon_clock_voltage_dependency_table *table =
2082 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2083 int i;
2084
2085 if (table && table->count) {
2086 for (i = table->count - 1; i >= 0; i--) {
2087 if (pi->high_voltage_t &&
2088 (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <=
2089 pi->high_voltage_t)) {
2090 *limit = i;
2091 return 0;
2092 }
2093 }
2094 } else {
2095 struct sumo_sclk_voltage_mapping_table *table =
2096 &pi->sys_info.sclk_voltage_mapping_table;
2097
2098 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
2099 if (pi->high_voltage_t &&
2100 (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <=
2101 pi->high_voltage_t)) {
2102 *limit = i;
2103 return 0;
2104 }
2105 }
2106 }
2107
2108 *limit = 0;
2109 return 0;
2110}
2111
2112static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
2113 struct radeon_ps *new_rps,
2114 struct radeon_ps *old_rps)
2115{
2116 struct kv_ps *ps = kv_get_ps(new_rps);
2117 struct kv_power_info *pi = kv_get_pi(rdev);
2118 u32 min_sclk = 10000; /* ??? */
2119 u32 sclk, mclk = 0;
2120 int i, limit;
2121 bool force_high;
2122 struct radeon_clock_voltage_dependency_table *table =
2123 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2124 u32 stable_p_state_sclk = 0;
2125 struct radeon_clock_and_voltage_limits *max_limits =
2126 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2127
2128 if (new_rps->vce_active) {
2129 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
2130 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
2131 } else {
2132 new_rps->evclk = 0;
2133 new_rps->ecclk = 0;
2134 }
2135
2136 mclk = max_limits->mclk;
2137 sclk = min_sclk;
2138
2139 if (pi->caps_stable_p_state) {
2140 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
2141
2142 for (i = table->count - 1; i >= 0; i++) {
2143 if (stable_p_state_sclk >= table->entries[i].clk) {
2144 stable_p_state_sclk = table->entries[i].clk;
2145 break;
2146 }
2147 }
2148
2149 if (i > 0)
2150 stable_p_state_sclk = table->entries[0].clk;
2151
2152 sclk = stable_p_state_sclk;
2153 }
2154
2155 if (new_rps->vce_active) {
2156 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
2157 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
2158 }
2159
2160 ps->need_dfs_bypass = true;
2161
2162 for (i = 0; i < ps->num_levels; i++) {
2163 if (ps->levels[i].sclk < sclk)
2164 ps->levels[i].sclk = sclk;
2165 }
2166
2167 if (table && table->count) {
2168 for (i = 0; i < ps->num_levels; i++) {
2169 if (pi->high_voltage_t &&
2170 (pi->high_voltage_t <
2171 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2172 kv_get_high_voltage_limit(rdev, &limit);
2173 ps->levels[i].sclk = table->entries[limit].clk;
2174 }
2175 }
2176 } else {
2177 struct sumo_sclk_voltage_mapping_table *table =
2178 &pi->sys_info.sclk_voltage_mapping_table;
2179
2180 for (i = 0; i < ps->num_levels; i++) {
2181 if (pi->high_voltage_t &&
2182 (pi->high_voltage_t <
2183 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2184 kv_get_high_voltage_limit(rdev, &limit);
2185 ps->levels[i].sclk = table->entries[limit].sclk_frequency;
2186 }
2187 }
2188 }
2189
2190 if (pi->caps_stable_p_state) {
2191 for (i = 0; i < ps->num_levels; i++) {
2192 ps->levels[i].sclk = stable_p_state_sclk;
2193 }
2194 }
2195
2196 pi->video_start = new_rps->dclk || new_rps->vclk ||
2197 new_rps->evclk || new_rps->ecclk;
2198
2199 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
2200 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
2201 pi->battery_state = true;
2202 else
2203 pi->battery_state = false;
2204
2205 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
2206 ps->dpm0_pg_nb_ps_lo = 0x1;
2207 ps->dpm0_pg_nb_ps_hi = 0x0;
2208 ps->dpmx_nb_ps_lo = 0x1;
2209 ps->dpmx_nb_ps_hi = 0x0;
2210 } else {
2211 ps->dpm0_pg_nb_ps_lo = 0x3;
2212 ps->dpm0_pg_nb_ps_hi = 0x0;
2213 ps->dpmx_nb_ps_lo = 0x3;
2214 ps->dpmx_nb_ps_hi = 0x0;
2215
2216 if (pi->sys_info.nb_dpm_enable) {
2217 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2218 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||
2219 pi->disable_nb_ps3_in_battery;
2220 ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
2221 ps->dpm0_pg_nb_ps_hi = 0x2;
2222 ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
2223 ps->dpmx_nb_ps_hi = 0x2;
2224 }
2225 }
2226}
2227
2228static void kv_dpm_power_level_enabled_for_throttle(struct radeon_device *rdev,
2229 u32 index, bool enable)
2230{
2231 struct kv_power_info *pi = kv_get_pi(rdev);
2232
2233 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2234}
2235
2236static int kv_calculate_ds_divider(struct radeon_device *rdev)
2237{
2238 struct kv_power_info *pi = kv_get_pi(rdev);
2239 u32 sclk_in_sr = 10000; /* ??? */
2240 u32 i;
2241
2242 if (pi->lowest_valid > pi->highest_valid)
2243 return -EINVAL;
2244
2245 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2246 pi->graphics_level[i].DeepSleepDivId =
2247 kv_get_sleep_divider_id_from_clock(rdev,
2248 be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2249 sclk_in_sr);
2250 }
2251 return 0;
2252}
2253
2254static int kv_calculate_nbps_level_settings(struct radeon_device *rdev)
2255{
2256 struct kv_power_info *pi = kv_get_pi(rdev);
2257 u32 i;
2258 bool force_high;
2259 struct radeon_clock_and_voltage_limits *max_limits =
2260 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2261 u32 mclk = max_limits->mclk;
2262
2263 if (pi->lowest_valid > pi->highest_valid)
2264 return -EINVAL;
2265
2266 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
2267 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2268 pi->graphics_level[i].GnbSlow = 1;
2269 pi->graphics_level[i].ForceNbPs1 = 0;
2270 pi->graphics_level[i].UpH = 0;
2271 }
2272
2273 if (!pi->sys_info.nb_dpm_enable)
2274 return 0;
2275
2276 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2277 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2278
2279 if (force_high) {
2280 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2281 pi->graphics_level[i].GnbSlow = 0;
2282 } else {
2283 if (pi->battery_state)
2284 pi->graphics_level[0].ForceNbPs1 = 1;
2285
2286 pi->graphics_level[1].GnbSlow = 0;
2287 pi->graphics_level[2].GnbSlow = 0;
2288 pi->graphics_level[3].GnbSlow = 0;
2289 pi->graphics_level[4].GnbSlow = 0;
2290 }
2291 } else {
2292 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2293 pi->graphics_level[i].GnbSlow = 1;
2294 pi->graphics_level[i].ForceNbPs1 = 0;
2295 pi->graphics_level[i].UpH = 0;
2296 }
2297
2298 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2299 pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2300 pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2301 if (pi->lowest_valid != pi->highest_valid)
2302 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2303 }
2304 }
2305 return 0;
2306}
2307
2308static int kv_calculate_dpm_settings(struct radeon_device *rdev)
2309{
2310 struct kv_power_info *pi = kv_get_pi(rdev);
2311 u32 i;
2312
2313 if (pi->lowest_valid > pi->highest_valid)
2314 return -EINVAL;
2315
2316 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2317 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2318
2319 return 0;
2320}
2321
2322static void kv_init_graphics_levels(struct radeon_device *rdev)
2323{
2324 struct kv_power_info *pi = kv_get_pi(rdev);
2325 u32 i;
2326 struct radeon_clock_voltage_dependency_table *table =
2327 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2328
2329 if (table && table->count) {
2330 u32 vid_2bit;
2331
2332 pi->graphics_dpm_level_count = 0;
2333 for (i = 0; i < table->count; i++) {
2334 if (pi->high_voltage_t &&
2335 (pi->high_voltage_t <
2336 kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v)))
2337 break;
2338
2339 kv_set_divider_value(rdev, i, table->entries[i].clk);
2340 vid_2bit = kv_convert_vid7_to_vid2(rdev,
2341 &pi->sys_info.vid_mapping_table,
2342 table->entries[i].v);
2343 kv_set_vid(rdev, i, vid_2bit);
2344 kv_set_at(rdev, i, pi->at[i]);
2345 kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2346 pi->graphics_dpm_level_count++;
2347 }
2348 } else {
2349 struct sumo_sclk_voltage_mapping_table *table =
2350 &pi->sys_info.sclk_voltage_mapping_table;
2351
2352 pi->graphics_dpm_level_count = 0;
2353 for (i = 0; i < table->num_max_dpm_entries; i++) {
2354 if (pi->high_voltage_t &&
2355 pi->high_voltage_t <
2356 kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit))
2357 break;
2358
2359 kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency);
2360 kv_set_vid(rdev, i, table->entries[i].vid_2bit);
2361 kv_set_at(rdev, i, pi->at[i]);
2362 kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2363 pi->graphics_dpm_level_count++;
2364 }
2365 }
2366
2367 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
2368 kv_dpm_power_level_enable(rdev, i, false);
2369}
2370
2371static void kv_enable_new_levels(struct radeon_device *rdev)
2372{
2373 struct kv_power_info *pi = kv_get_pi(rdev);
2374 u32 i;
2375
2376 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2377 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2378 kv_dpm_power_level_enable(rdev, i, true);
2379 }
2380}
2381
2382static int kv_set_enabled_level(struct radeon_device *rdev, u32 level)
2383{
2384 u32 new_mask = (1 << level);
2385
2386 return kv_send_msg_to_smc_with_parameter(rdev,
2387 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2388 new_mask);
2389}
2390
2391static int kv_set_enabled_levels(struct radeon_device *rdev)
2392{
2393 struct kv_power_info *pi = kv_get_pi(rdev);
2394 u32 i, new_mask = 0;
2395
2396 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2397 new_mask |= (1 << i);
2398
2399 return kv_send_msg_to_smc_with_parameter(rdev,
2400 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2401 new_mask);
2402}
2403
2404static void kv_program_nbps_index_settings(struct radeon_device *rdev,
2405 struct radeon_ps *new_rps)
2406{
2407 struct kv_ps *new_ps = kv_get_ps(new_rps);
2408 struct kv_power_info *pi = kv_get_pi(rdev);
2409 u32 nbdpmconfig1;
2410
2411 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2412 return;
2413
2414 if (pi->sys_info.nb_dpm_enable) {
2415 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1);
2416 nbdpmconfig1 &= ~(Dpm0PgNbPsLo_MASK | Dpm0PgNbPsHi_MASK |
2417 DpmXNbPsLo_MASK | DpmXNbPsHi_MASK);
2418 nbdpmconfig1 |= (Dpm0PgNbPsLo(new_ps->dpm0_pg_nb_ps_lo) |
2419 Dpm0PgNbPsHi(new_ps->dpm0_pg_nb_ps_hi) |
2420 DpmXNbPsLo(new_ps->dpmx_nb_ps_lo) |
2421 DpmXNbPsHi(new_ps->dpmx_nb_ps_hi));
2422 WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1);
2423 }
2424}
2425
2426static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
2427 int min_temp, int max_temp)
2428{
2429 int low_temp = 0 * 1000;
2430 int high_temp = 255 * 1000;
2431 u32 tmp;
2432
2433 if (low_temp < min_temp)
2434 low_temp = min_temp;
2435 if (high_temp > max_temp)
2436 high_temp = max_temp;
2437 if (high_temp < low_temp) {
2438 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
2439 return -EINVAL;
2440 }
2441
2442 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL);
2443 tmp &= ~(DIG_THERM_INTH_MASK | DIG_THERM_INTL_MASK);
2444 tmp |= (DIG_THERM_INTH(49 + (high_temp / 1000)) |
2445 DIG_THERM_INTL(49 + (low_temp / 1000)));
2446 WREG32_SMC(CG_THERMAL_INT_CTRL, tmp);
2447
2448 rdev->pm.dpm.thermal.min_temp = low_temp;
2449 rdev->pm.dpm.thermal.max_temp = high_temp;
2450
2451 return 0;
2452}
2453
2454union igp_info {
2455 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
2456 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2457 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
2458 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
2459 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
2460 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
2461};
2462
2463static int kv_parse_sys_info_table(struct radeon_device *rdev)
2464{
2465 struct kv_power_info *pi = kv_get_pi(rdev);
2466 struct radeon_mode_info *mode_info = &rdev->mode_info;
2467 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
2468 union igp_info *igp_info;
2469 u8 frev, crev;
2470 u16 data_offset;
2471 int i;
2472
2473 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2474 &frev, &crev, &data_offset)) {
2475 igp_info = (union igp_info *)(mode_info->atom_context->bios +
2476 data_offset);
2477
2478 if (crev != 8) {
2479 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
2480 return -EINVAL;
2481 }
2482 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2483 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2484 pi->sys_info.bootup_nb_voltage_index =
2485 le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
2486 if (igp_info->info_8.ucHtcTmpLmt == 0)
2487 pi->sys_info.htc_tmp_lmt = 203;
2488 else
2489 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2490 if (igp_info->info_8.ucHtcHystLmt == 0)
2491 pi->sys_info.htc_hyst_lmt = 5;
2492 else
2493 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2494 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2495 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
2496 }
2497
2498 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
2499 pi->sys_info.nb_dpm_enable = true;
2500 else
2501 pi->sys_info.nb_dpm_enable = false;
2502
2503 for (i = 0; i < KV_NUM_NBPSTATES; i++) {
2504 pi->sys_info.nbp_memory_clock[i] =
2505 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
2506 pi->sys_info.nbp_n_clock[i] =
2507 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
2508 }
2509 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
2510 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
2511 pi->caps_enable_dfs_bypass = true;
2512
2513 sumo_construct_sclk_voltage_mapping_table(rdev,
2514 &pi->sys_info.sclk_voltage_mapping_table,
2515 igp_info->info_8.sAvail_SCLK);
2516
2517 sumo_construct_vid_mapping_table(rdev,
2518 &pi->sys_info.vid_mapping_table,
2519 igp_info->info_8.sAvail_SCLK);
2520
2521 kv_construct_max_power_limits_table(rdev,
2522 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2523 }
2524 return 0;
2525}
2526
2527union power_info {
2528 struct _ATOM_POWERPLAY_INFO info;
2529 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2530 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2531 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2532 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2533 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2534};
2535
2536union pplib_clock_info {
2537 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2538 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2539 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2540 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2541};
2542
2543union pplib_power_state {
2544 struct _ATOM_PPLIB_STATE v1;
2545 struct _ATOM_PPLIB_STATE_V2 v2;
2546};
2547
2548static void kv_patch_boot_state(struct radeon_device *rdev,
2549 struct kv_ps *ps)
2550{
2551 struct kv_power_info *pi = kv_get_pi(rdev);
2552
2553 ps->num_levels = 1;
2554 ps->levels[0] = pi->boot_pl;
2555}
2556
2557static void kv_parse_pplib_non_clock_info(struct radeon_device *rdev,
2558 struct radeon_ps *rps,
2559 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
2560 u8 table_rev)
2561{
2562 struct kv_ps *ps = kv_get_ps(rps);
2563
2564 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2565 rps->class = le16_to_cpu(non_clock_info->usClassification);
2566 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
2567
2568 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2569 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2570 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2571 } else {
2572 rps->vclk = 0;
2573 rps->dclk = 0;
2574 }
2575
2576 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2577 rdev->pm.dpm.boot_ps = rps;
2578 kv_patch_boot_state(rdev, ps);
2579 }
2580 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
2581 rdev->pm.dpm.uvd_ps = rps;
2582}
2583
2584static void kv_parse_pplib_clock_info(struct radeon_device *rdev,
2585 struct radeon_ps *rps, int index,
2586 union pplib_clock_info *clock_info)
2587{
2588 struct kv_power_info *pi = kv_get_pi(rdev);
2589 struct kv_ps *ps = kv_get_ps(rps);
2590 struct kv_pl *pl = &ps->levels[index];
2591 u32 sclk;
2592
2593 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2594 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2595 pl->sclk = sclk;
2596 pl->vddc_index = clock_info->sumo.vddcIndex;
2597
2598 ps->num_levels = index + 1;
2599
2600 if (pi->caps_sclk_ds) {
2601 pl->ds_divider_index = 5;
2602 pl->ss_divider_index = 5;
2603 }
2604}
2605
2606static int kv_parse_power_table(struct radeon_device *rdev)
2607{
2608 struct radeon_mode_info *mode_info = &rdev->mode_info;
2609 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2610 union pplib_power_state *power_state;
2611 int i, j, k, non_clock_array_index, clock_array_index;
2612 union pplib_clock_info *clock_info;
2613 struct _StateArray *state_array;
2614 struct _ClockInfoArray *clock_info_array;
2615 struct _NonClockInfoArray *non_clock_info_array;
2616 union power_info *power_info;
2617 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2618 u16 data_offset;
2619 u8 frev, crev;
2620 u8 *power_state_offset;
2621 struct kv_ps *ps;
2622
2623 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2624 &frev, &crev, &data_offset))
2625 return -EINVAL;
2626 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2627
2628 state_array = (struct _StateArray *)
2629 (mode_info->atom_context->bios + data_offset +
2630 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2631 clock_info_array = (struct _ClockInfoArray *)
2632 (mode_info->atom_context->bios + data_offset +
2633 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2634 non_clock_info_array = (struct _NonClockInfoArray *)
2635 (mode_info->atom_context->bios + data_offset +
2636 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2637
2638 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
2639 state_array->ucNumEntries, GFP_KERNEL);
2640 if (!rdev->pm.dpm.ps)
2641 return -ENOMEM;
2642 power_state_offset = (u8 *)state_array->states;
2643 for (i = 0; i < state_array->ucNumEntries; i++) {
2644 u8 *idx;
2645 power_state = (union pplib_power_state *)power_state_offset;
2646 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2647 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2648 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2649 if (!rdev->pm.power_state[i].clock_info)
2650 return -EINVAL;
2651 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
2652 if (ps == NULL) {
2653 kfree(rdev->pm.dpm.ps);
2654 return -ENOMEM;
2655 }
2656 rdev->pm.dpm.ps[i].ps_priv = ps;
2657 k = 0;
2658 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
2659 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2660 clock_array_index = idx[j];
2661 if (clock_array_index >= clock_info_array->ucNumEntries)
2662 continue;
2663 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
2664 break;
2665 clock_info = (union pplib_clock_info *)
2666 ((u8 *)&clock_info_array->clockInfo[0] +
2667 (clock_array_index * clock_info_array->ucEntrySize));
2668 kv_parse_pplib_clock_info(rdev,
2669 &rdev->pm.dpm.ps[i], k,
2670 clock_info);
2671 k++;
2672 }
2673 kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
2674 non_clock_info,
2675 non_clock_info_array->ucEntrySize);
2676 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2677 }
2678 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
2679
2680 /* fill in the vce power states */
2681 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
2682 u32 sclk;
2683 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
2684 clock_info = (union pplib_clock_info *)
2685 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2686 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2687 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2688 rdev->pm.dpm.vce_states[i].sclk = sclk;
2689 rdev->pm.dpm.vce_states[i].mclk = 0;
2690 }
2691
2692 return 0;
2693}
2694
2695int kv_dpm_init(struct radeon_device *rdev)
2696{
2697 struct kv_power_info *pi;
2698 int ret, i;
2699
2700 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2701 if (pi == NULL)
2702 return -ENOMEM;
2703 rdev->pm.dpm.priv = pi;
2704
2705 ret = r600_get_platform_caps(rdev);
2706 if (ret)
2707 return ret;
2708
2709 ret = r600_parse_extended_power_table(rdev);
2710 if (ret)
2711 return ret;
2712
2713 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
2714 pi->at[i] = TRINITY_AT_DFLT;
2715
2716 pi->sram_end = SMC_RAM_END;
2717
2718 pi->enable_nb_dpm = true;
2719
2720 pi->caps_power_containment = true;
2721 pi->caps_cac = true;
2722 pi->enable_didt = false;
2723 if (pi->enable_didt) {
2724 pi->caps_sq_ramping = true;
2725 pi->caps_db_ramping = true;
2726 pi->caps_td_ramping = true;
2727 pi->caps_tcp_ramping = true;
2728 }
2729
2730 pi->caps_sclk_ds = true;
2731 pi->enable_auto_thermal_throttling = true;
2732 pi->disable_nb_ps3_in_battery = false;
2733 pi->bapm_enable = false;
2734 pi->voltage_drop_t = 0;
2735 pi->caps_sclk_throttle_low_notification = false;
2736 pi->caps_fps = false; /* true? */
2737 pi->caps_uvd_pg = true;
2738 pi->caps_uvd_dpm = true;
2739 pi->caps_vce_pg = false; /* XXX true */
2740 pi->caps_samu_pg = false;
2741 pi->caps_acp_pg = false;
2742 pi->caps_stable_p_state = false;
2743
2744 ret = kv_parse_sys_info_table(rdev);
2745 if (ret)
2746 return ret;
2747
2748 kv_patch_voltage_values(rdev);
2749 kv_construct_boot_state(rdev);
2750
2751 ret = kv_parse_power_table(rdev);
2752 if (ret)
2753 return ret;
2754
2755 pi->enable_dpm = true;
2756
2757 return 0;
2758}
2759
2760#ifdef CONFIG_DEBUG_FS
2761void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2762 struct seq_file *m)
2763{
2764 struct kv_power_info *pi = kv_get_pi(rdev);
2765 u32 current_index =
2766 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>
2767 CURR_SCLK_INDEX_SHIFT;
2768 u32 sclk, tmp;
2769 u16 vddc;
2770
2771 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2772 seq_printf(m, "invalid dpm profile %d\n", current_index);
2773 } else {
2774 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2775 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2776 SMU_VOLTAGE_CURRENT_LEVEL_SHIFT;
2777 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp);
2778 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
2779 current_index, sclk, vddc);
2780 }
2781}
2782#endif /* CONFIG_DEBUG_FS */
2783
2784void kv_dpm_print_power_state(struct radeon_device *rdev,
2785 struct radeon_ps *rps)
2786{
2787 int i;
2788 struct kv_ps *ps = kv_get_ps(rps);
2789
2790 r600_dpm_print_class_info(rps->class, rps->class2);
2791 r600_dpm_print_cap_info(rps->caps);
2792 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2793 for (i = 0; i < ps->num_levels; i++) {
2794 struct kv_pl *pl = &ps->levels[i];
2795 printk("\t\tpower level %d sclk: %u vddc: %u\n",
2796 i, pl->sclk,
2797 kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index));
2798 }
2799 r600_dpm_print_ps_status(rdev, rps);
2800}
2801
2802void kv_dpm_fini(struct radeon_device *rdev)
2803{
2804 int i;
2805
2806 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2807 kfree(rdev->pm.dpm.ps[i].ps_priv);
2808 }
2809 kfree(rdev->pm.dpm.ps);
2810 kfree(rdev->pm.dpm.priv);
2811 r600_free_extended_power_table(rdev);
2812}
2813
2814void kv_dpm_display_configuration_changed(struct radeon_device *rdev)
2815{
2816
2817}
2818
2819u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low)
2820{
2821 struct kv_power_info *pi = kv_get_pi(rdev);
2822 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2823
2824 if (low)
2825 return requested_state->levels[0].sclk;
2826 else
2827 return requested_state->levels[requested_state->num_levels - 1].sclk;
2828}
2829
2830u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low)
2831{
2832 struct kv_power_info *pi = kv_get_pi(rdev);
2833
2834 return pi->sys_info.bootup_uma_clk;
2835}
2836
2837