1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
3 | * Copyright © 2006-2007 Intel Corporation |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice (including the next |
13 | * paragraph) shall be included in all copies or substantial portions of the |
14 | * Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
22 | * DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: |
25 | * Eric Anholt <eric@anholt.net> |
26 | */ |
27 | #include <linux/i2c.h> |
28 | #include <linux/slab.h> |
29 | #include <drm/drmP.h> |
30 | #include <drm/drm_crtc.h> |
31 | #include "intel_drv.h" |
32 | #include <drm/i915_drm.h> |
33 | #include "i915_drv.h" |
34 | #include "dvo.h" |
35 | |
36 | #define SIL164_ADDR 0x38 |
37 | #define CH7xxx_ADDR 0x76 |
38 | #define TFP410_ADDR 0x38 |
39 | #define NS2501_ADDR 0x38 |
40 | |
41 | static const struct intel_dvo_device intel_dvo_devices[] = { |
42 | { |
43 | .type = INTEL_DVO_CHIP_TMDS, |
44 | .name = "sil164" , |
45 | .dvo_reg = DVOC, |
46 | .slave_addr = SIL164_ADDR, |
47 | .dev_ops = &sil164_ops, |
48 | }, |
49 | { |
50 | .type = INTEL_DVO_CHIP_TMDS, |
51 | .name = "ch7xxx" , |
52 | .dvo_reg = DVOC, |
53 | .slave_addr = CH7xxx_ADDR, |
54 | .dev_ops = &ch7xxx_ops, |
55 | }, |
56 | { |
57 | .type = INTEL_DVO_CHIP_TMDS, |
58 | .name = "ch7xxx" , |
59 | .dvo_reg = DVOC, |
60 | .slave_addr = 0x75, /* For some ch7010 */ |
61 | .dev_ops = &ch7xxx_ops, |
62 | }, |
63 | { |
64 | .type = INTEL_DVO_CHIP_LVDS, |
65 | .name = "ivch" , |
66 | .dvo_reg = DVOA, |
67 | .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ |
68 | .dev_ops = &ivch_ops, |
69 | }, |
70 | { |
71 | .type = INTEL_DVO_CHIP_TMDS, |
72 | .name = "tfp410" , |
73 | .dvo_reg = DVOC, |
74 | .slave_addr = TFP410_ADDR, |
75 | .dev_ops = &tfp410_ops, |
76 | }, |
77 | { |
78 | .type = INTEL_DVO_CHIP_LVDS, |
79 | .name = "ch7017" , |
80 | .dvo_reg = DVOC, |
81 | .slave_addr = 0x75, |
82 | .gpio = GMBUS_PORT_DPB, |
83 | .dev_ops = &ch7017_ops, |
84 | }, |
85 | { |
86 | .type = INTEL_DVO_CHIP_TMDS, |
87 | .name = "ns2501" , |
88 | .dvo_reg = DVOC, |
89 | .slave_addr = NS2501_ADDR, |
90 | .dev_ops = &ns2501_ops, |
91 | } |
92 | }; |
93 | |
94 | struct intel_dvo { |
95 | struct intel_encoder base; |
96 | |
97 | struct intel_dvo_device dev; |
98 | |
99 | struct drm_display_mode *panel_fixed_mode; |
100 | bool panel_wants_dither; |
101 | }; |
102 | |
103 | static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder) |
104 | { |
105 | return container_of(encoder, struct intel_dvo, base); |
106 | } |
107 | |
108 | static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector) |
109 | { |
110 | return enc_to_dvo(intel_attached_encoder(connector)); |
111 | } |
112 | |
113 | static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) |
114 | { |
115 | struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base); |
116 | |
117 | return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev); |
118 | } |
119 | |
120 | static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, |
121 | enum i915_pipe *pipe) |
122 | { |
123 | struct drm_device *dev = encoder->base.dev; |
124 | struct drm_i915_private *dev_priv = dev->dev_private; |
125 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
126 | u32 tmp; |
127 | |
128 | tmp = I915_READ(intel_dvo->dev.dvo_reg); |
129 | |
130 | if (!(tmp & DVO_ENABLE)) |
131 | return false; |
132 | |
133 | *pipe = PORT_TO_PIPE(tmp); |
134 | |
135 | return true; |
136 | } |
137 | |
138 | static void intel_dvo_get_config(struct intel_encoder *encoder, |
139 | struct intel_crtc_config *pipe_config) |
140 | { |
141 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
142 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
143 | u32 tmp, flags = 0; |
144 | |
145 | tmp = I915_READ(intel_dvo->dev.dvo_reg); |
146 | if (tmp & DVO_HSYNC_ACTIVE_HIGH) |
147 | flags |= DRM_MODE_FLAG_PHSYNC; |
148 | else |
149 | flags |= DRM_MODE_FLAG_NHSYNC; |
150 | if (tmp & DVO_VSYNC_ACTIVE_HIGH) |
151 | flags |= DRM_MODE_FLAG_PVSYNC; |
152 | else |
153 | flags |= DRM_MODE_FLAG_NVSYNC; |
154 | |
155 | pipe_config->adjusted_mode.flags |= flags; |
156 | |
157 | pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; |
158 | } |
159 | |
160 | static void intel_disable_dvo(struct intel_encoder *encoder) |
161 | { |
162 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
163 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
164 | u32 dvo_reg = intel_dvo->dev.dvo_reg; |
165 | u32 temp = I915_READ(dvo_reg); |
166 | |
167 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); |
168 | I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); |
169 | I915_READ(dvo_reg); |
170 | } |
171 | |
172 | static void intel_enable_dvo(struct intel_encoder *encoder) |
173 | { |
174 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
175 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
176 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
177 | u32 dvo_reg = intel_dvo->dev.dvo_reg; |
178 | u32 temp = I915_READ(dvo_reg); |
179 | |
180 | I915_WRITE(dvo_reg, temp | DVO_ENABLE); |
181 | I915_READ(dvo_reg); |
182 | intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, |
183 | &crtc->config.requested_mode, |
184 | &crtc->config.adjusted_mode); |
185 | |
186 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); |
187 | } |
188 | |
189 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
190 | static void intel_dvo_dpms(struct drm_connector *connector, int mode) |
191 | { |
192 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
193 | struct drm_crtc *crtc; |
194 | struct intel_crtc_config *config; |
195 | |
196 | /* dvo supports only 2 dpms states. */ |
197 | if (mode != DRM_MODE_DPMS_ON) |
198 | mode = DRM_MODE_DPMS_OFF; |
199 | |
200 | if (mode == connector->dpms) |
201 | return; |
202 | |
203 | connector->dpms = mode; |
204 | |
205 | /* Only need to change hw state when actually enabled */ |
206 | crtc = intel_dvo->base.base.crtc; |
207 | if (!crtc) { |
208 | intel_dvo->base.connectors_active = false; |
209 | return; |
210 | } |
211 | |
212 | /* We call connector dpms manually below in case pipe dpms doesn't |
213 | * change due to cloning. */ |
214 | if (mode == DRM_MODE_DPMS_ON) { |
215 | config = &to_intel_crtc(crtc)->config; |
216 | |
217 | intel_dvo->base.connectors_active = true; |
218 | |
219 | intel_crtc_update_dpms(crtc); |
220 | |
221 | intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, |
222 | &config->requested_mode, |
223 | &config->adjusted_mode); |
224 | |
225 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); |
226 | } else { |
227 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); |
228 | |
229 | intel_dvo->base.connectors_active = false; |
230 | |
231 | intel_crtc_update_dpms(crtc); |
232 | } |
233 | |
234 | intel_modeset_check_state(connector->dev); |
235 | } |
236 | |
237 | static enum drm_mode_status |
238 | intel_dvo_mode_valid(struct drm_connector *connector, |
239 | struct drm_display_mode *mode) |
240 | { |
241 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
242 | |
243 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
244 | return MODE_NO_DBLESCAN; |
245 | |
246 | /* XXX: Validate clock range */ |
247 | |
248 | if (intel_dvo->panel_fixed_mode) { |
249 | if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay) |
250 | return MODE_PANEL; |
251 | if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay) |
252 | return MODE_PANEL; |
253 | } |
254 | |
255 | return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); |
256 | } |
257 | |
258 | static bool intel_dvo_compute_config(struct intel_encoder *encoder, |
259 | struct intel_crtc_config *pipe_config) |
260 | { |
261 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
262 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
263 | |
264 | /* If we have timings from the BIOS for the panel, put them in |
265 | * to the adjusted mode. The CRTC will be set up for this mode, |
266 | * with the panel scaling set up to source from the H/VDisplay |
267 | * of the original mode. |
268 | */ |
269 | if (intel_dvo->panel_fixed_mode != NULL) { |
270 | #define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x |
271 | C(hdisplay); |
272 | C(hsync_start); |
273 | C(hsync_end); |
274 | C(htotal); |
275 | C(vdisplay); |
276 | C(vsync_start); |
277 | C(vsync_end); |
278 | C(vtotal); |
279 | C(clock); |
280 | #undef C |
281 | |
282 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
283 | } |
284 | |
285 | return true; |
286 | } |
287 | |
288 | static void intel_dvo_mode_set(struct intel_encoder *encoder) |
289 | { |
290 | struct drm_device *dev = encoder->base.dev; |
291 | struct drm_i915_private *dev_priv = dev->dev_private; |
292 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
293 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
294 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
295 | int pipe = crtc->pipe; |
296 | u32 dvo_val; |
297 | u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg; |
298 | |
299 | switch (dvo_reg) { |
300 | case DVOA: |
301 | default: |
302 | dvo_srcdim_reg = DVOA_SRCDIM; |
303 | break; |
304 | case DVOB: |
305 | dvo_srcdim_reg = DVOB_SRCDIM; |
306 | break; |
307 | case DVOC: |
308 | dvo_srcdim_reg = DVOC_SRCDIM; |
309 | break; |
310 | } |
311 | |
312 | /* Save the data order, since I don't know what it should be set to. */ |
313 | dvo_val = I915_READ(dvo_reg) & |
314 | (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG); |
315 | dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | |
316 | DVO_BLANK_ACTIVE_HIGH; |
317 | |
318 | if (pipe == 1) |
319 | dvo_val |= DVO_PIPE_B_SELECT; |
320 | dvo_val |= DVO_PIPE_STALL; |
321 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
322 | dvo_val |= DVO_HSYNC_ACTIVE_HIGH; |
323 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
324 | dvo_val |= DVO_VSYNC_ACTIVE_HIGH; |
325 | |
326 | /*I915_WRITE(DVOB_SRCDIM, |
327 | (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | |
328 | (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/ |
329 | I915_WRITE(dvo_srcdim_reg, |
330 | (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | |
331 | (adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); |
332 | /*I915_WRITE(DVOB, dvo_val);*/ |
333 | I915_WRITE(dvo_reg, dvo_val); |
334 | } |
335 | |
336 | /** |
337 | * Detect the output connection on our DVO device. |
338 | * |
339 | * Unimplemented. |
340 | */ |
341 | static enum drm_connector_status |
342 | intel_dvo_detect(struct drm_connector *connector, bool force) |
343 | { |
344 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
345 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n" , |
346 | connector->base.id, drm_get_connector_name(connector)); |
347 | return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); |
348 | } |
349 | |
350 | static int intel_dvo_get_modes(struct drm_connector *connector) |
351 | { |
352 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
353 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
354 | |
355 | /* We should probably have an i2c driver get_modes function for those |
356 | * devices which will have a fixed set of modes determined by the chip |
357 | * (TV-out, for example), but for now with just TMDS and LVDS, |
358 | * that's not the case. |
359 | */ |
360 | intel_ddc_get_modes(connector, |
361 | intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPC)); |
362 | if (!list_empty(&connector->probed_modes)) |
363 | return 1; |
364 | |
365 | if (intel_dvo->panel_fixed_mode != NULL) { |
366 | struct drm_display_mode *mode; |
367 | mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode); |
368 | if (mode) { |
369 | drm_mode_probed_add(connector, mode); |
370 | return 1; |
371 | } |
372 | } |
373 | |
374 | return 0; |
375 | } |
376 | |
377 | static void intel_dvo_destroy(struct drm_connector *connector) |
378 | { |
379 | drm_connector_cleanup(connector); |
380 | kfree(connector); |
381 | } |
382 | |
383 | static const struct drm_connector_funcs intel_dvo_connector_funcs = { |
384 | .dpms = intel_dvo_dpms, |
385 | .detect = intel_dvo_detect, |
386 | .destroy = intel_dvo_destroy, |
387 | .fill_modes = drm_helper_probe_single_connector_modes, |
388 | }; |
389 | |
390 | static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { |
391 | .mode_valid = intel_dvo_mode_valid, |
392 | .get_modes = intel_dvo_get_modes, |
393 | .best_encoder = intel_best_encoder, |
394 | }; |
395 | |
396 | static void intel_dvo_enc_destroy(struct drm_encoder *encoder) |
397 | { |
398 | struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder)); |
399 | |
400 | if (intel_dvo->dev.dev_ops->destroy) |
401 | intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); |
402 | |
403 | kfree(intel_dvo->panel_fixed_mode); |
404 | |
405 | intel_encoder_destroy(encoder); |
406 | } |
407 | |
408 | static const struct drm_encoder_funcs intel_dvo_enc_funcs = { |
409 | .destroy = intel_dvo_enc_destroy, |
410 | }; |
411 | |
412 | /** |
413 | * Attempts to get a fixed panel timing for LVDS (currently only the i830). |
414 | * |
415 | * Other chips with DVO LVDS will need to extend this to deal with the LVDS |
416 | * chip being on DVOB/C and having multiple pipes. |
417 | */ |
418 | static struct drm_display_mode * |
419 | intel_dvo_get_current_mode(struct drm_connector *connector) |
420 | { |
421 | struct drm_device *dev = connector->dev; |
422 | struct drm_i915_private *dev_priv = dev->dev_private; |
423 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
424 | uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg); |
425 | struct drm_display_mode *mode = NULL; |
426 | |
427 | /* If the DVO port is active, that'll be the LVDS, so we can pull out |
428 | * its timings to get how the BIOS set up the panel. |
429 | */ |
430 | if (dvo_val & DVO_ENABLE) { |
431 | struct drm_crtc *crtc; |
432 | int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0; |
433 | |
434 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
435 | if (crtc) { |
436 | mode = intel_crtc_mode_get(dev, crtc); |
437 | if (mode) { |
438 | mode->type |= DRM_MODE_TYPE_PREFERRED; |
439 | if (dvo_val & DVO_HSYNC_ACTIVE_HIGH) |
440 | mode->flags |= DRM_MODE_FLAG_PHSYNC; |
441 | if (dvo_val & DVO_VSYNC_ACTIVE_HIGH) |
442 | mode->flags |= DRM_MODE_FLAG_PVSYNC; |
443 | } |
444 | } |
445 | } |
446 | |
447 | return mode; |
448 | } |
449 | |
450 | void intel_dvo_init(struct drm_device *dev) |
451 | { |
452 | struct drm_i915_private *dev_priv = dev->dev_private; |
453 | struct intel_encoder *intel_encoder; |
454 | struct intel_dvo *intel_dvo; |
455 | struct intel_connector *intel_connector; |
456 | int i; |
457 | int encoder_type = DRM_MODE_ENCODER_NONE; |
458 | |
459 | intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL); |
460 | if (!intel_dvo) |
461 | return; |
462 | |
463 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
464 | if (!intel_connector) { |
465 | kfree(intel_dvo); |
466 | return; |
467 | } |
468 | |
469 | intel_encoder = &intel_dvo->base; |
470 | drm_encoder_init(dev, &intel_encoder->base, |
471 | &intel_dvo_enc_funcs, encoder_type); |
472 | |
473 | intel_encoder->disable = intel_disable_dvo; |
474 | intel_encoder->enable = intel_enable_dvo; |
475 | intel_encoder->get_hw_state = intel_dvo_get_hw_state; |
476 | intel_encoder->get_config = intel_dvo_get_config; |
477 | intel_encoder->compute_config = intel_dvo_compute_config; |
478 | intel_encoder->mode_set = intel_dvo_mode_set; |
479 | intel_connector->get_hw_state = intel_dvo_connector_get_hw_state; |
480 | intel_connector->unregister = intel_connector_unregister; |
481 | |
482 | /* Now, try to find a controller */ |
483 | for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { |
484 | struct drm_connector *connector = &intel_connector->base; |
485 | const struct intel_dvo_device *dvo = &intel_dvo_devices[i]; |
486 | struct i2c_adapter *i2c; |
487 | int gpio; |
488 | bool dvoinit; |
489 | |
490 | /* Allow the I2C driver info to specify the GPIO to be used in |
491 | * special cases, but otherwise default to what's defined |
492 | * in the spec. |
493 | */ |
494 | if (intel_gmbus_is_port_valid(dvo->gpio)) |
495 | gpio = dvo->gpio; |
496 | else if (dvo->type == INTEL_DVO_CHIP_LVDS) |
497 | gpio = GMBUS_PORT_SSC; |
498 | else |
499 | gpio = GMBUS_PORT_DPB; |
500 | |
501 | /* Set up the I2C bus necessary for the chip we're probing. |
502 | * It appears that everything is on GPIOE except for panels |
503 | * on i830 laptops, which are on GPIOB (DVOA). |
504 | */ |
505 | i2c = intel_gmbus_get_adapter(dev_priv, gpio); |
506 | |
507 | intel_dvo->dev = *dvo; |
508 | |
509 | /* GMBUS NAK handling seems to be unstable, hence let the |
510 | * transmitter detection run in bit banging mode for now. |
511 | */ |
512 | intel_gmbus_force_bit(i2c, true); |
513 | |
514 | dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c); |
515 | |
516 | intel_gmbus_force_bit(i2c, false); |
517 | |
518 | if (!dvoinit) |
519 | continue; |
520 | |
521 | intel_encoder->type = INTEL_OUTPUT_DVO; |
522 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
523 | switch (dvo->type) { |
524 | case INTEL_DVO_CHIP_TMDS: |
525 | intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) | |
526 | (1 << INTEL_OUTPUT_DVO); |
527 | drm_connector_init(dev, connector, |
528 | &intel_dvo_connector_funcs, |
529 | DRM_MODE_CONNECTOR_DVII); |
530 | encoder_type = DRM_MODE_ENCODER_TMDS; |
531 | break; |
532 | case INTEL_DVO_CHIP_LVDS: |
533 | intel_encoder->cloneable = 0; |
534 | drm_connector_init(dev, connector, |
535 | &intel_dvo_connector_funcs, |
536 | DRM_MODE_CONNECTOR_LVDS); |
537 | encoder_type = DRM_MODE_ENCODER_LVDS; |
538 | break; |
539 | } |
540 | |
541 | drm_connector_helper_add(connector, |
542 | &intel_dvo_connector_helper_funcs); |
543 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; |
544 | connector->interlace_allowed = false; |
545 | connector->doublescan_allowed = false; |
546 | |
547 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
548 | if (dvo->type == INTEL_DVO_CHIP_LVDS) { |
549 | /* For our LVDS chipsets, we should hopefully be able |
550 | * to dig the fixed panel mode out of the BIOS data. |
551 | * However, it's in a different format from the BIOS |
552 | * data on chipsets with integrated LVDS (stored in AIM |
553 | * headers, likely), so for now, just get the current |
554 | * mode being output through DVO. |
555 | */ |
556 | intel_dvo->panel_fixed_mode = |
557 | intel_dvo_get_current_mode(connector); |
558 | intel_dvo->panel_wants_dither = true; |
559 | } |
560 | |
561 | drm_sysfs_connector_add(connector); |
562 | return; |
563 | } |
564 | |
565 | drm_encoder_cleanup(&intel_encoder->base); |
566 | kfree(intel_dvo); |
567 | kfree(intel_connector); |
568 | } |
569 | |