1/* $NetBSD: xhcireg.h,v 1.8 2016/09/03 12:05:36 skrll Exp $ */
2
3/*-
4 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#ifndef _DEV_USB_XHCIREG_H_
29#define _DEV_USB_XHCIREG_H_
30
31/* XHCI PCI config registers */
32#define PCI_CBMEM 0x10 /* configuration base MEM */
33#define PCI_INTERFACE_XHCI 0x30
34
35#define PCI_USBREV 0x60 /* RO USB protocol revision */
36#define PCI_USBREV_MASK 0xFF
37#define PCI_USBREV_3_0 0x30 /* USB 3.0 */
38
39#define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */
40
41#define PCI_XHCI_INTEL_XUSB2PR 0xD0 /* Intel USB2 Port Routing */
42#define PCI_XHCI_INTEL_USB2PRM 0xD4 /* Intel USB2 Port Routing Mask */
43#define PCI_XHCI_INTEL_USB3_PSSEN 0xD8 /* Intel USB3 Port SuperSpeed Enable */
44#define PCI_XHCI_INTEL_USB3PRM 0xDC /* Intel USB3 Port Routing Mask */
45
46/* XHCI capability registers */
47#define XHCI_CAPLENGTH 0x00 /* RO capability */
48#define XHCI_CAP_CAPLENGTH(x) ((x) & 0xFF)
49#define XHCI_CAP_HCIVERSION(x) (((x) >> 16) & 0xFFFF) /* RO Interface version number */
50#define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */
51#define XHCI_HCIVERSION_0_96 0x0096 /* xHCI version 0.96 */
52#define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */
53
54#define XHCI_HCSPARAMS1 0x04 /* RO structual parameters 1 */
55#define XHCI_HCS1_MAXSLOTS(x) ((x) & 0xFF)
56#define XHCI_HCS1_MAXINTRS(x) (((x) >> 8) & 0x7FF)
57#define XHCI_HCS1_MAXPORTS(x) (((x) >> 24) & 0xFF)
58
59#define XHCI_HCSPARAMS2 0x08 /* RO structual parameters 2 */
60#define XHCI_HCS2_IST(x) ((x) & 0xF)
61#define XHCI_HCS2_ERST_MAX(x) (((x) >> 4) & 0xF)
62#define XHCI_HCS2_SPR(x) (((x) >> 24) & 0x1)
63#define XHCI_HCS2_SPBUFLO __BITS(31, 27)
64#define XHCI_HCS2_SPBUFHI __BITS(25, 21)
65#define XHCI_HCS2_MAXSPBUF(x) \
66 (__SHIFTOUT((x), XHCI_HCS2_SPBUFHI) << 5) | \
67 (__SHIFTOUT((x), XHCI_HCS2_SPBUFLO))
68
69#define XHCI_HCSPARAMS3 0x0C /* RO structual parameters 3 */
70#define XHCI_HCS3_U1_DEL(x) ((x) & 0xFF)
71#define XHCI_HCS3_U2_DEL(x) (((x) >> 16) & 0xFFFF)
72
73#define XHCI_HCCPARAMS 0x10 /* RO capability parameters */
74#define XHCI_HCC_AC64(x) (((x) >> 0) & 0x1) /* 64-bit capable */
75#define XHCI_HCC_BNC(x) (((x) >> 1) & 0x1) /* BW negotiation */
76#define XHCI_HCC_CSZ(x) (((x) >> 2) & 0x1) /* context size */
77#define XHCI_HCC_PPC(x) (((x) >> 3) & 0x1) /* port power control */
78#define XHCI_HCC_PIND(x) (((x) >> 4) & 0x1) /* port indicators */
79#define XHCI_HCC_LHRC(x) (((x) >> 5) & 0x1) /* light HC reset */
80#define XHCI_HCC_LTC(x) (((x) >> 6) & 0x1) /* latency tolerance msg */
81#define XHCI_HCC_NSS(x) (((x) >> 7) & 0x1) /* no secondary sid */
82#define XHCI_HCC_PAE(x) (((x) >> 8) & 0x1) /* Parse All Event Data */
83#define XHCI_HCC_SPC(x) (((x) >> 9) & 0x1) /* Short packet */
84#define XHCI_HCC_SEC(x) (((x) >> 10) & 0x1) /* Stopped EDTLA */
85#define XHCI_HCC_CFC(x) (((x) >> 11) & 0x1) /* Configuous Frame ID */
86#define XHCI_HCC_MAXPSASIZE(x) (((x) >> 12) & 0xF) /* max pri. stream array size */
87#define XHCI_HCC_XECP(x) (((x) >> 16) & 0xFFFF) /* extended capabilities pointer */
88
89#define XHCI_DBOFF 0x14 /* RO doorbell offset */
90#define XHCI_RTSOFF 0x18 /* RO runtime register space offset */
91
92/* XHCI operational registers. Offset given by XHCI_CAPLENGTH register */
93#define XHCI_USBCMD 0x00 /* XHCI command */
94#define XHCI_CMD_RS 0x00000001 /* RW Run/Stop */
95#define XHCI_CMD_HCRST 0x00000002 /* RW Host Controller Reset */
96#define XHCI_CMD_INTE 0x00000004 /* RW Interrupter Enable */
97#define XHCI_CMD_HSEE 0x00000008 /* RW Host System Error Enable */
98#define XHCI_CMD_LHCRST 0x00000080 /* RO/RW Light Host Controller Reset */
99#define XHCI_CMD_CSS 0x00000100 /* RW Controller Save State */
100#define XHCI_CMD_CRS 0x00000200 /* RW Controller Restore State */
101#define XHCI_CMD_EWE 0x00000400 /* RW Enable Wrap Event */
102#define XHCI_CMD_EU3S 0x00000800 /* RW Enable U3 MFINDEX Stop */
103
104#define XHCI_WAIT_CNR 100 /* in 1ms */
105#define XHCI_WAIT_HCRST 100 /* in 1ms */
106
107#define XHCI_USBSTS 0x04 /* XHCI status */
108#define XHCI_STS_HCH 0x00000001 /* RO - Host Controller Halted */
109#define XHCI_STS_HSE 0x00000004 /* RW - Host System Error */
110#define XHCI_STS_EINT 0x00000008 /* RW - Event Interrupt */
111#define XHCI_STS_PCD 0x00000010 /* RW - Port Change Detect */
112#define XHCI_STS_SSS 0x00000100 /* RO - Save State Status */
113#define XHCI_STS_RSS 0x00000200 /* RO - Restore State Status */
114#define XHCI_STS_SRE 0x00000400 /* RW - Save/Restore Error */
115#define XHCI_STS_CNR 0x00000800 /* RO - Controller Not Ready */
116#define XHCI_STS_HCE 0x00001000 /* RO - Host Controller Error */
117
118#define XHCI_PAGESIZE 0x08 /* XHCI page size mask */
119#define XHCI_PAGESIZE_4K 0x00000001 /* 4K Page Size */
120#define XHCI_PAGESIZE_8K 0x00000002 /* 8K Page Size */
121#define XHCI_PAGESIZE_16K 0x00000004 /* 16K Page Size */
122#define XHCI_PAGESIZE_32K 0x00000008 /* 32K Page Size */
123#define XHCI_PAGESIZE_64K 0x00000010 /* 64K Page Size */
124
125#define XHCI_DNCTRL 0x14 /* XHCI device notification control */
126#define XHCI_DNCTRL_MASK(n) (1U << (n))
127
128#define XHCI_CRCR 0x18 /* XHCI command ring control */
129#define XHCI_CRCR_LO_RCS 0x00000001 /* RW - consumer cycle state */
130#define XHCI_CRCR_LO_CS 0x00000002 /* RW - command stop */
131#define XHCI_CRCR_LO_CA 0x00000004 /* RW - command abort */
132#define XHCI_CRCR_LO_CRR 0x00000008 /* RW - command ring running */
133#define XHCI_CRCR_LO_MASK 0x0000000F
134
135#define XHCI_CRCR_HI 0x1C /* XHCI command ring control */
136#define XHCI_DCBAAP 0x30 /* XHCI dev context BA pointer */
137#define XHCI_DCBAAP_HI 0x34 /* XHCI dev context BA pointer */
138#define XHCI_CONFIG 0x38
139#define XHCI_CONFIG_SLOTS_MASK 0x000000FF /* RW - number of device slots enabled */
140
141/* XHCI port status registers */
142#define XHCI_PORTSC(n) (0x3F0 + (0x10 * (n))) /* XHCI port status */
143#define XHCI_PS_CCS 0x00000001 /* RO - current connect status */
144#define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */
145#define XHCI_PS_OCA 0x00000008 /* RO - over current active */
146#define XHCI_PS_PR 0x00000010 /* RW - port reset */
147#define XHCI_PS_PLS_GET(x) (((x) >> 5) & 0xF) /* RW - port link state */
148#define XHCI_PS_PLS_SET(x) (((x) & 0xF) << 5) /* RW - port link state */
149#define XHCI_PS_PP 0x00000200 /* RW - port power */
150#define XHCI_PS_SPEED_GET(x) (((x) >> 10) & 0xF) /* RO - port speed */
151#define XHCI_PS_SPEED_FS 1
152#define XHCI_PS_SPEED_LS 2
153#define XHCI_PS_SPEED_HS 3
154#define XHCI_PS_SPEED_SS 4
155#define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */
156#define XHCI_PS_PIC_SET(x) (((x) & 0x3) << 14) /* RW - port indicator */
157#define XHCI_PS_LWS 0x00010000 /* RW - port link state write strobe */
158#define XHCI_PS_CSC 0x00020000 /* RW - connect status change */
159#define XHCI_PS_PEC 0x00040000 /* RW - port enable/disable change */
160#define XHCI_PS_WRC 0x00080000 /* RW - warm port reset change */
161#define XHCI_PS_OCC 0x00100000 /* RW - over-current change */
162#define XHCI_PS_PRC 0x00200000 /* RW - port reset change */
163#define XHCI_PS_PLC 0x00400000 /* RW - port link state change */
164#define XHCI_PS_CEC 0x00800000 /* RW - config error change */
165#define XHCI_PS_CAS 0x01000000 /* RO - cold attach status */
166#define XHCI_PS_WCE 0x02000000 /* RW - wake on connect enable */
167#define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */
168#define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable */
169#define XHCI_PS_DR 0x40000000 /* RO - device removable */
170#define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */
171#define XHCI_PS_CLEAR 0x80FF01FFU /* command bits */
172
173#define XHCI_PORTPMSC(n) (0x3F4 + (0x10 * (n))) /* XHCI status and control */
174#define XHCI_PM3_U1TO_GET(x) (((x) >> 0) & 0xFF) /* RW - U1 timeout */
175#define XHCI_PM3_U1TO_SET(x) (((x) & 0xFF) << 0) /* RW - U1 timeout */
176#define XHCI_PM3_U2TO_GET(x) (((x) >> 8) & 0xFF) /* RW - U2 timeout */
177#define XHCI_PM3_U2TO_SET(x) (((x) & 0xFF) << 8) /* RW - U2 timeout */
178#define XHCI_PM3_FLA 0x00010000 /* RW - Force Link PM Accept */
179#define XHCI_PM2_L1S_GET(x) (((x) >> 0) & 0x7) /* RO - L1 status */
180#define XHCI_PM2_RWE 0x00000008 /* RW - remote wakup enable */
181#define XHCI_PM2_HIRD_GET(x) (((x) >> 4) & 0xF) /* RW - host initiated resume duration */
182#define XHCI_PM2_HIRD_SET(x) (((x) & 0xF) << 4) /* RW - host initiated resume duration */
183#define XHCI_PM2_L1SLOT_GET(x) (((x) >> 8) & 0xFF) /* RW - L1 device slot */
184#define XHCI_PM2_L1SLOT_SET(x) (((x) & 0xFF) << 8) /* RW - L1 device slot */
185#define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */
186
187#define XHCI_PORTLI(n) (0x3F8 + (0x10 * (n))) /* XHCI port link info */
188#define XHCI_PLI3_ERR_GET(x) (((x) >> 0) & 0xFFFF) /* RO - port link errors */
189
190#define XHCI_PORTRSV(n) (0x3FC + (0x10 * (n))) /* XHCI port reserved */
191
192/* XHCI runtime registers. Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers */
193#define XHCI_MFINDEX 0x0000 /* RO - microframe index */
194#define XHCI_MFINDEX_GET(x) ((x) & 0x3FFF)
195
196#define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) /* XHCI interrupt management */
197#define XHCI_IMAN_INTR_PEND 0x00000001 /* RW - interrupt pending */
198#define XHCI_IMAN_INTR_ENA 0x00000002 /* RW - interrupt enable */
199
200#define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) /* XHCI interrupt moderation */
201#define XHCI_IMOD_IVAL_GET(x) (((x) >> 0) & 0xFFFF) /* 250ns unit */
202#define XHCI_IMOD_IVAL_SET(x) (((x) & 0xFFFF) << 0) /* 250ns unit */
203#define XHCI_IMOD_ICNT_GET(x) (((x) >> 16) & 0xFFFF) /* 250ns unit */
204#define XHCI_IMOD_ICNT_SET(x) (((x) & 0xFFFF) << 16) /* 250ns unit */
205#define XHCI_IMOD_DEFAULT 0x000001F4U /* 8000 IRQ/second */
206#define XHCI_IMOD_DEFAULT_LP 0x000003E8U /* 4000 IRQ/sec for LynxPoint */
207
208#define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) /* XHCI event ring segment table size */
209#define XHCI_ERSTS_GET(x) ((x) & 0xFFFF)
210#define XHCI_ERSTS_SET(x) ((x) & 0xFFFF)
211
212#define XHCI_ERSTBA(n) (0x0030 + (0x20 * (n))) /* XHCI event ring segment table BA */
213#define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) /* XHCI event ring segment table BA */
214
215#define XHCI_ERDP(n) (0x0038 + (0x20 * (n))) /* XHCI event ring dequeue pointer */
216#define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) /* XHCI event ring dequeue pointer */
217#define XHCI_ERDP_LO_SINDEX(x) ((x) & 0x7) /* RO - dequeue segment index */
218#define XHCI_ERDP_LO_BUSY 0x00000008 /* RW - event handler busy */
219
220/* XHCI doorbell registers. Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers */
221#define XHCI_DOORBELL(n) (0x0000 + (4 * (n)))
222#define XHCI_DB_TARGET_GET(x) ((x) & 0xFF) /* RW - doorbell target */
223#define XHCI_DB_TARGET_SET(x) ((x) & 0xFF) /* RW - doorbell target */
224#define XHCI_DB_SID_GET(x) (((x) >> 16) & 0xFFFF) /* RW - doorbell stream ID */
225#define XHCI_DB_SID_SET(x) (((x) & 0xFFFF) << 16) /* RW - doorbell stream ID */
226
227/* XHCI legacy support */
228#define XHCI_XECP_ID(x) ((x) & 0xFF)
229#define XHCI_XECP_NEXT(x) (((x) >> 8) & 0xFF)
230#define XHCI_XECP_BIOS_SEM 0x0002
231#define XHCI_XECP_OS_SEM 0x0003
232
233/* XHCI extended capability ID's */
234#define XHCI_ID_USB_LEGACY 0x0001 /* USB Legacy Support */
235#define XHCI_XECP_USBLEGSUP 0x0000 /* Legacy Support Capability Reg */
236#define XHCI_XECP_USBLEGCTLSTS 0x0004 /* Legacy Support Ctrl & Status Reg */
237#define XHCI_ID_PROTOCOLS 0x0002 /* Supported Protocol */
238#define XHCI_ID_POWER_MGMT 0x0003 /* Extended Power Management */
239#define XHCI_ID_VIRTUALIZATION 0x0004 /* I/O Virtualization */
240#define XHCI_ID_MSG_IRQ 0x0005 /* Message Interrupt */
241#define XHCI_ID_USB_LOCAL_MEM 0x0006 /* Local Memory */
242#define XHCI_ID_USB_DEBUG 0x000A /* USB Debug Capability */
243#define XHCI_ID_XMSG_IRQ 0x0011 /* Extended Message Interrupt */
244
245#define XHCI_PAGE_SIZE(sc) ((sc)->sc_pgsz)
246
247/* Chapter 6, Table 49 */
248#define XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN 64
249#define XHCI_DEVICE_CONTEXT_ALIGN 64
250#define XHCI_INPUT_CONTROL_CONTEXT_ALIGN 64
251#define XHCI_SLOT_CONTEXT_ALIGN 32
252#define XHCI_ENDPOINT_CONTEXT_ALIGN 32
253#define XHCI_STREAM_CONTEXT_ALIGN 16
254#define XHCI_STREAM_ARRAY_ALIGN 16
255#define XHCI_TRANSFER_RING_SEGMENTS_ALIGN 16
256#define XHCI_COMMAND_RING_SEGMENTS_ALIGN 64
257#define XHCI_EVENT_RING_SEGMENTS_ALIGN 64
258#define XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN 64
259#define XHCI_SCRATCHPAD_BUFFER_ARRAY_ALIGN 64
260#define XHCI_SCRATCHPAD_BUFFERS_ALIGN XHCI_PAGE_SIZE
261
262#define XHCI_ERSTE_ALIGN 16
263#define XHCI_TRB_ALIGN 16
264
265struct xhci_trb {
266 uint64_t trb_0;
267 uint32_t trb_2;
268#define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF)
269#define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24)
270#define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F)
271#define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17)
272#define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF)
273#define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF)
274#define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF)
275#define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF)
276#define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF)
277#define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22)
278#define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF)
279#define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16)
280 uint32_t trb_3;
281#define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F)
282#define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10)
283#define XHCI_TRB_3_CYCLE_BIT (1U << 0)
284#define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */
285#define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */
286#define XHCI_TRB_3_ISP_BIT (1U << 2)
287#define XHCI_TRB_3_NSNOOP_BIT (1U << 3)
288#define XHCI_TRB_3_CHAIN_BIT (1U << 4)
289#define XHCI_TRB_3_IOC_BIT (1U << 5)
290#define XHCI_TRB_3_IDT_BIT (1U << 6)
291#define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3)
292#define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7)
293#define XHCI_TRB_3_BEI_BIT (1U << 9)
294#define XHCI_TRB_3_DCEP_BIT (1U << 9)
295#define XHCI_TRB_3_PRSV_BIT (1U << 9)
296#define XHCI_TRB_3_BSR_BIT (1U << 9)
297#define XHCI_TRB_3_TRT_MASK (3U << 16)
298#define XHCI_TRB_3_TRT_NONE (0U << 16)
299#define XHCI_TRB_3_TRT_OUT (2U << 16)
300#define XHCI_TRB_3_TRT_IN (3U << 16)
301#define XHCI_TRB_3_DIR_IN (1U << 16)
302#define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF)
303#define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16)
304#define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F)
305#define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16)
306#define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF)
307#define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20)
308#define XHCI_TRB_3_ISO_SIA_BIT (1U << 31)
309#define XHCI_TRB_3_SUSP_EP_BIT (1U << 23)
310#define XHCI_TRB_3_VFID_GET(x) (((x) >> 16) & 0xFF)
311#define XHCI_TRB_3_VFID_SET(x) (((x) & 0xFF) << 16)
312#define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF)
313#define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24)
314
315 /* Commands */
316#define XHCI_TRB_TYPE_RESERVED 0x00
317#define XHCI_TRB_TYPE_NORMAL 0x01
318#define XHCI_TRB_TYPE_SETUP_STAGE 0x02
319#define XHCI_TRB_TYPE_DATA_STAGE 0x03
320#define XHCI_TRB_TYPE_STATUS_STAGE 0x04
321#define XHCI_TRB_TYPE_ISOCH 0x05
322#define XHCI_TRB_TYPE_LINK 0x06
323#define XHCI_TRB_TYPE_EVENT_DATA 0x07
324#define XHCI_TRB_TYPE_NOOP 0x08
325#define XHCI_TRB_TYPE_ENABLE_SLOT 0x09
326#define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A
327#define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B
328#define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C
329#define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D
330#define XHCI_TRB_TYPE_RESET_EP 0x0E
331#define XHCI_TRB_TYPE_STOP_EP 0x0F
332#define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10
333#define XHCI_TRB_TYPE_RESET_DEVICE 0x11
334#define XHCI_TRB_TYPE_FORCE_EVENT 0x12
335#define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13
336#define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14
337#define XHCI_TRB_TYPE_GET_PORT_BW 0x15
338#define XHCI_TRB_TYPE_FORCE_HEADER 0x16
339#define XHCI_TRB_TYPE_NOOP_CMD 0x17
340
341 /* Events */
342#define XHCI_TRB_EVENT_TRANSFER 0x20
343#define XHCI_TRB_EVENT_CMD_COMPLETE 0x21
344#define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22
345#define XHCI_TRB_EVENT_BW_REQUEST 0x23
346#define XHCI_TRB_EVENT_DOORBELL 0x24
347#define XHCI_TRB_EVENT_HOST_CTRL 0x25
348#define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26
349#define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27
350
351 /* Error codes */
352#define XHCI_TRB_ERROR_INVALID 0x00
353#define XHCI_TRB_ERROR_SUCCESS 0x01
354#define XHCI_TRB_ERROR_DATA_BUF 0x02
355#define XHCI_TRB_ERROR_BABBLE 0x03
356#define XHCI_TRB_ERROR_XACT 0x04
357#define XHCI_TRB_ERROR_TRB 0x05
358#define XHCI_TRB_ERROR_STALL 0x06
359#define XHCI_TRB_ERROR_RESOURCE 0x07
360#define XHCI_TRB_ERROR_BANDWIDTH 0x08
361#define XHCI_TRB_ERROR_NO_SLOTS 0x09
362#define XHCI_TRB_ERROR_STREAM_TYPE 0x0A
363#define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B
364#define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C
365#define XHCI_TRB_ERROR_SHORT_PKT 0x0D
366#define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E
367#define XHCI_TRB_ERROR_RING_OVERRUN 0x0F
368#define XHCI_TRB_ERROR_VF_RING_FULL 0x10
369#define XHCI_TRB_ERROR_PARAMETER 0x11
370#define XHCI_TRB_ERROR_BW_OVERRUN 0x12
371#define XHCI_TRB_ERROR_CONTEXT_STATE 0x13
372#define XHCI_TRB_ERROR_NO_PING_RESP 0x14
373#define XHCI_TRB_ERROR_EV_RING_FULL 0x15
374#define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16
375#define XHCI_TRB_ERROR_MISSED_SERVICE 0x17
376#define XHCI_TRB_ERROR_CMD_RING_STOP 0x18
377#define XHCI_TRB_ERROR_CMD_ABORTED 0x19
378#define XHCI_TRB_ERROR_STOPPED 0x1A
379#define XHCI_TRB_ERROR_LENGTH 0x1B
380#define XHCI_TRB_ERROR_STOPPED_SHORT 0x1C
381#define XHCI_TRB_ERROR_BAD_MELAT 0x1D
382#define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F
383#define XHCI_TRB_ERROR_EVENT_LOST 0x20
384#define XHCI_TRB_ERROR_UNDEFINED 0x21
385#define XHCI_TRB_ERROR_INVALID_SID 0x22
386#define XHCI_TRB_ERROR_SEC_BW 0x23
387#define XHCI_TRB_ERROR_SPLIT_XACT 0x24
388} __packed __aligned(XHCI_TRB_ALIGN);
389#define XHCI_TRB_SIZE sizeof(struct xhci_trb)
390
391#define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF)
392#define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF)
393#define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20)
394#define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF)
395#define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25)
396#define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1)
397#define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26)
398#define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1)
399#define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27)
400#define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F)
401
402#define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF)
403#define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF)
404#define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16)
405#define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF)
406#define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24)
407#define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF)
408
409#define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF)
410#define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF)
411#define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8)
412#define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF)
413#define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16)
414#define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3)
415#define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22)
416#define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF)
417
418#define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF)
419#define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF)
420#define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27)
421#define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F)
422#define XHCI_SLOTSTATE_DISABLED 0 /* disabled or enabled */
423#define XHCI_SLOTSTATE_ENABLED 0
424#define XHCI_SLOTSTATE_DEFAULT 1
425#define XHCI_SLOTSTATE_ADDRESSED 2
426#define XHCI_SLOTSTATE_CONFIGURED 3
427
428
429#define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7)
430#define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7)
431#define XHCI_EPSTATE_DISABLED 0
432#define XHCI_EPSTATE_RUNNING 1
433#define XHCI_EPSTATE_HALTED 2
434#define XHCI_EPSTATE_STOPPED 3
435#define XHCI_EPSTATE_ERROR 4
436#define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8)
437#define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3)
438#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10)
439#define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F)
440#define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15)
441#define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1)
442#define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16)
443#define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF)
444#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK __BITS(31,24)
445#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK)
446#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK)
447
448#define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1)
449#define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3)
450#define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3)
451#define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7)
452#define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7)
453#define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1)
454#define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8)
455#define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF)
456#define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16)
457#define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF)
458
459#define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1)
460#define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1)
461#define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U
462
463#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF)
464#define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF)
465#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16)
466#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF)
467
468
469#define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU
470
471#define XHCI_INCTX_0_DROP_MASK(n) (1U << (n))
472
473#define XHCI_INCTX_1_ADD_MASK(n) (1U << (n))
474
475
476struct xhci_erste {
477 uint64_t erste_0; /* 63:6 base */
478 uint32_t erste_2; /* 15:0 trb count (16 to 4096) */
479 uint32_t erste_3; /* RsvdZ */
480} __packed __aligned(XHCI_ERSTE_ALIGN);
481#define XHCI_ERSTE_SIZE sizeof(struct xhci_erste)
482
483#endif /* _DEV_USB_XHCIREG_H_ */
484