1/* $NetBSD: if_liireg.h,v 1.2 2008/04/29 06:53:03 martin Exp $ */
2
3/*
4 * Copyright (c) 2008 The NetBSD Foundation.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * PCI configuration space seems to be mapped in the first 0x100 bytes of
31 * the register area.
32 */
33
34/* SPI Flash Control register */
35#define ATL2_SFC 0x0200
36#define SFC_STS_NON_RDY 0x00000001
37#define SFC_STS_WEN 0x00000002
38#define SFC_STS_WPEN 0x00000080
39#define SFC_DEV_STS_MASK 0x000000ff
40#define SFC_DEV_STS_SHIFT 0
41#define SFC_INS_MASK 0x07
42#define SFC_INS_SHIFT 8
43#define SFC_START 0x00000800
44#define SFC_EN_VPD 0x00002000
45#define SFC_LDSTART 0x00008000
46#define SFC_CS_HI_MASK 0x03
47#define SFC_CS_HI_SHIFT 16
48#define SFC_CS_HOLD_MASK 0x03
49#define SFC_CS_HOLD_SHIFT 18
50#define SFC_CLK_LO_MASK 0x03
51#define SFC_CLK_LO_SHIFT 20
52#define SFC_CLK_HI_MASK 0x03
53#define SFC_CLK_HI_SHIFT 22
54#define SFC_CS_SETUP_MASK 0x03
55#define SFC_CS_SETUP_SHIFT 24
56#define SFC_EROMPGSZ_MASK 0x03
57#define SFC_EROMPGSZ_SHIFT 26
58#define SFC_WAIT_READY 0x10000000
59
60/* SPI Flash Address register */
61#define ATL2_SF_ADDR 0x0204
62
63/* SPI Flash Data register */
64#define ATL2_SF_DATA 0x0208
65
66/* SPI Flash Configuration register */
67#define ATL2_SFCF 0x020c
68#define SFCF_LD_ADDR_MASK 0x00ffffff
69#define SFCF_LD_ADDR_SHIFT 0
70#define SFCF_VPD_ADDR_MASK 0x03
71#define SFCF_VPD_ADDR_SHIFT 24
72#define SFCF_LD_EXISTS 0x04000000
73
74/* SPI Flash op codes programmation registers */
75#define ATL2_SFOP_PROGRAM 0x0210
76#define ATL2_SFOP_SC_ERASE 0x0211
77#define ATL2_SFOP_CHIP_ERASE 0x0212
78#define ATL2_SFOP_RDID 0x0213
79#define ATL2_SFOP_WREN 0x0214
80#define ATL2_SFOP_RDSR 0x0215
81#define ATL2_SFOP_WRSR 0x0216
82#define ATL2_SFOP_READ 0x0217
83
84/* TWSI Control register, whatever that is */
85#define ATL2_TWSIC 0x0218
86#define TWSIC_LD_OFFSET_MASK 0x000000ff
87#define TWSIC_LD_OFFSET_SHIFT 0
88#define TWSIC_LD_SLV_ADDR_MASK 0x07
89#define TWSIC_LD_SLV_ADDR_SHIFT 8
90#define TWSIC_SW_LDSTART 0x00000800
91#define TWSIC_HW_LDSTART 0x00001000
92#define TWSIC_SMB_SLV_ADDR_MASK 0x7F
93#define TWSIC_SMB_SLV_ADDR_SHIFT 15
94#define TWSIC_LD_EXIST 0x00400000
95#define TWSIC_READ_FREQ_SEL_MASK 0x03
96#define TWSIC_READ_FREQ_SEL_SHIFT 23
97#define TWSIC_FREQ_SEL_100K 0
98#define TWSIC_FREQ_SEL_200K 1
99#define TWSIC_FREQ_SEL_300K 2
100#define TWSIC_FREQ_SEL_400K 3
101#define TWSIC_WRITE_FREQ_SEL_MASK 0x03
102#define TWSIC_WRITE_FREQ_SEL_SHIFT 24
103
104/* PCI-Express Device Misc. Control register? (size unknown) */
105#define ATL2_PCEDMC 0x021c
106#define PCEDMC_RETRY_BUFDIS 0x01
107#define PCEDMC_EXT_PIPE 0x02
108#define PCEDMC_SPIROM_EXISTS 0x04
109#define PCEDMC_SERDES_ENDIAN 0x08
110#define PCEDMC_SERDES_SEL_DIN 0x10
111
112/* PCI-Express PHY Miscellaneous register (size unknown) */
113#define ATL2_PCEPM 0x1000
114#define PCEPM_FORCE_RCV_DET 0x04
115
116/* PCI-Express DLL TX Control register */
117#define ATL2_PCEDTXC 0x1104
118#define PCEDTX_SEL_NOR_CLK 0x00000400
119#define PCEDTX_DEF 0x00000568
120
121/* PCI-Express-related register (LTSSM test mode) */
122#define ATL2_PCELTM 0x12fc
123#define PCELTM_DEF 0x00006500
124
125/* Selene Master Control register */
126#define ATL2_SMC 0x1400
127#define SMC_SOFT_RST 0x00000001
128#define SMC_MTIMER_EN 0x00000002
129#define SMC_ITIMER_EN 0x00000004
130#define SMC_MANUAL_INT 0x00000008
131#define SMC_REV_NUM_MASK 0xff
132#define SMC_REV_NUM_SHIFT 16
133#define SMC_DEV_ID_MASK 0xff
134#define SMC_DEV_ID_SHIFT 24
135
136/* Timer Initial Value register */
137#define ATL2_TIV 0x1404
138
139/* IRQ Moderator Timer Initial Value register */
140#define ATL2_IMTIV 0x1408
141
142/* PHY Control register */
143#define ATL2_PHYC 0x140c
144#define PHYC_ENABLE 0x0001
145
146/* IRQ Anti-Lost Timer Initial Value register
147 --> Time allowed for software to clear the interrupt */
148#define ATL2_IALTIV 0x140e
149
150/* Block Idle Status register
151 --> Bit set if matching state machine is not idle */
152#define ATL2_BIS 0x1410
153#define BIS_RXMAC 0x00000001
154#define BIS_TXMAC 0x00000002
155#define BIS_DMAR 0x00000004
156#define BIS_DMAW 0x00000008
157
158/* MDIO Control register */
159#define ATL2_MDIOC 0x1414
160#define MDIOC_DATA_MASK 0x0000ffff
161#define MDIOC_DATA_SHIFT 0
162#define MDIOC_REG_MASK 0x1f
163#define MDIOC_REG_SHIFT 16
164#define MDIOC_WRITE 0x00000000
165#define MDIOC_READ 0x00200000
166#define MDIOC_SUP_PREAMBLE 0x00400000
167#define MDIOC_START 0x00800000
168#define MDIOC_CLK_SEL_MASK 0x07
169#define MDIOC_CLK_SEL_SHIFT 24
170#define MDIOC_CLK_25_4 0
171#define MDIOC_CLK_25_6 2
172#define MDIOC_CLK_25_8 3
173#define MDIOC_CLK_25_10 4
174#define MDIOC_CLK_25_14 5
175#define MDIOC_CLK_25_20 6
176#define MDIOC_CLK_25_28 7
177#define MDIOC_BUSY 0x08000000
178/* Time to wait for MDIO, waiting for 2us in-between */
179#define MDIO_WAIT_TIMES 10
180
181/* SerDes Lock Detect Control and Status register */
182#define ATL2_SERDES 0x1424
183#define SERDES_LOCK_DETECT 0x01
184#define SERDES_LOCK_DETECT_EN 0x02
185
186/* MAC Control register */
187#define ATL2_MACC 0x1480
188#define MACC_TX_EN 0x00000001
189#define MACC_RX_EN 0x00000002
190#define MACC_TX_FLOW_EN 0x00000004
191#define MACC_RX_FLOW_EN 0x00000008
192#define MACC_LOOPBACK 0x00000010
193#define MACC_FDX 0x00000020
194#define MACC_ADD_CRC 0x00000040
195#define MACC_PAD 0x00000080
196#define MACC_PREAMBLE_LEN_MASK 0x0f
197#define MACC_PREAMBLE_LEN_SHIFT 10
198#define MACC_STRIP_VLAN 0x00004000
199#define MACC_PROMISC_EN 0x00008000
200#define MACC_DBG_TX_BKPRESSURE 0x00100000
201#define MACC_ALLMULTI_EN 0x02000000
202#define MACC_BCAST_EN 0x04000000
203#define MACC_MACLP_CLK_PHY 0x08000000
204#define MACC_HDX_LEFT_BUF_MASK 0x0f
205#define MACC_HDX_LEFT_BUF_SHIFT 28
206
207/* MAC IPG/IFG Control register */
208#define ATL2_MIPFG 0x1484
209#define MIPFG_IPGT_MASK 0x0000007f
210#define MIPFG_IPGT_SHIFT 0
211#define MIPFG_MIFG_MASK 0xff
212#define MIPFG_MIFG_SHIFT 8
213#define MIPFG_IPGR1_MASK 0x7f
214#define MIPFG_IPGR1_SHIFT 16
215#define MIPFG_IPGR2_MASK 0x7f
216#define MIPFG_IPGR2_SHIFT 24
217
218/* MAC Address registers */
219#define ATL2_MAC_ADDR_0 0x1488
220#define ATL2_MAC_ADDR_1 0x148c
221
222/* Multicast Hash Table register */
223#define ATL2_MHT 0x1490
224
225/* MAC Half-Duplex Control register */
226#define ATL2_MHDC 0x1498
227#define MHDC_LCOL_MASK 0x000003ff
228#define MHDC_LCOL_SHIFT 0
229#define MHDC_RETRY_MASK 0x0f
230#define MHDC_RETRY_SHIFT 12
231#define MHDC_EXC_DEF_EN 0x00010000
232#define MHDC_NO_BACK_C 0x00020000
233#define MHDC_NO_BACK_P 0x00040000
234#define MHDC_ABEDE 0x00080000
235#define MHDC_ABEBT_MASK 0x0f
236#define MHDC_ABEBT_SHIFT 20
237#define MHDC_JAMIPG_MASK 0x0f
238#define MHDC_JAMIPG_SHIFT 24
239
240/* MTU Control register */
241#define ATL2_MTU 0x149c
242
243/* WOL Control register */
244#define ATL2_WOLC
245#define WOLC_PATTERN_EN 0x00000001
246#define WOLC_PATTERN_PME_EN 0x00000002
247#define WOLC_MAGIC_EN 0x00000004
248#define WOLC_MAGIC_PME_EN 0x00000008
249#define WOLC_LINK_CHG_EN 0x00000010
250#define WOLC_LINK_CHG_PME_EN 0x00000020
251#define WOLC_PATTERN_ST 0x00000100
252#define WOLC_MAGIC_ST 0x00000200
253#define WOLC_LINK_CHG_ST 0x00000400
254#define WOLC_PT0_EN 0x00010000
255#define WOLC_PT1_EN 0x00020000
256#define WOLC_PT2_EN 0x00040000
257#define WOLC_PT3_EN 0x00080000
258#define WOLC_PT4_EN 0x00100000
259#define WOLC_PT0_MATCH 0x01000000
260#define WOLC_PT1_MATCH 0x02000000
261#define WOLC_PT2_MATCH 0x04000000
262#define WOLC_PT3_MATCH 0x08000000
263#define WOLC_PT4_MATCH 0x10000000
264
265/* Internal SRAM Partition register */
266#define ATL2_SRAM_TXRAM_END 0x1500
267#define ATL2_SRAM_RXRAM_END 0x1502
268
269/* Descriptor Control registers */
270#define ATL2_DESC_BASE_ADDR_HI 0x1540
271#define ATL2_TXD_BASE_ADDR_LO 0x1544
272#define ATL2_TXD_BUFFER_SIZE 0x1548
273#define ATL2_TXS_BASE_ADDR_LO 0x154c
274#define ATL2_TXS_NUM_ENTRIES 0x1550
275#define ATL2_RXD_BASE_ADDR_LO 0x1554
276#define ATL2_RXD_NUM_ENTRIES 0x1558
277
278/* DMAR Control register */
279#define ATL2_DMAR 0x1580
280#define DMAR_EN 0x01
281
282/* TX Cur-Through Control register */
283#define ATL2_TX_CUT_THRESH 0x1590
284
285/* DMAW Control register */
286#define ATL2_DMAW 0x15a0
287#define DMAW_EN 0x01
288
289/* Flow Control registers */
290#define ATL2_PAUSE_ON_TH 0x15a8
291#define ATL2_PAUSE_OFF_TH 0x15aa
292
293/* Mailbox registers */
294#define ATL2_MB_TXD_WR_IDX 0x15f0
295#define ATL2_MB_RXD_RD_IDX 0x15f4
296
297/* Interrupt Status register */
298#define ATL2_ISR 0x1600
299#define ISR_TIMER 0x00000001
300#define ISR_MANUAL 0x00000002
301#define ISR_RXF_OV 0x00000004
302#define ISR_TXF_UR 0x00000008
303#define ISR_TXS_OV 0x00000010
304#define ISR_RXS_OV 0x00000020
305#define ISR_LINK_CHG 0x00000040
306#define ISR_HOST_TXD_UR 0x00000080
307#define ISR_HOST_RXD_OV 0x00000100
308#define ISR_DMAR_TO_RST 0x00000200
309#define ISR_DMAW_TO_RST 0x00000400
310#define ISR_PHY 0x00000800
311#define ISR_TS_UPDATE 0x00010000
312#define ISR_RS_UPDATE 0x00020000
313#define ISR_TX_EARLY 0x00040000
314#define ISR_UR_DETECTED 0x01000000
315#define ISR_FERR_DETECTED 0x02000000
316#define ISR_NFERR_DETECTED 0x04000000
317#define ISR_CERR_DETECTED 0x08000000
318#define ISR_PHY_LINKDOWN 0x10000000
319#define ISR_DIS_INT 0x80000000
320
321#define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | \
322 ISR_HOST_TXD_UR | ISR_TS_UPDATE | \
323 ISR_TX_EARLY)
324#define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | \
325 ISR_HOST_RXD_OV | ISR_RS_UPDATE)
326
327/* Interrupt Mask register */
328#define ATL2_IMR 0x1604
329#define IMR_NORMAL_MASK (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | \
330 ISR_PHY | ISR_PHY_LINKDOWN | \
331 ISR_TS_UPDATE | ISR_RS_UPDATE | \
332 ISR_MANUAL)
333
334/* MAC RX Statistics registers */
335#define ATL2_STS_RX_PAUSE 0x1700
336#define ATL2_STS_RXD_OV 0x1704
337#define ATL2_STS_RXS_OV 0x1708
338#define ATL2_STS_RX_FILTER 0x170c
339
340struct tx_pkt_header {
341 uint16_t txph_size;
342#define ATL2_TXH_ADD_VLAN_TAG 0x8000
343 uint16_t txph_vlan;
344} __packed;
345
346struct tx_pkt_status {
347 uint16_t txps_size;
348 uint16_t txps_flags :15;
349#define ATL2_TXF_SUCCESS 0x0001
350#define ATL2_TXF_BCAST 0x0002
351#define ATL2_TXF_MCAST 0x0004
352#define ATL2_TXF_PAUSE 0x0008
353#define ATL2_TXF_CTRL 0x0010
354#define ATL2_TXF_DEFER 0x0020
355#define ATL2_TXF_EXC_DEFER 0x0040
356#define ATL2_TXF_SINGLE_COL 0x0080
357#define ATL2_TXF_MULTI_COL 0x0100
358#define ATL2_TXF_LATE_COL 0x0200
359#define ATL2_TXF_ABORT_COL 0x0400
360#define ATL2_TXF_UNDERRUN 0x0800
361 uint16_t txps_update:1;
362} __packed;
363
364struct rx_pkt {
365 uint16_t rxp_size;
366 uint16_t rxp_flags :15;
367#define ATL2_RXF_SUCCESS 0x0001
368#define ATL2_RXF_BCAST 0x0002
369#define ATL2_RXF_MCAST 0x0004
370#define ATL2_RXF_PAUSE 0x0008
371#define ATL2_RXF_CTRL 0x0010
372#define ATL2_RXF_CRC 0x0020
373#define ATL2_RXF_CODE 0x0040
374#define ATL2_RXF_RUNT 0x0080
375#define ATL2_RXF_FRAG 0x0100
376#define ATL2_RXF_TRUNC 0x0200
377#define ATL2_RXF_ALIGN 0x0400
378#define ATL2_RXF_VLAN 0x0800
379 uint16_t rxp_update:1;
380 uint16_t rxp_vlan;
381 uint16_t __pad;
382 uint8_t rxp_data[1528];
383} __packed;
384