1 | /* $NetBSD: nouveau_engine_fifo_nv17.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_fifo_nv17.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $" ); |
29 | |
30 | #include <core/os.h> |
31 | #include <core/class.h> |
32 | #include <core/engctx.h> |
33 | #include <core/ramht.h> |
34 | |
35 | #include <subdev/instmem.h> |
36 | #include <subdev/instmem/nv04.h> |
37 | #include <subdev/fb.h> |
38 | |
39 | #include <engine/fifo.h> |
40 | |
41 | #include "nv04.h" |
42 | |
43 | static struct ramfc_desc |
44 | nv17_ramfc[] = { |
45 | { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, |
46 | { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, |
47 | { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, |
48 | { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, |
49 | { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, |
50 | { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE }, |
51 | { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, |
52 | { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE }, |
53 | { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 }, |
54 | { 32, 0, 0x20, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE }, |
55 | { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP }, |
56 | { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT }, |
57 | { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_SEMAPHORE }, |
58 | { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE }, |
59 | {} |
60 | }; |
61 | |
62 | /******************************************************************************* |
63 | * FIFO channel objects |
64 | ******************************************************************************/ |
65 | |
66 | static int |
67 | nv17_fifo_chan_ctor(struct nouveau_object *parent, |
68 | struct nouveau_object *engine, |
69 | struct nouveau_oclass *oclass, void *data, u32 size, |
70 | struct nouveau_object **pobject) |
71 | { |
72 | struct nv04_fifo_priv *priv = (void *)engine; |
73 | struct nv04_fifo_chan *chan; |
74 | struct nv03_channel_dma_class *args = data; |
75 | int ret; |
76 | |
77 | if (size < sizeof(*args)) |
78 | return -EINVAL; |
79 | |
80 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, |
81 | 0x10000, args->pushbuf, |
82 | (1ULL << NVDEV_ENGINE_DMAOBJ) | |
83 | (1ULL << NVDEV_ENGINE_SW) | |
84 | (1ULL << NVDEV_ENGINE_GR) | |
85 | (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */ |
86 | &chan); |
87 | *pobject = nv_object(chan); |
88 | if (ret) |
89 | return ret; |
90 | |
91 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; |
92 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; |
93 | nv_parent(chan)->context_attach = nv04_fifo_context_attach; |
94 | chan->ramfc = chan->base.chid * 64; |
95 | |
96 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); |
97 | nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset); |
98 | nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); |
99 | nv_wo32(priv->ramfc, chan->ramfc + 0x14, |
100 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | |
101 | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | |
102 | #ifdef __BIG_ENDIAN |
103 | NV_PFIFO_CACHE1_BIG_ENDIAN | |
104 | #endif |
105 | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); |
106 | return 0; |
107 | } |
108 | |
109 | static struct nouveau_ofuncs |
110 | nv17_fifo_ofuncs = { |
111 | .ctor = nv17_fifo_chan_ctor, |
112 | .dtor = nv04_fifo_chan_dtor, |
113 | .init = nv04_fifo_chan_init, |
114 | .fini = nv04_fifo_chan_fini, |
115 | .rd32 = _nouveau_fifo_channel_rd32, |
116 | .wr32 = _nouveau_fifo_channel_wr32, |
117 | }; |
118 | |
119 | static struct nouveau_oclass |
120 | nv17_fifo_sclass[] = { |
121 | { NV17_CHANNEL_DMA_CLASS, &nv17_fifo_ofuncs }, |
122 | {} |
123 | }; |
124 | |
125 | /******************************************************************************* |
126 | * FIFO context - basically just the instmem reserved for the channel |
127 | ******************************************************************************/ |
128 | |
129 | static struct nouveau_oclass |
130 | nv17_fifo_cclass = { |
131 | .handle = NV_ENGCTX(FIFO, 0x17), |
132 | .ofuncs = &(struct nouveau_ofuncs) { |
133 | .ctor = nv04_fifo_context_ctor, |
134 | .dtor = _nouveau_fifo_context_dtor, |
135 | .init = _nouveau_fifo_context_init, |
136 | .fini = _nouveau_fifo_context_fini, |
137 | .rd32 = _nouveau_fifo_context_rd32, |
138 | .wr32 = _nouveau_fifo_context_wr32, |
139 | }, |
140 | }; |
141 | |
142 | /******************************************************************************* |
143 | * PFIFO engine |
144 | ******************************************************************************/ |
145 | |
146 | static int |
147 | nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
148 | struct nouveau_oclass *oclass, void *data, u32 size, |
149 | struct nouveau_object **pobject) |
150 | { |
151 | struct nv04_instmem_priv *imem = nv04_instmem(parent); |
152 | struct nv04_fifo_priv *priv; |
153 | int ret; |
154 | |
155 | ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv); |
156 | *pobject = nv_object(priv); |
157 | if (ret) |
158 | return ret; |
159 | |
160 | nouveau_ramht_ref(imem->ramht, &priv->ramht); |
161 | nouveau_gpuobj_ref(imem->ramro, &priv->ramro); |
162 | nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); |
163 | |
164 | nv_subdev(priv)->unit = 0x00000100; |
165 | nv_subdev(priv)->intr = nv04_fifo_intr; |
166 | nv_engine(priv)->cclass = &nv17_fifo_cclass; |
167 | nv_engine(priv)->sclass = nv17_fifo_sclass; |
168 | priv->base.pause = nv04_fifo_pause; |
169 | priv->base.start = nv04_fifo_start; |
170 | priv->ramfc_desc = nv17_ramfc; |
171 | return 0; |
172 | } |
173 | |
174 | static int |
175 | nv17_fifo_init(struct nouveau_object *object) |
176 | { |
177 | struct nv04_fifo_priv *priv = (void *)object; |
178 | int ret; |
179 | |
180 | ret = nouveau_fifo_init(&priv->base); |
181 | if (ret) |
182 | return ret; |
183 | |
184 | nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff); |
185 | nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); |
186 | |
187 | nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | |
188 | ((priv->ramht->bits - 9) << 16) | |
189 | (priv->ramht->base.addr >> 8)); |
190 | nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); |
191 | nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8 | 0x00010000); |
192 | |
193 | nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); |
194 | |
195 | nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff); |
196 | nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff); |
197 | |
198 | nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); |
199 | nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); |
200 | nv_wr32(priv, NV03_PFIFO_CACHES, 1); |
201 | return 0; |
202 | } |
203 | |
204 | struct nouveau_oclass * |
205 | nv17_fifo_oclass = &(struct nouveau_oclass) { |
206 | .handle = NV_ENGINE(FIFO, 0x17), |
207 | .ofuncs = &(struct nouveau_ofuncs) { |
208 | .ctor = nv17_fifo_ctor, |
209 | .dtor = nv04_fifo_dtor, |
210 | .init = nv17_fifo_init, |
211 | .fini = _nouveau_fifo_fini, |
212 | }, |
213 | }; |
214 | |