1 | /* $NetBSD: nouveau_subdev_bios_rammap.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2013 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_bios_rammap.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $" ); |
29 | |
30 | #include <subdev/bios.h> |
31 | #include <subdev/bios/bit.h> |
32 | #include <subdev/bios/ramcfg.h> |
33 | #include <subdev/bios/rammap.h> |
34 | |
35 | u32 |
36 | nvbios_rammapTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, |
37 | u8 *cnt, u8 *len, u8 *snr, u8 *ssz) |
38 | { |
39 | struct bit_entry bit_P; |
40 | u16 rammap = 0x0000; |
41 | |
42 | if (!bit_entry(bios, 'P', &bit_P)) { |
43 | if (bit_P.version == 2) |
44 | rammap = nv_ro16(bios, bit_P.offset + 4); |
45 | |
46 | if (rammap) { |
47 | *ver = nv_ro08(bios, rammap + 0); |
48 | switch (*ver) { |
49 | case 0x10: |
50 | case 0x11: |
51 | *hdr = nv_ro08(bios, rammap + 1); |
52 | *cnt = nv_ro08(bios, rammap + 5); |
53 | *len = nv_ro08(bios, rammap + 2); |
54 | *snr = nv_ro08(bios, rammap + 4); |
55 | *ssz = nv_ro08(bios, rammap + 3); |
56 | return rammap; |
57 | default: |
58 | break; |
59 | } |
60 | } |
61 | } |
62 | |
63 | return 0x0000; |
64 | } |
65 | |
66 | u32 |
67 | nvbios_rammapEe(struct nouveau_bios *bios, int idx, |
68 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len) |
69 | { |
70 | u8 snr, ssz; |
71 | u16 rammap = nvbios_rammapTe(bios, ver, hdr, cnt, len, &snr, &ssz); |
72 | if (rammap && idx < *cnt) { |
73 | rammap = rammap + *hdr + (idx * (*len + (snr * ssz))); |
74 | *hdr = *len; |
75 | *cnt = snr; |
76 | *len = ssz; |
77 | return rammap; |
78 | } |
79 | return 0x0000; |
80 | } |
81 | |
82 | u32 |
83 | nvbios_rammapEm(struct nouveau_bios *bios, u16 khz, |
84 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len) |
85 | { |
86 | int idx = 0; |
87 | u32 data; |
88 | while ((data = nvbios_rammapEe(bios, idx++, ver, hdr, cnt, len))) { |
89 | if (khz >= nv_ro16(bios, data + 0x00) && |
90 | khz <= nv_ro16(bios, data + 0x02)) |
91 | break; |
92 | } |
93 | return data; |
94 | } |
95 | |
96 | u32 |
97 | nvbios_rammapEp(struct nouveau_bios *bios, u16 khz, |
98 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, |
99 | struct nvbios_ramcfg *p) |
100 | { |
101 | u32 data = nvbios_rammapEm(bios, khz, ver, hdr, cnt, len); |
102 | memset(p, 0x00, sizeof(*p)); |
103 | switch (!!data * *ver) { |
104 | case 0x11: |
105 | p->rammap_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0; |
106 | p->rammap_11_08_0c = (nv_ro08(bios, data + 0x08) & 0x0c) >> 2; |
107 | p->rammap_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4; |
108 | p->rammap_11_11_0c = (nv_ro08(bios, data + 0x11) & 0x0c) >> 2; |
109 | break; |
110 | default: |
111 | data = 0; |
112 | break; |
113 | } |
114 | return data; |
115 | } |
116 | |
117 | u32 |
118 | nvbios_rammapSe(struct nouveau_bios *bios, u32 data, |
119 | u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, |
120 | u8 *ver, u8 *hdr) |
121 | { |
122 | if (idx < ecnt) { |
123 | data = data + ehdr + (idx * elen); |
124 | *ver = ever; |
125 | *hdr = elen; |
126 | return data; |
127 | } |
128 | return 0; |
129 | } |
130 | |
131 | u32 |
132 | nvbios_rammapSp(struct nouveau_bios *bios, u32 data, |
133 | u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, |
134 | u8 *ver, u8 *hdr, struct nvbios_ramcfg *p) |
135 | { |
136 | data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr); |
137 | switch (!!data * *ver) { |
138 | case 0x11: |
139 | p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0; |
140 | p->ramcfg_11_01_02 = (nv_ro08(bios, data + 0x01) & 0x02) >> 1; |
141 | p->ramcfg_11_01_04 = (nv_ro08(bios, data + 0x01) & 0x04) >> 2; |
142 | p->ramcfg_11_01_08 = (nv_ro08(bios, data + 0x01) & 0x08) >> 3; |
143 | p->ramcfg_11_01_10 = (nv_ro08(bios, data + 0x01) & 0x10) >> 4; |
144 | p->ramcfg_11_01_20 = (nv_ro08(bios, data + 0x01) & 0x20) >> 5; |
145 | p->ramcfg_11_01_40 = (nv_ro08(bios, data + 0x01) & 0x40) >> 6; |
146 | p->ramcfg_11_01_80 = (nv_ro08(bios, data + 0x01) & 0x80) >> 7; |
147 | p->ramcfg_11_02_03 = (nv_ro08(bios, data + 0x02) & 0x03) >> 0; |
148 | p->ramcfg_11_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2; |
149 | p->ramcfg_11_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3; |
150 | p->ramcfg_11_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4; |
151 | p->ramcfg_11_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6; |
152 | p->ramcfg_11_02_80 = (nv_ro08(bios, data + 0x02) & 0x80) >> 7; |
153 | p->ramcfg_11_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0; |
154 | p->ramcfg_11_03_30 = (nv_ro08(bios, data + 0x03) & 0x30) >> 4; |
155 | p->ramcfg_11_03_c0 = (nv_ro08(bios, data + 0x03) & 0xc0) >> 6; |
156 | p->ramcfg_11_03_f0 = (nv_ro08(bios, data + 0x03) & 0xf0) >> 4; |
157 | p->ramcfg_11_04 = (nv_ro08(bios, data + 0x04) & 0xff) >> 0; |
158 | p->ramcfg_11_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0; |
159 | p->ramcfg_11_07_02 = (nv_ro08(bios, data + 0x07) & 0x02) >> 1; |
160 | p->ramcfg_11_07_04 = (nv_ro08(bios, data + 0x07) & 0x04) >> 2; |
161 | p->ramcfg_11_07_08 = (nv_ro08(bios, data + 0x07) & 0x08) >> 3; |
162 | p->ramcfg_11_07_10 = (nv_ro08(bios, data + 0x07) & 0x10) >> 4; |
163 | p->ramcfg_11_07_40 = (nv_ro08(bios, data + 0x07) & 0x40) >> 6; |
164 | p->ramcfg_11_07_80 = (nv_ro08(bios, data + 0x07) & 0x80) >> 7; |
165 | p->ramcfg_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0; |
166 | p->ramcfg_11_08_02 = (nv_ro08(bios, data + 0x08) & 0x02) >> 1; |
167 | p->ramcfg_11_08_04 = (nv_ro08(bios, data + 0x08) & 0x04) >> 2; |
168 | p->ramcfg_11_08_08 = (nv_ro08(bios, data + 0x08) & 0x08) >> 3; |
169 | p->ramcfg_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4; |
170 | p->ramcfg_11_08_20 = (nv_ro08(bios, data + 0x08) & 0x20) >> 5; |
171 | p->ramcfg_11_09 = (nv_ro08(bios, data + 0x09) & 0xff) >> 0; |
172 | break; |
173 | default: |
174 | data = 0; |
175 | break; |
176 | } |
177 | return data; |
178 | } |
179 | |