1 | /****************************************************************************** |
2 | |
3 | Copyright (c) 2001-2013, Intel Corporation |
4 | All rights reserved. |
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31 | |
32 | ******************************************************************************/ |
33 | /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 251964 2013-06-18 21:28:19Z jfv $*/ |
34 | |
35 | #include "ixgbe_x540.h" |
36 | #include "ixgbe_type.h" |
37 | #include "ixgbe_api.h" |
38 | #include "ixgbe_common.h" |
39 | #include "ixgbe_phy.h" |
40 | |
41 | static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); |
42 | static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); |
43 | static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); |
44 | |
45 | /** |
46 | * ixgbe_init_ops_X540 - Inits func ptrs and MAC type |
47 | * @hw: pointer to hardware structure |
48 | * |
49 | * Initialize the function pointers and assign the MAC type for X540. |
50 | * Does not touch the hardware. |
51 | **/ |
52 | s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) |
53 | { |
54 | struct ixgbe_mac_info *mac = &hw->mac; |
55 | struct ixgbe_phy_info *phy = &hw->phy; |
56 | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; |
57 | s32 ret_val; |
58 | |
59 | DEBUGFUNC("ixgbe_init_ops_X540" ); |
60 | |
61 | ret_val = ixgbe_init_phy_ops_generic(hw); |
62 | ret_val = ixgbe_init_ops_generic(hw); |
63 | |
64 | |
65 | /* EEPROM */ |
66 | eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540; |
67 | eeprom->ops.read = &ixgbe_read_eerd_X540; |
68 | eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540; |
69 | eeprom->ops.write = &ixgbe_write_eewr_X540; |
70 | eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540; |
71 | eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540; |
72 | eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540; |
73 | eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540; |
74 | |
75 | /* PHY */ |
76 | phy->ops.init = &ixgbe_init_phy_ops_generic; |
77 | phy->ops.reset = NULL; |
78 | |
79 | /* MAC */ |
80 | mac->ops.reset_hw = &ixgbe_reset_hw_X540; |
81 | mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; |
82 | mac->ops.get_media_type = &ixgbe_get_media_type_X540; |
83 | mac->ops.get_supported_physical_layer = |
84 | &ixgbe_get_supported_physical_layer_X540; |
85 | mac->ops.read_analog_reg8 = NULL; |
86 | mac->ops.write_analog_reg8 = NULL; |
87 | mac->ops.start_hw = &ixgbe_start_hw_X540; |
88 | mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic; |
89 | mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic; |
90 | mac->ops.get_device_caps = &ixgbe_get_device_caps_generic; |
91 | mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic; |
92 | mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic; |
93 | mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540; |
94 | mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540; |
95 | mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic; |
96 | mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic; |
97 | |
98 | /* RAR, Multicast, VLAN */ |
99 | mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; |
100 | mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic; |
101 | mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; |
102 | mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; |
103 | mac->rar_highwater = 1; |
104 | mac->ops.set_vfta = &ixgbe_set_vfta_generic; |
105 | mac->ops.set_vlvf = &ixgbe_set_vlvf_generic; |
106 | mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; |
107 | mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; |
108 | mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing; |
109 | mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing; |
110 | |
111 | /* Link */ |
112 | mac->ops.get_link_capabilities = |
113 | &ixgbe_get_copper_link_capabilities_generic; |
114 | mac->ops.setup_link = &ixgbe_setup_mac_link_X540; |
115 | mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic; |
116 | mac->ops.check_link = &ixgbe_check_mac_link_generic; |
117 | |
118 | |
119 | mac->mcft_size = 128; |
120 | mac->vft_size = 128; |
121 | mac->num_rar_entries = 128; |
122 | mac->rx_pb_size = 384; |
123 | mac->max_tx_queues = 128; |
124 | mac->max_rx_queues = 128; |
125 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); |
126 | |
127 | /* |
128 | * FWSM register |
129 | * ARC supported; valid only if manageability features are |
130 | * enabled. |
131 | */ |
132 | mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) & |
133 | IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE; |
134 | |
135 | hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; |
136 | |
137 | /* LEDs */ |
138 | mac->ops.blink_led_start = ixgbe_blink_led_start_X540; |
139 | mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; |
140 | |
141 | /* Manageability interface */ |
142 | mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic; |
143 | |
144 | mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic; |
145 | |
146 | return ret_val; |
147 | } |
148 | |
149 | /** |
150 | * ixgbe_get_link_capabilities_X540 - Determines link capabilities |
151 | * @hw: pointer to hardware structure |
152 | * @speed: pointer to link speed |
153 | * @autoneg: TRUE when autoneg or autotry is enabled |
154 | * |
155 | * Determines the link capabilities by reading the AUTOC register. |
156 | **/ |
157 | s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, |
158 | ixgbe_link_speed *speed, |
159 | bool *autoneg) |
160 | { |
161 | ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); |
162 | |
163 | return IXGBE_SUCCESS; |
164 | } |
165 | |
166 | /** |
167 | * ixgbe_get_media_type_X540 - Get media type |
168 | * @hw: pointer to hardware structure |
169 | * |
170 | * Returns the media type (fiber, copper, backplane) |
171 | **/ |
172 | enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) |
173 | { |
174 | UNREFERENCED_1PARAMETER(hw); |
175 | return ixgbe_media_type_copper; |
176 | } |
177 | |
178 | /** |
179 | * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities |
180 | * @hw: pointer to hardware structure |
181 | * @speed: new link speed |
182 | * @autoneg_wait_to_complete: TRUE when waiting for completion is needed |
183 | **/ |
184 | s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, |
185 | ixgbe_link_speed speed, |
186 | bool autoneg_wait_to_complete) |
187 | { |
188 | DEBUGFUNC("ixgbe_setup_mac_link_X540" ); |
189 | return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); |
190 | } |
191 | |
192 | /** |
193 | * ixgbe_reset_hw_X540 - Perform hardware reset |
194 | * @hw: pointer to hardware structure |
195 | * |
196 | * Resets the hardware by resetting the transmit and receive units, masks |
197 | * and clears all interrupts, and perform a reset. |
198 | **/ |
199 | s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) |
200 | { |
201 | s32 status; |
202 | u32 ctrl, i; |
203 | |
204 | DEBUGFUNC("ixgbe_reset_hw_X540" ); |
205 | |
206 | /* Call adapter stop to disable tx/rx and clear interrupts */ |
207 | status = hw->mac.ops.stop_adapter(hw); |
208 | if (status != IXGBE_SUCCESS) |
209 | goto reset_hw_out; |
210 | |
211 | /* flush pending Tx transactions */ |
212 | ixgbe_clear_tx_pending(hw); |
213 | |
214 | mac_reset_top: |
215 | ctrl = IXGBE_CTRL_RST; |
216 | ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); |
217 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); |
218 | IXGBE_WRITE_FLUSH(hw); |
219 | |
220 | /* Poll for reset bit to self-clear indicating reset is complete */ |
221 | for (i = 0; i < 10; i++) { |
222 | usec_delay(1); |
223 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); |
224 | if (!(ctrl & IXGBE_CTRL_RST_MASK)) |
225 | break; |
226 | } |
227 | |
228 | if (ctrl & IXGBE_CTRL_RST_MASK) { |
229 | status = IXGBE_ERR_RESET_FAILED; |
230 | ERROR_REPORT1(IXGBE_ERROR_POLLING, |
231 | "Reset polling failed to complete.\n" ); |
232 | } |
233 | msec_delay(100); |
234 | |
235 | /* |
236 | * Double resets are required for recovery from certain error |
237 | * conditions. Between resets, it is necessary to stall to allow time |
238 | * for any pending HW events to complete. |
239 | */ |
240 | if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { |
241 | hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; |
242 | goto mac_reset_top; |
243 | } |
244 | |
245 | /* Set the Rx packet buffer size. */ |
246 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); |
247 | |
248 | /* Store the permanent mac address */ |
249 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); |
250 | |
251 | /* |
252 | * Store MAC address from RAR0, clear receive address registers, and |
253 | * clear the multicast table. Also reset num_rar_entries to 128, |
254 | * since we modify this value when programming the SAN MAC address. |
255 | */ |
256 | hw->mac.num_rar_entries = 128; |
257 | hw->mac.ops.init_rx_addrs(hw); |
258 | |
259 | /* Store the permanent SAN mac address */ |
260 | hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); |
261 | |
262 | /* Add the SAN MAC address to the RAR only if it's a valid address */ |
263 | if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { |
264 | hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, |
265 | hw->mac.san_addr, 0, IXGBE_RAH_AV); |
266 | |
267 | /* Save the SAN MAC RAR index */ |
268 | hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; |
269 | |
270 | /* Reserve the last RAR for the SAN MAC address */ |
271 | hw->mac.num_rar_entries--; |
272 | } |
273 | |
274 | /* Store the alternative WWNN/WWPN prefix */ |
275 | hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, |
276 | &hw->mac.wwpn_prefix); |
277 | |
278 | reset_hw_out: |
279 | return status; |
280 | } |
281 | |
282 | /** |
283 | * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx |
284 | * @hw: pointer to hardware structure |
285 | * |
286 | * Starts the hardware using the generic start_hw function |
287 | * and the generation start_hw function. |
288 | * Then performs revision-specific operations, if any. |
289 | **/ |
290 | s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) |
291 | { |
292 | s32 ret_val = IXGBE_SUCCESS; |
293 | |
294 | DEBUGFUNC("ixgbe_start_hw_X540" ); |
295 | |
296 | ret_val = ixgbe_start_hw_generic(hw); |
297 | if (ret_val != IXGBE_SUCCESS) |
298 | goto out; |
299 | |
300 | ret_val = ixgbe_start_hw_gen2(hw); |
301 | |
302 | out: |
303 | return ret_val; |
304 | } |
305 | |
306 | /** |
307 | * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type |
308 | * @hw: pointer to hardware structure |
309 | * |
310 | * Determines physical layer capabilities of the current configuration. |
311 | **/ |
312 | u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) |
313 | { |
314 | u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; |
315 | u16 ext_ability = 0; |
316 | |
317 | DEBUGFUNC("ixgbe_get_supported_physical_layer_X540" ); |
318 | |
319 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, |
320 | IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); |
321 | if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) |
322 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; |
323 | if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) |
324 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; |
325 | if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) |
326 | physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; |
327 | |
328 | return physical_layer; |
329 | } |
330 | |
331 | /** |
332 | * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params |
333 | * @hw: pointer to hardware structure |
334 | * |
335 | * Initializes the EEPROM parameters ixgbe_eeprom_info within the |
336 | * ixgbe_hw struct in order to set up EEPROM access. |
337 | **/ |
338 | s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) |
339 | { |
340 | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; |
341 | u32 eec; |
342 | u16 eeprom_size; |
343 | |
344 | DEBUGFUNC("ixgbe_init_eeprom_params_X540" ); |
345 | |
346 | if (eeprom->type == ixgbe_eeprom_uninitialized) { |
347 | eeprom->semaphore_delay = 10; |
348 | eeprom->type = ixgbe_flash; |
349 | |
350 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); |
351 | eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> |
352 | IXGBE_EEC_SIZE_SHIFT); |
353 | eeprom->word_size = 1 << (eeprom_size + |
354 | IXGBE_EEPROM_WORD_SIZE_SHIFT); |
355 | |
356 | DEBUGOUT2("Eeprom params: type = %d, size = %d\n" , |
357 | eeprom->type, eeprom->word_size); |
358 | } |
359 | |
360 | return IXGBE_SUCCESS; |
361 | } |
362 | |
363 | /** |
364 | * ixgbe_read_eerd_X540- Read EEPROM word using EERD |
365 | * @hw: pointer to hardware structure |
366 | * @offset: offset of word in the EEPROM to read |
367 | * @data: word read from the EEPROM |
368 | * |
369 | * Reads a 16 bit word from the EEPROM using the EERD register. |
370 | **/ |
371 | s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) |
372 | { |
373 | s32 status = IXGBE_SUCCESS; |
374 | |
375 | DEBUGFUNC("ixgbe_read_eerd_X540" ); |
376 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == |
377 | IXGBE_SUCCESS) { |
378 | status = ixgbe_read_eerd_generic(hw, offset, data); |
379 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
380 | } else { |
381 | status = IXGBE_ERR_SWFW_SYNC; |
382 | } |
383 | |
384 | return status; |
385 | } |
386 | |
387 | /** |
388 | * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD |
389 | * @hw: pointer to hardware structure |
390 | * @offset: offset of word in the EEPROM to read |
391 | * @words: number of words |
392 | * @data: word(s) read from the EEPROM |
393 | * |
394 | * Reads a 16 bit word(s) from the EEPROM using the EERD register. |
395 | **/ |
396 | s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, |
397 | u16 offset, u16 words, u16 *data) |
398 | { |
399 | s32 status = IXGBE_SUCCESS; |
400 | |
401 | DEBUGFUNC("ixgbe_read_eerd_buffer_X540" ); |
402 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == |
403 | IXGBE_SUCCESS) { |
404 | status = ixgbe_read_eerd_buffer_generic(hw, offset, |
405 | words, data); |
406 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
407 | } else { |
408 | status = IXGBE_ERR_SWFW_SYNC; |
409 | } |
410 | |
411 | return status; |
412 | } |
413 | |
414 | /** |
415 | * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR |
416 | * @hw: pointer to hardware structure |
417 | * @offset: offset of word in the EEPROM to write |
418 | * @data: word write to the EEPROM |
419 | * |
420 | * Write a 16 bit word to the EEPROM using the EEWR register. |
421 | **/ |
422 | s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) |
423 | { |
424 | s32 status = IXGBE_SUCCESS; |
425 | |
426 | DEBUGFUNC("ixgbe_write_eewr_X540" ); |
427 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == |
428 | IXGBE_SUCCESS) { |
429 | status = ixgbe_write_eewr_generic(hw, offset, data); |
430 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
431 | } else { |
432 | status = IXGBE_ERR_SWFW_SYNC; |
433 | } |
434 | |
435 | return status; |
436 | } |
437 | |
438 | /** |
439 | * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR |
440 | * @hw: pointer to hardware structure |
441 | * @offset: offset of word in the EEPROM to write |
442 | * @words: number of words |
443 | * @data: word(s) write to the EEPROM |
444 | * |
445 | * Write a 16 bit word(s) to the EEPROM using the EEWR register. |
446 | **/ |
447 | s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, |
448 | u16 offset, u16 words, u16 *data) |
449 | { |
450 | s32 status = IXGBE_SUCCESS; |
451 | |
452 | DEBUGFUNC("ixgbe_write_eewr_buffer_X540" ); |
453 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == |
454 | IXGBE_SUCCESS) { |
455 | status = ixgbe_write_eewr_buffer_generic(hw, offset, |
456 | words, data); |
457 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
458 | } else { |
459 | status = IXGBE_ERR_SWFW_SYNC; |
460 | } |
461 | |
462 | return status; |
463 | } |
464 | |
465 | /** |
466 | * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum |
467 | * |
468 | * This function does not use synchronization for EERD and EEWR. It can |
469 | * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. |
470 | * |
471 | * @hw: pointer to hardware structure |
472 | **/ |
473 | u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) |
474 | { |
475 | u16 i; |
476 | u16 j; |
477 | u16 checksum = 0; |
478 | u16 length = 0; |
479 | u16 pointer = 0; |
480 | u16 word = 0; |
481 | |
482 | /* |
483 | * Do not use hw->eeprom.ops.read because we do not want to take |
484 | * the synchronization semaphores here. Instead use |
485 | * ixgbe_read_eerd_generic |
486 | */ |
487 | |
488 | DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540" ); |
489 | |
490 | /* Include 0x0-0x3F in the checksum */ |
491 | for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { |
492 | if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) { |
493 | DEBUGOUT("EEPROM read failed\n" ); |
494 | break; |
495 | } |
496 | checksum += word; |
497 | } |
498 | |
499 | /* |
500 | * Include all data from pointers 0x3, 0x6-0xE. This excludes the |
501 | * FW, PHY module, and PCIe Expansion/Option ROM pointers. |
502 | */ |
503 | for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { |
504 | if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) |
505 | continue; |
506 | |
507 | if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) { |
508 | DEBUGOUT("EEPROM read failed\n" ); |
509 | break; |
510 | } |
511 | |
512 | /* Skip pointer section if the pointer is invalid. */ |
513 | if (pointer == 0xFFFF || pointer == 0 || |
514 | pointer >= hw->eeprom.word_size) |
515 | continue; |
516 | |
517 | if (ixgbe_read_eerd_generic(hw, pointer, &length) != |
518 | IXGBE_SUCCESS) { |
519 | DEBUGOUT("EEPROM read failed\n" ); |
520 | break; |
521 | } |
522 | |
523 | /* Skip pointer section if length is invalid. */ |
524 | if (length == 0xFFFF || length == 0 || |
525 | (pointer + length) >= hw->eeprom.word_size) |
526 | continue; |
527 | |
528 | for (j = pointer+1; j <= pointer+length; j++) { |
529 | if (ixgbe_read_eerd_generic(hw, j, &word) != |
530 | IXGBE_SUCCESS) { |
531 | DEBUGOUT("EEPROM read failed\n" ); |
532 | break; |
533 | } |
534 | checksum += word; |
535 | } |
536 | } |
537 | |
538 | checksum = (u16)IXGBE_EEPROM_SUM - checksum; |
539 | |
540 | return checksum; |
541 | } |
542 | |
543 | /** |
544 | * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum |
545 | * @hw: pointer to hardware structure |
546 | * @checksum_val: calculated checksum |
547 | * |
548 | * Performs checksum calculation and validates the EEPROM checksum. If the |
549 | * caller does not need checksum_val, the value can be NULL. |
550 | **/ |
551 | s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, |
552 | u16 *checksum_val) |
553 | { |
554 | s32 status; |
555 | u16 checksum; |
556 | u16 read_checksum = 0; |
557 | |
558 | DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540" ); |
559 | |
560 | /* |
561 | * Read the first word from the EEPROM. If this times out or fails, do |
562 | * not continue or we could be in for a very long wait while every |
563 | * EEPROM read fails |
564 | */ |
565 | status = hw->eeprom.ops.read(hw, 0, &checksum); |
566 | |
567 | if (status != IXGBE_SUCCESS) { |
568 | DEBUGOUT("EEPROM read failed\n" ); |
569 | goto out; |
570 | } |
571 | |
572 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == |
573 | IXGBE_SUCCESS) { |
574 | checksum = hw->eeprom.ops.calc_checksum(hw); |
575 | |
576 | /* |
577 | * Do not use hw->eeprom.ops.read because we do not want to take |
578 | * the synchronization semaphores twice here. |
579 | */ |
580 | ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, |
581 | &read_checksum); |
582 | |
583 | /* |
584 | * Verify read checksum from EEPROM is the same as |
585 | * calculated checksum |
586 | */ |
587 | if (read_checksum != checksum) { |
588 | status = IXGBE_ERR_EEPROM_CHECKSUM; |
589 | ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, |
590 | "Invalid EEPROM checksum" ); |
591 | } |
592 | |
593 | /* If the user cares, return the calculated checksum */ |
594 | if (checksum_val) |
595 | *checksum_val = checksum; |
596 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
597 | } else { |
598 | status = IXGBE_ERR_SWFW_SYNC; |
599 | } |
600 | |
601 | out: |
602 | return status; |
603 | } |
604 | |
605 | /** |
606 | * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash |
607 | * @hw: pointer to hardware structure |
608 | * |
609 | * After writing EEPROM to shadow RAM using EEWR register, software calculates |
610 | * checksum and updates the EEPROM and instructs the hardware to update |
611 | * the flash. |
612 | **/ |
613 | s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) |
614 | { |
615 | s32 status; |
616 | u16 checksum; |
617 | |
618 | DEBUGFUNC("ixgbe_update_eeprom_checksum_X540" ); |
619 | |
620 | /* |
621 | * Read the first word from the EEPROM. If this times out or fails, do |
622 | * not continue or we could be in for a very long wait while every |
623 | * EEPROM read fails |
624 | */ |
625 | status = hw->eeprom.ops.read(hw, 0, &checksum); |
626 | |
627 | if (status != IXGBE_SUCCESS) |
628 | DEBUGOUT("EEPROM read failed\n" ); |
629 | |
630 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == |
631 | IXGBE_SUCCESS) { |
632 | checksum = hw->eeprom.ops.calc_checksum(hw); |
633 | |
634 | /* |
635 | * Do not use hw->eeprom.ops.write because we do not want to |
636 | * take the synchronization semaphores twice here. |
637 | */ |
638 | status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, |
639 | checksum); |
640 | |
641 | if (status == IXGBE_SUCCESS) |
642 | status = ixgbe_update_flash_X540(hw); |
643 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
644 | } else { |
645 | status = IXGBE_ERR_SWFW_SYNC; |
646 | } |
647 | |
648 | return status; |
649 | } |
650 | |
651 | /** |
652 | * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device |
653 | * @hw: pointer to hardware structure |
654 | * |
655 | * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy |
656 | * EEPROM from shadow RAM to the flash device. |
657 | **/ |
658 | s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) |
659 | { |
660 | u32 flup; |
661 | s32 status = IXGBE_ERR_EEPROM; |
662 | |
663 | DEBUGFUNC("ixgbe_update_flash_X540" ); |
664 | |
665 | status = ixgbe_poll_flash_update_done_X540(hw); |
666 | if (status == IXGBE_ERR_EEPROM) { |
667 | DEBUGOUT("Flash update time out\n" ); |
668 | goto out; |
669 | } |
670 | |
671 | flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP; |
672 | IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); |
673 | |
674 | status = ixgbe_poll_flash_update_done_X540(hw); |
675 | if (status == IXGBE_SUCCESS) |
676 | DEBUGOUT("Flash update complete\n" ); |
677 | else |
678 | DEBUGOUT("Flash update time out\n" ); |
679 | |
680 | if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) { |
681 | flup = IXGBE_READ_REG(hw, IXGBE_EEC); |
682 | |
683 | if (flup & IXGBE_EEC_SEC1VAL) { |
684 | flup |= IXGBE_EEC_FLUP; |
685 | IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); |
686 | } |
687 | |
688 | status = ixgbe_poll_flash_update_done_X540(hw); |
689 | if (status == IXGBE_SUCCESS) |
690 | DEBUGOUT("Flash update complete\n" ); |
691 | else |
692 | DEBUGOUT("Flash update time out\n" ); |
693 | } |
694 | out: |
695 | return status; |
696 | } |
697 | |
698 | /** |
699 | * ixgbe_poll_flash_update_done_X540 - Poll flash update status |
700 | * @hw: pointer to hardware structure |
701 | * |
702 | * Polls the FLUDONE (bit 26) of the EEC Register to determine when the |
703 | * flash update is done. |
704 | **/ |
705 | static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) |
706 | { |
707 | u32 i; |
708 | u32 reg; |
709 | s32 status = IXGBE_ERR_EEPROM; |
710 | |
711 | DEBUGFUNC("ixgbe_poll_flash_update_done_X540" ); |
712 | |
713 | for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { |
714 | reg = IXGBE_READ_REG(hw, IXGBE_EEC); |
715 | if (reg & IXGBE_EEC_FLUDONE) { |
716 | status = IXGBE_SUCCESS; |
717 | break; |
718 | } |
719 | usec_delay(5); |
720 | } |
721 | |
722 | if (i == IXGBE_FLUDONE_ATTEMPTS) |
723 | ERROR_REPORT1(IXGBE_ERROR_POLLING, |
724 | "Flash update status polling timed out" ); |
725 | |
726 | return status; |
727 | } |
728 | |
729 | /** |
730 | * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore |
731 | * @hw: pointer to hardware structure |
732 | * @mask: Mask to specify which semaphore to acquire |
733 | * |
734 | * Acquires the SWFW semaphore thought the SW_FW_SYNC register for |
735 | * the specified function (CSR, PHY0, PHY1, NVM, Flash) |
736 | **/ |
737 | s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) |
738 | { |
739 | u32 swfw_sync; |
740 | u32 swmask = mask; |
741 | u32 fwmask = mask << 5; |
742 | u32 hwmask = 0; |
743 | u32 timeout = 200; |
744 | u32 i; |
745 | s32 ret_val = IXGBE_SUCCESS; |
746 | |
747 | DEBUGFUNC("ixgbe_acquire_swfw_sync_X540" ); |
748 | |
749 | if (swmask == IXGBE_GSSR_EEP_SM) |
750 | hwmask = IXGBE_GSSR_FLASH_SM; |
751 | |
752 | /* SW only mask doesn't have FW bit pair */ |
753 | if (swmask == IXGBE_GSSR_SW_MNG_SM) |
754 | fwmask = 0; |
755 | |
756 | for (i = 0; i < timeout; i++) { |
757 | /* |
758 | * SW NVM semaphore bit is used for access to all |
759 | * SW_FW_SYNC bits (not just NVM) |
760 | */ |
761 | if (ixgbe_get_swfw_sync_semaphore(hw)) { |
762 | ret_val = IXGBE_ERR_SWFW_SYNC; |
763 | goto out; |
764 | } |
765 | |
766 | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); |
767 | if (!(swfw_sync & (fwmask | swmask | hwmask))) { |
768 | swfw_sync |= swmask; |
769 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); |
770 | ixgbe_release_swfw_sync_semaphore(hw); |
771 | goto out; |
772 | } else { |
773 | /* |
774 | * Firmware currently using resource (fwmask), hardware |
775 | * currently using resource (hwmask), or other software |
776 | * thread currently using resource (swmask) |
777 | */ |
778 | ixgbe_release_swfw_sync_semaphore(hw); |
779 | msec_delay(5); |
780 | } |
781 | } |
782 | |
783 | /* Failed to get SW only semaphore */ |
784 | if (swmask == IXGBE_GSSR_SW_MNG_SM) { |
785 | ret_val = IXGBE_ERR_SWFW_SYNC; |
786 | ERROR_REPORT1(IXGBE_ERROR_POLLING, |
787 | "Failed to get SW only semaphore" ); |
788 | goto out; |
789 | } |
790 | |
791 | /* If the resource is not released by the FW/HW the SW can assume that |
792 | * the FW/HW malfunctions. In that case the SW should set the SW bit(s) |
793 | * of the requested resource(s) while ignoring the corresponding FW/HW |
794 | * bits in the SW_FW_SYNC register. |
795 | */ |
796 | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); |
797 | if (swfw_sync & (fwmask | hwmask)) { |
798 | if (ixgbe_get_swfw_sync_semaphore(hw)) { |
799 | ret_val = IXGBE_ERR_SWFW_SYNC; |
800 | goto out; |
801 | } |
802 | |
803 | swfw_sync |= swmask; |
804 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); |
805 | ixgbe_release_swfw_sync_semaphore(hw); |
806 | msec_delay(5); |
807 | } |
808 | /* If the resource is not released by other SW the SW can assume that |
809 | * the other SW malfunctions. In that case the SW should clear all SW |
810 | * flags that it does not own and then repeat the whole process once |
811 | * again. |
812 | */ |
813 | else if (swfw_sync & swmask) { |
814 | ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM | |
815 | IXGBE_GSSR_PHY0_SM | IXGBE_GSSR_PHY1_SM | |
816 | IXGBE_GSSR_MAC_CSR_SM); |
817 | ret_val = IXGBE_ERR_SWFW_SYNC; |
818 | } |
819 | |
820 | out: |
821 | return ret_val; |
822 | } |
823 | |
824 | /** |
825 | * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore |
826 | * @hw: pointer to hardware structure |
827 | * @mask: Mask to specify which semaphore to release |
828 | * |
829 | * Releases the SWFW semaphore through the SW_FW_SYNC register |
830 | * for the specified function (CSR, PHY0, PHY1, EVM, Flash) |
831 | **/ |
832 | void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) |
833 | { |
834 | u32 swfw_sync; |
835 | u32 swmask = mask; |
836 | |
837 | DEBUGFUNC("ixgbe_release_swfw_sync_X540" ); |
838 | |
839 | ixgbe_get_swfw_sync_semaphore(hw); |
840 | |
841 | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); |
842 | swfw_sync &= ~swmask; |
843 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); |
844 | |
845 | ixgbe_release_swfw_sync_semaphore(hw); |
846 | } |
847 | |
848 | /** |
849 | * ixgbe_get_nvm_semaphore - Get hardware semaphore |
850 | * @hw: pointer to hardware structure |
851 | * |
852 | * Sets the hardware semaphores so SW/FW can gain control of shared resources |
853 | **/ |
854 | static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) |
855 | { |
856 | s32 status = IXGBE_ERR_EEPROM; |
857 | u32 timeout = 2000; |
858 | u32 i; |
859 | u32 swsm; |
860 | |
861 | DEBUGFUNC("ixgbe_get_swfw_sync_semaphore" ); |
862 | |
863 | /* Get SMBI software semaphore between device drivers first */ |
864 | for (i = 0; i < timeout; i++) { |
865 | /* |
866 | * If the SMBI bit is 0 when we read it, then the bit will be |
867 | * set and we have the semaphore |
868 | */ |
869 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); |
870 | if (!(swsm & IXGBE_SWSM_SMBI)) { |
871 | status = IXGBE_SUCCESS; |
872 | break; |
873 | } |
874 | usec_delay(50); |
875 | } |
876 | |
877 | /* Now get the semaphore between SW/FW through the REGSMP bit */ |
878 | if (status == IXGBE_SUCCESS) { |
879 | for (i = 0; i < timeout; i++) { |
880 | swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); |
881 | if (!(swsm & IXGBE_SWFW_REGSMP)) |
882 | break; |
883 | |
884 | usec_delay(50); |
885 | } |
886 | |
887 | /* |
888 | * Release semaphores and return error if SW NVM semaphore |
889 | * was not granted because we don't have access to the EEPROM |
890 | */ |
891 | if (i >= timeout) { |
892 | ERROR_REPORT1(IXGBE_ERROR_POLLING, |
893 | "REGSMP Software NVM semaphore not granted.\n" ); |
894 | ixgbe_release_swfw_sync_semaphore(hw); |
895 | status = IXGBE_ERR_EEPROM; |
896 | } |
897 | } else { |
898 | ERROR_REPORT1(IXGBE_ERROR_POLLING, |
899 | "Software semaphore SMBI between device drivers " |
900 | "not granted.\n" ); |
901 | } |
902 | |
903 | return status; |
904 | } |
905 | |
906 | /** |
907 | * ixgbe_release_nvm_semaphore - Release hardware semaphore |
908 | * @hw: pointer to hardware structure |
909 | * |
910 | * This function clears hardware semaphore bits. |
911 | **/ |
912 | static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) |
913 | { |
914 | u32 swsm; |
915 | |
916 | DEBUGFUNC("ixgbe_release_swfw_sync_semaphore" ); |
917 | |
918 | /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ |
919 | |
920 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); |
921 | swsm &= ~IXGBE_SWSM_SMBI; |
922 | IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); |
923 | |
924 | swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); |
925 | swsm &= ~IXGBE_SWFW_REGSMP; |
926 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm); |
927 | |
928 | IXGBE_WRITE_FLUSH(hw); |
929 | } |
930 | |
931 | /** |
932 | * ixgbe_blink_led_start_X540 - Blink LED based on index. |
933 | * @hw: pointer to hardware structure |
934 | * @index: led number to blink |
935 | * |
936 | * Devices that implement the version 2 interface: |
937 | * X540 |
938 | **/ |
939 | s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) |
940 | { |
941 | u32 macc_reg; |
942 | u32 ledctl_reg; |
943 | ixgbe_link_speed speed; |
944 | bool link_up; |
945 | |
946 | DEBUGFUNC("ixgbe_blink_led_start_X540" ); |
947 | |
948 | /* |
949 | * Link should be up in order for the blink bit in the LED control |
950 | * register to work. Force link and speed in the MAC if link is down. |
951 | * This will be reversed when we stop the blinking. |
952 | */ |
953 | hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); |
954 | if (link_up == FALSE) { |
955 | macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); |
956 | macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; |
957 | IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); |
958 | } |
959 | /* Set the LED to LINK_UP + BLINK. */ |
960 | ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); |
961 | ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); |
962 | ledctl_reg |= IXGBE_LED_BLINK(index); |
963 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); |
964 | IXGBE_WRITE_FLUSH(hw); |
965 | |
966 | return IXGBE_SUCCESS; |
967 | } |
968 | |
969 | /** |
970 | * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. |
971 | * @hw: pointer to hardware structure |
972 | * @index: led number to stop blinking |
973 | * |
974 | * Devices that implement the version 2 interface: |
975 | * X540 |
976 | **/ |
977 | s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) |
978 | { |
979 | u32 macc_reg; |
980 | u32 ledctl_reg; |
981 | |
982 | DEBUGFUNC("ixgbe_blink_led_stop_X540" ); |
983 | |
984 | /* Restore the LED to its default value. */ |
985 | ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); |
986 | ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); |
987 | ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); |
988 | ledctl_reg &= ~IXGBE_LED_BLINK(index); |
989 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); |
990 | |
991 | /* Unforce link and speed in the MAC. */ |
992 | macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); |
993 | macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); |
994 | IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); |
995 | IXGBE_WRITE_FLUSH(hw); |
996 | |
997 | return IXGBE_SUCCESS; |
998 | } |
999 | |
1000 | |
1001 | |