1 | /* $NetBSD: nouveau_subdev_clock_nvc0.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_clock_nvc0.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $" ); |
29 | |
30 | #include <subdev/clock.h> |
31 | #include <subdev/bios.h> |
32 | #include <subdev/bios/pll.h> |
33 | #include <subdev/timer.h> |
34 | |
35 | #include "pll.h" |
36 | |
37 | struct nvc0_clock_info { |
38 | u32 freq; |
39 | u32 ssel; |
40 | u32 mdiv; |
41 | u32 dsrc; |
42 | u32 ddiv; |
43 | u32 coef; |
44 | }; |
45 | |
46 | struct nvc0_clock_priv { |
47 | struct nouveau_clock base; |
48 | struct nvc0_clock_info eng[16]; |
49 | }; |
50 | |
51 | static u32 read_div(struct nvc0_clock_priv *, int, u32, u32); |
52 | |
53 | static u32 |
54 | read_vco(struct nvc0_clock_priv *priv, u32 dsrc) |
55 | { |
56 | struct nouveau_clock *clk = &priv->base; |
57 | u32 ssrc = nv_rd32(priv, dsrc); |
58 | if (!(ssrc & 0x00000100)) |
59 | return clk->read(clk, nv_clk_src_sppll0); |
60 | return clk->read(clk, nv_clk_src_sppll1); |
61 | } |
62 | |
63 | static u32 |
64 | read_pll(struct nvc0_clock_priv *priv, u32 pll) |
65 | { |
66 | struct nouveau_clock *clk = &priv->base; |
67 | u32 ctrl = nv_rd32(priv, pll + 0x00); |
68 | u32 coef = nv_rd32(priv, pll + 0x04); |
69 | u32 P = (coef & 0x003f0000) >> 16; |
70 | u32 N = (coef & 0x0000ff00) >> 8; |
71 | u32 M = (coef & 0x000000ff) >> 0; |
72 | u32 sclk; |
73 | |
74 | if (!(ctrl & 0x00000001)) |
75 | return 0; |
76 | |
77 | switch (pll) { |
78 | case 0x00e800: |
79 | case 0x00e820: |
80 | sclk = nv_device(priv)->crystal; |
81 | P = 1; |
82 | break; |
83 | case 0x132000: |
84 | sclk = clk->read(clk, nv_clk_src_mpllsrc); |
85 | break; |
86 | case 0x132020: |
87 | sclk = clk->read(clk, nv_clk_src_mpllsrcref); |
88 | break; |
89 | case 0x137000: |
90 | case 0x137020: |
91 | case 0x137040: |
92 | case 0x1370e0: |
93 | sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140); |
94 | break; |
95 | default: |
96 | return 0; |
97 | } |
98 | |
99 | return sclk * N / M / P; |
100 | } |
101 | |
102 | static u32 |
103 | read_div(struct nvc0_clock_priv *priv, int doff, u32 dsrc, u32 dctl) |
104 | { |
105 | u32 ssrc = nv_rd32(priv, dsrc + (doff * 4)); |
106 | u32 sctl = nv_rd32(priv, dctl + (doff * 4)); |
107 | |
108 | switch (ssrc & 0x00000003) { |
109 | case 0: |
110 | if ((ssrc & 0x00030000) != 0x00030000) |
111 | return nv_device(priv)->crystal; |
112 | return 108000; |
113 | case 2: |
114 | return 100000; |
115 | case 3: |
116 | if (sctl & 0x80000000) { |
117 | u32 sclk = read_vco(priv, dsrc + (doff * 4)); |
118 | u32 sdiv = (sctl & 0x0000003f) + 2; |
119 | return (sclk * 2) / sdiv; |
120 | } |
121 | |
122 | return read_vco(priv, dsrc + (doff * 4)); |
123 | default: |
124 | return 0; |
125 | } |
126 | } |
127 | |
128 | static u32 |
129 | read_clk(struct nvc0_clock_priv *priv, int clk) |
130 | { |
131 | u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); |
132 | u32 ssel = nv_rd32(priv, 0x137100); |
133 | u32 sclk, sdiv; |
134 | |
135 | if (ssel & (1 << clk)) { |
136 | if (clk < 7) |
137 | sclk = read_pll(priv, 0x137000 + (clk * 0x20)); |
138 | else |
139 | sclk = read_pll(priv, 0x1370e0); |
140 | sdiv = ((sctl & 0x00003f00) >> 8) + 2; |
141 | } else { |
142 | sclk = read_div(priv, clk, 0x137160, 0x1371d0); |
143 | sdiv = ((sctl & 0x0000003f) >> 0) + 2; |
144 | } |
145 | |
146 | if (sctl & 0x80000000) |
147 | return (sclk * 2) / sdiv; |
148 | |
149 | return sclk; |
150 | } |
151 | |
152 | static int |
153 | nvc0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) |
154 | { |
155 | struct nouveau_device *device = nv_device(clk); |
156 | struct nvc0_clock_priv *priv = (void *)clk; |
157 | |
158 | switch (src) { |
159 | case nv_clk_src_crystal: |
160 | return device->crystal; |
161 | case nv_clk_src_href: |
162 | return 100000; |
163 | case nv_clk_src_sppll0: |
164 | return read_pll(priv, 0x00e800); |
165 | case nv_clk_src_sppll1: |
166 | return read_pll(priv, 0x00e820); |
167 | |
168 | case nv_clk_src_mpllsrcref: |
169 | return read_div(priv, 0, 0x137320, 0x137330); |
170 | case nv_clk_src_mpllsrc: |
171 | return read_pll(priv, 0x132020); |
172 | case nv_clk_src_mpll: |
173 | return read_pll(priv, 0x132000); |
174 | case nv_clk_src_mdiv: |
175 | return read_div(priv, 0, 0x137300, 0x137310); |
176 | case nv_clk_src_mem: |
177 | if (nv_rd32(priv, 0x1373f0) & 0x00000002) |
178 | return clk->read(clk, nv_clk_src_mpll); |
179 | return clk->read(clk, nv_clk_src_mdiv); |
180 | |
181 | case nv_clk_src_gpc: |
182 | return read_clk(priv, 0x00); |
183 | case nv_clk_src_rop: |
184 | return read_clk(priv, 0x01); |
185 | case nv_clk_src_hubk07: |
186 | return read_clk(priv, 0x02); |
187 | case nv_clk_src_hubk06: |
188 | return read_clk(priv, 0x07); |
189 | case nv_clk_src_hubk01: |
190 | return read_clk(priv, 0x08); |
191 | case nv_clk_src_copy: |
192 | return read_clk(priv, 0x09); |
193 | case nv_clk_src_daemon: |
194 | return read_clk(priv, 0x0c); |
195 | case nv_clk_src_vdec: |
196 | return read_clk(priv, 0x0e); |
197 | default: |
198 | nv_error(clk, "invalid clock source %d\n" , src); |
199 | return -EINVAL; |
200 | } |
201 | } |
202 | |
203 | static u32 |
204 | calc_div(struct nvc0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) |
205 | { |
206 | u32 div = min((ref * 2) / freq, (u32)65); |
207 | if (div < 2) |
208 | div = 2; |
209 | |
210 | *ddiv = div - 2; |
211 | return (ref * 2) / div; |
212 | } |
213 | |
214 | static u32 |
215 | calc_src(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) |
216 | { |
217 | u32 sclk; |
218 | |
219 | /* use one of the fixed frequencies if possible */ |
220 | *ddiv = 0x00000000; |
221 | switch (freq) { |
222 | case 27000: |
223 | case 108000: |
224 | *dsrc = 0x00000000; |
225 | if (freq == 108000) |
226 | *dsrc |= 0x00030000; |
227 | return freq; |
228 | case 100000: |
229 | *dsrc = 0x00000002; |
230 | return freq; |
231 | default: |
232 | *dsrc = 0x00000003; |
233 | break; |
234 | } |
235 | |
236 | /* otherwise, calculate the closest divider */ |
237 | sclk = read_vco(priv, 0x137160 + (clk * 4)); |
238 | if (clk < 7) |
239 | sclk = calc_div(priv, clk, sclk, freq, ddiv); |
240 | return sclk; |
241 | } |
242 | |
243 | static u32 |
244 | calc_pll(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *coef) |
245 | { |
246 | struct nouveau_bios *bios = nouveau_bios(priv); |
247 | struct nvbios_pll limits; |
248 | int N, M, P, ret; |
249 | |
250 | ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits); |
251 | if (ret) |
252 | return 0; |
253 | |
254 | limits.refclk = read_div(priv, clk, 0x137120, 0x137140); |
255 | if (!limits.refclk) |
256 | return 0; |
257 | |
258 | ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P); |
259 | if (ret <= 0) |
260 | return 0; |
261 | |
262 | *coef = (P << 16) | (N << 8) | M; |
263 | return ret; |
264 | } |
265 | |
266 | static int |
267 | calc_clk(struct nvc0_clock_priv *priv, |
268 | struct nouveau_cstate *cstate, int clk, int dom) |
269 | { |
270 | struct nvc0_clock_info *info = &priv->eng[clk]; |
271 | u32 freq = cstate->domain[dom]; |
272 | u32 src0, div0, div1D, div1P = 0; |
273 | u32 clk0, clk1 = 0; |
274 | |
275 | /* invalid clock domain */ |
276 | if (!freq) |
277 | return 0; |
278 | |
279 | /* first possible path, using only dividers */ |
280 | clk0 = calc_src(priv, clk, freq, &src0, &div0); |
281 | clk0 = calc_div(priv, clk, clk0, freq, &div1D); |
282 | |
283 | /* see if we can get any closer using PLLs */ |
284 | if (clk0 != freq && (0x00004387 & (1 << clk))) { |
285 | if (clk <= 7) |
286 | clk1 = calc_pll(priv, clk, freq, &info->coef); |
287 | else |
288 | clk1 = cstate->domain[nv_clk_src_hubk06]; |
289 | clk1 = calc_div(priv, clk, clk1, freq, &div1P); |
290 | } |
291 | |
292 | /* select the method which gets closest to target freq */ |
293 | if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { |
294 | info->dsrc = src0; |
295 | if (div0) { |
296 | info->ddiv |= 0x80000000; |
297 | info->ddiv |= div0 << 8; |
298 | info->ddiv |= div0; |
299 | } |
300 | if (div1D) { |
301 | info->mdiv |= 0x80000000; |
302 | info->mdiv |= div1D; |
303 | } |
304 | info->ssel = info->coef = 0; |
305 | info->freq = clk0; |
306 | } else { |
307 | if (div1P) { |
308 | info->mdiv |= 0x80000000; |
309 | info->mdiv |= div1P << 8; |
310 | } |
311 | info->ssel = (1 << clk); |
312 | info->freq = clk1; |
313 | } |
314 | |
315 | return 0; |
316 | } |
317 | |
318 | static int |
319 | nvc0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) |
320 | { |
321 | struct nvc0_clock_priv *priv = (void *)clk; |
322 | int ret; |
323 | |
324 | if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) || |
325 | (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) || |
326 | (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) || |
327 | (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) || |
328 | (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) || |
329 | (ret = calc_clk(priv, cstate, 0x09, nv_clk_src_copy)) || |
330 | (ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) || |
331 | (ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec))) |
332 | return ret; |
333 | |
334 | return 0; |
335 | } |
336 | |
337 | static void |
338 | nvc0_clock_prog_0(struct nvc0_clock_priv *priv, int clk) |
339 | { |
340 | struct nvc0_clock_info *info = &priv->eng[clk]; |
341 | if (clk < 7 && !info->ssel) { |
342 | nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv); |
343 | nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); |
344 | } |
345 | } |
346 | |
347 | static void |
348 | nvc0_clock_prog_1(struct nvc0_clock_priv *priv, int clk) |
349 | { |
350 | nv_mask(priv, 0x137100, (1 << clk), 0x00000000); |
351 | nv_wait(priv, 0x137100, (1 << clk), 0x00000000); |
352 | } |
353 | |
354 | static void |
355 | nvc0_clock_prog_2(struct nvc0_clock_priv *priv, int clk) |
356 | { |
357 | struct nvc0_clock_info *info = &priv->eng[clk]; |
358 | const u32 addr = 0x137000 + (clk * 0x20); |
359 | if (clk <= 7) { |
360 | nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000); |
361 | nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000); |
362 | if (info->coef) { |
363 | nv_wr32(priv, addr + 0x04, info->coef); |
364 | nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001); |
365 | nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000); |
366 | nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004); |
367 | } |
368 | } |
369 | } |
370 | |
371 | static void |
372 | nvc0_clock_prog_3(struct nvc0_clock_priv *priv, int clk) |
373 | { |
374 | struct nvc0_clock_info *info = &priv->eng[clk]; |
375 | if (info->ssel) { |
376 | nv_mask(priv, 0x137100, (1 << clk), info->ssel); |
377 | nv_wait(priv, 0x137100, (1 << clk), info->ssel); |
378 | } |
379 | } |
380 | |
381 | static void |
382 | nvc0_clock_prog_4(struct nvc0_clock_priv *priv, int clk) |
383 | { |
384 | struct nvc0_clock_info *info = &priv->eng[clk]; |
385 | nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); |
386 | } |
387 | |
388 | static int |
389 | nvc0_clock_prog(struct nouveau_clock *clk) |
390 | { |
391 | struct nvc0_clock_priv *priv = (void *)clk; |
392 | struct { |
393 | void (*exec)(struct nvc0_clock_priv *, int); |
394 | } stage[] = { |
395 | { nvc0_clock_prog_0 }, /* div programming */ |
396 | { nvc0_clock_prog_1 }, /* select div mode */ |
397 | { nvc0_clock_prog_2 }, /* (maybe) program pll */ |
398 | { nvc0_clock_prog_3 }, /* (maybe) select pll mode */ |
399 | { nvc0_clock_prog_4 }, /* final divider */ |
400 | }; |
401 | int i, j; |
402 | |
403 | for (i = 0; i < ARRAY_SIZE(stage); i++) { |
404 | for (j = 0; j < ARRAY_SIZE(priv->eng); j++) { |
405 | if (!priv->eng[j].freq) |
406 | continue; |
407 | stage[i].exec(priv, j); |
408 | } |
409 | } |
410 | |
411 | return 0; |
412 | } |
413 | |
414 | static void |
415 | nvc0_clock_tidy(struct nouveau_clock *clk) |
416 | { |
417 | struct nvc0_clock_priv *priv = (void *)clk; |
418 | memset(priv->eng, 0x00, sizeof(priv->eng)); |
419 | } |
420 | |
421 | static struct nouveau_clocks |
422 | nvc0_domain[] = { |
423 | { nv_clk_src_crystal, 0xff }, |
424 | { nv_clk_src_href , 0xff }, |
425 | { nv_clk_src_hubk06 , 0x00 }, |
426 | { nv_clk_src_hubk01 , 0x01 }, |
427 | { nv_clk_src_copy , 0x02 }, |
428 | { nv_clk_src_gpc , 0x03, 0, "core" , 2000 }, |
429 | { nv_clk_src_rop , 0x04 }, |
430 | { nv_clk_src_mem , 0x05, 0, "memory" , 1000 }, |
431 | { nv_clk_src_vdec , 0x06 }, |
432 | { nv_clk_src_daemon , 0x0a }, |
433 | { nv_clk_src_hubk07 , 0x0b }, |
434 | { nv_clk_src_max } |
435 | }; |
436 | |
437 | static int |
438 | nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
439 | struct nouveau_oclass *oclass, void *data, u32 size, |
440 | struct nouveau_object **pobject) |
441 | { |
442 | struct nvc0_clock_priv *priv; |
443 | int ret; |
444 | |
445 | ret = nouveau_clock_create(parent, engine, oclass, nvc0_domain, &priv); |
446 | *pobject = nv_object(priv); |
447 | if (ret) |
448 | return ret; |
449 | |
450 | priv->base.read = nvc0_clock_read; |
451 | priv->base.calc = nvc0_clock_calc; |
452 | priv->base.prog = nvc0_clock_prog; |
453 | priv->base.tidy = nvc0_clock_tidy; |
454 | return 0; |
455 | } |
456 | |
457 | struct nouveau_oclass |
458 | nvc0_clock_oclass = { |
459 | .handle = NV_SUBDEV(CLOCK, 0xc0), |
460 | .ofuncs = &(struct nouveau_ofuncs) { |
461 | .ctor = nvc0_clock_ctor, |
462 | .dtor = _nouveau_clock_dtor, |
463 | .init = _nouveau_clock_init, |
464 | .fini = _nouveau_clock_fini, |
465 | }, |
466 | }; |
467 | |