1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Christian König. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Christian König |
25 | */ |
26 | #include <linux/hdmi.h> |
27 | #include <linux/gcd.h> |
28 | #include <drm/drmP.h> |
29 | #include <drm/radeon_drm.h> |
30 | #include "radeon.h" |
31 | #include "radeon_asic.h" |
32 | #include "r600d.h" |
33 | #include "atom.h" |
34 | |
35 | /* |
36 | * HDMI color format |
37 | */ |
38 | enum r600_hdmi_color_format { |
39 | RGB = 0, |
40 | YCC_422 = 1, |
41 | YCC_444 = 2 |
42 | }; |
43 | |
44 | /* |
45 | * IEC60958 status bits |
46 | */ |
47 | enum r600_hdmi_iec_status_bits { |
48 | AUDIO_STATUS_DIG_ENABLE = 0x01, |
49 | AUDIO_STATUS_V = 0x02, |
50 | AUDIO_STATUS_VCFG = 0x04, |
51 | AUDIO_STATUS_EMPHASIS = 0x08, |
52 | AUDIO_STATUS_COPYRIGHT = 0x10, |
53 | AUDIO_STATUS_NONAUDIO = 0x20, |
54 | AUDIO_STATUS_PROFESSIONAL = 0x40, |
55 | AUDIO_STATUS_LEVEL = 0x80 |
56 | }; |
57 | |
58 | static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { |
59 | /* 32kHz 44.1kHz 48kHz */ |
60 | /* Clock N CTS N CTS N CTS */ |
61 | { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */ |
62 | { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ |
63 | { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ |
64 | { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ |
65 | { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ |
66 | { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ |
67 | { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */ |
68 | { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ |
69 | { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */ |
70 | { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ |
71 | }; |
72 | |
73 | |
74 | /* |
75 | * calculate CTS and N values if they are not found in the table |
76 | */ |
77 | static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq) |
78 | { |
79 | int n, cts; |
80 | unsigned long div, mul; |
81 | |
82 | /* Safe, but overly large values */ |
83 | n = 128 * freq; |
84 | cts = clock * 1000; |
85 | |
86 | /* Smallest valid fraction */ |
87 | div = gcd(n, cts); |
88 | |
89 | n /= div; |
90 | cts /= div; |
91 | |
92 | /* |
93 | * The optimal N is 128*freq/1000. Calculate the closest larger |
94 | * value that doesn't truncate any bits. |
95 | */ |
96 | mul = ((128*freq/1000) + (n-1))/n; |
97 | |
98 | n *= mul; |
99 | cts *= mul; |
100 | |
101 | /* Check that we are in spec (not always possible) */ |
102 | if (n < (128*freq/1500)) |
103 | printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n" ); |
104 | if (n > (128*freq/300)) |
105 | printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n" ); |
106 | |
107 | *N = n; |
108 | *CTS = cts; |
109 | |
110 | DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n" , |
111 | *N, *CTS, freq); |
112 | } |
113 | |
114 | struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) |
115 | { |
116 | struct radeon_hdmi_acr res; |
117 | u8 i; |
118 | |
119 | /* Precalculated values for common clocks */ |
120 | for (i = 0; i < ARRAY_SIZE(r600_hdmi_predefined_acr); i++) { |
121 | if (r600_hdmi_predefined_acr[i].clock == clock) |
122 | return r600_hdmi_predefined_acr[i]; |
123 | } |
124 | |
125 | /* And odd clocks get manually calculated */ |
126 | r600_hdmi_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000); |
127 | r600_hdmi_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100); |
128 | r600_hdmi_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000); |
129 | |
130 | return res; |
131 | } |
132 | |
133 | /* |
134 | * update the N and CTS parameters for a given pixel clock rate |
135 | */ |
136 | static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
137 | { |
138 | struct drm_device *dev = encoder->dev; |
139 | struct radeon_device *rdev = dev->dev_private; |
140 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
141 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
142 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
143 | uint32_t offset = dig->afmt->offset; |
144 | |
145 | WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz)); |
146 | WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz); |
147 | |
148 | WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz)); |
149 | WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz); |
150 | |
151 | WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz)); |
152 | WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz); |
153 | } |
154 | |
155 | /* |
156 | * build a HDMI Video Info Frame |
157 | */ |
158 | static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, |
159 | void *buffer, size_t size) |
160 | { |
161 | struct drm_device *dev = encoder->dev; |
162 | struct radeon_device *rdev = dev->dev_private; |
163 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
164 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
165 | uint32_t offset = dig->afmt->offset; |
166 | const uint8_t *frame = (const uint8_t *)buffer + 3; |
167 | uint8_t * = buffer; |
168 | |
169 | WREG32(HDMI0_AVI_INFO0 + offset, |
170 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
171 | WREG32(HDMI0_AVI_INFO1 + offset, |
172 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
173 | WREG32(HDMI0_AVI_INFO2 + offset, |
174 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
175 | WREG32(HDMI0_AVI_INFO3 + offset, |
176 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); |
177 | } |
178 | |
179 | /* |
180 | * build a Audio Info Frame |
181 | */ |
182 | static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, |
183 | const void *buffer, size_t size) |
184 | { |
185 | struct drm_device *dev = encoder->dev; |
186 | struct radeon_device *rdev = dev->dev_private; |
187 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
188 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
189 | uint32_t offset = dig->afmt->offset; |
190 | const u8 *frame = (const u8 *)buffer + 3; |
191 | |
192 | WREG32(HDMI0_AUDIO_INFO0 + offset, |
193 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
194 | WREG32(HDMI0_AUDIO_INFO1 + offset, |
195 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); |
196 | } |
197 | |
198 | /* |
199 | * test if audio buffer is filled enough to start playing |
200 | */ |
201 | static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) |
202 | { |
203 | struct drm_device *dev = encoder->dev; |
204 | struct radeon_device *rdev = dev->dev_private; |
205 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
206 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
207 | uint32_t offset = dig->afmt->offset; |
208 | |
209 | return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; |
210 | } |
211 | |
212 | /* |
213 | * have buffer status changed since last call? |
214 | */ |
215 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) |
216 | { |
217 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
218 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
219 | int status, result; |
220 | |
221 | if (!dig->afmt || !dig->afmt->enabled) |
222 | return 0; |
223 | |
224 | status = r600_hdmi_is_audio_buffer_filled(encoder); |
225 | result = dig->afmt->last_buffer_filled_status != status; |
226 | dig->afmt->last_buffer_filled_status = status; |
227 | |
228 | return result; |
229 | } |
230 | |
231 | /* |
232 | * write the audio workaround status to the hardware |
233 | */ |
234 | static void r600_hdmi_audio_workaround(struct drm_encoder *encoder) |
235 | { |
236 | struct drm_device *dev = encoder->dev; |
237 | struct radeon_device *rdev = dev->dev_private; |
238 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
239 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
240 | uint32_t offset = dig->afmt->offset; |
241 | bool hdmi_audio_workaround = false; /* FIXME */ |
242 | u32 value; |
243 | |
244 | if (!hdmi_audio_workaround || |
245 | r600_hdmi_is_audio_buffer_filled(encoder)) |
246 | value = 0; /* disable workaround */ |
247 | else |
248 | value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ |
249 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, |
250 | value, ~HDMI0_AUDIO_TEST_EN); |
251 | } |
252 | |
253 | static void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
254 | { |
255 | struct drm_device *dev = encoder->dev; |
256 | struct radeon_device *rdev = dev->dev_private; |
257 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
258 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
259 | u32 base_rate = 24000; |
260 | u32 max_ratio = clock / base_rate; |
261 | u32 dto_phase; |
262 | u32 dto_modulo = clock; |
263 | u32 wallclock_ratio; |
264 | u32 dto_cntl; |
265 | |
266 | if (!dig || !dig->afmt) |
267 | return; |
268 | |
269 | if (max_ratio >= 8) { |
270 | dto_phase = 192 * 1000; |
271 | wallclock_ratio = 3; |
272 | } else if (max_ratio >= 4) { |
273 | dto_phase = 96 * 1000; |
274 | wallclock_ratio = 2; |
275 | } else if (max_ratio >= 2) { |
276 | dto_phase = 48 * 1000; |
277 | wallclock_ratio = 1; |
278 | } else { |
279 | dto_phase = 24 * 1000; |
280 | wallclock_ratio = 0; |
281 | } |
282 | |
283 | /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. |
284 | * doesn't matter which one you use. Just use the first one. |
285 | */ |
286 | /* XXX two dtos; generally use dto0 for hdmi */ |
287 | /* Express [24MHz / target pixel clock] as an exact rational |
288 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
289 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
290 | */ |
291 | if (ASIC_IS_DCE32(rdev)) { |
292 | if (dig->dig_encoder == 0) { |
293 | dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
294 | dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
295 | WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); |
296 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
297 | WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); |
298 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ |
299 | } else { |
300 | dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
301 | dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
302 | WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl); |
303 | WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase); |
304 | WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo); |
305 | WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ |
306 | } |
307 | } else { |
308 | /* according to the reg specs, this should DCE3.2 only, but in |
309 | * practice it seems to cover DCE2.0/3.0/3.1 as well. |
310 | */ |
311 | if (dig->dig_encoder == 0) { |
312 | WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); |
313 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); |
314 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ |
315 | } else { |
316 | WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100); |
317 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); |
318 | WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ |
319 | } |
320 | } |
321 | } |
322 | |
323 | static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder) |
324 | { |
325 | struct radeon_device *rdev = encoder->dev->dev_private; |
326 | struct drm_connector *connector; |
327 | struct radeon_connector *radeon_connector = NULL; |
328 | u32 tmp; |
329 | u8 *sadb; |
330 | int sad_count; |
331 | |
332 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
333 | if (connector->encoder == encoder) { |
334 | radeon_connector = to_radeon_connector(connector); |
335 | break; |
336 | } |
337 | } |
338 | |
339 | if (!radeon_connector) { |
340 | DRM_ERROR("Couldn't find encoder's connector\n" ); |
341 | return; |
342 | } |
343 | |
344 | sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb); |
345 | if (sad_count < 0) { |
346 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n" , sad_count); |
347 | return; |
348 | } |
349 | |
350 | /* program the speaker allocation */ |
351 | tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
352 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
353 | /* set HDMI mode */ |
354 | tmp |= HDMI_CONNECTION; |
355 | if (sad_count) |
356 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
357 | else |
358 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
359 | WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
360 | |
361 | kfree(sadb); |
362 | } |
363 | |
364 | static void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder) |
365 | { |
366 | struct radeon_device *rdev = encoder->dev->dev_private; |
367 | struct drm_connector *connector; |
368 | struct radeon_connector *radeon_connector = NULL; |
369 | struct cea_sad *sads; |
370 | int i, sad_count; |
371 | |
372 | static const u16 eld_reg_to_type[][2] = { |
373 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
374 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
375 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
376 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
377 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
378 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
379 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
380 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
381 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
382 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
383 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
384 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
385 | }; |
386 | |
387 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
388 | if (connector->encoder == encoder) { |
389 | radeon_connector = to_radeon_connector(connector); |
390 | break; |
391 | } |
392 | } |
393 | |
394 | if (!radeon_connector) { |
395 | DRM_ERROR("Couldn't find encoder's connector\n" ); |
396 | return; |
397 | } |
398 | |
399 | sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); |
400 | if (sad_count < 0) { |
401 | DRM_ERROR("Couldn't read SADs: %d\n" , sad_count); |
402 | return; |
403 | } |
404 | BUG_ON(!sads); |
405 | |
406 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
407 | u32 value = 0; |
408 | u8 stereo_freqs = 0; |
409 | int max_channels = -1; |
410 | int j; |
411 | |
412 | for (j = 0; j < sad_count; j++) { |
413 | struct cea_sad *sad = &sads[j]; |
414 | |
415 | if (sad->format == eld_reg_to_type[i][1]) { |
416 | if (sad->channels > max_channels) { |
417 | value = MAX_CHANNELS(sad->channels) | |
418 | DESCRIPTOR_BYTE_2(sad->byte2) | |
419 | SUPPORTED_FREQUENCIES(sad->freq); |
420 | max_channels = sad->channels; |
421 | } |
422 | |
423 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
424 | stereo_freqs |= sad->freq; |
425 | else |
426 | break; |
427 | } |
428 | } |
429 | |
430 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); |
431 | |
432 | WREG32(eld_reg_to_type[i][0], value); |
433 | } |
434 | |
435 | kfree(sads); |
436 | } |
437 | |
438 | /* |
439 | * update the info frames with the data from the current display mode |
440 | */ |
441 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
442 | { |
443 | struct drm_device *dev = encoder->dev; |
444 | struct radeon_device *rdev = dev->dev_private; |
445 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
446 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
447 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
448 | struct hdmi_avi_infoframe frame; |
449 | uint32_t offset; |
450 | ssize_t err; |
451 | |
452 | if (!dig || !dig->afmt) |
453 | return; |
454 | |
455 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
456 | if (!dig->afmt->enabled) |
457 | return; |
458 | offset = dig->afmt->offset; |
459 | |
460 | /* disable audio prior to setting up hw */ |
461 | dig->afmt->pin = r600_audio_get_pin(rdev); |
462 | r600_audio_enable(rdev, dig->afmt->pin, false); |
463 | |
464 | r600_audio_set_dto(encoder, mode->clock); |
465 | |
466 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
467 | HDMI0_NULL_SEND); /* send null packets when required */ |
468 | |
469 | WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); |
470 | |
471 | if (ASIC_IS_DCE32(rdev)) { |
472 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, |
473 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ |
474 | HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
475 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, |
476 | AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ |
477 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
478 | } else { |
479 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, |
480 | HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ |
481 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ |
482 | HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ |
483 | HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
484 | } |
485 | |
486 | if (ASIC_IS_DCE32(rdev)) { |
487 | dce3_2_afmt_write_speaker_allocation(encoder); |
488 | dce3_2_afmt_write_sad_regs(encoder); |
489 | } |
490 | |
491 | WREG32(HDMI0_ACR_PACKET_CONTROL + offset, |
492 | HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */ |
493 | HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
494 | |
495 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
496 | HDMI0_NULL_SEND | /* send null packets when required */ |
497 | HDMI0_GC_SEND | /* send general control packets */ |
498 | HDMI0_GC_CONT); /* send general control packets every frame */ |
499 | |
500 | /* TODO: HDMI0_AUDIO_INFO_UPDATE */ |
501 | WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, |
502 | HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ |
503 | HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ |
504 | HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
505 | HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ |
506 | |
507 | WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, |
508 | HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ |
509 | HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
510 | |
511 | WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */ |
512 | |
513 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
514 | if (err < 0) { |
515 | DRM_ERROR("failed to setup AVI infoframe: %zd\n" , err); |
516 | return; |
517 | } |
518 | |
519 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
520 | if (err < 0) { |
521 | DRM_ERROR("failed to pack AVI infoframe: %zd\n" , err); |
522 | return; |
523 | } |
524 | |
525 | r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
526 | r600_hdmi_update_ACR(encoder, mode->clock); |
527 | |
528 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
529 | WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
530 | WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); |
531 | WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); |
532 | WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); |
533 | |
534 | r600_hdmi_audio_workaround(encoder); |
535 | |
536 | /* enable audio after to setting up hw */ |
537 | r600_audio_enable(rdev, dig->afmt->pin, true); |
538 | } |
539 | |
540 | /* |
541 | * update settings with current parameters from audio engine |
542 | */ |
543 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) |
544 | { |
545 | struct drm_device *dev = encoder->dev; |
546 | struct radeon_device *rdev = dev->dev_private; |
547 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
548 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
549 | struct r600_audio_pin audio = r600_audio_status(rdev); |
550 | uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; |
551 | struct hdmi_audio_infoframe frame; |
552 | uint32_t offset; |
553 | uint32_t iec; |
554 | ssize_t err; |
555 | |
556 | if (!dig->afmt || !dig->afmt->enabled) |
557 | return; |
558 | offset = dig->afmt->offset; |
559 | |
560 | DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n" , |
561 | r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped" , |
562 | audio.channels, audio.rate, audio.bits_per_sample); |
563 | DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n" , |
564 | (int)audio.status_bits, (int)audio.category_code); |
565 | |
566 | iec = 0; |
567 | if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL) |
568 | iec |= 1 << 0; |
569 | if (audio.status_bits & AUDIO_STATUS_NONAUDIO) |
570 | iec |= 1 << 1; |
571 | if (audio.status_bits & AUDIO_STATUS_COPYRIGHT) |
572 | iec |= 1 << 2; |
573 | if (audio.status_bits & AUDIO_STATUS_EMPHASIS) |
574 | iec |= 1 << 3; |
575 | |
576 | iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code); |
577 | |
578 | switch (audio.rate) { |
579 | case 32000: |
580 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3); |
581 | break; |
582 | case 44100: |
583 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0); |
584 | break; |
585 | case 48000: |
586 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2); |
587 | break; |
588 | case 88200: |
589 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8); |
590 | break; |
591 | case 96000: |
592 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa); |
593 | break; |
594 | case 176400: |
595 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc); |
596 | break; |
597 | case 192000: |
598 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe); |
599 | break; |
600 | } |
601 | |
602 | WREG32(HDMI0_60958_0 + offset, iec); |
603 | |
604 | iec = 0; |
605 | switch (audio.bits_per_sample) { |
606 | case 16: |
607 | iec |= HDMI0_60958_CS_WORD_LENGTH(0x2); |
608 | break; |
609 | case 20: |
610 | iec |= HDMI0_60958_CS_WORD_LENGTH(0x3); |
611 | break; |
612 | case 24: |
613 | iec |= HDMI0_60958_CS_WORD_LENGTH(0xb); |
614 | break; |
615 | } |
616 | if (audio.status_bits & AUDIO_STATUS_V) |
617 | iec |= 0x5 << 16; |
618 | WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f); |
619 | |
620 | err = hdmi_audio_infoframe_init(&frame); |
621 | if (err < 0) { |
622 | DRM_ERROR("failed to setup audio infoframe\n" ); |
623 | return; |
624 | } |
625 | |
626 | frame.channels = audio.channels; |
627 | |
628 | err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); |
629 | if (err < 0) { |
630 | DRM_ERROR("failed to pack audio infoframe\n" ); |
631 | return; |
632 | } |
633 | |
634 | r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); |
635 | r600_hdmi_audio_workaround(encoder); |
636 | } |
637 | |
638 | /* |
639 | * enable the HDMI engine |
640 | */ |
641 | void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) |
642 | { |
643 | struct drm_device *dev = encoder->dev; |
644 | struct radeon_device *rdev = dev->dev_private; |
645 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
646 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
647 | u32 hdmi = HDMI0_ERROR_ACK; |
648 | |
649 | if (!dig || !dig->afmt) |
650 | return; |
651 | |
652 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
653 | if (enable && dig->afmt->enabled) |
654 | return; |
655 | if (!enable && !dig->afmt->enabled) |
656 | return; |
657 | |
658 | /* Older chipsets require setting HDMI and routing manually */ |
659 | if (!ASIC_IS_DCE3(rdev)) { |
660 | if (enable) |
661 | hdmi |= HDMI0_ENABLE; |
662 | switch (radeon_encoder->encoder_id) { |
663 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
664 | if (enable) { |
665 | WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); |
666 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); |
667 | } else { |
668 | WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); |
669 | } |
670 | break; |
671 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
672 | if (enable) { |
673 | WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); |
674 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); |
675 | } else { |
676 | WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); |
677 | } |
678 | break; |
679 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
680 | if (enable) { |
681 | WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); |
682 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); |
683 | } else { |
684 | WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); |
685 | } |
686 | break; |
687 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
688 | if (enable) |
689 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); |
690 | break; |
691 | default: |
692 | dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n" , |
693 | radeon_encoder->encoder_id); |
694 | break; |
695 | } |
696 | WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); |
697 | } |
698 | |
699 | if (rdev->irq.installed) { |
700 | /* if irq is available use it */ |
701 | /* XXX: shouldn't need this on any asics. Double check DCE2/3 */ |
702 | if (enable) |
703 | radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); |
704 | else |
705 | radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); |
706 | } |
707 | |
708 | dig->afmt->enabled = enable; |
709 | |
710 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n" , |
711 | enable ? "En" : "Dis" , dig->afmt->offset, radeon_encoder->encoder_id); |
712 | } |
713 | |
714 | |