1 | /* $NetBSD: if_stereg.h,v 1.5 2008/04/28 20:23:55 martin Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 2001 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Jason R. Thorpe. |
9 | * |
10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions |
12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. |
15 | * 2. Redistributions in binary form must reproduce the above copyright |
16 | * notice, this list of conditions and the following disclaimer in the |
17 | * documentation and/or other materials provided with the distribution. |
18 | * |
19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
29 | * POSSIBILITY OF SUCH DAMAGE. |
30 | */ |
31 | |
32 | #ifndef _DEV_PCI_IF_STEREG_H_ |
33 | #define _DEV_PCI_IF_STEREG_H_ |
34 | |
35 | /* |
36 | * Register description for the Sundance Tech. ST-201 10/100 |
37 | * Ethernet controller. |
38 | */ |
39 | |
40 | /* |
41 | * ST-201 buffer fragment descriptor. |
42 | */ |
43 | struct ste_frag { |
44 | uint32_t frag_addr; /* buffer address */ |
45 | uint32_t frag_len; /* buffer length */ |
46 | } __packed; |
47 | |
48 | #define FRAG_LEN 0x00001fff /* length mask */ |
49 | #define FRAG_LAST (1U << 31) /* last frag in list */ |
50 | |
51 | /* |
52 | * ST-201 Transmit Frame Descriptor. Note the number of fragments |
53 | * here is arbitrary, but we can't exceed 512 bytes of TFD. |
54 | */ |
55 | #define STE_NTXFRAGS 16 |
56 | struct ste_tfd { |
57 | uint32_t tfd_next; /* next TFD in list */ |
58 | uint32_t tfd_control; /* control bits */ |
59 | /* the buffer fragments */ |
60 | struct ste_frag tfd_frags[STE_NTXFRAGS]; |
61 | } __packed; |
62 | |
63 | #define TFD_WordAlign_dword 0 /* align to dword in TxFIFO */ |
64 | #define TFD_WordAlign_word 2 /* align to word in TxFIFO */ |
65 | #define TFD_WordAlign_disable 1 /* disable alignment */ |
66 | #define TFD_FrameId(x) ((x) << 2) |
67 | #define TFD_FrameId_MAX 0xff |
68 | #define TFD_FcsAppendDisable (1U << 13) |
69 | #define TFD_TxIndicate (1U << 15) |
70 | #define TFD_TxDMAComplete (1U << 16) |
71 | #define TFD_TxDMAIndicate (1U << 31) |
72 | |
73 | /* |
74 | * ST-201 Receive Frame Descriptor. Note the number of fragments |
75 | * here is arbitrary (we only use one), but we can't exceed 512 |
76 | * bytes of RFD. |
77 | */ |
78 | struct ste_rfd { |
79 | uint32_t rfd_next; /* next RFD in list */ |
80 | uint32_t rfd_status; /* status bits */ |
81 | struct ste_frag rfd_frag; /* the buffer */ |
82 | } __packed; |
83 | |
84 | #define RFD_RxDMAFrameLen(x) ((x) & FRAG_LEN) |
85 | #define RFD_RxFrameError (1U << 14) |
86 | #define RFD_RxDMAComplete (1U << 15) |
87 | #define RFD_RxFIFOOverrun (1U << 16) |
88 | #define RFD_RxRuntFrame (1U << 17) |
89 | #define RFD_RxAlignmentError (1U << 18) |
90 | #define RFD_RxFCSError (1U << 19) |
91 | #define RFD_RxOversizedFrame (1U << 20) |
92 | #define RFD_DribbleBits (1U << 23) |
93 | #define RFD_RxDMAOverflow (1U << 24) |
94 | #define RFD_ImpliedBufferEnable (1U << 28) |
95 | |
96 | /* |
97 | * PCI configuration registers used by the ST-201. |
98 | */ |
99 | |
100 | #define STE_PCI_IOBA (PCI_MAPREG_START + 0x00) |
101 | #define STE_PCI_MMBA (PCI_MAPREG_START + 0x04) |
102 | |
103 | /* |
104 | * EEPROM offsets. |
105 | */ |
106 | #define STE_EEPROM_ConfigParam 0x00 |
107 | #define STE_EEPROM_AsicCtrl 0x02 |
108 | #define STE_EEPROM_SubSystemVendorId 0x04 |
109 | #define STE_EEPROM_SubSystemId 0x06 |
110 | #define STE_EEPROM_StationAddress0 0x10 |
111 | #define STE_EEPROM_StationAddress1 0x12 |
112 | #define STE_EEPROM_StationAddress2 0x14 |
113 | |
114 | /* |
115 | * The ST-201 register space. |
116 | */ |
117 | |
118 | #define STE_DMACtrl 0x00 /* 32-bit */ |
119 | #define DC_RxDMAHalted (1U << 0) |
120 | #define DC_TxDMACmplReq (1U << 1) |
121 | #define DC_TxDMAHalted (1U << 2) |
122 | #define DC_RxDMAComplete (1U << 3) |
123 | #define DC_TxDMAComplete (1U << 4) |
124 | #define DC_RxDMAHalt (1U << 8) |
125 | #define DC_RxDMAResume (1U << 9) |
126 | #define DC_TxDMAHalt (1U << 10) |
127 | #define DC_TxDMAResume (1U << 11) |
128 | #define DC_TxDMAInProg (1U << 14) |
129 | #define DC_DMAHaltBusy (1U << 15) |
130 | #define DC_RxEarlyEnable (1U << 17) |
131 | #define DC_CountdownSpeed (1U << 18) |
132 | #define DC_CountdownMode (1U << 19) |
133 | #define DC_MWIDisable (1U << 20) |
134 | #define DC_RxDMAOverrunFrame (1U << 22) |
135 | #define DC_CountdownIntEnable (1U << 23) |
136 | #define DC_TargetAbort (1U << 30) |
137 | #define DC_MasterAbort (1U << 31) |
138 | |
139 | #define STE_TxDMAListPtr 0x04 /* 32-bit */ |
140 | |
141 | #define STE_TxDMABurstThresh 0x08 /* 8-bit */ |
142 | |
143 | #define STE_TxDMAUrgentThresh 0x09 /* 8-bit */ |
144 | |
145 | #define STE_TxDMAPollPeriod 0x0a /* 8-bit */ |
146 | |
147 | #define STE_RxDMAStatus 0x0c /* 32-bit */ |
148 | #define RDS_RxDMAFrameLen(x) ((x) & 0x1fff) |
149 | #define RDS_RxFrameError (1U << 14) |
150 | #define RDS_RxDMAComplete (1U << 15) |
151 | #define RDS_RxFIFOOverrun (1U << 16) |
152 | #define RDS_RxRuntFrame (1U << 17) |
153 | #define RDS_RxAlignmentError (1U << 18) |
154 | #define RDS_RxFCSError (1U << 19) |
155 | #define RDS_RxOversizedFrame (1U << 20) |
156 | #define RDS_DribbleBits (1U << 23) |
157 | #define RDS_RxDMAOverflow (1U << 24) |
158 | |
159 | #define STE_RxDMAListPtr 0x10 /* 32-bit */ |
160 | |
161 | #define STE_RxDMABurstThresh 0x14 /* 8-bit */ |
162 | |
163 | #define STE_RxDMAUrgentThresh 0x15 /* 8-bit */ |
164 | |
165 | #define STE_RxDMAPollPeriod 0x16 /* 8-bit */ |
166 | |
167 | #define STE_DebugCtrl 0x1a /* 16-bit */ |
168 | #define DC_GPIO0Ctrl (1U << 0) /* 1 = input */ |
169 | #define DC_GPIO1Ctrl (1U << 1) /* 1 = input */ |
170 | #define DC_GPIO0 (1U << 2) |
171 | #define DC_GPIO1 (1U << 3) |
172 | |
173 | #define STE_AsicCtrl 0x30 /* 32-bit */ |
174 | #define AC_ExpRomSize (1U << 1) /* 0 = 32K, 1 = 64K */ |
175 | #define AC_TxLargeEnable (1U << 2) /* > 2K */ |
176 | #define AC_RxLargeEnable (1U << 3) /* > 2K */ |
177 | #define AC_ExpRomDisable (1U << 4) |
178 | #define AC_PhySpeed10 (1U << 5) |
179 | #define AC_PhySpeed100 (1U << 6) |
180 | #define AC_PhyMedia(x) (((x) >> 7) & 0x7) |
181 | #define AC_PhyMedia_10T 1 |
182 | #define AC_PhyMedia_100T 2 |
183 | #define AC_PhyMedia_10_100T 3 |
184 | #define AC_PhyMedia_10F 5 |
185 | #define AC_PhyMedia_100F 6 |
186 | #define AC_PhyMedia_10_100F 7 |
187 | #define AC_ForcedConfig(x) (((x) >> 8) & 0x7) |
188 | #define AC_D3ResetDisable (1U << 11) |
189 | #define AC_SpeedupMode (1U << 13) |
190 | #define AC_LEDMode (1U << 14) |
191 | #define AC_RstOutPolarity (1U << 15) |
192 | #define AC_GlobalReset (1U << 16) |
193 | #define AC_RxReset (1U << 17) |
194 | #define AC_TxReset (1U << 18) |
195 | #define AC_DMA (1U << 19) |
196 | #define AC_FIFO (1U << 20) |
197 | #define AC_Network (1U << 21) |
198 | #define AC_Host (1U << 22) |
199 | #define AC_AutoInit (1U << 23) |
200 | #define AC_RstOut (1U << 24) |
201 | #define AC_InterruptRequest (1U << 25) |
202 | #define AC_ResetBusy (1U << 26) |
203 | |
204 | #define STE_EepromData 0x34 /* 16-bit */ |
205 | |
206 | #define STE_EepromCtrl 0x36 /* 16-bit */ |
207 | #define EC_EepromAddress(x) ((x) & 0xff) |
208 | #define EC_EepromOpcode(x) ((x) << 8) |
209 | #define EC_OP_WE 0 |
210 | #define EC_OP_W 1 |
211 | #define EC_OP_R 2 |
212 | #define EC_OP_E 3 |
213 | #define EC_EepromBusy (1U << 15) |
214 | |
215 | #define STE_FIFOCtrl 0x3a /* 16-bit */ |
216 | #define FC_RAMTestMode (1U << 0) |
217 | #define FC_RxOverrunFrame (1U << 9) |
218 | #define FC_RxFIFOFull (1U << 11) |
219 | #define FC_Transmitting (1U << 14) |
220 | #define FC_Receiving (1U << 15) |
221 | |
222 | #define STE_TxStartThresh 0x3c /* 16-bit */ |
223 | |
224 | #define STE_RxEarlyThresh 0x3e /* 16-bit */ |
225 | |
226 | #define STE_ExpRomAddr 0x40 /* 32-bit */ |
227 | |
228 | #define STE_ExpRomData 0x44 /* 8-bit */ |
229 | |
230 | #define STE_WakeEvent 0x45 /* 8-bit */ |
231 | #define WE_WakePktEnable (1U << 0) |
232 | #define WE_MagicPktEnable (1U << 1) |
233 | #define WE_LinkEventEnable (1U << 2) |
234 | #define WE_WakePolarity (1U << 3) |
235 | #define WE_WakePktEvent (1U << 4) |
236 | #define WE_MagicPktEvent (1U << 5) |
237 | #define WE_LinkEvent (1U << 6) |
238 | #define WE_WakeOnLanEnable (1U << 7) |
239 | |
240 | #define STE_TxStatus 0x46 /* 8-bit */ |
241 | #define TS_TxReleaseError (1U << 1) |
242 | #define TS_TxStatusOverflow (1U << 2) |
243 | #define TS_MaxCollisions (1U << 3) |
244 | #define TS_TxUnderrun (1U << 4) |
245 | #define TS_TxIndicateReqd (1U << 6) |
246 | #define TS_TxComplete (1U << 7) |
247 | |
248 | #define STE_TxFrameId 0x47 /* 8-bit */ |
249 | |
250 | #define STE_Countdown 0x48 /* 16-bit */ |
251 | |
252 | #define STE_IntStatusAck 0x4a /* 16-bit */ |
253 | |
254 | #define STE_IntEnable 0x4c /* 16-bit */ |
255 | #define IE_HostError (1U << 1) |
256 | #define IE_TxComplete (1U << 2) |
257 | #define IE_MACControlFrame (1U << 3) |
258 | #define IE_RxComplete (1U << 4) |
259 | #define IE_RxEarly (1U << 5) |
260 | #define IE_IntRequested (1U << 6) |
261 | #define IE_UpdateStats (1U << 7) |
262 | #define IE_LinkEvent (1U << 8) |
263 | #define IE_TxDMAComplete (1U << 9) |
264 | #define IE_RxDMAComplete (1U << 10) |
265 | |
266 | #define STE_IntStatus 0x4e /* 16-bit */ |
267 | #define IS_InterruptStatus (1U << 0) |
268 | |
269 | #define STE_MacCtrl0 0x50 /* 16-bit */ |
270 | #define MC0_IFSSelect(x) ((x) << 0) |
271 | #define MC0_FullDuplexEnable (1U << 5) |
272 | #define MC0_RcvLargeFrames (1U << 6) |
273 | #define MC0_FlowControlEnable (1U << 8) |
274 | #define MC0_RcvFCS (1U << 9) |
275 | #define MC0_FIFOLoopback (1U << 10) |
276 | #define MC0_MACLoopback (1U << 11) |
277 | |
278 | #define STE_MacCtrl1 0x52 /* 16-bit */ |
279 | #define MC1_CollsionDetect (1U << 0) |
280 | #define MC1_CarrierSense (1U << 1) |
281 | #define MC1_TxInProg (1U << 2) |
282 | #define MC1_TxError (1U << 3) |
283 | #define MC1_StatisticsEnable (1U << 5) |
284 | #define MC1_StatisticsDisable (1U << 6) |
285 | #define MC1_StatisticsEnabled (1U << 7) |
286 | #define MC1_TxEnable (1U << 8) |
287 | #define MC1_TxDisable (1U << 9) |
288 | #define MC1_TxEnabled (1U << 10) |
289 | #define MC1_RxEnable (1U << 11) |
290 | #define MC1_RxDisable (1U << 12) |
291 | #define MC1_RxEnabled (1U << 13) |
292 | #define MC1_Paused (1U << 14) |
293 | |
294 | #define STE_StationAddress0 0x54 /* 16-bit */ |
295 | |
296 | #define STE_StationAddress1 0x56 /* 16-bit */ |
297 | |
298 | #define STE_StationAddress2 0x58 /* 16-bit */ |
299 | |
300 | #define STE_MaxFrameSize 0x5a /* 16-bit */ |
301 | |
302 | #define STE_ReceiveMode 0x5c /* 8-bit */ |
303 | #define RM_ReceiveUnicast (1U << 0) |
304 | #define RM_ReceiveMulticast (1U << 1) |
305 | #define RM_ReceiveBroadcast (1U << 2) |
306 | #define RM_ReceiveAllFrames (1U << 3) |
307 | #define RM_ReceiveMulticastHash (1U << 4) |
308 | #define RM_ReceiveIPMulticast (1U << 5) |
309 | |
310 | #define STE_TxReleaseThresh 0x5d /* 8-bit */ |
311 | |
312 | #define STE_PhyCtrl 0x5e /* 8-bit */ |
313 | #define PC_MgmtClk (1U << 0) |
314 | #define PC_MgmtData (1U << 1) |
315 | #define PC_MgmtDir (1U << 2) /* 1 = MAC->Phy */ |
316 | #define PC_DisableClk25 (1U << 3) |
317 | #define PC_PhyDuplexPolarity (1U << 4) |
318 | #define PC_PhyDuplexStatus (1U << 5) |
319 | #define PC_PhySpeedStatus (1U << 6) |
320 | #define PC_PhyLinkStatus (1U << 7) |
321 | |
322 | #define STE_HashTable0 0x60 /* 16-bit */ |
323 | |
324 | #define STE_HashTable1 0x62 /* 16-bit */ |
325 | |
326 | #define STE_HashTable2 0x64 /* 16-bit */ |
327 | |
328 | #define STE_HashTable3 0x66 /* 16-bit */ |
329 | |
330 | #define STE_OctetsReceivedOk0 0x68 /* 16-bit */ |
331 | |
332 | #define STE_OctetsReceivedOk1 0x6a /* 16-bit */ |
333 | |
334 | #define STE_OctetsTransmittedOk0 0x6c /* 16-bit */ |
335 | |
336 | #define STE_OctetsTransmittedOk1 0x6e /* 16-bit */ |
337 | |
338 | #define STE_FramesTransmittedOK 0x70 /* 16-bit */ |
339 | |
340 | #define STE_FramesReceivedOK 0x72 /* 16-bit */ |
341 | |
342 | #define STE_CarrierSenseErrors 0x74 /* 8-bit */ |
343 | |
344 | #define STE_LateCollisions 0x75 /* 8-bit */ |
345 | |
346 | #define STE_MultipleColFrames 0x76 /* 8-bit */ |
347 | |
348 | #define STE_SingleColFrames 0x77 /* 8-bit */ |
349 | |
350 | #define STE_FramesWDeferredXmt 0x78 /* 8-bit */ |
351 | |
352 | #define STE_FramesLostRxErrors 0x79 /* 8-bit */ |
353 | |
354 | #define STE_FramesWExDeferral 0x7a /* 8-bit */ |
355 | |
356 | #define STE_FramesXbortXSColls 0x7b /* 8-bit */ |
357 | |
358 | #define STE_BcstFramesXmtdOk 0x7c /* 8-bit */ |
359 | |
360 | #define STE_BcstFramesRcvdOk 0x7d /* 8-bit */ |
361 | |
362 | #define STE_McstFramesXmtdOk 0x7e /* 8-bit */ |
363 | |
364 | #define STE_McstFramesRcvdOk 0x7f /* 8-bit */ |
365 | |
366 | #endif /* _DEV_PCI_IF_STEREG_H_ */ |
367 | |