1 | /* $NetBSD: dpt_pci.c,v 1.27 2014/03/29 19:28:24 christos Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1999, 2000, 2001 Andrew Doran <ad@NetBSD.org> |
5 | * All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * |
16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
26 | * SUCH DAMAGE. |
27 | * |
28 | */ |
29 | |
30 | /* |
31 | * PCI front-end for DPT EATA SCSI driver. |
32 | */ |
33 | |
34 | #include <sys/cdefs.h> |
35 | __KERNEL_RCSID(0, "$NetBSD: dpt_pci.c,v 1.27 2014/03/29 19:28:24 christos Exp $" ); |
36 | |
37 | #include <sys/param.h> |
38 | #include <sys/systm.h> |
39 | #include <sys/device.h> |
40 | #include <sys/queue.h> |
41 | |
42 | #include <sys/bus.h> |
43 | #include <sys/intr.h> |
44 | |
45 | #include <dev/scsipi/scsipi_all.h> |
46 | #include <dev/scsipi/scsiconf.h> |
47 | |
48 | #include <dev/pci/pcidevs.h> |
49 | #include <dev/pci/pcivar.h> |
50 | |
51 | #include <dev/ic/dptreg.h> |
52 | #include <dev/ic/dptvar.h> |
53 | |
54 | #include <dev/i2o/dptivar.h> |
55 | |
56 | #define PCI_CBMA 0x14 /* Configuration base memory address */ |
57 | #define PCI_CBIO 0x10 /* Configuration base I/O address */ |
58 | |
59 | static int dpt_pci_match(device_t, cfdata_t, void *); |
60 | static void dpt_pci_attach(device_t, device_t, void *); |
61 | |
62 | CFATTACH_DECL_NEW(dpt_pci, sizeof(struct dpt_softc), |
63 | dpt_pci_match, dpt_pci_attach, NULL, NULL); |
64 | |
65 | static int |
66 | dpt_pci_match(device_t parent, cfdata_t match, void *aux) |
67 | { |
68 | struct pci_attach_args *pa; |
69 | |
70 | pa = (struct pci_attach_args *)aux; |
71 | |
72 | if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_DPT && |
73 | PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_DPT_SC_RAID) |
74 | return (1); |
75 | |
76 | return (0); |
77 | } |
78 | |
79 | static void |
80 | dpt_pci_attach(device_t parent, device_t self, void *aux) |
81 | { |
82 | struct pci_attach_args *pa; |
83 | struct dpt_softc *sc; |
84 | pci_chipset_tag_t pc; |
85 | pci_intr_handle_t ih; |
86 | bus_space_handle_t ioh; |
87 | const char *intrstr; |
88 | pcireg_t csr; |
89 | char intrbuf[PCI_INTRSTR_LEN]; |
90 | |
91 | aprint_naive(": Storage controller\n" ); |
92 | |
93 | sc = device_private(self); |
94 | sc->sc_dev = self; |
95 | pa = (struct pci_attach_args *)aux; |
96 | pc = pa->pa_pc; |
97 | aprint_normal(": " ); |
98 | |
99 | if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, &sc->sc_iot, |
100 | &ioh, NULL, NULL)) { |
101 | aprint_error("can't map i/o space\n" ); |
102 | return; |
103 | } |
104 | |
105 | /* Need to map in by 16 registers. */ |
106 | if (bus_space_subregion(sc->sc_iot, ioh, 16, 16, &sc->sc_ioh)) { |
107 | aprint_error("can't map i/o subregion\n" ); |
108 | return; |
109 | } |
110 | |
111 | sc->sc_dmat = pa->pa_dmat; |
112 | |
113 | /* Enable the device. */ |
114 | csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); |
115 | pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, |
116 | csr | PCI_COMMAND_MASTER_ENABLE); |
117 | |
118 | /* Map and establish the interrupt. */ |
119 | if (pci_intr_map(pa, &ih)) { |
120 | aprint_error("can't map interrupt\n" ); |
121 | return; |
122 | } |
123 | intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); |
124 | sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, dpt_intr, sc); |
125 | if (sc->sc_ih == NULL) { |
126 | aprint_error("can't establish interrupt" ); |
127 | if (intrstr != NULL) |
128 | aprint_error(" at %s" , intrstr); |
129 | aprint_error("\n" ); |
130 | return; |
131 | } |
132 | |
133 | /* Read the EATA configuration. */ |
134 | if (dpt_readcfg(sc)) { |
135 | aprint_error_dev(sc->sc_dev, "readcfg failed - see dpt(4)\n" ); |
136 | return; |
137 | } |
138 | |
139 | sc->sc_bustype = SI_PCI_BUS; |
140 | |
141 | /* Now attach to the bus-independent code. */ |
142 | dpt_init(sc, intrstr); |
143 | } |
144 | |