1 | /* $NetBSD: amr.c,v 1.62 2016/09/27 03:33:32 pgoyette Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Andrew Doran. |
9 | * |
10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions |
12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. |
15 | * 2. Redistributions in binary form must reproduce the above copyright |
16 | * notice, this list of conditions and the following disclaimer in the |
17 | * documentation and/or other materials provided with the distribution. |
18 | * |
19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
29 | * POSSIBILITY OF SUCH DAMAGE. |
30 | */ |
31 | |
32 | /*- |
33 | * Copyright (c) 1999,2000 Michael Smith |
34 | * Copyright (c) 2000 BSDi |
35 | * All rights reserved. |
36 | * |
37 | * Redistribution and use in source and binary forms, with or without |
38 | * modification, are permitted provided that the following conditions |
39 | * are met: |
40 | * 1. Redistributions of source code must retain the above copyright |
41 | * notice, this list of conditions and the following disclaimer. |
42 | * 2. Redistributions in binary form must reproduce the above copyright |
43 | * notice, this list of conditions and the following disclaimer in the |
44 | * documentation and/or other materials provided with the distribution. |
45 | * |
46 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
47 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
48 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
49 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
50 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
51 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
52 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
53 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
54 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
55 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
56 | * SUCH DAMAGE. |
57 | * |
58 | * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp |
59 | * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp |
60 | */ |
61 | |
62 | /* |
63 | * Driver for AMI RAID controllers. |
64 | */ |
65 | |
66 | #include <sys/cdefs.h> |
67 | __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.62 2016/09/27 03:33:32 pgoyette Exp $" ); |
68 | |
69 | #include <sys/param.h> |
70 | #include <sys/systm.h> |
71 | #include <sys/kernel.h> |
72 | #include <sys/device.h> |
73 | #include <sys/queue.h> |
74 | #include <sys/proc.h> |
75 | #include <sys/buf.h> |
76 | #include <sys/malloc.h> |
77 | #include <sys/conf.h> |
78 | #include <sys/kthread.h> |
79 | #include <sys/kauth.h> |
80 | #include <sys/mutex.h> |
81 | #include <sys/condvar.h> |
82 | #include <sys/module.h> |
83 | |
84 | #include <machine/endian.h> |
85 | #include <sys/bus.h> |
86 | |
87 | #include <dev/pci/pcidevs.h> |
88 | #include <dev/pci/pcivar.h> |
89 | #include <dev/pci/amrreg.h> |
90 | #include <dev/pci/amrvar.h> |
91 | #include <dev/pci/amrio.h> |
92 | |
93 | #include "locators.h" |
94 | |
95 | #include "ioconf.h" |
96 | |
97 | static void amr_attach(device_t, device_t, void *); |
98 | static void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); |
99 | static void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, |
100 | void *); |
101 | static int amr_init(struct amr_softc *, const char *, |
102 | struct pci_attach_args *pa); |
103 | static int amr_intr(void *); |
104 | static int amr_match(device_t, cfdata_t, void *); |
105 | static int amr_rescan(device_t, const char *, const int *); |
106 | static int amr_print(void *, const char *); |
107 | static void amr_shutdown(void *); |
108 | static void amr_teardown(struct amr_softc *); |
109 | static void amr_quartz_thread(void *); |
110 | static void amr_std_thread(void *); |
111 | |
112 | static int amr_quartz_get_work(struct amr_softc *, |
113 | struct amr_mailbox_resp *); |
114 | static int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); |
115 | static int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); |
116 | static int amr_std_submit(struct amr_softc *, struct amr_ccb *); |
117 | |
118 | static dev_type_open(amropen); |
119 | static dev_type_close(amrclose); |
120 | static dev_type_ioctl(amrioctl); |
121 | |
122 | CFATTACH_DECL3_NEW(amr, sizeof(struct amr_softc), |
123 | amr_match, amr_attach, NULL, NULL, amr_rescan, NULL, 0); |
124 | |
125 | const struct cdevsw amr_cdevsw = { |
126 | .d_open = amropen, |
127 | .d_close = amrclose, |
128 | .d_read = noread, |
129 | .d_write = nowrite, |
130 | .d_ioctl = amrioctl, |
131 | .d_stop = nostop, |
132 | .d_tty = notty, |
133 | .d_poll = nopoll, |
134 | .d_mmap = nommap, |
135 | .d_kqfilter = nokqfilter, |
136 | .d_discard = nodiscard, |
137 | .d_flag = D_OTHER |
138 | }; |
139 | |
140 | extern struct cfdriver amr_cd; |
141 | |
142 | #define AT_QUARTZ 0x01 /* `Quartz' chipset */ |
143 | #define AT_SIG 0x02 /* Check for signature */ |
144 | |
145 | static struct amr_pci_type { |
146 | u_short apt_vendor; |
147 | u_short apt_product; |
148 | u_short apt_flags; |
149 | } const amr_pci_type[] = { |
150 | { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, |
151 | { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, |
152 | { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, |
153 | { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, |
154 | { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, |
155 | { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, |
156 | { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, |
157 | { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, |
158 | { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, |
159 | { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, |
160 | { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ }, |
161 | { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ }, |
162 | { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, |
163 | { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, |
164 | { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, |
165 | }; |
166 | |
167 | static struct amr_typestr { |
168 | const char *at_str; |
169 | int at_sig; |
170 | } const amr_typestr[] = { |
171 | { "Series 431" , AMR_SIG_431 }, |
172 | { "Series 438" , AMR_SIG_438 }, |
173 | { "Series 466" , AMR_SIG_466 }, |
174 | { "Series 467" , AMR_SIG_467 }, |
175 | { "Series 490" , AMR_SIG_490 }, |
176 | { "Series 762" , AMR_SIG_762 }, |
177 | { "HP NetRAID (T5)" , AMR_SIG_T5 }, |
178 | { "HP NetRAID (T7)" , AMR_SIG_T7 }, |
179 | }; |
180 | |
181 | static struct { |
182 | const char *ds_descr; |
183 | int ds_happy; |
184 | } const amr_dstate[] = { |
185 | { "offline" , 0 }, |
186 | { "degraded" , 1 }, |
187 | { "optimal" , 1 }, |
188 | { "online" , 1 }, |
189 | { "failed" , 0 }, |
190 | { "rebuilding" , 1 }, |
191 | { "hotspare" , 0 }, |
192 | }; |
193 | |
194 | static void *amr_sdh; |
195 | |
196 | static kcondvar_t thread_cv; |
197 | static kmutex_t thread_mutex; |
198 | |
199 | static int amr_max_segs; |
200 | int amr_max_xfer; |
201 | |
202 | static inline u_int8_t |
203 | amr_inb(struct amr_softc *amr, int off) |
204 | { |
205 | bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, |
206 | BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); |
207 | return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); |
208 | } |
209 | |
210 | static inline u_int32_t |
211 | amr_inl(struct amr_softc *amr, int off) |
212 | { |
213 | bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, |
214 | BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); |
215 | return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); |
216 | } |
217 | |
218 | static inline void |
219 | amr_outb(struct amr_softc *amr, int off, u_int8_t val) |
220 | { |
221 | bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); |
222 | bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, |
223 | BUS_SPACE_BARRIER_WRITE); |
224 | } |
225 | |
226 | static inline void |
227 | amr_outl(struct amr_softc *amr, int off, u_int32_t val) |
228 | { |
229 | bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); |
230 | bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, |
231 | BUS_SPACE_BARRIER_WRITE); |
232 | } |
233 | |
234 | /* |
235 | * Match a supported device. |
236 | */ |
237 | static int |
238 | amr_match(device_t parent, cfdata_t match, void *aux) |
239 | { |
240 | struct pci_attach_args *pa; |
241 | pcireg_t s; |
242 | int i; |
243 | |
244 | pa = (struct pci_attach_args *)aux; |
245 | |
246 | /* |
247 | * Don't match the device if it's operating in I2O mode. In this |
248 | * case it should be handled by the `iop' driver. |
249 | */ |
250 | if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) |
251 | return (0); |
252 | |
253 | for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) |
254 | if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && |
255 | PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) |
256 | break; |
257 | |
258 | if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) |
259 | return (0); |
260 | |
261 | if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) |
262 | return (1); |
263 | |
264 | s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; |
265 | return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); |
266 | } |
267 | |
268 | /* |
269 | * Attach a supported device. |
270 | */ |
271 | static void |
272 | amr_attach(device_t parent, device_t self, void *aux) |
273 | { |
274 | struct pci_attach_args *pa; |
275 | const struct amr_pci_type *apt; |
276 | struct amr_softc *amr; |
277 | pci_chipset_tag_t pc; |
278 | pci_intr_handle_t ih; |
279 | const char *intrstr; |
280 | pcireg_t reg; |
281 | int rseg, i, size, rv, memreg, ioreg; |
282 | struct amr_ccb *ac; |
283 | char intrbuf[PCI_INTRSTR_LEN]; |
284 | |
285 | aprint_naive(": RAID controller\n" ); |
286 | |
287 | amr = device_private(self); |
288 | amr->amr_dv = self; |
289 | |
290 | mutex_init(&amr->amr_mutex, MUTEX_DEFAULT, IPL_BIO); |
291 | |
292 | pa = (struct pci_attach_args *)aux; |
293 | pc = pa->pa_pc; |
294 | |
295 | for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) |
296 | if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && |
297 | PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) |
298 | break; |
299 | apt = amr_pci_type + i; |
300 | |
301 | memreg = ioreg = 0; |
302 | for (i = 0x10; i <= 0x14; i += 4) { |
303 | reg = pci_conf_read(pc, pa->pa_tag, i); |
304 | switch (PCI_MAPREG_TYPE(reg)) { |
305 | case PCI_MAPREG_TYPE_MEM: |
306 | if (PCI_MAPREG_MEM_SIZE(reg) != 0) |
307 | memreg = i; |
308 | break; |
309 | case PCI_MAPREG_TYPE_IO: |
310 | if (PCI_MAPREG_IO_SIZE(reg) != 0) |
311 | ioreg = i; |
312 | break; |
313 | } |
314 | } |
315 | |
316 | if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, |
317 | &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) |
318 | ; |
319 | else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, |
320 | &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) |
321 | ; |
322 | else { |
323 | aprint_error("can't map control registers\n" ); |
324 | amr_teardown(amr); |
325 | return; |
326 | } |
327 | |
328 | amr->amr_flags |= AMRF_PCI_REGS; |
329 | amr->amr_dmat = pa->pa_dmat; |
330 | amr->amr_pc = pa->pa_pc; |
331 | |
332 | /* Enable the device. */ |
333 | reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); |
334 | pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, |
335 | reg | PCI_COMMAND_MASTER_ENABLE); |
336 | |
337 | /* Map and establish the interrupt. */ |
338 | if (pci_intr_map(pa, &ih)) { |
339 | aprint_error("can't map interrupt\n" ); |
340 | amr_teardown(amr); |
341 | return; |
342 | } |
343 | intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); |
344 | amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); |
345 | if (amr->amr_ih == NULL) { |
346 | aprint_error("can't establish interrupt" ); |
347 | if (intrstr != NULL) |
348 | aprint_error(" at %s" , intrstr); |
349 | aprint_error("\n" ); |
350 | amr_teardown(amr); |
351 | return; |
352 | } |
353 | amr->amr_flags |= AMRF_PCI_INTR; |
354 | |
355 | /* |
356 | * Allocate space for the mailbox and S/G lists. Some controllers |
357 | * don't like S/G lists to be located below 0x2000, so we allocate |
358 | * enough slop to enable us to compensate. |
359 | * |
360 | * The standard mailbox structure needs to be aligned on a 16-byte |
361 | * boundary. The 64-bit mailbox has one extra field, 4 bytes in |
362 | * size, which precedes the standard mailbox. |
363 | */ |
364 | size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; |
365 | amr->amr_dmasize = size; |
366 | |
367 | if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, |
368 | &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { |
369 | aprint_error_dev(amr->amr_dv, |
370 | "unable to allocate buffer, rv = %d\n" , rv); |
371 | amr_teardown(amr); |
372 | return; |
373 | } |
374 | amr->amr_flags |= AMRF_DMA_ALLOC; |
375 | |
376 | if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, |
377 | (void **)&amr->amr_mbox, |
378 | BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { |
379 | aprint_error_dev(amr->amr_dv, "unable to map buffer, rv = %d\n" , |
380 | rv); |
381 | amr_teardown(amr); |
382 | return; |
383 | } |
384 | amr->amr_flags |= AMRF_DMA_MAP; |
385 | |
386 | if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, |
387 | BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { |
388 | aprint_error_dev(amr->amr_dv, |
389 | "unable to create buffer DMA map, rv = %d\n" , rv); |
390 | amr_teardown(amr); |
391 | return; |
392 | } |
393 | amr->amr_flags |= AMRF_DMA_CREATE; |
394 | |
395 | if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, |
396 | amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { |
397 | aprint_error_dev(amr->amr_dv, |
398 | "unable to load buffer DMA map, rv = %d\n" , rv); |
399 | amr_teardown(amr); |
400 | return; |
401 | } |
402 | amr->amr_flags |= AMRF_DMA_LOAD; |
403 | |
404 | memset(amr->amr_mbox, 0, size); |
405 | |
406 | amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; |
407 | amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; |
408 | amr->amr_sgls = (struct amr_sgentry *)((char *)amr->amr_mbox + |
409 | amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); |
410 | |
411 | /* |
412 | * Allocate and initalise the command control blocks. |
413 | */ |
414 | ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); |
415 | amr->amr_ccbs = ac; |
416 | SLIST_INIT(&amr->amr_ccb_freelist); |
417 | TAILQ_INIT(&amr->amr_ccb_active); |
418 | amr->amr_flags |= AMRF_CCBS; |
419 | |
420 | if (amr_max_xfer == 0) { |
421 | amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); |
422 | amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; |
423 | } |
424 | |
425 | for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { |
426 | rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, |
427 | amr_max_segs, amr_max_xfer, 0, |
428 | BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); |
429 | if (rv != 0) |
430 | break; |
431 | |
432 | ac->ac_ident = i; |
433 | cv_init(&ac->ac_cv, "amr1ccb" ); |
434 | mutex_init(&ac->ac_mutex, MUTEX_DEFAULT, IPL_NONE); |
435 | amr_ccb_free(amr, ac); |
436 | } |
437 | if (i != AMR_MAX_CMDS) { |
438 | aprint_error_dev(amr->amr_dv, "memory exhausted\n" ); |
439 | amr_teardown(amr); |
440 | return; |
441 | } |
442 | |
443 | /* |
444 | * Take care of model-specific tasks. |
445 | */ |
446 | if ((apt->apt_flags & AT_QUARTZ) != 0) { |
447 | amr->amr_submit = amr_quartz_submit; |
448 | amr->amr_get_work = amr_quartz_get_work; |
449 | } else { |
450 | amr->amr_submit = amr_std_submit; |
451 | amr->amr_get_work = amr_std_get_work; |
452 | |
453 | /* Notify the controller of the mailbox location. */ |
454 | amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); |
455 | amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); |
456 | |
457 | /* Clear outstanding interrupts and enable interrupts. */ |
458 | amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); |
459 | amr_outb(amr, AMR_SREG_TOGL, |
460 | amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); |
461 | } |
462 | |
463 | /* |
464 | * Retrieve parameters, and tell the world about us. |
465 | */ |
466 | amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); |
467 | amr->amr_flags |= AMRF_ENQBUF; |
468 | amr->amr_maxqueuecnt = i; |
469 | aprint_normal(": AMI RAID " ); |
470 | if (amr_init(amr, intrstr, pa) != 0) { |
471 | amr_teardown(amr); |
472 | return; |
473 | } |
474 | |
475 | /* |
476 | * Cap the maximum number of outstanding commands. AMI's Linux |
477 | * driver doesn't trust the controller's reported value, and lockups |
478 | * have been seen when we do. |
479 | */ |
480 | amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); |
481 | if (amr->amr_maxqueuecnt > i) |
482 | amr->amr_maxqueuecnt = i; |
483 | |
484 | /* Set our `shutdownhook' before we start any device activity. */ |
485 | if (amr_sdh == NULL) |
486 | amr_sdh = shutdownhook_establish(amr_shutdown, NULL); |
487 | |
488 | /* Attach sub-devices. */ |
489 | amr_rescan(self, "amr" , 0); |
490 | |
491 | SIMPLEQ_INIT(&amr->amr_ccb_queue); |
492 | |
493 | cv_init(&thread_cv, "amrwdog" ); |
494 | mutex_init(&thread_mutex, MUTEX_DEFAULT, IPL_NONE); |
495 | |
496 | if ((apt->apt_flags & AT_QUARTZ) == 0) { |
497 | rv = kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL, |
498 | amr_std_thread, amr, &amr->amr_thread, |
499 | "%s" , device_xname(amr->amr_dv)); |
500 | } else { |
501 | rv = kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL, |
502 | amr_quartz_thread, amr, &amr->amr_thread, |
503 | "%s" , device_xname(amr->amr_dv)); |
504 | } |
505 | if (rv != 0) |
506 | aprint_error_dev(amr->amr_dv, "unable to create thread (%d)" , |
507 | rv); |
508 | else |
509 | amr->amr_flags |= AMRF_THREAD; |
510 | } |
511 | |
512 | static int |
513 | amr_rescan(device_t self, const char *attr, const int *flags) |
514 | { |
515 | int j; |
516 | int locs[AMRCF_NLOCS]; |
517 | struct amr_attach_args amra; |
518 | struct amr_softc *amr; |
519 | |
520 | amr = device_private(self); |
521 | for (j = 0; j < amr->amr_numdrives; j++) { |
522 | if (amr->amr_drive[j].al_dv) |
523 | continue; |
524 | if (amr->amr_drive[j].al_size == 0) |
525 | continue; |
526 | amra.amra_unit = j; |
527 | |
528 | locs[AMRCF_UNIT] = j; |
529 | |
530 | amr->amr_drive[j].al_dv = config_found_sm_loc(amr->amr_dv, |
531 | attr, locs, &amra, amr_print, config_stdsubmatch); |
532 | } |
533 | return 0; |
534 | } |
535 | |
536 | /* |
537 | * Free up resources. |
538 | */ |
539 | static void |
540 | amr_teardown(struct amr_softc *amr) |
541 | { |
542 | struct amr_ccb *ac; |
543 | int fl; |
544 | |
545 | fl = amr->amr_flags; |
546 | |
547 | if ((fl & AMRF_THREAD) != 0) { |
548 | amr->amr_flags |= AMRF_THREAD_EXIT; |
549 | mutex_enter(&thread_mutex); |
550 | cv_broadcast(&thread_cv); |
551 | mutex_exit(&thread_mutex); |
552 | while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { |
553 | mutex_enter(&thread_mutex); |
554 | cv_wait(&thread_cv, &thread_mutex); |
555 | mutex_exit(&thread_mutex); |
556 | } |
557 | } |
558 | if ((fl & AMRF_CCBS) != 0) { |
559 | SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { |
560 | bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); |
561 | } |
562 | free(amr->amr_ccbs, M_DEVBUF); |
563 | } |
564 | if ((fl & AMRF_ENQBUF) != 0) |
565 | free(amr->amr_enqbuf, M_DEVBUF); |
566 | if ((fl & AMRF_DMA_LOAD) != 0) |
567 | bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); |
568 | if ((fl & AMRF_DMA_MAP) != 0) |
569 | bus_dmamem_unmap(amr->amr_dmat, (void *)amr->amr_mbox, |
570 | amr->amr_dmasize); |
571 | if ((fl & AMRF_DMA_ALLOC) != 0) |
572 | bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); |
573 | if ((fl & AMRF_DMA_CREATE) != 0) |
574 | bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); |
575 | if ((fl & AMRF_PCI_INTR) != 0) |
576 | pci_intr_disestablish(amr->amr_pc, amr->amr_ih); |
577 | if ((fl & AMRF_PCI_REGS) != 0) |
578 | bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); |
579 | } |
580 | |
581 | /* |
582 | * Print autoconfiguration message for a sub-device. |
583 | */ |
584 | static int |
585 | amr_print(void *aux, const char *pnp) |
586 | { |
587 | struct amr_attach_args *amra; |
588 | |
589 | amra = (struct amr_attach_args *)aux; |
590 | |
591 | if (pnp != NULL) |
592 | aprint_normal("block device at %s" , pnp); |
593 | aprint_normal(" unit %d" , amra->amra_unit); |
594 | return (UNCONF); |
595 | } |
596 | |
597 | /* |
598 | * Retrieve operational parameters and describe the controller. |
599 | */ |
600 | static int |
601 | amr_init(struct amr_softc *amr, const char *intrstr, |
602 | struct pci_attach_args *pa) |
603 | { |
604 | struct amr_adapter_info *aa; |
605 | struct amr_prodinfo *ap; |
606 | struct amr_enquiry *ae; |
607 | struct amr_enquiry3 *aex; |
608 | const char *prodstr; |
609 | u_int i, sig, ishp; |
610 | char sbuf[64]; |
611 | |
612 | /* |
613 | * Try to get 40LD product info, which tells us what the card is |
614 | * labelled as. |
615 | */ |
616 | ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, |
617 | amr->amr_enqbuf); |
618 | if (ap != NULL) { |
619 | aprint_normal("<%.80s>\n" , ap->ap_product); |
620 | if (intrstr != NULL) |
621 | aprint_normal_dev(amr->amr_dv, "interrupting at %s\n" , |
622 | intrstr); |
623 | aprint_normal_dev(amr->amr_dv, |
624 | "firmware %.16s, BIOS %.16s, %dMB RAM\n" , |
625 | ap->ap_firmware, ap->ap_bios, le16toh(ap->ap_memsize)); |
626 | |
627 | amr->amr_maxqueuecnt = ap->ap_maxio; |
628 | |
629 | /* |
630 | * Fetch and record state of logical drives. |
631 | */ |
632 | aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, |
633 | AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); |
634 | if (aex == NULL) { |
635 | aprint_error_dev(amr->amr_dv, "ENQUIRY3 failed\n" ); |
636 | return (-1); |
637 | } |
638 | |
639 | if (aex->ae_numldrives > __arraycount(aex->ae_drivestate)) { |
640 | aprint_error_dev(amr->amr_dv, "Inquiry returned more " |
641 | "drives (%d) than the array can handle (%zu)\n" , |
642 | aex->ae_numldrives, |
643 | __arraycount(aex->ae_drivestate)); |
644 | aex->ae_numldrives = __arraycount(aex->ae_drivestate); |
645 | } |
646 | if (aex->ae_numldrives > AMR_MAX_UNITS) { |
647 | aprint_error_dev(amr->amr_dv, |
648 | "adjust AMR_MAX_UNITS to %d (currently %d)\n" , |
649 | AMR_MAX_UNITS, amr->amr_numdrives); |
650 | amr->amr_numdrives = AMR_MAX_UNITS; |
651 | } else |
652 | amr->amr_numdrives = aex->ae_numldrives; |
653 | |
654 | for (i = 0; i < amr->amr_numdrives; i++) { |
655 | amr->amr_drive[i].al_size = |
656 | le32toh(aex->ae_drivesize[i]); |
657 | amr->amr_drive[i].al_state = aex->ae_drivestate[i]; |
658 | amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; |
659 | } |
660 | |
661 | return (0); |
662 | } |
663 | |
664 | /* |
665 | * Try 8LD extended ENQUIRY to get the controller signature. Once |
666 | * found, search for a product description. |
667 | */ |
668 | ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); |
669 | if (ae != NULL) { |
670 | i = 0; |
671 | sig = le32toh(ae->ae_signature); |
672 | |
673 | while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { |
674 | if (amr_typestr[i].at_sig == sig) |
675 | break; |
676 | i++; |
677 | } |
678 | if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { |
679 | snprintf(sbuf, sizeof(sbuf), |
680 | "unknown ENQUIRY2 sig (0x%08x)" , sig); |
681 | prodstr = sbuf; |
682 | } else |
683 | prodstr = amr_typestr[i].at_str; |
684 | } else { |
685 | ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); |
686 | if (ae == NULL) { |
687 | aprint_error_dev(amr->amr_dv, |
688 | "unsupported controller\n" ); |
689 | return (-1); |
690 | } |
691 | |
692 | switch (PCI_PRODUCT(pa->pa_id)) { |
693 | case PCI_PRODUCT_AMI_MEGARAID: |
694 | prodstr = "Series 428" ; |
695 | break; |
696 | case PCI_PRODUCT_AMI_MEGARAID2: |
697 | prodstr = "Series 434" ; |
698 | break; |
699 | default: |
700 | snprintf(sbuf, sizeof(sbuf), |
701 | "unknown PCI dev (0x%04x)" , |
702 | PCI_PRODUCT(pa->pa_id)); |
703 | prodstr = sbuf; |
704 | break; |
705 | } |
706 | } |
707 | |
708 | /* |
709 | * HP NetRaid controllers have a special encoding of the firmware |
710 | * and BIOS versions. The AMI version seems to have it as strings |
711 | * whereas the HP version does it with a leading uppercase character |
712 | * and two binary numbers. |
713 | */ |
714 | aa = &ae->ae_adapter; |
715 | |
716 | if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && |
717 | aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && |
718 | aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && |
719 | aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { |
720 | if (le32toh(ae->ae_signature) == AMR_SIG_438) { |
721 | /* The AMI 438 is a NetRaid 3si in HP-land. */ |
722 | prodstr = "HP NetRaid 3si" ; |
723 | } |
724 | ishp = 1; |
725 | } else |
726 | ishp = 0; |
727 | |
728 | aprint_normal("<%s>\n" , prodstr); |
729 | if (intrstr != NULL) |
730 | aprint_normal_dev(amr->amr_dv, "interrupting at %s\n" , |
731 | intrstr); |
732 | |
733 | if (ishp) |
734 | aprint_normal_dev(amr->amr_dv, "firmware <%c.%02d.%02d>, " |
735 | "BIOS <%c.%02d.%02d>, %dMB RAM\n" , aa->aa_firmware[2], |
736 | aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], |
737 | aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); |
738 | else |
739 | aprint_normal_dev(amr->amr_dv, "firmware <%.4s>, BIOS <%.4s>, " |
740 | "%dMB RAM\n" , aa->aa_firmware, aa->aa_bios, |
741 | aa->aa_memorysize); |
742 | |
743 | amr->amr_maxqueuecnt = aa->aa_maxio; |
744 | |
745 | /* |
746 | * Record state of logical drives. |
747 | */ |
748 | if (ae->ae_ldrv.al_numdrives > __arraycount(ae->ae_ldrv.al_size)) { |
749 | aprint_error_dev(amr->amr_dv, "Inquiry returned more drives " |
750 | "(%d) than the array can handle (%zu)\n" , |
751 | ae->ae_ldrv.al_numdrives, |
752 | __arraycount(ae->ae_ldrv.al_size)); |
753 | ae->ae_ldrv.al_numdrives = __arraycount(ae->ae_ldrv.al_size); |
754 | } |
755 | if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { |
756 | aprint_error_dev(amr->amr_dv, |
757 | "adjust AMR_MAX_UNITS to %d (currently %d)\n" , |
758 | ae->ae_ldrv.al_numdrives, AMR_MAX_UNITS); |
759 | amr->amr_numdrives = AMR_MAX_UNITS; |
760 | } else |
761 | amr->amr_numdrives = ae->ae_ldrv.al_numdrives; |
762 | |
763 | for (i = 0; i < amr->amr_numdrives; i++) { |
764 | amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); |
765 | amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; |
766 | amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; |
767 | } |
768 | |
769 | return (0); |
770 | } |
771 | |
772 | /* |
773 | * Flush the internal cache on each configured controller. Called at |
774 | * shutdown time. |
775 | */ |
776 | static void |
777 | amr_shutdown(void *cookie) |
778 | { |
779 | extern struct cfdriver amr_cd; |
780 | struct amr_softc *amr; |
781 | struct amr_ccb *ac; |
782 | int i, rv; |
783 | |
784 | for (i = 0; i < amr_cd.cd_ndevs; i++) { |
785 | if ((amr = device_lookup_private(&amr_cd, i)) == NULL) |
786 | continue; |
787 | |
788 | if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { |
789 | ac->ac_cmd.mb_command = AMR_CMD_FLUSH; |
790 | rv = amr_ccb_poll(amr, ac, 30000); |
791 | amr_ccb_free(amr, ac); |
792 | } |
793 | if (rv != 0) |
794 | aprint_error_dev(amr->amr_dv, |
795 | "unable to flush cache (%d)\n" , rv); |
796 | } |
797 | } |
798 | |
799 | /* |
800 | * Interrupt service routine. |
801 | */ |
802 | static int |
803 | amr_intr(void *cookie) |
804 | { |
805 | struct amr_softc *amr; |
806 | struct amr_ccb *ac; |
807 | struct amr_mailbox_resp mbox; |
808 | u_int i, forus, idx; |
809 | |
810 | amr = cookie; |
811 | forus = 0; |
812 | |
813 | mutex_spin_enter(&amr->amr_mutex); |
814 | |
815 | while ((*amr->amr_get_work)(amr, &mbox) == 0) { |
816 | /* Iterate over completed commands in this result. */ |
817 | for (i = 0; i < mbox.mb_nstatus; i++) { |
818 | idx = mbox.mb_completed[i] - 1; |
819 | ac = amr->amr_ccbs + idx; |
820 | |
821 | if (idx >= amr->amr_maxqueuecnt) { |
822 | printf("%s: bad status (bogus ID: %u=%u)\n" , |
823 | device_xname(amr->amr_dv), i, idx); |
824 | continue; |
825 | } |
826 | |
827 | if ((ac->ac_flags & AC_ACTIVE) == 0) { |
828 | printf("%s: bad status (not active; 0x04%x)\n" , |
829 | device_xname(amr->amr_dv), ac->ac_flags); |
830 | continue; |
831 | } |
832 | |
833 | ac->ac_status = mbox.mb_status; |
834 | ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | |
835 | AC_COMPLETE; |
836 | TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); |
837 | |
838 | if ((ac->ac_flags & AC_MOAN) != 0) |
839 | printf("%s: ccb %d completed\n" , |
840 | device_xname(amr->amr_dv), ac->ac_ident); |
841 | |
842 | /* Pass notification to upper layers. */ |
843 | mutex_spin_exit(&amr->amr_mutex); |
844 | if (ac->ac_handler != NULL) { |
845 | (*ac->ac_handler)(ac); |
846 | } else { |
847 | mutex_enter(&ac->ac_mutex); |
848 | cv_signal(&ac->ac_cv); |
849 | mutex_exit(&ac->ac_mutex); |
850 | } |
851 | mutex_spin_enter(&amr->amr_mutex); |
852 | } |
853 | forus = 1; |
854 | } |
855 | |
856 | mutex_spin_exit(&amr->amr_mutex); |
857 | |
858 | if (forus) |
859 | amr_ccb_enqueue(amr, NULL); |
860 | |
861 | return (forus); |
862 | } |
863 | |
864 | /* |
865 | * Watchdog thread. |
866 | */ |
867 | static void |
868 | amr_quartz_thread(void *cookie) |
869 | { |
870 | struct amr_softc *amr; |
871 | struct amr_ccb *ac; |
872 | |
873 | amr = cookie; |
874 | |
875 | for (;;) { |
876 | mutex_enter(&thread_mutex); |
877 | cv_timedwait(&thread_cv, &thread_mutex, AMR_WDOG_TICKS); |
878 | mutex_exit(&thread_mutex); |
879 | |
880 | if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { |
881 | amr->amr_flags ^= AMRF_THREAD_EXIT; |
882 | mutex_enter(&thread_mutex); |
883 | cv_signal(&thread_cv); |
884 | mutex_exit(&thread_mutex); |
885 | kthread_exit(0); |
886 | } |
887 | |
888 | if (amr_intr(amr) == 0) |
889 | amr_ccb_enqueue(amr, NULL); |
890 | |
891 | mutex_spin_enter(&amr->amr_mutex); |
892 | ac = TAILQ_FIRST(&amr->amr_ccb_active); |
893 | while (ac != NULL) { |
894 | if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) |
895 | break; |
896 | if ((ac->ac_flags & AC_MOAN) == 0) { |
897 | printf("%s: ccb %d timed out; mailbox:\n" , |
898 | device_xname(amr->amr_dv), ac->ac_ident); |
899 | amr_ccb_dump(amr, ac); |
900 | ac->ac_flags |= AC_MOAN; |
901 | } |
902 | ac = TAILQ_NEXT(ac, ac_chain.tailq); |
903 | } |
904 | mutex_spin_exit(&amr->amr_mutex); |
905 | } |
906 | } |
907 | |
908 | static void |
909 | amr_std_thread(void *cookie) |
910 | { |
911 | struct amr_softc *amr; |
912 | struct amr_ccb *ac; |
913 | struct amr_logdrive *al; |
914 | struct amr_enquiry *ae; |
915 | int rv, i; |
916 | |
917 | amr = cookie; |
918 | ae = amr->amr_enqbuf; |
919 | |
920 | for (;;) { |
921 | mutex_enter(&thread_mutex); |
922 | cv_timedwait(&thread_cv, &thread_mutex, AMR_WDOG_TICKS); |
923 | mutex_exit(&thread_mutex); |
924 | |
925 | if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { |
926 | amr->amr_flags ^= AMRF_THREAD_EXIT; |
927 | mutex_enter(&thread_mutex); |
928 | cv_signal(&thread_cv); |
929 | mutex_exit(&thread_mutex); |
930 | kthread_exit(0); |
931 | } |
932 | |
933 | if (amr_intr(amr) == 0) |
934 | amr_ccb_enqueue(amr, NULL); |
935 | |
936 | mutex_spin_enter(&amr->amr_mutex); |
937 | ac = TAILQ_FIRST(&amr->amr_ccb_active); |
938 | while (ac != NULL) { |
939 | if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) |
940 | break; |
941 | if ((ac->ac_flags & AC_MOAN) == 0) { |
942 | printf("%s: ccb %d timed out; mailbox:\n" , |
943 | device_xname(amr->amr_dv), ac->ac_ident); |
944 | amr_ccb_dump(amr, ac); |
945 | ac->ac_flags |= AC_MOAN; |
946 | } |
947 | ac = TAILQ_NEXT(ac, ac_chain.tailq); |
948 | } |
949 | mutex_spin_exit(&amr->amr_mutex); |
950 | |
951 | if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { |
952 | printf("%s: ccb_alloc failed (%d)\n" , |
953 | device_xname(amr->amr_dv), rv); |
954 | continue; |
955 | } |
956 | |
957 | ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; |
958 | |
959 | rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, |
960 | AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); |
961 | if (rv != 0) { |
962 | aprint_error_dev(amr->amr_dv, "ccb_map failed (%d)\n" , |
963 | rv); |
964 | amr_ccb_free(amr, ac); |
965 | continue; |
966 | } |
967 | |
968 | rv = amr_ccb_wait(amr, ac); |
969 | amr_ccb_unmap(amr, ac); |
970 | if (rv != 0) { |
971 | aprint_error_dev(amr->amr_dv, |
972 | "enquiry failed (st=%d)\n" , ac->ac_status); |
973 | continue; |
974 | } |
975 | amr_ccb_free(amr, ac); |
976 | |
977 | al = amr->amr_drive; |
978 | for (i = 0; i < __arraycount(ae->ae_ldrv.al_state); i++, al++) { |
979 | if (al->al_dv == NULL) |
980 | continue; |
981 | if (al->al_state == ae->ae_ldrv.al_state[i]) |
982 | continue; |
983 | |
984 | printf("%s: state changed: %s -> %s\n" , |
985 | device_xname(al->al_dv), |
986 | amr_drive_state(al->al_state, NULL), |
987 | amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); |
988 | |
989 | al->al_state = ae->ae_ldrv.al_state[i]; |
990 | } |
991 | } |
992 | } |
993 | |
994 | /* |
995 | * Return a text description of a logical drive's current state. |
996 | */ |
997 | const char * |
998 | amr_drive_state(int state, int *happy) |
999 | { |
1000 | const char *str; |
1001 | |
1002 | state = AMR_DRV_CURSTATE(state); |
1003 | if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { |
1004 | if (happy) |
1005 | *happy = 1; |
1006 | str = "status unknown" ; |
1007 | } else { |
1008 | if (happy) |
1009 | *happy = amr_dstate[state].ds_happy; |
1010 | str = amr_dstate[state].ds_descr; |
1011 | } |
1012 | |
1013 | return (str); |
1014 | } |
1015 | |
1016 | /* |
1017 | * Run a generic enquiry-style command. |
1018 | */ |
1019 | static void * |
1020 | amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, |
1021 | u_int8_t cmdqual, void *sbuf) |
1022 | { |
1023 | struct amr_ccb *ac; |
1024 | u_int8_t *mb; |
1025 | int rv; |
1026 | |
1027 | if (amr_ccb_alloc(amr, &ac) != 0) |
1028 | return (NULL); |
1029 | |
1030 | /* Build the command proper. */ |
1031 | mb = (u_int8_t *)&ac->ac_cmd; |
1032 | mb[0] = cmd; |
1033 | mb[2] = cmdsub; |
1034 | mb[3] = cmdqual; |
1035 | |
1036 | rv = amr_ccb_map(amr, ac, sbuf, AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); |
1037 | if (rv == 0) { |
1038 | rv = amr_ccb_poll(amr, ac, 2000); |
1039 | amr_ccb_unmap(amr, ac); |
1040 | } |
1041 | amr_ccb_free(amr, ac); |
1042 | |
1043 | return (rv ? NULL : sbuf); |
1044 | } |
1045 | |
1046 | /* |
1047 | * Allocate and initialise a CCB. |
1048 | */ |
1049 | int |
1050 | amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) |
1051 | { |
1052 | mutex_spin_enter(&amr->amr_mutex); |
1053 | if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { |
1054 | mutex_spin_exit(&amr->amr_mutex); |
1055 | return (EAGAIN); |
1056 | } |
1057 | SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); |
1058 | mutex_spin_exit(&amr->amr_mutex); |
1059 | |
1060 | return (0); |
1061 | } |
1062 | |
1063 | /* |
1064 | * Free a CCB. |
1065 | */ |
1066 | void |
1067 | amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) |
1068 | { |
1069 | memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); |
1070 | ac->ac_cmd.mb_ident = ac->ac_ident + 1; |
1071 | ac->ac_cmd.mb_busy = 1; |
1072 | ac->ac_handler = NULL; |
1073 | ac->ac_flags = 0; |
1074 | |
1075 | mutex_spin_enter(&amr->amr_mutex); |
1076 | SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); |
1077 | mutex_spin_exit(&amr->amr_mutex); |
1078 | } |
1079 | |
1080 | /* |
1081 | * If a CCB is specified, enqueue it. Pull CCBs off the software queue in |
1082 | * the order that they were enqueued and try to submit their command blocks |
1083 | * to the controller for execution. |
1084 | */ |
1085 | void |
1086 | amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) |
1087 | { |
1088 | if (ac != NULL) { |
1089 | mutex_spin_enter(&amr->amr_mutex); |
1090 | SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); |
1091 | mutex_spin_exit(&amr->amr_mutex); |
1092 | } |
1093 | |
1094 | while (SIMPLEQ_FIRST(&amr->amr_ccb_queue) != NULL) { |
1095 | mutex_spin_enter(&amr->amr_mutex); |
1096 | if ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { |
1097 | if ((*amr->amr_submit)(amr, ac) != 0) { |
1098 | mutex_spin_exit(&amr->amr_mutex); |
1099 | break; |
1100 | } |
1101 | SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, |
1102 | ac_chain.simpleq); |
1103 | TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, |
1104 | ac_chain.tailq); |
1105 | } |
1106 | mutex_spin_exit(&amr->amr_mutex); |
1107 | } |
1108 | } |
1109 | |
1110 | /* |
1111 | * Map the specified CCB's data buffer onto the bus, and fill the |
1112 | * scatter-gather list. |
1113 | */ |
1114 | int |
1115 | amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, |
1116 | int tflag) |
1117 | { |
1118 | struct amr_sgentry *sge; |
1119 | struct amr_mailbox_cmd *mb; |
1120 | int nsegs, i, rv, sgloff; |
1121 | bus_dmamap_t xfer; |
1122 | int dmaflag = 0; |
1123 | |
1124 | xfer = ac->ac_xfer_map; |
1125 | |
1126 | rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, |
1127 | BUS_DMA_NOWAIT); |
1128 | if (rv != 0) |
1129 | return (rv); |
1130 | |
1131 | mb = &ac->ac_cmd; |
1132 | ac->ac_xfer_size = size; |
1133 | ac->ac_flags |= (tflag & (AC_XFER_OUT | AC_XFER_IN)); |
1134 | sgloff = AMR_SGL_SIZE * ac->ac_ident; |
1135 | |
1136 | if (tflag & AC_XFER_OUT) |
1137 | dmaflag |= BUS_DMASYNC_PREWRITE; |
1138 | if (tflag & AC_XFER_IN) |
1139 | dmaflag |= BUS_DMASYNC_PREREAD; |
1140 | |
1141 | /* We don't need to use a scatter/gather list for just 1 segment. */ |
1142 | nsegs = xfer->dm_nsegs; |
1143 | if (nsegs == 1) { |
1144 | mb->mb_nsgelem = 0; |
1145 | mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); |
1146 | ac->ac_flags |= AC_NOSGL; |
1147 | } else { |
1148 | mb->mb_nsgelem = nsegs; |
1149 | mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); |
1150 | |
1151 | sge = (struct amr_sgentry *)((char *)amr->amr_sgls + sgloff); |
1152 | for (i = 0; i < nsegs; i++, sge++) { |
1153 | sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); |
1154 | sge->sge_count = htole32(xfer->dm_segs[i].ds_len); |
1155 | } |
1156 | } |
1157 | |
1158 | bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, dmaflag); |
1159 | |
1160 | if ((ac->ac_flags & AC_NOSGL) == 0) |
1161 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, |
1162 | AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); |
1163 | |
1164 | return (0); |
1165 | } |
1166 | |
1167 | /* |
1168 | * Unmap the specified CCB's data buffer. |
1169 | */ |
1170 | void |
1171 | amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) |
1172 | { |
1173 | int dmaflag = 0; |
1174 | |
1175 | if (ac->ac_flags & AC_XFER_IN) |
1176 | dmaflag |= BUS_DMASYNC_POSTREAD; |
1177 | if (ac->ac_flags & AC_XFER_OUT) |
1178 | dmaflag |= BUS_DMASYNC_POSTWRITE; |
1179 | |
1180 | if ((ac->ac_flags & AC_NOSGL) == 0) |
1181 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, |
1182 | AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, |
1183 | BUS_DMASYNC_POSTWRITE); |
1184 | bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, |
1185 | dmaflag); |
1186 | bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); |
1187 | } |
1188 | |
1189 | /* |
1190 | * Submit a command to the controller and poll on completion. Return |
1191 | * non-zero on timeout or error. |
1192 | */ |
1193 | int |
1194 | amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) |
1195 | { |
1196 | int rv, i; |
1197 | |
1198 | mutex_spin_enter(&amr->amr_mutex); |
1199 | if ((rv = (*amr->amr_submit)(amr, ac)) != 0) { |
1200 | mutex_spin_exit(&amr->amr_mutex); |
1201 | return (rv); |
1202 | } |
1203 | TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); |
1204 | mutex_spin_exit(&amr->amr_mutex); |
1205 | |
1206 | for (i = timo * 10; i > 0; i--) { |
1207 | amr_intr(amr); |
1208 | if ((ac->ac_flags & AC_COMPLETE) != 0) |
1209 | break; |
1210 | DELAY(100); |
1211 | } |
1212 | |
1213 | if (i == 0) |
1214 | printf("%s: polled operation timed out after %d ms\n" , |
1215 | device_xname(amr->amr_dv), timo); |
1216 | |
1217 | return ((i == 0 || ac->ac_status != 0) ? EIO : 0); |
1218 | } |
1219 | |
1220 | /* |
1221 | * Submit a command to the controller and sleep on completion. Return |
1222 | * non-zero on error. |
1223 | */ |
1224 | int |
1225 | amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) |
1226 | { |
1227 | amr_ccb_enqueue(amr, ac); |
1228 | mutex_enter(&ac->ac_mutex); |
1229 | cv_wait(&ac->ac_cv, &ac->ac_mutex); |
1230 | mutex_exit(&ac->ac_mutex); |
1231 | |
1232 | return (ac->ac_status != 0 ? EIO : 0); |
1233 | } |
1234 | |
1235 | #if 0 |
1236 | /* |
1237 | * Wait for the mailbox to become available. |
1238 | */ |
1239 | static int |
1240 | amr_mbox_wait(struct amr_softc *amr) |
1241 | { |
1242 | int timo; |
1243 | |
1244 | for (timo = 10000; timo != 0; timo--) { |
1245 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1246 | sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); |
1247 | if (amr->amr_mbox->mb_cmd.mb_busy == 0) |
1248 | break; |
1249 | DELAY(100); |
1250 | } |
1251 | |
1252 | if (timo == 0) |
1253 | printf("%s: controller wedged\n" , device_xname(amr->amr_dv)); |
1254 | |
1255 | return (timo != 0 ? 0 : EAGAIN); |
1256 | } |
1257 | #endif |
1258 | |
1259 | /* |
1260 | * Tell the controller that the mailbox contains a valid command. Must be |
1261 | * called with interrupts blocked. |
1262 | */ |
1263 | static int |
1264 | amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) |
1265 | { |
1266 | int i = 0; |
1267 | u_int32_t v; |
1268 | |
1269 | amr->amr_mbox->mb_poll = 0; |
1270 | amr->amr_mbox->mb_ack = 0; |
1271 | |
1272 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1273 | sizeof(struct amr_mailbox), |
1274 | BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); |
1275 | |
1276 | v = amr_inl(amr, AMR_QREG_ODB); |
1277 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1278 | sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); |
1279 | while ((amr->amr_mbox->mb_cmd.mb_busy != 0) && (i++ < 10)) { |
1280 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1281 | sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); |
1282 | /* This is a no-op read that flushes pending mailbox updates */ |
1283 | v = amr_inl(amr, AMR_QREG_ODB); |
1284 | DELAY(1); |
1285 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1286 | sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); |
1287 | } |
1288 | |
1289 | if (amr->amr_mbox->mb_cmd.mb_busy != 0) |
1290 | return (EAGAIN); |
1291 | |
1292 | v = amr_inl(amr, AMR_QREG_IDB); |
1293 | if ((v & AMR_QIDB_SUBMIT) != 0) { |
1294 | amr->amr_mbox->mb_cmd.mb_busy = 0; |
1295 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1296 | sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); |
1297 | printf("%s: submit failed\n" , device_xname(amr->amr_dv)); |
1298 | return (EAGAIN); |
1299 | } |
1300 | |
1301 | amr->amr_mbox->mb_segment = 0; |
1302 | memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); |
1303 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1304 | sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); |
1305 | |
1306 | ac->ac_start_time = time_uptime; |
1307 | ac->ac_flags |= AC_ACTIVE; |
1308 | |
1309 | amr_outl(amr, AMR_QREG_IDB, |
1310 | (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); |
1311 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1312 | sizeof(struct amr_mailbox), BUS_DMASYNC_POSTWRITE); |
1313 | |
1314 | return (0); |
1315 | } |
1316 | |
1317 | static int |
1318 | amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) |
1319 | { |
1320 | |
1321 | amr->amr_mbox->mb_poll = 0; |
1322 | amr->amr_mbox->mb_ack = 0; |
1323 | |
1324 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1325 | sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); |
1326 | |
1327 | if (amr->amr_mbox->mb_cmd.mb_busy != 0) |
1328 | return (EAGAIN); |
1329 | |
1330 | if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { |
1331 | amr->amr_mbox->mb_cmd.mb_busy = 0; |
1332 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1333 | sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); |
1334 | return (EAGAIN); |
1335 | } |
1336 | |
1337 | amr->amr_mbox->mb_segment = 0; |
1338 | memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); |
1339 | |
1340 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1341 | sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); |
1342 | |
1343 | ac->ac_start_time = time_uptime; |
1344 | ac->ac_flags |= AC_ACTIVE; |
1345 | amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); |
1346 | |
1347 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1348 | sizeof(struct amr_mailbox), BUS_DMASYNC_POSTWRITE); |
1349 | |
1350 | return (0); |
1351 | } |
1352 | |
1353 | /* |
1354 | * Claim any work that the controller has completed; acknowledge completion, |
1355 | * save details of the completion in (mbsave). Must be called with |
1356 | * interrupts blocked. |
1357 | */ |
1358 | static int |
1359 | amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) |
1360 | { |
1361 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1362 | sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); |
1363 | |
1364 | /* Work waiting for us? */ |
1365 | if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) |
1366 | return (-1); |
1367 | |
1368 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1369 | sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); |
1370 | |
1371 | /* Save the mailbox, which contains a list of completed commands. */ |
1372 | memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); |
1373 | |
1374 | /* Ack the interrupt and mailbox transfer. */ |
1375 | amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); |
1376 | amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); |
1377 | |
1378 | /* |
1379 | * This waits for the controller to notice that we've taken the |
1380 | * command from it. It's very inefficient, and we shouldn't do it, |
1381 | * but if we remove this code, we stop completing commands under |
1382 | * load. |
1383 | * |
1384 | * Peter J says we shouldn't do this. The documentation says we |
1385 | * should. Who is right? |
1386 | */ |
1387 | while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) |
1388 | DELAY(10); |
1389 | |
1390 | return (0); |
1391 | } |
1392 | |
1393 | static int |
1394 | amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) |
1395 | { |
1396 | u_int8_t istat; |
1397 | |
1398 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1399 | sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); |
1400 | |
1401 | /* Check for valid interrupt status. */ |
1402 | if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) |
1403 | return (-1); |
1404 | |
1405 | /* Ack the interrupt. */ |
1406 | amr_outb(amr, AMR_SREG_INTR, istat); |
1407 | |
1408 | bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, |
1409 | sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); |
1410 | |
1411 | /* Save mailbox, which contains a list of completed commands. */ |
1412 | memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); |
1413 | |
1414 | /* Ack mailbox transfer. */ |
1415 | amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); |
1416 | |
1417 | return (0); |
1418 | } |
1419 | |
1420 | static void |
1421 | amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) |
1422 | { |
1423 | int i; |
1424 | |
1425 | printf("%s: " , device_xname(amr->amr_dv)); |
1426 | for (i = 0; i < 4; i++) |
1427 | printf("%08x " , ((u_int32_t *)&ac->ac_cmd)[i]); |
1428 | printf("\n" ); |
1429 | } |
1430 | |
1431 | static int |
1432 | amropen(dev_t dev, int flag, int mode, struct lwp *l) |
1433 | { |
1434 | struct amr_softc *amr; |
1435 | |
1436 | if ((amr = device_lookup_private(&amr_cd, minor(dev))) == NULL) |
1437 | return (ENXIO); |
1438 | if ((amr->amr_flags & AMRF_OPEN) != 0) |
1439 | return (EBUSY); |
1440 | |
1441 | amr->amr_flags |= AMRF_OPEN; |
1442 | return (0); |
1443 | } |
1444 | |
1445 | static int |
1446 | amrclose(dev_t dev, int flag, int mode, struct lwp *l) |
1447 | { |
1448 | struct amr_softc *amr; |
1449 | |
1450 | amr = device_lookup_private(&amr_cd, minor(dev)); |
1451 | amr->amr_flags &= ~AMRF_OPEN; |
1452 | return (0); |
1453 | } |
1454 | |
1455 | /* used below to correct for a firmware bug */ |
1456 | static unsigned long |
1457 | amrioctl_buflen(unsigned long len) |
1458 | { |
1459 | if (len <= 4 * 1024) |
1460 | return (4 * 1024); |
1461 | if (len <= 8 * 1024) |
1462 | return (8 * 1024); |
1463 | if (len <= 32 * 1024) |
1464 | return (32 * 1024); |
1465 | if (len <= 64 * 1024) |
1466 | return (64 * 1024); |
1467 | return (len); |
1468 | } |
1469 | |
1470 | static int |
1471 | amrioctl(dev_t dev, u_long cmd, void *data, int flag, |
1472 | struct lwp *l) |
1473 | { |
1474 | struct amr_softc *amr; |
1475 | struct amr_user_ioctl *au; |
1476 | struct amr_ccb *ac; |
1477 | struct amr_mailbox_ioctl *mbi; |
1478 | unsigned long au_length; |
1479 | uint8_t *au_cmd; |
1480 | int error; |
1481 | void *dp = NULL, *au_buffer; |
1482 | |
1483 | amr = device_lookup_private(&amr_cd, minor(dev)); |
1484 | |
1485 | /* This should be compatible with the FreeBSD interface */ |
1486 | |
1487 | switch (cmd) { |
1488 | case AMR_IO_VERSION: |
1489 | *(int *)data = AMR_IO_VERSION_NUMBER; |
1490 | return 0; |
1491 | case AMR_IO_COMMAND: |
1492 | error = kauth_authorize_device_passthru(l->l_cred, dev, |
1493 | KAUTH_REQ_DEVICE_RAWIO_PASSTHRU_ALL, data); |
1494 | if (error) |
1495 | return (error); |
1496 | |
1497 | au = (struct amr_user_ioctl *)data; |
1498 | au_cmd = au->au_cmd; |
1499 | au_buffer = au->au_buffer; |
1500 | au_length = au->au_length; |
1501 | break; |
1502 | default: |
1503 | return ENOTTY; |
1504 | } |
1505 | |
1506 | if (au_cmd[0] == AMR_CMD_PASS) { |
1507 | /* not yet */ |
1508 | return EOPNOTSUPP; |
1509 | } |
1510 | |
1511 | if (au_length <= 0 || au_length > MAXPHYS || au_cmd[0] == 0x06) |
1512 | return (EINVAL); |
1513 | |
1514 | /* |
1515 | * allocate kernel memory for data, doing I/O directly to user |
1516 | * buffer isn't that easy. Correct allocation size for a bug |
1517 | * in at least some versions of the device firmware, by using |
1518 | * the amrioctl_buflen() function, defined above. |
1519 | */ |
1520 | dp = malloc(amrioctl_buflen(au_length), M_DEVBUF, M_WAITOK|M_ZERO); |
1521 | if (dp == NULL) |
1522 | return ENOMEM; |
1523 | if ((error = copyin(au_buffer, dp, au_length)) != 0) |
1524 | goto out; |
1525 | |
1526 | /* direct command to controller */ |
1527 | while (amr_ccb_alloc(amr, &ac) != 0) { |
1528 | mutex_enter(&thread_mutex); |
1529 | error = cv_timedwait_sig(&thread_cv, &thread_mutex, hz); |
1530 | mutex_exit(&thread_mutex); |
1531 | if (error == EINTR) |
1532 | goto out; |
1533 | } |
1534 | |
1535 | mbi = (struct amr_mailbox_ioctl *)&ac->ac_cmd; |
1536 | mbi->mb_command = au_cmd[0]; |
1537 | mbi->mb_channel = au_cmd[1]; |
1538 | mbi->mb_param = au_cmd[2]; |
1539 | mbi->mb_pad[0] = au_cmd[3]; |
1540 | mbi->mb_drive = au_cmd[4]; |
1541 | error = amr_ccb_map(amr, ac, dp, (int)au_length, |
1542 | AC_XFER_IN | AC_XFER_OUT); |
1543 | if (error == 0) { |
1544 | error = amr_ccb_wait(amr, ac); |
1545 | amr_ccb_unmap(amr, ac); |
1546 | if (error == 0) |
1547 | error = copyout(dp, au_buffer, au_length); |
1548 | |
1549 | } |
1550 | amr_ccb_free(amr, ac); |
1551 | out: |
1552 | free(dp, M_DEVBUF); |
1553 | return (error); |
1554 | } |
1555 | |
1556 | MODULE(MODULE_CLASS_DRIVER, amr, "pci" ); |
1557 | |
1558 | #ifdef _MODULE |
1559 | #include "ioconf.c" |
1560 | #endif |
1561 | |
1562 | static int |
1563 | amr_modcmd(modcmd_t cmd, void *opaque) |
1564 | { |
1565 | int error = 0; |
1566 | |
1567 | #ifdef _MODULE |
1568 | switch (cmd) { |
1569 | case MODULE_CMD_INIT: |
1570 | error = config_init_component(cfdriver_ioconf_amr, |
1571 | cfattach_ioconf_amr, cfdata_ioconf_amr); |
1572 | break; |
1573 | case MODULE_CMD_FINI: |
1574 | error = config_fini_component(cfdriver_ioconf_amr, |
1575 | cfattach_ioconf_amr, cfdata_ioconf_amr); |
1576 | break; |
1577 | default: |
1578 | error = ENOTTY; |
1579 | break; |
1580 | } |
1581 | #endif |
1582 | |
1583 | return error; |
1584 | } |
1585 | |
1586 | |