1/******************************************************************************
2
3 Copyright (c) 2001-2013, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_api.h 251964 2013-06-18 21:28:19Z jfv $*/
34/*$NetBSD: ixgbe_api.h,v 1.6 2015/08/13 10:03:38 msaitoh Exp $*/
35
36#ifndef _IXGBE_API_H_
37#define _IXGBE_API_H_
38
39#include "ixgbe_type.h"
40
41void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map);
42
43s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);
44
45extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
46extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
47extern s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);
48extern s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw);
49
50s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);
51s32 ixgbe_init_hw(struct ixgbe_hw *hw);
52s32 ixgbe_reset_hw(struct ixgbe_hw *hw);
53s32 ixgbe_start_hw(struct ixgbe_hw *hw);
54void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw);
55s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw);
56enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw);
57s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr);
58s32 ixgbe_get_bus_info(struct ixgbe_hw *hw);
59u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw);
60u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw);
61s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
62s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num);
63s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);
64
65s32 ixgbe_identify_phy(struct ixgbe_hw *hw);
66s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
67s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
68 u16 *phy_data);
69s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
70 u16 phy_data);
71
72s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
73s32 ixgbe_check_phy_link(struct ixgbe_hw *hw,
74 ixgbe_link_speed *speed,
75 bool *link_up);
76s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw,
77 ixgbe_link_speed speed,
78 bool autoneg_wait_to_complete);
79void ixgbe_disable_tx_laser(struct ixgbe_hw *hw);
80void ixgbe_enable_tx_laser(struct ixgbe_hw *hw);
81void ixgbe_flap_tx_laser(struct ixgbe_hw *hw);
82s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
83 bool autoneg_wait_to_complete);
84s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
85 bool *link_up, bool link_up_wait_to_complete);
86s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
87 bool *autoneg);
88s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);
89s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);
90s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);
91s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index);
92
93s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw);
94s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data);
95s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
96 u16 words, u16 *data);
97s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);
98s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
99 u16 words, u16 *data);
100
101s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);
102s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw);
103
104s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
105s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
106 u32 enable_addr);
107s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index);
108s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
109s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq);
110s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
111s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
112u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);
113s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
114 u32 addr_count, ixgbe_mc_addr_itr func);
115s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
116 u32 mc_addr_count, ixgbe_mc_addr_itr func,
117 bool clear);
118void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq);
119s32 ixgbe_enable_mc(struct ixgbe_hw *hw);
120s32 ixgbe_disable_mc(struct ixgbe_hw *hw);
121s32 ixgbe_clear_vfta(struct ixgbe_hw *hw);
122s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,
123 u32 vind, bool vlan_on);
124s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
125 bool vlan_on, bool *vfta_changed);
126s32 ixgbe_fc_enable(struct ixgbe_hw *hw);
127s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
128 u8 ver);
129void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);
130s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw,
131 u16 *firmware_version);
132s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
133s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
134s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw);
135s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data);
136u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);
137s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval);
138s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw);
139s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw);
140s32 ixgbe_mng_fw_enabled(struct ixgbe_hw *hw);
141s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
142s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
143s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
144s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
145 union ixgbe_atr_hash_dword input,
146 union ixgbe_atr_hash_dword common,
147 u8 queue);
148s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
149 union ixgbe_atr_input *input_mask);
150s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
151 union ixgbe_atr_input *input,
152 u16 soft_id, u8 queue);
153s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
154 union ixgbe_atr_input *input,
155 u16 soft_id);
156s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
157 union ixgbe_atr_input *input,
158 union ixgbe_atr_input *mask,
159 u16 soft_id,
160 u8 queue);
161void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
162 union ixgbe_atr_input *mask);
163u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
164 union ixgbe_atr_hash_dword common);
165bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
166s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
167 u8 *data);
168s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
169 u8 data);
170s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);
171s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
172s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
173s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);
174s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
175void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
176s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
177 u16 *wwpn_prefix);
178s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);
179
180#endif /* _IXGBE_API_H_ */
181