1 | /* $NetBSD: nouveau_subdev_bios_init.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $ */ |
2 | |
3 | #include <sys/cdefs.h> |
4 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_bios_init.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $" ); |
5 | |
6 | #include <core/engine.h> |
7 | #include <core/device.h> |
8 | |
9 | #include <subdev/bios.h> |
10 | #include <subdev/bios/bmp.h> |
11 | #include <subdev/bios/bit.h> |
12 | #include <subdev/bios/conn.h> |
13 | #include <subdev/bios/dcb.h> |
14 | #include <subdev/bios/dp.h> |
15 | #include <subdev/bios/gpio.h> |
16 | #include <subdev/bios/init.h> |
17 | #include <subdev/bios/ramcfg.h> |
18 | #include <subdev/devinit.h> |
19 | #include <subdev/i2c.h> |
20 | #include <subdev/vga.h> |
21 | #include <subdev/gpio.h> |
22 | |
23 | #define bioslog(lvl, fmt, args...) do { \ |
24 | nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \ |
25 | init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \ |
26 | } while(0) |
27 | #define cont(fmt, args...) do { \ |
28 | if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \ |
29 | printk(fmt, ##args); \ |
30 | } while(0) |
31 | #define trace(fmt, args...) bioslog(TRACE, fmt, ##args) |
32 | #define warn(fmt, args...) bioslog(WARN, fmt, ##args) |
33 | #define error(fmt, args...) bioslog(ERROR, fmt, ##args) |
34 | |
35 | /****************************************************************************** |
36 | * init parser control flow helpers |
37 | *****************************************************************************/ |
38 | |
39 | static inline bool |
40 | init_exec(struct nvbios_init *init) |
41 | { |
42 | return (init->execute == 1) || ((init->execute & 5) == 5); |
43 | } |
44 | |
45 | static inline void |
46 | init_exec_set(struct nvbios_init *init, bool exec) |
47 | { |
48 | if (exec) init->execute &= 0xfd; |
49 | else init->execute |= 0x02; |
50 | } |
51 | |
52 | static inline void |
53 | init_exec_inv(struct nvbios_init *init) |
54 | { |
55 | init->execute ^= 0x02; |
56 | } |
57 | |
58 | static inline void |
59 | init_exec_force(struct nvbios_init *init, bool exec) |
60 | { |
61 | if (exec) init->execute |= 0x04; |
62 | else init->execute &= 0xfb; |
63 | } |
64 | |
65 | /****************************************************************************** |
66 | * init parser wrappers for normal register/i2c/whatever accessors |
67 | *****************************************************************************/ |
68 | |
69 | static inline int |
70 | init_or(struct nvbios_init *init) |
71 | { |
72 | if (init_exec(init)) { |
73 | if (init->outp) |
74 | return ffs(init->outp->or) - 1; |
75 | error("script needs OR!!\n" ); |
76 | } |
77 | return 0; |
78 | } |
79 | |
80 | static inline int |
81 | init_link(struct nvbios_init *init) |
82 | { |
83 | if (init_exec(init)) { |
84 | if (init->outp) |
85 | return !(init->outp->sorconf.link & 1); |
86 | error("script needs OR link\n" ); |
87 | } |
88 | return 0; |
89 | } |
90 | |
91 | static inline int |
92 | init_crtc(struct nvbios_init *init) |
93 | { |
94 | if (init_exec(init)) { |
95 | if (init->crtc >= 0) |
96 | return init->crtc; |
97 | error("script needs crtc\n" ); |
98 | } |
99 | return 0; |
100 | } |
101 | |
102 | static u8 |
103 | init_conn(struct nvbios_init *init) |
104 | { |
105 | struct nouveau_bios *bios = init->bios; |
106 | u8 ver, len; |
107 | u16 conn; |
108 | |
109 | if (init_exec(init)) { |
110 | if (init->outp) { |
111 | conn = init->outp->connector; |
112 | conn = dcb_conn(bios, conn, &ver, &len); |
113 | if (conn) |
114 | return nv_ro08(bios, conn); |
115 | } |
116 | |
117 | error("script needs connector type\n" ); |
118 | } |
119 | |
120 | return 0xff; |
121 | } |
122 | |
123 | static inline u32 |
124 | init_nvreg(struct nvbios_init *init, u32 reg) |
125 | { |
126 | struct nouveau_devinit *devinit = nouveau_devinit(init->bios); |
127 | |
128 | /* C51 (at least) sometimes has the lower bits set which the VBIOS |
129 | * interprets to mean that access needs to go through certain IO |
130 | * ports instead. The NVIDIA binary driver has been seen to access |
131 | * these through the NV register address, so lets assume we can |
132 | * do the same |
133 | */ |
134 | reg &= ~0x00000003; |
135 | |
136 | /* GF8+ display scripts need register addresses mangled a bit to |
137 | * select a specific CRTC/OR |
138 | */ |
139 | if (nv_device(init->bios)->card_type >= NV_50) { |
140 | if (reg & 0x80000000) { |
141 | reg += init_crtc(init) * 0x800; |
142 | reg &= ~0x80000000; |
143 | } |
144 | |
145 | if (reg & 0x40000000) { |
146 | reg += init_or(init) * 0x800; |
147 | reg &= ~0x40000000; |
148 | if (reg & 0x20000000) { |
149 | reg += init_link(init) * 0x80; |
150 | reg &= ~0x20000000; |
151 | } |
152 | } |
153 | } |
154 | |
155 | if (reg & ~0x00fffffc) |
156 | warn("unknown bits in register 0x%08x\n" , reg); |
157 | |
158 | if (devinit->mmio) |
159 | reg = devinit->mmio(devinit, reg); |
160 | return reg; |
161 | } |
162 | |
163 | static u32 |
164 | init_rd32(struct nvbios_init *init, u32 reg) |
165 | { |
166 | reg = init_nvreg(init, reg); |
167 | if (reg != ~0 && init_exec(init)) |
168 | return nv_rd32(init->subdev, reg); |
169 | return 0x00000000; |
170 | } |
171 | |
172 | static void |
173 | init_wr32(struct nvbios_init *init, u32 reg, u32 val) |
174 | { |
175 | reg = init_nvreg(init, reg); |
176 | if (reg != ~0 && init_exec(init)) |
177 | nv_wr32(init->subdev, reg, val); |
178 | } |
179 | |
180 | static u32 |
181 | init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val) |
182 | { |
183 | reg = init_nvreg(init, reg); |
184 | if (reg != ~0 && init_exec(init)) { |
185 | u32 tmp = nv_rd32(init->subdev, reg); |
186 | nv_wr32(init->subdev, reg, (tmp & ~mask) | val); |
187 | return tmp; |
188 | } |
189 | return 0x00000000; |
190 | } |
191 | |
192 | static u8 |
193 | init_rdport(struct nvbios_init *init, u16 port) |
194 | { |
195 | if (init_exec(init)) |
196 | return nv_rdport(init->subdev, init->crtc, port); |
197 | return 0x00; |
198 | } |
199 | |
200 | static void |
201 | init_wrport(struct nvbios_init *init, u16 port, u8 value) |
202 | { |
203 | if (init_exec(init)) |
204 | nv_wrport(init->subdev, init->crtc, port, value); |
205 | } |
206 | |
207 | static u8 |
208 | init_rdvgai(struct nvbios_init *init, u16 port, u8 index) |
209 | { |
210 | struct nouveau_subdev *subdev = init->subdev; |
211 | if (init_exec(init)) { |
212 | int head = init->crtc < 0 ? 0 : init->crtc; |
213 | return nv_rdvgai(subdev, head, port, index); |
214 | } |
215 | return 0x00; |
216 | } |
217 | |
218 | static void |
219 | init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value) |
220 | { |
221 | /* force head 0 for updates to cr44, it only exists on first head */ |
222 | if (nv_device(init->subdev)->card_type < NV_50) { |
223 | if (port == 0x03d4 && index == 0x44) |
224 | init->crtc = 0; |
225 | } |
226 | |
227 | if (init_exec(init)) { |
228 | int head = init->crtc < 0 ? 0 : init->crtc; |
229 | nv_wrvgai(init->subdev, head, port, index, value); |
230 | } |
231 | |
232 | /* select head 1 if cr44 write selected it */ |
233 | if (nv_device(init->subdev)->card_type < NV_50) { |
234 | if (port == 0x03d4 && index == 0x44 && value == 3) |
235 | init->crtc = 1; |
236 | } |
237 | } |
238 | |
239 | static struct nouveau_i2c_port * |
240 | init_i2c(struct nvbios_init *init, int index) |
241 | { |
242 | struct nouveau_i2c *i2c = nouveau_i2c(init->bios); |
243 | |
244 | if (index == 0xff) { |
245 | index = NV_I2C_DEFAULT(0); |
246 | if (init->outp && init->outp->i2c_upper_default) |
247 | index = NV_I2C_DEFAULT(1); |
248 | } else |
249 | if (index < 0) { |
250 | if (!init->outp) { |
251 | if (init_exec(init)) |
252 | error("script needs output for i2c\n" ); |
253 | return NULL; |
254 | } |
255 | |
256 | if (index == -2 && init->outp->location) { |
257 | index = NV_I2C_TYPE_EXTAUX(init->outp->extdev); |
258 | return i2c->find_type(i2c, index); |
259 | } |
260 | |
261 | index = init->outp->i2c_index; |
262 | } |
263 | |
264 | return i2c->find(i2c, index); |
265 | } |
266 | |
267 | static int |
268 | init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg) |
269 | { |
270 | struct nouveau_i2c_port *port = init_i2c(init, index); |
271 | if (port && init_exec(init)) |
272 | return nv_rdi2cr(port, addr, reg); |
273 | return -ENODEV; |
274 | } |
275 | |
276 | static int |
277 | init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val) |
278 | { |
279 | struct nouveau_i2c_port *port = init_i2c(init, index); |
280 | if (port && init_exec(init)) |
281 | return nv_wri2cr(port, addr, reg, val); |
282 | return -ENODEV; |
283 | } |
284 | |
285 | static int |
286 | init_rdauxr(struct nvbios_init *init, u32 addr) |
287 | { |
288 | struct nouveau_i2c_port *port = init_i2c(init, -2); |
289 | u8 data; |
290 | |
291 | if (port && init_exec(init)) { |
292 | int ret = nv_rdaux(port, addr, &data, 1); |
293 | if (ret) |
294 | return ret; |
295 | return data; |
296 | } |
297 | |
298 | return -ENODEV; |
299 | } |
300 | |
301 | static int |
302 | init_wrauxr(struct nvbios_init *init, u32 addr, u8 data) |
303 | { |
304 | struct nouveau_i2c_port *port = init_i2c(init, -2); |
305 | if (port && init_exec(init)) |
306 | return nv_wraux(port, addr, &data, 1); |
307 | return -ENODEV; |
308 | } |
309 | |
310 | static void |
311 | init_prog_pll(struct nvbios_init *init, u32 id, u32 freq) |
312 | { |
313 | struct nouveau_devinit *devinit = nouveau_devinit(init->bios); |
314 | if (devinit->pll_set && init_exec(init)) { |
315 | int ret = devinit->pll_set(devinit, id, freq); |
316 | if (ret) |
317 | warn("failed to prog pll 0x%08x to %dkHz\n" , id, freq); |
318 | } |
319 | } |
320 | |
321 | /****************************************************************************** |
322 | * parsing of bios structures that are required to execute init tables |
323 | *****************************************************************************/ |
324 | |
325 | static u16 |
326 | init_table(struct nouveau_bios *bios, u16 *len) |
327 | { |
328 | struct bit_entry bit_I; |
329 | |
330 | if (!bit_entry(bios, 'I', &bit_I)) { |
331 | *len = bit_I.length; |
332 | return bit_I.offset; |
333 | } |
334 | |
335 | if (bmp_version(bios) >= 0x0510) { |
336 | *len = 14; |
337 | return bios->bmp_offset + 75; |
338 | } |
339 | |
340 | return 0x0000; |
341 | } |
342 | |
343 | static u16 |
344 | init_table_(struct nvbios_init *init, u16 offset, const char *name) |
345 | { |
346 | struct nouveau_bios *bios = init->bios; |
347 | u16 len, data = init_table(bios, &len); |
348 | if (data) { |
349 | if (len >= offset + 2) { |
350 | data = nv_ro16(bios, data + offset); |
351 | if (data) |
352 | return data; |
353 | |
354 | warn("%s pointer invalid\n" , name); |
355 | return 0x0000; |
356 | } |
357 | |
358 | warn("init data too short for %s pointer" , name); |
359 | return 0x0000; |
360 | } |
361 | |
362 | warn("init data not found\n" ); |
363 | return 0x0000; |
364 | } |
365 | |
366 | #define init_script_table(b) init_table_((b), 0x00, "script table") |
367 | #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table") |
368 | #define init_macro_table(b) init_table_((b), 0x04, "macro table") |
369 | #define init_condition_table(b) init_table_((b), 0x06, "condition table") |
370 | #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table") |
371 | #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table") |
372 | #define init_function_table(b) init_table_((b), 0x0c, "function table") |
373 | #define init_xlat_table(b) init_table_((b), 0x10, "xlat table"); |
374 | |
375 | static u16 |
376 | init_script(struct nouveau_bios *bios, int index) |
377 | { |
378 | struct nvbios_init init = { .bios = bios }; |
379 | u16 bmp_ver = bmp_version(bios), data; |
380 | |
381 | if (bmp_ver && bmp_ver < 0x0510) { |
382 | if (index > 1 || bmp_ver < 0x0100) |
383 | return 0x0000; |
384 | |
385 | data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18); |
386 | return nv_ro16(bios, data + (index * 2)); |
387 | } |
388 | |
389 | data = init_script_table(&init); |
390 | if (data) |
391 | return nv_ro16(bios, data + (index * 2)); |
392 | |
393 | return 0x0000; |
394 | } |
395 | |
396 | static u16 |
397 | init_unknown_script(struct nouveau_bios *bios) |
398 | { |
399 | u16 len, data = init_table(bios, &len); |
400 | if (data && len >= 16) |
401 | return nv_ro16(bios, data + 14); |
402 | return 0x0000; |
403 | } |
404 | |
405 | static u8 |
406 | init_ram_restrict_group_count(struct nvbios_init *init) |
407 | { |
408 | return nvbios_ramcfg_count(init->bios); |
409 | } |
410 | |
411 | static u8 |
412 | init_ram_restrict(struct nvbios_init *init) |
413 | { |
414 | /* This appears to be the behaviour of the VBIOS parser, and *is* |
415 | * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to |
416 | * avoid fucking up the memory controller (somehow) by reading it |
417 | * on every INIT_RAM_RESTRICT_ZM_GROUP opcode. |
418 | * |
419 | * Preserving the non-caching behaviour on earlier chipsets just |
420 | * in case *not* re-reading the strap causes similar breakage. |
421 | */ |
422 | if (!init->ramcfg || init->bios->version.major < 0x70) |
423 | init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev); |
424 | return (init->ramcfg & 0x7fffffff); |
425 | } |
426 | |
427 | static u8 |
428 | init_xlat_(struct nvbios_init *init, u8 index, u8 offset) |
429 | { |
430 | struct nouveau_bios *bios = init->bios; |
431 | u16 table = init_xlat_table(init); |
432 | if (table) { |
433 | u16 data = nv_ro16(bios, table + (index * 2)); |
434 | if (data) |
435 | return nv_ro08(bios, data + offset); |
436 | warn("xlat table pointer %d invalid\n" , index); |
437 | } |
438 | return 0x00; |
439 | } |
440 | |
441 | /****************************************************************************** |
442 | * utility functions used by various init opcode handlers |
443 | *****************************************************************************/ |
444 | |
445 | static bool |
446 | init_condition_met(struct nvbios_init *init, u8 cond) |
447 | { |
448 | struct nouveau_bios *bios = init->bios; |
449 | u16 table = init_condition_table(init); |
450 | if (table) { |
451 | u32 reg = nv_ro32(bios, table + (cond * 12) + 0); |
452 | u32 msk = nv_ro32(bios, table + (cond * 12) + 4); |
453 | u32 val = nv_ro32(bios, table + (cond * 12) + 8); |
454 | trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n" , |
455 | cond, reg, msk, val); |
456 | return (init_rd32(init, reg) & msk) == val; |
457 | } |
458 | return false; |
459 | } |
460 | |
461 | static bool |
462 | init_io_condition_met(struct nvbios_init *init, u8 cond) |
463 | { |
464 | struct nouveau_bios *bios = init->bios; |
465 | u16 table = init_io_condition_table(init); |
466 | if (table) { |
467 | u16 port = nv_ro16(bios, table + (cond * 5) + 0); |
468 | u8 index = nv_ro08(bios, table + (cond * 5) + 2); |
469 | u8 mask = nv_ro08(bios, table + (cond * 5) + 3); |
470 | u8 value = nv_ro08(bios, table + (cond * 5) + 4); |
471 | trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n" , |
472 | cond, port, index, mask, value); |
473 | return (init_rdvgai(init, port, index) & mask) == value; |
474 | } |
475 | return false; |
476 | } |
477 | |
478 | static bool |
479 | init_io_flag_condition_met(struct nvbios_init *init, u8 cond) |
480 | { |
481 | struct nouveau_bios *bios = init->bios; |
482 | u16 table = init_io_flag_condition_table(init); |
483 | if (table) { |
484 | u16 port = nv_ro16(bios, table + (cond * 9) + 0); |
485 | u8 index = nv_ro08(bios, table + (cond * 9) + 2); |
486 | u8 mask = nv_ro08(bios, table + (cond * 9) + 3); |
487 | u8 shift = nv_ro08(bios, table + (cond * 9) + 4); |
488 | u16 data = nv_ro16(bios, table + (cond * 9) + 5); |
489 | u8 dmask = nv_ro08(bios, table + (cond * 9) + 7); |
490 | u8 value = nv_ro08(bios, table + (cond * 9) + 8); |
491 | u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift; |
492 | return (nv_ro08(bios, data + ioval) & dmask) == value; |
493 | } |
494 | return false; |
495 | } |
496 | |
497 | static inline u32 |
498 | init_shift(u32 data, u8 shift) |
499 | { |
500 | if (shift < 0x80) |
501 | return data >> shift; |
502 | return data << (0x100 - shift); |
503 | } |
504 | |
505 | static u32 |
506 | init_tmds_reg(struct nvbios_init *init, u8 tmds) |
507 | { |
508 | /* For mlv < 0x80, it is an index into a table of TMDS base addresses. |
509 | * For mlv == 0x80 use the "or" value of the dcb_entry indexed by |
510 | * CR58 for CR57 = 0 to index a table of offsets to the basic |
511 | * 0x6808b0 address. |
512 | * For mlv == 0x81 use the "or" value of the dcb_entry indexed by |
513 | * CR58 for CR57 = 0 to index a table of offsets to the basic |
514 | * 0x6808b0 address, and then flip the offset by 8. |
515 | */ |
516 | |
517 | const int pramdac_offset[13] = { |
518 | 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; |
519 | const u32 pramdac_table[4] = { |
520 | 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; |
521 | |
522 | if (tmds >= 0x80) { |
523 | if (init->outp) { |
524 | u32 dacoffset = pramdac_offset[init->outp->or]; |
525 | if (tmds == 0x81) |
526 | dacoffset ^= 8; |
527 | return 0x6808b0 + dacoffset; |
528 | } |
529 | |
530 | if (init_exec(init)) |
531 | error("tmds opcodes need dcb\n" ); |
532 | } else { |
533 | if (tmds < ARRAY_SIZE(pramdac_table)) |
534 | return pramdac_table[tmds]; |
535 | |
536 | error("tmds selector 0x%02x unknown\n" , tmds); |
537 | } |
538 | |
539 | return 0; |
540 | } |
541 | |
542 | /****************************************************************************** |
543 | * init opcode handlers |
544 | *****************************************************************************/ |
545 | |
546 | /** |
547 | * init_reserved - stub for various unknown/unused single-byte opcodes |
548 | * |
549 | */ |
550 | static void |
551 | init_reserved(struct nvbios_init *init) |
552 | { |
553 | u8 opcode = nv_ro08(init->bios, init->offset); |
554 | u8 length, i; |
555 | |
556 | switch (opcode) { |
557 | case 0xaa: |
558 | length = 4; |
559 | break; |
560 | default: |
561 | length = 1; |
562 | break; |
563 | } |
564 | |
565 | trace("RESERVED 0x%02x\t" , opcode); |
566 | for (i = 1; i < length; i++) |
567 | cont(" 0x%02x" , nv_ro08(init->bios, init->offset + i)); |
568 | cont("\n" ); |
569 | init->offset += length; |
570 | } |
571 | |
572 | /** |
573 | * INIT_DONE - opcode 0x71 |
574 | * |
575 | */ |
576 | static void |
577 | init_done(struct nvbios_init *init) |
578 | { |
579 | trace("DONE\n" ); |
580 | init->offset = 0x0000; |
581 | } |
582 | |
583 | /** |
584 | * INIT_IO_RESTRICT_PROG - opcode 0x32 |
585 | * |
586 | */ |
587 | static void |
588 | init_io_restrict_prog(struct nvbios_init *init) |
589 | { |
590 | struct nouveau_bios *bios = init->bios; |
591 | u16 port = nv_ro16(bios, init->offset + 1); |
592 | u8 index = nv_ro08(bios, init->offset + 3); |
593 | u8 mask = nv_ro08(bios, init->offset + 4); |
594 | u8 shift = nv_ro08(bios, init->offset + 5); |
595 | u8 count = nv_ro08(bios, init->offset + 6); |
596 | u32 reg = nv_ro32(bios, init->offset + 7); |
597 | u8 conf, i; |
598 | |
599 | trace("IO_RESTRICT_PROG\tR[0x%06x] = " |
600 | "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n" , |
601 | reg, port, index, mask, shift); |
602 | init->offset += 11; |
603 | |
604 | conf = (init_rdvgai(init, port, index) & mask) >> shift; |
605 | for (i = 0; i < count; i++) { |
606 | u32 data = nv_ro32(bios, init->offset); |
607 | |
608 | if (i == conf) { |
609 | trace("\t0x%08x *\n" , data); |
610 | init_wr32(init, reg, data); |
611 | } else { |
612 | trace("\t0x%08x\n" , data); |
613 | } |
614 | |
615 | init->offset += 4; |
616 | } |
617 | trace("}]\n" ); |
618 | } |
619 | |
620 | /** |
621 | * INIT_REPEAT - opcode 0x33 |
622 | * |
623 | */ |
624 | static void |
625 | init_repeat(struct nvbios_init *init) |
626 | { |
627 | struct nouveau_bios *bios = init->bios; |
628 | u8 count = nv_ro08(bios, init->offset + 1); |
629 | u16 repeat = init->repeat; |
630 | |
631 | trace("REPEAT\t0x%02x\n" , count); |
632 | init->offset += 2; |
633 | |
634 | init->repeat = init->offset; |
635 | init->repend = init->offset; |
636 | while (count--) { |
637 | init->offset = init->repeat; |
638 | nvbios_exec(init); |
639 | if (count) |
640 | trace("REPEAT\t0x%02x\n" , count); |
641 | } |
642 | init->offset = init->repend; |
643 | init->repeat = repeat; |
644 | } |
645 | |
646 | /** |
647 | * INIT_IO_RESTRICT_PLL - opcode 0x34 |
648 | * |
649 | */ |
650 | static void |
651 | init_io_restrict_pll(struct nvbios_init *init) |
652 | { |
653 | struct nouveau_bios *bios = init->bios; |
654 | u16 port = nv_ro16(bios, init->offset + 1); |
655 | u8 index = nv_ro08(bios, init->offset + 3); |
656 | u8 mask = nv_ro08(bios, init->offset + 4); |
657 | u8 shift = nv_ro08(bios, init->offset + 5); |
658 | s8 iofc = nv_ro08(bios, init->offset + 6); |
659 | u8 count = nv_ro08(bios, init->offset + 7); |
660 | u32 reg = nv_ro32(bios, init->offset + 8); |
661 | u8 conf, i; |
662 | |
663 | trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= " |
664 | "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n" , |
665 | reg, port, index, mask, shift, iofc); |
666 | init->offset += 12; |
667 | |
668 | conf = (init_rdvgai(init, port, index) & mask) >> shift; |
669 | for (i = 0; i < count; i++) { |
670 | u32 freq = nv_ro16(bios, init->offset) * 10; |
671 | |
672 | if (i == conf) { |
673 | trace("\t%dkHz *\n" , freq); |
674 | if (iofc > 0 && init_io_flag_condition_met(init, iofc)) |
675 | freq *= 2; |
676 | init_prog_pll(init, reg, freq); |
677 | } else { |
678 | trace("\t%dkHz\n" , freq); |
679 | } |
680 | |
681 | init->offset += 2; |
682 | } |
683 | trace("}]\n" ); |
684 | } |
685 | |
686 | /** |
687 | * INIT_END_REPEAT - opcode 0x36 |
688 | * |
689 | */ |
690 | static void |
691 | init_end_repeat(struct nvbios_init *init) |
692 | { |
693 | trace("END_REPEAT\n" ); |
694 | init->offset += 1; |
695 | |
696 | if (init->repeat) { |
697 | init->repend = init->offset; |
698 | init->offset = 0; |
699 | } |
700 | } |
701 | |
702 | /** |
703 | * INIT_COPY - opcode 0x37 |
704 | * |
705 | */ |
706 | static void |
707 | init_copy(struct nvbios_init *init) |
708 | { |
709 | struct nouveau_bios *bios = init->bios; |
710 | u32 reg = nv_ro32(bios, init->offset + 1); |
711 | u8 shift = nv_ro08(bios, init->offset + 5); |
712 | u8 smask = nv_ro08(bios, init->offset + 6); |
713 | u16 port = nv_ro16(bios, init->offset + 7); |
714 | u8 index = nv_ro08(bios, init->offset + 9); |
715 | u8 mask = nv_ro08(bios, init->offset + 10); |
716 | u8 data; |
717 | |
718 | trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= " |
719 | "((R[0x%06x] %s 0x%02x) & 0x%02x)\n" , |
720 | port, index, mask, reg, (shift & 0x80) ? "<<" : ">>" , |
721 | (shift & 0x80) ? (0x100 - shift) : shift, smask); |
722 | init->offset += 11; |
723 | |
724 | data = init_rdvgai(init, port, index) & mask; |
725 | data |= init_shift(init_rd32(init, reg), shift) & smask; |
726 | init_wrvgai(init, port, index, data); |
727 | } |
728 | |
729 | /** |
730 | * INIT_NOT - opcode 0x38 |
731 | * |
732 | */ |
733 | static void |
734 | init_not(struct nvbios_init *init) |
735 | { |
736 | trace("NOT\n" ); |
737 | init->offset += 1; |
738 | init_exec_inv(init); |
739 | } |
740 | |
741 | /** |
742 | * INIT_IO_FLAG_CONDITION - opcode 0x39 |
743 | * |
744 | */ |
745 | static void |
746 | init_io_flag_condition(struct nvbios_init *init) |
747 | { |
748 | struct nouveau_bios *bios = init->bios; |
749 | u8 cond = nv_ro08(bios, init->offset + 1); |
750 | |
751 | trace("IO_FLAG_CONDITION\t0x%02x\n" , cond); |
752 | init->offset += 2; |
753 | |
754 | if (!init_io_flag_condition_met(init, cond)) |
755 | init_exec_set(init, false); |
756 | } |
757 | |
758 | /** |
759 | * INIT_DP_CONDITION - opcode 0x3a |
760 | * |
761 | */ |
762 | static void |
763 | init_dp_condition(struct nvbios_init *init) |
764 | { |
765 | struct nouveau_bios *bios = init->bios; |
766 | struct nvbios_dpout info; |
767 | u8 cond = nv_ro08(bios, init->offset + 1); |
768 | u8 unkn = nv_ro08(bios, init->offset + 2); |
769 | u8 ver, hdr, cnt, len; |
770 | u16 data; |
771 | |
772 | trace("DP_CONDITION\t0x%02x 0x%02x\n" , cond, unkn); |
773 | init->offset += 3; |
774 | |
775 | switch (cond) { |
776 | case 0: |
777 | if (init_conn(init) != DCB_CONNECTOR_eDP) |
778 | init_exec_set(init, false); |
779 | break; |
780 | case 1: |
781 | case 2: |
782 | if ( init->outp && |
783 | (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP, |
784 | (init->outp->or << 0) | |
785 | (init->outp->sorconf.link << 6), |
786 | &ver, &hdr, &cnt, &len, &info))) |
787 | { |
788 | if (!(info.flags & cond)) |
789 | init_exec_set(init, false); |
790 | break; |
791 | } |
792 | |
793 | if (init_exec(init)) |
794 | warn("script needs dp output table data\n" ); |
795 | break; |
796 | case 5: |
797 | if (!(init_rdauxr(init, 0x0d) & 1)) |
798 | init_exec_set(init, false); |
799 | break; |
800 | default: |
801 | warn("unknown dp condition 0x%02x\n" , cond); |
802 | break; |
803 | } |
804 | } |
805 | |
806 | /** |
807 | * INIT_IO_MASK_OR - opcode 0x3b |
808 | * |
809 | */ |
810 | static void |
811 | init_io_mask_or(struct nvbios_init *init) |
812 | { |
813 | struct nouveau_bios *bios = init->bios; |
814 | u8 index = nv_ro08(bios, init->offset + 1); |
815 | u8 or = init_or(init); |
816 | u8 data; |
817 | |
818 | trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n" , index, or); |
819 | init->offset += 2; |
820 | |
821 | data = init_rdvgai(init, 0x03d4, index); |
822 | init_wrvgai(init, 0x03d4, index, data &= ~(1 << or)); |
823 | } |
824 | |
825 | /** |
826 | * INIT_IO_OR - opcode 0x3c |
827 | * |
828 | */ |
829 | static void |
830 | init_io_or(struct nvbios_init *init) |
831 | { |
832 | struct nouveau_bios *bios = init->bios; |
833 | u8 index = nv_ro08(bios, init->offset + 1); |
834 | u8 or = init_or(init); |
835 | u8 data; |
836 | |
837 | trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n" , index, or); |
838 | init->offset += 2; |
839 | |
840 | data = init_rdvgai(init, 0x03d4, index); |
841 | init_wrvgai(init, 0x03d4, index, data | (1 << or)); |
842 | } |
843 | |
844 | /** |
845 | * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49 |
846 | * |
847 | */ |
848 | static void |
849 | init_idx_addr_latched(struct nvbios_init *init) |
850 | { |
851 | struct nouveau_bios *bios = init->bios; |
852 | u32 creg = nv_ro32(bios, init->offset + 1); |
853 | u32 dreg = nv_ro32(bios, init->offset + 5); |
854 | u32 mask = nv_ro32(bios, init->offset + 9); |
855 | u32 data = nv_ro32(bios, init->offset + 13); |
856 | u8 count = nv_ro08(bios, init->offset + 17); |
857 | |
858 | trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n" , creg, dreg); |
859 | trace("\tCTRL &= 0x%08x |= 0x%08x\n" , mask, data); |
860 | init->offset += 18; |
861 | |
862 | while (count--) { |
863 | u8 iaddr = nv_ro08(bios, init->offset + 0); |
864 | u8 idata = nv_ro08(bios, init->offset + 1); |
865 | |
866 | trace("\t[0x%02x] = 0x%02x\n" , iaddr, idata); |
867 | init->offset += 2; |
868 | |
869 | init_wr32(init, dreg, idata); |
870 | init_mask(init, creg, ~mask, data | iaddr); |
871 | } |
872 | } |
873 | |
874 | /** |
875 | * INIT_IO_RESTRICT_PLL2 - opcode 0x4a |
876 | * |
877 | */ |
878 | static void |
879 | init_io_restrict_pll2(struct nvbios_init *init) |
880 | { |
881 | struct nouveau_bios *bios = init->bios; |
882 | u16 port = nv_ro16(bios, init->offset + 1); |
883 | u8 index = nv_ro08(bios, init->offset + 3); |
884 | u8 mask = nv_ro08(bios, init->offset + 4); |
885 | u8 shift = nv_ro08(bios, init->offset + 5); |
886 | u8 count = nv_ro08(bios, init->offset + 6); |
887 | u32 reg = nv_ro32(bios, init->offset + 7); |
888 | u8 conf, i; |
889 | |
890 | trace("IO_RESTRICT_PLL2\t" |
891 | "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n" , |
892 | reg, port, index, mask, shift); |
893 | init->offset += 11; |
894 | |
895 | conf = (init_rdvgai(init, port, index) & mask) >> shift; |
896 | for (i = 0; i < count; i++) { |
897 | u32 freq = nv_ro32(bios, init->offset); |
898 | if (i == conf) { |
899 | trace("\t%dkHz *\n" , freq); |
900 | init_prog_pll(init, reg, freq); |
901 | } else { |
902 | trace("\t%dkHz\n" , freq); |
903 | } |
904 | init->offset += 4; |
905 | } |
906 | trace("}]\n" ); |
907 | } |
908 | |
909 | /** |
910 | * INIT_PLL2 - opcode 0x4b |
911 | * |
912 | */ |
913 | static void |
914 | init_pll2(struct nvbios_init *init) |
915 | { |
916 | struct nouveau_bios *bios = init->bios; |
917 | u32 reg = nv_ro32(bios, init->offset + 1); |
918 | u32 freq = nv_ro32(bios, init->offset + 5); |
919 | |
920 | trace("PLL2\tR[0x%06x] =PLL= %dkHz\n" , reg, freq); |
921 | init->offset += 9; |
922 | |
923 | init_prog_pll(init, reg, freq); |
924 | } |
925 | |
926 | /** |
927 | * INIT_I2C_BYTE - opcode 0x4c |
928 | * |
929 | */ |
930 | static void |
931 | init_i2c_byte(struct nvbios_init *init) |
932 | { |
933 | struct nouveau_bios *bios = init->bios; |
934 | u8 index = nv_ro08(bios, init->offset + 1); |
935 | u8 addr = nv_ro08(bios, init->offset + 2) >> 1; |
936 | u8 count = nv_ro08(bios, init->offset + 3); |
937 | |
938 | trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n" , index, addr); |
939 | init->offset += 4; |
940 | |
941 | while (count--) { |
942 | u8 reg = nv_ro08(bios, init->offset + 0); |
943 | u8 mask = nv_ro08(bios, init->offset + 1); |
944 | u8 data = nv_ro08(bios, init->offset + 2); |
945 | int val; |
946 | |
947 | trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n" , reg, mask, data); |
948 | init->offset += 3; |
949 | |
950 | val = init_rdi2cr(init, index, addr, reg); |
951 | if (val < 0) |
952 | continue; |
953 | init_wri2cr(init, index, addr, reg, (val & mask) | data); |
954 | } |
955 | } |
956 | |
957 | /** |
958 | * INIT_ZM_I2C_BYTE - opcode 0x4d |
959 | * |
960 | */ |
961 | static void |
962 | init_zm_i2c_byte(struct nvbios_init *init) |
963 | { |
964 | struct nouveau_bios *bios = init->bios; |
965 | u8 index = nv_ro08(bios, init->offset + 1); |
966 | u8 addr = nv_ro08(bios, init->offset + 2) >> 1; |
967 | u8 count = nv_ro08(bios, init->offset + 3); |
968 | |
969 | trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n" , index, addr); |
970 | init->offset += 4; |
971 | |
972 | while (count--) { |
973 | u8 reg = nv_ro08(bios, init->offset + 0); |
974 | u8 data = nv_ro08(bios, init->offset + 1); |
975 | |
976 | trace("\t[0x%02x] = 0x%02x\n" , reg, data); |
977 | init->offset += 2; |
978 | |
979 | init_wri2cr(init, index, addr, reg, data); |
980 | } |
981 | |
982 | } |
983 | |
984 | /** |
985 | * INIT_ZM_I2C - opcode 0x4e |
986 | * |
987 | */ |
988 | static void |
989 | init_zm_i2c(struct nvbios_init *init) |
990 | { |
991 | struct nouveau_bios *bios = init->bios; |
992 | u8 index = nv_ro08(bios, init->offset + 1); |
993 | u8 addr = nv_ro08(bios, init->offset + 2) >> 1; |
994 | u8 count = nv_ro08(bios, init->offset + 3); |
995 | u8 data[256], i; |
996 | |
997 | trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n" , index, addr); |
998 | init->offset += 4; |
999 | |
1000 | for (i = 0; i < count; i++) { |
1001 | data[i] = nv_ro08(bios, init->offset); |
1002 | trace("\t0x%02x\n" , data[i]); |
1003 | init->offset++; |
1004 | } |
1005 | |
1006 | if (init_exec(init)) { |
1007 | struct nouveau_i2c_port *port = init_i2c(init, index); |
1008 | struct i2c_msg msg = { |
1009 | .addr = addr, .flags = 0, .len = count, .buf = data, |
1010 | }; |
1011 | int ret; |
1012 | |
1013 | if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1) |
1014 | warn("i2c wr failed, %d\n" , ret); |
1015 | } |
1016 | } |
1017 | |
1018 | /** |
1019 | * INIT_TMDS - opcode 0x4f |
1020 | * |
1021 | */ |
1022 | static void |
1023 | init_tmds(struct nvbios_init *init) |
1024 | { |
1025 | struct nouveau_bios *bios = init->bios; |
1026 | u8 tmds = nv_ro08(bios, init->offset + 1); |
1027 | u8 addr = nv_ro08(bios, init->offset + 2); |
1028 | u8 mask = nv_ro08(bios, init->offset + 3); |
1029 | u8 data = nv_ro08(bios, init->offset + 4); |
1030 | u32 reg = init_tmds_reg(init, tmds); |
1031 | |
1032 | trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n" , |
1033 | tmds, addr, mask, data); |
1034 | init->offset += 5; |
1035 | |
1036 | if (reg == 0) |
1037 | return; |
1038 | |
1039 | init_wr32(init, reg + 0, addr | 0x00010000); |
1040 | init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask)); |
1041 | init_wr32(init, reg + 0, addr); |
1042 | } |
1043 | |
1044 | /** |
1045 | * INIT_ZM_TMDS_GROUP - opcode 0x50 |
1046 | * |
1047 | */ |
1048 | static void |
1049 | init_zm_tmds_group(struct nvbios_init *init) |
1050 | { |
1051 | struct nouveau_bios *bios = init->bios; |
1052 | u8 tmds = nv_ro08(bios, init->offset + 1); |
1053 | u8 count = nv_ro08(bios, init->offset + 2); |
1054 | u32 reg = init_tmds_reg(init, tmds); |
1055 | |
1056 | trace("TMDS_ZM_GROUP\tT[0x%02x]\n" , tmds); |
1057 | init->offset += 3; |
1058 | |
1059 | while (count--) { |
1060 | u8 addr = nv_ro08(bios, init->offset + 0); |
1061 | u8 data = nv_ro08(bios, init->offset + 1); |
1062 | |
1063 | trace("\t[0x%02x] = 0x%02x\n" , addr, data); |
1064 | init->offset += 2; |
1065 | |
1066 | init_wr32(init, reg + 4, data); |
1067 | init_wr32(init, reg + 0, addr); |
1068 | } |
1069 | } |
1070 | |
1071 | /** |
1072 | * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51 |
1073 | * |
1074 | */ |
1075 | static void |
1076 | init_cr_idx_adr_latch(struct nvbios_init *init) |
1077 | { |
1078 | struct nouveau_bios *bios = init->bios; |
1079 | u8 addr0 = nv_ro08(bios, init->offset + 1); |
1080 | u8 addr1 = nv_ro08(bios, init->offset + 2); |
1081 | u8 base = nv_ro08(bios, init->offset + 3); |
1082 | u8 count = nv_ro08(bios, init->offset + 4); |
1083 | u8 save0; |
1084 | |
1085 | trace("CR_INDEX_ADDR C[%02x] C[%02x]\n" , addr0, addr1); |
1086 | init->offset += 5; |
1087 | |
1088 | save0 = init_rdvgai(init, 0x03d4, addr0); |
1089 | while (count--) { |
1090 | u8 data = nv_ro08(bios, init->offset); |
1091 | |
1092 | trace("\t\t[0x%02x] = 0x%02x\n" , base, data); |
1093 | init->offset += 1; |
1094 | |
1095 | init_wrvgai(init, 0x03d4, addr0, base++); |
1096 | init_wrvgai(init, 0x03d4, addr1, data); |
1097 | } |
1098 | init_wrvgai(init, 0x03d4, addr0, save0); |
1099 | } |
1100 | |
1101 | /** |
1102 | * INIT_CR - opcode 0x52 |
1103 | * |
1104 | */ |
1105 | static void |
1106 | init_cr(struct nvbios_init *init) |
1107 | { |
1108 | struct nouveau_bios *bios = init->bios; |
1109 | u8 addr = nv_ro08(bios, init->offset + 1); |
1110 | u8 mask = nv_ro08(bios, init->offset + 2); |
1111 | u8 data = nv_ro08(bios, init->offset + 3); |
1112 | u8 val; |
1113 | |
1114 | trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n" , addr, mask, data); |
1115 | init->offset += 4; |
1116 | |
1117 | val = init_rdvgai(init, 0x03d4, addr) & mask; |
1118 | init_wrvgai(init, 0x03d4, addr, val | data); |
1119 | } |
1120 | |
1121 | /** |
1122 | * INIT_ZM_CR - opcode 0x53 |
1123 | * |
1124 | */ |
1125 | static void |
1126 | init_zm_cr(struct nvbios_init *init) |
1127 | { |
1128 | struct nouveau_bios *bios = init->bios; |
1129 | u8 addr = nv_ro08(bios, init->offset + 1); |
1130 | u8 data = nv_ro08(bios, init->offset + 2); |
1131 | |
1132 | trace("ZM_CR\tC[0x%02x] = 0x%02x\n" , addr, data); |
1133 | init->offset += 3; |
1134 | |
1135 | init_wrvgai(init, 0x03d4, addr, data); |
1136 | } |
1137 | |
1138 | /** |
1139 | * INIT_ZM_CR_GROUP - opcode 0x54 |
1140 | * |
1141 | */ |
1142 | static void |
1143 | init_zm_cr_group(struct nvbios_init *init) |
1144 | { |
1145 | struct nouveau_bios *bios = init->bios; |
1146 | u8 count = nv_ro08(bios, init->offset + 1); |
1147 | |
1148 | trace("ZM_CR_GROUP\n" ); |
1149 | init->offset += 2; |
1150 | |
1151 | while (count--) { |
1152 | u8 addr = nv_ro08(bios, init->offset + 0); |
1153 | u8 data = nv_ro08(bios, init->offset + 1); |
1154 | |
1155 | trace("\t\tC[0x%02x] = 0x%02x\n" , addr, data); |
1156 | init->offset += 2; |
1157 | |
1158 | init_wrvgai(init, 0x03d4, addr, data); |
1159 | } |
1160 | } |
1161 | |
1162 | /** |
1163 | * INIT_CONDITION_TIME - opcode 0x56 |
1164 | * |
1165 | */ |
1166 | static void |
1167 | init_condition_time(struct nvbios_init *init) |
1168 | { |
1169 | struct nouveau_bios *bios = init->bios; |
1170 | u8 cond = nv_ro08(bios, init->offset + 1); |
1171 | u8 retry = nv_ro08(bios, init->offset + 2); |
1172 | u8 wait = min((u16)retry * 50, 100); |
1173 | |
1174 | trace("CONDITION_TIME\t0x%02x 0x%02x\n" , cond, retry); |
1175 | init->offset += 3; |
1176 | |
1177 | if (!init_exec(init)) |
1178 | return; |
1179 | |
1180 | while (wait--) { |
1181 | if (init_condition_met(init, cond)) |
1182 | return; |
1183 | mdelay(20); |
1184 | } |
1185 | |
1186 | init_exec_set(init, false); |
1187 | } |
1188 | |
1189 | /** |
1190 | * INIT_LTIME - opcode 0x57 |
1191 | * |
1192 | */ |
1193 | static void |
1194 | init_ltime(struct nvbios_init *init) |
1195 | { |
1196 | struct nouveau_bios *bios = init->bios; |
1197 | u16 msec = nv_ro16(bios, init->offset + 1); |
1198 | |
1199 | trace("LTIME\t0x%04x\n" , msec); |
1200 | init->offset += 3; |
1201 | |
1202 | if (init_exec(init)) |
1203 | mdelay(msec); |
1204 | } |
1205 | |
1206 | /** |
1207 | * INIT_ZM_REG_SEQUENCE - opcode 0x58 |
1208 | * |
1209 | */ |
1210 | static void |
1211 | init_zm_reg_sequence(struct nvbios_init *init) |
1212 | { |
1213 | struct nouveau_bios *bios = init->bios; |
1214 | u32 base = nv_ro32(bios, init->offset + 1); |
1215 | u8 count = nv_ro08(bios, init->offset + 5); |
1216 | |
1217 | trace("ZM_REG_SEQUENCE\t0x%02x\n" , count); |
1218 | init->offset += 6; |
1219 | |
1220 | while (count--) { |
1221 | u32 data = nv_ro32(bios, init->offset); |
1222 | |
1223 | trace("\t\tR[0x%06x] = 0x%08x\n" , base, data); |
1224 | init->offset += 4; |
1225 | |
1226 | init_wr32(init, base, data); |
1227 | base += 4; |
1228 | } |
1229 | } |
1230 | |
1231 | /** |
1232 | * INIT_SUB_DIRECT - opcode 0x5b |
1233 | * |
1234 | */ |
1235 | static void |
1236 | init_sub_direct(struct nvbios_init *init) |
1237 | { |
1238 | struct nouveau_bios *bios = init->bios; |
1239 | u16 addr = nv_ro16(bios, init->offset + 1); |
1240 | u16 save; |
1241 | |
1242 | trace("SUB_DIRECT\t0x%04x\n" , addr); |
1243 | |
1244 | if (init_exec(init)) { |
1245 | save = init->offset; |
1246 | init->offset = addr; |
1247 | if (nvbios_exec(init)) { |
1248 | error("error parsing sub-table\n" ); |
1249 | return; |
1250 | } |
1251 | init->offset = save; |
1252 | } |
1253 | |
1254 | init->offset += 3; |
1255 | } |
1256 | |
1257 | /** |
1258 | * INIT_JUMP - opcode 0x5c |
1259 | * |
1260 | */ |
1261 | static void |
1262 | init_jump(struct nvbios_init *init) |
1263 | { |
1264 | struct nouveau_bios *bios = init->bios; |
1265 | u16 offset = nv_ro16(bios, init->offset + 1); |
1266 | |
1267 | trace("JUMP\t0x%04x\n" , offset); |
1268 | |
1269 | if (init_exec(init)) |
1270 | init->offset = offset; |
1271 | else |
1272 | init->offset += 3; |
1273 | } |
1274 | |
1275 | /** |
1276 | * INIT_I2C_IF - opcode 0x5e |
1277 | * |
1278 | */ |
1279 | static void |
1280 | init_i2c_if(struct nvbios_init *init) |
1281 | { |
1282 | struct nouveau_bios *bios = init->bios; |
1283 | u8 index = nv_ro08(bios, init->offset + 1); |
1284 | u8 addr = nv_ro08(bios, init->offset + 2); |
1285 | u8 reg = nv_ro08(bios, init->offset + 3); |
1286 | u8 mask = nv_ro08(bios, init->offset + 4); |
1287 | u8 data = nv_ro08(bios, init->offset + 5); |
1288 | u8 value; |
1289 | |
1290 | trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n" , |
1291 | index, addr, reg, mask, data); |
1292 | init->offset += 6; |
1293 | init_exec_force(init, true); |
1294 | |
1295 | value = init_rdi2cr(init, index, addr, reg); |
1296 | if ((value & mask) != data) |
1297 | init_exec_set(init, false); |
1298 | |
1299 | init_exec_force(init, false); |
1300 | } |
1301 | |
1302 | /** |
1303 | * INIT_COPY_NV_REG - opcode 0x5f |
1304 | * |
1305 | */ |
1306 | static void |
1307 | init_copy_nv_reg(struct nvbios_init *init) |
1308 | { |
1309 | struct nouveau_bios *bios = init->bios; |
1310 | u32 sreg = nv_ro32(bios, init->offset + 1); |
1311 | u8 shift = nv_ro08(bios, init->offset + 5); |
1312 | u32 smask = nv_ro32(bios, init->offset + 6); |
1313 | u32 sxor = nv_ro32(bios, init->offset + 10); |
1314 | u32 dreg = nv_ro32(bios, init->offset + 14); |
1315 | u32 dmask = nv_ro32(bios, init->offset + 18); |
1316 | u32 data; |
1317 | |
1318 | trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= " |
1319 | "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n" , |
1320 | dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>" , |
1321 | (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor); |
1322 | init->offset += 22; |
1323 | |
1324 | data = init_shift(init_rd32(init, sreg), shift); |
1325 | init_mask(init, dreg, ~dmask, (data & smask) ^ sxor); |
1326 | } |
1327 | |
1328 | /** |
1329 | * INIT_ZM_INDEX_IO - opcode 0x62 |
1330 | * |
1331 | */ |
1332 | static void |
1333 | init_zm_index_io(struct nvbios_init *init) |
1334 | { |
1335 | struct nouveau_bios *bios = init->bios; |
1336 | u16 port = nv_ro16(bios, init->offset + 1); |
1337 | u8 index = nv_ro08(bios, init->offset + 3); |
1338 | u8 data = nv_ro08(bios, init->offset + 4); |
1339 | |
1340 | trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n" , port, index, data); |
1341 | init->offset += 5; |
1342 | |
1343 | init_wrvgai(init, port, index, data); |
1344 | } |
1345 | |
1346 | /** |
1347 | * INIT_COMPUTE_MEM - opcode 0x63 |
1348 | * |
1349 | */ |
1350 | static void |
1351 | init_compute_mem(struct nvbios_init *init) |
1352 | { |
1353 | struct nouveau_devinit *devinit = nouveau_devinit(init->bios); |
1354 | |
1355 | trace("COMPUTE_MEM\n" ); |
1356 | init->offset += 1; |
1357 | |
1358 | init_exec_force(init, true); |
1359 | if (init_exec(init) && devinit->meminit) |
1360 | devinit->meminit(devinit); |
1361 | init_exec_force(init, false); |
1362 | } |
1363 | |
1364 | /** |
1365 | * INIT_RESET - opcode 0x65 |
1366 | * |
1367 | */ |
1368 | static void |
1369 | init_reset(struct nvbios_init *init) |
1370 | { |
1371 | struct nouveau_bios *bios = init->bios; |
1372 | u32 reg = nv_ro32(bios, init->offset + 1); |
1373 | u32 data1 = nv_ro32(bios, init->offset + 5); |
1374 | u32 data2 = nv_ro32(bios, init->offset + 9); |
1375 | u32 savepci19; |
1376 | |
1377 | trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x" , reg, data1, data2); |
1378 | init->offset += 13; |
1379 | init_exec_force(init, true); |
1380 | |
1381 | savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000); |
1382 | init_wr32(init, reg, data1); |
1383 | udelay(10); |
1384 | init_wr32(init, reg, data2); |
1385 | init_wr32(init, 0x00184c, savepci19); |
1386 | init_mask(init, 0x001850, 0x00000001, 0x00000000); |
1387 | |
1388 | init_exec_force(init, false); |
1389 | } |
1390 | |
1391 | /** |
1392 | * INIT_CONFIGURE_MEM - opcode 0x66 |
1393 | * |
1394 | */ |
1395 | static u16 |
1396 | init_configure_mem_clk(struct nvbios_init *init) |
1397 | { |
1398 | u16 mdata = bmp_mem_init_table(init->bios); |
1399 | if (mdata) |
1400 | mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66; |
1401 | return mdata; |
1402 | } |
1403 | |
1404 | static void |
1405 | init_configure_mem(struct nvbios_init *init) |
1406 | { |
1407 | struct nouveau_bios *bios = init->bios; |
1408 | u16 mdata, sdata; |
1409 | u32 addr, data; |
1410 | |
1411 | trace("CONFIGURE_MEM\n" ); |
1412 | init->offset += 1; |
1413 | |
1414 | if (bios->version.major > 2) { |
1415 | init_done(init); |
1416 | return; |
1417 | } |
1418 | init_exec_force(init, true); |
1419 | |
1420 | mdata = init_configure_mem_clk(init); |
1421 | sdata = bmp_sdr_seq_table(bios); |
1422 | if (nv_ro08(bios, mdata) & 0x01) |
1423 | sdata = bmp_ddr_seq_table(bios); |
1424 | mdata += 6; /* skip to data */ |
1425 | |
1426 | data = init_rdvgai(init, 0x03c4, 0x01); |
1427 | init_wrvgai(init, 0x03c4, 0x01, data | 0x20); |
1428 | |
1429 | for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) { |
1430 | switch (addr) { |
1431 | case 0x10021c: /* CKE_NORMAL */ |
1432 | case 0x1002d0: /* CMD_REFRESH */ |
1433 | case 0x1002d4: /* CMD_PRECHARGE */ |
1434 | data = 0x00000001; |
1435 | break; |
1436 | default: |
1437 | data = nv_ro32(bios, mdata); |
1438 | mdata += 4; |
1439 | if (data == 0xffffffff) |
1440 | continue; |
1441 | break; |
1442 | } |
1443 | |
1444 | init_wr32(init, addr, data); |
1445 | } |
1446 | |
1447 | init_exec_force(init, false); |
1448 | } |
1449 | |
1450 | /** |
1451 | * INIT_CONFIGURE_CLK - opcode 0x67 |
1452 | * |
1453 | */ |
1454 | static void |
1455 | init_configure_clk(struct nvbios_init *init) |
1456 | { |
1457 | struct nouveau_bios *bios = init->bios; |
1458 | u16 mdata, clock; |
1459 | |
1460 | trace("CONFIGURE_CLK\n" ); |
1461 | init->offset += 1; |
1462 | |
1463 | if (bios->version.major > 2) { |
1464 | init_done(init); |
1465 | return; |
1466 | } |
1467 | init_exec_force(init, true); |
1468 | |
1469 | mdata = init_configure_mem_clk(init); |
1470 | |
1471 | /* NVPLL */ |
1472 | clock = nv_ro16(bios, mdata + 4) * 10; |
1473 | init_prog_pll(init, 0x680500, clock); |
1474 | |
1475 | /* MPLL */ |
1476 | clock = nv_ro16(bios, mdata + 2) * 10; |
1477 | if (nv_ro08(bios, mdata) & 0x01) |
1478 | clock *= 2; |
1479 | init_prog_pll(init, 0x680504, clock); |
1480 | |
1481 | init_exec_force(init, false); |
1482 | } |
1483 | |
1484 | /** |
1485 | * INIT_CONFIGURE_PREINIT - opcode 0x68 |
1486 | * |
1487 | */ |
1488 | static void |
1489 | init_configure_preinit(struct nvbios_init *init) |
1490 | { |
1491 | struct nouveau_bios *bios = init->bios; |
1492 | u32 strap; |
1493 | |
1494 | trace("CONFIGURE_PREINIT\n" ); |
1495 | init->offset += 1; |
1496 | |
1497 | if (bios->version.major > 2) { |
1498 | init_done(init); |
1499 | return; |
1500 | } |
1501 | init_exec_force(init, true); |
1502 | |
1503 | strap = init_rd32(init, 0x101000); |
1504 | strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6); |
1505 | init_wrvgai(init, 0x03d4, 0x3c, strap); |
1506 | |
1507 | init_exec_force(init, false); |
1508 | } |
1509 | |
1510 | /** |
1511 | * INIT_IO - opcode 0x69 |
1512 | * |
1513 | */ |
1514 | static void |
1515 | init_io(struct nvbios_init *init) |
1516 | { |
1517 | struct nouveau_bios *bios = init->bios; |
1518 | u16 port = nv_ro16(bios, init->offset + 1); |
1519 | u8 mask = nv_ro16(bios, init->offset + 3); |
1520 | u8 data = nv_ro16(bios, init->offset + 4); |
1521 | u8 value; |
1522 | |
1523 | trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n" , port, mask, data); |
1524 | init->offset += 5; |
1525 | |
1526 | /* ummm.. yes.. should really figure out wtf this is and why it's |
1527 | * needed some day.. it's almost certainly wrong, but, it also |
1528 | * somehow makes things work... |
1529 | */ |
1530 | if (nv_device(init->bios)->card_type >= NV_50 && |
1531 | port == 0x03c3 && data == 0x01) { |
1532 | init_mask(init, 0x614100, 0xf0800000, 0x00800000); |
1533 | init_mask(init, 0x00e18c, 0x00020000, 0x00020000); |
1534 | init_mask(init, 0x614900, 0xf0800000, 0x00800000); |
1535 | init_mask(init, 0x000200, 0x40000000, 0x00000000); |
1536 | mdelay(10); |
1537 | init_mask(init, 0x00e18c, 0x00020000, 0x00000000); |
1538 | init_mask(init, 0x000200, 0x40000000, 0x40000000); |
1539 | init_wr32(init, 0x614100, 0x00800018); |
1540 | init_wr32(init, 0x614900, 0x00800018); |
1541 | mdelay(10); |
1542 | init_wr32(init, 0x614100, 0x10000018); |
1543 | init_wr32(init, 0x614900, 0x10000018); |
1544 | } |
1545 | |
1546 | value = init_rdport(init, port) & mask; |
1547 | init_wrport(init, port, data | value); |
1548 | } |
1549 | |
1550 | /** |
1551 | * INIT_SUB - opcode 0x6b |
1552 | * |
1553 | */ |
1554 | static void |
1555 | init_sub(struct nvbios_init *init) |
1556 | { |
1557 | struct nouveau_bios *bios = init->bios; |
1558 | u8 index = nv_ro08(bios, init->offset + 1); |
1559 | u16 addr, save; |
1560 | |
1561 | trace("SUB\t0x%02x\n" , index); |
1562 | |
1563 | addr = init_script(bios, index); |
1564 | if (addr && init_exec(init)) { |
1565 | save = init->offset; |
1566 | init->offset = addr; |
1567 | if (nvbios_exec(init)) { |
1568 | error("error parsing sub-table\n" ); |
1569 | return; |
1570 | } |
1571 | init->offset = save; |
1572 | } |
1573 | |
1574 | init->offset += 2; |
1575 | } |
1576 | |
1577 | /** |
1578 | * INIT_RAM_CONDITION - opcode 0x6d |
1579 | * |
1580 | */ |
1581 | static void |
1582 | init_ram_condition(struct nvbios_init *init) |
1583 | { |
1584 | struct nouveau_bios *bios = init->bios; |
1585 | u8 mask = nv_ro08(bios, init->offset + 1); |
1586 | u8 value = nv_ro08(bios, init->offset + 2); |
1587 | |
1588 | trace("RAM_CONDITION\t" |
1589 | "(R[0x100000] & 0x%02x) == 0x%02x\n" , mask, value); |
1590 | init->offset += 3; |
1591 | |
1592 | if ((init_rd32(init, 0x100000) & mask) != value) |
1593 | init_exec_set(init, false); |
1594 | } |
1595 | |
1596 | /** |
1597 | * INIT_NV_REG - opcode 0x6e |
1598 | * |
1599 | */ |
1600 | static void |
1601 | init_nv_reg(struct nvbios_init *init) |
1602 | { |
1603 | struct nouveau_bios *bios = init->bios; |
1604 | u32 reg = nv_ro32(bios, init->offset + 1); |
1605 | u32 mask = nv_ro32(bios, init->offset + 5); |
1606 | u32 data = nv_ro32(bios, init->offset + 9); |
1607 | |
1608 | trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n" , reg, mask, data); |
1609 | init->offset += 13; |
1610 | |
1611 | init_mask(init, reg, ~mask, data); |
1612 | } |
1613 | |
1614 | /** |
1615 | * INIT_MACRO - opcode 0x6f |
1616 | * |
1617 | */ |
1618 | static void |
1619 | init_macro(struct nvbios_init *init) |
1620 | { |
1621 | struct nouveau_bios *bios = init->bios; |
1622 | u8 macro = nv_ro08(bios, init->offset + 1); |
1623 | u16 table; |
1624 | |
1625 | trace("MACRO\t0x%02x\n" , macro); |
1626 | |
1627 | table = init_macro_table(init); |
1628 | if (table) { |
1629 | u32 addr = nv_ro32(bios, table + (macro * 8) + 0); |
1630 | u32 data = nv_ro32(bios, table + (macro * 8) + 4); |
1631 | trace("\t\tR[0x%06x] = 0x%08x\n" , addr, data); |
1632 | init_wr32(init, addr, data); |
1633 | } |
1634 | |
1635 | init->offset += 2; |
1636 | } |
1637 | |
1638 | /** |
1639 | * INIT_RESUME - opcode 0x72 |
1640 | * |
1641 | */ |
1642 | static void |
1643 | init_resume(struct nvbios_init *init) |
1644 | { |
1645 | trace("RESUME\n" ); |
1646 | init->offset += 1; |
1647 | init_exec_set(init, true); |
1648 | } |
1649 | |
1650 | /** |
1651 | * INIT_TIME - opcode 0x74 |
1652 | * |
1653 | */ |
1654 | static void |
1655 | init_time(struct nvbios_init *init) |
1656 | { |
1657 | struct nouveau_bios *bios = init->bios; |
1658 | u16 usec = nv_ro16(bios, init->offset + 1); |
1659 | |
1660 | trace("TIME\t0x%04x\n" , usec); |
1661 | init->offset += 3; |
1662 | |
1663 | if (init_exec(init)) { |
1664 | if (usec < 1000) |
1665 | udelay(usec); |
1666 | else |
1667 | mdelay((usec + 900) / 1000); |
1668 | } |
1669 | } |
1670 | |
1671 | /** |
1672 | * INIT_CONDITION - opcode 0x75 |
1673 | * |
1674 | */ |
1675 | static void |
1676 | init_condition(struct nvbios_init *init) |
1677 | { |
1678 | struct nouveau_bios *bios = init->bios; |
1679 | u8 cond = nv_ro08(bios, init->offset + 1); |
1680 | |
1681 | trace("CONDITION\t0x%02x\n" , cond); |
1682 | init->offset += 2; |
1683 | |
1684 | if (!init_condition_met(init, cond)) |
1685 | init_exec_set(init, false); |
1686 | } |
1687 | |
1688 | /** |
1689 | * INIT_IO_CONDITION - opcode 0x76 |
1690 | * |
1691 | */ |
1692 | static void |
1693 | init_io_condition(struct nvbios_init *init) |
1694 | { |
1695 | struct nouveau_bios *bios = init->bios; |
1696 | u8 cond = nv_ro08(bios, init->offset + 1); |
1697 | |
1698 | trace("IO_CONDITION\t0x%02x\n" , cond); |
1699 | init->offset += 2; |
1700 | |
1701 | if (!init_io_condition_met(init, cond)) |
1702 | init_exec_set(init, false); |
1703 | } |
1704 | |
1705 | /** |
1706 | * INIT_INDEX_IO - opcode 0x78 |
1707 | * |
1708 | */ |
1709 | static void |
1710 | init_index_io(struct nvbios_init *init) |
1711 | { |
1712 | struct nouveau_bios *bios = init->bios; |
1713 | u16 port = nv_ro16(bios, init->offset + 1); |
1714 | u8 index = nv_ro16(bios, init->offset + 3); |
1715 | u8 mask = nv_ro08(bios, init->offset + 4); |
1716 | u8 data = nv_ro08(bios, init->offset + 5); |
1717 | u8 value; |
1718 | |
1719 | trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n" , |
1720 | port, index, mask, data); |
1721 | init->offset += 6; |
1722 | |
1723 | value = init_rdvgai(init, port, index) & mask; |
1724 | init_wrvgai(init, port, index, data | value); |
1725 | } |
1726 | |
1727 | /** |
1728 | * INIT_PLL - opcode 0x79 |
1729 | * |
1730 | */ |
1731 | static void |
1732 | init_pll(struct nvbios_init *init) |
1733 | { |
1734 | struct nouveau_bios *bios = init->bios; |
1735 | u32 reg = nv_ro32(bios, init->offset + 1); |
1736 | u32 freq = nv_ro16(bios, init->offset + 5) * 10; |
1737 | |
1738 | trace("PLL\tR[0x%06x] =PLL= %dkHz\n" , reg, freq); |
1739 | init->offset += 7; |
1740 | |
1741 | init_prog_pll(init, reg, freq); |
1742 | } |
1743 | |
1744 | /** |
1745 | * INIT_ZM_REG - opcode 0x7a |
1746 | * |
1747 | */ |
1748 | static void |
1749 | init_zm_reg(struct nvbios_init *init) |
1750 | { |
1751 | struct nouveau_bios *bios = init->bios; |
1752 | u32 addr = nv_ro32(bios, init->offset + 1); |
1753 | u32 data = nv_ro32(bios, init->offset + 5); |
1754 | |
1755 | trace("ZM_REG\tR[0x%06x] = 0x%08x\n" , addr, data); |
1756 | init->offset += 9; |
1757 | |
1758 | if (addr == 0x000200) |
1759 | data |= 0x00000001; |
1760 | |
1761 | init_wr32(init, addr, data); |
1762 | } |
1763 | |
1764 | /** |
1765 | * INIT_RAM_RESTRICT_PLL - opcde 0x87 |
1766 | * |
1767 | */ |
1768 | static void |
1769 | init_ram_restrict_pll(struct nvbios_init *init) |
1770 | { |
1771 | struct nouveau_bios *bios = init->bios; |
1772 | u8 type = nv_ro08(bios, init->offset + 1); |
1773 | u8 count = init_ram_restrict_group_count(init); |
1774 | u8 strap = init_ram_restrict(init); |
1775 | u8 cconf; |
1776 | |
1777 | trace("RAM_RESTRICT_PLL\t0x%02x\n" , type); |
1778 | init->offset += 2; |
1779 | |
1780 | for (cconf = 0; cconf < count; cconf++) { |
1781 | u32 freq = nv_ro32(bios, init->offset); |
1782 | |
1783 | if (cconf == strap) { |
1784 | trace("%dkHz *\n" , freq); |
1785 | init_prog_pll(init, type, freq); |
1786 | } else { |
1787 | trace("%dkHz\n" , freq); |
1788 | } |
1789 | |
1790 | init->offset += 4; |
1791 | } |
1792 | } |
1793 | |
1794 | /** |
1795 | * INIT_GPIO - opcode 0x8e |
1796 | * |
1797 | */ |
1798 | static void |
1799 | init_gpio(struct nvbios_init *init) |
1800 | { |
1801 | struct nouveau_gpio *gpio = nouveau_gpio(init->bios); |
1802 | |
1803 | trace("GPIO\n" ); |
1804 | init->offset += 1; |
1805 | |
1806 | if (init_exec(init) && gpio && gpio->reset) |
1807 | gpio->reset(gpio, DCB_GPIO_UNUSED); |
1808 | } |
1809 | |
1810 | /** |
1811 | * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f |
1812 | * |
1813 | */ |
1814 | static void |
1815 | init_ram_restrict_zm_reg_group(struct nvbios_init *init) |
1816 | { |
1817 | struct nouveau_bios *bios = init->bios; |
1818 | u32 addr = nv_ro32(bios, init->offset + 1); |
1819 | u8 incr = nv_ro08(bios, init->offset + 5); |
1820 | u8 num = nv_ro08(bios, init->offset + 6); |
1821 | u8 count = init_ram_restrict_group_count(init); |
1822 | u8 index = init_ram_restrict(init); |
1823 | u8 i, j; |
1824 | |
1825 | trace("RAM_RESTRICT_ZM_REG_GROUP\t" |
1826 | "R[0x%08x] 0x%02x 0x%02x\n" , addr, incr, num); |
1827 | init->offset += 7; |
1828 | |
1829 | for (i = 0; i < num; i++) { |
1830 | trace("\tR[0x%06x] = {\n" , addr); |
1831 | for (j = 0; j < count; j++) { |
1832 | u32 data = nv_ro32(bios, init->offset); |
1833 | |
1834 | if (j == index) { |
1835 | trace("\t\t0x%08x *\n" , data); |
1836 | init_wr32(init, addr, data); |
1837 | } else { |
1838 | trace("\t\t0x%08x\n" , data); |
1839 | } |
1840 | |
1841 | init->offset += 4; |
1842 | } |
1843 | trace("\t}\n" ); |
1844 | addr += incr; |
1845 | } |
1846 | } |
1847 | |
1848 | /** |
1849 | * INIT_COPY_ZM_REG - opcode 0x90 |
1850 | * |
1851 | */ |
1852 | static void |
1853 | init_copy_zm_reg(struct nvbios_init *init) |
1854 | { |
1855 | struct nouveau_bios *bios = init->bios; |
1856 | u32 sreg = nv_ro32(bios, init->offset + 1); |
1857 | u32 dreg = nv_ro32(bios, init->offset + 5); |
1858 | |
1859 | trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n" , dreg, sreg); |
1860 | init->offset += 9; |
1861 | |
1862 | init_wr32(init, dreg, init_rd32(init, sreg)); |
1863 | } |
1864 | |
1865 | /** |
1866 | * INIT_ZM_REG_GROUP - opcode 0x91 |
1867 | * |
1868 | */ |
1869 | static void |
1870 | init_zm_reg_group(struct nvbios_init *init) |
1871 | { |
1872 | struct nouveau_bios *bios = init->bios; |
1873 | u32 addr = nv_ro32(bios, init->offset + 1); |
1874 | u8 count = nv_ro08(bios, init->offset + 5); |
1875 | |
1876 | trace("ZM_REG_GROUP\tR[0x%06x] =\n" , addr); |
1877 | init->offset += 6; |
1878 | |
1879 | while (count--) { |
1880 | u32 data = nv_ro32(bios, init->offset); |
1881 | trace("\t0x%08x\n" , data); |
1882 | init_wr32(init, addr, data); |
1883 | init->offset += 4; |
1884 | } |
1885 | } |
1886 | |
1887 | /** |
1888 | * INIT_XLAT - opcode 0x96 |
1889 | * |
1890 | */ |
1891 | static void |
1892 | init_xlat(struct nvbios_init *init) |
1893 | { |
1894 | struct nouveau_bios *bios = init->bios; |
1895 | u32 saddr = nv_ro32(bios, init->offset + 1); |
1896 | u8 sshift = nv_ro08(bios, init->offset + 5); |
1897 | u8 smask = nv_ro08(bios, init->offset + 6); |
1898 | u8 index = nv_ro08(bios, init->offset + 7); |
1899 | u32 daddr = nv_ro32(bios, init->offset + 8); |
1900 | u32 dmask = nv_ro32(bios, init->offset + 12); |
1901 | u8 shift = nv_ro08(bios, init->offset + 16); |
1902 | u32 data; |
1903 | |
1904 | trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= " |
1905 | "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n" , |
1906 | daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>" , |
1907 | (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift); |
1908 | init->offset += 17; |
1909 | |
1910 | data = init_shift(init_rd32(init, saddr), sshift) & smask; |
1911 | data = init_xlat_(init, index, data) << shift; |
1912 | init_mask(init, daddr, ~dmask, data); |
1913 | } |
1914 | |
1915 | /** |
1916 | * INIT_ZM_MASK_ADD - opcode 0x97 |
1917 | * |
1918 | */ |
1919 | static void |
1920 | init_zm_mask_add(struct nvbios_init *init) |
1921 | { |
1922 | struct nouveau_bios *bios = init->bios; |
1923 | u32 addr = nv_ro32(bios, init->offset + 1); |
1924 | u32 mask = nv_ro32(bios, init->offset + 5); |
1925 | u32 add = nv_ro32(bios, init->offset + 9); |
1926 | u32 data; |
1927 | |
1928 | trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n" , addr, mask, add); |
1929 | init->offset += 13; |
1930 | |
1931 | data = init_rd32(init, addr); |
1932 | data = (data & mask) | ((data + add) & ~mask); |
1933 | init_wr32(init, addr, data); |
1934 | } |
1935 | |
1936 | /** |
1937 | * INIT_AUXCH - opcode 0x98 |
1938 | * |
1939 | */ |
1940 | static void |
1941 | init_auxch(struct nvbios_init *init) |
1942 | { |
1943 | struct nouveau_bios *bios = init->bios; |
1944 | u32 addr = nv_ro32(bios, init->offset + 1); |
1945 | u8 count = nv_ro08(bios, init->offset + 5); |
1946 | |
1947 | trace("AUXCH\tAUX[0x%08x] 0x%02x\n" , addr, count); |
1948 | init->offset += 6; |
1949 | |
1950 | while (count--) { |
1951 | u8 mask = nv_ro08(bios, init->offset + 0); |
1952 | u8 data = nv_ro08(bios, init->offset + 1); |
1953 | trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n" , addr, mask, data); |
1954 | mask = init_rdauxr(init, addr) & mask; |
1955 | init_wrauxr(init, addr, mask | data); |
1956 | init->offset += 2; |
1957 | } |
1958 | } |
1959 | |
1960 | /** |
1961 | * INIT_AUXCH - opcode 0x99 |
1962 | * |
1963 | */ |
1964 | static void |
1965 | init_zm_auxch(struct nvbios_init *init) |
1966 | { |
1967 | struct nouveau_bios *bios = init->bios; |
1968 | u32 addr = nv_ro32(bios, init->offset + 1); |
1969 | u8 count = nv_ro08(bios, init->offset + 5); |
1970 | |
1971 | trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n" , addr, count); |
1972 | init->offset += 6; |
1973 | |
1974 | while (count--) { |
1975 | u8 data = nv_ro08(bios, init->offset + 0); |
1976 | trace("\tAUX[0x%08x] = 0x%02x\n" , addr, data); |
1977 | init_wrauxr(init, addr, data); |
1978 | init->offset += 1; |
1979 | } |
1980 | } |
1981 | |
1982 | /** |
1983 | * INIT_I2C_LONG_IF - opcode 0x9a |
1984 | * |
1985 | */ |
1986 | static void |
1987 | init_i2c_long_if(struct nvbios_init *init) |
1988 | { |
1989 | struct nouveau_bios *bios = init->bios; |
1990 | u8 index = nv_ro08(bios, init->offset + 1); |
1991 | u8 addr = nv_ro08(bios, init->offset + 2) >> 1; |
1992 | u8 reglo = nv_ro08(bios, init->offset + 3); |
1993 | u8 reghi = nv_ro08(bios, init->offset + 4); |
1994 | u8 mask = nv_ro08(bios, init->offset + 5); |
1995 | u8 data = nv_ro08(bios, init->offset + 6); |
1996 | struct nouveau_i2c_port *port; |
1997 | |
1998 | trace("I2C_LONG_IF\t" |
1999 | "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n" , |
2000 | index, addr, reglo, reghi, mask, data); |
2001 | init->offset += 7; |
2002 | |
2003 | port = init_i2c(init, index); |
2004 | if (port) { |
2005 | u8 i[2] = { reghi, reglo }; |
2006 | u8 o[1] = {}; |
2007 | struct i2c_msg msg[] = { |
2008 | { .addr = addr, .flags = 0, .len = 2, .buf = i }, |
2009 | { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o } |
2010 | }; |
2011 | int ret; |
2012 | |
2013 | ret = i2c_transfer(&port->adapter, msg, 2); |
2014 | if (ret == 2 && ((o[0] & mask) == data)) |
2015 | return; |
2016 | } |
2017 | |
2018 | init_exec_set(init, false); |
2019 | } |
2020 | |
2021 | /** |
2022 | * INIT_GPIO_NE - opcode 0xa9 |
2023 | * |
2024 | */ |
2025 | static void |
2026 | init_gpio_ne(struct nvbios_init *init) |
2027 | { |
2028 | struct nouveau_bios *bios = init->bios; |
2029 | struct nouveau_gpio *gpio = nouveau_gpio(bios); |
2030 | struct dcb_gpio_func func; |
2031 | u8 count = nv_ro08(bios, init->offset + 1); |
2032 | u8 idx = 0, ver, len; |
2033 | u16 data, i; |
2034 | |
2035 | trace("GPIO_NE\t" ); |
2036 | init->offset += 2; |
2037 | |
2038 | for (i = init->offset; i < init->offset + count; i++) |
2039 | cont("0x%02x " , nv_ro08(bios, i)); |
2040 | cont("\n" ); |
2041 | |
2042 | while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) { |
2043 | if (func.func != DCB_GPIO_UNUSED) { |
2044 | for (i = init->offset; i < init->offset + count; i++) { |
2045 | if (func.func == nv_ro08(bios, i)) |
2046 | break; |
2047 | } |
2048 | |
2049 | trace("\tFUNC[0x%02x]" , func.func); |
2050 | if (i == (init->offset + count)) { |
2051 | cont(" *" ); |
2052 | if (init_exec(init) && gpio && gpio->reset) |
2053 | gpio->reset(gpio, func.func); |
2054 | } |
2055 | cont("\n" ); |
2056 | } |
2057 | } |
2058 | |
2059 | init->offset += count; |
2060 | } |
2061 | |
2062 | static struct nvbios_init_opcode { |
2063 | void (*exec)(struct nvbios_init *); |
2064 | } init_opcode[] = { |
2065 | [0x32] = { init_io_restrict_prog }, |
2066 | [0x33] = { init_repeat }, |
2067 | [0x34] = { init_io_restrict_pll }, |
2068 | [0x36] = { init_end_repeat }, |
2069 | [0x37] = { init_copy }, |
2070 | [0x38] = { init_not }, |
2071 | [0x39] = { init_io_flag_condition }, |
2072 | [0x3a] = { init_dp_condition }, |
2073 | [0x3b] = { init_io_mask_or }, |
2074 | [0x3c] = { init_io_or }, |
2075 | [0x49] = { init_idx_addr_latched }, |
2076 | [0x4a] = { init_io_restrict_pll2 }, |
2077 | [0x4b] = { init_pll2 }, |
2078 | [0x4c] = { init_i2c_byte }, |
2079 | [0x4d] = { init_zm_i2c_byte }, |
2080 | [0x4e] = { init_zm_i2c }, |
2081 | [0x4f] = { init_tmds }, |
2082 | [0x50] = { init_zm_tmds_group }, |
2083 | [0x51] = { init_cr_idx_adr_latch }, |
2084 | [0x52] = { init_cr }, |
2085 | [0x53] = { init_zm_cr }, |
2086 | [0x54] = { init_zm_cr_group }, |
2087 | [0x56] = { init_condition_time }, |
2088 | [0x57] = { init_ltime }, |
2089 | [0x58] = { init_zm_reg_sequence }, |
2090 | [0x5b] = { init_sub_direct }, |
2091 | [0x5c] = { init_jump }, |
2092 | [0x5e] = { init_i2c_if }, |
2093 | [0x5f] = { init_copy_nv_reg }, |
2094 | [0x62] = { init_zm_index_io }, |
2095 | [0x63] = { init_compute_mem }, |
2096 | [0x65] = { init_reset }, |
2097 | [0x66] = { init_configure_mem }, |
2098 | [0x67] = { init_configure_clk }, |
2099 | [0x68] = { init_configure_preinit }, |
2100 | [0x69] = { init_io }, |
2101 | [0x6b] = { init_sub }, |
2102 | [0x6d] = { init_ram_condition }, |
2103 | [0x6e] = { init_nv_reg }, |
2104 | [0x6f] = { init_macro }, |
2105 | [0x71] = { init_done }, |
2106 | [0x72] = { init_resume }, |
2107 | [0x74] = { init_time }, |
2108 | [0x75] = { init_condition }, |
2109 | [0x76] = { init_io_condition }, |
2110 | [0x78] = { init_index_io }, |
2111 | [0x79] = { init_pll }, |
2112 | [0x7a] = { init_zm_reg }, |
2113 | [0x87] = { init_ram_restrict_pll }, |
2114 | [0x8c] = { init_reserved }, |
2115 | [0x8d] = { init_reserved }, |
2116 | [0x8e] = { init_gpio }, |
2117 | [0x8f] = { init_ram_restrict_zm_reg_group }, |
2118 | [0x90] = { init_copy_zm_reg }, |
2119 | [0x91] = { init_zm_reg_group }, |
2120 | [0x92] = { init_reserved }, |
2121 | [0x96] = { init_xlat }, |
2122 | [0x97] = { init_zm_mask_add }, |
2123 | [0x98] = { init_auxch }, |
2124 | [0x99] = { init_zm_auxch }, |
2125 | [0x9a] = { init_i2c_long_if }, |
2126 | [0xa9] = { init_gpio_ne }, |
2127 | [0xaa] = { init_reserved }, |
2128 | }; |
2129 | |
2130 | #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0])) |
2131 | |
2132 | int |
2133 | nvbios_exec(struct nvbios_init *init) |
2134 | { |
2135 | init->nested++; |
2136 | while (init->offset) { |
2137 | u8 opcode = nv_ro08(init->bios, init->offset); |
2138 | if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) { |
2139 | error("unknown opcode 0x%02x\n" , opcode); |
2140 | return -EINVAL; |
2141 | } |
2142 | |
2143 | init_opcode[opcode].exec(init); |
2144 | } |
2145 | init->nested--; |
2146 | return 0; |
2147 | } |
2148 | |
2149 | int |
2150 | nvbios_init(struct nouveau_subdev *subdev, bool execute) |
2151 | { |
2152 | struct nouveau_bios *bios = nouveau_bios(subdev); |
2153 | int ret = 0; |
2154 | int i = -1; |
2155 | u16 data; |
2156 | |
2157 | if (execute) |
2158 | nv_info(bios, "running init tables\n" ); |
2159 | while (!ret && (data = (init_script(bios, ++i)))) { |
2160 | struct nvbios_init init = { |
2161 | .subdev = subdev, |
2162 | .bios = bios, |
2163 | .offset = data, |
2164 | .outp = NULL, |
2165 | .crtc = -1, |
2166 | .execute = execute ? 1 : 0, |
2167 | }; |
2168 | |
2169 | ret = nvbios_exec(&init); |
2170 | } |
2171 | |
2172 | /* the vbios parser will run this right after the normal init |
2173 | * tables, whereas the binary driver appears to run it later. |
2174 | */ |
2175 | if (!ret && (data = init_unknown_script(bios))) { |
2176 | struct nvbios_init init = { |
2177 | .subdev = subdev, |
2178 | .bios = bios, |
2179 | .offset = data, |
2180 | .outp = NULL, |
2181 | .crtc = -1, |
2182 | .execute = execute ? 1 : 0, |
2183 | }; |
2184 | |
2185 | ret = nvbios_exec(&init); |
2186 | } |
2187 | |
2188 | return ret; |
2189 | } |
2190 | |