1/* $NetBSD: piixpm.c,v 1.51 2016/10/13 17:11:09 jdolecek Exp $ */
2/* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */
3
4/*
5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20/*
21 * Intel PIIX and compatible Power Management controller driver.
22 */
23
24#include <sys/cdefs.h>
25__KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.51 2016/10/13 17:11:09 jdolecek Exp $");
26
27#include <sys/param.h>
28#include <sys/systm.h>
29#include <sys/device.h>
30#include <sys/kernel.h>
31#include <sys/mutex.h>
32#include <sys/proc.h>
33
34#include <sys/bus.h>
35
36#include <dev/pci/pcidevs.h>
37#include <dev/pci/pcireg.h>
38#include <dev/pci/pcivar.h>
39
40#include <dev/pci/piixpmreg.h>
41
42#include <dev/i2c/i2cvar.h>
43
44#include <dev/ic/acpipmtimer.h>
45
46#ifdef PIIXPM_DEBUG
47#define DPRINTF(x) printf x
48#else
49#define DPRINTF(x)
50#endif
51
52#define PIIXPM_IS_CSB5(id) \
53 (PCI_VENDOR((id)) == PCI_VENDOR_SERVERWORKS && \
54 PCI_PRODUCT((id)) == PCI_PRODUCT_SERVERWORKS_CSB5)
55#define PIIXPM_DELAY 200
56#define PIIXPM_TIMEOUT 1
57
58struct piixpm_smbus {
59 int sda;
60 struct piixpm_softc *softc;
61};
62
63struct piixpm_softc {
64 device_t sc_dev;
65
66 bus_space_tag_t sc_iot;
67#define sc_pm_iot sc_iot
68#define sc_smb_iot sc_iot
69 bus_space_handle_t sc_pm_ioh;
70 bus_space_handle_t sc_sb800_ioh;
71 bus_space_handle_t sc_smb_ioh;
72 void * sc_smb_ih;
73 int sc_poll;
74
75 pci_chipset_tag_t sc_pc;
76 pcitag_t sc_pcitag;
77 pcireg_t sc_id;
78
79 int sc_numbusses;
80 device_t sc_i2c_device[4];
81 struct piixpm_smbus sc_busses[4];
82 struct i2c_controller sc_i2c_tags[4];
83
84 kmutex_t sc_i2c_mutex;
85 struct {
86 i2c_op_t op;
87 void * buf;
88 size_t len;
89 int flags;
90 volatile int error;
91 } sc_i2c_xfer;
92
93 pcireg_t sc_devact[2];
94};
95
96static int piixpm_match(device_t, cfdata_t, void *);
97static void piixpm_attach(device_t, device_t, void *);
98static int piixpm_rescan(device_t, const char *, const int *);
99static void piixpm_chdet(device_t, device_t);
100
101static bool piixpm_suspend(device_t, const pmf_qual_t *);
102static bool piixpm_resume(device_t, const pmf_qual_t *);
103
104static int piixpm_sb800_init(struct piixpm_softc *);
105static void piixpm_csb5_reset(void *);
106static int piixpm_i2c_acquire_bus(void *, int);
107static void piixpm_i2c_release_bus(void *, int);
108static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *,
109 size_t, void *, size_t, int);
110
111static int piixpm_intr(void *);
112
113CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc),
114 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0);
115
116static int
117piixpm_match(device_t parent, cfdata_t match, void *aux)
118{
119 struct pci_attach_args *pa;
120
121 pa = (struct pci_attach_args *)aux;
122 switch (PCI_VENDOR(pa->pa_id)) {
123 case PCI_VENDOR_INTEL:
124 switch (PCI_PRODUCT(pa->pa_id)) {
125 case PCI_PRODUCT_INTEL_82371AB_PMC:
126 case PCI_PRODUCT_INTEL_82440MX_PMC:
127 return 1;
128 }
129 break;
130 case PCI_VENDOR_ATI:
131 switch (PCI_PRODUCT(pa->pa_id)) {
132 case PCI_PRODUCT_ATI_SB200_SMB:
133 case PCI_PRODUCT_ATI_SB300_SMB:
134 case PCI_PRODUCT_ATI_SB400_SMB:
135 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */
136 return 1;
137 }
138 break;
139 case PCI_VENDOR_SERVERWORKS:
140 switch (PCI_PRODUCT(pa->pa_id)) {
141 case PCI_PRODUCT_SERVERWORKS_OSB4:
142 case PCI_PRODUCT_SERVERWORKS_CSB5:
143 case PCI_PRODUCT_SERVERWORKS_CSB6:
144 case PCI_PRODUCT_SERVERWORKS_HT1000SB:
145 return 1;
146 }
147 break;
148 case PCI_VENDOR_AMD:
149 switch (PCI_PRODUCT(pa->pa_id)) {
150 case PCI_PRODUCT_AMD_HUDSON_SMB:
151 return 1;
152 }
153 break;
154 }
155
156 return 0;
157}
158
159static void
160piixpm_attach(device_t parent, device_t self, void *aux)
161{
162 struct piixpm_softc *sc = device_private(self);
163 struct pci_attach_args *pa = aux;
164 pcireg_t base, conf;
165 pcireg_t pmmisc;
166 pci_intr_handle_t ih;
167 const char *intrstr = NULL;
168 int i, flags;
169 char intrbuf[PCI_INTRSTR_LEN];
170
171 sc->sc_dev = self;
172 sc->sc_iot = pa->pa_iot;
173 sc->sc_id = pa->pa_id;
174 sc->sc_pc = pa->pa_pc;
175 sc->sc_pcitag = pa->pa_tag;
176 sc->sc_numbusses = 1;
177
178 pci_aprint_devinfo(pa, NULL);
179
180 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume))
181 aprint_error_dev(self, "couldn't establish power handler\n");
182
183 /* Read configuration */
184 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC);
185 DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf));
186
187 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) ||
188 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC))
189 goto nopowermanagement;
190
191 /* check whether I/O access to PM regs is enabled */
192 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC);
193 if (!(pmmisc & 1))
194 goto nopowermanagement;
195
196 /* Map I/O space */
197 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE);
198 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base),
199 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) {
200 aprint_error_dev(self,
201 "can't map power management I/O space\n");
202 goto nopowermanagement;
203 }
204
205 /*
206 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M.
207 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20
208 * in the "Specification update" (document #297738).
209 */
210 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh,
211 PIIX_PM_PMTMR,
212 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 );
213
214nopowermanagement:
215
216 /* SB800 rev 0x40+ and AMD HUDSON need special initialization */
217 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD &&
218 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_HUDSON_SMB) {
219 if (piixpm_sb800_init(sc) == 0) {
220 goto attach_i2c;
221 }
222 aprint_normal_dev(self, "SMBus initialization failed\n");
223 return;
224 }
225 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
226 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB &&
227 PCI_REVISION(pa->pa_class) >= 0x40) {
228 if (piixpm_sb800_init(sc) == 0) {
229 sc->sc_numbusses = 4;
230 goto attach_i2c;
231 }
232 aprint_normal_dev(self, "SMBus initialization failed\n");
233 return;
234 }
235
236 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) {
237 aprint_normal_dev(self, "SMBus disabled\n");
238 return;
239 }
240
241 /* Map I/O space */
242 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff;
243 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base),
244 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
245 aprint_error_dev(self, "can't map smbus I/O space\n");
246 return;
247 }
248
249 sc->sc_poll = 1;
250 aprint_normal_dev(self, "");
251 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) {
252 /* No PCI IRQ */
253 aprint_normal("interrupting at SMI, ");
254 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) {
255 /* Install interrupt handler */
256 if (pci_intr_map(pa, &ih) == 0) {
257 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf,
258 sizeof(intrbuf));
259 sc->sc_smb_ih = pci_intr_establish_xname(pa->pa_pc, ih,
260 IPL_BIO, piixpm_intr, sc, device_xname(sc->sc_dev));
261 if (sc->sc_smb_ih != NULL) {
262 aprint_normal("interrupting at %s", intrstr);
263 sc->sc_poll = 0;
264 }
265 }
266 }
267 if (sc->sc_poll)
268 aprint_normal("polling");
269
270 aprint_normal("\n");
271
272attach_i2c:
273 for (i = 0; i < sc->sc_numbusses; i++)
274 sc->sc_i2c_device[i] = NULL;
275
276 flags = 0;
277 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE);
278 piixpm_rescan(self, "i2cbus", &flags);
279}
280
281static int
282piixpm_rescan(device_t self, const char *ifattr, const int *flags)
283{
284 struct piixpm_softc *sc = device_private(self);
285 struct i2cbus_attach_args iba;
286 int i;
287
288 if (!ifattr_match(ifattr, "i2cbus"))
289 return 0;
290
291 /* Attach I2C bus */
292
293 for (i = 0; i < sc->sc_numbusses; i++) {
294 if (sc->sc_i2c_device[i])
295 continue;
296 sc->sc_busses[i].sda = i;
297 sc->sc_busses[i].softc = sc;
298 sc->sc_i2c_tags[i].ic_cookie = &sc->sc_busses[i];
299 sc->sc_i2c_tags[i].ic_acquire_bus = piixpm_i2c_acquire_bus;
300 sc->sc_i2c_tags[i].ic_release_bus = piixpm_i2c_release_bus;
301 sc->sc_i2c_tags[i].ic_exec = piixpm_i2c_exec;
302 memset(&iba, 0, sizeof(iba));
303 iba.iba_type = I2C_TYPE_SMBUS;
304 iba.iba_tag = &sc->sc_i2c_tags[i];
305 sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba,
306 iicbus_print);
307 }
308
309 return 0;
310}
311
312static void
313piixpm_chdet(device_t self, device_t child)
314{
315 struct piixpm_softc *sc = device_private(self);
316 int i;
317
318 for (i = 0; i < sc->sc_numbusses; i++) {
319 if (sc->sc_i2c_device[i] == child) {
320 sc->sc_i2c_device[i] = NULL;
321 break;
322 }
323 }
324}
325
326
327static bool
328piixpm_suspend(device_t dv, const pmf_qual_t *qual)
329{
330 struct piixpm_softc *sc = device_private(dv);
331
332 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
333 PIIX_DEVACTA);
334 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
335 PIIX_DEVACTB);
336
337 return true;
338}
339
340static bool
341piixpm_resume(device_t dv, const pmf_qual_t *qual)
342{
343 struct piixpm_softc *sc = device_private(dv);
344
345 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA,
346 sc->sc_devact[0]);
347 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB,
348 sc->sc_devact[1]);
349
350 return true;
351}
352
353/*
354 * Extract SMBus base address from SB800 Power Management (PM) registers.
355 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or
356 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only
357 * called once it uses indirect I/O for simplicity.
358 */
359static int
360piixpm_sb800_init(struct piixpm_softc *sc)
361{
362 bus_space_tag_t iot = sc->sc_iot;
363 bus_space_handle_t ioh; /* indirect I/O handle */
364 uint16_t val, base_addr;
365
366 /* Fetch SMB base address */
367 if (bus_space_map(iot,
368 PIIXPM_INDIRECTIO_BASE, PIIXPM_INDIRECTIO_SIZE, 0, &ioh)) {
369 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n");
370 return EBUSY;
371 }
372 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX,
373 SB800_PM_SMBUS0EN_LO);
374 val = bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA);
375 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX,
376 SB800_PM_SMBUS0EN_HI);
377 val |= bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA) << 8;
378 sc->sc_sb800_ioh = ioh;
379
380 if ((val & SB800_PM_SMBUS0EN_ENABLE) == 0)
381 return ENOENT;
382
383 base_addr = val & SB800_PM_SMBUS0EN_BADDR;
384
385 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr);
386
387 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX,
388 SB800_PM_SMBUS0SELEN);
389 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_DATA, 1); /* SMBUS0SEL */
390
391 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr),
392 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
393 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n");
394 return EBUSY;
395 }
396 aprint_normal_dev(sc->sc_dev, "polling (SB800)\n");
397 sc->sc_poll = 1;
398
399 return 0;
400}
401
402static void
403piixpm_csb5_reset(void *arg)
404{
405 struct piixpm_softc *sc = arg;
406 pcireg_t base, hostc, pmbase;
407
408 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE);
409 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC);
410
411 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE);
412 pmbase |= PIIX_PM_BASE_CSB5_RESET;
413 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase);
414 pmbase &= ~PIIX_PM_BASE_CSB5_RESET;
415 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase);
416
417 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base);
418 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc);
419
420 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2);
421}
422
423static int
424piixpm_i2c_acquire_bus(void *cookie, int flags)
425{
426 struct piixpm_smbus *smbus = cookie;
427 struct piixpm_softc *sc = smbus->softc;
428
429 if (!cold)
430 mutex_enter(&sc->sc_i2c_mutex);
431
432 if (smbus->sda > 0) /* SB800 */
433 {
434 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
435 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL);
436 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
437 PIIXPM_INDIRECTIO_DATA, smbus->sda << 1);
438 }
439
440 return 0;
441}
442
443static void
444piixpm_i2c_release_bus(void *cookie, int flags)
445{
446 struct piixpm_smbus *smbus = cookie;
447 struct piixpm_softc *sc = smbus->softc;
448
449 if (smbus->sda > 0) /* SB800 */
450 {
451 /*
452 * HP Microserver hangs after reboot if not set to SDA0.
453 * Also add shutdown hook?
454 */
455 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
456 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL);
457 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
458 PIIXPM_INDIRECTIO_DATA, 0);
459 }
460
461 if (!cold)
462 mutex_exit(&sc->sc_i2c_mutex);
463}
464
465static int
466piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr,
467 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
468{
469 struct piixpm_smbus *smbus = cookie;
470 struct piixpm_softc *sc = smbus->softc;
471 const u_int8_t *b;
472 u_int8_t ctl = 0, st;
473 int retries;
474
475 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %zu, len %zu, flags 0x%x\n",
476 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags));
477
478 /* Clear status bits */
479 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS,
480 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR |
481 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED);
482 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1,
483 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
484
485 /* Wait for bus to be idle */
486 for (retries = 100; retries > 0; retries--) {
487 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh,
488 PIIX_SMB_HS);
489 if (!(st & PIIX_SMB_HS_BUSY))
490 break;
491 DELAY(PIIXPM_DELAY);
492 }
493 DPRINTF(("%s: exec: st 0x%d\n", device_xname(sc->sc_dev), st & 0xff));
494 if (st & PIIX_SMB_HS_BUSY)
495 return (1);
496
497 if (cold || sc->sc_poll)
498 flags |= I2C_F_POLL;
499
500 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 ||
501 (cmdlen == 0 && len > 1))
502 return (1);
503
504 /* Setup transfer */
505 sc->sc_i2c_xfer.op = op;
506 sc->sc_i2c_xfer.buf = buf;
507 sc->sc_i2c_xfer.len = len;
508 sc->sc_i2c_xfer.flags = flags;
509 sc->sc_i2c_xfer.error = 0;
510
511 /* Set slave address and transfer direction */
512 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA,
513 PIIX_SMB_TXSLVA_ADDR(addr) |
514 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0));
515
516 b = cmdbuf;
517 if (cmdlen > 0)
518 /* Set command byte */
519 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh,
520 PIIX_SMB_HCMD, b[0]);
521
522 if (I2C_OP_WRITE_P(op)) {
523 /* Write data */
524 b = buf;
525 if (cmdlen == 0 && len == 1)
526 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh,
527 PIIX_SMB_HCMD, b[0]);
528 else if (len > 0)
529 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh,
530 PIIX_SMB_HD0, b[0]);
531 if (len > 1)
532 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh,
533 PIIX_SMB_HD1, b[1]);
534 }
535
536 /* Set SMBus command */
537 if (cmdlen == 0) {
538 if (len == 0)
539 ctl = PIIX_SMB_HC_CMD_QUICK;
540 else
541 ctl = PIIX_SMB_HC_CMD_BYTE;
542 } else if (len == 1)
543 ctl = PIIX_SMB_HC_CMD_BDATA;
544 else if (len == 2)
545 ctl = PIIX_SMB_HC_CMD_WDATA;
546
547 if ((flags & I2C_F_POLL) == 0)
548 ctl |= PIIX_SMB_HC_INTREN;
549
550 /* Start transaction */
551 ctl |= PIIX_SMB_HC_START;
552 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl);
553
554 if (flags & I2C_F_POLL) {
555 /* Poll for completion */
556 if (PIIXPM_IS_CSB5(sc->sc_id))
557 DELAY(2*PIIXPM_DELAY);
558 else
559 DELAY(PIIXPM_DELAY);
560 for (retries = 1000; retries > 0; retries--) {
561 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh,
562 PIIX_SMB_HS);
563 if ((st & PIIX_SMB_HS_BUSY) == 0)
564 break;
565 DELAY(PIIXPM_DELAY);
566 }
567 if (st & PIIX_SMB_HS_BUSY)
568 goto timeout;
569 piixpm_intr(sc);
570 } else {
571 /* Wait for interrupt */
572 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz))
573 goto timeout;
574 }
575
576 if (sc->sc_i2c_xfer.error)
577 return (1);
578
579 return (0);
580
581timeout:
582 /*
583 * Transfer timeout. Kill the transaction and clear status bits.
584 */
585 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st);
586 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC,
587 PIIX_SMB_HC_KILL);
588 DELAY(PIIXPM_DELAY);
589 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS);
590 if ((st & PIIX_SMB_HS_FAILED) == 0)
591 aprint_error_dev(sc->sc_dev,
592 "transaction abort failed, status 0x%x\n", st);
593 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st);
594 /*
595 * CSB5 needs hard reset to unlock the smbus after timeout.
596 */
597 if (PIIXPM_IS_CSB5(sc->sc_id))
598 piixpm_csb5_reset(sc);
599 return (1);
600}
601
602static int
603piixpm_intr(void *arg)
604{
605 struct piixpm_softc *sc = arg;
606 u_int8_t st;
607 u_int8_t *b;
608 size_t len;
609
610 /* Read status */
611 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS);
612 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR |
613 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR |
614 PIIX_SMB_HS_FAILED)) == 0)
615 /* Interrupt was not for us */
616 return (0);
617
618 DPRINTF(("%s: intr st 0x%d\n", device_xname(sc->sc_dev), st & 0xff));
619
620 /* Clear status bits */
621 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st);
622
623 /* Check for errors */
624 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR |
625 PIIX_SMB_HS_FAILED)) {
626 sc->sc_i2c_xfer.error = 1;
627 goto done;
628 }
629
630 if (st & PIIX_SMB_HS_INTR) {
631 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op))
632 goto done;
633
634 /* Read data */
635 b = sc->sc_i2c_xfer.buf;
636 len = sc->sc_i2c_xfer.len;
637 if (len > 0)
638 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh,
639 PIIX_SMB_HD0);
640 if (len > 1)
641 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh,
642 PIIX_SMB_HD1);
643 }
644
645done:
646 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0)
647 wakeup(sc);
648 return (1);
649}
650