1 | /* $NetBSD: nouveau_engine_graph_nve4.c,v 1.2 2015/10/18 15:42:00 jmcneill Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2013 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs <bskeggs@redhat.com> |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_graph_nve4.c,v 1.2 2015/10/18 15:42:00 jmcneill Exp $" ); |
29 | |
30 | #include "nvc0.h" |
31 | #include "ctxnvc0.h" |
32 | |
33 | /******************************************************************************* |
34 | * Graphics object classes |
35 | ******************************************************************************/ |
36 | |
37 | static struct nouveau_oclass |
38 | nve4_graph_sclass[] = { |
39 | { 0x902d, &nouveau_object_ofuncs }, |
40 | { 0xa040, &nouveau_object_ofuncs }, |
41 | { 0xa097, &nouveau_object_ofuncs }, |
42 | { 0xa0c0, &nouveau_object_ofuncs }, |
43 | {} |
44 | }; |
45 | |
46 | /******************************************************************************* |
47 | * PGRAPH register lists |
48 | ******************************************************************************/ |
49 | |
50 | const struct nvc0_graph_init |
51 | nve4_graph_init_main_0[] = { |
52 | { 0x400080, 1, 0x04, 0x003083c2 }, |
53 | { 0x400088, 1, 0x04, 0x0001ffe7 }, |
54 | { 0x40008c, 1, 0x04, 0x00000000 }, |
55 | { 0x400090, 1, 0x04, 0x00000030 }, |
56 | { 0x40013c, 1, 0x04, 0x003901f7 }, |
57 | { 0x400140, 1, 0x04, 0x00000100 }, |
58 | { 0x400144, 1, 0x04, 0x00000000 }, |
59 | { 0x400148, 1, 0x04, 0x00000110 }, |
60 | { 0x400138, 1, 0x04, 0x00000000 }, |
61 | { 0x400130, 2, 0x04, 0x00000000 }, |
62 | { 0x400124, 1, 0x04, 0x00000002 }, |
63 | {} |
64 | }; |
65 | |
66 | static const struct nvc0_graph_init |
67 | nve4_graph_init_ds_0[] = { |
68 | { 0x405844, 1, 0x04, 0x00ffffff }, |
69 | { 0x405850, 1, 0x04, 0x00000000 }, |
70 | { 0x405900, 1, 0x04, 0x0000ff34 }, |
71 | { 0x405908, 1, 0x04, 0x00000000 }, |
72 | { 0x405928, 2, 0x04, 0x00000000 }, |
73 | {} |
74 | }; |
75 | |
76 | static const struct nvc0_graph_init |
77 | nve4_graph_init_sked_0[] = { |
78 | { 0x407010, 1, 0x04, 0x00000000 }, |
79 | {} |
80 | }; |
81 | |
82 | static const struct nvc0_graph_init |
83 | nve4_graph_init_cwd_0[] = { |
84 | { 0x405b50, 1, 0x04, 0x00000000 }, |
85 | {} |
86 | }; |
87 | |
88 | static const struct nvc0_graph_init |
89 | nve4_graph_init_gpc_unk_1[] = { |
90 | { 0x418d00, 1, 0x04, 0x00000000 }, |
91 | { 0x418d28, 2, 0x04, 0x00000000 }, |
92 | { 0x418f00, 1, 0x04, 0x00000000 }, |
93 | { 0x418f08, 1, 0x04, 0x00000000 }, |
94 | { 0x418f20, 2, 0x04, 0x00000000 }, |
95 | { 0x418e00, 1, 0x04, 0x00000060 }, |
96 | { 0x418e08, 1, 0x04, 0x00000000 }, |
97 | { 0x418e1c, 2, 0x04, 0x00000000 }, |
98 | {} |
99 | }; |
100 | |
101 | const struct nvc0_graph_init |
102 | nve4_graph_init_tpccs_0[] = { |
103 | { 0x419d0c, 1, 0x04, 0x00000000 }, |
104 | { 0x419d10, 1, 0x04, 0x00000014 }, |
105 | {} |
106 | }; |
107 | |
108 | const struct nvc0_graph_init |
109 | nve4_graph_init_pe_0[] = { |
110 | { 0x41980c, 1, 0x04, 0x00000010 }, |
111 | { 0x419844, 1, 0x04, 0x00000000 }, |
112 | { 0x419850, 1, 0x04, 0x00000004 }, |
113 | { 0x419854, 2, 0x04, 0x00000000 }, |
114 | {} |
115 | }; |
116 | |
117 | static const struct nvc0_graph_init |
118 | nve4_graph_init_l1c_0[] = { |
119 | { 0x419c98, 1, 0x04, 0x00000000 }, |
120 | { 0x419ca8, 1, 0x04, 0x00000000 }, |
121 | { 0x419cb0, 1, 0x04, 0x01000000 }, |
122 | { 0x419cb4, 1, 0x04, 0x00000000 }, |
123 | { 0x419cb8, 1, 0x04, 0x00b08bea }, |
124 | { 0x419c84, 1, 0x04, 0x00010384 }, |
125 | { 0x419cbc, 1, 0x04, 0x28137646 }, |
126 | { 0x419cc0, 2, 0x04, 0x00000000 }, |
127 | { 0x419c80, 1, 0x04, 0x00020232 }, |
128 | {} |
129 | }; |
130 | |
131 | static const struct nvc0_graph_init |
132 | nve4_graph_init_sm_0[] = { |
133 | { 0x419e00, 1, 0x04, 0x00000000 }, |
134 | { 0x419ea0, 1, 0x04, 0x00000000 }, |
135 | { 0x419ee4, 1, 0x04, 0x00000000 }, |
136 | { 0x419ea4, 1, 0x04, 0x00000100 }, |
137 | { 0x419ea8, 1, 0x04, 0x00000000 }, |
138 | { 0x419eb4, 4, 0x04, 0x00000000 }, |
139 | { 0x419edc, 1, 0x04, 0x00000000 }, |
140 | { 0x419f00, 1, 0x04, 0x00000000 }, |
141 | { 0x419f74, 1, 0x04, 0x00000555 }, |
142 | {} |
143 | }; |
144 | |
145 | const struct nvc0_graph_init |
146 | nve4_graph_init_be_0[] = { |
147 | { 0x40880c, 1, 0x04, 0x00000000 }, |
148 | { 0x408850, 1, 0x04, 0x00000004 }, |
149 | { 0x408910, 9, 0x04, 0x00000000 }, |
150 | { 0x408950, 1, 0x04, 0x00000000 }, |
151 | { 0x408954, 1, 0x04, 0x0000ffff }, |
152 | { 0x408958, 1, 0x04, 0x00000034 }, |
153 | { 0x408984, 1, 0x04, 0x00000000 }, |
154 | { 0x408988, 1, 0x04, 0x08040201 }, |
155 | { 0x40898c, 1, 0x04, 0x80402010 }, |
156 | {} |
157 | }; |
158 | |
159 | const struct nvc0_graph_pack |
160 | nve4_graph_pack_mmio[] = { |
161 | { nve4_graph_init_main_0 }, |
162 | { nvc0_graph_init_fe_0 }, |
163 | { nvc0_graph_init_pri_0 }, |
164 | { nvc0_graph_init_rstr2d_0 }, |
165 | { nvd9_graph_init_pd_0 }, |
166 | { nve4_graph_init_ds_0 }, |
167 | { nvc0_graph_init_scc_0 }, |
168 | { nve4_graph_init_sked_0 }, |
169 | { nve4_graph_init_cwd_0 }, |
170 | { nvd9_graph_init_prop_0 }, |
171 | { nvc1_graph_init_gpc_unk_0 }, |
172 | { nvc0_graph_init_setup_0 }, |
173 | { nvc0_graph_init_crstr_0 }, |
174 | { nvc1_graph_init_setup_1 }, |
175 | { nvc0_graph_init_zcull_0 }, |
176 | { nvd9_graph_init_gpm_0 }, |
177 | { nve4_graph_init_gpc_unk_1 }, |
178 | { nvc0_graph_init_gcc_0 }, |
179 | { nve4_graph_init_tpccs_0 }, |
180 | { nvd9_graph_init_tex_0 }, |
181 | { nve4_graph_init_pe_0 }, |
182 | { nve4_graph_init_l1c_0 }, |
183 | { nvc0_graph_init_mpc_0 }, |
184 | { nve4_graph_init_sm_0 }, |
185 | { nvd7_graph_init_pes_0 }, |
186 | { nvd7_graph_init_wwdx_0 }, |
187 | { nvd7_graph_init_cbm_0 }, |
188 | { nve4_graph_init_be_0 }, |
189 | { nvc0_graph_init_fe_1 }, |
190 | {} |
191 | }; |
192 | |
193 | /******************************************************************************* |
194 | * PGRAPH engine/subdev functions |
195 | ******************************************************************************/ |
196 | |
197 | int |
198 | nve4_graph_fini(struct nouveau_object *object, bool suspend) |
199 | { |
200 | struct nvc0_graph_priv *priv = (void *)object; |
201 | |
202 | /*XXX: this is a nasty hack to power on gr on certain boards |
203 | * where it's disabled by therm, somehow. ideally it'd |
204 | * be nice to know when we should be doing this, and why, |
205 | * but, it's yet to be determined. for now we test for |
206 | * the particular mmio error that occurs in the situation, |
207 | * and then bash therm in the way nvidia do. |
208 | */ |
209 | nv_mask(priv, 0x000200, 0x08001000, 0x08001000); |
210 | nv_rd32(priv, 0x000200); |
211 | if (nv_rd32(priv, 0x400700) == 0xbadf1000) { |
212 | nv_mask(priv, 0x000200, 0x08001000, 0x00000000); |
213 | nv_rd32(priv, 0x000200); |
214 | nv_mask(priv, 0x020004, 0xc0000000, 0x40000000); |
215 | } |
216 | |
217 | return nouveau_graph_fini(&priv->base, suspend); |
218 | } |
219 | |
220 | int |
221 | nve4_graph_init(struct nouveau_object *object) |
222 | { |
223 | struct nvc0_graph_oclass *oclass = (void *)object->oclass; |
224 | struct nvc0_graph_priv *priv = (void *)object; |
225 | const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); |
226 | u32 data[TPC_MAX / 8] = {}; |
227 | u8 tpcnr[GPC_MAX]; |
228 | int gpc, tpc, rop; |
229 | int ret, i; |
230 | |
231 | ret = nouveau_graph_init(&priv->base); |
232 | if (ret) |
233 | return ret; |
234 | |
235 | nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); |
236 | nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); |
237 | nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); |
238 | nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); |
239 | nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); |
240 | nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); |
241 | nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); |
242 | nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); |
243 | |
244 | nvc0_graph_mmio(priv, oclass->mmio); |
245 | |
246 | nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); |
247 | |
248 | memset(data, 0x00, sizeof(data)); |
249 | memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); |
250 | for (i = 0, gpc = -1; i < priv->tpc_total; i++) { |
251 | do { |
252 | gpc = (gpc + 1) % priv->gpc_nr; |
253 | } while (!tpcnr[gpc]); |
254 | tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; |
255 | |
256 | data[i / 8] |= tpc << ((i % 8) * 4); |
257 | } |
258 | |
259 | nv_wr32(priv, GPC_BCAST(0x0980), data[0]); |
260 | nv_wr32(priv, GPC_BCAST(0x0984), data[1]); |
261 | nv_wr32(priv, GPC_BCAST(0x0988), data[2]); |
262 | nv_wr32(priv, GPC_BCAST(0x098c), data[3]); |
263 | |
264 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { |
265 | nv_wr32(priv, GPC_UNIT(gpc, 0x0914), |
266 | priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); |
267 | nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | |
268 | priv->tpc_total); |
269 | nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); |
270 | } |
271 | |
272 | nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); |
273 | nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); |
274 | |
275 | nv_wr32(priv, 0x400500, 0x00010001); |
276 | |
277 | nv_wr32(priv, 0x400100, 0xffffffff); |
278 | nv_wr32(priv, 0x40013c, 0xffffffff); |
279 | |
280 | nv_wr32(priv, 0x409ffc, 0x00000000); |
281 | nv_wr32(priv, 0x409c14, 0x00003e3e); |
282 | nv_wr32(priv, 0x409c24, 0x000f0001); |
283 | nv_wr32(priv, 0x404000, 0xc0000000); |
284 | nv_wr32(priv, 0x404600, 0xc0000000); |
285 | nv_wr32(priv, 0x408030, 0xc0000000); |
286 | nv_wr32(priv, 0x404490, 0xc0000000); |
287 | nv_wr32(priv, 0x406018, 0xc0000000); |
288 | nv_wr32(priv, 0x407020, 0x40000000); |
289 | nv_wr32(priv, 0x405840, 0xc0000000); |
290 | nv_wr32(priv, 0x405844, 0x00ffffff); |
291 | nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); |
292 | nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); |
293 | |
294 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { |
295 | nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000); |
296 | nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); |
297 | nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); |
298 | nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); |
299 | nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); |
300 | for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { |
301 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); |
302 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); |
303 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); |
304 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); |
305 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); |
306 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); |
307 | nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); |
308 | } |
309 | nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); |
310 | nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); |
311 | } |
312 | |
313 | for (rop = 0; rop < priv->rop_nr; rop++) { |
314 | nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); |
315 | nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); |
316 | nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); |
317 | nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); |
318 | } |
319 | |
320 | nv_wr32(priv, 0x400108, 0xffffffff); |
321 | nv_wr32(priv, 0x400138, 0xffffffff); |
322 | nv_wr32(priv, 0x400118, 0xffffffff); |
323 | nv_wr32(priv, 0x400130, 0xffffffff); |
324 | nv_wr32(priv, 0x40011c, 0xffffffff); |
325 | nv_wr32(priv, 0x400134, 0xffffffff); |
326 | |
327 | nv_wr32(priv, 0x400054, 0x34ce3464); |
328 | return nvc0_graph_init_ctxctl(priv); |
329 | } |
330 | |
331 | #include "fuc/hubnve0.fuc.h" |
332 | |
333 | static struct nvc0_graph_ucode |
334 | nve4_graph_fecs_ucode = { |
335 | .code.data = nve0_grhub_code, |
336 | .code.size = sizeof(nve0_grhub_code), |
337 | .data.data = nve0_grhub_data, |
338 | .data.size = sizeof(nve0_grhub_data), |
339 | }; |
340 | |
341 | #include "fuc/gpcnve0.fuc.h" |
342 | |
343 | static struct nvc0_graph_ucode |
344 | nve4_graph_gpccs_ucode = { |
345 | .code.data = nve0_grgpc_code, |
346 | .code.size = sizeof(nve0_grgpc_code), |
347 | .data.data = nve0_grgpc_data, |
348 | .data.size = sizeof(nve0_grgpc_data), |
349 | }; |
350 | |
351 | struct nouveau_oclass * |
352 | nve4_graph_oclass = &(struct nvc0_graph_oclass) { |
353 | .base.handle = NV_ENGINE(GR, 0xe4), |
354 | .base.ofuncs = &(struct nouveau_ofuncs) { |
355 | .ctor = nvc0_graph_ctor, |
356 | .dtor = nvc0_graph_dtor, |
357 | .init = nve4_graph_init, |
358 | .fini = nve4_graph_fini, |
359 | }, |
360 | .cclass = &nve4_grctx_oclass, |
361 | .sclass = nve4_graph_sclass, |
362 | .mmio = nve4_graph_pack_mmio, |
363 | .fecs.ucode = &nve4_graph_fecs_ucode, |
364 | .gpccs.ucode = &nve4_graph_gpccs_ucode, |
365 | }.base; |
366 | |