1 | /* $NetBSD: rrunnerreg.h,v 1.9 2008/04/28 20:23:51 martin Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code contributed to The NetBSD Foundation by Kevin M. Lahey |
8 | * of the Numerical Aerospace Simulation Facility, NASA Ames Research |
9 | * Center. |
10 | * |
11 | * Partially based on a HIPPI driver written by Essential Communications |
12 | * Corporation. Thanks to Jason Thorpe, Matt Jacob, and Fred Templin |
13 | * for invaluable advice and encouragement! |
14 | * |
15 | * Redistribution and use in source and binary forms, with or without |
16 | * modification, are permitted provided that the following conditions |
17 | * are met: |
18 | * 1. Redistributions of source code must retain the above copyright |
19 | * notice, this list of conditions and the following disclaimer. |
20 | * 2. Redistributions in binary form must reproduce the above copyright |
21 | * notice, this list of conditions and the following disclaimer in the |
22 | * documentation and/or other materials provided with the distribution. |
23 | * |
24 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
25 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
26 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
27 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
28 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
34 | * POSSIBILITY OF SUCH DAMAGE. |
35 | */ |
36 | |
37 | /* |
38 | * Description of RoadRunner registers and hardware constructs. |
39 | * |
40 | * We're trying to support version 1 AND version 2 of the RunCode. |
41 | * The fields that changed for version 2 are prefixed with RR2_ instead |
42 | * of RR_. If version 1 disappears (it is currently deprecated), |
43 | * we can remove compatibility, but it seems a shame to lose functionality |
44 | * for no good reason. |
45 | */ |
46 | |
47 | /* PCI registers */ |
48 | |
49 | #define RR_PCI_BIST 0x0c /* Built-In Self Test */ |
50 | |
51 | /* General control registers */ |
52 | |
53 | #define RR_MISC_HOST_CTL 0x40 /* Misc. Host Control */ |
54 | #define RR_MISC_LOCAL_CTL 0x44 /* Misc. Local Control */ |
55 | #define RR_PROC_PC 0x48 /* i960 program counter */ |
56 | #define RR_PROC_BREAKPT 0x4c /* set breakpoint on i960 */ |
57 | #define RR_TIMER 0x54 /* clock */ |
58 | #define RR_TIMER_REF 0x58 /* When this matches the TIMER, interrupt */ |
59 | #define RR_PCI_STATE 0x5c /* misc configuration */ |
60 | #define RR_MAIN_EVENT 0x60 /* main event register for i960 & RoadRunner */ |
61 | #define RR_WINDOW_BASE 0x68 /* pointer to internal memory*/ |
62 | #define RR_WINDOW_DATA 0x6c /* value of mem at WINDOW_BASE */ |
63 | #define RR_RX_STATE 0x70 /* HIPPI receiver state */ |
64 | #define RR_TX_STATE 0x74 /* HIPPI transmitter state */ |
65 | #define RR_EXT_SER_DATA 0x7c /* controls hardware besides RR on board */ |
66 | |
67 | /* Host DMA registers */ |
68 | |
69 | #define RR_WRITE_HOST 0x80 /* 64-bit pointer to data on host */ |
70 | #define RR_READ_HOST 0x90 |
71 | #define RR_WRITE_LENGTH 0x9c /* length of data to be moved */ |
72 | #define RR_READ_LENGTH 0xac |
73 | #define RR_DMA_WRITE_STATE 0xa0 /* controls DMA */ |
74 | #define RR_DMA_READ_STATE 0xb0 |
75 | #define RR_WRITE_DST 0xa4 /* Internal destination of DMA */ |
76 | #define RR_READ_DST 0xb4 |
77 | |
78 | /* RunCode registers */ |
79 | |
80 | #define RR_EVENT_CONSUMER 0x200 /* index of consumer in event ring */ |
81 | #define RR_SEND_PRODUCER 0x218 /* index of producer in sender ring */ |
82 | #define RR_SNAP_RECV_PRODUCER 0x21c /* index of producer in SNAP ring */ |
83 | #define RR_RECVS_PRODUCER 0x220 /* index of producer in recv rings */ |
84 | #define RR_COMMAND_RING 0x240 /* set of 16 command ring elements */ |
85 | |
86 | #define RR_ULA 0x280 /* Universal LAN Address */ |
87 | #define RR_RECV_RING_PTR 0x288 /* receive ring address */ |
88 | #define RR_GEN_INFO_PTR 0x290 /* general info block address */ |
89 | #define RR_MODE_AND_STATUS 0x298 /* operating mode and status */ |
90 | #define RR_CONN_RETRY_COUNT 0x29c /* when no campon, try count */ |
91 | #define RR_CONN_RETRY_TIMER 0x2a0 /* clock ticks to delay retry */ |
92 | #define RR_CONN_TIMEOUT 0x2a4 /* campon delay timeout */ |
93 | #define RR_STATS_TIMER 0x2a8 /* clock ticks between stats copy */ |
94 | #define RR_MAX_RECV_RINGS 0x2ac /* max receive rings (RO) */ |
95 | #define RR_INTERRUPT_TIMER 0x2b0 /* clock ticks between interrupts */ |
96 | #define RR_TX_TIMEOUT 0x2b4 /* transmit data not moving timer */ |
97 | #define RR_RX_TIMEOUT 0x2b8 /* receive data not moving timer */ |
98 | #define RR_EVENT_PRODUCER 0x2bc /* index of producer in event ring */ |
99 | #define RR_TRACE_INDEX 0x2c0 /* RunCode trace pointer */ |
100 | #define RR_RUNCODE_FAIL1 0x2c4 /* failure codes */ |
101 | #define RR_RUNCODE_FAIL2 0x2c8 |
102 | #define RR_FILTER_LA 0x2d0 /* internal debug, filtering */ |
103 | #define RR_RUNCODE_VERSION 0x2d4 /* RunCode version data */ |
104 | |
105 | #define RR_RUNCODE_RECV_CONS 0x300 /* Runcode receive ring consumption */ |
106 | #define RR_DRIVER_RECV_CONS 0x320 /* Driver receive ring consumption */ |
107 | |
108 | #define RR_MEMORY_WINDOW 0x800 /* Memory window */ |
109 | |
110 | |
111 | /* |
112 | * Event codes |
113 | */ |
114 | |
115 | /* General events */ |
116 | |
117 | #define RR_EC_RUNCODE_UP 0x01 |
118 | #define RR_EC_WATCHDOG 0x02 |
119 | #define RR_EC_TRACE 0x03 |
120 | #define RR_EC_STATS_RETRIEVED 0x04 |
121 | #define RR_EC_INVALID_CMD 0x05 |
122 | #define RR_EC_SET_CMD_CONSUMER 0x06 |
123 | #define RR_EC_LINK_ON 0x07 |
124 | #define RR_EC_LINK_OFF 0x08 |
125 | #define RR2_EC_INTERNAL_ERROR 0x09 |
126 | #define RR_EC_INTERNAL_ERROR 0x0a |
127 | #define RR2_EC_SOFTWARE_ERROR 0x0a |
128 | #define RR_EC_STATS_UPDATE 0x0b |
129 | #define RR_EC_REJECTING 0x0c |
130 | |
131 | /* Send events */ |
132 | |
133 | #define RR_EC_SET_SND_CONSUMER 0x10 |
134 | #define RR_EC_PACKET_SENT 0x11 |
135 | #define RR_EC_SEND_RING_LOW 0x12 |
136 | #define RR_EC_CONN_REJECT 0x13 |
137 | #define RR_EC_CAMPON_TIMEOUT 0x14 |
138 | #define RR_EC_CONN_TIMEOUT 0x15 |
139 | #define RR_EC_DISCONN_ERR 0x16 |
140 | #define RR_EC_INTERNAL_PARITY 0x17 |
141 | #define RR_EC_TX_IDLE 0x18 |
142 | #define RR_EC_SEND_LINK_OFF 0x19 |
143 | #define RR_EC_BAD_SEND_RING 0x1a |
144 | #define RR_EC_BAD_SEND_BUF 0x1b |
145 | #define RR_EC_BAD_SEND_DESC 0x1c |
146 | |
147 | /* Receive events */ |
148 | |
149 | #define RR_EC_RING_ENABLED 0x20 |
150 | #define RR_EC_RING_ENABLE_ERR 0x21 |
151 | #define RR_EC_RING_DISABLED 0x22 |
152 | #define RR_EC_RECV_RING_LOW 0x23 |
153 | #define RR_EC_RECV_RING_OUT 0x24 |
154 | #define RR_EC_PACKET_DISCARDED 0x25 |
155 | #define RR_EC_RECV_RING_FLUSH 0x26 |
156 | #define RR_EC_RECV_ERROR_INFO 0x27 |
157 | #define RR_EC_SET_RECV_CONSUMER 0x29 |
158 | #define RR_EC_PACKET_RECVED 0x2a |
159 | #define RR_EC_PARITY_ERR 0x2b |
160 | #define RR_EC_LLRC_ERR 0x2c |
161 | #define RR_EC_IP_HDR_CKSUM_ERR 0x2d |
162 | #define RR_EC_DATA_CKSUM_ERR 0x2e |
163 | #define RR_EC_SHORT_BURST_ERR 0x2f |
164 | #define RR_EC_RECV_LINK_OFF 0x30 |
165 | #define RR_EC_FLAG_SYNC_ERR 0x31 |
166 | #define RR_EC_FRAME_ERR 0x32 |
167 | #define RR_EC_RECV_IDLE 0x33 |
168 | #define RR_EC_PKT_LENGTH_ERR 0x34 |
169 | #define RR_EC_STATE_TRANS_ERR 0x35 |
170 | #define RR_EC_NO_READY_PULSE 0x3c |
171 | #define RR_EC_BAD_RECV_BUF 0x36 |
172 | #define RR_EC_BAD_RECV_DESC 0x37 |
173 | #define RR_EC_BAD_RECV_RING 0x38 |
174 | #define RR_EC_NO_RING_FOR_ULP 0x3a |
175 | #define RR_EC_OUT_OF_BUF 0x3b |
176 | #define RR_EC_UNIMPLEMENTED 0x40 |
177 | |
178 | |
179 | /* |
180 | * Command codes |
181 | */ |
182 | |
183 | #define RR_CC_START_RUNCODE 0x01 |
184 | #define RR_CC_UPDATE_STATS 0x02 |
185 | #define RR_CC_DISCONN_SRC 0x03 |
186 | #define RR_CC_DISCONN_DST 0x04 |
187 | #define RR_CC_WATCHDOG 0x05 |
188 | #define RR_CC_TRACE 0x06 |
189 | #define RR_CC_SET_SEND_PRODUCER 0x07 |
190 | #define RR_CC_SET_RECV_PRODUCER 0x08 |
191 | #define RR_CC_DISABLE_RING 0x09 |
192 | #define RR_CC_ENABLE_RING 0x0a |
193 | #define RR_CC_DISCARD_PKT 0x0b |
194 | #define RR_CC_FLUSH_RECV_RING 0x0c /* unimplemented */ |
195 | #define RR_CC_CONN_MGT 0x0d |
196 | |
197 | |
198 | /* |
199 | * Masks for registers |
200 | */ |
201 | |
202 | /* Misc Host Control */ |
203 | |
204 | #define RR_MH_INTERRUPT 0x001 /* interrupt state */ |
205 | #define RR_MH_CLEAR_INT 0x002 /* clear interrupt */ |
206 | #define RR_MH_NO_SWAP 0x004 /* disable normal endian swap to host */ |
207 | #define RR_MH_HALT_PROC 0x010 /* set to halt processor, clear to start */ |
208 | #define RR_MH_STEP 0x020 /* set to single step processor */ |
209 | #define RR_MH_PROC_HALT 0x100 /* indicates processor has been halted */ |
210 | #define RR_MH_BAD_INSTR 0x200 /* indicates invalid instruction executed */ |
211 | |
212 | #define RR_MH_REVISION_MASK 0xf0000000 /* mask to retrieve revision code */ |
213 | |
214 | /* Misc Local Control */ |
215 | |
216 | #define RR_LC_CLEAR_INT 0x0002 /* clear interrupt */ |
217 | #define RR_LC_FAST_PROM 0x0008 /* use fast EEPROM access */ |
218 | #define RR_LC_ADD_SRAM 0x0100 /* > 1MB SRAM present */ |
219 | #define RR_LC_ADD_HIPPI 0x0200 /* double number of HIPPI descriptors */ |
220 | #define RR_LC_PARITY_ON 0x0400 /* enable local parity checking */ |
221 | #define RR_LC_WRITE_PROM 0x1000 /* EEPROM write enable */ |
222 | |
223 | /* PCI State */ |
224 | |
225 | #define RR_PS_READ_MASK 0x1c |
226 | #define RR_PS_READ_SHIFT 2 |
227 | #define RR_PS_READ_DISABLE (0 << RR_PS_READ_SHIFT) |
228 | #define RR_PS_READ_4 (1 << RR_PS_READ_SHIFT) |
229 | #define RR_PS_READ_16 (2 << RR_PS_READ_SHIFT) |
230 | #define RR_PS_READ_32 (3 << RR_PS_READ_SHIFT) |
231 | #define RR_PS_READ_64 (4 << RR_PS_READ_SHIFT) |
232 | #define RR_PS_READ_128 (5 << RR_PS_READ_SHIFT) |
233 | #define RR_PS_READ_256 (6 << RR_PS_READ_SHIFT) |
234 | #define RR_PS_READ_1024 (7 << RR_PS_READ_SHIFT) |
235 | |
236 | #define RR_PS_WRITE_MASK 0xe0 |
237 | #define RR_PS_WRITE_SHIFT 5 |
238 | #define RR_PS_WRITE_DISABLE (0 << RR_PS_WRITE_SHIFT) |
239 | #define RR_PS_WRITE_4 (1 << RR_PS_WRITE_SHIFT) |
240 | #define RR_PS_WRITE_16 (2 << RR_PS_WRITE_SHIFT) |
241 | #define RR_PS_WRITE_32 (3 << RR_PS_WRITE_SHIFT) |
242 | #define RR_PS_WRITE_64 (4 << RR_PS_WRITE_SHIFT) |
243 | #define RR_PS_WRITE_128 (5 << RR_PS_WRITE_SHIFT) |
244 | #define RR_PS_WRITE_256 (6 << RR_PS_WRITE_SHIFT) |
245 | #define RR_PS_WRITE_1024 (7 << RR_PS_WRITE_SHIFT) |
246 | #define RR_PS_MIN_DMA_MASK 0xff00 |
247 | #define RR_PS_MIN_DMA_SHIFT 8 |
248 | |
249 | /* HIPPI Receive State */ |
250 | |
251 | #define RR_RS_ENABLE 0x01 /* enable new connections */ |
252 | #define RR_RS_RESET 0x02 /* reset receive interface */ |
253 | #define RR_RS_REJECT_NONE 0x00 /* don't ever reject connections */ |
254 | #define RR_RS_REJECT_2K 0x20 /* reject if only 2KB free */ |
255 | #define RR_RS_REJECT_4K 0x30 /* reject if only 4KB free */ |
256 | #define RR_RS_REJECT_8K 0x40 /* reject if only 8KB free */ |
257 | #define RR_RS_REJECT_16K 0x50 /* reject if only 16KB free */ |
258 | #define RR_RS_REJECT_32K 0x60 /* reject if only 32KB free */ |
259 | #define RR_RS_REJECT_64K 0x70 /* reject if only 64KB free */ |
260 | |
261 | /* HIPPI Transmit State */ |
262 | |
263 | #define RR_TS_ENABLE 0x01 /* enable transmit state machine */ |
264 | #define RR_TS_PERMANENT 0x02 /* this connection permanent while set */ |
265 | |
266 | /* External Serial Data */ |
267 | |
268 | /* |
269 | * This controls hardware that is external to the RoadRunner. |
270 | * Bits 0-15 are set on write, 16-31 are read on read. |
271 | */ |
272 | |
273 | #define RR_ES_TDAV 0x004 /* transmit data available */ |
274 | #define RR_ES_LED1 0x008 /* LED1 control */ |
275 | #define RR_ES_LED2 0x010 /* LED2 control */ |
276 | #define RR_ES_RX_PERM 0x020 /* set permanent receive connection */ |
277 | #define RR_ES_LEDAUTO 0x040 /* clear to let LED1 and LED2 control LEDs */ |
278 | #define RR_ES_LLB_ENA 0x080 /* local loopback enable */ |
279 | #define RR_ES_TP_START 0x100 /* test points (bits 8-13) */ |
280 | |
281 | #define RR_ES_REGINT 0x10000 /* interrupt from SEEQ-8100 (Gig-E) */ |
282 | #define RR_ES_MISC 0x20000 /* misc input */ |
283 | #define RR_ES_RXSIGDET 0x40000 /* fiber optic RXSIGDET output */ |
284 | |
285 | /* DMA Read State */ |
286 | |
287 | #define RR_DR_RESET 0x001 /* set to reset read DMA */ |
288 | #define RR_DR_ACTIVE 0x008 /* set to start DMA */ |
289 | #define RR_DR_THRESHOLD_MASK 0x1f0 /* mask off threshold values */ |
290 | #define RR_DR_THRESHOLD_SHIFT 4 /* shift to set threshold values */ |
291 | #define RR_DR_THRESHOLD_MAX 16 |
292 | |
293 | /* DMA Write State */ |
294 | |
295 | #define RR_DW_RESET 0x001 /* set to reset write DMA */ |
296 | #define RR_DW_CKSUM 0x004 /* set to enable checksum calc on DMA */ |
297 | #define RR_DW_ACTIVE 0x008 /* set to start DMA */ |
298 | #define RR_DW_THRESHOLD_MASK 0x1f0 /* mask off threshold values */ |
299 | #define RR_DW_THRESHOLD_SHIFT 4 /* shift to set threshold values */ |
300 | #define RR_DW_THRESHOLD_MAX 18 |
301 | |
302 | |
303 | /* Operating Mode and Status */ |
304 | |
305 | #define RR_MS_LOOPBACK 0x0001 /* loopback through the GLink hardware */ |
306 | #define RR_MS_PH_MODE 0x0002 /* set for PH, clear for FP */ |
307 | #define RR_MS_LONG_PTRS 0x0004 /* set indicates 64-bit pointers */ |
308 | #define RR_MS_WORD_SWAP 0x0008 /* set to swap words in 64-bit pointers */ |
309 | #define RR_MS_WARNINGS 0x0010 /* set to enable warning events */ |
310 | #define RR_MS_ERR_TERM 0x0020 /* set to terminate connection on error */ |
311 | #define RR_MS_DIRECT 0x0040 /* debug flag. enable filterLA checks */ |
312 | #define RR_MS_NO_WATCHDOG 0x0080 /* set to disable watchdog */ |
313 | #define RR_MS_SWAP_DATA 0x0100 /* set to byte swap data */ |
314 | #define RR_MS_SWAP_CNTRL 0x0200 /* set to byte swap control structures */ |
315 | #define RR_MS_ERR_HALT 0x0400 /* set to halt NIC on RunCode error */ |
316 | #define RR_MS_NO_RESTART 0x0800 /* set to prevent NIC restart after error */ |
317 | #define RR_MS_TX_HALFDUP 0x1000 /* NIC does half-duplex transmit */ |
318 | #define RR_MS_RX_HALFDUP 0x2000 /* NIC does half-duplex receive */ |
319 | #define RR_MS_GIG_E 0x4000 /* NIC does Gig-E instead of HIPPI */ |
320 | |
321 | #define RR_MS_FATAL_ERR 0x4000000 /* fatal error on NIC */ |
322 | #define RR_MS_EVENT_OVER 0x8000000 /* event ring overflow */ |
323 | |
324 | /* Options field (top half of high word of ULA in RunCode) */ |
325 | |
326 | #define RR_OP_GIGE 0x01 /* Support for Gig-E NIC */ |
327 | #define RR_OP_TRACED 0x02 /* Runcode generates debug traces */ |
328 | #define RR_OP_1MEG 0x04 /* Support for 1MB of SRAM */ |
329 | #define RR_OP_CDI 0x08 /* Support for Character Device Interace */ |
330 | #define RR_OP_MSDOS 0x10 /* For testing RunCode under MS-DOS!? */ |
331 | #define RR_OP_COMEV 0x20 /* New v2 Command/Event interface */ |
332 | #define RR_OP_LONG_TX 0x40 /* Long transmit descr */ |
333 | #define RR_OP_LONG_RX 0x80 /* Long receive descr (set when not CDI) */ |
334 | |
335 | /* |
336 | * EEPROM locations |
337 | * |
338 | * The EEPROM layout is a little weird. There is a valid byte every |
339 | * eight bytes. Words are then smeared out over 32 bytes. |
340 | * All addresses listed here are the actual starting addresses. |
341 | * The programmer is responsible for assembling a word from each of the |
342 | * bytes available. |
343 | * |
344 | * NB: This is incomplete. I just ran out of patience for entering values. |
345 | */ |
346 | |
347 | #define RR_EE_OFFSET 0x80000000 /* offset to the start of EEPROM mem */ |
348 | #define RR_EE_WORD_LEN 0x20 /* jump between words in the EEPROM */ |
349 | #define RR_EE_BYTE_LEN 0x08 /* jump between bytes in the EEPROM */ |
350 | #define RR_EE_MAX_LEN 8192 /* maximum number of words in EEPROM */ |
351 | #define RR_EE_SEG_SIZE 512 /* maximum size of a segment */ |
352 | |
353 | #define RR_EE_PROM_INIT 0x801ff00 /* jump here to start RunCode loader */ |
354 | |
355 | #define 1 /* version number we can handle*/ |
356 | |
357 | #define RR_EE_SRAM_SIZE 0x0040 /* SRAM size */ |
358 | #define RR_EE_PHASE1_START 0x0060 /* target byte address in SRAM */ |
359 | #define RR_EE_PHASE1_LEN 0x0080 /* length in words of phase 1 */ |
360 | #define RR_EE_PHASE1_EE_START 0x00a0 /* address of phase 1 in EEPROM */ |
361 | |
362 | #define RR_EE_PCI_DEV_VEND 0x0100 /* PCI device/vendor */ |
363 | #define RR_EE_PCI_REV_CLASS 0x0120 /* PCI revision/class */ |
364 | #define RR_EE_PCI_LATENCY 0x0140 /* PCI latency timer */ |
365 | #define RR_EE_PCI_BAR0 0x0160 /* PCI bar0 address */ |
366 | #define RR_EE_PCI_COMM_STAT 0x0180 /* PCI command/status */ |
367 | #define RR_EE_PCI_LAT_GNT 0x01a0 /* PCI max latency/ minimum grant */ |
368 | #define RR_EE_PCI_CHECKSUM 0x01f0 /* PCI area checksum */ |
369 | |
370 | #define 0x0200 /* revision of header format |
371 | (should be 1) */ |
372 | #define RR_EE_ULA_HI 0x0500 /* Universal LAN Address (ULA) */ |
373 | #define RR_EE_ULA_LO 0x0520 |
374 | |
375 | #define RR_EE_RUNCODE_START 0x0a00 /* runcode start PC */ |
376 | #define RR_EE_RUNCODE_VERSION 0x0a20 /* runcode revision number */ |
377 | #define RR_EE_RUNCODE_DATE 0x0a40 /* runcode revision date */ |
378 | #define RR_EE_RUNCODE_SEGMENTS 0x0a80 /* address of count of segments */ |
379 | |
380 | #define RR_EE_MODE_AND_STATUS 0x0e00 /* mode and status saved value */ |
381 | #define RR_EE_CONN_RETRY_COUNT 0x0e20 /* connection retry count */ |
382 | #define RR_EE_CONN_RETRY_TIMER 0x0e40 /* clock ticks to delay retry */ |
383 | #define RR_EE_CONN_TIMEOUT 0x0e60 /* campon delay timeout */ |
384 | #define RR_EE_STATS_TIMER 0x0e80 /* clock ticks between stats copy */ |
385 | #define RR_EE_INTERRUPT_TIMER 0x0ea0 /* clock ticks between interrupts */ |
386 | #define RR_EE_TX_TIMEOUT 0x0ec0 /* transmit data not moving timer */ |
387 | #define RR_EE_RX_TIMEOUT 0x0ee0 /* receive data not moving timer */ |
388 | |
389 | #define RR_EE_PCI_STATE 0x0f00 /* misc PCI DMA config */ |
390 | #define RR_EE_DMA_WRITE_STATE 0x0f20 /* dma write config */ |
391 | #define RR_EE_DMA_READ_STATE 0x0f40 /* dma read config */ |
392 | #define RR_EE_DRIVER_PARAM 0x0f60 /* driver-specific params (unused) */ |
393 | |
394 | #define 0x0fe0 /* checksum for manufacturing header |
395 | (0x200 - 0xfc0) */ |
396 | |
397 | #define RR_EE_PHASE2_START 0x1040 /* phase 2 start in SRAM */ |
398 | #define RR_EE_PHASE2_LENGTH 0x1060 /* phase 2 length in words */ |
399 | #define RR_EE_PHASE2_EE_START 0x1080 /* phase 2 EEPROM start */ |
400 | |
401 | /* |
402 | * Event descriptor |
403 | */ |
404 | |
405 | struct rr_event { |
406 | u_int16_t re_index; /* merge? Different event types? */ |
407 | u_int8_t re_ring; |
408 | u_int8_t re_code; |
409 | u_int32_t re_timestamp; |
410 | }; |
411 | |
412 | /* |
413 | * Command descriptor |
414 | */ |
415 | |
416 | union rr_cmd { |
417 | struct { |
418 | u_int16_t rc_index; |
419 | u_int8_t rc_ring; |
420 | u_int8_t rc_code; |
421 | } b; |
422 | u_int32_t l; |
423 | }; |
424 | |
425 | /* |
426 | * Scatter/gather descriptor -- points to buffers to be DMA'ed in and |
427 | * out of host space. |
428 | */ |
429 | |
430 | struct rr_descr { |
431 | u_int32_t rd_reserved1; |
432 | u_int32_t rd_buffer_addr; |
433 | u_int32_t rd_reserved2; |
434 | u_int16_t rd_length; |
435 | u_int8_t rd_ring; |
436 | u_int8_t rd_control; |
437 | #define RR_CT_TX_IPCKSUM 0x04 |
438 | #define RR_CT_PACKET_END 0x08 |
439 | #define RR_CT_PACKET_START 0x10 |
440 | #define RR_CT_INTERRUPT 0x20 |
441 | #define RR_CT_SHORT_BURST 0x40 |
442 | #define RR_CT_SAME_IFIELD 0x80 |
443 | }; |
444 | |
445 | /* |
446 | * Long scatter/gather descriptor -- similar to above descriptor, |
447 | * but closer to RR's Assist register layout, so that it can just |
448 | * be DMA'ed into the NIC, and let loose. Required by Runcode v. 2 |
449 | * and greater. |
450 | */ |
451 | |
452 | struct rr2_descr { |
453 | u_int32_t rd_reserved1; |
454 | u_int32_t rd_buffer_addr; |
455 | u_int32_t rd_reserved2; |
456 | u_int16_t rd_length; |
457 | u_int8_t rd_reserved3; |
458 | u_int8_t rd_control; |
459 | u_int32_t rd_dma_state; |
460 | #define RR_DM_TX 0x00606 /* swap code for dma_state on tx */ |
461 | #define RR_DM_RX 0x20606 /* swap code for dma_state on rx */ |
462 | u_int32_t rd_reserved4; |
463 | u_int32_t rd_pkt_length; |
464 | u_int32_t rd_reserved5; |
465 | #define RR2_CT_INTERRUPT 0x02 |
466 | #define RR2_CT_TX_IPCKSUM 0x04 |
467 | #define RR2_CT_PACKET_END 0x08 |
468 | #define RR2_CT_PACKET_START 0x10 |
469 | #define RR2_CT_RING_OUT 0x20 |
470 | #define RR2_CT_SHORT_BURST 0x40 |
471 | #define RR2_CT_SAME_IFIELD 0x80 |
472 | }; |
473 | |
474 | /* |
475 | * Ring control structure -- points to array of buffer descriptors |
476 | */ |
477 | |
478 | struct rr_ring_ctl { |
479 | u_int32_t rr_reserved1; |
480 | u_int32_t rr_ring_addr; /* pointer to array of s/g descrs */ |
481 | u_int16_t rr_entries; |
482 | u_int8_t rr_free_bufs; |
483 | #define RR_RR_DONT_COMPLAIN 0xff /* disable free_bufs warning */ |
484 | u_int8_t rr_entry_size; |
485 | u_int16_t rr_prod_index; |
486 | u_int16_t rr_mode; |
487 | /* XXX: Picture in docs is right, description is wrong */ |
488 | #define RR_RR_CHARACTER 0x01 /* character mode interface */ |
489 | #define RR_RR_SEPARATE 0x02 /* separate headers from data */ |
490 | #define RR_RR_CHECKSUM 0x04 /* doing IP checksums (requires IP on) */ |
491 | #define RR_RR_IP 0x08 /* receiving IP packets to this ring */ |
492 | }; |
493 | |
494 | /* Statistics block, for now, undifferentiated. */ |
495 | |
496 | struct rr_stats { |
497 | u_int32_t rs_stats[128]; |
498 | }; |
499 | |
500 | /* |
501 | * General information block |
502 | */ |
503 | |
504 | struct rr_gen_info { |
505 | struct rr_stats ri_stats; |
506 | struct rr_ring_ctl ri_event_ring_ctl; |
507 | struct rr_ring_ctl ri_cmd_ring_ctl; |
508 | struct rr_ring_ctl ri_send_ring_ctl; |
509 | u_int8_t ri_reserved1[464]; |
510 | u_int8_t ri_nic_trace[3072]; |
511 | }; |
512 | |
513 | /* |
514 | * A few constants: |
515 | */ |
516 | |
517 | #define RR_DMA_BOUNDARY (64 * 1024) /* can't cross 64K boundaries on DMA */ |
518 | #define RR_DMA_MAX 65535 /* maximum that can be transferred in |
519 | one DMA operation */ |
520 | #define RR_ULP_COUNT 256 /* number of possible ULPs */ |
521 | #define RR_INIT_CMD 15 /* initial command index */ |
522 | |
523 | /* NB: All of the ring sizes have to be powers of two */ |
524 | |
525 | #define RR_MAX_RECV_RING 32 /* maximum number of receive rings */ |
526 | #define RR_MAX_DESCR 256 /* maximum number of possible |
527 | descriptors. XXX: increase |
528 | with caution, as this allocates |
529 | static space! */ |
530 | #define RR_EVENT_RING_SIZE 128 /* why not go for it? */ |
531 | #define RR_SEND_RING_SIZE 32 /* firmware restriction! */ |
532 | |
533 | #define RR_SNAP_RECV_RING_SIZE 32 /* seems to work */ |
534 | #define RR_FP_RECV_RING_SIZE 32 /* seems to work */ |
535 | |
536 | #define RR2_SEND_RING_SIZE 16 /* firmware restriction! */ |
537 | #define RR2_SNAP_RECV_RING_SIZE 16 /* firmware restriction! */ |
538 | |
539 | #define RR_MAX_SEND_RING_SIZE max(RR_SEND_RING_SIZE, RR2_SEND_RING_SIZE) |
540 | #define RR_MAX_SNAP_RECV_RING_SIZE \ |
541 | max(RR_SNAP_RECV_RING_SIZE, RR_SNAP_RECV_RING_SIZE) |
542 | |