1/* $NetBSD: nouveau_engine_disp_sornv94.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */
2
3/*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26
27#include <sys/cdefs.h>
28__KERNEL_RCSID(0, "$NetBSD: nouveau_engine_disp_sornv94.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $");
29
30#include <core/os.h>
31#include <core/class.h>
32
33#include <subdev/bios.h>
34#include <subdev/bios/dcb.h>
35#include <subdev/bios/dp.h>
36#include <subdev/bios/init.h>
37
38#include "nv50.h"
39
40static inline u32
41nv94_sor_soff(struct dcb_output *outp)
42{
43 return (ffs(outp->or) - 1) * 0x800;
44}
45
46static inline u32
47nv94_sor_loff(struct dcb_output *outp)
48{
49 return nv94_sor_soff(outp) + !(outp->sorconf.link & 1) * 0x80;
50}
51
52static inline u32
53nv94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
54{
55 static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
56 static const u8 nv94[] = { 16, 8, 0, 24 };
57 if (nv_device(priv)->chipset == 0xaf)
58 return nvaf[lane];
59 return nv94[lane];
60}
61
62static int
63nv94_sor_dp_pattern(struct nouveau_disp *disp, struct dcb_output *outp,
64 int head, int pattern)
65{
66 struct nv50_disp_priv *priv = (void *)disp;
67 const u32 loff = nv94_sor_loff(outp);
68 nv_mask(priv, 0x61c10c + loff, 0x0f000000, pattern << 24);
69 return 0;
70}
71
72static int
73nv94_sor_dp_lnk_ctl(struct nouveau_disp *disp, struct dcb_output *outp,
74 int head, int link_nr, int link_bw, bool enh_frame)
75{
76 struct nv50_disp_priv *priv = (void *)disp;
77 const u32 soff = nv94_sor_soff(outp);
78 const u32 loff = nv94_sor_loff(outp);
79 u32 dpctrl = 0x00000000;
80 u32 clksor = 0x00000000;
81 u32 lane = 0;
82 int i;
83
84 dpctrl |= ((1 << link_nr) - 1) << 16;
85 if (enh_frame)
86 dpctrl |= 0x00004000;
87 if (link_bw > 0x06)
88 clksor |= 0x00040000;
89
90 for (i = 0; i < link_nr; i++)
91 lane |= 1 << (nv94_sor_dp_lane_map(priv, i) >> 3);
92
93 nv_mask(priv, 0x614300 + soff, 0x000c0000, clksor);
94 nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl);
95 nv_mask(priv, 0x61c130 + loff, 0x0000000f, lane);
96 return 0;
97}
98
99static int
100nv94_sor_dp_drv_ctl(struct nouveau_disp *disp, struct dcb_output *outp,
101 int head, int lane, int swing, int preem)
102{
103 struct nouveau_bios *bios = nouveau_bios(disp);
104 struct nv50_disp_priv *priv = (void *)disp;
105 const u32 shift = nv94_sor_dp_lane_map(priv, lane);
106 const u32 loff = nv94_sor_loff(outp);
107 u32 addr, data[3];
108 u8 ver, hdr, cnt, len;
109 struct nvbios_dpout info;
110 struct nvbios_dpcfg ocfg;
111
112 addr = nvbios_dpout_match(bios, outp->hasht, outp->hashm,
113 &ver, &hdr, &cnt, &len, &info);
114 if (!addr)
115 return -ENODEV;
116
117 addr = nvbios_dpcfg_match(bios, addr, 0, swing, preem,
118 &ver, &hdr, &cnt, &len, &ocfg);
119 if (!addr)
120 return -EINVAL;
121
122 data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
123 data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
124 data[2] = nv_rd32(priv, 0x61c130 + loff) & ~(0x0000ff00);
125 nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.drv << shift));
126 nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pre << shift));
127 nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.unk << 8));
128 return 0;
129}
130
131const struct nouveau_dp_func
132nv94_sor_dp_func = {
133 .pattern = nv94_sor_dp_pattern,
134 .lnk_ctl = nv94_sor_dp_lnk_ctl,
135 .drv_ctl = nv94_sor_dp_drv_ctl,
136};
137