1 | /* $NetBSD: nouveau_engine_graph_nv50.c,v 1.2 2014/08/23 08:03:33 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_graph_nv50.c,v 1.2 2014/08/23 08:03:33 riastradh Exp $" ); |
29 | |
30 | #include <core/os.h> |
31 | #include <core/class.h> |
32 | #include <core/client.h> |
33 | #include <core/handle.h> |
34 | #include <core/engctx.h> |
35 | #include <core/enum.h> |
36 | |
37 | #include <subdev/fb.h> |
38 | #include <subdev/vm.h> |
39 | #include <subdev/timer.h> |
40 | |
41 | #include <engine/fifo.h> |
42 | #include <engine/graph.h> |
43 | |
44 | #include "nv50.h" |
45 | |
46 | struct nv50_graph_priv { |
47 | struct nouveau_graph base; |
48 | spinlock_t lock; |
49 | u32 size; |
50 | }; |
51 | |
52 | struct nv50_graph_chan { |
53 | struct nouveau_graph_chan base; |
54 | }; |
55 | |
56 | static u64 |
57 | nv50_graph_units(struct nouveau_graph *graph) |
58 | { |
59 | struct nv50_graph_priv *priv = (void *)graph; |
60 | |
61 | return nv_rd32(priv, 0x1540); |
62 | } |
63 | |
64 | /******************************************************************************* |
65 | * Graphics object classes |
66 | ******************************************************************************/ |
67 | |
68 | static int |
69 | nv50_graph_object_ctor(struct nouveau_object *parent, |
70 | struct nouveau_object *engine, |
71 | struct nouveau_oclass *oclass, void *data, u32 size, |
72 | struct nouveau_object **pobject) |
73 | { |
74 | struct nouveau_gpuobj *obj; |
75 | int ret; |
76 | |
77 | ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, |
78 | 16, 16, 0, &obj); |
79 | *pobject = nv_object(obj); |
80 | if (ret) |
81 | return ret; |
82 | |
83 | nv_wo32(obj, 0x00, nv_mclass(obj)); |
84 | nv_wo32(obj, 0x04, 0x00000000); |
85 | nv_wo32(obj, 0x08, 0x00000000); |
86 | nv_wo32(obj, 0x0c, 0x00000000); |
87 | return 0; |
88 | } |
89 | |
90 | static struct nouveau_ofuncs |
91 | nv50_graph_ofuncs = { |
92 | .ctor = nv50_graph_object_ctor, |
93 | .dtor = _nouveau_gpuobj_dtor, |
94 | .init = _nouveau_gpuobj_init, |
95 | .fini = _nouveau_gpuobj_fini, |
96 | .rd32 = _nouveau_gpuobj_rd32, |
97 | .wr32 = _nouveau_gpuobj_wr32, |
98 | }; |
99 | |
100 | static struct nouveau_oclass |
101 | nv50_graph_sclass[] = { |
102 | { 0x0030, &nv50_graph_ofuncs }, |
103 | { 0x502d, &nv50_graph_ofuncs }, |
104 | { 0x5039, &nv50_graph_ofuncs }, |
105 | { 0x5097, &nv50_graph_ofuncs }, |
106 | { 0x50c0, &nv50_graph_ofuncs }, |
107 | {} |
108 | }; |
109 | |
110 | static struct nouveau_oclass |
111 | nv84_graph_sclass[] = { |
112 | { 0x0030, &nv50_graph_ofuncs }, |
113 | { 0x502d, &nv50_graph_ofuncs }, |
114 | { 0x5039, &nv50_graph_ofuncs }, |
115 | { 0x50c0, &nv50_graph_ofuncs }, |
116 | { 0x8297, &nv50_graph_ofuncs }, |
117 | {} |
118 | }; |
119 | |
120 | static struct nouveau_oclass |
121 | nva0_graph_sclass[] = { |
122 | { 0x0030, &nv50_graph_ofuncs }, |
123 | { 0x502d, &nv50_graph_ofuncs }, |
124 | { 0x5039, &nv50_graph_ofuncs }, |
125 | { 0x50c0, &nv50_graph_ofuncs }, |
126 | { 0x8397, &nv50_graph_ofuncs }, |
127 | {} |
128 | }; |
129 | |
130 | static struct nouveau_oclass |
131 | nva3_graph_sclass[] = { |
132 | { 0x0030, &nv50_graph_ofuncs }, |
133 | { 0x502d, &nv50_graph_ofuncs }, |
134 | { 0x5039, &nv50_graph_ofuncs }, |
135 | { 0x50c0, &nv50_graph_ofuncs }, |
136 | { 0x8597, &nv50_graph_ofuncs }, |
137 | { 0x85c0, &nv50_graph_ofuncs }, |
138 | {} |
139 | }; |
140 | |
141 | static struct nouveau_oclass |
142 | nvaf_graph_sclass[] = { |
143 | { 0x0030, &nv50_graph_ofuncs }, |
144 | { 0x502d, &nv50_graph_ofuncs }, |
145 | { 0x5039, &nv50_graph_ofuncs }, |
146 | { 0x50c0, &nv50_graph_ofuncs }, |
147 | { 0x85c0, &nv50_graph_ofuncs }, |
148 | { 0x8697, &nv50_graph_ofuncs }, |
149 | {} |
150 | }; |
151 | |
152 | /******************************************************************************* |
153 | * PGRAPH context |
154 | ******************************************************************************/ |
155 | |
156 | static int |
157 | nv50_graph_context_ctor(struct nouveau_object *parent, |
158 | struct nouveau_object *engine, |
159 | struct nouveau_oclass *oclass, void *data, u32 size, |
160 | struct nouveau_object **pobject) |
161 | { |
162 | struct nv50_graph_priv *priv = (void *)engine; |
163 | struct nv50_graph_chan *chan; |
164 | int ret; |
165 | |
166 | ret = nouveau_graph_context_create(parent, engine, oclass, NULL, |
167 | priv->size, 0, |
168 | NVOBJ_FLAG_ZERO_ALLOC, &chan); |
169 | *pobject = nv_object(chan); |
170 | if (ret) |
171 | return ret; |
172 | |
173 | nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan)); |
174 | return 0; |
175 | } |
176 | |
177 | static struct nouveau_oclass |
178 | nv50_graph_cclass = { |
179 | .handle = NV_ENGCTX(GR, 0x50), |
180 | .ofuncs = &(struct nouveau_ofuncs) { |
181 | .ctor = nv50_graph_context_ctor, |
182 | .dtor = _nouveau_graph_context_dtor, |
183 | .init = _nouveau_graph_context_init, |
184 | .fini = _nouveau_graph_context_fini, |
185 | .rd32 = _nouveau_graph_context_rd32, |
186 | .wr32 = _nouveau_graph_context_wr32, |
187 | }, |
188 | }; |
189 | |
190 | /******************************************************************************* |
191 | * PGRAPH engine/subdev functions |
192 | ******************************************************************************/ |
193 | |
194 | static const struct nouveau_bitfield nv50_pgraph_status[] = { |
195 | { 0x00000001, "BUSY" }, /* set when any bit is set */ |
196 | { 0x00000002, "DISPATCH" }, |
197 | { 0x00000004, "UNK2" }, |
198 | { 0x00000008, "UNK3" }, |
199 | { 0x00000010, "UNK4" }, |
200 | { 0x00000020, "UNK5" }, |
201 | { 0x00000040, "M2MF" }, |
202 | { 0x00000080, "UNK7" }, |
203 | { 0x00000100, "CTXPROG" }, |
204 | { 0x00000200, "VFETCH" }, |
205 | { 0x00000400, "CCACHE_PREGEOM" }, |
206 | { 0x00000800, "STRMOUT_VATTR_POSTGEOM" }, |
207 | { 0x00001000, "VCLIP" }, |
208 | { 0x00002000, "RATTR_APLANE" }, |
209 | { 0x00004000, "TRAST" }, |
210 | { 0x00008000, "CLIPID" }, |
211 | { 0x00010000, "ZCULL" }, |
212 | { 0x00020000, "ENG2D" }, |
213 | { 0x00040000, "RMASK" }, |
214 | { 0x00080000, "TPC_RAST" }, |
215 | { 0x00100000, "TPC_PROP" }, |
216 | { 0x00200000, "TPC_TEX" }, |
217 | { 0x00400000, "TPC_GEOM" }, |
218 | { 0x00800000, "TPC_MP" }, |
219 | { 0x01000000, "ROP" }, |
220 | {} |
221 | }; |
222 | |
223 | static const char *const nv50_pgraph_vstatus_0[] = { |
224 | "VFETCH" , "CCACHE" , "PREGEOM" , "POSTGEOM" , "VATTR" , "STRMOUT" , "VCLIP" , |
225 | NULL |
226 | }; |
227 | |
228 | static const char *const nv50_pgraph_vstatus_1[] = { |
229 | "TPC_RAST" , "TPC_PROP" , "TPC_TEX" , "TPC_GEOM" , "TPC_MP" , NULL |
230 | }; |
231 | |
232 | static const char *const nv50_pgraph_vstatus_2[] = { |
233 | "RATTR" , "APLANE" , "TRAST" , "CLIPID" , "ZCULL" , "ENG2D" , "RMASK" , |
234 | "ROP" , NULL |
235 | }; |
236 | |
237 | static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r, |
238 | const char *const units[], u32 status) |
239 | { |
240 | int i; |
241 | |
242 | nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x" , r, status); |
243 | |
244 | for (i = 0; units[i] && status; i++) { |
245 | if ((status & 7) == 1) |
246 | pr_cont(" %s" , units[i]); |
247 | status >>= 3; |
248 | } |
249 | if (status) |
250 | pr_cont(" (invalid: 0x%x)" , status); |
251 | pr_cont("\n" ); |
252 | } |
253 | |
254 | static int |
255 | nv84_graph_tlb_flush(struct nouveau_engine *engine) |
256 | { |
257 | struct nouveau_timer *ptimer = nouveau_timer(engine); |
258 | struct nv50_graph_priv *priv = (void *)engine; |
259 | bool idle, timeout = false; |
260 | unsigned long flags; |
261 | u64 start; |
262 | u32 tmp; |
263 | |
264 | spin_lock_irqsave(&priv->lock, flags); |
265 | nv_mask(priv, 0x400500, 0x00000001, 0x00000000); |
266 | |
267 | start = ptimer->read(ptimer); |
268 | do { |
269 | idle = true; |
270 | |
271 | for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) { |
272 | if ((tmp & 7) == 1) |
273 | idle = false; |
274 | } |
275 | |
276 | for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) { |
277 | if ((tmp & 7) == 1) |
278 | idle = false; |
279 | } |
280 | |
281 | for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) { |
282 | if ((tmp & 7) == 1) |
283 | idle = false; |
284 | } |
285 | } while (!idle && |
286 | !(timeout = ptimer->read(ptimer) - start > 2000000000)); |
287 | |
288 | if (timeout) { |
289 | nv_error(priv, "PGRAPH TLB flush idle timeout fail\n" ); |
290 | |
291 | tmp = nv_rd32(priv, 0x400700); |
292 | nv_error(priv, "PGRAPH_STATUS : 0x%08x" , tmp); |
293 | nouveau_bitfield_print(nv50_pgraph_status, tmp); |
294 | pr_cont("\n" ); |
295 | |
296 | nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0, |
297 | nv_rd32(priv, 0x400380)); |
298 | nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1, |
299 | nv_rd32(priv, 0x400384)); |
300 | nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2, |
301 | nv_rd32(priv, 0x400388)); |
302 | } |
303 | |
304 | |
305 | nv_wr32(priv, 0x100c80, 0x00000001); |
306 | if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) |
307 | nv_error(priv, "vm flush timeout\n" ); |
308 | nv_mask(priv, 0x400500, 0x00000001, 0x00000001); |
309 | spin_unlock_irqrestore(&priv->lock, flags); |
310 | return timeout ? -EBUSY : 0; |
311 | } |
312 | |
313 | static const struct nouveau_bitfield nv50_mp_exec_errors[] = { |
314 | { 0x01, "STACK_UNDERFLOW" }, |
315 | { 0x02, "STACK_MISMATCH" }, |
316 | { 0x04, "QUADON_ACTIVE" }, |
317 | { 0x08, "TIMEOUT" }, |
318 | { 0x10, "INVALID_OPCODE" }, |
319 | { 0x20, "PM_OVERFLOW" }, |
320 | { 0x40, "BREAKPOINT" }, |
321 | {} |
322 | }; |
323 | |
324 | static const struct nouveau_bitfield nv50_mpc_traps[] = { |
325 | { 0x0000001, "LOCAL_LIMIT_READ" }, |
326 | { 0x0000010, "LOCAL_LIMIT_WRITE" }, |
327 | { 0x0000040, "STACK_LIMIT" }, |
328 | { 0x0000100, "GLOBAL_LIMIT_READ" }, |
329 | { 0x0001000, "GLOBAL_LIMIT_WRITE" }, |
330 | { 0x0010000, "MP0" }, |
331 | { 0x0020000, "MP1" }, |
332 | { 0x0040000, "GLOBAL_LIMIT_RED" }, |
333 | { 0x0400000, "GLOBAL_LIMIT_ATOM" }, |
334 | { 0x4000000, "MP2" }, |
335 | {} |
336 | }; |
337 | |
338 | static const struct nouveau_bitfield nv50_tex_traps[] = { |
339 | { 0x00000001, "" }, /* any bit set? */ |
340 | { 0x00000002, "FAULT" }, |
341 | { 0x00000004, "STORAGE_TYPE_MISMATCH" }, |
342 | { 0x00000008, "LINEAR_MISMATCH" }, |
343 | { 0x00000020, "WRONG_MEMTYPE" }, |
344 | {} |
345 | }; |
346 | |
347 | static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = { |
348 | { 0x00000001, "NOTIFY" }, |
349 | { 0x00000002, "IN" }, |
350 | { 0x00000004, "OUT" }, |
351 | {} |
352 | }; |
353 | |
354 | static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = { |
355 | { 0x00000001, "FAULT" }, |
356 | {} |
357 | }; |
358 | |
359 | static const struct nouveau_bitfield nv50_graph_trap_strmout[] = { |
360 | { 0x00000001, "FAULT" }, |
361 | {} |
362 | }; |
363 | |
364 | static const struct nouveau_bitfield nv50_graph_trap_ccache[] = { |
365 | { 0x00000001, "FAULT" }, |
366 | {} |
367 | }; |
368 | |
369 | /* There must be a *lot* of these. Will take some time to gather them up. */ |
370 | const struct nouveau_enum nv50_data_error_names[] = { |
371 | { 0x00000003, "INVALID_OPERATION" , NULL }, |
372 | { 0x00000004, "INVALID_VALUE" , NULL }, |
373 | { 0x00000005, "INVALID_ENUM" , NULL }, |
374 | { 0x00000008, "INVALID_OBJECT" , NULL }, |
375 | { 0x00000009, "READ_ONLY_OBJECT" , NULL }, |
376 | { 0x0000000a, "SUPERVISOR_OBJECT" , NULL }, |
377 | { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT" , NULL }, |
378 | { 0x0000000c, "INVALID_BITFIELD" , NULL }, |
379 | { 0x0000000d, "BEGIN_END_ACTIVE" , NULL }, |
380 | { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT" , NULL }, |
381 | { 0x0000000f, "VIEWPORT_ID_NEEDS_GP" , NULL }, |
382 | { 0x00000010, "RT_DOUBLE_BIND" , NULL }, |
383 | { 0x00000011, "RT_TYPES_MISMATCH" , NULL }, |
384 | { 0x00000012, "RT_LINEAR_WITH_ZETA" , NULL }, |
385 | { 0x00000015, "FP_TOO_FEW_REGS" , NULL }, |
386 | { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH" , NULL }, |
387 | { 0x00000017, "RT_LINEAR_WITH_MSAA" , NULL }, |
388 | { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT" , NULL }, |
389 | { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT" , NULL }, |
390 | { 0x0000001a, "RT_INVALID_ALIGNMENT" , NULL }, |
391 | { 0x0000001b, "SAMPLER_OVER_LIMIT" , NULL }, |
392 | { 0x0000001c, "TEXTURE_OVER_LIMIT" , NULL }, |
393 | { 0x0000001e, "GP_TOO_MANY_OUTPUTS" , NULL }, |
394 | { 0x0000001f, "RT_BPP128_WITH_MS8" , NULL }, |
395 | { 0x00000021, "Z_OUT_OF_BOUNDS" , NULL }, |
396 | { 0x00000023, "XY_OUT_OF_BOUNDS" , NULL }, |
397 | { 0x00000024, "VP_ZERO_INPUTS" , NULL }, |
398 | { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED" , NULL }, |
399 | { 0x00000028, "CP_NO_REG_SPACE_STRIPED" , NULL }, |
400 | { 0x00000029, "CP_NO_REG_SPACE_PACKED" , NULL }, |
401 | { 0x0000002a, "CP_NOT_ENOUGH_WARPS" , NULL }, |
402 | { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH" , NULL }, |
403 | { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS" , NULL }, |
404 | { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS" , NULL }, |
405 | { 0x0000002e, "CP_NO_BLOCKDIM_LATCH" , NULL }, |
406 | { 0x00000031, "ENG2D_FORMAT_MISMATCH" , NULL }, |
407 | { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP" , NULL }, |
408 | { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT" , NULL }, |
409 | { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT" , NULL }, |
410 | { 0x00000046, "LAYER_ID_NEEDS_GP" , NULL }, |
411 | { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT" , NULL }, |
412 | { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT" , NULL }, |
413 | {} |
414 | }; |
415 | |
416 | static const struct nouveau_bitfield nv50_graph_intr_name[] = { |
417 | { 0x00000001, "NOTIFY" }, |
418 | { 0x00000002, "COMPUTE_QUERY" }, |
419 | { 0x00000010, "ILLEGAL_MTHD" }, |
420 | { 0x00000020, "ILLEGAL_CLASS" }, |
421 | { 0x00000040, "DOUBLE_NOTIFY" }, |
422 | { 0x00001000, "CONTEXT_SWITCH" }, |
423 | { 0x00010000, "BUFFER_NOTIFY" }, |
424 | { 0x00100000, "DATA_ERROR" }, |
425 | { 0x00200000, "TRAP" }, |
426 | { 0x01000000, "SINGLE_STEP" }, |
427 | {} |
428 | }; |
429 | |
430 | static const struct nouveau_bitfield nv50_graph_trap_prop[] = { |
431 | { 0x00000004, "SURF_WIDTH_OVERRUN" }, |
432 | { 0x00000008, "SURF_HEIGHT_OVERRUN" }, |
433 | { 0x00000010, "DST2D_FAULT" }, |
434 | { 0x00000020, "ZETA_FAULT" }, |
435 | { 0x00000040, "RT_FAULT" }, |
436 | { 0x00000080, "CUDA_FAULT" }, |
437 | { 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" }, |
438 | { 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" }, |
439 | { 0x00000400, "RT_STORAGE_TYPE_MISMATCH" }, |
440 | { 0x00000800, "DST2D_LINEAR_MISMATCH" }, |
441 | { 0x00001000, "RT_LINEAR_MISMATCH" }, |
442 | {} |
443 | }; |
444 | |
445 | static void |
446 | nv50_priv_prop_trap(struct nv50_graph_priv *priv, |
447 | u32 ustatus_addr, u32 ustatus, u32 tp) |
448 | { |
449 | u32 e0c = nv_rd32(priv, ustatus_addr + 0x04); |
450 | u32 e10 = nv_rd32(priv, ustatus_addr + 0x08); |
451 | u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c); |
452 | u32 e18 = nv_rd32(priv, ustatus_addr + 0x10); |
453 | u32 e1c = nv_rd32(priv, ustatus_addr + 0x14); |
454 | u32 e20 = nv_rd32(priv, ustatus_addr + 0x18); |
455 | u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c); |
456 | |
457 | /* CUDA memory: l[], g[] or stack. */ |
458 | if (ustatus & 0x00000080) { |
459 | if (e18 & 0x80000000) { |
460 | /* g[] read fault? */ |
461 | nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n" , |
462 | tp, e14, e10 | ((e18 >> 24) & 0x1f)); |
463 | e18 &= ~0x1f000000; |
464 | } else if (e18 & 0xc) { |
465 | /* g[] write fault? */ |
466 | nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n" , |
467 | tp, e14, e10 | ((e18 >> 7) & 0x1f)); |
468 | e18 &= ~0x00000f80; |
469 | } else { |
470 | nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n" , |
471 | tp, e14, e10); |
472 | } |
473 | ustatus &= ~0x00000080; |
474 | } |
475 | if (ustatus) { |
476 | nv_error(priv, "TRAP_PROP - TP %d -" , tp); |
477 | nouveau_bitfield_print(nv50_graph_trap_prop, ustatus); |
478 | pr_cont(" - Address %02x%08x\n" , e14, e10); |
479 | } |
480 | nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n" , |
481 | tp, e0c, e18, e1c, e20, e24); |
482 | } |
483 | |
484 | static void |
485 | nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display) |
486 | { |
487 | u32 units = nv_rd32(priv, 0x1540); |
488 | u32 addr, mp10, status, pc, oplow, ophigh; |
489 | int i; |
490 | int mps = 0; |
491 | for (i = 0; i < 4; i++) { |
492 | if (!(units & 1 << (i+24))) |
493 | continue; |
494 | if (nv_device(priv)->chipset < 0xa0) |
495 | addr = 0x408200 + (tpid << 12) + (i << 7); |
496 | else |
497 | addr = 0x408100 + (tpid << 11) + (i << 7); |
498 | mp10 = nv_rd32(priv, addr + 0x10); |
499 | status = nv_rd32(priv, addr + 0x14); |
500 | if (!status) |
501 | continue; |
502 | if (display) { |
503 | nv_rd32(priv, addr + 0x20); |
504 | pc = nv_rd32(priv, addr + 0x24); |
505 | oplow = nv_rd32(priv, addr + 0x70); |
506 | ophigh = nv_rd32(priv, addr + 0x74); |
507 | nv_error(priv, "TRAP_MP_EXEC - " |
508 | "TP %d MP %d:" , tpid, i); |
509 | nouveau_bitfield_print(nv50_mp_exec_errors, status); |
510 | pr_cont(" at %06x warp %d, opcode %08x %08x\n" , |
511 | pc&0xffffff, pc >> 24, |
512 | oplow, ophigh); |
513 | } |
514 | nv_wr32(priv, addr + 0x10, mp10); |
515 | nv_wr32(priv, addr + 0x14, 0); |
516 | mps++; |
517 | } |
518 | if (!mps && display) |
519 | nv_error(priv, "TRAP_MP_EXEC - TP %d: " |
520 | "No MPs claiming errors?\n" , tpid); |
521 | } |
522 | |
523 | static void |
524 | nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old, |
525 | u32 ustatus_new, int display, const char *name) |
526 | { |
527 | int tps = 0; |
528 | u32 units = nv_rd32(priv, 0x1540); |
529 | int i, r; |
530 | u32 ustatus_addr, ustatus; |
531 | for (i = 0; i < 16; i++) { |
532 | if (!(units & (1 << i))) |
533 | continue; |
534 | if (nv_device(priv)->chipset < 0xa0) |
535 | ustatus_addr = ustatus_old + (i << 12); |
536 | else |
537 | ustatus_addr = ustatus_new + (i << 11); |
538 | ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff; |
539 | if (!ustatus) |
540 | continue; |
541 | tps++; |
542 | switch (type) { |
543 | case 6: /* texture error... unknown for now */ |
544 | if (display) { |
545 | nv_error(priv, "magic set %d:\n" , i); |
546 | for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4) |
547 | nv_error(priv, "\t0x%08x: 0x%08x\n" , r, |
548 | nv_rd32(priv, r)); |
549 | if (ustatus) { |
550 | nv_error(priv, "%s - TP%d:" , name, i); |
551 | nouveau_bitfield_print(nv50_tex_traps, |
552 | ustatus); |
553 | pr_cont("\n" ); |
554 | ustatus = 0; |
555 | } |
556 | } |
557 | break; |
558 | case 7: /* MP error */ |
559 | if (ustatus & 0x04030000) { |
560 | nv50_priv_mp_trap(priv, i, display); |
561 | ustatus &= ~0x04030000; |
562 | } |
563 | if (ustatus && display) { |
564 | nv_error(priv, "%s - TP%d:" , name, i); |
565 | nouveau_bitfield_print(nv50_mpc_traps, ustatus); |
566 | pr_cont("\n" ); |
567 | ustatus = 0; |
568 | } |
569 | break; |
570 | case 8: /* PROP error */ |
571 | if (display) |
572 | nv50_priv_prop_trap( |
573 | priv, ustatus_addr, ustatus, i); |
574 | ustatus = 0; |
575 | break; |
576 | } |
577 | if (ustatus) { |
578 | if (display) |
579 | nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n" , name, i, ustatus); |
580 | } |
581 | nv_wr32(priv, ustatus_addr, 0xc0000000); |
582 | } |
583 | |
584 | if (!tps && display) |
585 | nv_warn(priv, "%s - No TPs claiming errors?\n" , name); |
586 | } |
587 | |
588 | static int |
589 | nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, |
590 | int chid, u64 inst, struct nouveau_object *engctx) |
591 | { |
592 | u32 status = nv_rd32(priv, 0x400108); |
593 | u32 ustatus; |
594 | |
595 | if (!status && display) { |
596 | nv_error(priv, "TRAP: no units reporting traps?\n" ); |
597 | return 1; |
598 | } |
599 | |
600 | /* DISPATCH: Relays commands to other units and handles NOTIFY, |
601 | * COND, QUERY. If you get a trap from it, the command is still stuck |
602 | * in DISPATCH and you need to do something about it. */ |
603 | if (status & 0x001) { |
604 | ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff; |
605 | if (!ustatus && display) { |
606 | nv_error(priv, "TRAP_DISPATCH - no ustatus?\n" ); |
607 | } |
608 | |
609 | nv_wr32(priv, 0x400500, 0x00000000); |
610 | |
611 | /* Known to be triggered by screwed up NOTIFY and COND... */ |
612 | if (ustatus & 0x00000001) { |
613 | u32 addr = nv_rd32(priv, 0x400808); |
614 | u32 subc = (addr & 0x00070000) >> 16; |
615 | u32 mthd = (addr & 0x00001ffc); |
616 | u32 datal = nv_rd32(priv, 0x40080c); |
617 | u32 datah = nv_rd32(priv, 0x400810); |
618 | u32 class = nv_rd32(priv, 0x400814); |
619 | u32 r848 = nv_rd32(priv, 0x400848); |
620 | |
621 | nv_error(priv, "TRAP DISPATCH_FAULT\n" ); |
622 | if (display && (addr & 0x80000000)) { |
623 | nv_error(priv, |
624 | "ch %d [0x%010" PRIx64" %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n" , |
625 | chid, inst, |
626 | nouveau_client_name(engctx), subc, |
627 | class, mthd, datah, datal, addr, r848); |
628 | } else |
629 | if (display) { |
630 | nv_error(priv, "no stuck command?\n" ); |
631 | } |
632 | |
633 | nv_wr32(priv, 0x400808, 0); |
634 | nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3); |
635 | nv_wr32(priv, 0x400848, 0); |
636 | ustatus &= ~0x00000001; |
637 | } |
638 | |
639 | if (ustatus & 0x00000002) { |
640 | u32 addr = nv_rd32(priv, 0x40084c); |
641 | u32 subc = (addr & 0x00070000) >> 16; |
642 | u32 mthd = (addr & 0x00001ffc); |
643 | u32 data = nv_rd32(priv, 0x40085c); |
644 | u32 class = nv_rd32(priv, 0x400814); |
645 | |
646 | nv_error(priv, "TRAP DISPATCH_QUERY\n" ); |
647 | if (display && (addr & 0x80000000)) { |
648 | nv_error(priv, |
649 | "ch %d [0x%010" PRIx64" %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n" , |
650 | chid, inst, |
651 | nouveau_client_name(engctx), subc, |
652 | class, mthd, data, addr); |
653 | } else |
654 | if (display) { |
655 | nv_error(priv, "no stuck command?\n" ); |
656 | } |
657 | |
658 | nv_wr32(priv, 0x40084c, 0); |
659 | ustatus &= ~0x00000002; |
660 | } |
661 | |
662 | if (ustatus && display) { |
663 | nv_error(priv, "TRAP_DISPATCH (unknown " |
664 | "0x%08x)\n" , ustatus); |
665 | } |
666 | |
667 | nv_wr32(priv, 0x400804, 0xc0000000); |
668 | nv_wr32(priv, 0x400108, 0x001); |
669 | status &= ~0x001; |
670 | if (!status) |
671 | return 0; |
672 | } |
673 | |
674 | /* M2MF: Memory to memory copy engine. */ |
675 | if (status & 0x002) { |
676 | u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff; |
677 | if (display) { |
678 | nv_error(priv, "TRAP_M2MF" ); |
679 | nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus); |
680 | pr_cont("\n" ); |
681 | nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n" , |
682 | nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808), |
683 | nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810)); |
684 | |
685 | } |
686 | |
687 | /* No sane way found yet -- just reset the bugger. */ |
688 | nv_wr32(priv, 0x400040, 2); |
689 | nv_wr32(priv, 0x400040, 0); |
690 | nv_wr32(priv, 0x406800, 0xc0000000); |
691 | nv_wr32(priv, 0x400108, 0x002); |
692 | status &= ~0x002; |
693 | } |
694 | |
695 | /* VFETCH: Fetches data from vertex buffers. */ |
696 | if (status & 0x004) { |
697 | u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff; |
698 | if (display) { |
699 | nv_error(priv, "TRAP_VFETCH" ); |
700 | nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus); |
701 | pr_cont("\n" ); |
702 | nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n" , |
703 | nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08), |
704 | nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10)); |
705 | } |
706 | |
707 | nv_wr32(priv, 0x400c04, 0xc0000000); |
708 | nv_wr32(priv, 0x400108, 0x004); |
709 | status &= ~0x004; |
710 | } |
711 | |
712 | /* STRMOUT: DirectX streamout / OpenGL transform feedback. */ |
713 | if (status & 0x008) { |
714 | ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff; |
715 | if (display) { |
716 | nv_error(priv, "TRAP_STRMOUT" ); |
717 | nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus); |
718 | pr_cont("\n" ); |
719 | nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n" , |
720 | nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808), |
721 | nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810)); |
722 | |
723 | } |
724 | |
725 | /* No sane way found yet -- just reset the bugger. */ |
726 | nv_wr32(priv, 0x400040, 0x80); |
727 | nv_wr32(priv, 0x400040, 0); |
728 | nv_wr32(priv, 0x401800, 0xc0000000); |
729 | nv_wr32(priv, 0x400108, 0x008); |
730 | status &= ~0x008; |
731 | } |
732 | |
733 | /* CCACHE: Handles code and c[] caches and fills them. */ |
734 | if (status & 0x010) { |
735 | ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff; |
736 | if (display) { |
737 | nv_error(priv, "TRAP_CCACHE" ); |
738 | nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus); |
739 | pr_cont("\n" ); |
740 | nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x" |
741 | " %08x %08x %08x\n" , |
742 | nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004), |
743 | nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c), |
744 | nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014), |
745 | nv_rd32(priv, 0x40501c)); |
746 | |
747 | } |
748 | |
749 | nv_wr32(priv, 0x405018, 0xc0000000); |
750 | nv_wr32(priv, 0x400108, 0x010); |
751 | status &= ~0x010; |
752 | } |
753 | |
754 | /* Unknown, not seen yet... 0x402000 is the only trap status reg |
755 | * remaining, so try to handle it anyway. Perhaps related to that |
756 | * unknown DMA slot on tesla? */ |
757 | if (status & 0x20) { |
758 | ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff; |
759 | if (display) |
760 | nv_error(priv, "TRAP_UNKC04 0x%08x\n" , ustatus); |
761 | nv_wr32(priv, 0x402000, 0xc0000000); |
762 | /* no status modifiction on purpose */ |
763 | } |
764 | |
765 | /* TEXTURE: CUDA texturing units */ |
766 | if (status & 0x040) { |
767 | nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display, |
768 | "TRAP_TEXTURE" ); |
769 | nv_wr32(priv, 0x400108, 0x040); |
770 | status &= ~0x040; |
771 | } |
772 | |
773 | /* MP: CUDA execution engines. */ |
774 | if (status & 0x080) { |
775 | nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display, |
776 | "TRAP_MP" ); |
777 | nv_wr32(priv, 0x400108, 0x080); |
778 | status &= ~0x080; |
779 | } |
780 | |
781 | /* PROP: Handles TP-initiated uncached memory accesses: |
782 | * l[], g[], stack, 2d surfaces, render targets. */ |
783 | if (status & 0x100) { |
784 | nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display, |
785 | "TRAP_PROP" ); |
786 | nv_wr32(priv, 0x400108, 0x100); |
787 | status &= ~0x100; |
788 | } |
789 | |
790 | if (status) { |
791 | if (display) |
792 | nv_error(priv, "TRAP: unknown 0x%08x\n" , status); |
793 | nv_wr32(priv, 0x400108, status); |
794 | } |
795 | |
796 | return 1; |
797 | } |
798 | |
799 | static void |
800 | nv50_graph_intr(struct nouveau_subdev *subdev) |
801 | { |
802 | struct nouveau_fifo *pfifo = nouveau_fifo(subdev); |
803 | struct nouveau_engine *engine = nv_engine(subdev); |
804 | struct nouveau_object *engctx; |
805 | struct nouveau_handle *handle = NULL; |
806 | struct nv50_graph_priv *priv = (void *)subdev; |
807 | u32 stat = nv_rd32(priv, 0x400100); |
808 | u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff; |
809 | u32 addr = nv_rd32(priv, 0x400704); |
810 | u32 subc = (addr & 0x00070000) >> 16; |
811 | u32 mthd = (addr & 0x00001ffc); |
812 | u32 data = nv_rd32(priv, 0x400708); |
813 | u32 class = nv_rd32(priv, 0x400814); |
814 | u32 show = stat, show_bitfield = stat; |
815 | int chid; |
816 | |
817 | engctx = nouveau_engctx_get(engine, inst); |
818 | chid = pfifo->chid(pfifo, engctx); |
819 | |
820 | if (stat & 0x00000010) { |
821 | handle = nouveau_handle_get_class(engctx, class); |
822 | if (handle && !nv_call(handle->object, mthd, data)) |
823 | show &= ~0x00000010; |
824 | nouveau_handle_put(handle); |
825 | } |
826 | |
827 | if (show & 0x00100000) { |
828 | u32 ecode = nv_rd32(priv, 0x400110); |
829 | nv_error(priv, "DATA_ERROR " ); |
830 | nouveau_enum_print(nv50_data_error_names, ecode); |
831 | pr_cont("\n" ); |
832 | show_bitfield &= ~0x00100000; |
833 | } |
834 | |
835 | if (stat & 0x00200000) { |
836 | if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12, |
837 | engctx)) |
838 | show &= ~0x00200000; |
839 | show_bitfield &= ~0x00200000; |
840 | } |
841 | |
842 | nv_wr32(priv, 0x400100, stat); |
843 | nv_wr32(priv, 0x400500, 0x00010001); |
844 | |
845 | if (show) { |
846 | show &= show_bitfield; |
847 | if (show) { |
848 | nv_error(priv, "%s" , "" ); |
849 | nouveau_bitfield_print(nv50_graph_intr_name, show); |
850 | pr_cont("\n" ); |
851 | } |
852 | nv_error(priv, |
853 | "ch %d [0x%010" PRIx64" %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n" , |
854 | chid, (u64)inst << 12, nouveau_client_name(engctx), |
855 | subc, class, mthd, data); |
856 | } |
857 | |
858 | if (nv_rd32(priv, 0x400824) & (1 << 31)) |
859 | nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31)); |
860 | |
861 | nouveau_engctx_put(engctx); |
862 | } |
863 | |
864 | static int |
865 | nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
866 | struct nouveau_oclass *oclass, void *data, u32 size, |
867 | struct nouveau_object **pobject) |
868 | { |
869 | struct nv50_graph_priv *priv; |
870 | int ret; |
871 | |
872 | ret = nouveau_graph_create(parent, engine, oclass, true, &priv); |
873 | *pobject = nv_object(priv); |
874 | if (ret) |
875 | return ret; |
876 | |
877 | nv_subdev(priv)->unit = 0x00201000; |
878 | nv_subdev(priv)->intr = nv50_graph_intr; |
879 | nv_engine(priv)->cclass = &nv50_graph_cclass; |
880 | |
881 | priv->base.units = nv50_graph_units; |
882 | |
883 | switch (nv_device(priv)->chipset) { |
884 | case 0x50: |
885 | nv_engine(priv)->sclass = nv50_graph_sclass; |
886 | break; |
887 | case 0x84: |
888 | case 0x86: |
889 | case 0x92: |
890 | case 0x94: |
891 | case 0x96: |
892 | case 0x98: |
893 | nv_engine(priv)->sclass = nv84_graph_sclass; |
894 | break; |
895 | case 0xa0: |
896 | case 0xaa: |
897 | case 0xac: |
898 | nv_engine(priv)->sclass = nva0_graph_sclass; |
899 | break; |
900 | case 0xa3: |
901 | case 0xa5: |
902 | case 0xa8: |
903 | nv_engine(priv)->sclass = nva3_graph_sclass; |
904 | break; |
905 | case 0xaf: |
906 | nv_engine(priv)->sclass = nvaf_graph_sclass; |
907 | break; |
908 | |
909 | }; |
910 | |
911 | /* unfortunate hw bug workaround... */ |
912 | if (nv_device(priv)->chipset != 0x50 && |
913 | nv_device(priv)->chipset != 0xac) |
914 | nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush; |
915 | |
916 | spin_lock_init(&priv->lock); |
917 | return 0; |
918 | } |
919 | |
920 | static int |
921 | nv50_graph_init(struct nouveau_object *object) |
922 | { |
923 | struct nv50_graph_priv *priv = (void *)object; |
924 | int ret, units, i; |
925 | |
926 | ret = nouveau_graph_init(&priv->base); |
927 | if (ret) |
928 | return ret; |
929 | |
930 | /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */ |
931 | nv_wr32(priv, 0x40008c, 0x00000004); |
932 | |
933 | /* reset/enable traps and interrupts */ |
934 | nv_wr32(priv, 0x400804, 0xc0000000); |
935 | nv_wr32(priv, 0x406800, 0xc0000000); |
936 | nv_wr32(priv, 0x400c04, 0xc0000000); |
937 | nv_wr32(priv, 0x401800, 0xc0000000); |
938 | nv_wr32(priv, 0x405018, 0xc0000000); |
939 | nv_wr32(priv, 0x402000, 0xc0000000); |
940 | |
941 | units = nv_rd32(priv, 0x001540); |
942 | for (i = 0; i < 16; i++) { |
943 | if (!(units & (1 << i))) |
944 | continue; |
945 | |
946 | if (nv_device(priv)->chipset < 0xa0) { |
947 | nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000); |
948 | nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000); |
949 | nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000); |
950 | } else { |
951 | nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000); |
952 | nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000); |
953 | nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000); |
954 | } |
955 | } |
956 | |
957 | nv_wr32(priv, 0x400108, 0xffffffff); |
958 | nv_wr32(priv, 0x400138, 0xffffffff); |
959 | nv_wr32(priv, 0x400100, 0xffffffff); |
960 | nv_wr32(priv, 0x40013c, 0xffffffff); |
961 | nv_wr32(priv, 0x400500, 0x00010001); |
962 | |
963 | /* upload context program, initialise ctxctl defaults */ |
964 | ret = nv50_grctx_init(nv_device(priv), &priv->size); |
965 | if (ret) |
966 | return ret; |
967 | |
968 | nv_wr32(priv, 0x400824, 0x00000000); |
969 | nv_wr32(priv, 0x400828, 0x00000000); |
970 | nv_wr32(priv, 0x40082c, 0x00000000); |
971 | nv_wr32(priv, 0x400830, 0x00000000); |
972 | nv_wr32(priv, 0x40032c, 0x00000000); |
973 | nv_wr32(priv, 0x400330, 0x00000000); |
974 | |
975 | /* some unknown zcull magic */ |
976 | switch (nv_device(priv)->chipset & 0xf0) { |
977 | case 0x50: |
978 | case 0x80: |
979 | case 0x90: |
980 | nv_wr32(priv, 0x402ca8, 0x00000800); |
981 | break; |
982 | case 0xa0: |
983 | default: |
984 | nv_wr32(priv, 0x402cc0, 0x00000000); |
985 | if (nv_device(priv)->chipset == 0xa0 || |
986 | nv_device(priv)->chipset == 0xaa || |
987 | nv_device(priv)->chipset == 0xac) { |
988 | nv_wr32(priv, 0x402ca8, 0x00000802); |
989 | } else { |
990 | nv_wr32(priv, 0x402cc0, 0x00000000); |
991 | nv_wr32(priv, 0x402ca8, 0x00000002); |
992 | } |
993 | |
994 | break; |
995 | } |
996 | |
997 | /* zero out zcull regions */ |
998 | for (i = 0; i < 8; i++) { |
999 | nv_wr32(priv, 0x402c20 + (i * 8), 0x00000000); |
1000 | nv_wr32(priv, 0x402c24 + (i * 8), 0x00000000); |
1001 | nv_wr32(priv, 0x402c28 + (i * 8), 0x00000000); |
1002 | nv_wr32(priv, 0x402c2c + (i * 8), 0x00000000); |
1003 | } |
1004 | return 0; |
1005 | } |
1006 | |
1007 | struct nouveau_oclass |
1008 | nv50_graph_oclass = { |
1009 | .handle = NV_ENGINE(GR, 0x50), |
1010 | .ofuncs = &(struct nouveau_ofuncs) { |
1011 | .ctor = nv50_graph_ctor, |
1012 | .dtor = _nouveau_graph_dtor, |
1013 | .init = nv50_graph_init, |
1014 | .fini = _nouveau_graph_fini, |
1015 | }, |
1016 | }; |
1017 | |