1 | /* $NetBSD: am79c930reg.h,v 1.7 2008/04/28 20:23:49 martin Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 1999 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Bill Sommerfeld |
9 | * |
10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions |
12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. |
15 | * 2. Redistributions in binary form must reproduce the above copyright |
16 | * notice, this list of conditions and the following disclaimer in the |
17 | * documentation and/or other materials provided with the distribution. |
18 | * |
19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
29 | * POSSIBILITY OF SUCH DAMAGE. |
30 | */ |
31 | |
32 | /* |
33 | * Device register definitions gleaned from from the AMD "Am79C930 |
34 | * PCnet(tm)-Mobile Single Chip Wireless LAN Media Access Controller" |
35 | * data sheet, AMD Pub #20183, Rev B, amendment/0, issue date August 1997. |
36 | * |
37 | * As of 1999/10/23, this was available from AMD's web site in PDF |
38 | * form. |
39 | */ |
40 | |
41 | |
42 | /* |
43 | * The 79c930 contains a bus interface unit, a media access |
44 | * controller, and a tranceiver attachment interface. |
45 | * The MAC contains an 80188 CPU core. |
46 | * typical devices built around this chip typically add 32k or 64k of |
47 | * memory for buffers. |
48 | * |
49 | * The 80188 runs firmware which handles most of the 802.11 gorp, and |
50 | * communicates with the host using shared data structures in this |
51 | * memory; the specifics of the shared memory layout are not covered |
52 | * in this source file; see <dev/ic/am80211fw.h> for details of that layer. |
53 | */ |
54 | |
55 | /* |
56 | * Device Registers |
57 | */ |
58 | |
59 | #define AM79C930_IO_BASE 0 |
60 | #define AM79C930_IO_SIZE 16 |
61 | #define AM79C930_IO_SIZE_BIG 40 |
62 | #define AM79C930_IO_ALIGN 0x40 /* am79c930 decodes lower 6bits */ |
63 | |
64 | |
65 | #define AM79C930_GCR 0 /* General Config Register */ |
66 | |
67 | #define AM79C930_GCR_SWRESET 0x80 /* software reset */ |
68 | #define AM79C930_GCR_CORESET 0x40 /* core reset */ |
69 | #define AM79C930_GCR_DISPWDN 0x20 /* disable powerdown */ |
70 | #define AM79C930_GCR_ECWAIT 0x10 /* embedded controller wait */ |
71 | #define AM79C930_GCR_ECINT 0x08 /* interrupt from embedded ctrlr */ |
72 | #define AM79C930_GCR_INT2EC 0x04 /* interrupt to embedded ctrlr */ |
73 | #define AM79C930_GCR_ENECINT 0x02 /* enable interrupts from e.c. */ |
74 | #define AM79C930_GCR_DAM 0x01 /* direct access mode (read only) */ |
75 | |
76 | #define AM79C930_GCR_BITS "\020\1DAM\2ENECINT\3INT2EC\4ECINT\5ECWAIT\6DISPWDN\7CORESET\010SWRESET" |
77 | |
78 | #define AM79C930_BSS 1 /* Bank Switching Select register */ |
79 | |
80 | #define AM79C930_BSS_ECATR 0x80 /* E.C. ALE test read */ |
81 | #define AM79C930_BSS_FS 0x20 /* Flash Select */ |
82 | #define AM79C930_BSS_MBS 0x18 /* Memory Bank Select */ |
83 | #define AM79C930_BSS_EIOW 0x04 /* Expand I/O Window */ |
84 | #define AM79C930_BSS_TBS 0x03 /* TAI Bank Select */ |
85 | |
86 | #define AM79C930_LMA_LO 2 /* Local Memory Address register (low byte) */ |
87 | |
88 | #define AM79C930_LMA_HI 3 /* Local Memory Address register (high byte) */ |
89 | |
90 | /* set this bit to turn off ISAPnP version */ |
91 | #define AM79C930_LMA_HI_ISAPWRDWN 0x80 |
92 | |
93 | /* |
94 | * mmm, inconsistency in chip documentation: |
95 | * According to page 79--80, all four of the following are equivalent |
96 | * and address the single byte pointed at by BSS_{FS,MBS} | LMA_{HI,LO} |
97 | * According to tables on p63 and p67, they're the LSB through MSB |
98 | * of a 32-bit word. |
99 | */ |
100 | |
101 | #define AM79C930_IODPA 4 /* I/O Data port A */ |
102 | #define AM79C930_IODPB 5 /* I/O Data port B */ |
103 | #define AM79C930_IODPC 6 /* I/O Data port C */ |
104 | #define AM79C930_IODPD 7 /* I/O Data port D */ |
105 | |
106 | |
107 | /* |
108 | * Tranceiver Attachment Interface Registers (TIR space) |
109 | * (omitted for now, since host access to them is for diagnostic |
110 | * purposes only). |
111 | */ |
112 | |
113 | /* |
114 | * memory space goo. |
115 | */ |
116 | |
117 | #define AM79C930_MEM_SIZE 0x8000 /* 32k */ |
118 | #define AM79C930_MEM_BASE 0x0 /* starting at 0 */ |
119 | |