1 | /* $NetBSD: if_bgevar.h,v 1.21 2015/11/18 10:26:57 msaitoh Exp $ */ |
2 | /* |
3 | * Copyright (c) 2001 Wind River Systems |
4 | * Copyright (c) 1997, 1998, 1999, 2001 |
5 | * Bill Paul <wpaul@windriver.com>. All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * 3. All advertising materials mentioning features or use of this software |
16 | * must display the following acknowledgement: |
17 | * This product includes software developed by Bill Paul. |
18 | * 4. Neither the name of the author nor the names of any co-contributors |
19 | * may be used to endorse or promote products derived from this software |
20 | * without specific prior written permission. |
21 | * |
22 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
23 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
25 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
26 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
29 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
30 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
31 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
32 | * THE POSSIBILITY OF SUCH DAMAGE. |
33 | * |
34 | * $FreeBSD: if_bgereg.h,v 1.1.2.7 2002/11/02 18:17:55 mp Exp $ |
35 | */ |
36 | |
37 | /* |
38 | * BCM570x memory map. The internal memory layout varies somewhat |
39 | * depending on whether or not we have external SSRAM attached. |
40 | * The BCM5700 can have up to 16MB of external memory. The BCM5701 |
41 | * is apparently not designed to use external SSRAM. The mappings |
42 | * up to the first 4 send rings are the same for both internal and |
43 | * external memory configurations. Note that mini RX ring space is |
44 | * only available with external SSRAM configurations, which means |
45 | * the mini RX ring is not supported on the BCM5701. |
46 | * |
47 | * The NIC's memory can be accessed by the host in one of 3 ways: |
48 | * |
49 | * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA |
50 | * registers in PCI config space can be used to read any 32-bit |
51 | * address within the NIC's memory. |
52 | * |
53 | * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config |
54 | * space can be used in conjunction with the memory window in the |
55 | * device register space at offset 0x8000 to read any 32K chunk |
56 | * of NIC memory. |
57 | * |
58 | * 3) Flat mode. If the 'flat mode' bit in the PCI state register is |
59 | * set, the device I/O mapping consumes 32MB of host address space, |
60 | * allowing all of the registers and internal NIC memory to be |
61 | * accessed directly. NIC memory addresses are offset by 0x01000000. |
62 | * Flat mode consumes so much host address space that it is not |
63 | * recommended. |
64 | */ |
65 | |
66 | #ifndef _DEV_PCI_IF_BGEVAR_H_ |
67 | #define _DEV_PCI_IF_BGEVAR_H_ |
68 | |
69 | #include <sys/bus.h> |
70 | #include <sys/rndsource.h> |
71 | #include <net/if_ether.h> |
72 | #include <dev/pci/pcivar.h> |
73 | |
74 | #define BGE_HOSTADDR(x, y) \ |
75 | do { \ |
76 | (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ |
77 | if (sizeof (bus_addr_t) == 8) \ |
78 | (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ |
79 | else \ |
80 | (x).bge_addr_hi = 0; \ |
81 | } while(0) |
82 | |
83 | #define RCB_WRITE_4(sc, rcb, offset, val) \ |
84 | bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ |
85 | rcb + offsetof(struct bge_rcb, offset), val) |
86 | |
87 | /* |
88 | * Other utility macros. |
89 | */ |
90 | #define BGE_INC(x, y) (x) = (x + 1) % y |
91 | |
92 | /* |
93 | * Register access macros. The Tigon always uses memory mapped register |
94 | * accesses and all registers must be accessed with 32 bit operations. |
95 | */ |
96 | |
97 | #define CSR_WRITE_4(sc, reg, val) \ |
98 | bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) |
99 | |
100 | #define CSR_READ_4(sc, reg) \ |
101 | bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) |
102 | |
103 | #define CSR_WRITE_4_FLUSH(sc, reg, val) \ |
104 | do { \ |
105 | CSR_WRITE_4(sc, reg, val); \ |
106 | CSR_READ_4(sc, reg); \ |
107 | } while(0) |
108 | |
109 | #define BGE_SETBIT(sc, reg, x) \ |
110 | CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) |
111 | #define BGE_SETBIT_FLUSH(sc, reg, x) \ |
112 | do { \ |
113 | BGE_SETBIT(sc, reg, x); \ |
114 | CSR_READ_4(sc, reg); \ |
115 | } while(0) |
116 | #define BGE_CLRBIT(sc, reg, x) \ |
117 | CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) |
118 | #define BGE_CLRBIT_FLUSH(sc, reg, x) \ |
119 | do { \ |
120 | BGE_CLRBIT(sc, reg, x); \ |
121 | CSR_READ_4(sc, reg); \ |
122 | } while(0) |
123 | |
124 | /* BAR2 APE register access macros. */ |
125 | #define APE_WRITE_4(sc, reg, val) \ |
126 | bus_space_write_4(sc->bge_apetag, sc->bge_apehandle, reg, val) |
127 | |
128 | #define APE_READ_4(sc, reg) \ |
129 | bus_space_read_4(sc->bge_apetag, sc->bge_apehandle, reg) |
130 | |
131 | #define APE_WRITE_4_FLUSH(sc, reg, val) \ |
132 | do { \ |
133 | APE_WRITE_4(sc, reg, val); \ |
134 | APE_READ_4(sc, reg); \ |
135 | } while(0) |
136 | |
137 | #define APE_SETBIT(sc, reg, x) \ |
138 | APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x))) |
139 | #define APE_CLRBIT(sc, reg, x) \ |
140 | APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x))) |
141 | |
142 | #define PCI_SETBIT(pc, tag, reg, x) \ |
143 | pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) |
144 | #define PCI_CLRBIT(pc, tag, reg, x) \ |
145 | pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) |
146 | |
147 | /* |
148 | * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS |
149 | * values are tuneable. They control the actual amount of buffers |
150 | * allocated for the standard, mini and jumbo receive rings. |
151 | */ |
152 | |
153 | #define BGE_SSLOTS 256 |
154 | #define BGE_MSLOTS 256 |
155 | #define BGE_JSLOTS 384 |
156 | |
157 | #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) |
158 | #define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \ |
159 | (BGE_JRAWLEN % sizeof(uint64_t)))) |
160 | #define BGE_JPAGESZ PAGE_SIZE |
161 | #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) |
162 | #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) |
163 | |
164 | /* |
165 | * Ring structures. Most of these reside in host memory and we tell |
166 | * the NIC where they are via the ring control blocks. The exceptions |
167 | * are the tx and command rings, which live in NIC memory and which |
168 | * we access via the shared memory window. |
169 | */ |
170 | struct bge_ring_data { |
171 | struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; |
172 | struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; |
173 | struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; |
174 | struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; |
175 | struct bge_status_block bge_status_block; |
176 | struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ |
177 | struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ |
178 | struct bge_gib bge_info; |
179 | }; |
180 | |
181 | #define BGE_RING_DMA_ADDR(sc, offset) \ |
182 | ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ |
183 | offsetof(struct bge_ring_data, offset)) |
184 | |
185 | /* |
186 | * Number of DMA segments in a TxCB. Note that this is carefully |
187 | * chosen to make the total struct size an even power of two. It's |
188 | * critical that no TxCB be split across a page boundary since |
189 | * no attempt is made to allocate physically contiguous memory. |
190 | * |
191 | */ |
192 | #if 0 /* pre-TSO values */ |
193 | #define BGE_TXDMA_MAX ETHER_MAX_LEN_JUMBO |
194 | #ifdef _LP64 |
195 | #define BGE_NTXSEG 30 |
196 | #else |
197 | #define BGE_NTXSEG 31 |
198 | #endif |
199 | #else /* TSO values */ |
200 | #define BGE_TXDMA_MAX (round_page(IP_MAXPACKET)) /* for TSO */ |
201 | #ifdef _LP64 |
202 | #define BGE_NTXSEG 120 /* XXX just a guess */ |
203 | #else |
204 | #define BGE_NTXSEG 124 /* XXX just a guess */ |
205 | #endif |
206 | #endif /* TSO values */ |
207 | |
208 | #define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) |
209 | |
210 | /* |
211 | * Mbuf pointers. We need these to keep track of the virtual addresses |
212 | * of our mbuf chains since we can only convert from physical to virtual, |
213 | * not the other way around. |
214 | */ |
215 | struct bge_chain_data { |
216 | struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; |
217 | struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; |
218 | struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; |
219 | struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; |
220 | bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; |
221 | bus_dmamap_t bge_rx_jumbo_map; |
222 | /* Stick the jumbo mem management stuff here too. */ |
223 | void * bge_jslots[BGE_JSLOTS]; |
224 | void * bge_jumbo_buf; |
225 | }; |
226 | |
227 | #define BGE_JUMBO_DMA_ADDR(sc, m) \ |
228 | ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ |
229 | (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) |
230 | |
231 | struct bge_type { |
232 | uint16_t bge_vid; |
233 | uint16_t bge_did; |
234 | char *bge_name; |
235 | }; |
236 | |
237 | #define BGE_TIMEOUT 100000 |
238 | #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ |
239 | |
240 | struct bge_jpool_entry { |
241 | int slot; |
242 | SLIST_ENTRY(bge_jpool_entry) jpool_entries; |
243 | }; |
244 | |
245 | struct bge_bcom_hack { |
246 | int reg; |
247 | int val; |
248 | }; |
249 | |
250 | struct txdmamap_pool_entry { |
251 | bus_dmamap_t dmamap; |
252 | SLIST_ENTRY(txdmamap_pool_entry) link; |
253 | }; |
254 | |
255 | #define ASF_ENABLE 1 |
256 | #define ASF_NEW_HANDSHAKE 2 |
257 | #define ASF_STACKUP 4 |
258 | |
259 | struct bge_softc { |
260 | device_t bge_dev; |
261 | struct ethercom ethercom; /* interface info */ |
262 | bus_space_handle_t bge_bhandle; |
263 | bus_space_tag_t bge_btag; |
264 | bus_size_t bge_bsize; |
265 | bus_space_handle_t bge_apehandle; |
266 | bus_space_tag_t bge_apetag; |
267 | bus_size_t bge_apesize; |
268 | void *bge_intrhand; |
269 | pci_intr_handle_t *bge_pihp; |
270 | pci_chipset_tag_t sc_pc; |
271 | pcitag_t sc_pcitag; |
272 | |
273 | struct pci_attach_args bge_pa; |
274 | struct mii_data bge_mii; |
275 | struct ifmedia bge_ifmedia; /* media info */ |
276 | uint32_t bge_return_ring_cnt; |
277 | uint32_t bge_tx_prodidx; |
278 | bus_dma_tag_t bge_dmatag; |
279 | uint32_t bge_pcixcap; |
280 | uint32_t bge_pciecap; |
281 | uint32_t bge_msicap; |
282 | uint16_t bge_mps; |
283 | int bge_expmrq; |
284 | uint32_t bge_lasttag; |
285 | u_int32_t bge_mfw_flags; /* Management F/W flags */ |
286 | #define BGE_MFW_ON_RXCPU 0x00000001 |
287 | #define BGE_MFW_ON_APE 0x00000002 |
288 | #define BGE_MFW_TYPE_NCSI 0x00000004 |
289 | #define BGE_MFW_TYPE_DASH 0x00000008 |
290 | int bge_phy_ape_lock; |
291 | int bge_phy_addr; |
292 | uint32_t bge_chipid; |
293 | uint8_t bge_asf_mode; |
294 | uint8_t bge_asf_count; |
295 | struct bge_ring_data *bge_rdata; /* rings */ |
296 | struct bge_chain_data bge_cdata; /* mbufs */ |
297 | bus_dmamap_t bge_ring_map; |
298 | bus_dma_segment_t bge_ring_seg; |
299 | int bge_ring_rseg; |
300 | uint16_t bge_tx_saved_considx; |
301 | uint16_t bge_rx_saved_considx; |
302 | uint16_t bge_ev_saved_considx; |
303 | uint16_t bge_std; /* current std ring head */ |
304 | uint16_t bge_jumbo; /* current jumo ring head */ |
305 | SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; |
306 | SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; |
307 | uint32_t bge_stat_ticks; |
308 | uint32_t bge_rx_coal_ticks; |
309 | uint32_t bge_tx_coal_ticks; |
310 | uint32_t bge_rx_max_coal_bds; |
311 | uint32_t bge_tx_max_coal_bds; |
312 | uint32_t bge_tx_buf_ratio; |
313 | uint32_t bge_sts; |
314 | #define BGE_STS_LINK 0x00000001 /* MAC link status */ |
315 | #define BGE_STS_LINK_EVT 0x00000002 /* pending link event */ |
316 | #define BGE_STS_AUTOPOLL 0x00000004 /* PHY auto-polling */ |
317 | #define BGE_STS_BIT(sc, x) ((sc)->bge_sts & (x)) |
318 | #define BGE_STS_SETBIT(sc, x) ((sc)->bge_sts |= (x)) |
319 | #define BGE_STS_CLRBIT(sc, x) ((sc)->bge_sts &= ~(x)) |
320 | int bge_if_flags; |
321 | uint32_t bge_flags; |
322 | uint32_t bge_phy_flags; |
323 | int bge_flowflags; |
324 | #ifdef BGE_EVENT_COUNTERS |
325 | /* |
326 | * Event counters. |
327 | */ |
328 | struct evcnt bge_ev_intr; /* interrupts */ |
329 | struct evcnt bge_ev_tx_xoff; /* send PAUSE(len>0) packets */ |
330 | struct evcnt bge_ev_tx_xon; /* send PAUSE(len=0) packets */ |
331 | struct evcnt bge_ev_rx_xoff; /* receive PAUSE(len>0) packets */ |
332 | struct evcnt bge_ev_rx_xon; /* receive PAUSE(len=0) packets */ |
333 | struct evcnt bge_ev_rx_macctl; /* receive MAC control packets */ |
334 | struct evcnt bge_ev_xoffentered;/* XOFF state entered */ |
335 | #endif /* BGE_EVENT_COUNTERS */ |
336 | int bge_txcnt; |
337 | struct callout bge_timeout; |
338 | int bge_pending_rxintr_change; |
339 | int bge_detaching; |
340 | SLIST_HEAD(, txdmamap_pool_entry) txdma_list; |
341 | struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; |
342 | |
343 | struct sysctllog *bge_log; |
344 | |
345 | krndsource_t rnd_source; /* random source */ |
346 | }; |
347 | |
348 | #endif /* _DEV_PCI_IF_BGEVAR_H_ */ |
349 | |