1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 | * DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: |
24 | * Eric Anholt <eric@anholt.net> |
25 | */ |
26 | |
27 | #include <linux/dmi.h> |
28 | #include <linux/i2c.h> |
29 | #include <linux/slab.h> |
30 | #include <drm/drmP.h> |
31 | #include <drm/drm_crtc.h> |
32 | #include <drm/drm_crtc_helper.h> |
33 | #include <drm/drm_edid.h> |
34 | #include "intel_drv.h" |
35 | #include <drm/i915_drm.h> |
36 | #include "i915_drv.h" |
37 | |
38 | /* Here's the desired hotplug mode */ |
39 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ |
40 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ |
41 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ |
42 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ |
43 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ |
44 | ADPA_CRT_HOTPLUG_ENABLE) |
45 | |
46 | struct intel_crt { |
47 | struct intel_encoder base; |
48 | /* DPMS state is stored in the connector, which we need in the |
49 | * encoder's enable/disable callbacks */ |
50 | struct intel_connector *connector; |
51 | bool force_hotplug_required; |
52 | u32 adpa_reg; |
53 | }; |
54 | |
55 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
56 | { |
57 | return container_of(encoder, struct intel_crt, base); |
58 | } |
59 | |
60 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
61 | { |
62 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
63 | } |
64 | |
65 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
66 | enum i915_pipe *pipe) |
67 | { |
68 | struct drm_device *dev = encoder->base.dev; |
69 | struct drm_i915_private *dev_priv = dev->dev_private; |
70 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
71 | enum intel_display_power_domain power_domain; |
72 | u32 tmp; |
73 | |
74 | power_domain = intel_display_port_power_domain(encoder); |
75 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
76 | return false; |
77 | |
78 | tmp = I915_READ(crt->adpa_reg); |
79 | |
80 | if (!(tmp & ADPA_DAC_ENABLE)) |
81 | return false; |
82 | |
83 | if (HAS_PCH_CPT(dev)) |
84 | *pipe = PORT_TO_PIPE_CPT(tmp); |
85 | else |
86 | *pipe = PORT_TO_PIPE(tmp); |
87 | |
88 | return true; |
89 | } |
90 | |
91 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
92 | { |
93 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
94 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
95 | u32 tmp, flags = 0; |
96 | |
97 | tmp = I915_READ(crt->adpa_reg); |
98 | |
99 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) |
100 | flags |= DRM_MODE_FLAG_PHSYNC; |
101 | else |
102 | flags |= DRM_MODE_FLAG_NHSYNC; |
103 | |
104 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) |
105 | flags |= DRM_MODE_FLAG_PVSYNC; |
106 | else |
107 | flags |= DRM_MODE_FLAG_NVSYNC; |
108 | |
109 | return flags; |
110 | } |
111 | |
112 | static void intel_crt_get_config(struct intel_encoder *encoder, |
113 | struct intel_crtc_config *pipe_config) |
114 | { |
115 | struct drm_device *dev = encoder->base.dev; |
116 | int dotclock; |
117 | |
118 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); |
119 | |
120 | dotclock = pipe_config->port_clock; |
121 | |
122 | if (HAS_PCH_SPLIT(dev)) |
123 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
124 | |
125 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
126 | } |
127 | |
128 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
129 | struct intel_crtc_config *pipe_config) |
130 | { |
131 | intel_ddi_get_config(encoder, pipe_config); |
132 | |
133 | pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
134 | DRM_MODE_FLAG_NHSYNC | |
135 | DRM_MODE_FLAG_PVSYNC | |
136 | DRM_MODE_FLAG_NVSYNC); |
137 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); |
138 | } |
139 | |
140 | /* Note: The caller is required to filter out dpms modes not supported by the |
141 | * platform. */ |
142 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
143 | { |
144 | struct drm_device *dev = encoder->base.dev; |
145 | struct drm_i915_private *dev_priv = dev->dev_private; |
146 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
147 | u32 temp; |
148 | |
149 | temp = I915_READ(crt->adpa_reg); |
150 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
151 | temp &= ~ADPA_DAC_ENABLE; |
152 | |
153 | switch (mode) { |
154 | case DRM_MODE_DPMS_ON: |
155 | temp |= ADPA_DAC_ENABLE; |
156 | break; |
157 | case DRM_MODE_DPMS_STANDBY: |
158 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
159 | break; |
160 | case DRM_MODE_DPMS_SUSPEND: |
161 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
162 | break; |
163 | case DRM_MODE_DPMS_OFF: |
164 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
165 | break; |
166 | } |
167 | |
168 | I915_WRITE(crt->adpa_reg, temp); |
169 | } |
170 | |
171 | static void intel_disable_crt(struct intel_encoder *encoder) |
172 | { |
173 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); |
174 | } |
175 | |
176 | static void intel_enable_crt(struct intel_encoder *encoder) |
177 | { |
178 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
179 | |
180 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); |
181 | } |
182 | |
183 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
184 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
185 | { |
186 | struct drm_device *dev = connector->dev; |
187 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
188 | struct drm_crtc *crtc; |
189 | int old_dpms; |
190 | |
191 | /* PCH platforms and VLV only support on/off. */ |
192 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
193 | mode = DRM_MODE_DPMS_OFF; |
194 | |
195 | if (mode == connector->dpms) |
196 | return; |
197 | |
198 | old_dpms = connector->dpms; |
199 | connector->dpms = mode; |
200 | |
201 | /* Only need to change hw state when actually enabled */ |
202 | crtc = encoder->base.crtc; |
203 | if (!crtc) { |
204 | encoder->connectors_active = false; |
205 | return; |
206 | } |
207 | |
208 | /* We need the pipe to run for anything but OFF. */ |
209 | if (mode == DRM_MODE_DPMS_OFF) |
210 | encoder->connectors_active = false; |
211 | else |
212 | encoder->connectors_active = true; |
213 | |
214 | /* We call connector dpms manually below in case pipe dpms doesn't |
215 | * change due to cloning. */ |
216 | if (mode < old_dpms) { |
217 | /* From off to on, enable the pipe first. */ |
218 | intel_crtc_update_dpms(crtc); |
219 | |
220 | intel_crt_set_dpms(encoder, mode); |
221 | } else { |
222 | intel_crt_set_dpms(encoder, mode); |
223 | |
224 | intel_crtc_update_dpms(crtc); |
225 | } |
226 | |
227 | intel_modeset_check_state(connector->dev); |
228 | } |
229 | |
230 | static enum drm_mode_status |
231 | intel_crt_mode_valid(struct drm_connector *connector, |
232 | struct drm_display_mode *mode) |
233 | { |
234 | struct drm_device *dev = connector->dev; |
235 | |
236 | int max_clock = 0; |
237 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
238 | return MODE_NO_DBLESCAN; |
239 | |
240 | if (mode->clock < 25000) |
241 | return MODE_CLOCK_LOW; |
242 | |
243 | if (IS_GEN2(dev)) |
244 | max_clock = 350000; |
245 | else |
246 | max_clock = 400000; |
247 | if (mode->clock > max_clock) |
248 | return MODE_CLOCK_HIGH; |
249 | |
250 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
251 | if (HAS_PCH_LPT(dev) && |
252 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
253 | return MODE_CLOCK_HIGH; |
254 | |
255 | return MODE_OK; |
256 | } |
257 | |
258 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
259 | struct intel_crtc_config *pipe_config) |
260 | { |
261 | struct drm_device *dev = encoder->base.dev; |
262 | |
263 | if (HAS_PCH_SPLIT(dev)) |
264 | pipe_config->has_pch_encoder = true; |
265 | |
266 | /* LPT FDI RX only supports 8bpc. */ |
267 | if (HAS_PCH_LPT(dev)) |
268 | pipe_config->pipe_bpp = 24; |
269 | |
270 | /* FDI must always be 2.7 GHz */ |
271 | if (HAS_DDI(dev)) |
272 | pipe_config->port_clock = 135000 * 2; |
273 | |
274 | return true; |
275 | } |
276 | |
277 | static void intel_crt_mode_set(struct intel_encoder *encoder) |
278 | { |
279 | |
280 | struct drm_device *dev = encoder->base.dev; |
281 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
282 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
283 | struct drm_i915_private *dev_priv = dev->dev_private; |
284 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
285 | u32 adpa; |
286 | |
287 | if (INTEL_INFO(dev)->gen >= 5) |
288 | adpa = ADPA_HOTPLUG_BITS; |
289 | else |
290 | adpa = 0; |
291 | |
292 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
293 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
294 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
295 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
296 | |
297 | /* For CPT allow 3 pipe config, for others just use A or B */ |
298 | if (HAS_PCH_LPT(dev)) |
299 | ; /* Those bits don't exist here */ |
300 | else if (HAS_PCH_CPT(dev)) |
301 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); |
302 | else if (crtc->pipe == 0) |
303 | adpa |= ADPA_PIPE_A_SELECT; |
304 | else |
305 | adpa |= ADPA_PIPE_B_SELECT; |
306 | |
307 | if (!HAS_PCH_SPLIT(dev)) |
308 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
309 | |
310 | I915_WRITE(crt->adpa_reg, adpa); |
311 | } |
312 | |
313 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
314 | { |
315 | struct drm_device *dev = connector->dev; |
316 | struct intel_crt *crt = intel_attached_crt(connector); |
317 | struct drm_i915_private *dev_priv = dev->dev_private; |
318 | u32 adpa; |
319 | bool ret; |
320 | |
321 | /* The first time through, trigger an explicit detection cycle */ |
322 | if (crt->force_hotplug_required) { |
323 | bool turn_off_dac = HAS_PCH_SPLIT(dev); |
324 | u32 save_adpa; |
325 | |
326 | crt->force_hotplug_required = 0; |
327 | |
328 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
329 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n" , adpa); |
330 | |
331 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
332 | if (turn_off_dac) |
333 | adpa &= ~ADPA_DAC_ENABLE; |
334 | |
335 | I915_WRITE(crt->adpa_reg, adpa); |
336 | |
337 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
338 | 1000)) |
339 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER" ); |
340 | |
341 | if (turn_off_dac) { |
342 | I915_WRITE(crt->adpa_reg, save_adpa); |
343 | POSTING_READ(crt->adpa_reg); |
344 | } |
345 | } |
346 | |
347 | /* Check the status to see if both blue and green are on now */ |
348 | adpa = I915_READ(crt->adpa_reg); |
349 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
350 | ret = true; |
351 | else |
352 | ret = false; |
353 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n" , adpa, ret); |
354 | |
355 | return ret; |
356 | } |
357 | |
358 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
359 | { |
360 | struct drm_device *dev = connector->dev; |
361 | struct intel_crt *crt = intel_attached_crt(connector); |
362 | struct drm_i915_private *dev_priv = dev->dev_private; |
363 | u32 adpa; |
364 | bool ret; |
365 | u32 save_adpa; |
366 | |
367 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
368 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n" , adpa); |
369 | |
370 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
371 | |
372 | I915_WRITE(crt->adpa_reg, adpa); |
373 | |
374 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
375 | 1000)) { |
376 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER" ); |
377 | I915_WRITE(crt->adpa_reg, save_adpa); |
378 | } |
379 | |
380 | /* Check the status to see if both blue and green are on now */ |
381 | adpa = I915_READ(crt->adpa_reg); |
382 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
383 | ret = true; |
384 | else |
385 | ret = false; |
386 | |
387 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n" , adpa, ret); |
388 | |
389 | return ret; |
390 | } |
391 | |
392 | /** |
393 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. |
394 | * |
395 | * Not for i915G/i915GM |
396 | * |
397 | * \return true if CRT is connected. |
398 | * \return false if CRT is disconnected. |
399 | */ |
400 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
401 | { |
402 | struct drm_device *dev = connector->dev; |
403 | struct drm_i915_private *dev_priv = dev->dev_private; |
404 | u32 hotplug_en, orig, stat; |
405 | bool ret = false; |
406 | int i, tries = 0; |
407 | |
408 | if (HAS_PCH_SPLIT(dev)) |
409 | return intel_ironlake_crt_detect_hotplug(connector); |
410 | |
411 | if (IS_VALLEYVIEW(dev)) |
412 | return valleyview_crt_detect_hotplug(connector); |
413 | |
414 | /* |
415 | * On 4 series desktop, CRT detect sequence need to be done twice |
416 | * to get a reliable result. |
417 | */ |
418 | |
419 | if (IS_G4X(dev) && !IS_GM45(dev)) |
420 | tries = 2; |
421 | else |
422 | tries = 1; |
423 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
424 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
425 | |
426 | for (i = 0; i < tries ; i++) { |
427 | /* turn on the FORCE_DETECT */ |
428 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
429 | /* wait for FORCE_DETECT to go off */ |
430 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
431 | CRT_HOTPLUG_FORCE_DETECT) == 0, |
432 | 1000)) |
433 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off" ); |
434 | } |
435 | |
436 | stat = I915_READ(PORT_HOTPLUG_STAT); |
437 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
438 | ret = true; |
439 | |
440 | /* clear the interrupt we just generated, if any */ |
441 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
442 | |
443 | /* and put the bits back */ |
444 | I915_WRITE(PORT_HOTPLUG_EN, orig); |
445 | |
446 | return ret; |
447 | } |
448 | |
449 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
450 | struct i2c_adapter *i2c) |
451 | { |
452 | struct edid *edid; |
453 | |
454 | edid = drm_get_edid(connector, i2c); |
455 | |
456 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { |
457 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n" ); |
458 | intel_gmbus_force_bit(i2c, true); |
459 | edid = drm_get_edid(connector, i2c); |
460 | intel_gmbus_force_bit(i2c, false); |
461 | } |
462 | |
463 | return edid; |
464 | } |
465 | |
466 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
467 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
468 | struct i2c_adapter *adapter) |
469 | { |
470 | struct edid *edid; |
471 | int ret; |
472 | |
473 | edid = intel_crt_get_edid(connector, adapter); |
474 | if (!edid) |
475 | return 0; |
476 | |
477 | ret = intel_connector_update_modes(connector, edid); |
478 | kfree(edid); |
479 | |
480 | return ret; |
481 | } |
482 | |
483 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
484 | { |
485 | struct intel_crt *crt = intel_attached_crt(connector); |
486 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
487 | struct edid *edid; |
488 | struct i2c_adapter *i2c; |
489 | |
490 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
491 | |
492 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
493 | edid = intel_crt_get_edid(connector, i2c); |
494 | |
495 | if (edid) { |
496 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; |
497 | |
498 | /* |
499 | * This may be a DVI-I connector with a shared DDC |
500 | * link between analog and digital outputs, so we |
501 | * have to check the EDID input spec of the attached device. |
502 | */ |
503 | if (!is_digital) { |
504 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n" ); |
505 | return true; |
506 | } |
507 | |
508 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n" ); |
509 | } else { |
510 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n" ); |
511 | } |
512 | |
513 | kfree(edid); |
514 | |
515 | return false; |
516 | } |
517 | |
518 | static enum drm_connector_status |
519 | intel_crt_load_detect(struct intel_crt *crt) |
520 | { |
521 | struct drm_device *dev = crt->base.base.dev; |
522 | struct drm_i915_private *dev_priv = dev->dev_private; |
523 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
524 | uint32_t save_bclrpat; |
525 | uint32_t save_vtotal; |
526 | uint32_t vtotal, vactive; |
527 | uint32_t vsample; |
528 | uint32_t vblank, vblank_start, vblank_end; |
529 | uint32_t dsl; |
530 | uint32_t bclrpat_reg; |
531 | uint32_t vtotal_reg; |
532 | uint32_t vblank_reg; |
533 | uint32_t vsync_reg; |
534 | uint32_t pipeconf_reg; |
535 | uint32_t pipe_dsl_reg; |
536 | uint8_t st00; |
537 | enum drm_connector_status status; |
538 | |
539 | DRM_DEBUG_KMS("starting load-detect on CRT\n" ); |
540 | |
541 | bclrpat_reg = BCLRPAT(pipe); |
542 | vtotal_reg = VTOTAL(pipe); |
543 | vblank_reg = VBLANK(pipe); |
544 | vsync_reg = VSYNC(pipe); |
545 | pipeconf_reg = PIPECONF(pipe); |
546 | pipe_dsl_reg = PIPEDSL(pipe); |
547 | |
548 | save_bclrpat = I915_READ(bclrpat_reg); |
549 | save_vtotal = I915_READ(vtotal_reg); |
550 | vblank = I915_READ(vblank_reg); |
551 | |
552 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; |
553 | vactive = (save_vtotal & 0x7ff) + 1; |
554 | |
555 | vblank_start = (vblank & 0xfff) + 1; |
556 | vblank_end = ((vblank >> 16) & 0xfff) + 1; |
557 | |
558 | /* Set the border color to purple. */ |
559 | I915_WRITE(bclrpat_reg, 0x500050); |
560 | |
561 | if (!IS_GEN2(dev)) { |
562 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
563 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
564 | POSTING_READ(pipeconf_reg); |
565 | /* Wait for next Vblank to substitue |
566 | * border color for Color info */ |
567 | intel_wait_for_vblank(dev, pipe); |
568 | st00 = I915_READ8(VGA_MSR_WRITE); |
569 | status = ((st00 & (1 << 4)) != 0) ? |
570 | connector_status_connected : |
571 | connector_status_disconnected; |
572 | |
573 | I915_WRITE(pipeconf_reg, pipeconf); |
574 | } else { |
575 | bool restore_vblank = false; |
576 | int count, detect; |
577 | |
578 | /* |
579 | * If there isn't any border, add some. |
580 | * Yes, this will flicker |
581 | */ |
582 | if (vblank_start <= vactive && vblank_end >= vtotal) { |
583 | uint32_t vsync = I915_READ(vsync_reg); |
584 | uint32_t vsync_start = (vsync & 0xffff) + 1; |
585 | |
586 | vblank_start = vsync_start; |
587 | I915_WRITE(vblank_reg, |
588 | (vblank_start - 1) | |
589 | ((vblank_end - 1) << 16)); |
590 | restore_vblank = true; |
591 | } |
592 | /* sample in the vertical border, selecting the larger one */ |
593 | if (vblank_start - vactive >= vtotal - vblank_end) |
594 | vsample = (vblank_start + vactive) >> 1; |
595 | else |
596 | vsample = (vtotal + vblank_end) >> 1; |
597 | |
598 | /* |
599 | * Wait for the border to be displayed |
600 | */ |
601 | while (I915_READ(pipe_dsl_reg) >= vactive) |
602 | ; |
603 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) |
604 | ; |
605 | /* |
606 | * Watch ST00 for an entire scanline |
607 | */ |
608 | detect = 0; |
609 | count = 0; |
610 | do { |
611 | count++; |
612 | /* Read the ST00 VGA status register */ |
613 | st00 = I915_READ8(VGA_MSR_WRITE); |
614 | if (st00 & (1 << 4)) |
615 | detect++; |
616 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
617 | |
618 | /* restore vblank if necessary */ |
619 | if (restore_vblank) |
620 | I915_WRITE(vblank_reg, vblank); |
621 | /* |
622 | * If more than 3/4 of the scanline detected a monitor, |
623 | * then it is assumed to be present. This works even on i830, |
624 | * where there isn't any way to force the border color across |
625 | * the screen |
626 | */ |
627 | status = detect * 4 > count * 3 ? |
628 | connector_status_connected : |
629 | connector_status_disconnected; |
630 | } |
631 | |
632 | /* Restore previous settings */ |
633 | I915_WRITE(bclrpat_reg, save_bclrpat); |
634 | |
635 | return status; |
636 | } |
637 | |
638 | static enum drm_connector_status |
639 | intel_crt_detect(struct drm_connector *connector, bool force) |
640 | { |
641 | struct drm_device *dev = connector->dev; |
642 | struct drm_i915_private *dev_priv = dev->dev_private; |
643 | struct intel_crt *crt = intel_attached_crt(connector); |
644 | struct intel_encoder *intel_encoder = &crt->base; |
645 | enum intel_display_power_domain power_domain; |
646 | enum drm_connector_status status; |
647 | struct intel_load_detect_pipe tmp; |
648 | |
649 | intel_runtime_pm_get(dev_priv); |
650 | |
651 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n" , |
652 | connector->base.id, drm_get_connector_name(connector), |
653 | force); |
654 | |
655 | power_domain = intel_display_port_power_domain(intel_encoder); |
656 | intel_display_power_get(dev_priv, power_domain); |
657 | |
658 | if (I915_HAS_HOTPLUG(dev)) { |
659 | /* We can not rely on the HPD pin always being correctly wired |
660 | * up, for example many KVM do not pass it through, and so |
661 | * only trust an assertion that the monitor is connected. |
662 | */ |
663 | if (intel_crt_detect_hotplug(connector)) { |
664 | DRM_DEBUG_KMS("CRT detected via hotplug\n" ); |
665 | status = connector_status_connected; |
666 | goto out; |
667 | } else |
668 | DRM_DEBUG_KMS("CRT not detected via hotplug\n" ); |
669 | } |
670 | |
671 | if (intel_crt_detect_ddc(connector)) { |
672 | status = connector_status_connected; |
673 | goto out; |
674 | } |
675 | |
676 | /* Load detection is broken on HPD capable machines. Whoever wants a |
677 | * broken monitor (without edid) to work behind a broken kvm (that fails |
678 | * to have the right resistors for HP detection) needs to fix this up. |
679 | * For now just bail out. */ |
680 | if (I915_HAS_HOTPLUG(dev)) { |
681 | status = connector_status_disconnected; |
682 | goto out; |
683 | } |
684 | |
685 | if (!force) { |
686 | status = connector->status; |
687 | goto out; |
688 | } |
689 | |
690 | /* for pre-945g platforms use load detect */ |
691 | if (intel_get_load_detect_pipe(connector, NULL, &tmp)) { |
692 | if (intel_crt_detect_ddc(connector)) |
693 | status = connector_status_connected; |
694 | else |
695 | status = intel_crt_load_detect(crt); |
696 | intel_release_load_detect_pipe(connector, &tmp); |
697 | } else |
698 | status = connector_status_unknown; |
699 | |
700 | out: |
701 | intel_display_power_put(dev_priv, power_domain); |
702 | intel_runtime_pm_put(dev_priv); |
703 | |
704 | return status; |
705 | } |
706 | |
707 | static void intel_crt_destroy(struct drm_connector *connector) |
708 | { |
709 | drm_connector_cleanup(connector); |
710 | kfree(connector); |
711 | } |
712 | |
713 | static int intel_crt_get_modes(struct drm_connector *connector) |
714 | { |
715 | struct drm_device *dev = connector->dev; |
716 | struct drm_i915_private *dev_priv = dev->dev_private; |
717 | struct intel_crt *crt = intel_attached_crt(connector); |
718 | struct intel_encoder *intel_encoder = &crt->base; |
719 | enum intel_display_power_domain power_domain; |
720 | int ret; |
721 | struct i2c_adapter *i2c; |
722 | |
723 | power_domain = intel_display_port_power_domain(intel_encoder); |
724 | intel_display_power_get(dev_priv, power_domain); |
725 | |
726 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
727 | ret = intel_crt_ddc_get_modes(connector, i2c); |
728 | if (ret || !IS_G4X(dev)) |
729 | goto out; |
730 | |
731 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
732 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
733 | ret = intel_crt_ddc_get_modes(connector, i2c); |
734 | |
735 | out: |
736 | intel_display_power_put(dev_priv, power_domain); |
737 | |
738 | return ret; |
739 | } |
740 | |
741 | static int intel_crt_set_property(struct drm_connector *connector, |
742 | struct drm_property *property, |
743 | uint64_t value) |
744 | { |
745 | return 0; |
746 | } |
747 | |
748 | static void intel_crt_reset(struct drm_connector *connector) |
749 | { |
750 | struct drm_device *dev = connector->dev; |
751 | struct drm_i915_private *dev_priv = dev->dev_private; |
752 | struct intel_crt *crt = intel_attached_crt(connector); |
753 | |
754 | if (INTEL_INFO(dev)->gen >= 5) { |
755 | u32 adpa; |
756 | |
757 | adpa = I915_READ(crt->adpa_reg); |
758 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
759 | adpa |= ADPA_HOTPLUG_BITS; |
760 | I915_WRITE(crt->adpa_reg, adpa); |
761 | POSTING_READ(crt->adpa_reg); |
762 | |
763 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n" , adpa); |
764 | crt->force_hotplug_required = 1; |
765 | } |
766 | |
767 | } |
768 | |
769 | /* |
770 | * Routines for controlling stuff on the analog port |
771 | */ |
772 | |
773 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
774 | .reset = intel_crt_reset, |
775 | .dpms = intel_crt_dpms, |
776 | .detect = intel_crt_detect, |
777 | .fill_modes = drm_helper_probe_single_connector_modes, |
778 | .destroy = intel_crt_destroy, |
779 | .set_property = intel_crt_set_property, |
780 | }; |
781 | |
782 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { |
783 | .mode_valid = intel_crt_mode_valid, |
784 | .get_modes = intel_crt_get_modes, |
785 | .best_encoder = intel_best_encoder, |
786 | }; |
787 | |
788 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
789 | .destroy = intel_encoder_destroy, |
790 | }; |
791 | |
792 | static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
793 | { |
794 | DRM_INFO("Skipping CRT initialization for %s\n" , id->ident); |
795 | return 1; |
796 | } |
797 | |
798 | static const struct dmi_system_id intel_no_crt[] = { |
799 | { |
800 | .callback = intel_no_crt_dmi_callback, |
801 | .ident = "ACER ZGB" , |
802 | .matches = { |
803 | DMI_MATCH(DMI_SYS_VENDOR, "ACER" ), |
804 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB" ), |
805 | }, |
806 | }, |
807 | { |
808 | .callback = intel_no_crt_dmi_callback, |
809 | .ident = "DELL XPS 8700" , |
810 | .matches = { |
811 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc." ), |
812 | DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700" ), |
813 | }, |
814 | }, |
815 | { .callback = NULL } |
816 | }; |
817 | |
818 | void intel_crt_init(struct drm_device *dev) |
819 | { |
820 | struct drm_connector *connector; |
821 | struct intel_crt *crt; |
822 | struct intel_connector *intel_connector; |
823 | struct drm_i915_private *dev_priv = dev->dev_private; |
824 | |
825 | /* Skip machines without VGA that falsely report hotplug events */ |
826 | if (dmi_check_system(intel_no_crt)) |
827 | return; |
828 | |
829 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
830 | if (!crt) |
831 | return; |
832 | |
833 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
834 | if (!intel_connector) { |
835 | kfree(crt); |
836 | return; |
837 | } |
838 | |
839 | connector = &intel_connector->base; |
840 | crt->connector = intel_connector; |
841 | drm_connector_init(dev, &intel_connector->base, |
842 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
843 | |
844 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
845 | DRM_MODE_ENCODER_DAC); |
846 | |
847 | intel_connector_attach_encoder(intel_connector, &crt->base); |
848 | |
849 | crt->base.type = INTEL_OUTPUT_ANALOG; |
850 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
851 | if (IS_I830(dev)) |
852 | crt->base.crtc_mask = (1 << 0); |
853 | else |
854 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
855 | |
856 | if (IS_GEN2(dev)) |
857 | connector->interlace_allowed = 0; |
858 | else |
859 | connector->interlace_allowed = 1; |
860 | connector->doublescan_allowed = 0; |
861 | |
862 | if (HAS_PCH_SPLIT(dev)) |
863 | crt->adpa_reg = PCH_ADPA; |
864 | else if (IS_VALLEYVIEW(dev)) |
865 | crt->adpa_reg = VLV_ADPA; |
866 | else |
867 | crt->adpa_reg = ADPA; |
868 | |
869 | crt->base.compute_config = intel_crt_compute_config; |
870 | crt->base.mode_set = intel_crt_mode_set; |
871 | crt->base.disable = intel_disable_crt; |
872 | crt->base.enable = intel_enable_crt; |
873 | if (I915_HAS_HOTPLUG(dev)) |
874 | crt->base.hpd_pin = HPD_CRT; |
875 | if (HAS_DDI(dev)) { |
876 | crt->base.get_config = hsw_crt_get_config; |
877 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
878 | } else { |
879 | crt->base.get_config = intel_crt_get_config; |
880 | crt->base.get_hw_state = intel_crt_get_hw_state; |
881 | } |
882 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
883 | intel_connector->unregister = intel_connector_unregister; |
884 | |
885 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
886 | |
887 | drm_sysfs_connector_add(connector); |
888 | |
889 | if (!I915_HAS_HOTPLUG(dev)) |
890 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
891 | |
892 | /* |
893 | * Configure the automatic hotplug detection stuff |
894 | */ |
895 | crt->force_hotplug_required = 0; |
896 | |
897 | /* |
898 | * TODO: find a proper way to discover whether we need to set the the |
899 | * polarity and link reversal bits or not, instead of relying on the |
900 | * BIOS. |
901 | */ |
902 | if (HAS_PCH_LPT(dev)) { |
903 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
904 | FDI_RX_LINK_REVERSAL_OVERRIDE; |
905 | |
906 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; |
907 | } |
908 | |
909 | intel_crt_reset(connector); |
910 | } |
911 | |