1 | /* $NetBSD: inphyreg.h,v 1.5 2008/04/28 20:23:53 martin Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 1998 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, |
9 | * NASA Ames Research Center. |
10 | * |
11 | * Redistribution and use in source and binary forms, with or without |
12 | * modification, are permitted provided that the following conditions |
13 | * are met: |
14 | * 1. Redistributions of source code must retain the above copyright |
15 | * notice, this list of conditions and the following disclaimer. |
16 | * 2. Redistributions in binary form must reproduce the above copyright |
17 | * notice, this list of conditions and the following disclaimer in the |
18 | * documentation and/or other materials provided with the distribution. |
19 | * |
20 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
21 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
22 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
23 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
24 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
30 | * POSSIBILITY OF SUCH DAMAGE. |
31 | */ |
32 | |
33 | #ifndef _DEV_MII_INPHYREG_H_ |
34 | #define _DEV_MII_INPHYREG_H_ |
35 | |
36 | /* |
37 | * Intel 82555 registers. |
38 | */ |
39 | |
40 | #define MII_INPHY_SCR 0x10 /* Status and Control */ |
41 | #define SCR_FLOWCTL 0x8000 /* PHY Base flow control enabled */ |
42 | #define SCR_CSDC 0x2000 /* Carrier sense disconnect control */ |
43 | #define SCR_TFCD 0x1000 /* Transmit flow control disable */ |
44 | #define SCR_RDSI 0x0800 /* Receive deserializer in-sync */ |
45 | #define SCR_100TXPD 0x0400 /* 100baseTX is powered down */ |
46 | #define SCR_10TPD 0x0200 /* 10baseT is powered down */ |
47 | #define SCR_POLARITY 0x0100 /* reverse 10baseT polarity */ |
48 | #define SCR_T4 0x0004 /* autoneg resulted in 100baseT4 */ |
49 | #define SCR_S100 0x0002 /* autoneg resulted in 100baseTX */ |
50 | #define SCR_FDX 0x0001 /* autoneg resulted in full-duplex */ |
51 | |
52 | #define MII_INPHY_SCTRL 0x11 /* Special Control Bit */ |
53 | #define SCTRL_SCRBYPASS 0x8000 /* scrambler bypass */ |
54 | #define SCTRL_4B5BNYPASS 0x4000 /* 4bit to 5bit bypass */ |
55 | #define SCTRL_FTHP 0x2000 /* force transmit H-pattern */ |
56 | #define SCTRL_F34TP 0x1000 /* force 34 transmit patter */ |
57 | #define SCTRL_GOODLINK 0x0800 /* 100baseTX link good */ |
58 | #define SCTRL_TCSD 0x0200 /* transmit carrier sense disable */ |
59 | #define SCTRL_DDPD 0x0100 /* disable dynamic power-down */ |
60 | #define SCTRL_ANEGLOOP 0x0080 /* autonegotiation loopback */ |
61 | #define SCTRL_MDITRISTATE 0x0040 /* MDI Tri-state */ |
62 | #define SCTRL_FILTERBYPASS 0x0020 /* Filter bypass */ |
63 | #define SCTRL_AUTOPOLDIS 0x0010 /* auto-polarity disable */ |
64 | #define SCTRL_SQUELCHDIS 0x0008 /* squlch test disable */ |
65 | #define SCTRL_EXTSQUELCH 0x0004 /* extended sequelch enable */ |
66 | #define SCTRL_LINKINTDIS 0x0002 /* link integrity disable */ |
67 | #define SCTRL_JABBERDIS 0x0001 /* jabber disabled */ |
68 | |
69 | #define MII_INPHY_100TXRDC 0x14 /* 100baseTX Receive Disconnect Cntr */ |
70 | |
71 | #define MII_INPHY_100TXREFC 0x15 /* 100baseTX Receive Error Frame Ctr */ |
72 | |
73 | #define MII_INPHY_RSEC 0x16 /* Receive Symbol Error Counter */ |
74 | |
75 | #define MII_INPHY_100TXRPEOFC 0x17 /* 100baseTX Rcv Premature EOF Ctr */ |
76 | |
77 | #define MII_INPHY_10TREOFC 0x18 /* 10baseT Rcv EOF Ctr */ |
78 | |
79 | #define MII_INPHY_10TTJDC 0x19 /* 10baseT Tx Jabber Detect Ctr */ |
80 | |
81 | #define MII_INPHY_SCTRL2 0x1b /* 82555 Special Control */ |
82 | #define SCTRL2_LEDMASK 0x0007 /* mask of LEDs control: see below */ |
83 | |
84 | #define LEDMASK_ACTLINK 0x0000 /* A = Activity, L = Link */ |
85 | #define LEDMASK_SPDCOLL 0x0001 /* A = Speed, L = Collision */ |
86 | #define LEDMASK_SPDLINK 0x0002 /* A = Speed, L = Link */ |
87 | #define LEDMASK_ACTCOLL 0x0003 /* A = Activity, L = Collision */ |
88 | #define LEDMASK_OFFOFF 0x0004 /* A = off, L = off */ |
89 | #define LEDMASK_OFFON 0x0005 /* A = off, L = on */ |
90 | #define LEDMASK_ONOFF 0x0006 /* A = on, L = off */ |
91 | #define LESMASK_ONON 0x0007 /* A = on, L = on */ |
92 | |
93 | #endif /* _DEV_MII_INPHYREG_H_ */ |
94 | |