1 | /* $NetBSD: sdhcreg.h,v 1.18 2015/12/31 11:53:19 ryo Exp $ */ |
2 | /* $OpenBSD: sdhcreg.h,v 1.4 2006/07/30 17:20:40 fgsch Exp $ */ |
3 | |
4 | /* |
5 | * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> |
6 | * |
7 | * Permission to use, copy, modify, and distribute this software for any |
8 | * purpose with or without fee is hereby granted, provided that the above |
9 | * copyright notice and this permission notice appear in all copies. |
10 | * |
11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
18 | */ |
19 | |
20 | #ifndef _SDHCREG_H_ |
21 | #define _SDHCREG_H_ |
22 | |
23 | /* Host standard register set */ |
24 | #define SDHC_DMA_ADDR 0x00 |
25 | #define SDHC_BLOCK_SIZE 0x04 |
26 | #define SDHC_DMA_BOUNDARY_SHIFT 12 |
27 | #define SDHC_DMA_BOUNDARY_MASK 0x7 |
28 | #define SDHC_BLOCK_COUNT 0x06 |
29 | #define SDHC_BLOCK_COUNT_MAX 512 |
30 | #define SDHC_ARGUMENT 0x08 |
31 | #define SDHC_TRANSFER_MODE 0x0c |
32 | #define SDHC_MULTI_BLOCK_MODE (1<<5) |
33 | #define SDHC_READ_MODE (1<<4) |
34 | #define SDHC_AUTO_CMD12_ENABLE (1<<2) |
35 | #define SDHC_BLOCK_COUNT_ENABLE (1<<1) |
36 | #define SDHC_DMA_ENABLE (1<<0) |
37 | #define SDHC_COMMAND 0x0e |
38 | /* 14-15 reserved */ |
39 | #define SDHC_COMMAND_INDEX_SHIFT 8 |
40 | #define SDHC_COMMAND_INDEX_MASK 0x3f |
41 | #define SDHC_COMMAND_TYPE_ABORT (3<<6) |
42 | #define SDHC_COMMAND_TYPE_RESUME (2<<6) |
43 | #define SDHC_COMMAND_TYPE_SUSPEND (1<<6) |
44 | #define SDHC_COMMAND_TYPE_NORMAL (0<<6) |
45 | #define SDHC_DATA_PRESENT_SELECT (1<<5) |
46 | #define SDHC_INDEX_CHECK_ENABLE (1<<4) |
47 | #define SDHC_CRC_CHECK_ENABLE (1<<3) |
48 | /* 2 reserved */ |
49 | #define SDHC_RESP_LEN_48_CHK_BUSY (3<<0) |
50 | #define SDHC_RESP_LEN_48 (2<<0) |
51 | #define SDHC_RESP_LEN_136 (1<<0) |
52 | #define SDHC_NO_RESPONSE (0<<0) |
53 | #define SDHC_RESPONSE 0x10 /* - 0x1f */ |
54 | #define SDHC_DATA 0x20 |
55 | #define SDHC_PRESENT_STATE 0x24 |
56 | /* 25-31 reserved */ |
57 | #define SDHC_CMD_LINE_SIGNAL_LEVEL (1<<24) |
58 | #define SDHC_DAT3_LINE_LEVEL (1<<23) |
59 | #define SDHC_DAT2_LINE_LEVEL (1<<22) |
60 | #define SDHC_DAT1_LINE_LEVEL (1<<21) |
61 | #define SDHC_DAT0_LINE_LEVEL (1<<20) |
62 | #define SDHC_WRITE_PROTECT_SWITCH (1<<19) |
63 | #define SDHC_CARD_DETECT_PIN_LEVEL (1<<18) |
64 | #define SDHC_CARD_STATE_STABLE (1<<17) |
65 | #define SDHC_CARD_INSERTED (1<<16) |
66 | /* 12-15 reserved */ |
67 | #define SDHC_BUFFER_READ_ENABLE (1<<11) |
68 | #define SDHC_BUFFER_WRITE_ENABLE (1<<10) |
69 | #define SDHC_READ_TRANSFER_ACTIVE (1<<9) |
70 | #define SDHC_WRITE_TRANSFER_ACTIVE (1<<8) |
71 | /* 4-7 reserved */ |
72 | #define SDHC_SDSTB (1<<3) /* uSDHC */ |
73 | #define SDHC_DAT_ACTIVE (1<<2) |
74 | #define SDHC_CMD_INHIBIT_DAT (1<<1) |
75 | #define SDHC_CMD_INHIBIT_CMD (1<<0) |
76 | #define SDHC_CMD_INHIBIT_MASK 0x0003 |
77 | #define SDHC_HOST_CTL 0x28 |
78 | #define SDHC_USDHC_BURST_LEN_EN (1<<27) /* uSDHC */ |
79 | #define SDHC_USDHC_HOST_CTL_RESV23 (1<<23) /* uSDHC */ |
80 | #define SDHC_USDHC_DMA_SELECT (3<<8) /* uSDHC */ |
81 | #define SDHC_USDHC_DMA_SELECT_ADMA1 (1<<8) /* uSDHC */ |
82 | #define SDHC_USDHC_DMA_SELECT_ADMA2 (2<<8) /* uSDHC */ |
83 | #define SDHC_USDHC_EMODE (3<<4) /* uSDHC */ |
84 | #define SDHC_USDHC_EMODE_LE (2<<4) /* uSDHC */ |
85 | #define SDHC_8BIT_MODE (1<<5) |
86 | #define SDHC_DMA_SELECT (3<<3) |
87 | #define SDHC_DMA_SELECT_SDMA (0<<3) |
88 | #define SDHC_DMA_SELECT_ADMA2 (2<<3) |
89 | #define SDHC_HIGH_SPEED (1<<2) |
90 | #define SDHC_ESDHC_8BIT_MODE (1<<2) /* eSDHC */ |
91 | #define SDHC_4BIT_MODE (1<<1) |
92 | #define SDHC_LED_ON (1<<0) |
93 | #define SDHC_POWER_CTL 0x29 |
94 | #define SDHC_VOLTAGE_SHIFT 1 |
95 | #define SDHC_VOLTAGE_MASK 0x07 |
96 | #define SDHC_VOLTAGE_3_3V 0x07 |
97 | #define SDHC_VOLTAGE_3_0V 0x06 |
98 | #define SDHC_VOLTAGE_1_8V 0x05 |
99 | #define SDHC_BUS_POWER (1<<0) |
100 | #define SDHC_BLOCK_GAP_CTL 0x2a |
101 | #define SDHC_WAKEUP_CTL 0x2b |
102 | #define SDHC_CLOCK_CTL 0x2c |
103 | #define SDHC_SDCLK_DIV_SHIFT 8 |
104 | #define SDHC_SDCLK_DIV_MASK 0xff |
105 | #define SDHC_SDCLK_XDIV_SHIFT 6 |
106 | #define SDHC_SDCLK_XDIV_MASK 0x3 |
107 | #define SDHC_SDCLK_CGM (1<<5) |
108 | #define SDHC_SDCLK_DVS_SHIFT 4 |
109 | #define SDHC_SDCLK_DVS_MASK 0xf |
110 | #define SDHC_SDCLK_ENABLE (1<<2) |
111 | #define SDHC_INTCLK_STABLE (1<<1) |
112 | #define SDHC_INTCLK_ENABLE (1<<0) |
113 | #define SDHC_TIMEOUT_CTL 0x2e |
114 | #define SDHC_TIMEOUT_MAX 0x0e |
115 | #define SDHC_SOFTWARE_RESET 0x2f |
116 | #define SDHC_INIT_ACTIVE (1<<3) /* ESDHC */ |
117 | #define SDHC_RESET_MASK 0x5 |
118 | #define SDHC_RESET_DAT (1<<2) |
119 | #define SDHC_RESET_CMD (1<<1) |
120 | #define SDHC_RESET_ALL (1<<0) |
121 | #define SDHC_NINTR_STATUS 0x30 |
122 | #define SDHC_ERROR_INTERRUPT (1<<15) |
123 | #define SDHC_RETUNING_EVENT (1<<12) |
124 | #define SDHC_CARD_INTERRUPT (1<<8) |
125 | #define SDHC_CARD_REMOVAL (1<<7) |
126 | #define SDHC_CARD_INSERTION (1<<6) |
127 | #define SDHC_BUFFER_READ_READY (1<<5) |
128 | #define SDHC_BUFFER_WRITE_READY (1<<4) |
129 | #define SDHC_DMA_INTERRUPT (1<<3) |
130 | #define SDHC_BLOCK_GAP_EVENT (1<<2) |
131 | #define SDHC_TRANSFER_COMPLETE (1<<1) |
132 | #define SDHC_COMMAND_COMPLETE (1<<0) |
133 | #define SDHC_NINTR_STATUS_MASK 0x91ff |
134 | #define SDHC_EINTR_STATUS 0x32 |
135 | #define SDHC_DMA_ERROR (1<<12) |
136 | #define SDHC_ADMA_ERROR (1<<9) |
137 | #define SDHC_AUTO_CMD12_ERROR (1<<8) |
138 | #define SDHC_CURRENT_LIMIT_ERROR (1<<7) |
139 | #define SDHC_DATA_END_BIT_ERROR (1<<6) |
140 | #define SDHC_DATA_CRC_ERROR (1<<5) |
141 | #define SDHC_DATA_TIMEOUT_ERROR (1<<4) |
142 | #define SDHC_CMD_INDEX_ERROR (1<<3) |
143 | #define SDHC_CMD_END_BIT_ERROR (1<<2) |
144 | #define SDHC_CMD_CRC_ERROR (1<<1) |
145 | #define SDHC_CMD_TIMEOUT_ERROR (1<<0) |
146 | #define SDHC_EINTR_STATUS_MASK 0x03ff /* excluding vendor signals */ |
147 | #define SDHC_NINTR_STATUS_EN 0x34 |
148 | #define SDHC_EINTR_STATUS_EN 0x36 |
149 | #define SDHC_NINTR_SIGNAL_EN 0x38 |
150 | #define SDHC_NINTR_SIGNAL_MASK 0x01ff |
151 | #define SDHC_EINTR_SIGNAL_EN 0x3a |
152 | #define SDHC_EINTR_SIGNAL_MASK 0x03ff /* excluding vendor signals */ |
153 | #define SDHC_CMD12_ERROR_STATUS 0x3c |
154 | #define SDHC_HOST_CTL2 0x3e |
155 | #define SDHC_SAMPLING_CLOCK_SEL (1<<7) |
156 | #define SDHC_EXECUTE_TUNING (1<<6) |
157 | #define SDHC_1_8V_SIGNAL_EN (1<<3) |
158 | #define SDHC_UHS_MODE_SELECT_SHIFT 0 |
159 | #define SDHC_UHS_MODE_SELECT_MASK 0x7 |
160 | #define SDHC_UHS_MODE_SELECT_SDR12 0 |
161 | #define SDHC_UHS_MODE_SELECT_SDR25 1 |
162 | #define SDHC_UHS_MODE_SELECT_SDR50 2 |
163 | #define SDHC_UHS_MODE_SELECT_SDR104 3 |
164 | #define SDHC_UHS_MODE_SELECT_DDR50 4 |
165 | #define SDHC_CAPABILITIES 0x40 |
166 | #define SDHC_SHARED_BUS_SLOT (1<<31) |
167 | #define SDHC_EMBEDDED_SLOT (1<<30) |
168 | #define SDHC_ASYNC_INTR (1<<29) |
169 | #define SDHC_64BIT_SYS_BUS (1<<28) |
170 | #define SDHC_VOLTAGE_SUPP_1_8V (1<<26) |
171 | #define SDHC_VOLTAGE_SUPP_3_0V (1<<25) |
172 | #define SDHC_VOLTAGE_SUPP_3_3V (1<<24) |
173 | #define SDHC_DMA_SUPPORT (1<<22) |
174 | #define SDHC_HIGH_SPEED_SUPP (1<<21) |
175 | #define SDHC_ADMA1_SUPP (1<<20) |
176 | #define SDHC_ADMA2_SUPP (1<<19) |
177 | #define SDHC_8BIT_SUPP (1<<18) |
178 | #define SDHC_MAX_BLK_LEN_512 0 |
179 | #define SDHC_MAX_BLK_LEN_1024 1 |
180 | #define SDHC_MAX_BLK_LEN_2048 2 |
181 | #define SDHC_MAX_BLK_LEN_4096 3 |
182 | #define SDHC_MAX_BLK_LEN_SHIFT 16 |
183 | #define SDHC_MAX_BLK_LEN_MASK 0x3 |
184 | #define SDHC_BASE_FREQ_SHIFT 8 |
185 | #define SDHC_BASE_FREQ_MASK 0x3f |
186 | #define SDHC_BASE_V3_FREQ_MASK 0xff |
187 | #define SDHC_TIMEOUT_FREQ_UNIT (1<<7) /* 0=KHz, 1=MHz */ |
188 | #define SDHC_TIMEOUT_FREQ_SHIFT 0 |
189 | #define SDHC_TIMEOUT_FREQ_MASK 0x1f |
190 | #define SDHC_CAPABILITIES2 0x44 |
191 | #define SDHC_SDR50_SUPP (1<<0) |
192 | #define SDHC_SDR104_SUPP (1<<1) |
193 | #define SDHC_DDR50_SUPP (1<<2) |
194 | #define SDHC_DRIVER_TYPE_A (1<<4) |
195 | #define SDHC_DRIVER_TYPE_C (1<<5) |
196 | #define SDHC_DRIVER_TYPE_D (1<<6) |
197 | #define SDHC_TIMER_COUNT_SHIFT 8 |
198 | #define SDHC_TIMER_COUNT_MASK 0xf |
199 | #define SDHC_TUNING_SDR50 (1<<13) |
200 | #define SDHC_RETUNING_MODES_SHIFT 14 |
201 | #define SDHC_RETUNING_MODES_MASK 0x3 |
202 | #define SDHC_RETUNING_MODE_1 (0 << SDHC_RETUNING_MODES_SHIFT) |
203 | #define SDHC_RETUNING_MODE_2 (1 << SDHC_RETUNING_MODES_SHIFT) |
204 | #define SDHC_RETUNING_MODE_3 (2 << SDHC_RETUNING_MODES_SHIFT) |
205 | #define SDHC_CLOCK_MULTIPLIER_SHIFT 16 |
206 | #define SDHC_CLOCK_MULTIPLIER_MASK 0xff |
207 | #define SDHC_ADMA_ERROR_STATUS 0x54 |
208 | #define SDHC_ADMA_LENGTH_MISMATCH (1<<2) |
209 | #define SDHC_ADMA_ERROR_STATE (3<<0) |
210 | #define SDHC_ADMA_SYSTEM_ADDR 0x58 |
211 | #define SDHC_WATERMARK_LEVEL 0x44 /* ESDHC/uSDHC */ |
212 | #define SDHC_WATERMARK_WR_BRST_SHIFT 24 /* uSDHC */ |
213 | #define SDHC_WATERMARK_WR_BRST_MASK 0x1f /* uSDHC */ |
214 | #define SDHC_WATERMARK_WRITE_SHIFT 16 |
215 | #define SDHC_WATERMARK_WRITE_MASK 0xff |
216 | #define SDHC_WATERMARK_RD_BRST_SHIFT 8 /* uSDHC */ |
217 | #define SDHC_WATERMARK_RD_BRST_MASK 0x1f /* uSDHC */ |
218 | #define SDHC_WATERMARK_READ_SHIFT 0 |
219 | #define SDHC_WATERMARK_READ_MASK 0xff |
220 | #define SDHC_MAX_CAPABILITIES 0x48 |
221 | #define SDHC_SLOT_INTR_STATUS 0xfc |
222 | #define SDHC_ESDHC_HOST_CTL_VERSION 0xfc /* eSDHC */ |
223 | #define SDHC_HOST_CTL_VERSION 0xfe |
224 | #define SDHC_SPEC_VERS_SHIFT 0 |
225 | #define SDHC_SPEC_VERS_MASK 0xff |
226 | #define SDHC_VENDOR_VERS_SHIFT 8 |
227 | #define SDHC_VENDOR_VERS_MASK 0xff |
228 | #define SDHC_DMA_CTL 0x40c /* eSDHC */ |
229 | #define SDHC_DMA_SNOOP 0x40 |
230 | #define SDHC_MIX_CTRL 0x48 /* uSDHC */ |
231 | #define SDHC_USDHC_DDR_EN (1<<3) |
232 | #define SDHC_VEND_SPEC 0xc0 /* uSDHC */ |
233 | #define SDHC_VEND_SPEC_MBO (1<<29) |
234 | #define SDHC_VEND_SPEC_CARD_CLK_SOFT_EN (1<<14) |
235 | #define SDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN (1<<13) |
236 | #define SDHC_VEND_SPEC_HCLK_SOFT_EN (1<<12) |
237 | #define SDHC_VEND_SPEC_IPG_CLK_SOFT_EN (1<<11) |
238 | #define SDHC_VEND_SPEC_FRC_SDCLK_ON (1<<8) |
239 | #define SDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN (1<<3) |
240 | #define SDHC_VEND_SPEC_VSELECT (1<<1) |
241 | #define SDHC_MMC_BOOT 0xc4 /* uSDHC */ |
242 | #define SDHC_VEND_SPEC2 0xc8 /* uSDHC */ |
243 | |
244 | /* SDHC_SPEC_VERS */ |
245 | #define SDHC_SPEC_VERS_100 0x00 |
246 | #define SDHC_SPEC_VERS_200 0x01 |
247 | #define SDHC_SPEC_VERS_300 0x02 |
248 | #define SDHC_SPEC_VERS_400 0x03 |
249 | |
250 | /* SDHC_CAPABILITIES decoding */ |
251 | #define SDHC_BASE_V3_FREQ_KHZ(cap) \ |
252 | ((((cap) >> SDHC_BASE_FREQ_SHIFT) & SDHC_BASE_V3_FREQ_MASK) * 1000) |
253 | #define SDHC_BASE_FREQ_KHZ(cap) \ |
254 | ((((cap) >> SDHC_BASE_FREQ_SHIFT) & SDHC_BASE_FREQ_MASK) * 1000) |
255 | #define SDHC_TIMEOUT_FREQ(cap) \ |
256 | (((cap) >> SDHC_TIMEOUT_FREQ_SHIFT) & SDHC_TIMEOUT_FREQ_MASK) |
257 | #define SDHC_TIMEOUT_FREQ_KHZ(cap) \ |
258 | (((cap) & SDHC_TIMEOUT_FREQ_UNIT) ? \ |
259 | SDHC_TIMEOUT_FREQ(cap) * 1000: \ |
260 | SDHC_TIMEOUT_FREQ(cap)) |
261 | |
262 | /* SDHC_HOST_CTL_VERSION decoding */ |
263 | #define SDHC_SPEC_VERSION(hcv) \ |
264 | (((hcv) >> SDHC_SPEC_VERS_SHIFT) & SDHC_SPEC_VERS_MASK) |
265 | #define SDHC_VENDOR_VERSION(hcv) \ |
266 | (((hcv) >> SDHC_VENDOR_VERS_SHIFT) & SDHC_VENDOR_VERS_MASK) |
267 | |
268 | #define SDHC_PRESENT_STATE_BITS \ |
269 | "\20\31CL\30D3L\27D2L\26D1L\25D0L\24WPS\23CD\22CSS\21CI" \ |
270 | "\14BRE\13BWE\12RTA\11WTA\3DLA\2CID\1CIC" |
271 | #define SDHC_NINTR_STATUS_BITS \ |
272 | "\20\20ERROR\11CARD\10REMOVAL\7INSERTION\6READ\5WRITE" \ |
273 | "\4DMA\3GAP\2XFER\1CMD" |
274 | #define SDHC_EINTR_STATUS_BITS \ |
275 | "\20\11ACMD12\10CL\7DEB\6DCRC\5DT\4CI\3CEB\2CCRC\1CT" |
276 | #define SDHC_CAPABILITIES_BITS \ |
277 | "\20\33Vdd1.8V\32Vdd3.0V\31Vdd3.3V\30SUSPEND\27DMA\26HIGHSPEED" |
278 | |
279 | #define SDHC_ADMA2_VALID (1<<0) |
280 | #define SDHC_ADMA2_END (1<<1) |
281 | #define SDHC_ADMA2_INT (1<<2) |
282 | #define SDHC_ADMA2_ACT (3<<4) |
283 | #define SDHC_ADMA2_ACT_NOP (0<<4) |
284 | #define SDHC_ADMA2_ACT_TRANS (2<<4) |
285 | #define SDHC_ADMA2_ACT_LINK (3<<4) |
286 | |
287 | struct sdhc_adma2_descriptor32 { |
288 | uint16_t attribute; |
289 | uint16_t length; |
290 | uint32_t address; |
291 | } __packed; |
292 | |
293 | struct sdhc_adma2_descriptor64 { |
294 | uint16_t attribute; |
295 | uint16_t length; |
296 | uint32_t address; |
297 | uint32_t address_hi; |
298 | } __packed; |
299 | |
300 | #endif /* _SDHCREG_H_ */ |
301 | |