1 | #ifndef __NVBIOS_PLL_H__ |
2 | #define __NVBIOS_PLL_H__ |
3 | |
4 | /*XXX: kill me */ |
5 | struct nouveau_pll_vals { |
6 | union { |
7 | struct { |
8 | #ifdef __BIG_ENDIAN |
9 | uint8_t N1, M1, N2, M2; |
10 | #else |
11 | uint8_t M1, N1, M2, N2; |
12 | #endif |
13 | }; |
14 | struct { |
15 | uint16_t NM1, NM2; |
16 | } __attribute__((packed)); |
17 | }; |
18 | int log2P; |
19 | |
20 | int refclk; |
21 | }; |
22 | |
23 | struct nouveau_bios; |
24 | |
25 | /* these match types in pll limits table version 0x40, |
26 | * nouveau uses them on all chipsets internally where a |
27 | * specific pll needs to be referenced, but the exact |
28 | * register isn't known. |
29 | */ |
30 | enum nvbios_pll_type { |
31 | PLL_CORE = 0x01, |
32 | PLL_SHADER = 0x02, |
33 | PLL_UNK03 = 0x03, |
34 | PLL_MEMORY = 0x04, |
35 | PLL_VDEC = 0x05, |
36 | PLL_UNK40 = 0x40, |
37 | PLL_UNK41 = 0x41, |
38 | PLL_UNK42 = 0x42, |
39 | PLL_VPLL0 = 0x80, |
40 | PLL_VPLL1 = 0x81, |
41 | PLL_VPLL2 = 0x82, |
42 | PLL_VPLL3 = 0x83, |
43 | PLL_MAX = 0xff |
44 | }; |
45 | |
46 | struct nvbios_pll { |
47 | enum nvbios_pll_type type; |
48 | u32 reg; |
49 | u32 refclk; |
50 | |
51 | u8 min_p; |
52 | u8 max_p; |
53 | u8 bias_p; |
54 | |
55 | /* |
56 | * for most pre nv50 cards setting a log2P of 7 (the common max_log2p |
57 | * value) is no different to 6 (at least for vplls) so allowing the MNP |
58 | * calc to use 7 causes the generated clock to be out by a factor of 2. |
59 | * however, max_log2p cannot be fixed-up during parsing as the |
60 | * unmodified max_log2p value is still needed for setting mplls, hence |
61 | * an additional max_usable_log2p member |
62 | */ |
63 | u8 max_p_usable; |
64 | |
65 | struct { |
66 | u32 min_freq; |
67 | u32 max_freq; |
68 | u32 min_inputfreq; |
69 | u32 max_inputfreq; |
70 | u8 min_m; |
71 | u8 max_m; |
72 | u8 min_n; |
73 | u8 max_n; |
74 | } vco1, vco2; |
75 | }; |
76 | |
77 | int nvbios_pll_parse(struct nouveau_bios *, u32 type, struct nvbios_pll *); |
78 | |
79 | #endif |
80 | |