1/* $NetBSD: agp_i810.c,v 1.122 2016/05/01 04:22:50 nonaka Exp $ */
2
3/*-
4 * Copyright (c) 2000 Doug Rabson
5 * Copyright (c) 2000 Ruslan Ermilov
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.122 2016/05/01 04:22:50 nonaka Exp $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/atomic.h>
38#include <sys/malloc.h>
39#include <sys/kernel.h>
40#include <sys/proc.h>
41#include <sys/device.h>
42#include <sys/conf.h>
43#include <sys/xcall.h>
44
45#include <dev/pci/pcivar.h>
46#include <dev/pci/pcireg.h>
47#include <dev/pci/pcidevs.h>
48#include <dev/pci/agpvar.h>
49#include <dev/pci/agpreg.h>
50#include <dev/pci/agp_i810var.h>
51
52#include <sys/agpio.h>
53
54#include <sys/bus.h>
55
56#include "agp_intel.h"
57
58#ifdef AGP_DEBUG
59#define DPRINTF(sc, fmt, ...) \
60 device_printf((sc)->as_dev, "%s: " fmt, __func__, ##__VA_ARGS__)
61#else
62#define DPRINTF(sc, fmt, ...) do {} while (0)
63#endif
64
65struct agp_softc *agp_i810_sc = NULL;
66
67#define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off)
68#define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off)
69#define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v)
70
71#define CHIP_I810 0 /* i810/i815 */
72#define CHIP_I830 1 /* 830M/845G */
73#define CHIP_I855 2 /* 852GM/855GM/865G */
74#define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */
75#define CHIP_I965 4 /* 965Q/965PM */
76#define CHIP_G33 5 /* G33/Q33/Q35 */
77#define CHIP_G4X 6 /* G45/Q45 */
78#define CHIP_PINEVIEW 7 /* Pineview */
79
80/* XXX hack, see below */
81static bus_addr_t agp_i810_vga_regbase;
82static bus_size_t agp_i810_vga_regsize;
83static bus_space_tag_t agp_i810_vga_bst;
84static bus_space_handle_t agp_i810_vga_bsh;
85
86static u_int32_t agp_i810_get_aperture(struct agp_softc *);
87static int agp_i810_set_aperture(struct agp_softc *, u_int32_t);
88static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t);
89static int agp_i810_unbind_page(struct agp_softc *, off_t);
90static void agp_i810_flush_tlb(struct agp_softc *);
91static int agp_i810_enable(struct agp_softc *, u_int32_t mode);
92static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int,
93 vsize_t);
94static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *);
95static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *,
96 off_t);
97static int agp_i810_bind_memory_dcache(struct agp_softc *, struct agp_memory *,
98 off_t);
99static int agp_i810_bind_memory_hwcursor(struct agp_softc *,
100 struct agp_memory *, off_t);
101static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *);
102
103static bool agp_i810_resume(device_t, const pmf_qual_t *);
104static int agp_i810_init(struct agp_softc *);
105
106static int agp_i810_setup_chipset_flush_page(struct agp_softc *);
107static void agp_i810_teardown_chipset_flush_page(struct agp_softc *);
108static int agp_i810_init(struct agp_softc *);
109
110static struct agp_methods agp_i810_methods = {
111 agp_i810_get_aperture,
112 agp_i810_set_aperture,
113 agp_i810_bind_page,
114 agp_i810_unbind_page,
115 agp_i810_flush_tlb,
116 agp_i810_enable,
117 agp_i810_alloc_memory,
118 agp_i810_free_memory,
119 agp_i810_bind_memory,
120 agp_i810_unbind_memory,
121};
122
123int
124agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off,
125 bus_addr_t addr, int flags)
126{
127 u_int32_t pte;
128
129 /*
130 * Bits 11:4 (physical start address extension) should be zero.
131 * Flag bits 3:0 should be zero too.
132 *
133 * XXX This should be a kassert -- no reason for this routine
134 * to allow failure.
135 */
136 if ((addr & 0xfff) != 0)
137 return EINVAL;
138 KASSERT(flags == (flags & 0x7));
139
140 pte = (u_int32_t)addr;
141 /*
142 * We need to massage the pte if bus_addr_t is wider than 32 bits.
143 * The compiler isn't smart enough, hence the casts to uintmax_t.
144 */
145 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) {
146 /* 965+ can do 36-bit addressing, add in the extra bits. */
147 if (isc->chiptype == CHIP_I965 ||
148 isc->chiptype == CHIP_G33 ||
149 isc->chiptype == CHIP_PINEVIEW ||
150 isc->chiptype == CHIP_G4X) {
151 if (((uintmax_t)addr >> 36) != 0)
152 return EINVAL;
153 pte |= (addr >> 28) & 0xf0;
154 } else {
155 if (((uintmax_t)addr >> 32) != 0)
156 return EINVAL;
157 }
158 }
159
160 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh,
161 4*(off >> AGP_PAGE_SHIFT), pte | flags);
162
163 return 0;
164}
165
166void
167agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off)
168{
169
170 /*
171 * See <https://bugs.freedesktop.org/show_bug.cgi?id=88191>.
172 * Out of paranoia, let's do the write barrier and posting
173 * read, because I don't have enough time or hardware to
174 * conduct conclusive tests.
175 */
176 membar_producer();
177 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh,
178 4*(off >> AGP_PAGE_SHIFT));
179}
180
181static void
182agp_flush_cache_xc(void *a __unused, void *b __unused)
183{
184
185 agp_flush_cache();
186}
187
188void
189agp_i810_chipset_flush(struct agp_i810_softc *isc)
190{
191 unsigned int timo = 20000; /* * 50 us = 1 s */
192
193 switch (isc->chiptype) {
194 case CHIP_I810:
195 break;
196 case CHIP_I830:
197 case CHIP_I855:
198 /*
199 * Flush all CPU caches. If we're cold, we can't run
200 * xcalls, but there should be only one CPU up, so
201 * flushing only the local CPU's cache should suffice.
202 *
203 * XXX Come to think of it, do these chipsets appear in
204 * any multi-CPU systems?
205 */
206 if (cold)
207 agp_flush_cache();
208 else
209 xc_wait(xc_broadcast(0, &agp_flush_cache_xc,
210 NULL, NULL));
211 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31));
212 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) {
213 if (timo-- == 0)
214 break;
215 DELAY(50);
216 }
217 break;
218 case CHIP_I915:
219 case CHIP_I965:
220 case CHIP_G33:
221 case CHIP_PINEVIEW:
222 case CHIP_G4X:
223 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1);
224 break;
225 }
226}
227
228/* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */
229static int
230agp_i810_vgamatch(const struct pci_attach_args *pa)
231{
232
233 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY ||
234 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA)
235 return (0);
236
237 switch (PCI_PRODUCT(pa->pa_id)) {
238 case PCI_PRODUCT_INTEL_82810_GC:
239 case PCI_PRODUCT_INTEL_82810_DC100_GC:
240 case PCI_PRODUCT_INTEL_82810E_GC:
241 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH:
242 case PCI_PRODUCT_INTEL_82830MP_IV:
243 case PCI_PRODUCT_INTEL_82845G_IGD:
244 case PCI_PRODUCT_INTEL_82855GM_IGD:
245 case PCI_PRODUCT_INTEL_82865_IGD:
246 case PCI_PRODUCT_INTEL_82915G_IGD:
247 case PCI_PRODUCT_INTEL_82915GM_IGD:
248 case PCI_PRODUCT_INTEL_82945P_IGD:
249 case PCI_PRODUCT_INTEL_82945GM_IGD:
250 case PCI_PRODUCT_INTEL_82945GM_IGD_1:
251 case PCI_PRODUCT_INTEL_82945GME_IGD:
252 case PCI_PRODUCT_INTEL_E7221_IGD:
253 case PCI_PRODUCT_INTEL_82965Q_IGD:
254 case PCI_PRODUCT_INTEL_82965Q_IGD_1:
255 case PCI_PRODUCT_INTEL_82965PM_IGD:
256 case PCI_PRODUCT_INTEL_82965PM_IGD_1:
257 case PCI_PRODUCT_INTEL_82G33_IGD:
258 case PCI_PRODUCT_INTEL_82G33_IGD_1:
259 case PCI_PRODUCT_INTEL_82965G_IGD:
260 case PCI_PRODUCT_INTEL_82965G_IGD_1:
261 case PCI_PRODUCT_INTEL_82965GME_IGD:
262 case PCI_PRODUCT_INTEL_82Q35_IGD:
263 case PCI_PRODUCT_INTEL_82Q35_IGD_1:
264 case PCI_PRODUCT_INTEL_82Q33_IGD:
265 case PCI_PRODUCT_INTEL_82Q33_IGD_1:
266 case PCI_PRODUCT_INTEL_82G35_IGD:
267 case PCI_PRODUCT_INTEL_82G35_IGD_1:
268 case PCI_PRODUCT_INTEL_82946GZ_IGD:
269 case PCI_PRODUCT_INTEL_82GM45_IGD:
270 case PCI_PRODUCT_INTEL_82GM45_IGD_1:
271 case PCI_PRODUCT_INTEL_82IGD_E_IGD:
272 case PCI_PRODUCT_INTEL_82Q45_IGD:
273 case PCI_PRODUCT_INTEL_82G45_IGD:
274 case PCI_PRODUCT_INTEL_82G41_IGD:
275 case PCI_PRODUCT_INTEL_82B43_IGD:
276 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD:
277 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD:
278 case PCI_PRODUCT_INTEL_PINEVIEW_IGD:
279 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD:
280 return (1);
281 }
282
283 return (0);
284}
285
286static int
287agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg)
288{
289 /*
290 * Find the aperture. Don't map it (yet), this would
291 * eat KVA.
292 */
293 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg,
294 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize,
295 &sc->as_apflags) != 0)
296 return ENXIO;
297
298 sc->as_apt = pa->pa_memt;
299
300 return 0;
301}
302
303int
304agp_i810_attach(device_t parent, device_t self, void *aux)
305{
306 struct agp_softc *sc = device_private(self);
307 struct agp_i810_softc *isc;
308 int apbase, mmadr_bar, gtt_bar;
309 int mmadr_type, mmadr_flags;
310 bus_addr_t mmadr;
311 bus_size_t mmadr_size, gtt_off;
312 int error;
313
314 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO);
315 if (isc == NULL) {
316 aprint_error(": can't allocate chipset-specific softc\n");
317 error = ENOMEM;
318 goto fail0;
319 }
320 sc->as_chipc = isc;
321 sc->as_methods = &agp_i810_methods;
322
323 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) {
324#if NAGP_INTEL > 0
325 const struct pci_attach_args *pa = aux;
326
327 switch (PCI_PRODUCT(pa->pa_id)) {
328 case PCI_PRODUCT_INTEL_82840_HB:
329 case PCI_PRODUCT_INTEL_82865_HB:
330 case PCI_PRODUCT_INTEL_82845G_DRAM:
331 case PCI_PRODUCT_INTEL_82815_FULL_HUB:
332 case PCI_PRODUCT_INTEL_82855GM_MCH:
333 free(isc, M_AGP);
334 return agp_intel_attach(parent, self, aux);
335 }
336#endif
337 aprint_error(": can't find internal VGA"
338 " config space\n");
339 error = ENOENT;
340 goto fail1;
341 }
342
343 /* XXXfvdl */
344 sc->as_dmat = isc->vga_pa.pa_dmat;
345
346 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) {
347 case PCI_PRODUCT_INTEL_82810_GC:
348 case PCI_PRODUCT_INTEL_82810_DC100_GC:
349 case PCI_PRODUCT_INTEL_82810E_GC:
350 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH:
351 isc->chiptype = CHIP_I810;
352 aprint_normal(": i810-family chipset\n");
353 break;
354 case PCI_PRODUCT_INTEL_82830MP_IV:
355 case PCI_PRODUCT_INTEL_82845G_IGD:
356 isc->chiptype = CHIP_I830;
357 aprint_normal(": i830-family chipset\n");
358 break;
359 case PCI_PRODUCT_INTEL_82855GM_IGD:
360 case PCI_PRODUCT_INTEL_82865_IGD:
361 isc->chiptype = CHIP_I855;
362 aprint_normal(": i855-family chipset\n");
363 break;
364 case PCI_PRODUCT_INTEL_82915G_IGD:
365 case PCI_PRODUCT_INTEL_82915GM_IGD:
366 case PCI_PRODUCT_INTEL_82945P_IGD:
367 case PCI_PRODUCT_INTEL_82945GM_IGD:
368 case PCI_PRODUCT_INTEL_82945GM_IGD_1:
369 case PCI_PRODUCT_INTEL_82945GME_IGD:
370 case PCI_PRODUCT_INTEL_E7221_IGD:
371 isc->chiptype = CHIP_I915;
372 aprint_normal(": i915-family chipset\n");
373 break;
374 case PCI_PRODUCT_INTEL_82965Q_IGD:
375 case PCI_PRODUCT_INTEL_82965Q_IGD_1:
376 case PCI_PRODUCT_INTEL_82965PM_IGD:
377 case PCI_PRODUCT_INTEL_82965PM_IGD_1:
378 case PCI_PRODUCT_INTEL_82965G_IGD:
379 case PCI_PRODUCT_INTEL_82965G_IGD_1:
380 case PCI_PRODUCT_INTEL_82965GME_IGD:
381 case PCI_PRODUCT_INTEL_82946GZ_IGD:
382 case PCI_PRODUCT_INTEL_82G35_IGD:
383 case PCI_PRODUCT_INTEL_82G35_IGD_1:
384 isc->chiptype = CHIP_I965;
385 aprint_normal(": i965-family chipset\n");
386 break;
387 case PCI_PRODUCT_INTEL_82Q35_IGD:
388 case PCI_PRODUCT_INTEL_82Q35_IGD_1:
389 case PCI_PRODUCT_INTEL_82G33_IGD:
390 case PCI_PRODUCT_INTEL_82G33_IGD_1:
391 case PCI_PRODUCT_INTEL_82Q33_IGD:
392 case PCI_PRODUCT_INTEL_82Q33_IGD_1:
393 isc->chiptype = CHIP_G33;
394 aprint_normal(": G33-family chipset\n");
395 break;
396 case PCI_PRODUCT_INTEL_PINEVIEW_IGD:
397 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD:
398 isc->chiptype = CHIP_PINEVIEW;
399 aprint_normal(": Pineview chipset\n");
400 break;
401 case PCI_PRODUCT_INTEL_82GM45_IGD:
402 case PCI_PRODUCT_INTEL_82GM45_IGD_1:
403 case PCI_PRODUCT_INTEL_82IGD_E_IGD:
404 case PCI_PRODUCT_INTEL_82Q45_IGD:
405 case PCI_PRODUCT_INTEL_82G45_IGD:
406 case PCI_PRODUCT_INTEL_82G41_IGD:
407 case PCI_PRODUCT_INTEL_82B43_IGD:
408 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD:
409 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD:
410 isc->chiptype = CHIP_G4X;
411 aprint_normal(": G4X-family chipset\n");
412 break;
413 }
414 aprint_naive("\n");
415
416 /* Discriminate on the chipset to choose the relevant BARs. */
417 switch (isc->chiptype) {
418 case CHIP_I915:
419 case CHIP_G33:
420 case CHIP_PINEVIEW:
421 apbase = AGP_I915_GMADR;
422 mmadr_bar = AGP_I915_MMADR;
423 gtt_bar = AGP_I915_GTTADR;
424 gtt_off = ~(bus_size_t)0; /* XXXGCC */
425 break;
426 case CHIP_I965:
427 apbase = AGP_I965_GMADR;
428 mmadr_bar = AGP_I965_MMADR;
429 gtt_bar = 0;
430 gtt_off = AGP_I965_GTT;
431 break;
432 case CHIP_G4X:
433 apbase = AGP_I965_GMADR;
434 mmadr_bar = AGP_I965_MMADR;
435 gtt_bar = 0;
436 gtt_off = AGP_G4X_GTT;
437 break;
438 default:
439 apbase = AGP_I810_GMADR;
440 mmadr_bar = AGP_I810_MMADR;
441 gtt_bar = 0;
442 gtt_off = AGP_I810_GTT;
443 break;
444 }
445
446 /*
447 * Ensure the MMIO BAR is, in fact, a memory BAR.
448 *
449 * XXX This is required because we use pa_memt below. It is
450 * not a priori clear to me there is any other reason to
451 * require this.
452 */
453 mmadr_type = pci_mapreg_type(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag,
454 mmadr_bar);
455 if (PCI_MAPREG_TYPE(mmadr_type) != PCI_MAPREG_TYPE_MEM) {
456 aprint_error_dev(self, "non-memory device MMIO registers\n");
457 error = ENXIO;
458 goto fail1;
459 }
460
461 /*
462 * Determine the size of the MMIO registers.
463 *
464 * XXX The size of the MMIO registers we use is statically
465 * determined, as a function of the chipset, by the driver's
466 * implementation.
467 *
468 * On some chipsets, the GTT is part of the MMIO register BAR.
469 * We would like to map the GTT separately, so that we can map
470 * it prefetchable, which we can't do with the MMIO registers.
471 * Consequently, we would especially like to map a fixed size
472 * of MMIO registers, not just whatever size the BAR says.
473 *
474 * However, old drm assumes that the combined GTT/MMIO register
475 * space is a single bus space mapping, so mapping them
476 * separately breaks that. Once we rip out old drm, we can
477 * replace the pci_mapreg_info call by the chipset switch.
478 */
479#if notyet
480 switch (isc->chiptype) {
481 case CHIP_I810:
482 case CHIP_I830:
483 case CHIP_I855:
484 case CHIP_I915:
485 case CHIP_I965:
486 case CHIP_G33:
487 case CHIP_PINEVIEW:
488 case CHIP_G4X:
489 isc->size = 512*1024;
490 break;
491 case CHIP_SANDYBRIDGE:
492 case CHIP_IVYBRIDGE:
493 case CHIP_HASWELL:
494 isc->size = 2*1024*1024;
495 break;
496 }
497#else
498 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag,
499 mmadr_bar, mmadr_type, NULL, &isc->size, NULL))
500 isc->size = 512*1024;
501#endif /* notyet */
502
503 /* Map (or, rather, find the address and size of) the aperture. */
504 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X)
505 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase);
506 else
507 error = agp_map_aperture(&isc->vga_pa, sc, apbase);
508 if (error) {
509 aprint_error_dev(self, "can't map aperture: %d\n", error);
510 goto fail1;
511 }
512
513 /* Map the memory-mapped I/O registers, or the non-GTT part. */
514 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar,
515 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) {
516 aprint_error_dev(self, "can't find MMIO registers\n");
517 error = ENXIO;
518 goto fail1;
519 }
520 if (mmadr_size < isc->size) {
521 aprint_error_dev(self, "MMIO registers too small"
522 ": %"PRIuMAX" < %"PRIuMAX"\n",
523 (uintmax_t)mmadr_size, (uintmax_t)isc->size);
524 error = ENXIO;
525 goto fail1;
526 }
527 isc->bst = isc->vga_pa.pa_memt;
528 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags,
529 &isc->bsh);
530 if (error) {
531 aprint_error_dev(self, "can't map MMIO registers: %d\n",
532 error);
533 error = ENXIO;
534 goto fail1;
535 }
536
537 /* Set up a chipset flush page if necessary. */
538 switch (isc->chiptype) {
539 case CHIP_I915:
540 case CHIP_I965:
541 case CHIP_G33:
542 case CHIP_PINEVIEW:
543 case CHIP_G4X:
544 error = agp_i810_setup_chipset_flush_page(sc);
545 if (error) {
546 aprint_error_dev(self,
547 "can't set up chipset flush page: %d\n", error);
548 goto fail2;
549 }
550 break;
551 }
552
553 /*
554 * XXX horrible hack to allow drm code to use our mapping
555 * of VGA chip registers
556 */
557 agp_i810_vga_regbase = mmadr;
558 agp_i810_vga_regsize = isc->size;
559 agp_i810_vga_bst = isc->bst;
560 agp_i810_vga_bsh = isc->bsh;
561
562 /* Initialize the chipset. */
563 error = agp_i810_init(sc);
564 if (error)
565 goto fail3;
566
567 /* Map the GTT, from either part of the MMIO region or its own BAR. */
568 if (gtt_bar == 0) {
569 isc->gtt_bst = isc->bst;
570 if ((mmadr_size - gtt_off) < isc->gtt_size) {
571 aprint_error_dev(self, "GTTMMADR too small for GTT"
572 ": (%"PRIxMAX" - %"PRIxMAX") < %"PRIxMAX"\n",
573 (uintmax_t)mmadr_size,
574 (uintmax_t)gtt_off,
575 (uintmax_t)isc->gtt_size);
576 error = ENXIO;
577 goto fail4;
578 }
579 /*
580 * Map the GTT separately if we can, so that we can map
581 * it prefetchable, but in early models, there are MMIO
582 * registers before and after the GTT, so we can only
583 * take a subregion.
584 */
585 if (isc->size < gtt_off)
586 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off),
587 isc->gtt_size, mmadr_flags, &isc->gtt_bsh);
588 else
589 error = bus_space_subregion(isc->bst, isc->bsh,
590 gtt_off, isc->gtt_size, &isc->gtt_bsh);
591 if (error) {
592 aprint_error_dev(self, "can't map GTT: %d\n", error);
593 error = ENXIO;
594 goto fail4;
595 }
596 } else {
597 bus_size_t gtt_bar_size;
598 /*
599 * All chipsets with a separate BAR for the GTT, namely
600 * the i915 and G33 families, have 32-bit GTT BARs.
601 *
602 * XXX [citation needed]
603 */
604 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM,
605 0,
606 &isc->gtt_bst, &isc->gtt_bsh, NULL, &gtt_bar_size)) {
607 aprint_error_dev(self, "can't map GTT\n");
608 error = ENXIO;
609 goto fail4;
610 }
611 if (gtt_bar_size != isc->gtt_size) {
612 aprint_error_dev(self,
613 "BAR size %"PRIxMAX
614 " mismatches detected GTT size %"PRIxMAX
615 "; trusting BAR\n",
616 (uintmax_t)gtt_bar_size,
617 (uintmax_t)isc->gtt_size);
618 isc->gtt_size = gtt_bar_size;
619 }
620 }
621
622 /* Power management. (XXX Nothing to save on suspend? Fishy...) */
623 if (!pmf_device_register(self, NULL, agp_i810_resume))
624 aprint_error_dev(self, "can't establish power handler\n");
625
626 /* Match the generic AGP code's autoconf output format. */
627 aprint_normal("%s", device_xname(self));
628
629 /* Success! */
630 return 0;
631
632fail5: __unused
633 pmf_device_deregister(self);
634 if ((gtt_bar != 0) || (isc->size < gtt_off))
635 bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size);
636 isc->gtt_size = 0;
637fail4:
638#if notyet
639 agp_i810_fini(sc);
640#endif
641fail3: switch (isc->chiptype) {
642 case CHIP_I915:
643 case CHIP_I965:
644 case CHIP_G33:
645 case CHIP_PINEVIEW:
646 case CHIP_G4X:
647 agp_i810_teardown_chipset_flush_page(sc);
648 break;
649 }
650fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size);
651 isc->size = 0;
652fail1: free(isc, M_AGP);
653 sc->as_chipc = NULL;
654fail0: agp_generic_detach(sc);
655 KASSERT(error);
656 return error;
657}
658
659/*
660 * Skip pages reserved by the BIOS. Notably, skip 0xa0000-0xfffff,
661 * which includes the video BIOS at 0xc0000-0xdffff which the display
662 * drivers need for video mode detection.
663 *
664 * XXX Is there an MI name for this, or a conventional x86 name? Or
665 * should we really use bus_dma instead?
666 */
667#define PCIBIOS_MIN_MEM 0x100000
668
669static int
670agp_i810_setup_chipset_flush_page(struct agp_softc *sc)
671{
672 struct agp_i810_softc *const isc = sc->as_chipc;
673 const pci_chipset_tag_t pc = sc->as_pc;
674 const pcitag_t tag = sc->as_tag;
675 pcireg_t lo, hi;
676 bus_addr_t addr, minaddr, maxaddr;
677 int error;
678
679 /* We always use memory-mapped I/O. */
680 isc->flush_bst = isc->vga_pa.pa_memt;
681
682 /* No page allocated yet. */
683 isc->flush_addr = 0;
684
685 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */
686 if (isc->chiptype == CHIP_I915) {
687 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR);
688 minaddr = PCIBIOS_MIN_MEM;
689 maxaddr = UINT32_MAX;
690 } else {
691 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4);
692 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR);
693 /*
694 * Convert to uint64_t, rather than bus_addr_t which
695 * may be 32-bit, to avoid undefined behaviour with a
696 * too-wide shift. Since the BIOS doesn't know whether
697 * the OS will run 64-bit or with PAE, it ought to
698 * configure at most a 32-bit physical address, so
699 * let's print a warning in case that happens.
700 */
701 addr = ((uint64_t)hi << 32) | lo;
702 if (hi) {
703 aprint_error_dev(sc->as_dev,
704 "BIOS configured >32-bit flush page address"
705 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo);
706#if __i386__ && !PAE
707 return EIO;
708#endif
709 }
710 minaddr = PCIBIOS_MIN_MEM;
711 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0);
712 }
713
714 /* Allocate or map a pre-allocated a page for it. */
715 if (ISSET(addr, 1)) {
716 /* BIOS allocated it for us. Use that. */
717 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0,
718 &isc->flush_bsh);
719 if (error)
720 return error;
721 } else {
722 /* None allocated. Allocate one. */
723 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr,
724 PAGE_SIZE, PAGE_SIZE, 0, 0,
725 &isc->flush_addr, &isc->flush_bsh);
726 if (error)
727 return error;
728 KASSERT(isc->flush_addr != 0);
729 /* Write it into the PCI config register. */
730 addr = isc->flush_addr | 1;
731 if (isc->chiptype == CHIP_I915) {
732 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr);
733 } else {
734 hi = __SHIFTOUT(addr, __BITS(63, 32));
735 lo = __SHIFTOUT(addr, __BITS(31, 0));
736 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi);
737 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo);
738 }
739 }
740
741 /* Success! */
742 return 0;
743}
744
745static void
746agp_i810_teardown_chipset_flush_page(struct agp_softc *sc)
747{
748 struct agp_i810_softc *const isc = sc->as_chipc;
749
750 if (isc->flush_addr) {
751 /* If we allocated a page, clear it. */
752 if (isc->chiptype == CHIP_I915) {
753 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR,
754 0);
755 } else {
756 pci_conf_write(sc->as_pc, sc->as_tag,
757 AGP_I965_IFPADDR, 0);
758 pci_conf_write(sc->as_pc, sc->as_tag,
759 AGP_I965_IFPADDR + 4, 0);
760 }
761 isc->flush_addr = 0;
762 bus_space_free(isc->flush_bst, isc->flush_bsh, PAGE_SIZE);
763 } else {
764 /* Otherwise, just unmap the pre-allocated page. */
765 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE);
766 }
767}
768
769/*
770 * XXX horrible hack to allow drm code to use our mapping
771 * of VGA chip registers
772 */
773int
774agp_i810_borrow(bus_addr_t base, bus_size_t size, bus_space_handle_t *hdlp)
775{
776
777 if (agp_i810_vga_regbase == 0)
778 return 0;
779 if (base < agp_i810_vga_regbase)
780 return 0;
781 if (agp_i810_vga_regsize < size)
782 return 0;
783 if ((base - agp_i810_vga_regbase) > (agp_i810_vga_regsize - size))
784 return 0;
785 if (bus_space_subregion(agp_i810_vga_bst, agp_i810_vga_bsh,
786 (base - agp_i810_vga_regbase), (agp_i810_vga_regsize - size),
787 hdlp))
788 return 0;
789 return 1;
790}
791
792static int
793agp_i810_init(struct agp_softc *sc)
794{
795 struct agp_i810_softc *isc;
796 int error;
797
798 isc = sc->as_chipc;
799
800 if (isc->chiptype == CHIP_I810) {
801 struct agp_gatt *gatt;
802 void *virtual;
803 int dummyseg;
804
805 /* Some i810s have on-chip memory called dcache */
806 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED)
807 isc->dcache_size = 4 * 1024 * 1024;
808 else
809 isc->dcache_size = 0;
810
811 /* According to the specs the gatt on the i810 must be 64k */
812 isc->gtt_size = 64 * 1024;
813 gatt = malloc(sizeof(*gatt), M_AGP, M_NOWAIT);
814 if (gatt == NULL) {
815 aprint_error_dev(sc->as_dev,
816 "can't malloc GATT record\n");
817 error = ENOMEM;
818 goto fail0;
819 }
820 gatt->ag_entries = isc->gtt_size / sizeof(uint32_t);
821 error = agp_alloc_dmamem(sc->as_dmat, isc->gtt_size,
822 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical,
823 &gatt->ag_dmaseg, 1, &dummyseg);
824 if (error) {
825 aprint_error_dev(sc->as_dev,
826 "can't allocate memory for GTT: %d\n", error);
827 free(gatt, M_AGP);
828 goto fail0;
829 }
830
831 gatt->ag_virtual = (uint32_t *)virtual;
832 gatt->ag_size = gatt->ag_entries * sizeof(uint32_t);
833 memset(gatt->ag_virtual, 0, gatt->ag_size);
834 agp_flush_cache();
835
836 /* Install the GATT. */
837 isc->pgtblctl = gatt->ag_physical | 1;
838 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl);
839 isc->gatt = gatt;
840 } else if (isc->chiptype == CHIP_I830) {
841 /* The i830 automatically initializes the 128k gatt on boot. */
842 /* XXX [citation needed] */
843 pcireg_t reg;
844 u_int16_t gcc1;
845
846 isc->gtt_size = 128 * 1024;
847
848 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0);
849 gcc1 = (u_int16_t)(reg >> 16);
850 switch (gcc1 & AGP_I830_GCC1_GMS) {
851 case AGP_I830_GCC1_GMS_STOLEN_512:
852 isc->stolen = (512 - 132) * 1024 / 4096;
853 break;
854 case AGP_I830_GCC1_GMS_STOLEN_1024:
855 isc->stolen = (1024 - 132) * 1024 / 4096;
856 break;
857 case AGP_I830_GCC1_GMS_STOLEN_8192:
858 isc->stolen = (8192 - 132) * 1024 / 4096;
859 break;
860 default:
861 isc->stolen = 0;
862 aprint_error_dev(sc->as_dev,
863 "unknown memory configuration, disabling\n");
864 error = ENXIO;
865 goto fail0;
866 }
867
868 if (isc->stolen > 0) {
869 aprint_normal_dev(sc->as_dev,
870 "detected %dk stolen memory\n",
871 isc->stolen * 4);
872 }
873
874 /* GATT address is already in there, make sure it's enabled */
875 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL);
876 isc->pgtblctl |= 1;
877 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl);
878 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 ||
879 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 ||
880 isc->chiptype == CHIP_PINEVIEW ||
881 isc->chiptype == CHIP_G4X) {
882 pcireg_t reg;
883 u_int32_t gtt_size, stolen; /* XXX kilobytes */
884 u_int16_t gcc1;
885
886 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1);
887 gcc1 = (u_int16_t)(reg >> 16);
888
889 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL);
890
891 /* Stolen memory is set up at the beginning of the aperture by
892 * the BIOS, consisting of the GATT followed by 4kb for the
893 * BIOS display.
894 */
895 switch (isc->chiptype) {
896 case CHIP_I855:
897 gtt_size = 128;
898 break;
899 case CHIP_I915:
900 gtt_size = 256;
901 break;
902 case CHIP_I965:
903 switch (isc->pgtblctl & AGP_I810_PGTBL_SIZE_MASK) {
904 case AGP_I810_PGTBL_SIZE_128KB:
905 case AGP_I810_PGTBL_SIZE_512KB:
906 gtt_size = 512;
907 break;
908 case AGP_I965_PGTBL_SIZE_1MB:
909 gtt_size = 1024;
910 break;
911 case AGP_I965_PGTBL_SIZE_2MB:
912 gtt_size = 2048;
913 break;
914 case AGP_I965_PGTBL_SIZE_1_5MB:
915 gtt_size = 1024 + 512;
916 break;
917 default:
918 aprint_error_dev(sc->as_dev,
919 "bad PGTBL size\n");
920 error = ENXIO;
921 goto fail0;
922 }
923 break;
924 case CHIP_G33:
925 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) {
926 case AGP_G33_PGTBL_SIZE_1M:
927 gtt_size = 1024;
928 break;
929 case AGP_G33_PGTBL_SIZE_2M:
930 gtt_size = 2048;
931 break;
932 default:
933 aprint_error_dev(sc->as_dev,
934 "bad PGTBL size\n");
935 error = ENXIO;
936 goto fail0;
937 }
938 break;
939 case CHIP_PINEVIEW:
940 switch (gcc1 & AGP_PINEVIEW_PGTBL_SIZE_MASK) {
941 case AGP_PINEVIEW_PGTBL_SIZE_1M:
942 gtt_size = 1024;
943 break;
944 default:
945 aprint_error_dev(sc->as_dev,
946 "bad PGTBL size\n");
947 error = ENXIO;
948 goto fail0;
949 }
950 break;
951 case CHIP_G4X:
952 switch (isc->pgtblctl & AGP_G4X_PGTBL_SIZE_MASK) {
953 case AGP_G4X_PGTBL_SIZE_512K:
954 gtt_size = 512;
955 break;
956 case AGP_G4X_PGTBL_SIZE_256K:
957 gtt_size = 256;
958 break;
959 case AGP_G4X_PGTBL_SIZE_128K:
960 gtt_size = 128;
961 break;
962 case AGP_G4X_PGTBL_SIZE_1M:
963 gtt_size = 1*1024;
964 break;
965 case AGP_G4X_PGTBL_SIZE_2M:
966 gtt_size = 2*1024;
967 break;
968 case AGP_G4X_PGTBL_SIZE_1_5M:
969 gtt_size = 1*1024 + 512;
970 break;
971 default:
972 aprint_error_dev(sc->as_dev,
973 "bad PGTBL size\n");
974 error = ENXIO;
975 goto fail0;
976 }
977 break;
978 default:
979 panic("impossible chiptype %d", isc->chiptype);
980 }
981
982 /*
983 * XXX If I'm reading the datasheets right, this stolen
984 * memory detection logic is totally wrong.
985 */
986 switch (gcc1 & AGP_I855_GCC1_GMS) {
987 case AGP_I855_GCC1_GMS_STOLEN_1M:
988 stolen = 1024;
989 break;
990 case AGP_I855_GCC1_GMS_STOLEN_4M:
991 stolen = 4 * 1024;
992 break;
993 case AGP_I855_GCC1_GMS_STOLEN_8M:
994 stolen = 8 * 1024;
995 break;
996 case AGP_I855_GCC1_GMS_STOLEN_16M:
997 stolen = 16 * 1024;
998 break;
999 case AGP_I855_GCC1_GMS_STOLEN_32M:
1000 stolen = 32 * 1024;
1001 break;
1002 case AGP_I915_GCC1_GMS_STOLEN_48M:
1003 stolen = 48 * 1024;
1004 break;
1005 case AGP_I915_GCC1_GMS_STOLEN_64M:
1006 stolen = 64 * 1024;
1007 break;
1008 case AGP_G33_GCC1_GMS_STOLEN_128M:
1009 stolen = 128 * 1024;
1010 break;
1011 case AGP_G33_GCC1_GMS_STOLEN_256M:
1012 stolen = 256 * 1024;
1013 break;
1014 case AGP_G4X_GCC1_GMS_STOLEN_96M:
1015 stolen = 96 * 1024;
1016 break;
1017 case AGP_G4X_GCC1_GMS_STOLEN_160M:
1018 stolen = 160 * 1024;
1019 break;
1020 case AGP_G4X_GCC1_GMS_STOLEN_224M:
1021 stolen = 224 * 1024;
1022 break;
1023 case AGP_G4X_GCC1_GMS_STOLEN_352M:
1024 stolen = 352 * 1024;
1025 break;
1026 default:
1027 aprint_error_dev(sc->as_dev,
1028 "unknown memory configuration, disabling\n");
1029 error = ENXIO;
1030 goto fail0;
1031 }
1032
1033 switch (gcc1 & AGP_I855_GCC1_GMS) {
1034 case AGP_I915_GCC1_GMS_STOLEN_48M:
1035 case AGP_I915_GCC1_GMS_STOLEN_64M:
1036 if (isc->chiptype != CHIP_I915 &&
1037 isc->chiptype != CHIP_I965 &&
1038 isc->chiptype != CHIP_G33 &&
1039 isc->chiptype != CHIP_PINEVIEW &&
1040 isc->chiptype != CHIP_G4X)
1041 stolen = 0;
1042 break;
1043 case AGP_G33_GCC1_GMS_STOLEN_128M:
1044 case AGP_G33_GCC1_GMS_STOLEN_256M:
1045 if (isc->chiptype != CHIP_I965 &&
1046 isc->chiptype != CHIP_G33 &&
1047 isc->chiptype != CHIP_PINEVIEW &&
1048 isc->chiptype != CHIP_G4X)
1049 stolen = 0;
1050 break;
1051 case AGP_G4X_GCC1_GMS_STOLEN_96M:
1052 case AGP_G4X_GCC1_GMS_STOLEN_160M:
1053 case AGP_G4X_GCC1_GMS_STOLEN_224M:
1054 case AGP_G4X_GCC1_GMS_STOLEN_352M:
1055 if (isc->chiptype != CHIP_I965 &&
1056 isc->chiptype != CHIP_G4X)
1057 stolen = 0;
1058 break;
1059 }
1060
1061 isc->gtt_size = gtt_size * 1024;
1062
1063 /* BIOS space */
1064 /* XXX [citation needed] */
1065 gtt_size += 4;
1066
1067 /* XXX [citation needed] for this subtraction */
1068 isc->stolen = (stolen - gtt_size) * 1024 / 4096;
1069
1070 if (isc->stolen > 0) {
1071 aprint_normal_dev(sc->as_dev,
1072 "detected %dk stolen memory\n",
1073 isc->stolen * 4);
1074 }
1075
1076 /* GATT address is already in there, make sure it's enabled */
1077 isc->pgtblctl |= 1;
1078 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl);
1079 }
1080
1081 /*
1082 * Make sure the chipset can see everything.
1083 */
1084 agp_flush_cache();
1085
1086 /*
1087 * Publish what we found for kludgey drivers (I'm looking at
1088 * you, drm).
1089 */
1090 if (agp_i810_sc == NULL)
1091 agp_i810_sc = sc;
1092 else
1093 aprint_error_dev(sc->as_dev, "agp already attached\n");
1094
1095 /* Success! */
1096 return 0;
1097
1098fail0: KASSERT(error);
1099 return error;
1100}
1101
1102#if 0
1103static int
1104agp_i810_detach(struct agp_softc *sc)
1105{
1106 int error;
1107 struct agp_i810_softc *isc = sc->as_chipc;
1108
1109 error = agp_generic_detach(sc);
1110 if (error)
1111 return error;
1112
1113 switch (isc->chiptype) {
1114 case CHIP_I915:
1115 case CHIP_I965:
1116 case CHIP_G33:
1117 case CHIP_PINEVIEW:
1118 case CHIP_G4X:
1119 agp_i810_teardown_chipset_flush_page(sc);
1120 break;
1121 }
1122
1123 /* Clear the GATT base. */
1124 if (sc->chiptype == CHIP_I810) {
1125 WRITE4(AGP_I810_PGTBL_CTL, 0);
1126 } else {
1127 unsigned int pgtblctl;
1128 pgtblctl = READ4(AGP_I810_PGTBL_CTL);
1129 pgtblctl &= ~1;
1130 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
1131 }
1132
1133 if (sc->chiptype == CHIP_I810) {
1134 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap,
1135 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1);
1136 free(isc->gatt, M_AGP);
1137 }
1138
1139 return 0;
1140}
1141#endif
1142
1143static u_int32_t
1144agp_i810_get_aperture(struct agp_softc *sc)
1145{
1146 struct agp_i810_softc *isc = sc->as_chipc;
1147 pcireg_t reg;
1148 u_int32_t size;
1149 u_int16_t miscc, gcc1;
1150
1151 size = 0;
1152
1153 switch (isc->chiptype) {
1154 case CHIP_I810:
1155 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM);
1156 miscc = (u_int16_t)(reg >> 16);
1157 if ((miscc & AGP_I810_MISCC_WINSIZE) ==
1158 AGP_I810_MISCC_WINSIZE_32)
1159 size = 32 * 1024 * 1024;
1160 else
1161 size = 64 * 1024 * 1024;
1162 break;
1163 case CHIP_I830:
1164 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0);
1165 gcc1 = (u_int16_t)(reg >> 16);
1166 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
1167 size = 64 * 1024 * 1024;
1168 else
1169 size = 128 * 1024 * 1024;
1170 break;
1171 case CHIP_I855:
1172 size = 128 * 1024 * 1024;
1173 break;
1174 case CHIP_I915:
1175 case CHIP_G33:
1176 case CHIP_PINEVIEW:
1177 case CHIP_G4X:
1178 size = sc->as_apsize;
1179 break;
1180 case CHIP_I965:
1181 size = 512 * 1024 * 1024;
1182 break;
1183 default:
1184 aprint_error(": Unknown chipset\n");
1185 }
1186
1187 return size;
1188}
1189
1190static int
1191agp_i810_set_aperture(struct agp_softc *sc __unused,
1192 uint32_t aperture __unused)
1193{
1194
1195 return ENOSYS;
1196}
1197
1198static int
1199agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
1200{
1201 struct agp_i810_softc *isc = sc->as_chipc;
1202
1203 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) {
1204 DPRINTF(sc, "failed"
1205 ": offset 0x%"PRIxMAX", shift %u, entries %"PRIuMAX"\n",
1206 (uintmax_t)offset,
1207 (unsigned)AGP_PAGE_SHIFT,
1208 (uintmax_t)isc->gtt_size/4);
1209 return EINVAL;
1210 }
1211
1212 if (isc->chiptype != CHIP_I810) {
1213 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) {
1214 DPRINTF(sc, "trying to bind into stolen memory\n");
1215 return EINVAL;
1216 }
1217 }
1218
1219 return agp_i810_write_gtt_entry(isc, offset, physical,
1220 AGP_I810_GTT_VALID);
1221}
1222
1223static int
1224agp_i810_unbind_page(struct agp_softc *sc, off_t offset)
1225{
1226 struct agp_i810_softc *isc = sc->as_chipc;
1227
1228 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT))
1229 return EINVAL;
1230
1231 if (isc->chiptype != CHIP_I810 ) {
1232 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) {
1233 DPRINTF(sc, "trying to unbind from stolen memory\n");
1234 return EINVAL;
1235 }
1236 }
1237
1238 return agp_i810_write_gtt_entry(isc, offset, 0, 0);
1239}
1240
1241/*
1242 * Writing via memory mapped registers already flushes all TLBs.
1243 */
1244static void
1245agp_i810_flush_tlb(struct agp_softc *sc)
1246{
1247}
1248
1249static int
1250agp_i810_enable(struct agp_softc *sc, u_int32_t mode)
1251{
1252
1253 return 0;
1254}
1255
1256#define AGP_I810_MEMTYPE_MAIN 0
1257#define AGP_I810_MEMTYPE_DCACHE 1
1258#define AGP_I810_MEMTYPE_HWCURSOR 2
1259
1260static struct agp_memory *
1261agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size)
1262{
1263 struct agp_i810_softc *isc = sc->as_chipc;
1264 struct agp_memory *mem;
1265 int error;
1266
1267 DPRINTF(sc, "AGP: alloc(%d, 0x%"PRIxMAX")\n", type, (uintmax_t)size);
1268
1269 if (size <= 0)
1270 return NULL;
1271 if ((size & (AGP_PAGE_SIZE - 1)) != 0)
1272 return NULL;
1273 KASSERT(sc->as_allocated <= sc->as_maxmem);
1274 if (size > (sc->as_maxmem - sc->as_allocated))
1275 return NULL;
1276 if (size > ((isc->gtt_size/4) << AGP_PAGE_SHIFT))
1277 return NULL;
1278
1279 switch (type) {
1280 case AGP_I810_MEMTYPE_MAIN:
1281 break;
1282 case AGP_I810_MEMTYPE_DCACHE:
1283 if (isc->chiptype != CHIP_I810)
1284 return NULL;
1285 if (size != isc->dcache_size)
1286 return NULL;
1287 break;
1288 case AGP_I810_MEMTYPE_HWCURSOR:
1289 if ((size != AGP_PAGE_SIZE) &&
1290 (size != AGP_PAGE_SIZE*4))
1291 return NULL;
1292 break;
1293 default:
1294 return NULL;
1295 }
1296
1297 mem = malloc(sizeof(*mem), M_AGP, M_WAITOK|M_ZERO);
1298 if (mem == NULL)
1299 goto fail0;
1300 mem->am_id = sc->as_nextid++;
1301 mem->am_size = size;
1302 mem->am_type = type;
1303
1304 switch (type) {
1305 case AGP_I810_MEMTYPE_MAIN:
1306 error = bus_dmamap_create(sc->as_dmat, size,
1307 (size >> AGP_PAGE_SHIFT) + 1, size, 0, BUS_DMA_WAITOK,
1308 &mem->am_dmamap);
1309 if (error)
1310 goto fail1;
1311 break;
1312 case AGP_I810_MEMTYPE_DCACHE:
1313 break;
1314 case AGP_I810_MEMTYPE_HWCURSOR:
1315 mem->am_dmaseg = malloc(sizeof(*mem->am_dmaseg), M_AGP,
1316 M_WAITOK);
1317 error = agp_alloc_dmamem(sc->as_dmat, size, 0, &mem->am_dmamap,
1318 &mem->am_virtual, &mem->am_physical, mem->am_dmaseg, 1,
1319 &mem->am_nseg);
1320 if (error) {
1321 free(mem->am_dmaseg, M_AGP);
1322 goto fail1;
1323 }
1324 (void)memset(mem->am_virtual, 0, size);
1325 break;
1326 default:
1327 panic("invalid agp memory type: %d", type);
1328 }
1329
1330 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link);
1331 sc->as_allocated += size;
1332
1333 return mem;
1334
1335fail1: free(mem, M_AGP);
1336fail0: return NULL;
1337}
1338
1339static int
1340agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem)
1341{
1342
1343 if (mem->am_is_bound)
1344 return EBUSY;
1345
1346 switch (mem->am_type) {
1347 case AGP_I810_MEMTYPE_MAIN:
1348 bus_dmamap_destroy(sc->as_dmat, mem->am_dmamap);
1349 break;
1350 case AGP_I810_MEMTYPE_DCACHE:
1351 break;
1352 case AGP_I810_MEMTYPE_HWCURSOR:
1353 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap,
1354 mem->am_virtual, mem->am_dmaseg, mem->am_nseg);
1355 free(mem->am_dmaseg, M_AGP);
1356 break;
1357 default:
1358 panic("invalid agp i810 memory type: %d", mem->am_type);
1359 }
1360
1361 sc->as_allocated -= mem->am_size;
1362 TAILQ_REMOVE(&sc->as_memory, mem, am_link);
1363 free(mem, M_AGP);
1364
1365 return 0;
1366}
1367
1368static int
1369agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem,
1370 off_t offset)
1371{
1372 struct agp_i810_softc *isc = sc->as_chipc;
1373 uint32_t pgtblctl;
1374 int error;
1375
1376 if (mem->am_is_bound)
1377 return EINVAL;
1378
1379 /*
1380 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the
1381 * X server for mysterious reasons which leads to crashes if we write
1382 * to the GTT through the MMIO window.
1383 * Until the issue is solved, simply restore it.
1384 */
1385 pgtblctl = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL);
1386 if (pgtblctl != isc->pgtblctl) {
1387 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%"PRIx32
1388 " - fixing\n", pgtblctl);
1389 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL,
1390 isc->pgtblctl);
1391 }
1392
1393 switch (mem->am_type) {
1394 case AGP_I810_MEMTYPE_MAIN:
1395 return agp_generic_bind_memory_bounded(sc, mem, offset,
1396 0, (isc->gtt_size/4) << AGP_PAGE_SHIFT);
1397 case AGP_I810_MEMTYPE_DCACHE:
1398 error = agp_i810_bind_memory_dcache(sc, mem, offset);
1399 break;
1400 case AGP_I810_MEMTYPE_HWCURSOR:
1401 error = agp_i810_bind_memory_hwcursor(sc, mem, offset);
1402 break;
1403 default:
1404 panic("invalid agp i810 memory type: %d", mem->am_type);
1405 }
1406 if (error)
1407 return error;
1408
1409 /* Success! */
1410 mem->am_is_bound = 1;
1411 return 0;
1412}
1413
1414static int
1415agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem,
1416 off_t offset)
1417{
1418 struct agp_i810_softc *const isc __diagused = sc->as_chipc;
1419 uint32_t i, j;
1420 int error;
1421
1422 KASSERT(isc->chiptype == CHIP_I810);
1423
1424 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0);
1425 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1426 error = agp_i810_write_gtt_entry(isc, offset + i,
1427 i, AGP_I810_GTT_VALID | AGP_I810_GTT_I810_DCACHE);
1428 if (error)
1429 goto fail0;
1430 }
1431
1432 /* Success! */
1433 mem->am_offset = offset;
1434 return 0;
1435
1436fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE)
1437 (void)agp_i810_unbind_page(sc, offset + j);
1438 return error;
1439}
1440
1441static int
1442agp_i810_bind_memory_hwcursor(struct agp_softc *sc, struct agp_memory *mem,
1443 off_t offset)
1444{
1445 const bus_addr_t pa = mem->am_physical;
1446 uint32_t i, j;
1447 int error;
1448
1449 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0);
1450 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1451 error = agp_i810_bind_page(sc, offset + i, pa + i);
1452 if (error)
1453 goto fail0;
1454 }
1455
1456 /* Success! */
1457 mem->am_offset = offset;
1458 return 0;
1459
1460fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE)
1461 (void)agp_i810_unbind_page(sc, offset + j);
1462 return error;
1463}
1464
1465static int
1466agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem)
1467{
1468 struct agp_i810_softc *isc __diagused = sc->as_chipc;
1469 u_int32_t i;
1470
1471 if (!mem->am_is_bound)
1472 return EINVAL;
1473
1474 switch (mem->am_type) {
1475 case AGP_I810_MEMTYPE_MAIN:
1476 return agp_generic_unbind_memory(sc, mem);
1477 case AGP_I810_MEMTYPE_DCACHE:
1478 KASSERT(isc->chiptype == CHIP_I810);
1479 /* FALLTHROUGH */
1480 case AGP_I810_MEMTYPE_HWCURSOR:
1481 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
1482 (void)agp_i810_unbind_page(sc, mem->am_offset + i);
1483 mem->am_offset = 0;
1484 break;
1485 default:
1486 panic("invalid agp i810 memory type: %d", mem->am_type);
1487 }
1488
1489 mem->am_is_bound = 0;
1490 return 0;
1491}
1492
1493static bool
1494agp_i810_resume(device_t dv, const pmf_qual_t *qual)
1495{
1496 struct agp_softc *sc = device_private(dv);
1497 struct agp_i810_softc *isc = sc->as_chipc;
1498
1499 /*
1500 * XXX Nothing uses this! Save on suspend, restore on resume?
1501 */
1502 isc->pgtblctl_resume_hack = READ4(AGP_I810_PGTBL_CTL);
1503 agp_flush_cache();
1504
1505 return true;
1506}
1507