1 | /* $NetBSD: cissreg.h,v 1.5 2016/06/17 17:05:04 christos Exp $ */ |
2 | /* $OpenBSD: cissreg.h,v 1.11 2010/06/03 01:02:13 dlg Exp $ */ |
3 | |
4 | /* |
5 | * Copyright (c) 2005,2006 Michael Shalayeff |
6 | * All rights reserved. |
7 | * |
8 | * Permission to use, copy, modify, and distribute this software for any |
9 | * purpose with or without fee is hereby granted, provided that the above |
10 | * copyright notice and this permission notice appear in all copies. |
11 | * |
12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
16 | * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN |
17 | * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT |
18 | * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
19 | */ |
20 | |
21 | #define CISS_BIGBIT 0x80 /* texas radio and the big beat! */ |
22 | |
23 | #define CISS_IDB 0x20 |
24 | #define CISS_IDB_CFG 0x01 |
25 | #define CISS_ISR 0x30 |
26 | #define CISS_IMR 0x34 |
27 | #define CISS_INTR_OPQ_SA5 (1<<3) |
28 | #define CISS_INTR_OPQ_SA5B (1<<2) |
29 | #define CISS_INTR_OPQ (CISS_INTR_OPQ_SA5|CISS_INTR_OPQ_SA5B) |
30 | #define CISS_INTR_MSI (1<<0) |
31 | #define CISS_INQ 0x40 |
32 | #define CISS_OUTQ 0x44 |
33 | #define CISS_CFG_BAR 0xb4 |
34 | #define CISS_CFG_OFF 0xb8 |
35 | |
36 | /* 64bit FIFO mode input/output post queues */ |
37 | #define CISS_INQ64_LO 0xc0 |
38 | #define CISS_INQ64_HI 0xc4 |
39 | #define CISS_OUTQ64_LO 0xc8 |
40 | #define CISS_OUTQ64_HI 0xcc |
41 | |
42 | #define CISS_DRVMAP_SIZE (128 / 8) |
43 | |
44 | #define CISS_CMD_CTRL_GET 0x26 |
45 | #define CISS_CMD_CTRL_SET 0x27 |
46 | /* sub-commands for GET/SET */ |
47 | #define CISS_CMS_CTRL_LDID 0x10 |
48 | #define CISS_CMS_CTRL_CTRL 0x11 |
49 | #define CISS_CMS_CTRL_LDSTAT 0x12 |
50 | #define CISS_CMS_CTRL_PDID 0x15 |
51 | #define CISS_CMS_CTRL_PDBLINK 0x16 |
52 | #define CISS_CMS_CTRL_PDBLSENS 0x17 |
53 | #define CISS_CMS_CTRL_LDIDEXT 0x18 |
54 | #define CISS_CMS_CTRL_REDSTAT 0x82 |
55 | #define CISS_CMS_CTRL_FLUSH 0xc2 |
56 | #define CISS_CMS_CTRL_ACCEPT 0xe0 |
57 | |
58 | #define CISS_CMD_READ 0xc0 |
59 | #define CISS_CMD_READ_EVENT 0xd0 |
60 | #define CISS_EVENT_RECENT 0x08 /* ignore previous events */ |
61 | #define CISS_EVENT_RSTOLD 0x04 /* start w/ the oldest one */ |
62 | #define CISS_EVENT_ORDER 0x02 /* keep the order */ |
63 | #define CISS_EVENT_SYNC 0x01 /* sync mode: wait till new come */ |
64 | #define CISS_CMD_LDMAP 0xc2 |
65 | #define CISS_CMD_PDMAP 0xc3 |
66 | |
67 | #define ciss_bitset(d, v) ((v)[(d) >> 3] & (1 << ((d) & 7))) |
68 | |
69 | struct ciss_softc; |
70 | |
71 | struct ciss_config { |
72 | u_int32_t signature; |
73 | #define CISS_SIGNATURE (*(const u_int32_t *)"CISS") |
74 | u_int32_t version; |
75 | u_int32_t methods; |
76 | #define CISS_METH_READY 0x00000001 /* indicate to accept commands */ |
77 | #define CISS_METH_SIMPL 0x00000002 /* simple mode */ |
78 | #define CISS_METH_PERF 0x00000004 /* performant mode */ |
79 | #define CISS_METH_EMQ 0x00000008 /* MEMQ method */ |
80 | #define CISS_METH_BIT63 0x08000000 /* address bit 63 is valid */ |
81 | #define CISS_METH_FIFO64_RRO 0x10000000 /* 64bit FIFO reverse read order */ |
82 | #define CISS_METH_SHORT_TAG 0x20000000 /* short 4 byte tag support */ |
83 | #define CISS_METH_MSIX 0x40000000 /* directed MSI-X support */ |
84 | #define CISS_METH_FIFO64 0x80000000 /* 64bit FIFO support */ |
85 | u_int32_t amethod; |
86 | u_int32_t rmethod; |
87 | u_int32_t paddr_lim; |
88 | u_int32_t int_delay; |
89 | u_int32_t int_count; |
90 | u_int32_t maxcmd; |
91 | u_int32_t scsibus; |
92 | #define CISS_BUS_U2 0x0001 |
93 | #define CISS_BUS_U3 0x0002 |
94 | #define CISS_BUS_FC1 0x0100 |
95 | #define CISS_BUS_FC2 0x0200 |
96 | u_int32_t troff; |
97 | u_int8_t hostname[16]; |
98 | u_int32_t heartbeat; |
99 | u_int32_t driverf; |
100 | #define CISS_DRV_UATT 0x0001 |
101 | #define CISS_DRV_QINI 0x0002 |
102 | #define CISS_DRV_LCKINT 0x0004 |
103 | #define CISS_DRV_QTAGS 0x0008 |
104 | #define CISS_DRV_ALPHA 0x0010 |
105 | #define CISS_DRV_LUNS 0x0020 |
106 | #define CISS_DRV_MSGRQ 0x0080 |
107 | #define CISS_DRV_DBRD 0x0100 |
108 | #define CISS_DRV_PRF 0x0200 |
109 | u_int32_t maxsg; |
110 | } __packed; |
111 | |
112 | struct ciss_inquiry { |
113 | u_int8_t numld; |
114 | u_int8_t sign[4]; |
115 | u_int8_t fw_running[4]; |
116 | u_int8_t fw_stored[4]; |
117 | u_int8_t hw_rev; |
118 | u_int8_t resv0[12]; |
119 | u_int16_t pci_vendor; |
120 | u_int16_t pci_product; |
121 | u_int8_t resv1[10]; |
122 | u_int8_t market_rev; |
123 | u_int8_t flags; |
124 | #define CISS_INQ_WIDE 0x08 |
125 | #define CISS_INQ_BIGMAP 0x80 |
126 | #define CISS_INQ_BITS "\020\04WIDE\010BIGMAP" |
127 | u_int8_t resv2[2]; |
128 | u_int8_t nscsi_bus; |
129 | u_int8_t resv3[4]; |
130 | u_int8_t clk[4]; /* unaligned dumbness */ |
131 | u_int8_t buswidth; |
132 | u_int8_t disks[CISS_DRVMAP_SIZE]; |
133 | u_int8_t extdisks[CISS_DRVMAP_SIZE]; |
134 | u_int8_t nondisks[CISS_DRVMAP_SIZE]; |
135 | } __packed; |
136 | |
137 | struct ciss_ldmap { |
138 | u_int32_t size; |
139 | u_int32_t resv; |
140 | struct { |
141 | u_int32_t tgt; |
142 | u_int32_t tgt2; |
143 | } map[1]; |
144 | } __packed; |
145 | |
146 | struct ciss_flush { |
147 | u_int16_t flush; |
148 | #define CISS_FLUSH_ENABLE 0 |
149 | #define CISS_FLUSH_DISABLE 1 |
150 | u_int16_t resv[255]; |
151 | } __packed; |
152 | |
153 | struct ciss_blink { |
154 | u_int32_t duration; /* x100ms */ |
155 | u_int32_t elapsed; /* only for sense */ |
156 | u_int8_t pdtab[256]; |
157 | #define CISS_BLINK_ALL 1 |
158 | #define CISS_BLINK_TIMED 2 |
159 | u_int8_t res[248]; |
160 | } __packed; |
161 | |
162 | struct ciss_ldid { |
163 | u_int16_t blksize; |
164 | u_int16_t nblocks[2]; /* UNALIGNED! */ |
165 | u_int8_t params[16]; |
166 | u_int8_t type; |
167 | #define CISS_LD_RAID0 0 |
168 | #define CISS_LD_RAID4 1 |
169 | #define CISS_LD_RAID1 2 |
170 | #define CISS_LD_RAID5 3 |
171 | #define CISS_LD_RAID51 4 |
172 | #define CISS_LD_RAIDADG 5 |
173 | u_int8_t res0; |
174 | u_int8_t bios_dis; |
175 | u_int8_t res1; |
176 | u_int32_t id; |
177 | u_int8_t label[64]; |
178 | u_int64_t nbigblocks; |
179 | u_int8_t res2[410]; |
180 | } __packed; |
181 | |
182 | struct ciss_ldstat { |
183 | u_int8_t stat; |
184 | #define CISS_LD_OK 0 |
185 | #define CISS_LD_FAILED 1 |
186 | #define CISS_LD_UNCONF 2 |
187 | #define CISS_LD_DEGRAD 3 |
188 | #define CISS_LD_RBLDRD 4 /* ready for rebuild */ |
189 | #define CISS_LD_REBLD 5 |
190 | #define CISS_LD_PDINV 6 /* wrong phys drive replaced */ |
191 | #define CISS_LD_PDUNC 7 /* phys drive is not connected proper */ |
192 | #define CISS_LD_EXPND 10 /* expanding */ |
193 | #define CISS_LD_NORDY 11 /* volume is not ready */ |
194 | #define CISS_LD_QEXPND 12 /* queued for expansion */ |
195 | u_int8_t failed[4]; /* failed map */ |
196 | u_int8_t res0[416]; |
197 | u_int8_t prog[4]; /* blocks left to rebuild/expand */ |
198 | u_int8_t rebuild; /* drive that is rebuilding */ |
199 | u_int16_t remapcnt[32]; /* count of remapped blocks for pds */ |
200 | u_int8_t replaced[4]; /* replaced drives map */ |
201 | u_int8_t spare[4]; /* used spares map */ |
202 | u_int8_t sparestat; /* spare status */ |
203 | #define CISS_LD_CONF 0x01 /* spare configured */ |
204 | #define CISS_LD_RBLD 0x02 /* spare is used and rebuilding */ |
205 | #define CISS_LD_DONE 0x04 /* spare rebuild done */ |
206 | #define CISS_LD_FAIL 0x08 /* at least one spare drive has failed */ |
207 | #define CISS_LD_USED 0x10 /* at least one spare drive is used */ |
208 | #define CISS_LD_AVAIL 0x20 /* at least one spare is available */ |
209 | u_int8_t sparemap[32]; /* spare->pd replacement map */ |
210 | u_int8_t replok[4]; /* replaced failed map */ |
211 | u_int8_t readyok; /* ready to become ok */ |
212 | u_int8_t memfail; /* cache mem failure */ |
213 | u_int8_t expfail; /* expansion failure */ |
214 | u_int8_t rebldfail; /* rebuild failure */ |
215 | #define CISS_LD_RBLD_READ 0x01 /* read faild */ |
216 | #define CISS_LD_RBLD_WRITE 0x02 /* write fail */ |
217 | u_int8_t bigfailed[16]; /* bigmap vers of same of the above */ |
218 | u_int8_t bigremapcnt[256]; |
219 | u_int8_t bigreplaced[16]; |
220 | u_int8_t bigspare[16]; |
221 | u_int8_t bigsparemap[128]; |
222 | u_int8_t bigreplok[16]; |
223 | u_int8_t bigrebuild; /* big-number rebuilding driveno */ |
224 | } __packed; |
225 | |
226 | struct ciss_pdid { |
227 | u_int8_t bus; |
228 | u_int8_t target; |
229 | u_int16_t blksz; |
230 | u_int32_t nblocks; |
231 | u_int32_t resblks; |
232 | u_int8_t model[40]; |
233 | u_int8_t serial[40]; |
234 | u_int8_t revision[8]; |
235 | u_int8_t bits; |
236 | u_int8_t res0[2]; |
237 | u_int8_t present; |
238 | #define CISS_PD_PRESENT 0x01 |
239 | #define CISS_PD_NONDSK 0x02 |
240 | #define CISS_PD_WIDE 0x04 |
241 | #define CISS_PD_SYNC 0x08 |
242 | #define CISS_PD_NARROW 0x10 |
243 | #define CISS_PD_W2NARR 0x20 /* wide downgrade to narrow */ |
244 | #define CISS_PD_ULTRA 0x40 |
245 | #define CISS_PD_ULTRA2 0x80 |
246 | u_int8_t config; |
247 | #define CISS_PD_SMART 0x01 |
248 | #define CISS_PD_SMERRR 0x02 |
249 | #define CISS_PD_SMERRE 0x04 |
250 | #define CISS_PD_SMERRD 0x08 |
251 | #define CISS_PD_EXT 0x10 |
252 | #define CISS_PD_CONF 0x20 |
253 | #define CISS_PD_SPARE 0x40 |
254 | #define CISS_PD_CASAVE 0x80 |
255 | u_int8_t res1; |
256 | u_int8_t cache; |
257 | #define CISS_PD_CACHE 0x01 |
258 | #define CISS_PD_CASAFE 0x01 |
259 | u_int8_t res2[5]; |
260 | u_int8_t connector[2]; |
261 | u_int8_t res3; |
262 | u_int8_t bay; |
263 | u_int16_t rpm; |
264 | u_int8_t type; |
265 | u_int8_t res4[393]; |
266 | } __packed; |
267 | |
268 | struct ciss_event { |
269 | u_int32_t reltime; /* time since controller boot */ |
270 | u_int16_t event; |
271 | #define CISS_EVCLS_PROTO 0 |
272 | #define CISS_EVCLS_PLUG 1 |
273 | #define CISS_EVCLS_HW 2 |
274 | #define CISS_EVCLS_ENV 3 |
275 | #define CISS_EVCLS_PD 4 /* ciss_evpdchg in details */ |
276 | #define CISS_EVCLS_LD 5 |
277 | #define CISS_EVCLS_CTRL 6 |
278 | #define CISS_EVCLS_CISS 8 /* funky errors */ |
279 | #define CISS_EVCLS_RESV 9 |
280 | u_int16_t subevent; |
281 | #define CISS_EVPROTO_STAT 0 |
282 | #define CISS_EVPROTO_ERR 1 |
283 | #define CISS_EVPLUG_PDCHG 0 /* ciss_evpdchg */ |
284 | #define CISS_EVPLUG_POWER 1 /* ciss_evpschg */ |
285 | #define CISS_EVPLUG_FAN 2 /* ciss_evfanchg */ |
286 | #define CISS_EVPLUG_UPS 3 /* ciss_evupschg */ |
287 | #define CISS_EVPLUG_CTRL 4 /* ciss_evctrlchg: ctrl removed? (; */ |
288 | #define CISS_EVHW_CABLES 0 |
289 | #define CISS_EVHW_MEMORY 1 |
290 | #define CISS_EVHW_FAN 2 /* detail as in CISS_EVPLUG_FAN */ |
291 | #define CISS_EVHW_VRM 3 |
292 | #define CISS_EVENV_TEMP 0 /* ciss_evtempchg */ |
293 | #define CISS_EVENV_PS 1 |
294 | #define CISS_EVENV_CHASSIS 2 |
295 | #define CISS_EVENV_AC 3 |
296 | #define CISS_EVPD_STAT 0 |
297 | #define CISS_EVLD_STAT 0 |
298 | #define CISS_EVLD_ERR 1 |
299 | #define CISS_EVLD_CHECK 2 /* surface check */ |
300 | #define CISS_EVCTRL_STAT 0 |
301 | u_int16_t detail; |
302 | #define CISS_EVSTAT_NONE 0 |
303 | #define CISS_EVSTAT_DISABLE 1 |
304 | #define CISS_EVSTAT_TMO 2 /* async event poll timeout */ |
305 | #define CISS_EVERR_OVERFLOW 0 /* event queue overflow */ |
306 | #define CISS_EVPLUG_REMOVE 0 |
307 | #define CISS_EVPLUG_INSERT 1 |
308 | #define CISS_EVFAN_FAULT 0 |
309 | #define CISS_EVFAN_DEGRADED 1 |
310 | #define CISS_EVFAN_OK 2 |
311 | #define CISS_EVVRM_REMOVE 0 |
312 | #define CISS_EVVRM_INSERT 1 |
313 | #define CISS_EVVRM_FAILED 2 |
314 | #define CISS_EVVRM_OK 3 |
315 | #define CISS_EVTEMP_LIMEX 0 /* limit exceeded */ |
316 | #define CISS_EVTEMP_WARN 1 |
317 | #define CISS_EVTEMP_OK 2 |
318 | #define CISS_EVPS_FAIL 0 |
319 | #define CISS_EVPS_OK 2 |
320 | #define CISS_EVCHAS_OPEN 0 |
321 | #define CISS_EVCHAS_CLOSE 2 |
322 | #define CISS_EVAC_FAIL 0 |
323 | #define CISS_EVAC_BATTLOW 1 |
324 | #define CISS_EVPDSTAT_FAIL 0 |
325 | #define CISS_EVLDSTAT_CHG 0 /* ciss_evldchg */ |
326 | #define CISS_EVLDSTAT_EXMEDIA 1 /* untolerant cfg got drive replaced */ |
327 | #define CISS_EVLDSTAT_RERDERR 2 /* ciss_evldrblderr */ |
328 | #define CISS_EVLDSTAT_REWRERR 3 /* ciss_evldrblderr */ |
329 | #define CISS_EVLDERR_FATAL 0 /* ciss_evlderr */ |
330 | #define CISS_EVCHECK_DONE 0 /* details have onle 16bit ld num */ |
331 | #define CISS_EVCTRLSTAT_CHG 0 /* ciss_evctrlstat */ |
332 | u_int8_t data[64]; |
333 | u_int8_t msg[80]; |
334 | u_int32_t tag; |
335 | u_int16_t monday; |
336 | u_int16_t year; |
337 | u_int32_t time; |
338 | u_int16_t presec; /* time for events before boot */ |
339 | u_int8_t device[8]; |
340 | u_int8_t resv[336]; |
341 | } __packed; |
342 | |
343 | struct ciss_evpdchg { /* details pointer */ |
344 | u_int16_t pd; |
345 | u_int8_t flag; /* 1 for configured */ |
346 | u_int8_t spare; |
347 | u_int8_t bigpd; /* big number of the pd */ |
348 | u_int8_t baynum; |
349 | } __packed; |
350 | |
351 | struct ciss_evpschg { /* details pointer */ |
352 | u_int16_t port; |
353 | u_int16_t psid; |
354 | u_int16_t box; |
355 | } __packed; |
356 | |
357 | struct ciss_evfanchg { /* details pointer */ |
358 | u_int16_t port; |
359 | u_int16_t fanid; |
360 | u_int16_t box; |
361 | } __packed; |
362 | |
363 | struct ciss_evupschg { /* details pointer */ |
364 | u_int16_t port; |
365 | u_int16_t upsid; |
366 | } __packed; |
367 | |
368 | struct ciss_evctrlchg { /* details pointer */ |
369 | u_int16_t slot; |
370 | } __packed; |
371 | |
372 | struct ciss_evtempchg { /* details pointer */ |
373 | u_int16_t port; |
374 | u_int16_t sensid; |
375 | u_int16_t box; |
376 | } __packed; |
377 | |
378 | struct ciss_evldchg { /* details pointer */ |
379 | u_int16_t ld; |
380 | u_int8_t prevstat; /* same as ldstat->state */ |
381 | u_int8_t newstat; /* same as ldstat->state */ |
382 | u_int8_t sparestat; |
383 | } __packed; |
384 | |
385 | struct ciss_evldrblderr { /* details pointer */ |
386 | u_int16_t ld; |
387 | u_int8_t replace; |
388 | u_int8_t errpd; |
389 | u_int8_t bigreplace; |
390 | u_int8_t bigerrpd; |
391 | } __packed; |
392 | |
393 | struct ciss_evlderr { /* details pointer */ |
394 | u_int16_t ld; |
395 | u_int16_t blkno[2]; /* unaligned; if >2tb see big later */ |
396 | u_int16_t count; |
397 | u_int8_t ldcmd; |
398 | u_int8_t bus; |
399 | u_int8_t target; |
400 | u_int8_t bigblkno[8]; /* unaligned */ |
401 | } __packed; |
402 | |
403 | struct ciss_evctrlstat { /* details pointer */ |
404 | u_int8_t prefctrl; |
405 | u_int8_t currmode; |
406 | u_int8_t redctrl; |
407 | u_int8_t redfail; |
408 | u_int8_t prevctrl; |
409 | u_int8_t prevmode; |
410 | u_int8_t prevred; |
411 | u_int8_t prevfail; |
412 | } __packed; |
413 | |
414 | struct ciss_cmd { |
415 | u_int8_t resv0; /* 00 */ |
416 | u_int8_t sgin; /* 01: #sg in the cmd */ |
417 | u_int16_t sglen; /* 02: #sg total */ |
418 | u_int32_t id; /* 04: cmd id << 2 and status bits */ |
419 | #define CISS_CMD_ERR 0x02 |
420 | u_int32_t id_hi; /* 08: not used */ |
421 | u_int32_t tgt; /* 0c: tgt:bus:mode or lun:mode */ |
422 | #define CISS_CMD_MODE_PERIPH 0x00000000 |
423 | #define CISS_CMD_MODE_LD 0x40000000 |
424 | #define CISS_CMD_TGT_MASK 0x40ffffff |
425 | #define CISS_CMD_BUS_MASK 0x3f000000 |
426 | #define CISS_CMD_BUS_SHIFT 24 |
427 | u_int32_t tgt2; /* 10: scsi-3 address bytes */ |
428 | |
429 | u_int8_t cdblen; /* 14: valid length of cdb */ |
430 | u_int8_t flags; /* 15 */ |
431 | #define CISS_CDB_CMD 0x00 |
432 | #define CISS_CDB_MSG 0x01 |
433 | #define CISS_CDB_NOTAG 0x00 |
434 | #define CISS_CDB_SIMPL 0x20 |
435 | #define CISS_CDB_QHEAD 0x28 |
436 | #define CISS_CDB_ORDR 0x30 |
437 | #define CISS_CDB_AUTO 0x38 |
438 | #define CISS_CDB_IN 0x80 |
439 | #define CISS_CDB_OUT 0x40 |
440 | u_int16_t tmo; /* 16: timeout in seconds */ |
441 | #define CISS_MAX_CDB 16 |
442 | u_int8_t cdb[16];/* 18 */ |
443 | |
444 | u_int64_t err_pa; /* 28: pa(struct ciss_error *) */ |
445 | u_int32_t err_len;/* 30 */ |
446 | |
447 | struct { /* 34 */ |
448 | u_int32_t addr_lo; |
449 | u_int32_t addr_hi; |
450 | u_int32_t len; |
451 | u_int32_t flags; |
452 | #define CISS_SG_EXT 0x0001 |
453 | } sgl[1]; |
454 | } __packed; |
455 | |
456 | struct ciss_error { |
457 | u_int8_t scsi_stat; /* SCSI_OK etc */ |
458 | u_int8_t senselen; |
459 | u_int16_t cmd_stat; |
460 | #define CISS_ERR_OK 0 |
461 | #define CISS_ERR_TGTST 1 /* target status */ |
462 | #define CISS_ERR_UNRUN 2 |
463 | #define CISS_ERR_OVRUN 3 |
464 | #define CISS_ERR_INVCMD 4 |
465 | #define CISS_ERR_PROTE 5 |
466 | #define CISS_ERR_HWERR 6 |
467 | #define CISS_ERR_CLOSS 7 |
468 | #define CISS_ERR_ABRT 8 |
469 | #define CISS_ERR_FABRT 9 |
470 | #define CISS_ERR_UABRT 10 |
471 | #define CISS_ERR_TMO 11 |
472 | #define CISS_ERR_NABRT 12 |
473 | u_int32_t resid; |
474 | u_int8_t err_type[4]; |
475 | u_int32_t err_info; |
476 | u_int8_t sense[32]; |
477 | } __packed; |
478 | |
479 | struct ciss_ccb { |
480 | TAILQ_ENTRY(ciss_ccb) ccb_link; |
481 | struct ciss_softc *ccb_sc; |
482 | paddr_t ccb_cmdpa; |
483 | enum { |
484 | CISS_CCB_FREE = 0x01, |
485 | CISS_CCB_READY = 0x02, |
486 | CISS_CCB_ONQ = 0x04, |
487 | CISS_CCB_PREQ = 0x08, |
488 | CISS_CCB_POLL = 0x10, |
489 | CISS_CCB_FAIL = 0x80 |
490 | #define CISS_CCB_BITS "\020\01FREE\02READY\03ONQ\04PREQ\05POLL\010FAIL" |
491 | } ccb_state; |
492 | |
493 | struct scsipi_xfer *ccb_xs; |
494 | size_t ccb_len; |
495 | void *ccb_data; |
496 | bus_dmamap_t ccb_dmamap; |
497 | |
498 | struct ciss_error ccb_err; |
499 | struct ciss_cmd ccb_cmd; /* followed by sgl */ |
500 | }; |
501 | |
502 | typedef TAILQ_HEAD(ciss_queue_head, ciss_ccb) ciss_queue_head; |
503 | |
504 | |