1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
25 | */ |
26 | #include <drm/drmP.h> |
27 | #include <drm/drm_crtc_helper.h> |
28 | #include <drm/radeon_drm.h> |
29 | #include <drm/drm_fixed.h> |
30 | #include "radeon.h" |
31 | #include "atom.h" |
32 | |
33 | static void radeon_overscan_setup(struct drm_crtc *crtc, |
34 | struct drm_display_mode *mode) |
35 | { |
36 | struct drm_device *dev = crtc->dev; |
37 | struct radeon_device *rdev = dev->dev_private; |
38 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
39 | |
40 | WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); |
41 | WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); |
42 | WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); |
43 | } |
44 | |
45 | static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, |
46 | struct drm_display_mode *mode) |
47 | { |
48 | struct drm_device *dev = crtc->dev; |
49 | struct radeon_device *rdev = dev->dev_private; |
50 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
51 | int xres = mode->hdisplay; |
52 | int yres = mode->vdisplay; |
53 | bool hscale = true, vscale = true; |
54 | int hsync_wid; |
55 | int vsync_wid; |
56 | int hsync_start; |
57 | int blank_width; |
58 | u32 scale, inc, crtc_more_cntl; |
59 | u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; |
60 | u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; |
61 | u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; |
62 | struct drm_display_mode *native_mode = &radeon_crtc->native_mode; |
63 | |
64 | fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & |
65 | (RADEON_VERT_STRETCH_RESERVED | |
66 | RADEON_VERT_AUTO_RATIO_INC); |
67 | fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & |
68 | (RADEON_HORZ_FP_LOOP_STRETCH | |
69 | RADEON_HORZ_AUTO_RATIO_INC); |
70 | |
71 | crtc_more_cntl = 0; |
72 | if ((rdev->family == CHIP_RS100) || |
73 | (rdev->family == CHIP_RS200)) { |
74 | /* This is to workaround the asic bug for RMX, some versions |
75 | of BIOS dosen't have this register initialized correctly. */ |
76 | crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; |
77 | } |
78 | |
79 | |
80 | fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
81 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
82 | |
83 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
84 | if (!hsync_wid) |
85 | hsync_wid = 1; |
86 | hsync_start = mode->crtc_hsync_start - 8; |
87 | |
88 | fp_h_sync_strt_wid = ((hsync_start & 0x1fff) |
89 | | ((hsync_wid & 0x3f) << 16) |
90 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
91 | ? RADEON_CRTC_H_SYNC_POL |
92 | : 0)); |
93 | |
94 | fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
95 | | ((mode->crtc_vdisplay - 1) << 16)); |
96 | |
97 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
98 | if (!vsync_wid) |
99 | vsync_wid = 1; |
100 | |
101 | fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
102 | | ((vsync_wid & 0x1f) << 16) |
103 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
104 | ? RADEON_CRTC_V_SYNC_POL |
105 | : 0)); |
106 | |
107 | fp_horz_vert_active = 0; |
108 | |
109 | if (native_mode->hdisplay == 0 || |
110 | native_mode->vdisplay == 0) { |
111 | hscale = false; |
112 | vscale = false; |
113 | } else { |
114 | if (xres > native_mode->hdisplay) |
115 | xres = native_mode->hdisplay; |
116 | if (yres > native_mode->vdisplay) |
117 | yres = native_mode->vdisplay; |
118 | |
119 | if (xres == native_mode->hdisplay) |
120 | hscale = false; |
121 | if (yres == native_mode->vdisplay) |
122 | vscale = false; |
123 | } |
124 | |
125 | switch (radeon_crtc->rmx_type) { |
126 | case RMX_FULL: |
127 | case RMX_ASPECT: |
128 | if (!hscale) |
129 | fp_horz_stretch |= ((xres/8-1) << 16); |
130 | else { |
131 | inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; |
132 | scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) |
133 | / native_mode->hdisplay + 1; |
134 | fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | |
135 | RADEON_HORZ_STRETCH_BLEND | |
136 | RADEON_HORZ_STRETCH_ENABLE | |
137 | ((native_mode->hdisplay/8-1) << 16)); |
138 | } |
139 | |
140 | if (!vscale) |
141 | fp_vert_stretch |= ((yres-1) << 12); |
142 | else { |
143 | inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; |
144 | scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) |
145 | / native_mode->vdisplay + 1; |
146 | fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | |
147 | RADEON_VERT_STRETCH_ENABLE | |
148 | RADEON_VERT_STRETCH_BLEND | |
149 | ((native_mode->vdisplay-1) << 12)); |
150 | } |
151 | break; |
152 | case RMX_CENTER: |
153 | fp_horz_stretch |= ((xres/8-1) << 16); |
154 | fp_vert_stretch |= ((yres-1) << 12); |
155 | |
156 | crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | |
157 | RADEON_CRTC_AUTO_VERT_CENTER_EN); |
158 | |
159 | blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; |
160 | if (blank_width > 110) |
161 | blank_width = 110; |
162 | |
163 | fp_crtc_h_total_disp = (((blank_width) & 0x3ff) |
164 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
165 | |
166 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
167 | if (!hsync_wid) |
168 | hsync_wid = 1; |
169 | |
170 | fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) |
171 | | ((hsync_wid & 0x3f) << 16) |
172 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
173 | ? RADEON_CRTC_H_SYNC_POL |
174 | : 0)); |
175 | |
176 | fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) |
177 | | ((mode->crtc_vdisplay - 1) << 16)); |
178 | |
179 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
180 | if (!vsync_wid) |
181 | vsync_wid = 1; |
182 | |
183 | fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) |
184 | | ((vsync_wid & 0x1f) << 16) |
185 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
186 | ? RADEON_CRTC_V_SYNC_POL |
187 | : 0))); |
188 | |
189 | fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | |
190 | (((native_mode->hdisplay / 8) & 0x1ff) << 16)); |
191 | break; |
192 | case RMX_OFF: |
193 | default: |
194 | fp_horz_stretch |= ((xres/8-1) << 16); |
195 | fp_vert_stretch |= ((yres-1) << 12); |
196 | break; |
197 | } |
198 | |
199 | WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); |
200 | WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); |
201 | WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); |
202 | WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); |
203 | WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); |
204 | WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); |
205 | WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); |
206 | WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); |
207 | } |
208 | |
209 | static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) |
210 | { |
211 | struct radeon_device *rdev = dev->dev_private; |
212 | int i = 0; |
213 | |
214 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
215 | the cause yet, but this workaround will mask the problem for now. |
216 | Other chips usually will pass at the very first test, so the |
217 | workaround shouldn't have any effect on them. */ |
218 | for (i = 0; |
219 | (i < 10000 && |
220 | RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
221 | i++); |
222 | } |
223 | |
224 | static void radeon_pll_write_update(struct drm_device *dev) |
225 | { |
226 | struct radeon_device *rdev = dev->dev_private; |
227 | |
228 | while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
229 | |
230 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
231 | RADEON_PPLL_ATOMIC_UPDATE_W, |
232 | ~(RADEON_PPLL_ATOMIC_UPDATE_W)); |
233 | } |
234 | |
235 | static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) |
236 | { |
237 | struct radeon_device *rdev = dev->dev_private; |
238 | int i = 0; |
239 | |
240 | |
241 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
242 | the cause yet, but this workaround will mask the problem for now. |
243 | Other chips usually will pass at the very first test, so the |
244 | workaround shouldn't have any effect on them. */ |
245 | for (i = 0; |
246 | (i < 10000 && |
247 | RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
248 | i++); |
249 | } |
250 | |
251 | static void radeon_pll2_write_update(struct drm_device *dev) |
252 | { |
253 | struct radeon_device *rdev = dev->dev_private; |
254 | |
255 | while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
256 | |
257 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
258 | RADEON_P2PLL_ATOMIC_UPDATE_W, |
259 | ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); |
260 | } |
261 | |
262 | static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, |
263 | uint16_t fb_div) |
264 | { |
265 | unsigned int vcoFreq; |
266 | |
267 | if (!ref_div) |
268 | return 1; |
269 | |
270 | vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; |
271 | |
272 | /* |
273 | * This is horribly crude: the VCO frequency range is divided into |
274 | * 3 parts, each part having a fixed PLL gain value. |
275 | */ |
276 | if (vcoFreq >= 30000) |
277 | /* |
278 | * [300..max] MHz : 7 |
279 | */ |
280 | return 7; |
281 | else if (vcoFreq >= 18000) |
282 | /* |
283 | * [180..300) MHz : 4 |
284 | */ |
285 | return 4; |
286 | else |
287 | /* |
288 | * [0..180) MHz : 1 |
289 | */ |
290 | return 1; |
291 | } |
292 | |
293 | static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) |
294 | { |
295 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
296 | struct drm_device *dev = crtc->dev; |
297 | struct radeon_device *rdev = dev->dev_private; |
298 | uint32_t crtc_ext_cntl = 0; |
299 | uint32_t mask; |
300 | |
301 | if (radeon_crtc->crtc_id) |
302 | mask = (RADEON_CRTC2_DISP_DIS | |
303 | RADEON_CRTC2_VSYNC_DIS | |
304 | RADEON_CRTC2_HSYNC_DIS | |
305 | RADEON_CRTC2_DISP_REQ_EN_B); |
306 | else |
307 | mask = (RADEON_CRTC_DISPLAY_DIS | |
308 | RADEON_CRTC_VSYNC_DIS | |
309 | RADEON_CRTC_HSYNC_DIS); |
310 | |
311 | /* |
312 | * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC. |
313 | * Therefore it is set in the DAC DMPS function. |
314 | * This is different for GPU's with a single CRTC but a primary and a |
315 | * TV DAC: here it controls the single CRTC no matter where it is |
316 | * routed. Therefore we set it here. |
317 | */ |
318 | if (rdev->flags & RADEON_SINGLE_CRTC) |
319 | crtc_ext_cntl = RADEON_CRTC_CRT_ON; |
320 | |
321 | switch (mode) { |
322 | case DRM_MODE_DPMS_ON: |
323 | radeon_crtc->enabled = true; |
324 | /* adjust pm to dpms changes BEFORE enabling crtcs */ |
325 | radeon_pm_compute_clocks(rdev); |
326 | if (radeon_crtc->crtc_id) |
327 | WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); |
328 | else { |
329 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | |
330 | RADEON_CRTC_DISP_REQ_EN_B)); |
331 | WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); |
332 | } |
333 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
334 | radeon_crtc_load_lut(crtc); |
335 | break; |
336 | case DRM_MODE_DPMS_STANDBY: |
337 | case DRM_MODE_DPMS_SUSPEND: |
338 | case DRM_MODE_DPMS_OFF: |
339 | drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
340 | if (radeon_crtc->crtc_id) |
341 | WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); |
342 | else { |
343 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | |
344 | RADEON_CRTC_DISP_REQ_EN_B)); |
345 | WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); |
346 | } |
347 | radeon_crtc->enabled = false; |
348 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
349 | radeon_pm_compute_clocks(rdev); |
350 | break; |
351 | } |
352 | } |
353 | |
354 | int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
355 | struct drm_framebuffer *old_fb) |
356 | { |
357 | return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); |
358 | } |
359 | |
360 | int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, |
361 | struct drm_framebuffer *fb, |
362 | int x, int y, enum mode_set_atomic state) |
363 | { |
364 | return radeon_crtc_do_set_base(crtc, fb, x, y, 1); |
365 | } |
366 | |
367 | int radeon_crtc_do_set_base(struct drm_crtc *crtc, |
368 | struct drm_framebuffer *fb, |
369 | int x, int y, int atomic) |
370 | { |
371 | struct drm_device *dev = crtc->dev; |
372 | struct radeon_device *rdev = dev->dev_private; |
373 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
374 | struct radeon_framebuffer *radeon_fb; |
375 | struct drm_framebuffer *target_fb; |
376 | struct drm_gem_object *obj; |
377 | struct radeon_bo *rbo; |
378 | uint64_t base; |
379 | uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; |
380 | uint32_t crtc_pitch, pitch_pixels; |
381 | uint32_t tiling_flags; |
382 | int format; |
383 | uint32_t gen_cntl_reg, gen_cntl_val; |
384 | int r; |
385 | |
386 | DRM_DEBUG_KMS("\n" ); |
387 | /* no fb bound */ |
388 | if (!atomic && !crtc->primary->fb) { |
389 | DRM_DEBUG_KMS("No FB bound\n" ); |
390 | return 0; |
391 | } |
392 | |
393 | if (atomic) { |
394 | radeon_fb = to_radeon_framebuffer(fb); |
395 | target_fb = fb; |
396 | } |
397 | else { |
398 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
399 | target_fb = crtc->primary->fb; |
400 | } |
401 | |
402 | switch (target_fb->bits_per_pixel) { |
403 | case 8: |
404 | format = 2; |
405 | break; |
406 | case 15: /* 555 */ |
407 | format = 3; |
408 | break; |
409 | case 16: /* 565 */ |
410 | format = 4; |
411 | break; |
412 | case 24: /* RGB */ |
413 | format = 5; |
414 | break; |
415 | case 32: /* xRGB */ |
416 | format = 6; |
417 | break; |
418 | default: |
419 | return false; |
420 | } |
421 | |
422 | /* Pin framebuffer & get tilling informations */ |
423 | obj = radeon_fb->obj; |
424 | rbo = gem_to_radeon_bo(obj); |
425 | if (atomic) { |
426 | /* |
427 | * If you want to do this in atomic, better have it |
428 | * pinned ahead of time. |
429 | */ |
430 | BUG_ON(rbo->pin_count == 0); |
431 | base = radeon_bo_gpu_offset(rbo); |
432 | tiling_flags = 0; |
433 | goto pinned; |
434 | } |
435 | retry: |
436 | r = radeon_bo_reserve(rbo, false); |
437 | if (unlikely(r != 0)) |
438 | return r; |
439 | /* Only 27 bit offset for legacy CRTC */ |
440 | r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27, |
441 | &base); |
442 | if (unlikely(r != 0)) { |
443 | radeon_bo_unreserve(rbo); |
444 | |
445 | /* On old GPU like RN50 with little vram pining can fails because |
446 | * current fb is taking all space needed. So instead of unpining |
447 | * the old buffer after pining the new one, first unpin old one |
448 | * and then retry pining new one. |
449 | * |
450 | * As only master can set mode only master can pin and it is |
451 | * unlikely the master client will race with itself especialy |
452 | * on those old gpu with single crtc. |
453 | * |
454 | * We don't shutdown the display controller because new buffer |
455 | * will end up in same spot. |
456 | */ |
457 | if (fb && fb != crtc->primary->fb) { |
458 | struct radeon_bo *old_rbo; |
459 | unsigned long nsize, osize; |
460 | |
461 | old_rbo = gem_to_radeon_bo(to_radeon_framebuffer(fb)->obj); |
462 | osize = radeon_bo_size(old_rbo); |
463 | nsize = radeon_bo_size(rbo); |
464 | if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) { |
465 | radeon_bo_unpin(old_rbo); |
466 | radeon_bo_unreserve(old_rbo); |
467 | fb = NULL; |
468 | goto retry; |
469 | } |
470 | } |
471 | return -EINVAL; |
472 | } |
473 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
474 | radeon_bo_unreserve(rbo); |
475 | pinned: |
476 | if (tiling_flags & RADEON_TILING_MICRO) |
477 | DRM_ERROR("trying to scanout microtiled buffer\n" ); |
478 | |
479 | /* if scanout was in GTT this really wouldn't work */ |
480 | /* crtc offset is from display base addr not FB location */ |
481 | radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; |
482 | |
483 | base -= radeon_crtc->legacy_display_base_addr; |
484 | |
485 | crtc_offset_cntl = 0; |
486 | |
487 | pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
488 | crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) + |
489 | ((target_fb->bits_per_pixel * 8) - 1)) / |
490 | (target_fb->bits_per_pixel * 8)); |
491 | crtc_pitch |= crtc_pitch << 16; |
492 | |
493 | crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; |
494 | if (tiling_flags & RADEON_TILING_MACRO) { |
495 | if (ASIC_IS_R300(rdev)) |
496 | crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | |
497 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
498 | R300_CRTC_MACRO_TILE_EN); |
499 | else |
500 | crtc_offset_cntl |= RADEON_CRTC_TILE_EN; |
501 | } else { |
502 | if (ASIC_IS_R300(rdev)) |
503 | crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | |
504 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
505 | R300_CRTC_MACRO_TILE_EN); |
506 | else |
507 | crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; |
508 | } |
509 | |
510 | if (tiling_flags & RADEON_TILING_MACRO) { |
511 | if (ASIC_IS_R300(rdev)) { |
512 | crtc_tile_x0_y0 = x | (y << 16); |
513 | base &= ~0x7ff; |
514 | } else { |
515 | int byteshift = target_fb->bits_per_pixel >> 4; |
516 | int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; |
517 | base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); |
518 | crtc_offset_cntl |= (y % 16); |
519 | } |
520 | } else { |
521 | int offset = y * pitch_pixels + x; |
522 | switch (target_fb->bits_per_pixel) { |
523 | case 8: |
524 | offset *= 1; |
525 | break; |
526 | case 15: |
527 | case 16: |
528 | offset *= 2; |
529 | break; |
530 | case 24: |
531 | offset *= 3; |
532 | break; |
533 | case 32: |
534 | offset *= 4; |
535 | break; |
536 | default: |
537 | return false; |
538 | } |
539 | base += offset; |
540 | } |
541 | |
542 | base &= ~7; |
543 | |
544 | if (radeon_crtc->crtc_id == 1) |
545 | gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; |
546 | else |
547 | gen_cntl_reg = RADEON_CRTC_GEN_CNTL; |
548 | |
549 | gen_cntl_val = RREG32(gen_cntl_reg); |
550 | gen_cntl_val &= ~(0xf << 8); |
551 | gen_cntl_val |= (format << 8); |
552 | gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; |
553 | WREG32(gen_cntl_reg, gen_cntl_val); |
554 | |
555 | crtc_offset = (u32)base; |
556 | |
557 | WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); |
558 | |
559 | if (ASIC_IS_R300(rdev)) { |
560 | if (radeon_crtc->crtc_id) |
561 | WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); |
562 | else |
563 | WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); |
564 | } |
565 | WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); |
566 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); |
567 | WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
568 | |
569 | if (!atomic && fb && fb != crtc->primary->fb) { |
570 | radeon_fb = to_radeon_framebuffer(fb); |
571 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
572 | r = radeon_bo_reserve(rbo, false); |
573 | if (unlikely(r != 0)) |
574 | return r; |
575 | radeon_bo_unpin(rbo); |
576 | radeon_bo_unreserve(rbo); |
577 | } |
578 | |
579 | /* Bytes per pixel may have changed */ |
580 | radeon_bandwidth_update(rdev); |
581 | |
582 | return 0; |
583 | } |
584 | |
585 | static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) |
586 | { |
587 | struct drm_device *dev = crtc->dev; |
588 | struct radeon_device *rdev = dev->dev_private; |
589 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
590 | struct drm_encoder *encoder; |
591 | int format; |
592 | int hsync_start; |
593 | int hsync_wid; |
594 | int vsync_wid; |
595 | uint32_t crtc_h_total_disp; |
596 | uint32_t crtc_h_sync_strt_wid; |
597 | uint32_t crtc_v_total_disp; |
598 | uint32_t crtc_v_sync_strt_wid; |
599 | bool is_tv = false; |
600 | |
601 | DRM_DEBUG_KMS("\n" ); |
602 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
603 | if (encoder->crtc == crtc) { |
604 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
605 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
606 | is_tv = true; |
607 | DRM_INFO("crtc %d is connected to a TV\n" , radeon_crtc->crtc_id); |
608 | break; |
609 | } |
610 | } |
611 | } |
612 | |
613 | switch (crtc->primary->fb->bits_per_pixel) { |
614 | case 8: |
615 | format = 2; |
616 | break; |
617 | case 15: /* 555 */ |
618 | format = 3; |
619 | break; |
620 | case 16: /* 565 */ |
621 | format = 4; |
622 | break; |
623 | case 24: /* RGB */ |
624 | format = 5; |
625 | break; |
626 | case 32: /* xRGB */ |
627 | format = 6; |
628 | break; |
629 | default: |
630 | return false; |
631 | } |
632 | |
633 | crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
634 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
635 | |
636 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
637 | if (!hsync_wid) |
638 | hsync_wid = 1; |
639 | hsync_start = mode->crtc_hsync_start - 8; |
640 | |
641 | crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
642 | | ((hsync_wid & 0x3f) << 16) |
643 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
644 | ? RADEON_CRTC_H_SYNC_POL |
645 | : 0)); |
646 | |
647 | /* This works for double scan mode. */ |
648 | crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
649 | | ((mode->crtc_vdisplay - 1) << 16)); |
650 | |
651 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
652 | if (!vsync_wid) |
653 | vsync_wid = 1; |
654 | |
655 | crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
656 | | ((vsync_wid & 0x1f) << 16) |
657 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
658 | ? RADEON_CRTC_V_SYNC_POL |
659 | : 0)); |
660 | |
661 | if (radeon_crtc->crtc_id) { |
662 | uint32_t crtc2_gen_cntl; |
663 | uint32_t disp2_merge_cntl; |
664 | |
665 | /* if TV DAC is enabled for another crtc and keep it enabled */ |
666 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; |
667 | crtc2_gen_cntl |= ((format << 8) |
668 | | RADEON_CRTC2_VSYNC_DIS |
669 | | RADEON_CRTC2_HSYNC_DIS |
670 | | RADEON_CRTC2_DISP_DIS |
671 | | RADEON_CRTC2_DISP_REQ_EN_B |
672 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
673 | ? RADEON_CRTC2_DBL_SCAN_EN |
674 | : 0) |
675 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
676 | ? RADEON_CRTC2_CSYNC_EN |
677 | : 0) |
678 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
679 | ? RADEON_CRTC2_INTERLACE_EN |
680 | : 0)); |
681 | |
682 | /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ |
683 | if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) |
684 | crtc2_gen_cntl |= RADEON_CRTC2_EN; |
685 | |
686 | disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
687 | disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
688 | |
689 | WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); |
690 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
691 | |
692 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); |
693 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); |
694 | } else { |
695 | uint32_t crtc_gen_cntl; |
696 | uint32_t crtc_ext_cntl; |
697 | uint32_t disp_merge_cntl; |
698 | |
699 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; |
700 | crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN |
701 | | (format << 8) |
702 | | RADEON_CRTC_DISP_REQ_EN_B |
703 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
704 | ? RADEON_CRTC_DBL_SCAN_EN |
705 | : 0) |
706 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
707 | ? RADEON_CRTC_CSYNC_EN |
708 | : 0) |
709 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
710 | ? RADEON_CRTC_INTERLACE_EN |
711 | : 0)); |
712 | |
713 | /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ |
714 | if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) |
715 | crtc_gen_cntl |= RADEON_CRTC_EN; |
716 | |
717 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
718 | crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | |
719 | RADEON_CRTC_VSYNC_DIS | |
720 | RADEON_CRTC_HSYNC_DIS | |
721 | RADEON_CRTC_DISPLAY_DIS); |
722 | |
723 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
724 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
725 | |
726 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
727 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
728 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
729 | } |
730 | |
731 | if (is_tv) |
732 | radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, |
733 | &crtc_h_sync_strt_wid, &crtc_v_total_disp, |
734 | &crtc_v_sync_strt_wid); |
735 | |
736 | WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); |
737 | WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); |
738 | WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); |
739 | WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); |
740 | |
741 | return true; |
742 | } |
743 | |
744 | static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
745 | { |
746 | struct drm_device *dev = crtc->dev; |
747 | struct radeon_device *rdev = dev->dev_private; |
748 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
749 | struct drm_encoder *encoder; |
750 | uint32_t feedback_div = 0; |
751 | uint32_t frac_fb_div = 0; |
752 | uint32_t reference_div = 0; |
753 | uint32_t post_divider = 0; |
754 | uint32_t freq = 0; |
755 | uint8_t pll_gain; |
756 | bool use_bios_divs = false; |
757 | /* PLL registers */ |
758 | uint32_t pll_ref_div = 0; |
759 | uint32_t pll_fb_post_div = 0; |
760 | uint32_t htotal_cntl = 0; |
761 | bool is_tv = false; |
762 | struct radeon_pll *pll; |
763 | |
764 | struct { |
765 | int divider; |
766 | int bitvalue; |
767 | } *post_div, post_divs[] = { |
768 | /* From RAGE 128 VR/RAGE 128 GL Register |
769 | * Reference Manual (Technical Reference |
770 | * Manual P/N RRG-G04100-C Rev. 0.04), page |
771 | * 3-17 (PLL_DIV_[3:0]). |
772 | */ |
773 | { 1, 0 }, /* VCLK_SRC */ |
774 | { 2, 1 }, /* VCLK_SRC/2 */ |
775 | { 4, 2 }, /* VCLK_SRC/4 */ |
776 | { 8, 3 }, /* VCLK_SRC/8 */ |
777 | { 3, 4 }, /* VCLK_SRC/3 */ |
778 | { 16, 5 }, /* VCLK_SRC/16 */ |
779 | { 6, 6 }, /* VCLK_SRC/6 */ |
780 | { 12, 7 }, /* VCLK_SRC/12 */ |
781 | { 0, 0 } |
782 | }; |
783 | |
784 | if (radeon_crtc->crtc_id) |
785 | pll = &rdev->clock.p2pll; |
786 | else |
787 | pll = &rdev->clock.p1pll; |
788 | |
789 | pll->flags = RADEON_PLL_LEGACY; |
790 | |
791 | if (mode->clock > 200000) /* range limits??? */ |
792 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
793 | else |
794 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
795 | |
796 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
797 | if (encoder->crtc == crtc) { |
798 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
799 | |
800 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
801 | is_tv = true; |
802 | break; |
803 | } |
804 | |
805 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
806 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
807 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { |
808 | if (!rdev->is_atom_bios) { |
809 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
810 | struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; |
811 | if (lvds) { |
812 | if (lvds->use_bios_dividers) { |
813 | pll_ref_div = lvds->panel_ref_divider; |
814 | pll_fb_post_div = (lvds->panel_fb_divider | |
815 | (lvds->panel_post_divider << 16)); |
816 | htotal_cntl = 0; |
817 | use_bios_divs = true; |
818 | } |
819 | } |
820 | } |
821 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
822 | } |
823 | } |
824 | } |
825 | |
826 | DRM_DEBUG_KMS("\n" ); |
827 | |
828 | if (!use_bios_divs) { |
829 | radeon_compute_pll_legacy(pll, mode->clock, |
830 | &freq, &feedback_div, &frac_fb_div, |
831 | &reference_div, &post_divider); |
832 | |
833 | for (post_div = &post_divs[0]; post_div->divider; ++post_div) { |
834 | if (post_div->divider == post_divider) |
835 | break; |
836 | } |
837 | |
838 | if (!post_div->divider) |
839 | post_div = &post_divs[0]; |
840 | |
841 | DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n" , |
842 | (unsigned)freq, |
843 | feedback_div, |
844 | reference_div, |
845 | post_divider); |
846 | |
847 | pll_ref_div = reference_div; |
848 | #if defined(__powerpc__) && (0) /* TODO */ |
849 | /* apparently programming this otherwise causes a hang??? */ |
850 | if (info->MacModel == RADEON_MAC_IBOOK) |
851 | pll_fb_post_div = 0x000600ad; |
852 | else |
853 | #endif |
854 | pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); |
855 | |
856 | htotal_cntl = mode->htotal & 0x7; |
857 | |
858 | } |
859 | |
860 | pll_gain = radeon_compute_pll_gain(pll->reference_freq, |
861 | pll_ref_div & 0x3ff, |
862 | pll_fb_post_div & 0x7ff); |
863 | |
864 | if (radeon_crtc->crtc_id) { |
865 | uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & |
866 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | |
867 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); |
868 | |
869 | if (is_tv) { |
870 | radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, |
871 | &pll_ref_div, &pll_fb_post_div, |
872 | &pixclks_cntl); |
873 | } |
874 | |
875 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
876 | RADEON_PIX2CLK_SRC_SEL_CPUCLK, |
877 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
878 | |
879 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
880 | RADEON_P2PLL_RESET |
881 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
882 | | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), |
883 | ~(RADEON_P2PLL_RESET |
884 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
885 | | RADEON_P2PLL_PVG_MASK)); |
886 | |
887 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
888 | pll_ref_div, |
889 | ~RADEON_P2PLL_REF_DIV_MASK); |
890 | |
891 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
892 | pll_fb_post_div, |
893 | ~RADEON_P2PLL_FB0_DIV_MASK); |
894 | |
895 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
896 | pll_fb_post_div, |
897 | ~RADEON_P2PLL_POST0_DIV_MASK); |
898 | |
899 | radeon_pll2_write_update(dev); |
900 | radeon_pll2_wait_for_read_update_complete(dev); |
901 | |
902 | WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); |
903 | |
904 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
905 | 0, |
906 | ~(RADEON_P2PLL_RESET |
907 | | RADEON_P2PLL_SLEEP |
908 | | RADEON_P2PLL_ATOMIC_UPDATE_EN)); |
909 | |
910 | DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n" , |
911 | (unsigned)pll_ref_div, |
912 | (unsigned)pll_fb_post_div, |
913 | (unsigned)htotal_cntl, |
914 | RREG32_PLL(RADEON_P2PLL_CNTL)); |
915 | DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n" , |
916 | (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, |
917 | (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, |
918 | (unsigned)((pll_fb_post_div & |
919 | RADEON_P2PLL_POST0_DIV_MASK) >> 16)); |
920 | |
921 | mdelay(50); /* Let the clock to lock */ |
922 | |
923 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
924 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, |
925 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
926 | |
927 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
928 | } else { |
929 | uint32_t pixclks_cntl; |
930 | |
931 | |
932 | if (is_tv) { |
933 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
934 | radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, |
935 | &pll_fb_post_div, &pixclks_cntl); |
936 | } |
937 | |
938 | if (rdev->flags & RADEON_IS_MOBILITY) { |
939 | /* A temporal workaround for the occasional blanking on certain laptop panels. |
940 | This appears to related to the PLL divider registers (fail to lock?). |
941 | It occurs even when all dividers are the same with their old settings. |
942 | In this case we really don't need to fiddle with PLL registers. |
943 | By doing this we can avoid the blanking problem with some panels. |
944 | */ |
945 | if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && |
946 | (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & |
947 | (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { |
948 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
949 | RADEON_PLL_DIV_SEL, |
950 | ~(RADEON_PLL_DIV_SEL)); |
951 | r100_pll_errata_after_index(rdev); |
952 | return; |
953 | } |
954 | } |
955 | |
956 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
957 | RADEON_VCLK_SRC_SEL_CPUCLK, |
958 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
959 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
960 | RADEON_PPLL_RESET |
961 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
962 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
963 | | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), |
964 | ~(RADEON_PPLL_RESET |
965 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
966 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
967 | | RADEON_PPLL_PVG_MASK)); |
968 | |
969 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
970 | RADEON_PLL_DIV_SEL, |
971 | ~(RADEON_PLL_DIV_SEL)); |
972 | r100_pll_errata_after_index(rdev); |
973 | |
974 | if (ASIC_IS_R300(rdev) || |
975 | (rdev->family == CHIP_RS300) || |
976 | (rdev->family == CHIP_RS400) || |
977 | (rdev->family == CHIP_RS480)) { |
978 | if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { |
979 | /* When restoring console mode, use saved PPLL_REF_DIV |
980 | * setting. |
981 | */ |
982 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
983 | pll_ref_div, |
984 | 0); |
985 | } else { |
986 | /* R300 uses ref_div_acc field as real ref divider */ |
987 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
988 | (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), |
989 | ~R300_PPLL_REF_DIV_ACC_MASK); |
990 | } |
991 | } else |
992 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
993 | pll_ref_div, |
994 | ~RADEON_PPLL_REF_DIV_MASK); |
995 | |
996 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
997 | pll_fb_post_div, |
998 | ~RADEON_PPLL_FB3_DIV_MASK); |
999 | |
1000 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
1001 | pll_fb_post_div, |
1002 | ~RADEON_PPLL_POST3_DIV_MASK); |
1003 | |
1004 | radeon_pll_write_update(dev); |
1005 | radeon_pll_wait_for_read_update_complete(dev); |
1006 | |
1007 | WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); |
1008 | |
1009 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
1010 | 0, |
1011 | ~(RADEON_PPLL_RESET |
1012 | | RADEON_PPLL_SLEEP |
1013 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
1014 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); |
1015 | |
1016 | DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n" , |
1017 | pll_ref_div, |
1018 | pll_fb_post_div, |
1019 | (unsigned)htotal_cntl, |
1020 | RREG32_PLL(RADEON_PPLL_CNTL)); |
1021 | DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n" , |
1022 | pll_ref_div & RADEON_PPLL_REF_DIV_MASK, |
1023 | pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, |
1024 | (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); |
1025 | |
1026 | mdelay(50); /* Let the clock to lock */ |
1027 | |
1028 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
1029 | RADEON_VCLK_SRC_SEL_PPLLCLK, |
1030 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
1031 | |
1032 | if (is_tv) |
1033 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
1034 | } |
1035 | } |
1036 | |
1037 | static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, |
1038 | const struct drm_display_mode *mode, |
1039 | struct drm_display_mode *adjusted_mode) |
1040 | { |
1041 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
1042 | return false; |
1043 | return true; |
1044 | } |
1045 | |
1046 | static int radeon_crtc_mode_set(struct drm_crtc *crtc, |
1047 | struct drm_display_mode *mode, |
1048 | struct drm_display_mode *adjusted_mode, |
1049 | int x, int y, struct drm_framebuffer *old_fb) |
1050 | { |
1051 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1052 | |
1053 | /* TODO TV */ |
1054 | radeon_crtc_set_base(crtc, x, y, old_fb); |
1055 | radeon_set_crtc_timing(crtc, adjusted_mode); |
1056 | radeon_set_pll(crtc, adjusted_mode); |
1057 | radeon_overscan_setup(crtc, adjusted_mode); |
1058 | if (radeon_crtc->crtc_id == 0) { |
1059 | radeon_legacy_rmx_mode_set(crtc, adjusted_mode); |
1060 | } else { |
1061 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1062 | /* FIXME: only first crtc has rmx what should we |
1063 | * do ? |
1064 | */ |
1065 | DRM_ERROR("Mode need scaling but only first crtc can do that.\n" ); |
1066 | } |
1067 | } |
1068 | return 0; |
1069 | } |
1070 | |
1071 | static void radeon_crtc_prepare(struct drm_crtc *crtc) |
1072 | { |
1073 | struct drm_device *dev = crtc->dev; |
1074 | struct drm_crtc *crtci; |
1075 | |
1076 | /* |
1077 | * The hardware wedges sometimes if you reconfigure one CRTC |
1078 | * whilst another is running (see fdo bug #24611). |
1079 | */ |
1080 | list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) |
1081 | radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF); |
1082 | } |
1083 | |
1084 | static void radeon_crtc_commit(struct drm_crtc *crtc) |
1085 | { |
1086 | struct drm_device *dev = crtc->dev; |
1087 | struct drm_crtc *crtci; |
1088 | |
1089 | /* |
1090 | * Reenable the CRTCs that should be running. |
1091 | */ |
1092 | list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) { |
1093 | if (crtci->enabled) |
1094 | radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); |
1095 | } |
1096 | } |
1097 | |
1098 | static void radeon_crtc_disable(struct drm_crtc *crtc) |
1099 | { |
1100 | radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
1101 | if (crtc->primary->fb) { |
1102 | int r; |
1103 | struct radeon_framebuffer *radeon_fb; |
1104 | struct radeon_bo *rbo; |
1105 | |
1106 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
1107 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
1108 | r = radeon_bo_reserve(rbo, false); |
1109 | if (unlikely(r)) |
1110 | DRM_ERROR("failed to reserve rbo before unpin\n" ); |
1111 | else { |
1112 | radeon_bo_unpin(rbo); |
1113 | radeon_bo_unreserve(rbo); |
1114 | } |
1115 | } |
1116 | } |
1117 | |
1118 | static const struct drm_crtc_helper_funcs legacy_helper_funcs = { |
1119 | .dpms = radeon_crtc_dpms, |
1120 | .mode_fixup = radeon_crtc_mode_fixup, |
1121 | .mode_set = radeon_crtc_mode_set, |
1122 | .mode_set_base = radeon_crtc_set_base, |
1123 | .mode_set_base_atomic = radeon_crtc_set_base_atomic, |
1124 | .prepare = radeon_crtc_prepare, |
1125 | .commit = radeon_crtc_commit, |
1126 | .load_lut = radeon_crtc_load_lut, |
1127 | .disable = radeon_crtc_disable |
1128 | }; |
1129 | |
1130 | |
1131 | void radeon_legacy_init_crtc(struct drm_device *dev, |
1132 | struct radeon_crtc *radeon_crtc) |
1133 | { |
1134 | if (radeon_crtc->crtc_id == 1) |
1135 | radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; |
1136 | drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); |
1137 | } |
1138 | |