1/* $NetBSD: if_urtwn.c,v 1.50 2016/11/04 20:44:57 mlelstv Exp $ */
2/* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */
3
4/*-
5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
6 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 */
21
22/*-
23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU
24 * RTL8192EU.
25 */
26
27#include <sys/cdefs.h>
28__KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.50 2016/11/04 20:44:57 mlelstv Exp $");
29
30#ifdef _KERNEL_OPT
31#include "opt_inet.h"
32#endif
33
34#include <sys/param.h>
35#include <sys/sockio.h>
36#include <sys/sysctl.h>
37#include <sys/mbuf.h>
38#include <sys/kernel.h>
39#include <sys/socket.h>
40#include <sys/systm.h>
41#include <sys/module.h>
42#include <sys/conf.h>
43#include <sys/device.h>
44
45#include <sys/bus.h>
46#include <machine/endian.h>
47#include <sys/intr.h>
48
49#include <net/bpf.h>
50#include <net/if.h>
51#include <net/if_arp.h>
52#include <net/if_dl.h>
53#include <net/if_ether.h>
54#include <net/if_media.h>
55#include <net/if_types.h>
56
57#include <netinet/in.h>
58#include <netinet/in_systm.h>
59#include <netinet/in_var.h>
60#include <netinet/ip.h>
61#include <netinet/if_inarp.h>
62
63#include <net80211/ieee80211_netbsd.h>
64#include <net80211/ieee80211_var.h>
65#include <net80211/ieee80211_radiotap.h>
66
67#include <dev/firmload.h>
68
69#include <dev/usb/usb.h>
70#include <dev/usb/usbdi.h>
71#include <dev/usb/usbdivar.h>
72#include <dev/usb/usbdi_util.h>
73#include <dev/usb/usbdevs.h>
74
75#include <dev/usb/if_urtwnreg.h>
76#include <dev/usb/if_urtwnvar.h>
77#include <dev/usb/if_urtwn_data.h>
78
79/*
80 * The sc_write_mtx locking is to prevent sequences of writes from
81 * being intermingled with each other. I don't know if this is really
82 * needed. I have added it just to be on the safe side.
83 */
84
85#ifdef URTWN_DEBUG
86#define DBG_INIT __BIT(0)
87#define DBG_FN __BIT(1)
88#define DBG_TX __BIT(2)
89#define DBG_RX __BIT(3)
90#define DBG_STM __BIT(4)
91#define DBG_RF __BIT(5)
92#define DBG_REG __BIT(6)
93#define DBG_ALL 0xffffffffU
94u_int urtwn_debug = 0;
95#define DPRINTFN(n, s) \
96 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0)
97#else
98#define DPRINTFN(n, s)
99#endif
100
101#define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 }
102#define URTWN_RTL8188E_DEV(v,p) \
103 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E }
104#define URTWN_RTL8192EU_DEV(v,p) \
105 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E }
106static const struct urtwn_dev {
107 struct usb_devno dev;
108 uint32_t flags;
109#define FLAG_RTL8188E __BIT(0)
110#define FLAG_RTL8192E __BIT(1)
111} urtwn_devs[] = {
112 URTWN_DEV(ABOCOM, RTL8188CU_1),
113 URTWN_DEV(ABOCOM, RTL8188CU_2),
114 URTWN_DEV(ABOCOM, RTL8192CU),
115 URTWN_DEV(ASUSTEK, RTL8192CU),
116 URTWN_DEV(ASUSTEK, RTL8192CU_3),
117 URTWN_DEV(ASUSTEK, USBN10NANO),
118 URTWN_DEV(ASUSTEK, RTL8192CU_3),
119 URTWN_DEV(AZUREWAVE, RTL8188CE_1),
120 URTWN_DEV(AZUREWAVE, RTL8188CE_2),
121 URTWN_DEV(AZUREWAVE, RTL8188CU),
122 URTWN_DEV(BELKIN, F7D2102),
123 URTWN_DEV(BELKIN, RTL8188CU),
124 URTWN_DEV(BELKIN, RTL8188CUS),
125 URTWN_DEV(BELKIN, RTL8192CU),
126 URTWN_DEV(BELKIN, RTL8192CU_1),
127 URTWN_DEV(BELKIN, RTL8192CU_2),
128 URTWN_DEV(CHICONY, RTL8188CUS_1),
129 URTWN_DEV(CHICONY, RTL8188CUS_2),
130 URTWN_DEV(CHICONY, RTL8188CUS_3),
131 URTWN_DEV(CHICONY, RTL8188CUS_4),
132 URTWN_DEV(CHICONY, RTL8188CUS_5),
133 URTWN_DEV(CHICONY, RTL8188CUS_6),
134 URTWN_DEV(COMPARE, RTL8192CU),
135 URTWN_DEV(COREGA, RTL8192CU),
136 URTWN_DEV(DLINK, DWA131B),
137 URTWN_DEV(DLINK, RTL8188CU),
138 URTWN_DEV(DLINK, RTL8192CU_1),
139 URTWN_DEV(DLINK, RTL8192CU_2),
140 URTWN_DEV(DLINK, RTL8192CU_3),
141 URTWN_DEV(DLINK, RTL8192CU_4),
142 URTWN_DEV(EDIMAX, RTL8188CU),
143 URTWN_DEV(EDIMAX, RTL8192CU),
144 URTWN_DEV(FEIXUN, RTL8188CU),
145 URTWN_DEV(FEIXUN, RTL8192CU),
146 URTWN_DEV(GUILLEMOT, HWNUP150),
147 URTWN_DEV(GUILLEMOT, RTL8192CU),
148 URTWN_DEV(HAWKING, RTL8192CU),
149 URTWN_DEV(HAWKING, RTL8192CU_2),
150 URTWN_DEV(HP3, RTL8188CU),
151 URTWN_DEV(IODATA, WNG150UM),
152 URTWN_DEV(IODATA, RTL8192CU),
153 URTWN_DEV(NETGEAR, WNA1000M),
154 URTWN_DEV(NETGEAR, RTL8192CU),
155 URTWN_DEV(NETGEAR4, RTL8188CU),
156 URTWN_DEV(NOVATECH, RTL8188CU),
157 URTWN_DEV(PLANEX2, RTL8188CU_1),
158 URTWN_DEV(PLANEX2, RTL8188CU_2),
159 URTWN_DEV(PLANEX2, RTL8192CU),
160 URTWN_DEV(PLANEX2, RTL8188CU_3),
161 URTWN_DEV(PLANEX2, RTL8188CU_4),
162 URTWN_DEV(PLANEX2, RTL8188CUS),
163 URTWN_DEV(REALTEK, RTL8188CE_0),
164 URTWN_DEV(REALTEK, RTL8188CE_1),
165 URTWN_DEV(REALTEK, RTL8188CTV),
166 URTWN_DEV(REALTEK, RTL8188CU_0),
167 URTWN_DEV(REALTEK, RTL8188CU_1),
168 URTWN_DEV(REALTEK, RTL8188CU_2),
169 URTWN_DEV(REALTEK, RTL8188CU_3),
170 URTWN_DEV(REALTEK, RTL8188CU_COMBO),
171 URTWN_DEV(REALTEK, RTL8188CUS),
172 URTWN_DEV(REALTEK, RTL8188RU),
173 URTWN_DEV(REALTEK, RTL8188RU_2),
174 URTWN_DEV(REALTEK, RTL8188RU_3),
175 URTWN_DEV(REALTEK, RTL8191CU),
176 URTWN_DEV(REALTEK, RTL8192CE),
177 URTWN_DEV(REALTEK, RTL8192CU),
178 URTWN_DEV(SITECOMEU, RTL8188CU),
179 URTWN_DEV(SITECOMEU, RTL8188CU_2),
180 URTWN_DEV(SITECOMEU, RTL8192CU),
181 URTWN_DEV(SITECOMEU, RTL8192CUR2),
182 URTWN_DEV(TPLINK, RTL8192CU),
183 URTWN_DEV(TRENDNET, RTL8188CU),
184 URTWN_DEV(TRENDNET, RTL8192CU),
185 URTWN_DEV(ZYXEL, RTL8192CU),
186
187 /* URTWN_RTL8188E */
188 URTWN_RTL8188E_DEV(DLINK, DWA125D1),
189 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M),
190 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV),
191 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU),
192 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU),
193
194 /* URTWN_RTL8192EU */
195 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU),
196};
197#undef URTWN_DEV
198#undef URTWN_RTL8188E_DEV
199#undef URTWN_RTL8192EU_DEV
200
201static int urtwn_match(device_t, cfdata_t, void *);
202static void urtwn_attach(device_t, device_t, void *);
203static int urtwn_detach(device_t, int);
204static int urtwn_activate(device_t, enum devact);
205
206CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match,
207 urtwn_attach, urtwn_detach, urtwn_activate);
208
209static int urtwn_open_pipes(struct urtwn_softc *);
210static void urtwn_close_pipes(struct urtwn_softc *);
211static int urtwn_alloc_rx_list(struct urtwn_softc *);
212static void urtwn_free_rx_list(struct urtwn_softc *);
213static int urtwn_alloc_tx_list(struct urtwn_softc *);
214static void urtwn_free_tx_list(struct urtwn_softc *);
215static void urtwn_task(void *);
216static void urtwn_do_async(struct urtwn_softc *,
217 void (*)(struct urtwn_softc *, void *), void *, int);
218static void urtwn_wait_async(struct urtwn_softc *);
219static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *,
220 int);
221static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t);
222static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t);
223static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t);
224static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *,
225 int);
226static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *,
227 int);
228static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t);
229static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t);
230static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t);
231static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int);
232static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t,
233 uint32_t);
234static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t,
235 uint32_t);
236static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t,
237 uint32_t);
238static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t);
239static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t);
240static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t);
241static void urtwn_efuse_read(struct urtwn_softc *);
242static void urtwn_efuse_switch_power(struct urtwn_softc *);
243static int urtwn_read_chipid(struct urtwn_softc *);
244#ifdef URTWN_DEBUG
245static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *);
246#endif
247static void urtwn_read_rom(struct urtwn_softc *);
248static void urtwn_r88e_read_rom(struct urtwn_softc *);
249static int urtwn_media_change(struct ifnet *);
250static int urtwn_ra_init(struct urtwn_softc *);
251static int urtwn_get_nettype(struct urtwn_softc *);
252static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t);
253static void urtwn_tsf_sync_enable(struct urtwn_softc *);
254static void urtwn_set_led(struct urtwn_softc *, int, int);
255static void urtwn_calib_to(void *);
256static void urtwn_calib_to_cb(struct urtwn_softc *, void *);
257static void urtwn_next_scan(void *);
258static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state,
259 int);
260static void urtwn_newstate_cb(struct urtwn_softc *, void *);
261static int urtwn_wme_update(struct ieee80211com *);
262static void urtwn_wme_update_cb(struct urtwn_softc *, void *);
263static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t);
264static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *);
265static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *);
266static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int);
267static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status);
268static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status);
269static int urtwn_tx(struct urtwn_softc *, struct mbuf *,
270 struct ieee80211_node *, struct urtwn_tx_data *);
271static struct urtwn_tx_data *
272 urtwn_get_tx_data(struct urtwn_softc *, size_t);
273static void urtwn_start(struct ifnet *);
274static void urtwn_watchdog(struct ifnet *);
275static int urtwn_ioctl(struct ifnet *, u_long, void *);
276static int urtwn_r92c_power_on(struct urtwn_softc *);
277static int urtwn_r92e_power_on(struct urtwn_softc *);
278static int urtwn_r88e_power_on(struct urtwn_softc *);
279static int urtwn_llt_init(struct urtwn_softc *);
280static void urtwn_fw_reset(struct urtwn_softc *);
281static void urtwn_r88e_fw_reset(struct urtwn_softc *);
282static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int);
283static int urtwn_load_firmware(struct urtwn_softc *);
284static int urtwn_r92c_dma_init(struct urtwn_softc *);
285static int urtwn_r88e_dma_init(struct urtwn_softc *);
286static void urtwn_mac_init(struct urtwn_softc *);
287static void urtwn_bb_init(struct urtwn_softc *);
288static void urtwn_rf_init(struct urtwn_softc *);
289static void urtwn_cam_init(struct urtwn_softc *);
290static void urtwn_pa_bias_init(struct urtwn_softc *);
291static void urtwn_rxfilter_init(struct urtwn_softc *);
292static void urtwn_edca_init(struct urtwn_softc *);
293static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]);
294static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int,
295 uint16_t[]);
296static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int,
297 u_int, uint16_t[]);
298static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int);
299static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *,
300 u_int);
301static void urtwn_iq_calib(struct urtwn_softc *, bool);
302static void urtwn_lc_calib(struct urtwn_softc *);
303static void urtwn_temp_calib(struct urtwn_softc *);
304static int urtwn_init(struct ifnet *);
305static void urtwn_stop(struct ifnet *, int);
306static int urtwn_reset(struct ifnet *);
307static void urtwn_chip_stop(struct urtwn_softc *);
308static void urtwn_newassoc(struct ieee80211_node *, int);
309static void urtwn_delay_ms(struct urtwn_softc *, int ms);
310
311/* Aliases. */
312#define urtwn_bb_write urtwn_write_4
313#define urtwn_bb_read urtwn_read_4
314
315#define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p))
316
317static const uint16_t addaReg[] = {
318 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA,
319 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON,
320 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK,
321 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX,
322 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN
323};
324
325static int
326urtwn_match(device_t parent, cfdata_t match, void *aux)
327{
328 struct usb_attach_arg *uaa = aux;
329
330 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) !=
331 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
332}
333
334static void
335urtwn_attach(device_t parent, device_t self, void *aux)
336{
337 struct urtwn_softc *sc = device_private(self);
338 struct ieee80211com *ic = &sc->sc_ic;
339 struct ifnet *ifp = &sc->sc_if;
340 struct usb_attach_arg *uaa = aux;
341 char *devinfop;
342 const struct urtwn_dev *dev;
343 usb_device_request_t req;
344 size_t i;
345 int error;
346
347 sc->sc_dev = self;
348 sc->sc_udev = uaa->uaa_device;
349
350 sc->chip = 0;
351 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product);
352 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E))
353 SET(sc->chip, URTWN_CHIP_88E);
354 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E))
355 SET(sc->chip, URTWN_CHIP_92EU);
356
357 aprint_naive("\n");
358 aprint_normal("\n");
359
360 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
361
362 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0);
363 aprint_normal_dev(self, "%s\n", devinfop);
364 usbd_devinfo_free(devinfop);
365
366 req.bmRequestType = UT_WRITE_DEVICE;
367 req.bRequest = UR_SET_FEATURE;
368 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP);
369 USETW(req.wIndex, UHF_PORT_SUSPEND);
370 USETW(req.wLength, 0);
371
372 (void) usbd_do_request(sc->sc_udev, &req, 0);
373
374 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET);
375 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE);
376 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE);
377 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE);
378 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE);
379
380 usb_init_task(&sc->sc_task, urtwn_task, sc, 0);
381
382 callout_init(&sc->sc_scan_to, 0);
383 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc);
384 callout_init(&sc->sc_calib_to, 0);
385 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc);
386
387 error = usbd_set_config_no(sc->sc_udev, 1, 0);
388 if (error != 0) {
389 aprint_error_dev(self, "failed to set configuration"
390 ", err=%s\n", usbd_errstr(error));
391 goto fail;
392 }
393
394 /* Get the first interface handle. */
395 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface);
396 if (error != 0) {
397 aprint_error_dev(self, "could not get interface handle\n");
398 goto fail;
399 }
400
401 error = urtwn_read_chipid(sc);
402 if (error != 0) {
403 aprint_error_dev(self, "unsupported test chip\n");
404 goto fail;
405 }
406
407 /* Determine number of Tx/Rx chains. */
408 if (sc->chip & URTWN_CHIP_92C) {
409 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2;
410 sc->nrxchains = 2;
411 } else if (sc->chip & URTWN_CHIP_92EU) {
412 sc->ntxchains = 2;
413 sc->nrxchains = 2;
414 } else {
415 sc->ntxchains = 1;
416 sc->nrxchains = 1;
417 }
418
419 if (ISSET(sc->chip, URTWN_CHIP_88E) ||
420 ISSET(sc->chip, URTWN_CHIP_92EU))
421 urtwn_r88e_read_rom(sc);
422 else
423 urtwn_read_rom(sc);
424
425 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n",
426 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" :
427 (sc->chip & URTWN_CHIP_92C) ? "8192CU" :
428 (sc->chip & URTWN_CHIP_88E) ? "8188EU" :
429 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" :
430 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" :
431 "8188CUS", sc->ntxchains, sc->nrxchains,
432 ether_sprintf(ic->ic_myaddr));
433
434 error = urtwn_open_pipes(sc);
435 if (error != 0) {
436 aprint_error_dev(sc->sc_dev, "could not open pipes\n");
437 goto fail;
438 }
439 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n",
440 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "",
441 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : "");
442
443 /*
444 * Setup the 802.11 device.
445 */
446 ic->ic_ifp = ifp;
447 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */
448 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */
449 ic->ic_state = IEEE80211_S_INIT;
450
451 /* Set device capabilities. */
452 ic->ic_caps =
453 IEEE80211_C_MONITOR | /* Monitor mode supported. */
454 IEEE80211_C_IBSS | /* IBSS mode supported */
455 IEEE80211_C_HOSTAP | /* HostAp mode supported */
456 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */
457 IEEE80211_C_SHSLOT | /* Short slot time supported. */
458 IEEE80211_C_WME | /* 802.11e */
459 IEEE80211_C_WPA; /* 802.11i */
460
461 /* Set supported .11b and .11g rates. */
462 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b;
463 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g;
464
465 /* Set supported .11b and .11g channels (1 through 14). */
466 for (i = 1; i <= 14; i++) {
467 ic->ic_channels[i].ic_freq =
468 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
469 ic->ic_channels[i].ic_flags =
470 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
471 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
472 }
473
474 ifp->if_softc = sc;
475 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
476 ifp->if_init = urtwn_init;
477 ifp->if_ioctl = urtwn_ioctl;
478 ifp->if_start = urtwn_start;
479 ifp->if_watchdog = urtwn_watchdog;
480 IFQ_SET_READY(&ifp->if_snd);
481 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
482
483 if_attach(ifp);
484 ieee80211_ifattach(ic);
485
486 /* override default methods */
487 ic->ic_newassoc = urtwn_newassoc;
488 ic->ic_reset = urtwn_reset;
489 ic->ic_wme.wme_update = urtwn_wme_update;
490
491 /* Override state transition machine. */
492 sc->sc_newstate = ic->ic_newstate;
493 ic->ic_newstate = urtwn_newstate;
494 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status);
495
496 bpf_attach2(ifp, DLT_IEEE802_11_RADIO,
497 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN,
498 &sc->sc_drvbpf);
499
500 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu);
501 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
502 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT);
503
504 sc->sc_txtap_len = sizeof(sc->sc_txtapu);
505 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
506 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT);
507
508 ieee80211_announce(ic);
509
510 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev);
511
512 if (!pmf_device_register(self, NULL, NULL))
513 aprint_error_dev(self, "couldn't establish power handler\n");
514
515 SET(sc->sc_flags, URTWN_FLAG_ATTACHED);
516 return;
517
518 fail:
519 sc->sc_dying = 1;
520 aprint_error_dev(self, "attach failed\n");
521}
522
523static int
524urtwn_detach(device_t self, int flags)
525{
526 struct urtwn_softc *sc = device_private(self);
527 struct ifnet *ifp = &sc->sc_if;
528 int s;
529
530 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
531
532 pmf_device_deregister(self);
533
534 s = splusb();
535
536 sc->sc_dying = 1;
537
538 callout_stop(&sc->sc_scan_to);
539 callout_stop(&sc->sc_calib_to);
540
541 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) {
542 usb_rem_task(sc->sc_udev, &sc->sc_task);
543 urtwn_stop(ifp, 0);
544
545 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
546 bpf_detach(ifp);
547 ieee80211_ifdetach(&sc->sc_ic);
548 if_detach(ifp);
549
550 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */
551 urtwn_close_pipes(sc);
552 }
553
554 splx(s);
555
556 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev);
557
558 callout_destroy(&sc->sc_scan_to);
559 callout_destroy(&sc->sc_calib_to);
560
561 mutex_destroy(&sc->sc_write_mtx);
562 mutex_destroy(&sc->sc_fwcmd_mtx);
563 mutex_destroy(&sc->sc_tx_mtx);
564 mutex_destroy(&sc->sc_rx_mtx);
565 mutex_destroy(&sc->sc_task_mtx);
566
567 return 0;
568}
569
570static int
571urtwn_activate(device_t self, enum devact act)
572{
573 struct urtwn_softc *sc = device_private(self);
574
575 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
576
577 switch (act) {
578 case DVACT_DEACTIVATE:
579 if_deactivate(sc->sc_ic.ic_ifp);
580 return 0;
581 default:
582 return EOPNOTSUPP;
583 }
584}
585
586static int
587urtwn_open_pipes(struct urtwn_softc *sc)
588{
589 /* Bulk-out endpoints addresses (from highest to lowest prio). */
590 static uint8_t epaddr[3];
591 static uint8_t rxepaddr[3];
592 usb_interface_descriptor_t *id;
593 usb_endpoint_descriptor_t *ed;
594 size_t i, ntx = 0, nrx = 0;
595 int error;
596
597 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
598
599 /* Determine the number of bulk-out pipes. */
600 id = usbd_get_interface_descriptor(sc->sc_iface);
601 for (i = 0; i < id->bNumEndpoints; i++) {
602 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i);
603 if (ed != NULL &&
604 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK &&
605 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) {
606 epaddr[ntx] = ed->bEndpointAddress;
607 ntx++;
608 }
609 if (ed != NULL &&
610 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK &&
611 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) {
612 rxepaddr[nrx] = ed->bEndpointAddress;
613 nrx++;
614 }
615 }
616 DPRINTFN(DBG_INIT, ("%s: %s: found %zd bulk-out pipes\n",
617 device_xname(sc->sc_dev), __func__, ntx));
618 if (ntx == 0 || ntx > R92C_MAX_EPOUT) {
619 aprint_error_dev(sc->sc_dev,
620 "%zd: invalid number of Tx bulk pipes\n", ntx);
621 return EIO;
622 }
623 sc->rx_npipe = nrx;
624 sc->tx_npipe = ntx;
625
626 /* Open bulk-in pipe at address 0x81. */
627 for (i = 0; i < nrx; i++) {
628 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i],
629 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]);
630 if (error != 0) {
631 aprint_error_dev(sc->sc_dev,
632 "could not open Rx bulk pipe 0x%02x: %d\n",
633 rxepaddr[i], error);
634 goto fail;
635 }
636 }
637
638 /* Open bulk-out pipes (up to 3). */
639 for (i = 0; i < ntx; i++) {
640 error = usbd_open_pipe(sc->sc_iface, epaddr[i],
641 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]);
642 if (error != 0) {
643 aprint_error_dev(sc->sc_dev,
644 "could not open Tx bulk pipe 0x%02x: %d\n",
645 epaddr[i], error);
646 goto fail;
647 }
648 }
649
650 /* Map 802.11 access categories to USB pipes. */
651 sc->ac2idx[WME_AC_BK] =
652 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0);
653 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0;
654 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */
655
656 fail:
657 if (error != 0)
658 urtwn_close_pipes(sc);
659 return error;
660}
661
662static void
663urtwn_close_pipes(struct urtwn_softc *sc)
664{
665 struct usbd_pipe *pipe;
666 size_t i;
667
668 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
669
670 /* Close Rx pipes. */
671 CTASSERT(sizeof(pipe) == sizeof(void *));
672 for (i = 0; i < sc->rx_npipe; i++) {
673 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL);
674 if (pipe != NULL) {
675 usbd_close_pipe(pipe);
676 }
677 }
678
679 /* Close Tx pipes. */
680 for (i = 0; i < sc->tx_npipe; i++) {
681 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL);
682 if (pipe != NULL) {
683 usbd_close_pipe(pipe);
684 }
685 }
686}
687
688static int
689urtwn_alloc_rx_list(struct urtwn_softc *sc)
690{
691 struct urtwn_rx_data *data;
692 size_t i;
693 int error = 0;
694
695 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
696
697 for (size_t j = 0; j < sc->rx_npipe; j++) {
698 TAILQ_INIT(&sc->rx_free_list[j]);
699 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) {
700 data = &sc->rx_data[j][i];
701
702 data->sc = sc; /* Backpointer for callbacks. */
703
704 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ,
705 USBD_SHORT_XFER_OK, 0, &data->xfer);
706 if (error) {
707 aprint_error_dev(sc->sc_dev,
708 "could not allocate xfer\n");
709 break;
710 }
711
712 data->buf = usbd_get_buffer(data->xfer);
713 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next);
714 }
715 }
716 if (error != 0)
717 urtwn_free_rx_list(sc);
718 return error;
719}
720
721static void
722urtwn_free_rx_list(struct urtwn_softc *sc)
723{
724 struct usbd_xfer *xfer;
725 size_t i;
726
727 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
728
729 /* NB: Caller must abort pipe first. */
730 for (size_t j = 0; j < sc->rx_npipe; j++) {
731 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) {
732 CTASSERT(sizeof(xfer) == sizeof(void *));
733 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL);
734 if (xfer != NULL)
735 usbd_destroy_xfer(xfer);
736 }
737 }
738}
739
740static int
741urtwn_alloc_tx_list(struct urtwn_softc *sc)
742{
743 struct urtwn_tx_data *data;
744 size_t i;
745 int error = 0;
746
747 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
748
749 mutex_enter(&sc->sc_tx_mtx);
750 for (size_t j = 0; j < sc->tx_npipe; j++) {
751 TAILQ_INIT(&sc->tx_free_list[j]);
752 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) {
753 data = &sc->tx_data[j][i];
754
755 data->sc = sc; /* Backpointer for callbacks. */
756 data->pidx = j;
757
758 error = usbd_create_xfer(sc->tx_pipe[j],
759 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0,
760 &data->xfer);
761 if (error) {
762 aprint_error_dev(sc->sc_dev,
763 "could not allocate xfer\n");
764 goto fail;
765 }
766
767 data->buf = usbd_get_buffer(data->xfer);
768
769 /* Append this Tx buffer to our free list. */
770 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next);
771 }
772 }
773 mutex_exit(&sc->sc_tx_mtx);
774 return 0;
775
776 fail:
777 urtwn_free_tx_list(sc);
778 mutex_exit(&sc->sc_tx_mtx);
779 return error;
780}
781
782static void
783urtwn_free_tx_list(struct urtwn_softc *sc)
784{
785 struct usbd_xfer *xfer;
786 size_t i;
787
788 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
789
790 /* NB: Caller must abort pipe first. */
791 for (size_t j = 0; j < sc->tx_npipe; j++) {
792 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) {
793 CTASSERT(sizeof(xfer) == sizeof(void *));
794 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL);
795 if (xfer != NULL)
796 usbd_destroy_xfer(xfer);
797 }
798 }
799}
800
801static void
802urtwn_task(void *arg)
803{
804 struct urtwn_softc *sc = arg;
805 struct urtwn_host_cmd_ring *ring = &sc->cmdq;
806 struct urtwn_host_cmd *cmd;
807 int s;
808
809 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
810
811 /* Process host commands. */
812 s = splusb();
813 mutex_spin_enter(&sc->sc_task_mtx);
814 while (ring->next != ring->cur) {
815 cmd = &ring->cmd[ring->next];
816 mutex_spin_exit(&sc->sc_task_mtx);
817 splx(s);
818 /* Invoke callback with kernel lock held. */
819 cmd->cb(sc, cmd->data);
820 s = splusb();
821 mutex_spin_enter(&sc->sc_task_mtx);
822 ring->queued--;
823 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT;
824 }
825 mutex_spin_exit(&sc->sc_task_mtx);
826 wakeup(&sc->cmdq);
827 splx(s);
828}
829
830static void
831urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *),
832 void *arg, int len)
833{
834 struct urtwn_host_cmd_ring *ring = &sc->cmdq;
835 struct urtwn_host_cmd *cmd;
836 int s;
837
838 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n",
839 device_xname(sc->sc_dev), __func__, cb, arg, len));
840
841 s = splusb();
842 mutex_spin_enter(&sc->sc_task_mtx);
843 cmd = &ring->cmd[ring->cur];
844 cmd->cb = cb;
845 KASSERT(len <= sizeof(cmd->data));
846 memcpy(cmd->data, arg, len);
847 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT;
848
849 /* If there is no pending command already, schedule a task. */
850 if (!sc->sc_dying && ++ring->queued == 1) {
851 mutex_spin_exit(&sc->sc_task_mtx);
852 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER);
853 } else
854 mutex_spin_exit(&sc->sc_task_mtx);
855 splx(s);
856}
857
858static void
859urtwn_wait_async(struct urtwn_softc *sc)
860{
861
862 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
863
864 /* Wait for all queued asynchronous commands to complete. */
865 while (sc->cmdq.queued > 0)
866 tsleep(&sc->cmdq, 0, "endtask", 0);
867}
868
869static int
870urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
871 int len)
872{
873 usb_device_request_t req;
874 usbd_status error;
875
876 KASSERT(mutex_owned(&sc->sc_write_mtx));
877
878 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
879 req.bRequest = R92C_REQ_REGS;
880 USETW(req.wValue, addr);
881 USETW(req.wIndex, 0);
882 USETW(req.wLength, len);
883 error = usbd_do_request(sc->sc_udev, &req, buf);
884 if (error != USBD_NORMAL_COMPLETION) {
885 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n",
886 device_xname(sc->sc_dev), __func__, error, addr, len));
887 }
888 return error;
889}
890
891static void
892urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val)
893{
894
895 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n",
896 device_xname(sc->sc_dev), __func__, addr, val));
897
898 urtwn_write_region_1(sc, addr, &val, 1);
899}
900
901static void
902urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val)
903{
904 uint8_t buf[2];
905
906 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n",
907 device_xname(sc->sc_dev), __func__, addr, val));
908
909 buf[0] = (uint8_t)val;
910 buf[1] = (uint8_t)(val >> 8);
911 urtwn_write_region_1(sc, addr, buf, 2);
912}
913
914static void
915urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val)
916{
917 uint8_t buf[4];
918
919 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n",
920 device_xname(sc->sc_dev), __func__, addr, val));
921
922 buf[0] = (uint8_t)val;
923 buf[1] = (uint8_t)(val >> 8);
924 buf[2] = (uint8_t)(val >> 16);
925 buf[3] = (uint8_t)(val >> 24);
926 urtwn_write_region_1(sc, addr, buf, 4);
927}
928
929static int
930urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len)
931{
932
933 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n",
934 device_xname(sc->sc_dev), __func__, addr, len));
935
936 return urtwn_write_region_1(sc, addr, buf, len);
937}
938
939static int
940urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
941 int len)
942{
943 usb_device_request_t req;
944 usbd_status error;
945
946 req.bmRequestType = UT_READ_VENDOR_DEVICE;
947 req.bRequest = R92C_REQ_REGS;
948 USETW(req.wValue, addr);
949 USETW(req.wIndex, 0);
950 USETW(req.wLength, len);
951 error = usbd_do_request(sc->sc_udev, &req, buf);
952 if (error != USBD_NORMAL_COMPLETION) {
953 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n",
954 device_xname(sc->sc_dev), __func__, error, addr, len));
955 }
956 return error;
957}
958
959static uint8_t
960urtwn_read_1(struct urtwn_softc *sc, uint16_t addr)
961{
962 uint8_t val;
963
964 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION)
965 return 0xff;
966
967 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n",
968 device_xname(sc->sc_dev), __func__, addr, val));
969 return val;
970}
971
972static uint16_t
973urtwn_read_2(struct urtwn_softc *sc, uint16_t addr)
974{
975 uint8_t buf[2];
976 uint16_t val;
977
978 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION)
979 return 0xffff;
980
981 val = LE_READ_2(&buf[0]);
982 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n",
983 device_xname(sc->sc_dev), __func__, addr, val));
984 return val;
985}
986
987static uint32_t
988urtwn_read_4(struct urtwn_softc *sc, uint16_t addr)
989{
990 uint8_t buf[4];
991 uint32_t val;
992
993 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION)
994 return 0xffffffff;
995
996 val = LE_READ_4(&buf[0]);
997 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n",
998 device_xname(sc->sc_dev), __func__, addr, val));
999 return val;
1000}
1001
1002static int
1003urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len)
1004{
1005 struct r92c_fw_cmd cmd;
1006 uint8_t *cp;
1007 int fwcur;
1008 int ntries;
1009
1010 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n",
1011 device_xname(sc->sc_dev), __func__, id, buf, len));
1012
1013 KASSERT(mutex_owned(&sc->sc_write_mtx));
1014
1015 mutex_enter(&sc->sc_fwcmd_mtx);
1016 fwcur = sc->fwcur;
1017 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX;
1018 mutex_exit(&sc->sc_fwcmd_mtx);
1019
1020 /* Wait for current FW box to be empty. */
1021 for (ntries = 0; ntries < 100; ntries++) {
1022 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur)))
1023 break;
1024 DELAY(10);
1025 }
1026 if (ntries == 100) {
1027 aprint_error_dev(sc->sc_dev,
1028 "could not send firmware command %d\n", id);
1029 return ETIMEDOUT;
1030 }
1031
1032 memset(&cmd, 0, sizeof(cmd));
1033 KASSERT(len <= sizeof(cmd.msg));
1034 memcpy(cmd.msg, buf, len);
1035
1036 /* Write the first word last since that will trigger the FW. */
1037 cp = (uint8_t *)&cmd;
1038 cmd.id = id;
1039 if (len >= 4) {
1040 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) {
1041 cmd.id |= R92C_CMD_FLAG_EXT;
1042 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur),
1043 &cp[1], 2);
1044 urtwn_write_4(sc, R92C_HMEBOX(fwcur),
1045 cp[0] + (cp[3] << 8) + (cp[4] << 16) +
1046 (cp[5] << 24));
1047 } else {
1048 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur),
1049 &cp[4], 2);
1050 urtwn_write_4(sc, R92C_HMEBOX(fwcur),
1051 cp[0] + (cp[1] << 8) + (cp[2] << 16) +
1052 (cp[3] << 24));
1053 }
1054 } else {
1055 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len);
1056 }
1057
1058 return 0;
1059}
1060
1061static __inline void
1062urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val)
1063{
1064
1065 sc->sc_rf_write(sc, chain, addr, val);
1066}
1067
1068static void
1069urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr,
1070 uint32_t val)
1071{
1072
1073 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1074 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
1075}
1076
1077static void
1078urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr,
1079 uint32_t val)
1080{
1081
1082 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1083 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
1084}
1085
1086static void
1087urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr,
1088 uint32_t val)
1089{
1090
1091 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1092 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
1093}
1094
1095static uint32_t
1096urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr)
1097{
1098 uint32_t reg[R92C_MAX_CHAINS], val;
1099
1100 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
1101 if (chain != 0) {
1102 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
1103 }
1104
1105 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1106 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
1107 DELAY(1000);
1108
1109 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
1110 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
1111 R92C_HSSI_PARAM2_READ_EDGE);
1112 DELAY(1000);
1113
1114 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1115 reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
1116 DELAY(1000);
1117
1118 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) {
1119 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
1120 } else {
1121 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
1122 }
1123 return MS(val, R92C_LSSI_READBACK_DATA);
1124}
1125
1126static int
1127urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data)
1128{
1129 int ntries;
1130
1131 KASSERT(mutex_owned(&sc->sc_write_mtx));
1132
1133 urtwn_write_4(sc, R92C_LLT_INIT,
1134 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
1135 SM(R92C_LLT_INIT_ADDR, addr) |
1136 SM(R92C_LLT_INIT_DATA, data));
1137 /* Wait for write operation to complete. */
1138 for (ntries = 0; ntries < 20; ntries++) {
1139 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
1140 R92C_LLT_INIT_OP_NO_ACTIVE) {
1141 /* Done */
1142 return 0;
1143 }
1144 DELAY(5);
1145 }
1146 return ETIMEDOUT;
1147}
1148
1149static uint8_t
1150urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr)
1151{
1152 uint32_t reg;
1153 int ntries;
1154
1155 KASSERT(mutex_owned(&sc->sc_write_mtx));
1156
1157 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1158 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr);
1159 reg &= ~R92C_EFUSE_CTRL_VALID;
1160 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg);
1161
1162 /* Wait for read operation to complete. */
1163 for (ntries = 0; ntries < 100; ntries++) {
1164 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1165 if (reg & R92C_EFUSE_CTRL_VALID) {
1166 /* Done */
1167 return MS(reg, R92C_EFUSE_CTRL_DATA);
1168 }
1169 DELAY(5);
1170 }
1171 aprint_error_dev(sc->sc_dev,
1172 "could not read efuse byte at address 0x%04x\n", addr);
1173 return 0xff;
1174}
1175
1176static void
1177urtwn_efuse_read(struct urtwn_softc *sc)
1178{
1179 uint8_t *rom = (uint8_t *)&sc->rom;
1180 uint32_t reg;
1181 uint16_t addr = 0;
1182 uint8_t off, msk;
1183 size_t i;
1184
1185 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1186
1187 KASSERT(mutex_owned(&sc->sc_write_mtx));
1188
1189 urtwn_efuse_switch_power(sc);
1190
1191 memset(&sc->rom, 0xff, sizeof(sc->rom));
1192 while (addr < 512) {
1193 reg = urtwn_efuse_read_1(sc, addr);
1194 if (reg == 0xff)
1195 break;
1196 addr++;
1197 off = reg >> 4;
1198 msk = reg & 0xf;
1199 for (i = 0; i < 4; i++) {
1200 if (msk & (1U << i))
1201 continue;
1202
1203 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr);
1204 addr++;
1205 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr);
1206 addr++;
1207 }
1208 }
1209#ifdef URTWN_DEBUG
1210 if (urtwn_debug & DBG_INIT) {
1211 /* Dump ROM content. */
1212 printf("%s: %s", device_xname(sc->sc_dev), __func__);
1213 for (i = 0; i < (int)sizeof(sc->rom); i++)
1214 printf(":%02x", rom[i]);
1215 printf("\n");
1216 }
1217#endif
1218}
1219
1220static void
1221urtwn_efuse_switch_power(struct urtwn_softc *sc)
1222{
1223 uint32_t reg;
1224
1225 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);
1226 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
1227 urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
1228 reg | R92C_SYS_ISO_CTRL_PWC_EV12V);
1229 }
1230 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
1231 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {
1232 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
1233 reg | R92C_SYS_FUNC_EN_ELDR);
1234 }
1235 reg = urtwn_read_2(sc, R92C_SYS_CLKR);
1236 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=
1237 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) {
1238 urtwn_write_2(sc, R92C_SYS_CLKR,
1239 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
1240 }
1241}
1242
1243static int
1244urtwn_read_chipid(struct urtwn_softc *sc)
1245{
1246 uint32_t reg;
1247
1248 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1249
1250 if (ISSET(sc->chip, URTWN_CHIP_88E) ||
1251 ISSET(sc->chip, URTWN_CHIP_92EU))
1252 return 0;
1253
1254 reg = urtwn_read_4(sc, R92C_SYS_CFG);
1255 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) {
1256 /* test chip, not supported */
1257 return EIO;
1258 }
1259 if (reg & R92C_SYS_CFG_TYPE_92C) {
1260 sc->chip |= URTWN_CHIP_92C;
1261 /* Check if it is a castrated 8192C. */
1262 if (MS(urtwn_read_4(sc, R92C_HPON_FSM),
1263 R92C_HPON_FSM_CHIP_BONDING_ID) ==
1264 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) {
1265 sc->chip |= URTWN_CHIP_92C_1T2R;
1266 }
1267 }
1268 if (reg & R92C_SYS_CFG_VENDOR_UMC) {
1269 sc->chip |= URTWN_CHIP_UMC;
1270 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) {
1271 sc->chip |= URTWN_CHIP_UMC_A_CUT;
1272 }
1273 }
1274 return 0;
1275}
1276
1277#ifdef URTWN_DEBUG
1278static void
1279urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp)
1280{
1281
1282 aprint_normal_dev(sc->sc_dev,
1283 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n",
1284 rp->id, rp->dbg_sel, rp->vid, rp->pid);
1285
1286 aprint_normal_dev(sc->sc_dev,
1287 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n",
1288 rp->usb_opt, rp->ep_setting, rp->usb_phy);
1289
1290 aprint_normal_dev(sc->sc_dev,
1291 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n",
1292 rp->macaddr[0], rp->macaddr[1],
1293 rp->macaddr[2], rp->macaddr[3],
1294 rp->macaddr[4], rp->macaddr[5]);
1295
1296 aprint_normal_dev(sc->sc_dev,
1297 "string %s, subcustomer_id 0x%x\n",
1298 rp->string, rp->subcustomer_id);
1299
1300 aprint_normal_dev(sc->sc_dev,
1301 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n",
1302 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2],
1303 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]);
1304
1305 aprint_normal_dev(sc->sc_dev,
1306 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n",
1307 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1],
1308 rp->ht40_1s_tx_pwr[0][2],
1309 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1],
1310 rp->ht40_1s_tx_pwr[1][2]);
1311
1312 aprint_normal_dev(sc->sc_dev,
1313 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n",
1314 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf,
1315 rp->ht40_2s_tx_pwr_diff[2] & 0xf,
1316 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf,
1317 rp->ht40_2s_tx_pwr_diff[2] >> 4);
1318
1319 aprint_normal_dev(sc->sc_dev,
1320 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n",
1321 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf,
1322 rp->ht20_tx_pwr_diff[2] & 0xf,
1323 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4,
1324 rp->ht20_tx_pwr_diff[2] >> 4);
1325
1326 aprint_normal_dev(sc->sc_dev,
1327 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n",
1328 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf,
1329 rp->ofdm_tx_pwr_diff[2] & 0xf,
1330 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4,
1331 rp->ofdm_tx_pwr_diff[2] >> 4);
1332
1333 aprint_normal_dev(sc->sc_dev,
1334 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n",
1335 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf,
1336 rp->ht40_max_pwr[2] & 0xf,
1337 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4,
1338 rp->ht40_max_pwr[2] >> 4);
1339
1340 aprint_normal_dev(sc->sc_dev,
1341 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n",
1342 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf,
1343 rp->ht20_max_pwr[2] & 0xf,
1344 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4,
1345 rp->ht20_max_pwr[2] >> 4);
1346
1347 aprint_normal_dev(sc->sc_dev,
1348 "xtal_calib %d, tssi %d %d, thermal %d\n",
1349 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter);
1350
1351 aprint_normal_dev(sc->sc_dev,
1352 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n",
1353 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4);
1354
1355 aprint_normal_dev(sc->sc_dev,
1356 "channnel_plan %d, version %d customer_id 0x%x\n",
1357 rp->channel_plan, rp->version, rp->curstomer_id);
1358}
1359#endif
1360
1361static void
1362urtwn_read_rom(struct urtwn_softc *sc)
1363{
1364 struct ieee80211com *ic = &sc->sc_ic;
1365 struct r92c_rom *rom = &sc->rom;
1366
1367 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1368
1369 mutex_enter(&sc->sc_write_mtx);
1370
1371 /* Read full ROM image. */
1372 urtwn_efuse_read(sc);
1373#ifdef URTWN_DEBUG
1374 if (urtwn_debug & DBG_REG)
1375 urtwn_dump_rom(sc, rom);
1376#endif
1377
1378 /* XXX Weird but this is what the vendor driver does. */
1379 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa);
1380 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE);
1381 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY);
1382
1383 DPRINTFN(DBG_INIT,
1384 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n",
1385 device_xname(sc->sc_dev), __func__, sc->pa_setting,
1386 sc->board_type, sc->regulatory));
1387
1388 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr);
1389
1390 sc->sc_rf_write = urtwn_r92c_rf_write;
1391 sc->sc_power_on = urtwn_r92c_power_on;
1392 sc->sc_dma_init = urtwn_r92c_dma_init;
1393
1394 mutex_exit(&sc->sc_write_mtx);
1395}
1396
1397static void
1398urtwn_r88e_read_rom(struct urtwn_softc *sc)
1399{
1400 struct ieee80211com *ic = &sc->sc_ic;
1401 uint8_t *rom = sc->r88e_rom;
1402 uint32_t reg;
1403 uint16_t addr = 0;
1404 uint8_t off, msk, tmp;
1405 int i;
1406
1407 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1408
1409 mutex_enter(&sc->sc_write_mtx);
1410
1411 off = 0;
1412 urtwn_efuse_switch_power(sc);
1413
1414 /* Read full ROM image. */
1415 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom));
1416 while (addr < 4096) {
1417 reg = urtwn_efuse_read_1(sc, addr);
1418 if (reg == 0xff)
1419 break;
1420 addr++;
1421 if ((reg & 0x1f) == 0x0f) {
1422 tmp = (reg & 0xe0) >> 5;
1423 reg = urtwn_efuse_read_1(sc, addr);
1424 if ((reg & 0x0f) != 0x0f)
1425 off = ((reg & 0xf0) >> 1) | tmp;
1426 addr++;
1427 } else
1428 off = reg >> 4;
1429 msk = reg & 0xf;
1430 for (i = 0; i < 4; i++) {
1431 if (msk & (1 << i))
1432 continue;
1433 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr);
1434 addr++;
1435 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr);
1436 addr++;
1437 }
1438 }
1439#ifdef URTWN_DEBUG
1440 if (urtwn_debug & DBG_REG) {
1441 }
1442#endif
1443
1444 addr = 0x10;
1445 for (i = 0; i < 6; i++)
1446 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++];
1447 for (i = 0; i < 5; i++)
1448 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++];
1449 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4;
1450 if (sc->bw20_tx_pwr_diff & 0x08)
1451 sc->bw20_tx_pwr_diff |= 0xf0;
1452 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf);
1453 if (sc->ofdm_tx_pwr_diff & 0x08)
1454 sc->ofdm_tx_pwr_diff |= 0xf0;
1455 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY);
1456
1457 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]);
1458
1459 if (ISSET(sc->chip, URTWN_CHIP_92EU)) {
1460 sc->sc_power_on = urtwn_r92e_power_on;
1461 sc->sc_rf_write = urtwn_r92e_rf_write;
1462 } else {
1463 sc->sc_power_on = urtwn_r88e_power_on;
1464 sc->sc_rf_write = urtwn_r88e_rf_write;
1465 }
1466 sc->sc_dma_init = urtwn_r88e_dma_init;
1467
1468 mutex_exit(&sc->sc_write_mtx);
1469}
1470
1471static int
1472urtwn_media_change(struct ifnet *ifp)
1473{
1474#ifdef URTWN_DEBUG
1475 struct urtwn_softc *sc = ifp->if_softc;
1476#endif
1477 int error;
1478
1479 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1480
1481 if ((error = ieee80211_media_change(ifp)) != ENETRESET)
1482 return error;
1483
1484 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1485 (IFF_UP | IFF_RUNNING)) {
1486 urtwn_init(ifp);
1487 }
1488 return 0;
1489}
1490
1491/*
1492 * Initialize rate adaptation in firmware.
1493 */
1494static int
1495urtwn_ra_init(struct urtwn_softc *sc)
1496{
1497 static const uint8_t map[] = {
1498 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108
1499 };
1500 struct ieee80211com *ic = &sc->sc_ic;
1501 struct ieee80211_node *ni = ic->ic_bss;
1502 struct ieee80211_rateset *rs = &ni->ni_rates;
1503 struct r92c_fw_cmd_macid_cfg cmd;
1504 uint32_t rates, basicrates;
1505 uint32_t mask, rrsr_mask, rrsr_rate;
1506 uint8_t mode;
1507 size_t maxrate, maxbasicrate, i, j;
1508 int error;
1509
1510 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1511
1512 KASSERT(mutex_owned(&sc->sc_write_mtx));
1513
1514 /* Get normal and basic rates mask. */
1515 rates = basicrates = 1;
1516 maxrate = maxbasicrate = 0;
1517 for (i = 0; i < rs->rs_nrates; i++) {
1518 /* Convert 802.11 rate to HW rate index. */
1519 for (j = 0; j < __arraycount(map); j++) {
1520 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) {
1521 break;
1522 }
1523 }
1524 if (j == __arraycount(map)) {
1525 /* Unknown rate, skip. */
1526 continue;
1527 }
1528
1529 rates |= 1U << j;
1530 if (j > maxrate) {
1531 maxrate = j;
1532 }
1533
1534 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) {
1535 basicrates |= 1U << j;
1536 if (j > maxbasicrate) {
1537 maxbasicrate = j;
1538 }
1539 }
1540 }
1541 if (ic->ic_curmode == IEEE80211_MODE_11B) {
1542 mode = R92C_RAID_11B;
1543 } else {
1544 mode = R92C_RAID_11BG;
1545 }
1546 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, "
1547 "maxrate=%zx, maxbasicrate=%zx\n",
1548 device_xname(sc->sc_dev), __func__, mode, rates, basicrates,
1549 maxrate, maxbasicrate));
1550
1551 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) {
1552 maxbasicrate |= R92C_RATE_SHORTGI;
1553 maxrate |= R92C_RATE_SHORTGI;
1554 }
1555
1556 /* Set rates mask for group addressed frames. */
1557 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID;
1558 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)
1559 cmd.macid |= URTWN_MACID_SHORTGI;
1560
1561 mask = (mode << 28) | basicrates;
1562 cmd.mask[0] = (uint8_t)mask;
1563 cmd.mask[1] = (uint8_t)(mask >> 8);
1564 cmd.mask[2] = (uint8_t)(mask >> 16);
1565 cmd.mask[3] = (uint8_t)(mask >> 24);
1566 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1567 if (error != 0) {
1568 aprint_error_dev(sc->sc_dev,
1569 "could not add broadcast station\n");
1570 return error;
1571 }
1572 /* Set initial MRR rate. */
1573 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n",
1574 device_xname(sc->sc_dev), __func__, maxbasicrate));
1575 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate);
1576
1577 /* Set rates mask for unicast frames. */
1578 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID;
1579 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)
1580 cmd.macid |= URTWN_MACID_SHORTGI;
1581
1582 mask = (mode << 28) | rates;
1583 cmd.mask[0] = (uint8_t)mask;
1584 cmd.mask[1] = (uint8_t)(mask >> 8);
1585 cmd.mask[2] = (uint8_t)(mask >> 16);
1586 cmd.mask[3] = (uint8_t)(mask >> 24);
1587 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1588 if (error != 0) {
1589 aprint_error_dev(sc->sc_dev, "could not add BSS station\n");
1590 return error;
1591 }
1592 /* Set initial MRR rate. */
1593 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev),
1594 __func__, maxrate));
1595 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate);
1596
1597 rrsr_rate = ic->ic_fixed_rate;
1598 if (rrsr_rate == -1)
1599 rrsr_rate = 11;
1600
1601 rrsr_mask = 0xffff >> (15 - rrsr_rate);
1602 urtwn_write_2(sc, R92C_RRSR, rrsr_mask);
1603
1604 /* Indicate highest supported rate. */
1605 ni->ni_txrate = rs->rs_nrates - 1;
1606
1607 return 0;
1608}
1609
1610static int
1611urtwn_get_nettype(struct urtwn_softc *sc)
1612{
1613 struct ieee80211com *ic = &sc->sc_ic;
1614 int type;
1615
1616 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1617
1618 switch (ic->ic_opmode) {
1619 case IEEE80211_M_STA:
1620 type = R92C_CR_NETTYPE_INFRA;
1621 break;
1622
1623 case IEEE80211_M_IBSS:
1624 type = R92C_CR_NETTYPE_ADHOC;
1625 break;
1626
1627 default:
1628 type = R92C_CR_NETTYPE_NOLINK;
1629 break;
1630 }
1631
1632 return type;
1633}
1634
1635static void
1636urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type)
1637{
1638 uint8_t reg;
1639
1640 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev),
1641 __func__, type));
1642
1643 KASSERT(mutex_owned(&sc->sc_write_mtx));
1644
1645 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c;
1646 urtwn_write_1(sc, R92C_CR + 2, reg | type);
1647}
1648
1649static void
1650urtwn_tsf_sync_enable(struct urtwn_softc *sc)
1651{
1652 struct ieee80211_node *ni = sc->sc_ic.ic_bss;
1653 uint64_t tsf;
1654
1655 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1656
1657 KASSERT(mutex_owned(&sc->sc_write_mtx));
1658
1659 /* Enable TSF synchronization. */
1660 urtwn_write_1(sc, R92C_BCN_CTRL,
1661 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0);
1662
1663 /* Correct TSF */
1664 urtwn_write_1(sc, R92C_BCN_CTRL,
1665 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN);
1666
1667 /* Set initial TSF. */
1668 tsf = ni->ni_tstamp.tsf;
1669 tsf = le64toh(tsf);
1670 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU));
1671 tsf -= IEEE80211_DUR_TU;
1672 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf);
1673 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32));
1674
1675 urtwn_write_1(sc, R92C_BCN_CTRL,
1676 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN);
1677}
1678
1679static void
1680urtwn_set_led(struct urtwn_softc *sc, int led, int on)
1681{
1682 uint8_t reg;
1683
1684 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev),
1685 __func__, led, on));
1686
1687 KASSERT(mutex_owned(&sc->sc_write_mtx));
1688
1689 if (led == URTWN_LED_LINK) {
1690 if (ISSET(sc->chip, URTWN_CHIP_92EU)) {
1691 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe);
1692 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON;
1693 urtwn_write_1(sc, R92C_LEDCFG1, reg |
1694 (R92C_LEDCFG0_DIS << 1));
1695 if (on) {
1696 reg = urtwn_read_1(sc, R92C_LEDCFG1) &
1697 R92E_LEDSON;
1698 urtwn_write_1(sc, R92C_LEDCFG1, reg);
1699 }
1700 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) {
1701 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;
1702 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60);
1703 if (!on) {
1704 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90;
1705 urtwn_write_1(sc, R92C_LEDCFG2,
1706 reg | R92C_LEDCFG0_DIS);
1707 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG);
1708 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG,
1709 reg & 0xfe);
1710 }
1711 } else {
1712 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70;
1713 if (!on) {
1714 reg |= R92C_LEDCFG0_DIS;
1715 }
1716 urtwn_write_1(sc, R92C_LEDCFG0, reg);
1717 }
1718 sc->ledlink = on; /* Save LED state. */
1719 }
1720}
1721
1722static void
1723urtwn_calib_to(void *arg)
1724{
1725 struct urtwn_softc *sc = arg;
1726
1727 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1728
1729 if (sc->sc_dying)
1730 return;
1731
1732 /* Do it in a process context. */
1733 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0);
1734}
1735
1736/* ARGSUSED */
1737static void
1738urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg)
1739{
1740 struct r92c_fw_cmd_rssi cmd;
1741 struct r92e_fw_cmd_rssi cmde;
1742
1743 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1744
1745 if (sc->sc_ic.ic_state != IEEE80211_S_RUN)
1746 goto restart_timer;
1747
1748 mutex_enter(&sc->sc_write_mtx);
1749 if (sc->avg_pwdb != -1) {
1750 /* Indicate Rx signal strength to FW for rate adaptation. */
1751 memset(&cmd, 0, sizeof(cmd));
1752 memset(&cmde, 0, sizeof(cmde));
1753 cmd.macid = 0; /* BSS. */
1754 cmde.macid = 0; /* BSS. */
1755 cmd.pwdb = sc->avg_pwdb;
1756 cmde.pwdb = sc->avg_pwdb;
1757 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n",
1758 device_xname(sc->sc_dev), __func__, sc->avg_pwdb));
1759 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) {
1760 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd,
1761 sizeof(cmd));
1762 } else {
1763 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde,
1764 sizeof(cmde));
1765 }
1766 }
1767
1768 /* Do temperature compensation. */
1769 urtwn_temp_calib(sc);
1770 mutex_exit(&sc->sc_write_mtx);
1771
1772 restart_timer:
1773 if (!sc->sc_dying) {
1774 /* Restart calibration timer. */
1775 callout_schedule(&sc->sc_calib_to, hz);
1776 }
1777}
1778
1779static void
1780urtwn_next_scan(void *arg)
1781{
1782 struct urtwn_softc *sc = arg;
1783 int s;
1784
1785 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1786
1787 if (sc->sc_dying)
1788 return;
1789
1790 s = splnet();
1791 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN)
1792 ieee80211_next_scan(&sc->sc_ic);
1793 splx(s);
1794}
1795
1796static void
1797urtwn_newassoc(struct ieee80211_node *ni, int isnew)
1798{
1799 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__,
1800 ether_sprintf(ni->ni_macaddr)));
1801 /* start with lowest Tx rate */
1802 ni->ni_txrate = 0;
1803}
1804
1805static int
1806urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1807{
1808 struct urtwn_softc *sc = ic->ic_ifp->if_softc;
1809 struct urtwn_cmd_newstate cmd;
1810
1811 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n",
1812 device_xname(sc->sc_dev), __func__,
1813 ieee80211_state_name[nstate], nstate, arg));
1814
1815 callout_stop(&sc->sc_scan_to);
1816 callout_stop(&sc->sc_calib_to);
1817
1818 /* Do it in a process context. */
1819 cmd.state = nstate;
1820 cmd.arg = arg;
1821 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd));
1822 return 0;
1823}
1824
1825static void
1826urtwn_newstate_cb(struct urtwn_softc *sc, void *arg)
1827{
1828 struct urtwn_cmd_newstate *cmd = arg;
1829 struct ieee80211com *ic = &sc->sc_ic;
1830 struct ieee80211_node *ni;
1831 enum ieee80211_state ostate = ic->ic_state;
1832 enum ieee80211_state nstate = cmd->state;
1833 uint32_t reg;
1834 uint8_t sifs_time, msr;
1835 int s;
1836
1837 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n",
1838 device_xname(sc->sc_dev), __func__,
1839 ieee80211_state_name[ostate], ostate,
1840 ieee80211_state_name[nstate], nstate));
1841
1842 s = splnet();
1843 mutex_enter(&sc->sc_write_mtx);
1844
1845 callout_stop(&sc->sc_scan_to);
1846 callout_stop(&sc->sc_calib_to);
1847
1848 switch (ostate) {
1849 case IEEE80211_S_INIT:
1850 break;
1851
1852 case IEEE80211_S_SCAN:
1853 if (nstate != IEEE80211_S_SCAN) {
1854 /*
1855 * End of scanning
1856 */
1857 /* flush 4-AC Queue after site_survey */
1858 urtwn_write_1(sc, R92C_TXPAUSE, 0x0);
1859
1860 /* Allow Rx from our BSSID only. */
1861 urtwn_write_4(sc, R92C_RCR,
1862 urtwn_read_4(sc, R92C_RCR) |
1863 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN);
1864 }
1865 break;
1866
1867 case IEEE80211_S_AUTH:
1868 case IEEE80211_S_ASSOC:
1869 break;
1870
1871 case IEEE80211_S_RUN:
1872 /* Turn link LED off. */
1873 urtwn_set_led(sc, URTWN_LED_LINK, 0);
1874
1875 /* Set media status to 'No Link'. */
1876 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
1877
1878 /* Stop Rx of data frames. */
1879 urtwn_write_2(sc, R92C_RXFLTMAP2, 0);
1880
1881 /* Reset TSF. */
1882 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03);
1883
1884 /* Disable TSF synchronization. */
1885 urtwn_write_1(sc, R92C_BCN_CTRL,
1886 urtwn_read_1(sc, R92C_BCN_CTRL) |
1887 R92C_BCN_CTRL_DIS_TSF_UDT0);
1888
1889 /* Back to 20MHz mode */
1890 urtwn_set_chan(sc, ic->ic_curchan,
1891 IEEE80211_HTINFO_2NDCHAN_NONE);
1892
1893 if (ic->ic_opmode == IEEE80211_M_IBSS ||
1894 ic->ic_opmode == IEEE80211_M_HOSTAP) {
1895 /* Stop BCN */
1896 urtwn_write_1(sc, R92C_BCN_CTRL,
1897 urtwn_read_1(sc, R92C_BCN_CTRL) &
1898 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT));
1899 }
1900
1901 /* Reset EDCA parameters. */
1902 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
1903 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317);
1904 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320);
1905 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444);
1906
1907 /* flush all cam entries */
1908 urtwn_cam_init(sc);
1909 break;
1910 }
1911
1912 switch (nstate) {
1913 case IEEE80211_S_INIT:
1914 /* Turn link LED off. */
1915 urtwn_set_led(sc, URTWN_LED_LINK, 0);
1916 break;
1917
1918 case IEEE80211_S_SCAN:
1919 if (ostate != IEEE80211_S_SCAN) {
1920 /*
1921 * Begin of scanning
1922 */
1923
1924 /* Set gain for scanning. */
1925 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1926 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1927 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
1928
1929 if (!ISSET(sc->chip, URTWN_CHIP_88E)) {
1930 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1931 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1932 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
1933 }
1934
1935 /* Set media status to 'No Link'. */
1936 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
1937
1938 /* Allow Rx from any BSSID. */
1939 urtwn_write_4(sc, R92C_RCR,
1940 urtwn_read_4(sc, R92C_RCR) &
1941 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
1942
1943 /* Stop Rx of data frames. */
1944 urtwn_write_2(sc, R92C_RXFLTMAP2, 0);
1945
1946 /* Disable update TSF */
1947 urtwn_write_1(sc, R92C_BCN_CTRL,
1948 urtwn_read_1(sc, R92C_BCN_CTRL) |
1949 R92C_BCN_CTRL_DIS_TSF_UDT0);
1950 }
1951
1952 /* Make link LED blink during scan. */
1953 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink);
1954
1955 /* Pause AC Tx queues. */
1956 urtwn_write_1(sc, R92C_TXPAUSE,
1957 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f);
1958
1959 urtwn_set_chan(sc, ic->ic_curchan,
1960 IEEE80211_HTINFO_2NDCHAN_NONE);
1961
1962 /* Start periodic scan. */
1963 if (!sc->sc_dying)
1964 callout_schedule(&sc->sc_scan_to, hz / 5);
1965 break;
1966
1967 case IEEE80211_S_AUTH:
1968 /* Set initial gain under link. */
1969 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1970 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
1971 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
1972
1973 if (!ISSET(sc->chip, URTWN_CHIP_88E)) {
1974 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1975 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
1976 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
1977 }
1978
1979 /* Set media status to 'No Link'. */
1980 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
1981
1982 /* Allow Rx from any BSSID. */
1983 urtwn_write_4(sc, R92C_RCR,
1984 urtwn_read_4(sc, R92C_RCR) &
1985 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
1986
1987 urtwn_set_chan(sc, ic->ic_curchan,
1988 IEEE80211_HTINFO_2NDCHAN_NONE);
1989 break;
1990
1991 case IEEE80211_S_ASSOC:
1992 break;
1993
1994 case IEEE80211_S_RUN:
1995 ni = ic->ic_bss;
1996
1997 /* XXX: Set 20MHz mode */
1998 urtwn_set_chan(sc, ic->ic_curchan,
1999 IEEE80211_HTINFO_2NDCHAN_NONE);
2000
2001 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
2002 /* Back to 20MHz mode */
2003 urtwn_set_chan(sc, ic->ic_curchan,
2004 IEEE80211_HTINFO_2NDCHAN_NONE);
2005
2006 /* Set media status to 'No Link'. */
2007 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
2008
2009 /* Enable Rx of data frames. */
2010 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
2011
2012 /* Allow Rx from any BSSID. */
2013 urtwn_write_4(sc, R92C_RCR,
2014 urtwn_read_4(sc, R92C_RCR) &
2015 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
2016
2017 /* Accept Rx data/control/management frames */
2018 urtwn_write_4(sc, R92C_RCR,
2019 urtwn_read_4(sc, R92C_RCR) |
2020 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF);
2021
2022 /* Turn link LED on. */
2023 urtwn_set_led(sc, URTWN_LED_LINK, 1);
2024 break;
2025 }
2026
2027 /* Set media status to 'Associated'. */
2028 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc));
2029
2030 /* Set BSSID. */
2031 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0]));
2032 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4]));
2033
2034 if (ic->ic_curmode == IEEE80211_MODE_11B) {
2035 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0);
2036 } else {
2037 /* 802.11b/g */
2038 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3);
2039 }
2040
2041 /* Enable Rx of data frames. */
2042 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
2043
2044 /* Set beacon interval. */
2045 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval);
2046
2047 msr = urtwn_read_1(sc, R92C_MSR);
2048 msr &= R92C_MSR_MASK;
2049 switch (ic->ic_opmode) {
2050 case IEEE80211_M_STA:
2051 /* Allow Rx from our BSSID only. */
2052 urtwn_write_4(sc, R92C_RCR,
2053 urtwn_read_4(sc, R92C_RCR) |
2054 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN);
2055
2056 /* Enable TSF synchronization. */
2057 urtwn_tsf_sync_enable(sc);
2058
2059 msr |= R92C_MSR_INFRA;
2060 break;
2061 case IEEE80211_M_HOSTAP:
2062 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f);
2063
2064 /* Allow Rx from any BSSID. */
2065 urtwn_write_4(sc, R92C_RCR,
2066 urtwn_read_4(sc, R92C_RCR) &
2067 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
2068
2069 /* Reset TSF timer to zero. */
2070 reg = urtwn_read_4(sc, R92C_TCR);
2071 reg &= ~0x01;
2072 urtwn_write_4(sc, R92C_TCR, reg);
2073 reg |= 0x01;
2074 urtwn_write_4(sc, R92C_TCR, reg);
2075
2076 msr |= R92C_MSR_AP;
2077 break;
2078 default:
2079 msr |= R92C_MSR_ADHOC;
2080 break;
2081 }
2082 urtwn_write_1(sc, R92C_MSR, msr);
2083
2084 sifs_time = 10;
2085 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time);
2086 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time);
2087 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time);
2088 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time);
2089 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time);
2090 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time);
2091
2092 /* Intialize rate adaptation. */
2093 if (ISSET(sc->chip, URTWN_CHIP_88E) ||
2094 ISSET(sc->chip, URTWN_CHIP_92EU))
2095 ni->ni_txrate = ni->ni_rates.rs_nrates - 1;
2096 else
2097 urtwn_ra_init(sc);
2098
2099 /* Turn link LED on. */
2100 urtwn_set_led(sc, URTWN_LED_LINK, 1);
2101
2102 /* Reset average RSSI. */
2103 sc->avg_pwdb = -1;
2104
2105 /* Reset temperature calibration state machine. */
2106 sc->thcal_state = 0;
2107 sc->thcal_lctemp = 0;
2108
2109 /* Start periodic calibration. */
2110 if (!sc->sc_dying)
2111 callout_schedule(&sc->sc_calib_to, hz);
2112 break;
2113 }
2114
2115 (*sc->sc_newstate)(ic, nstate, cmd->arg);
2116
2117 mutex_exit(&sc->sc_write_mtx);
2118 splx(s);
2119}
2120
2121static int
2122urtwn_wme_update(struct ieee80211com *ic)
2123{
2124 struct urtwn_softc *sc = ic->ic_ifp->if_softc;
2125
2126 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2127
2128 /* don't override default WME values if WME is not actually enabled */
2129 if (!(ic->ic_flags & IEEE80211_F_WME))
2130 return 0;
2131
2132 /* Do it in a process context. */
2133 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0);
2134 return 0;
2135}
2136
2137static void
2138urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg)
2139{
2140 static const uint16_t ac2reg[WME_NUM_AC] = {
2141 R92C_EDCA_BE_PARAM,
2142 R92C_EDCA_BK_PARAM,
2143 R92C_EDCA_VI_PARAM,
2144 R92C_EDCA_VO_PARAM
2145 };
2146 struct ieee80211com *ic = &sc->sc_ic;
2147 const struct wmeParams *wmep;
2148 int ac, aifs, slottime;
2149 int s;
2150
2151 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev),
2152 __func__));
2153
2154 s = splnet();
2155 mutex_enter(&sc->sc_write_mtx);
2156 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
2157 for (ac = 0; ac < WME_NUM_AC; ac++) {
2158 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
2159 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */
2160 aifs = wmep->wmep_aifsn * slottime + 10;
2161 urtwn_write_4(sc, ac2reg[ac],
2162 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) |
2163 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) |
2164 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) |
2165 SM(R92C_EDCA_PARAM_AIFS, aifs));
2166 }
2167 mutex_exit(&sc->sc_write_mtx);
2168 splx(s);
2169}
2170
2171static void
2172urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi)
2173{
2174 int pwdb;
2175
2176 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n",
2177 device_xname(sc->sc_dev), __func__, rate, rssi));
2178
2179 /* Convert antenna signal to percentage. */
2180 if (rssi <= -100 || rssi >= 20)
2181 pwdb = 0;
2182 else if (rssi >= 0)
2183 pwdb = 100;
2184 else
2185 pwdb = 100 + rssi;
2186 if (!ISSET(sc->chip, URTWN_CHIP_88E)) {
2187 if (rate <= 3) {
2188 /* CCK gain is smaller than OFDM/MCS gain. */
2189 pwdb += 6;
2190 if (pwdb > 100)
2191 pwdb = 100;
2192 if (pwdb <= 14)
2193 pwdb -= 4;
2194 else if (pwdb <= 26)
2195 pwdb -= 8;
2196 else if (pwdb <= 34)
2197 pwdb -= 6;
2198 else if (pwdb <= 42)
2199 pwdb -= 2;
2200 }
2201 }
2202 if (sc->avg_pwdb == -1) /* Init. */
2203 sc->avg_pwdb = pwdb;
2204 else if (sc->avg_pwdb < pwdb)
2205 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1;
2206 else
2207 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20);
2208
2209 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n",
2210 device_xname(sc->sc_dev), __func__,
2211 rate, rssi, pwdb, sc->avg_pwdb));
2212}
2213
2214static int8_t
2215urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt)
2216{
2217 static const int8_t cckoff[] = { 16, -12, -26, -46 };
2218 struct r92c_rx_phystat *phy;
2219 struct r92c_rx_cck *cck;
2220 uint8_t rpt;
2221 int8_t rssi;
2222
2223 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev),
2224 __func__, rate));
2225
2226 if (rate <= 3) {
2227 cck = (struct r92c_rx_cck *)physt;
2228 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) {
2229 rpt = (cck->agc_rpt >> 5) & 0x3;
2230 rssi = (cck->agc_rpt & 0x1f) << 1;
2231 } else {
2232 rpt = (cck->agc_rpt >> 6) & 0x3;
2233 rssi = cck->agc_rpt & 0x3e;
2234 }
2235 rssi = cckoff[rpt] - rssi;
2236 } else { /* OFDM/HT. */
2237 phy = (struct r92c_rx_phystat *)physt;
2238 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
2239 }
2240 return rssi;
2241}
2242
2243static int8_t
2244urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt)
2245{
2246 struct r92c_rx_phystat *phy;
2247 struct r88e_rx_cck *cck;
2248 uint8_t cck_agc_rpt, lna_idx, vga_idx;
2249 int8_t rssi;
2250
2251 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev),
2252 __func__, rate));
2253
2254 rssi = 0;
2255 if (rate <= 3) {
2256 cck = (struct r88e_rx_cck *)physt;
2257 cck_agc_rpt = cck->agc_rpt;
2258 lna_idx = (cck_agc_rpt & 0xe0) >> 5;
2259 vga_idx = cck_agc_rpt & 0x1f;
2260 switch (lna_idx) {
2261 case 7:
2262 if (vga_idx <= 27)
2263 rssi = -100 + 2* (27 - vga_idx);
2264 else
2265 rssi = -100;
2266 break;
2267 case 6:
2268 rssi = -48 + 2 * (2 - vga_idx);
2269 break;
2270 case 5:
2271 rssi = -42 + 2 * (7 - vga_idx);
2272 break;
2273 case 4:
2274 rssi = -36 + 2 * (7 - vga_idx);
2275 break;
2276 case 3:
2277 rssi = -24 + 2 * (7 - vga_idx);
2278 break;
2279 case 2:
2280 rssi = -12 + 2 * (5 - vga_idx);
2281 break;
2282 case 1:
2283 rssi = 8 - (2 * vga_idx);
2284 break;
2285 case 0:
2286 rssi = 14 - (2 * vga_idx);
2287 break;
2288 }
2289 rssi += 6;
2290 } else { /* OFDM/HT. */
2291 phy = (struct r92c_rx_phystat *)physt;
2292 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
2293 }
2294 return rssi;
2295}
2296
2297static void
2298urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen)
2299{
2300 struct ieee80211com *ic = &sc->sc_ic;
2301 struct ifnet *ifp = ic->ic_ifp;
2302 struct ieee80211_frame *wh;
2303 struct ieee80211_node *ni;
2304 struct r92c_rx_stat *stat;
2305 uint32_t rxdw0, rxdw3;
2306 struct mbuf *m;
2307 uint8_t rate;
2308 int8_t rssi = 0;
2309 int s, infosz;
2310
2311 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n",
2312 device_xname(sc->sc_dev), __func__, buf, pktlen));
2313
2314 stat = (struct r92c_rx_stat *)buf;
2315 rxdw0 = le32toh(stat->rxdw0);
2316 rxdw3 = le32toh(stat->rxdw3);
2317
2318 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) {
2319 /*
2320 * This should not happen since we setup our Rx filter
2321 * to not receive these frames.
2322 */
2323 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n",
2324 device_xname(sc->sc_dev), __func__));
2325 ifp->if_ierrors++;
2326 return;
2327 }
2328 /*
2329 * XXX: This will drop most control packets. Do we really
2330 * want this in IEEE80211_M_MONITOR mode?
2331 */
2332// if (__predict_false(pktlen < (int)sizeof(*wh))) {
2333 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) {
2334 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n",
2335 device_xname(sc->sc_dev), __func__, pktlen));
2336 ic->ic_stats.is_rx_tooshort++;
2337 ifp->if_ierrors++;
2338 return;
2339 }
2340 if (__predict_false(pktlen > MCLBYTES)) {
2341 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n",
2342 device_xname(sc->sc_dev), __func__, pktlen));
2343 ifp->if_ierrors++;
2344 return;
2345 }
2346
2347 rate = MS(rxdw3, R92C_RXDW3_RATE);
2348 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
2349
2350 /* Get RSSI from PHY status descriptor if present. */
2351 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) {
2352 if (!ISSET(sc->chip, URTWN_CHIP_92C))
2353 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]);
2354 else
2355 rssi = urtwn_get_rssi(sc, rate, &stat[1]);
2356 /* Update our average RSSI. */
2357 urtwn_update_avgrssi(sc, rate, rssi);
2358 }
2359
2360 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n",
2361 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi));
2362
2363 MGETHDR(m, M_DONTWAIT, MT_DATA);
2364 if (__predict_false(m == NULL)) {
2365 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n");
2366 ic->ic_stats.is_rx_nobuf++;
2367 ifp->if_ierrors++;
2368 return;
2369 }
2370 if (pktlen > (int)MHLEN) {
2371 MCLGET(m, M_DONTWAIT);
2372 if (__predict_false(!(m->m_flags & M_EXT))) {
2373 aprint_error_dev(sc->sc_dev,
2374 "couldn't allocate rx mbuf cluster\n");
2375 m_freem(m);
2376 ic->ic_stats.is_rx_nobuf++;
2377 ifp->if_ierrors++;
2378 return;
2379 }
2380 }
2381
2382 /* Finalize mbuf. */
2383 m_set_rcvif(m, ifp);
2384 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz);
2385 memcpy(mtod(m, uint8_t *), wh, pktlen);
2386 m->m_pkthdr.len = m->m_len = pktlen;
2387
2388 s = splnet();
2389 if (__predict_false(sc->sc_drvbpf != NULL)) {
2390 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap;
2391
2392 tap->wr_flags = 0;
2393 if (!(rxdw3 & R92C_RXDW3_HT)) {
2394 switch (rate) {
2395 /* CCK. */
2396 case 0: tap->wr_rate = 2; break;
2397 case 1: tap->wr_rate = 4; break;
2398 case 2: tap->wr_rate = 11; break;
2399 case 3: tap->wr_rate = 22; break;
2400 /* OFDM. */
2401 case 4: tap->wr_rate = 12; break;
2402 case 5: tap->wr_rate = 18; break;
2403 case 6: tap->wr_rate = 24; break;
2404 case 7: tap->wr_rate = 36; break;
2405 case 8: tap->wr_rate = 48; break;
2406 case 9: tap->wr_rate = 72; break;
2407 case 10: tap->wr_rate = 96; break;
2408 case 11: tap->wr_rate = 108; break;
2409 }
2410 } else if (rate >= 12) { /* MCS0~15. */
2411 /* Bit 7 set means HT MCS instead of rate. */
2412 tap->wr_rate = 0x80 | (rate - 12);
2413 }
2414 tap->wr_dbm_antsignal = rssi;
2415 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
2416 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
2417
2418 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m);
2419 }
2420
2421 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
2422
2423 /* push the frame up to the 802.11 stack */
2424 ieee80211_input(ic, m, ni, rssi, 0);
2425
2426 /* Node is no longer needed. */
2427 ieee80211_free_node(ni);
2428
2429 splx(s);
2430}
2431
2432static void
2433urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
2434{
2435 struct urtwn_rx_data *data = priv;
2436 struct urtwn_softc *sc = data->sc;
2437 struct r92c_rx_stat *stat;
2438 size_t pidx = data->pidx;
2439 uint32_t rxdw0;
2440 uint8_t *buf;
2441 int len, totlen, pktlen, infosz, npkts;
2442
2443 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n",
2444 device_xname(sc->sc_dev), __func__, status));
2445
2446 mutex_enter(&sc->sc_rx_mtx);
2447 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next);
2448 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next);
2449 /* Put this Rx buffer back to our free list. */
2450 mutex_exit(&sc->sc_rx_mtx);
2451
2452 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
2453 if (status == USBD_STALLED)
2454 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]);
2455 else if (status != USBD_CANCELLED)
2456 goto resubmit;
2457 return;
2458 }
2459 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL);
2460
2461 if (__predict_false(len < (int)sizeof(*stat))) {
2462 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n",
2463 device_xname(sc->sc_dev), __func__, len));
2464 goto resubmit;
2465 }
2466 buf = data->buf;
2467
2468 /* Get the number of encapsulated frames. */
2469 stat = (struct r92c_rx_stat *)buf;
2470 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT);
2471 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n",
2472 device_xname(sc->sc_dev), __func__, npkts));
2473
2474 /* Process all of them. */
2475 while (npkts-- > 0) {
2476 if (__predict_false(len < (int)sizeof(*stat))) {
2477 DPRINTFN(DBG_RX,
2478 ("%s: %s: len(%d) is short than header\n",
2479 device_xname(sc->sc_dev), __func__, len));
2480 break;
2481 }
2482 stat = (struct r92c_rx_stat *)buf;
2483 rxdw0 = le32toh(stat->rxdw0);
2484
2485 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN);
2486 if (__predict_false(pktlen == 0)) {
2487 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n",
2488 device_xname(sc->sc_dev), __func__));
2489 break;
2490 }
2491
2492 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
2493
2494 /* Make sure everything fits in xfer. */
2495 totlen = sizeof(*stat) + infosz + pktlen;
2496 if (__predict_false(totlen > len)) {
2497 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n",
2498 device_xname(sc->sc_dev), __func__, totlen,
2499 (int)sizeof(*stat), infosz, pktlen, len));
2500 break;
2501 }
2502
2503 /* Process 802.11 frame. */
2504 urtwn_rx_frame(sc, buf, pktlen);
2505
2506 /* Next chunk is 128-byte aligned. */
2507 totlen = roundup2(totlen, 128);
2508 buf += totlen;
2509 len -= totlen;
2510 }
2511
2512 resubmit:
2513 /* Setup a new transfer. */
2514 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ,
2515 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof);
2516 (void)usbd_transfer(xfer);
2517}
2518
2519static void
2520urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
2521{
2522 struct urtwn_tx_data *data = priv;
2523 struct urtwn_softc *sc = data->sc;
2524 struct ifnet *ifp = &sc->sc_if;
2525 size_t pidx = data->pidx;
2526 int s;
2527
2528 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n",
2529 device_xname(sc->sc_dev), __func__, status));
2530
2531 mutex_enter(&sc->sc_tx_mtx);
2532 /* Put this Tx buffer back to our free list. */
2533 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next);
2534 mutex_exit(&sc->sc_tx_mtx);
2535
2536 s = splnet();
2537 sc->tx_timer = 0;
2538 ifp->if_flags &= ~IFF_OACTIVE;
2539
2540 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
2541 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) {
2542 if (status == USBD_STALLED) {
2543 struct usbd_pipe *pipe = sc->tx_pipe[pidx];
2544 usbd_clear_endpoint_stall_async(pipe);
2545 }
2546 printf("ERROR1\n");
2547 ifp->if_oerrors++;
2548 }
2549 splx(s);
2550 return;
2551 }
2552
2553 ifp->if_opackets++;
2554 urtwn_start(ifp);
2555 splx(s);
2556
2557}
2558
2559static int
2560urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
2561 struct urtwn_tx_data *data)
2562{
2563 struct ieee80211com *ic = &sc->sc_ic;
2564 struct ieee80211_frame *wh;
2565 struct ieee80211_key *k = NULL;
2566 struct r92c_tx_desc *txd;
2567 size_t i, padsize, xferlen, txd_len;
2568 uint16_t seq, sum;
2569 uint8_t raid, type, tid;
2570 int s, hasqos, error;
2571
2572 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2573
2574 wh = mtod(m, struct ieee80211_frame *);
2575 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2576 txd_len = sizeof(*txd);
2577
2578 if (!ISSET(sc->chip, URTWN_CHIP_92EU))
2579 txd_len = 32;
2580
2581 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
2582 k = ieee80211_crypto_encap(ic, ni, m);
2583 if (k == NULL)
2584 return ENOBUFS;
2585
2586 /* packet header may have moved, reset our local pointer */
2587 wh = mtod(m, struct ieee80211_frame *);
2588 }
2589
2590 if (__predict_false(sc->sc_drvbpf != NULL)) {
2591 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap;
2592
2593 tap->wt_flags = 0;
2594 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
2595 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
2596 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
2597 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
2598
2599 /* XXX: set tap->wt_rate? */
2600
2601 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m);
2602 }
2603
2604 /* non-qos data frames */
2605 tid = R92C_TXDW1_QSEL_BE;
2606 if ((hasqos = ieee80211_has_qos(wh))) {
2607 /* data frames in 11n mode */
2608 struct ieee80211_qosframe *qwh = (void *)wh;
2609 tid = qwh->i_qos[0] & IEEE80211_QOS_TID;
2610 } else if (type != IEEE80211_FC0_TYPE_DATA) {
2611 tid = R92C_TXDW1_QSEL_MGNT;
2612 }
2613
2614 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */
2615 padsize = 8;
2616 else
2617 padsize = 0;
2618
2619 if (ISSET(sc->chip, URTWN_CHIP_92EU))
2620 padsize = 0;
2621
2622 /* Fill Tx descriptor. */
2623 txd = (struct r92c_tx_desc *)data->buf;
2624 memset(txd, 0, txd_len + padsize);
2625
2626 txd->txdw0 |= htole32(
2627 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) |
2628 SM(R92C_TXDW0_OFFSET, txd_len));
2629 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) {
2630 txd->txdw0 |= htole32(
2631 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG);
2632 }
2633
2634 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
2635 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST);
2636
2637 /* fix pad field */
2638 if (padsize > 0) {
2639 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n",
2640 device_xname(sc->sc_dev), __func__, padsize));
2641 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8)));
2642 }
2643
2644 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
2645 type == IEEE80211_FC0_TYPE_DATA) {
2646 if (ic->ic_curmode == IEEE80211_MODE_11B)
2647 raid = R92C_RAID_11B;
2648 else
2649 raid = R92C_RAID_11BG;
2650 DPRINTFN(DBG_TX,
2651 ("%s: %s: data packet: tid=%d, raid=%d\n",
2652 device_xname(sc->sc_dev), __func__, tid, raid));
2653
2654 if (!ISSET(sc->chip, URTWN_CHIP_92C)) {
2655 txd->txdw1 |= htole32(
2656 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) |
2657 SM(R92C_TXDW1_QSEL, tid) |
2658 SM(R92C_TXDW1_RAID, raid) |
2659 R92C_TXDW1_AGGBK);
2660 } else
2661 txd->txdw1 |= htole32(
2662 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) |
2663 SM(R92C_TXDW1_QSEL, tid) |
2664 SM(R92C_TXDW1_RAID, raid) |
2665 R92C_TXDW1_AGGBK);
2666
2667 if (ISSET(sc->chip, URTWN_CHIP_88E))
2668 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK);
2669 if (ISSET(sc->chip, URTWN_CHIP_92EU))
2670 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK);
2671
2672 if (hasqos) {
2673 txd->txdw4 |= htole32(R92C_TXDW4_QOS);
2674 }
2675
2676 if (ic->ic_flags & IEEE80211_F_USEPROT) {
2677 /* for 11g */
2678 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
2679 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF |
2680 R92C_TXDW4_HWRTSEN);
2681 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
2682 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |
2683 R92C_TXDW4_HWRTSEN);
2684 }
2685 }
2686 /* Send RTS at OFDM24. */
2687 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8));
2688 txd->txdw5 |= htole32(0x0001ff00);
2689 /* Send data at OFDM54. */
2690 if (ISSET(sc->chip, URTWN_CHIP_88E))
2691 txd->txdw5 |= htole32(0x13 & 0x3f);
2692 else
2693 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11));
2694 } else if (type == IEEE80211_FC0_TYPE_MGT) {
2695 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n",
2696 device_xname(sc->sc_dev), __func__));
2697 txd->txdw1 |= htole32(
2698 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) |
2699 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) |
2700 SM(R92C_TXDW1_RAID, R92C_RAID_11B));
2701
2702 /* Force CCK1. */
2703 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
2704 /* Use 1Mbps */
2705 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0));
2706 } else {
2707 /* broadcast or multicast packets */
2708 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n",
2709 device_xname(sc->sc_dev), __func__));
2710 txd->txdw1 |= htole32(
2711 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) |
2712 SM(R92C_TXDW1_RAID, R92C_RAID_11B));
2713
2714 /* Force CCK1. */
2715 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
2716 /* Use 1Mbps */
2717 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0));
2718 }
2719 /* Set sequence number */
2720 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT;
2721 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) {
2722 txd->txdseq |= htole16(seq);
2723
2724 if (!hasqos) {
2725 /* Use HW sequence numbering for non-QoS frames. */
2726 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ);
2727 txd->txdseq |= htole16(R92C_HWSEQ_EN);
2728 }
2729 } else {
2730 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) <<
2731 R92E_HWSEQ_SHIFT);
2732 if (!hasqos) {
2733 /* Use HW sequence numbering for non-QoS frames. */
2734 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ);
2735 txd->txdw7 |= htole16(R92C_HWSEQ_EN);
2736 }
2737 }
2738
2739 /* Compute Tx descriptor checksum. */
2740 sum = 0;
2741 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++)
2742 sum ^= ((uint16_t *)txd)[i];
2743 txd->txdsum = sum; /* NB: already little endian. */
2744
2745 xferlen = txd_len + m->m_pkthdr.len + padsize;
2746 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize);
2747
2748 s = splnet();
2749 usbd_setup_xfer(data->xfer, data, data->buf, xferlen,
2750 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT,
2751 urtwn_txeof);
2752 error = usbd_transfer(data->xfer);
2753 if (__predict_false(error != USBD_NORMAL_COMPLETION &&
2754 error != USBD_IN_PROGRESS)) {
2755 splx(s);
2756 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n",
2757 device_xname(sc->sc_dev), __func__, error));
2758 return error;
2759 }
2760 splx(s);
2761 return 0;
2762}
2763
2764struct urtwn_tx_data *
2765urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx)
2766{
2767 struct urtwn_tx_data *data = NULL;
2768
2769 mutex_enter(&sc->sc_tx_mtx);
2770 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) {
2771 data = TAILQ_FIRST(&sc->tx_free_list[pidx]);
2772 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next);
2773 }
2774 mutex_exit(&sc->sc_tx_mtx);
2775
2776 return data;
2777}
2778
2779static void
2780urtwn_start(struct ifnet *ifp)
2781{
2782 struct urtwn_softc *sc = ifp->if_softc;
2783 struct ieee80211com *ic = &sc->sc_ic;
2784 struct urtwn_tx_data *data;
2785 struct ether_header *eh;
2786 struct ieee80211_node *ni;
2787 struct mbuf *m;
2788
2789 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2790
2791 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2792 return;
2793
2794 data = NULL;
2795 for (;;) {
2796 /* Send pending management frames first. */
2797 IF_POLL(&ic->ic_mgtq, m);
2798 if (m != NULL) {
2799 /* Use AC_VO for management frames. */
2800
2801 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]);
2802
2803 if (data == NULL) {
2804 ifp->if_flags |= IFF_OACTIVE;
2805 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n",
2806 device_xname(sc->sc_dev)));
2807 return;
2808 }
2809 IF_DEQUEUE(&ic->ic_mgtq, m);
2810 ni = M_GETCTX(m, struct ieee80211_node *);
2811 M_CLEARCTX(m);
2812 goto sendit;
2813 }
2814 if (ic->ic_state != IEEE80211_S_RUN)
2815 break;
2816
2817 /* Encapsulate and send data frames. */
2818 IFQ_POLL(&ifp->if_snd, m);
2819 if (m == NULL)
2820 break;
2821
2822 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *);
2823 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2824 uint8_t qid = WME_AC_BE;
2825 if (ieee80211_has_qos(wh)) {
2826 /* data frames in 11n mode */
2827 struct ieee80211_qosframe *qwh = (void *)wh;
2828 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID;
2829 qid = TID_TO_WME_AC(tid);
2830 } else if (type != IEEE80211_FC0_TYPE_DATA) {
2831 qid = WME_AC_VO;
2832 }
2833 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]);
2834
2835 if (data == NULL) {
2836 ifp->if_flags |= IFF_OACTIVE;
2837 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n",
2838 device_xname(sc->sc_dev)));
2839 return;
2840 }
2841 IFQ_DEQUEUE(&ifp->if_snd, m);
2842
2843 if (m->m_len < (int)sizeof(*eh) &&
2844 (m = m_pullup(m, sizeof(*eh))) == NULL) {
2845 printf("ERROR6\n");
2846 ifp->if_oerrors++;
2847 continue;
2848 }
2849 eh = mtod(m, struct ether_header *);
2850 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
2851 if (ni == NULL) {
2852 m_freem(m);
2853 printf("ERROR5\n");
2854 ifp->if_oerrors++;
2855 continue;
2856 }
2857
2858 bpf_mtap(ifp, m);
2859
2860 if ((m = ieee80211_encap(ic, m, ni)) == NULL) {
2861 ieee80211_free_node(ni);
2862 printf("ERROR4\n");
2863 ifp->if_oerrors++;
2864 continue;
2865 }
2866 sendit:
2867 bpf_mtap3(ic->ic_rawbpf, m);
2868
2869 if (urtwn_tx(sc, m, ni, data) != 0) {
2870 m_freem(m);
2871 ieee80211_free_node(ni);
2872 printf("ERROR3\n");
2873 ifp->if_oerrors++;
2874 continue;
2875 }
2876 m_freem(m);
2877 ieee80211_free_node(ni);
2878 sc->tx_timer = 5;
2879 ifp->if_timer = 1;
2880 }
2881}
2882
2883static void
2884urtwn_watchdog(struct ifnet *ifp)
2885{
2886 struct urtwn_softc *sc = ifp->if_softc;
2887
2888 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2889
2890 ifp->if_timer = 0;
2891
2892 if (sc->tx_timer > 0) {
2893 if (--sc->tx_timer == 0) {
2894 aprint_error_dev(sc->sc_dev, "device timeout\n");
2895 /* urtwn_init(ifp); XXX needs a process context! */
2896 printf("ERROR2\n");
2897 ifp->if_oerrors++;
2898 return;
2899 }
2900 ifp->if_timer = 1;
2901 }
2902 ieee80211_watchdog(&sc->sc_ic);
2903}
2904
2905static int
2906urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data)
2907{
2908 struct urtwn_softc *sc = ifp->if_softc;
2909 struct ieee80211com *ic = &sc->sc_ic;
2910 int s, error = 0;
2911
2912 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n",
2913 device_xname(sc->sc_dev), __func__, cmd, data));
2914
2915 s = splnet();
2916
2917 switch (cmd) {
2918 case SIOCSIFFLAGS:
2919 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
2920 break;
2921 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
2922 case IFF_UP | IFF_RUNNING:
2923 break;
2924 case IFF_UP:
2925 urtwn_init(ifp);
2926 break;
2927 case IFF_RUNNING:
2928 urtwn_stop(ifp, 1);
2929 break;
2930 case 0:
2931 break;
2932 }
2933 break;
2934
2935 case SIOCADDMULTI:
2936 case SIOCDELMULTI:
2937 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
2938 /* setup multicast filter, etc */
2939 error = 0;
2940 }
2941 break;
2942
2943 default:
2944 error = ieee80211_ioctl(ic, cmd, data);
2945 break;
2946 }
2947 if (error == ENETRESET) {
2948 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
2949 (IFF_UP | IFF_RUNNING) &&
2950 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) {
2951 urtwn_init(ifp);
2952 }
2953 error = 0;
2954 }
2955
2956 splx(s);
2957
2958 return error;
2959}
2960
2961static __inline int
2962urtwn_power_on(struct urtwn_softc *sc)
2963{
2964
2965 return sc->sc_power_on(sc);
2966}
2967
2968static int
2969urtwn_r92c_power_on(struct urtwn_softc *sc)
2970{
2971 uint32_t reg;
2972 int ntries;
2973
2974 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2975
2976 KASSERT(mutex_owned(&sc->sc_write_mtx));
2977
2978 /* Wait for autoload done bit. */
2979 for (ntries = 0; ntries < 1000; ntries++) {
2980 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
2981 break;
2982 DELAY(5);
2983 }
2984 if (ntries == 1000) {
2985 aprint_error_dev(sc->sc_dev,
2986 "timeout waiting for chip autoload\n");
2987 return ETIMEDOUT;
2988 }
2989
2990 /* Unlock ISO/CLK/Power control register. */
2991 urtwn_write_1(sc, R92C_RSV_CTRL, 0);
2992 /* Move SPS into PWM mode. */
2993 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
2994 DELAY(5);
2995
2996 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL);
2997 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {
2998 urtwn_write_1(sc, R92C_LDOV12D_CTRL,
2999 reg | R92C_LDOV12D_CTRL_LDV12_EN);
3000 DELAY(100);
3001 urtwn_write_1(sc, R92C_SYS_ISO_CTRL,
3002 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) &
3003 ~R92C_SYS_ISO_CTRL_MD2PP);
3004 }
3005
3006 /* Auto enable WLAN. */
3007 urtwn_write_2(sc, R92C_APS_FSMCO,
3008 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
3009 for (ntries = 0; ntries < 1000; ntries++) {
3010 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
3011 R92C_APS_FSMCO_APFM_ONMAC))
3012 break;
3013 DELAY(100);
3014 }
3015 if (ntries == 1000) {
3016 aprint_error_dev(sc->sc_dev,
3017 "timeout waiting for MAC auto ON\n");
3018 return ETIMEDOUT;
3019 }
3020
3021 /* Enable radio, GPIO and LED functions. */
3022 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN |
3023 R92C_APS_FSMCO_PFM_ALDN) == 0x0812);
3024 urtwn_write_2(sc, R92C_APS_FSMCO,
3025 R92C_APS_FSMCO_AFSM_HSUS |
3026 R92C_APS_FSMCO_PDN_EN |
3027 R92C_APS_FSMCO_PFM_ALDN);
3028
3029 /* Release RF digital isolation. */
3030 urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
3031 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR);
3032
3033 /* Initialize MAC. */
3034 urtwn_write_1(sc, R92C_APSD_CTRL,
3035 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF);
3036 for (ntries = 0; ntries < 200; ntries++) {
3037 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) &
3038 R92C_APSD_CTRL_OFF_STATUS))
3039 break;
3040 DELAY(5);
3041 }
3042 if (ntries == 200) {
3043 aprint_error_dev(sc->sc_dev,
3044 "timeout waiting for MAC initialization\n");
3045 return ETIMEDOUT;
3046 }
3047
3048 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
3049 reg = urtwn_read_2(sc, R92C_CR);
3050 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
3051 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
3052 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
3053 R92C_CR_ENSEC;
3054 urtwn_write_2(sc, R92C_CR, reg);
3055
3056 urtwn_write_1(sc, 0xfe10, 0x19);
3057 return 0;
3058}
3059
3060static int
3061urtwn_r92e_power_on(struct urtwn_softc *sc)
3062{
3063 uint32_t reg;
3064 uint32_t val;
3065 int ntries;
3066
3067 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3068
3069 KASSERT(mutex_owned(&sc->sc_write_mtx));
3070
3071 /* Enable radio, GPIO and LED functions. */
3072 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN |
3073 R92C_APS_FSMCO_PFM_ALDN) == 0x0812);
3074 urtwn_write_2(sc, R92C_APS_FSMCO,
3075 R92C_APS_FSMCO_AFSM_HSUS |
3076 R92C_APS_FSMCO_PDN_EN |
3077 R92C_APS_FSMCO_PFM_ALDN);
3078
3079 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){
3080 /* LDO. */
3081 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3);
3082 }
3083 else {
3084 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc,
3085 R92C_SYS_SWR_CTRL2) & 0xffff);
3086 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83);
3087 }
3088
3089 for (ntries = 0; ntries < 2; ntries++) {
3090 urtwn_write_1(sc, R92C_AFE_PLL_CTRL,
3091 urtwn_read_1(sc, R92C_AFE_PLL_CTRL));
3092 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc,
3093 R92C_AFE_CTRL4));
3094 }
3095
3096 /* Reset BB. */
3097 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
3098 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB |
3099 R92C_SYS_FUNC_EN_BB_GLB_RST));
3100
3101 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc,
3102 R92C_AFE_XTAL_CTRL + 2) | 0x80);
3103
3104 /* Disable HWPDN. */
3105 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc,
3106 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN);
3107
3108 /* Disable WL suspend. */
3109 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc,
3110 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE |
3111 R92C_APS_FSMCO_AFSM_HSUS));
3112
3113 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc,
3114 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON);
3115 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc,
3116 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
3117 for (ntries = 0; ntries < 10000; ntries++) {
3118 val = urtwn_read_2(sc, R92C_APS_FSMCO) &
3119 R92C_APS_FSMCO_APFM_ONMAC;
3120 if (val == 0x0)
3121 break;
3122 DELAY(10);
3123 }
3124 if (ntries == 10000) {
3125 aprint_error_dev(sc->sc_dev,
3126 "timeout waiting for chip power up\n");
3127 return ETIMEDOUT;
3128 }
3129
3130 urtwn_write_2(sc, R92C_CR, 0x00);
3131 reg = urtwn_read_2(sc, R92C_CR);
3132 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
3133 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
3134 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC;
3135 urtwn_write_2(sc, R92C_CR, reg);
3136
3137 return 0;
3138}
3139
3140static int
3141urtwn_r88e_power_on(struct urtwn_softc *sc)
3142{
3143 uint32_t reg;
3144 uint8_t val;
3145 int ntries;
3146
3147 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3148
3149 KASSERT(mutex_owned(&sc->sc_write_mtx));
3150
3151 /* Wait for power ready bit. */
3152 for (ntries = 0; ntries < 5000; ntries++) {
3153 val = urtwn_read_1(sc, 0x6) & 0x2;
3154 if (val == 0x2)
3155 break;
3156 DELAY(10);
3157 }
3158 if (ntries == 5000) {
3159 aprint_error_dev(sc->sc_dev,
3160 "timeout waiting for chip power up\n");
3161 return ETIMEDOUT;
3162 }
3163
3164 /* Reset BB. */
3165 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
3166 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB |
3167 R92C_SYS_FUNC_EN_BB_GLB_RST));
3168
3169 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80);
3170
3171 /* Disable HWPDN. */
3172 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80);
3173
3174 /* Disable WL suspend. */
3175 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18);
3176
3177 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1);
3178 for (ntries = 0; ntries < 5000; ntries++) {
3179 if (!(urtwn_read_1(sc, 0x5) & 0x1))
3180 break;
3181 DELAY(10);
3182 }
3183 if (ntries == 5000)
3184 return ETIMEDOUT;
3185
3186 /* Enable LDO normal mode. */
3187 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10);
3188
3189 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
3190 urtwn_write_2(sc, R92C_CR, 0);
3191 reg = urtwn_read_2(sc, R92C_CR);
3192 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
3193 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
3194 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN;
3195 urtwn_write_2(sc, R92C_CR, reg);
3196
3197 return 0;
3198}
3199
3200static int
3201urtwn_llt_init(struct urtwn_softc *sc)
3202{
3203 size_t i, page_count, pktbuf_count;
3204 uint32_t val;
3205 int error;
3206
3207 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3208
3209 KASSERT(mutex_owned(&sc->sc_write_mtx));
3210
3211 if (sc->chip & URTWN_CHIP_88E)
3212 page_count = R88E_TX_PAGE_COUNT;
3213 else if (sc->chip & URTWN_CHIP_92EU)
3214 page_count = R92E_TX_PAGE_COUNT;
3215 else
3216 page_count = R92C_TX_PAGE_COUNT;
3217 if (sc->chip & URTWN_CHIP_88E)
3218 pktbuf_count = R88E_TXPKTBUF_COUNT;
3219 else if (sc->chip & URTWN_CHIP_92EU)
3220 pktbuf_count = R88E_TXPKTBUF_COUNT;
3221 else
3222 pktbuf_count = R92C_TXPKTBUF_COUNT;
3223
3224 if (sc->chip & URTWN_CHIP_92EU) {
3225 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN;
3226 urtwn_write_4(sc, R92E_AUTO_LLT, val);
3227 DELAY(100);
3228 val = urtwn_read_4(sc, R92E_AUTO_LLT);
3229 if (val & R92E_AUTO_LLT_EN)
3230 return EIO;
3231 return 0;
3232 }
3233
3234 /* Reserve pages [0; page_count]. */
3235 for (i = 0; i < page_count; i++) {
3236 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
3237 return error;
3238 }
3239 /* NB: 0xff indicates end-of-list. */
3240 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0)
3241 return error;
3242 /*
3243 * Use pages [page_count + 1; pktbuf_count - 1]
3244 * as ring buffer.
3245 */
3246 for (++i; i < pktbuf_count - 1; i++) {
3247 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
3248 return error;
3249 }
3250 /* Make the last page point to the beginning of the ring buffer. */
3251 error = urtwn_llt_write(sc, i, pktbuf_count + 1);
3252 return error;
3253}
3254
3255static void
3256urtwn_fw_reset(struct urtwn_softc *sc)
3257{
3258 uint16_t reg;
3259 int ntries;
3260
3261 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3262
3263 KASSERT(mutex_owned(&sc->sc_write_mtx));
3264
3265 /* Tell 8051 to reset itself. */
3266 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20);
3267
3268 /* Wait until 8051 resets by itself. */
3269 for (ntries = 0; ntries < 100; ntries++) {
3270 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
3271 if (!(reg & R92C_SYS_FUNC_EN_CPUEN))
3272 return;
3273 DELAY(50);
3274 }
3275 /* Force 8051 reset. */
3276 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
3277 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN);
3278}
3279
3280static void
3281urtwn_r88e_fw_reset(struct urtwn_softc *sc)
3282{
3283 uint16_t reg;
3284
3285 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3286
3287 KASSERT(mutex_owned(&sc->sc_write_mtx));
3288
3289 if (ISSET(sc->chip, URTWN_CHIP_92EU)) {
3290 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN;
3291 urtwn_write_2(sc,R92C_RSV_CTRL, reg);
3292 }
3293 DELAY(50);
3294
3295 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
3296 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
3297 DELAY(50);
3298
3299 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN);
3300 DELAY(50);
3301
3302 if (ISSET(sc->chip, URTWN_CHIP_92EU)) {
3303 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN;
3304 urtwn_write_2(sc,R92C_RSV_CTRL, reg);
3305 }
3306 DELAY(50);
3307
3308}
3309
3310static int
3311urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len)
3312{
3313 uint32_t reg;
3314 int off, mlen, error = 0;
3315
3316 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n",
3317 device_xname(sc->sc_dev), __func__, page, buf, len));
3318
3319 reg = urtwn_read_4(sc, R92C_MCUFWDL);
3320 reg = RW(reg, R92C_MCUFWDL_PAGE, page);
3321 urtwn_write_4(sc, R92C_MCUFWDL, reg);
3322
3323 off = R92C_FW_START_ADDR;
3324 while (len > 0) {
3325 if (len > 196)
3326 mlen = 196;
3327 else if (len > 4)
3328 mlen = 4;
3329 else
3330 mlen = 1;
3331 error = urtwn_write_region(sc, off, buf, mlen);
3332 if (error != 0)
3333 break;
3334 off += mlen;
3335 buf += mlen;
3336 len -= mlen;
3337 }
3338 return error;
3339}
3340
3341static int
3342urtwn_load_firmware(struct urtwn_softc *sc)
3343{
3344 firmware_handle_t fwh;
3345 const struct r92c_fw_hdr *hdr;
3346 const char *name;
3347 u_char *fw, *ptr;
3348 size_t len;
3349 uint32_t reg;
3350 int mlen, ntries, page, error;
3351
3352 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3353
3354 KASSERT(mutex_owned(&sc->sc_write_mtx));
3355
3356 /* Read firmware image from the filesystem. */
3357 if (ISSET(sc->chip, URTWN_CHIP_88E))
3358 name = "rtl8188eufw.bin";
3359 else if (ISSET(sc->chip, URTWN_CHIP_92EU))
3360 name = "rtl8192eefw.bin";
3361 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
3362 URTWN_CHIP_UMC_A_CUT)
3363 name = "rtl8192cfwU.bin";
3364 else
3365 name = "rtl8192cfw.bin";
3366 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) {
3367 aprint_error_dev(sc->sc_dev,
3368 "failed load firmware of file %s (error %d)\n", name,
3369 error);
3370 return error;
3371 }
3372 const size_t fwlen = len = firmware_get_size(fwh);
3373 fw = firmware_malloc(len);
3374 if (fw == NULL) {
3375 aprint_error_dev(sc->sc_dev,
3376 "failed to allocate firmware memory\n");
3377 firmware_close(fwh);
3378 return ENOMEM;
3379 }
3380 error = firmware_read(fwh, 0, fw, len);
3381 firmware_close(fwh);
3382 if (error != 0) {
3383 aprint_error_dev(sc->sc_dev,
3384 "failed to read firmware (error %d)\n", error);
3385 firmware_free(fw, fwlen);
3386 return error;
3387 }
3388
3389 len = fwlen;
3390 ptr = fw;
3391 hdr = (const struct r92c_fw_hdr *)ptr;
3392 /* Check if there is a valid FW header and skip it. */
3393 if ((le16toh(hdr->signature) >> 4) == 0x88c ||
3394 (le16toh(hdr->signature) >> 4) == 0x88e ||
3395 (le16toh(hdr->signature) >> 4) == 0x92e ||
3396 (le16toh(hdr->signature) >> 4) == 0x92c) {
3397 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n",
3398 device_xname(sc->sc_dev), __func__,
3399 le16toh(hdr->version), le16toh(hdr->subversion),
3400 hdr->month, hdr->date, hdr->hour, hdr->minute));
3401 ptr += sizeof(*hdr);
3402 len -= sizeof(*hdr);
3403 }
3404
3405 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) {
3406 if (ISSET(sc->chip, URTWN_CHIP_88E) ||
3407 ISSET(sc->chip, URTWN_CHIP_92EU))
3408 urtwn_r88e_fw_reset(sc);
3409 else
3410 urtwn_fw_reset(sc);
3411 }
3412 if (!ISSET(sc->chip, URTWN_CHIP_88E) &&
3413 !ISSET(sc->chip, URTWN_CHIP_92EU)) {
3414 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
3415 urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
3416 R92C_SYS_FUNC_EN_CPUEN);
3417 }
3418
3419 /* download enabled */
3420 urtwn_write_1(sc, R92C_MCUFWDL,
3421 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN);
3422 urtwn_write_1(sc, R92C_MCUFWDL + 2,
3423 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08);
3424
3425 /* Reset the FWDL checksum. */
3426 urtwn_write_1(sc, R92C_MCUFWDL,
3427 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT);
3428
3429 DELAY(50);
3430 /* download firmware */
3431 for (page = 0; len > 0; page++) {
3432 mlen = MIN(len, R92C_FW_PAGE_SIZE);
3433 error = urtwn_fw_loadpage(sc, page, ptr, mlen);
3434 if (error != 0) {
3435 aprint_error_dev(sc->sc_dev,
3436 "could not load firmware page %d\n", page);
3437 goto fail;
3438 }
3439 ptr += mlen;
3440 len -= mlen;
3441 }
3442
3443 /* download disable */
3444 urtwn_write_1(sc, R92C_MCUFWDL,
3445 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN);
3446 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0);
3447
3448 /* Wait for checksum report. */
3449 for (ntries = 0; ntries < 1000; ntries++) {
3450 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
3451 break;
3452 DELAY(5);
3453 }
3454 if (ntries == 1000) {
3455 aprint_error_dev(sc->sc_dev,
3456 "timeout waiting for checksum report\n");
3457 error = ETIMEDOUT;
3458 goto fail;
3459 }
3460
3461 /* Wait for firmware readiness. */
3462 reg = urtwn_read_4(sc, R92C_MCUFWDL);
3463 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY;
3464 urtwn_write_4(sc, R92C_MCUFWDL, reg);
3465 if (ISSET(sc->chip, URTWN_CHIP_88E) ||
3466 ISSET(sc->chip, URTWN_CHIP_92EU))
3467 urtwn_r88e_fw_reset(sc);
3468 for (ntries = 0; ntries < 1000; ntries++) {
3469 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
3470 break;
3471 DELAY(5);
3472 }
3473 if (ntries == 1000) {
3474 aprint_error_dev(sc->sc_dev,
3475 "timeout waiting for firmware readiness\n");
3476 error = ETIMEDOUT;
3477 goto fail;
3478 }
3479 fail:
3480 firmware_free(fw, fwlen);
3481 return error;
3482}
3483
3484static __inline int
3485urtwn_dma_init(struct urtwn_softc *sc)
3486{
3487
3488 return sc->sc_dma_init(sc);
3489}
3490
3491static int
3492urtwn_r92c_dma_init(struct urtwn_softc *sc)
3493{
3494 int hashq, hasnq, haslq, nqueues, nqpages, nrempages;
3495 uint32_t reg;
3496 int error;
3497
3498 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3499
3500 KASSERT(mutex_owned(&sc->sc_write_mtx));
3501
3502 /* Initialize LLT table. */
3503 error = urtwn_llt_init(sc);
3504 if (error != 0)
3505 return error;
3506
3507 /* Get Tx queues to USB endpoints mapping. */
3508 hashq = hasnq = haslq = 0;
3509 reg = urtwn_read_2(sc, R92C_USB_EP + 1);
3510 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n",
3511 device_xname(sc->sc_dev), __func__, reg));
3512 if (MS(reg, R92C_USB_EP_HQ) != 0)
3513 hashq = 1;
3514 if (MS(reg, R92C_USB_EP_NQ) != 0)
3515 hasnq = 1;
3516 if (MS(reg, R92C_USB_EP_LQ) != 0)
3517 haslq = 1;
3518 nqueues = hashq + hasnq + haslq;
3519 if (nqueues == 0)
3520 return EIO;
3521 /* Get the number of pages for each queue. */
3522 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues;
3523 /* The remaining pages are assigned to the high priority queue. */
3524 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues;
3525
3526 /* Set number of pages for normal priority queue. */
3527 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0);
3528 urtwn_write_4(sc, R92C_RQPN,
3529 /* Set number of pages for public queue. */
3530 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) |
3531 /* Set number of pages for high priority queue. */
3532 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) |
3533 /* Set number of pages for low priority queue. */
3534 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) |
3535 /* Load values. */
3536 R92C_RQPN_LD);
3537
3538 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY);
3539 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY);
3540 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY);
3541 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY);
3542 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY);
3543
3544 /* Set queue to USB pipe mapping. */
3545 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
3546 reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
3547 if (nqueues == 1) {
3548 if (hashq) {
3549 reg |= R92C_TRXDMA_CTRL_QMAP_HQ;
3550 } else if (hasnq) {
3551 reg |= R92C_TRXDMA_CTRL_QMAP_NQ;
3552 } else {
3553 reg |= R92C_TRXDMA_CTRL_QMAP_LQ;
3554 }
3555 } else if (nqueues == 2) {
3556 /* All 2-endpoints configs have a high priority queue. */
3557 if (!hashq) {
3558 return EIO;
3559 }
3560 if (hasnq) {
3561 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;
3562 } else {
3563 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ;
3564 }
3565 } else {
3566 reg |= R92C_TRXDMA_CTRL_QMAP_3EP;
3567 }
3568 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
3569
3570 /* Set Tx/Rx transfer page boundary. */
3571 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff);
3572
3573 /* Set Tx/Rx transfer page size. */
3574 urtwn_write_1(sc, R92C_PBP,
3575 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128));
3576 return 0;
3577}
3578
3579static int
3580urtwn_r88e_dma_init(struct urtwn_softc *sc)
3581{
3582 usb_interface_descriptor_t *id;
3583 uint32_t reg;
3584 int nqueues;
3585 int error;
3586
3587 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3588
3589 KASSERT(mutex_owned(&sc->sc_write_mtx));
3590
3591 /* Initialize LLT table. */
3592 error = urtwn_llt_init(sc);
3593 if (error != 0)
3594 return error;
3595
3596 /* Get Tx queues to USB endpoints mapping. */
3597 id = usbd_get_interface_descriptor(sc->sc_iface);
3598 nqueues = id->bNumEndpoints - 1;
3599 if (nqueues == 0)
3600 return EIO;
3601
3602 /* Set number of pages for normal priority queue. */
3603 urtwn_write_2(sc, R92C_RQPN_NPQ, 0);
3604 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d);
3605 urtwn_write_4(sc, R92C_RQPN, 0x808e000d);
3606
3607 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY);
3608 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY);
3609 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY);
3610 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY);
3611 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY);
3612
3613 /* Set queue to USB pipe mapping. */
3614 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
3615 reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
3616 if (nqueues == 1)
3617 reg |= R92C_TRXDMA_CTRL_QMAP_LQ;
3618 else if (nqueues == 2)
3619 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;
3620 else
3621 reg |= R92C_TRXDMA_CTRL_QMAP_3EP;
3622 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
3623
3624 /* Set Tx/Rx transfer page boundary. */
3625 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff);
3626
3627 /* Set Tx/Rx transfer page size. */
3628 urtwn_write_1(sc, R92C_PBP,
3629 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128));
3630
3631 return 0;
3632}
3633
3634static void
3635urtwn_mac_init(struct urtwn_softc *sc)
3636{
3637 size_t i;
3638
3639 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3640
3641 KASSERT(mutex_owned(&sc->sc_write_mtx));
3642
3643 /* Write MAC initialization values. */
3644 if (ISSET(sc->chip, URTWN_CHIP_88E)) {
3645 for (i = 0; i < __arraycount(rtl8188eu_mac); i++)
3646 urtwn_write_1(sc, rtl8188eu_mac[i].reg,
3647 rtl8188eu_mac[i].val);
3648 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) {
3649 for (i = 0; i < __arraycount(rtl8192eu_mac); i++)
3650 urtwn_write_1(sc, rtl8192eu_mac[i].reg,
3651 rtl8192eu_mac[i].val);
3652 } else {
3653 for (i = 0; i < __arraycount(rtl8192cu_mac); i++)
3654 urtwn_write_1(sc, rtl8192cu_mac[i].reg,
3655 rtl8192cu_mac[i].val);
3656 }
3657}
3658
3659static void
3660urtwn_bb_init(struct urtwn_softc *sc)
3661{
3662 const struct urtwn_bb_prog *prog;
3663 uint32_t reg;
3664 uint8_t crystalcap;
3665 size_t i;
3666
3667 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3668
3669 KASSERT(mutex_owned(&sc->sc_write_mtx));
3670
3671 /* Enable BB and RF. */
3672 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
3673 urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
3674 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
3675 R92C_SYS_FUNC_EN_DIO_RF);
3676
3677 if (!ISSET(sc->chip, URTWN_CHIP_88E) &&
3678 !ISSET(sc->chip, URTWN_CHIP_92EU)) {
3679 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83);
3680 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb);
3681 }
3682
3683 urtwn_write_1(sc, R92C_RF_CTRL,
3684 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
3685 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
3686 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
3687 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
3688
3689 if (!ISSET(sc->chip, URTWN_CHIP_88E) &&
3690 !ISSET(sc->chip, URTWN_CHIP_92EU)) {
3691 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f);
3692 urtwn_write_1(sc, 0x15, 0xe9);
3693 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
3694 }
3695
3696 /* Select BB programming based on board type. */
3697 if (ISSET(sc->chip, URTWN_CHIP_88E))
3698 prog = &rtl8188eu_bb_prog;
3699 else if (ISSET(sc->chip, URTWN_CHIP_92EU))
3700 prog = &rtl8192eu_bb_prog;
3701 else if (!(sc->chip & URTWN_CHIP_92C)) {
3702 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) {
3703 prog = &rtl8188ce_bb_prog;
3704 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) {
3705 prog = &rtl8188ru_bb_prog;
3706 } else {
3707 prog = &rtl8188cu_bb_prog;
3708 }
3709 } else {
3710 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) {
3711 prog = &rtl8192ce_bb_prog;
3712 } else {
3713 prog = &rtl8192cu_bb_prog;
3714 }
3715 }
3716 /* Write BB initialization values. */
3717 for (i = 0; i < prog->count; i++) {
3718 /* additional delay depend on registers */
3719 switch (prog->regs[i]) {
3720 case 0xfe:
3721 urtwn_delay_ms(sc, 50);
3722 break;
3723 case 0xfd:
3724 urtwn_delay_ms(sc, 5);
3725 break;
3726 case 0xfc:
3727 urtwn_delay_ms(sc, 1);
3728 break;
3729 case 0xfb:
3730 DELAY(50);
3731 break;
3732 case 0xfa:
3733 DELAY(5);
3734 break;
3735 case 0xf9:
3736 DELAY(1);
3737 break;
3738 }
3739 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
3740 DELAY(1);
3741 }
3742
3743 if (sc->chip & URTWN_CHIP_92C_1T2R) {
3744 /* 8192C 1T only configuration. */
3745 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
3746 reg = (reg & ~0x00000003) | 0x2;
3747 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
3748
3749 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
3750 reg = (reg & ~0x00300033) | 0x00200022;
3751 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
3752
3753 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
3754 reg = (reg & ~0xff000000) | (0x45 << 24);
3755 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
3756
3757 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
3758 reg = (reg & ~0x000000ff) | 0x23;
3759 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
3760
3761 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
3762 reg = (reg & ~0x00000030) | (1 << 4);
3763 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
3764
3765 reg = urtwn_bb_read(sc, 0xe74);
3766 reg = (reg & ~0x0c000000) | (2 << 26);
3767 urtwn_bb_write(sc, 0xe74, reg);
3768 reg = urtwn_bb_read(sc, 0xe78);
3769 reg = (reg & ~0x0c000000) | (2 << 26);
3770 urtwn_bb_write(sc, 0xe78, reg);
3771 reg = urtwn_bb_read(sc, 0xe7c);
3772 reg = (reg & ~0x0c000000) | (2 << 26);
3773 urtwn_bb_write(sc, 0xe7c, reg);
3774 reg = urtwn_bb_read(sc, 0xe80);
3775 reg = (reg & ~0x0c000000) | (2 << 26);
3776 urtwn_bb_write(sc, 0xe80, reg);
3777 reg = urtwn_bb_read(sc, 0xe88);
3778 reg = (reg & ~0x0c000000) | (2 << 26);
3779 urtwn_bb_write(sc, 0xe88, reg);
3780 }
3781
3782 /* Write AGC values. */
3783 for (i = 0; i < prog->agccount; i++) {
3784 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]);
3785 DELAY(1);
3786 }
3787
3788 if (ISSET(sc->chip, URTWN_CHIP_88E) ||
3789 ISSET(sc->chip, URTWN_CHIP_92EU)) {
3790 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
3791 DELAY(1);
3792 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420);
3793 DELAY(1);
3794
3795 if (ISSET(sc->chip, URTWN_CHIP_92EU)) {
3796 urtwn_write_2(sc, R92C_AFE_CTRL3, urtwn_read_2(sc,
3797 R92C_AFE_CTRL3));
3798 }
3799
3800 crystalcap = sc->r88e_rom[0xb9];
3801 if (crystalcap == 0xff)
3802 crystalcap = 0x20;
3803 crystalcap &= 0x3f;
3804 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
3805 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
3806 RW(reg, R92C_AFE_XTAL_CTRL_ADDR,
3807 crystalcap | crystalcap << 6));
3808 } else {
3809 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
3810 R92C_HSSI_PARAM2_CCK_HIPWR) {
3811 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR);
3812 }
3813 }
3814}
3815
3816static void
3817urtwn_rf_init(struct urtwn_softc *sc)
3818{
3819 const struct urtwn_rf_prog *prog;
3820 uint32_t reg, mask, saved;
3821 size_t i, j, idx;
3822
3823 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3824
3825 /* Select RF programming based on board type. */
3826 if (ISSET(sc->chip, URTWN_CHIP_88E))
3827 prog = rtl8188eu_rf_prog;
3828 else if (ISSET(sc->chip, URTWN_CHIP_92EU))
3829 prog = rtl8192eu_rf_prog;
3830 else if (!(sc->chip & URTWN_CHIP_92C)) {
3831 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) {
3832 prog = rtl8188ce_rf_prog;
3833 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) {
3834 prog = rtl8188ru_rf_prog;
3835 } else {
3836 prog = rtl8188cu_rf_prog;
3837 }
3838 } else {
3839 prog = rtl8192ce_rf_prog;
3840 }
3841
3842 for (i = 0; i < sc->nrxchains; i++) {
3843 /* Save RF_ENV control type. */
3844 idx = i / 2;
3845 mask = 0xffffU << ((i % 2) * 16);
3846 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask;
3847
3848 /* Set RF_ENV enable. */
3849 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
3850 reg |= 0x100000;
3851 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
3852 DELAY(50);
3853
3854 /* Set RF_ENV output high. */
3855 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
3856 reg |= 0x10;
3857 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
3858 DELAY(50);
3859
3860 /* Set address and data lengths of RF registers. */
3861 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
3862 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH;
3863 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
3864 DELAY(50);
3865 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
3866 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH;
3867 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
3868 DELAY(50);
3869
3870 /* Write RF initialization values for this chain. */
3871 for (j = 0; j < prog[i].count; j++) {
3872 if (prog[i].regs[j] >= 0xf9 &&
3873 prog[i].regs[j] <= 0xfe) {
3874 /*
3875 * These are fake RF registers offsets that
3876 * indicate a delay is required.
3877 */
3878 urtwn_delay_ms(sc, 50);
3879 continue;
3880 }
3881 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]);
3882 DELAY(5);
3883 }
3884
3885 /* Restore RF_ENV control type. */
3886 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask;
3887 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved);
3888 }
3889
3890 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
3891 URTWN_CHIP_UMC_A_CUT) {
3892 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255);
3893 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00);
3894 }
3895
3896 /* Cache RF register CHNLBW. */
3897 for (i = 0; i < 2; i++) {
3898 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW);
3899 }
3900}
3901
3902static void
3903urtwn_cam_init(struct urtwn_softc *sc)
3904{
3905 uint32_t content, command;
3906 uint8_t idx;
3907 size_t i;
3908
3909 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3910
3911 KASSERT(mutex_owned(&sc->sc_write_mtx));
3912 if (ISSET(sc->chip, URTWN_CHIP_92EU))
3913 return;
3914
3915 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) {
3916 content = (idx & 3)
3917 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S)
3918 | R92C_CAM_VALID;
3919
3920 command = R92C_CAMCMD_POLLING
3921 | R92C_CAMCMD_WRITE
3922 | R92C_CAM_CTL0(idx);
3923
3924 urtwn_write_4(sc, R92C_CAMWRITE, content);
3925 urtwn_write_4(sc, R92C_CAMCMD, command);
3926 }
3927
3928 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) {
3929 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) {
3930 if (i == 0) {
3931 content = (idx & 3)
3932 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S)
3933 | R92C_CAM_VALID;
3934 } else {
3935 content = 0;
3936 }
3937
3938 command = R92C_CAMCMD_POLLING
3939 | R92C_CAMCMD_WRITE
3940 | R92C_CAM_CTL0(idx)
3941 | i;
3942
3943 urtwn_write_4(sc, R92C_CAMWRITE, content);
3944 urtwn_write_4(sc, R92C_CAMCMD, command);
3945 }
3946 }
3947
3948 /* Invalidate all CAM entries. */
3949 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR);
3950}
3951
3952static void
3953urtwn_pa_bias_init(struct urtwn_softc *sc)
3954{
3955 uint8_t reg;
3956 size_t i;
3957
3958 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3959
3960 KASSERT(mutex_owned(&sc->sc_write_mtx));
3961
3962 for (i = 0; i < sc->nrxchains; i++) {
3963 if (sc->pa_setting & (1U << i))
3964 continue;
3965
3966 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406);
3967 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406);
3968 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406);
3969 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406);
3970 }
3971 if (!(sc->pa_setting & 0x10)) {
3972 reg = urtwn_read_1(sc, 0x16);
3973 reg = (reg & ~0xf0) | 0x90;
3974 urtwn_write_1(sc, 0x16, reg);
3975 }
3976}
3977
3978static void
3979urtwn_rxfilter_init(struct urtwn_softc *sc)
3980{
3981
3982 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3983
3984 KASSERT(mutex_owned(&sc->sc_write_mtx));
3985
3986 /* Initialize Rx filter. */
3987 /* TODO: use better filter for monitor mode. */
3988 urtwn_write_4(sc, R92C_RCR,
3989 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB |
3990 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL |
3991 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS);
3992 /* Accept all multicast frames. */
3993 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff);
3994 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff);
3995 /* Accept all management frames. */
3996 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff);
3997 /* Reject all control frames. */
3998 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000);
3999 /* Accept all data frames. */
4000 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
4001}
4002
4003static void
4004urtwn_edca_init(struct urtwn_softc *sc)
4005{
4006
4007 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
4008
4009 KASSERT(mutex_owned(&sc->sc_write_mtx));
4010
4011 /* set spec SIFS (used in NAV) */
4012 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a);
4013 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a);
4014
4015 /* set SIFS CCK/OFDM */
4016 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a);
4017 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a);
4018
4019 /* TXOP */
4020 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
4021 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
4022 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324);
4023 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226);
4024}
4025
4026static void
4027urtwn_write_txpower(struct urtwn_softc *sc, int chain,
4028 uint16_t power[URTWN_RIDX_COUNT])
4029{
4030 uint32_t reg;
4031
4032 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev),
4033 __func__, chain));
4034
4035 /* Write per-CCK rate Tx power. */
4036 if (chain == 0) {
4037 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
4038 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);
4039 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
4040
4041 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
4042 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);
4043 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);
4044 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);
4045 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
4046 } else {
4047 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
4048 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);
4049 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);
4050 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);
4051 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
4052
4053 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
4054 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);
4055 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
4056 }
4057 /* Write per-OFDM rate Tx power. */
4058 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
4059 SM(R92C_TXAGC_RATE06, power[ 4]) |
4060 SM(R92C_TXAGC_RATE09, power[ 5]) |
4061 SM(R92C_TXAGC_RATE12, power[ 6]) |
4062 SM(R92C_TXAGC_RATE18, power[ 7]));
4063 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
4064 SM(R92C_TXAGC_RATE24, power[ 8]) |
4065 SM(R92C_TXAGC_RATE36, power[ 9]) |
4066 SM(R92C_TXAGC_RATE48, power[10]) |
4067 SM(R92C_TXAGC_RATE54, power[11]));
4068 /* Write per-MCS Tx power. */
4069 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
4070 SM(R92C_TXAGC_MCS00, power[12]) |
4071 SM(R92C_TXAGC_MCS01, power[13]) |
4072 SM(R92C_TXAGC_MCS02, power[14]) |
4073 SM(R92C_TXAGC_MCS03, power[15]));
4074 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
4075 SM(R92C_TXAGC_MCS04, power[16]) |
4076 SM(R92C_TXAGC_MCS05, power[17]) |
4077 SM(R92C_TXAGC_MCS06, power[18]) |
4078 SM(R92C_TXAGC_MCS07, power[19]));
4079 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
4080 SM(R92C_TXAGC_MCS08, power[20]) |
4081 SM(R92C_TXAGC_MCS09, power[21]) |
4082 SM(R92C_TXAGC_MCS10, power[22]) |
4083 SM(R92C_TXAGC_MCS11, power[23]));
4084 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
4085 SM(R92C_TXAGC_MCS12, power[24]) |
4086 SM(R92C_TXAGC_MCS13, power[25]) |
4087 SM(R92C_TXAGC_MCS14, power[26]) |
4088 SM(R92C_TXAGC_MCS15, power[27]));
4089}
4090
4091static void
4092urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m,
4093 uint16_t power[URTWN_RIDX_COUNT])
4094{
4095 struct r92c_rom *rom = &sc->rom;
4096 uint16_t cckpow, ofdmpow, htpow, diff, maxpow;
4097 const struct urtwn_txpwr *base;
4098 int ridx, group;
4099
4100 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n",
4101 device_xname(sc->sc_dev), __func__, chain, chan));
4102
4103 /* Determine channel group. */
4104 if (chan <= 3) {
4105 group = 0;
4106 } else if (chan <= 9) {
4107 group = 1;
4108 } else {
4109 group = 2;
4110 }
4111
4112 /* Get original Tx power based on board type and RF chain. */
4113 if (!(sc->chip & URTWN_CHIP_92C)) {
4114 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) {
4115 base = &rtl8188ru_txagc[chain];
4116 } else {
4117 base = &rtl8192cu_txagc[chain];
4118 }
4119 } else {
4120 base = &rtl8192cu_txagc[chain];
4121 }
4122
4123 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0]));
4124 if (sc->regulatory == 0) {
4125 for (ridx = 0; ridx <= 3; ridx++) {
4126 power[ridx] = base->pwr[0][ridx];
4127 }
4128 }
4129 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) {
4130 if (sc->regulatory == 3) {
4131 power[ridx] = base->pwr[0][ridx];
4132 /* Apply vendor limits. */
4133 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) {
4134 maxpow = rom->ht40_max_pwr[group];
4135 } else {
4136 maxpow = rom->ht20_max_pwr[group];
4137 }
4138 maxpow = (maxpow >> (chain * 4)) & 0xf;
4139 if (power[ridx] > maxpow) {
4140 power[ridx] = maxpow;
4141 }
4142 } else if (sc->regulatory == 1) {
4143 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) {
4144 power[ridx] = base->pwr[group][ridx];
4145 }
4146 } else if (sc->regulatory != 2) {
4147 power[ridx] = base->pwr[0][ridx];
4148 }
4149 }
4150
4151 /* Compute per-CCK rate Tx power. */
4152 cckpow = rom->cck_tx_pwr[chain][group];
4153 for (ridx = 0; ridx <= 3; ridx++) {
4154 power[ridx] += cckpow;
4155 if (power[ridx] > R92C_MAX_TX_PWR) {
4156 power[ridx] = R92C_MAX_TX_PWR;
4157 }
4158 }
4159
4160 htpow = rom->ht40_1s_tx_pwr[chain][group];
4161 if (sc->ntxchains > 1) {
4162 /* Apply reduction for 2 spatial streams. */
4163 diff = rom->ht40_2s_tx_pwr_diff[group];
4164 diff = (diff >> (chain * 4)) & 0xf;
4165 htpow = (htpow > diff) ? htpow - diff : 0;
4166 }
4167
4168 /* Compute per-OFDM rate Tx power. */
4169 diff = rom->ofdm_tx_pwr_diff[group];
4170 diff = (diff >> (chain * 4)) & 0xf;
4171 ofdmpow = htpow + diff; /* HT->OFDM correction. */
4172 for (ridx = 4; ridx <= 11; ridx++) {
4173 power[ridx] += ofdmpow;
4174 if (power[ridx] > R92C_MAX_TX_PWR) {
4175 power[ridx] = R92C_MAX_TX_PWR;
4176 }
4177 }
4178
4179 /* Compute per-MCS Tx power. */
4180 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) {
4181 diff = rom->ht20_tx_pwr_diff[group];
4182 diff = (diff >> (chain * 4)) & 0xf;
4183 htpow += diff; /* HT40->HT20 correction. */
4184 }
4185 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) {
4186 power[ridx] += htpow;
4187 if (power[ridx] > R92C_MAX_TX_PWR) {
4188 power[ridx] = R92C_MAX_TX_PWR;
4189 }
4190 }
4191#ifdef URTWN_DEBUG
4192 if (urtwn_debug & DBG_RF) {
4193 /* Dump per-rate Tx power values. */
4194 printf("%s: %s: Tx power for chain %zd:\n",
4195 device_xname(sc->sc_dev), __func__, chain);
4196 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) {
4197 printf("%s: %s: Rate %d = %u\n",
4198 device_xname(sc->sc_dev), __func__, ridx,
4199 power[ridx]);
4200 }
4201 }
4202#endif
4203}
4204
4205void
4206urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan,
4207 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT])
4208{
4209 uint16_t cckpow, ofdmpow, bw20pow, htpow;
4210 const struct urtwn_r88e_txpwr *base;
4211 int ridx, group;
4212
4213 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n",
4214 device_xname(sc->sc_dev), __func__, chain, chan));
4215
4216 /* Determine channel group. */
4217 if (chan <= 2)
4218 group = 0;
4219 else if (chan <= 5)
4220 group = 1;
4221 else if (chan <= 8)
4222 group = 2;
4223 else if (chan <= 11)
4224 group = 3;
4225 else if (chan <= 13)
4226 group = 4;
4227 else
4228 group = 5;
4229
4230 /* Get original Tx power based on board type and RF chain. */
4231 base = &rtl8188eu_txagc[chain];
4232
4233 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0]));
4234 if (sc->regulatory == 0) {
4235 for (ridx = 0; ridx <= 3; ridx++)
4236 power[ridx] = base->pwr[0][ridx];
4237 }
4238 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) {
4239 if (sc->regulatory == 3)
4240 power[ridx] = base->pwr[0][ridx];
4241 else if (sc->regulatory == 1) {
4242 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE)
4243 power[ridx] = base->pwr[group][ridx];
4244 } else if (sc->regulatory != 2)
4245 power[ridx] = base->pwr[0][ridx];
4246 }
4247
4248 /* Compute per-CCK rate Tx power. */
4249 cckpow = sc->cck_tx_pwr[group];
4250 for (ridx = 0; ridx <= 3; ridx++) {
4251 power[ridx] += cckpow;
4252 if (power[ridx] > R92C_MAX_TX_PWR)
4253 power[ridx] = R92C_MAX_TX_PWR;
4254 }
4255
4256 htpow = sc->ht40_tx_pwr[group];
4257
4258 /* Compute per-OFDM rate Tx power. */
4259 ofdmpow = htpow + sc->ofdm_tx_pwr_diff;
4260 for (ridx = 4; ridx <= 11; ridx++) {
4261 power[ridx] += ofdmpow;
4262 if (power[ridx] > R92C_MAX_TX_PWR)
4263 power[ridx] = R92C_MAX_TX_PWR;
4264 }
4265
4266 bw20pow = htpow + sc->bw20_tx_pwr_diff;
4267 for (ridx = 12; ridx <= 27; ridx++) {
4268 power[ridx] += bw20pow;
4269 if (power[ridx] > R92C_MAX_TX_PWR)
4270 power[ridx] = R92C_MAX_TX_PWR;
4271 }
4272}
4273
4274static void
4275urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m)
4276{
4277 uint16_t power[URTWN_RIDX_COUNT];
4278 size_t i;
4279
4280 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
4281
4282 for (i = 0; i < sc->ntxchains; i++) {
4283 /* Compute per-rate Tx power values. */
4284 if (ISSET(sc->chip, URTWN_CHIP_88E) ||
4285 ISSET(sc->chip, URTWN_CHIP_92EU))
4286 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power);
4287 else
4288 urtwn_get_txpower(sc, i, chan, ht40m, power);
4289 /* Write per-rate Tx power values to hardware. */
4290 urtwn_write_txpower(sc, i, power);
4291 }
4292}
4293
4294static void
4295urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m)
4296{
4297 struct ieee80211com *ic = &sc->sc_ic;
4298 u_int chan;
4299 size_t i;
4300
4301 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
4302
4303 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev),
4304 __func__, chan));
4305
4306 KASSERT(mutex_owned(&sc->sc_write_mtx));
4307
4308 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) {
4309 chan += 2;
4310 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){
4311 chan -= 2;
4312 }
4313
4314 /* Set Tx power for this new channel. */
4315 urtwn_set_txpower(sc, chan, ht40m);
4316
4317 for (i = 0; i < sc->nrxchains; i++) {
4318 urtwn_rf_write(sc, i, R92C_RF_CHNLBW,
4319 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));
4320 }
4321
4322 if (ht40m) {
4323 /* Is secondary channel below or above primary? */
4324 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE);
4325 uint32_t reg;
4326
4327 urtwn_write_1(sc, R92C_BWOPMODE,
4328 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ);
4329
4330 reg = urtwn_read_1(sc, R92C_RRSR + 2);
4331 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5;
4332 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg);
4333
4334 urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
4335 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
4336 urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
4337 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
4338
4339 /* Set CCK side band. */
4340 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM);
4341 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;
4342 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
4343
4344 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF);
4345 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;
4346 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
4347
4348 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
4349 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
4350 ~R92C_FPGA0_ANAPARAM2_CBW20);
4351
4352 reg = urtwn_bb_read(sc, 0x818);
4353 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;
4354 urtwn_bb_write(sc, 0x818, reg);
4355
4356 /* Select 40MHz bandwidth. */
4357 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
4358 (sc->rf_chnlbw[0] & ~0xfff) | chan);
4359 } else {
4360 urtwn_write_1(sc, R92C_BWOPMODE,
4361 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ);
4362
4363 urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
4364 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
4365 urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
4366 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
4367
4368 if (!ISSET(sc->chip, URTWN_CHIP_88E) &&
4369 !ISSET(sc->chip, URTWN_CHIP_92EU)) {
4370 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
4371 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
4372 R92C_FPGA0_ANAPARAM2_CBW20);
4373 }
4374
4375 /* Select 20MHz bandwidth. */
4376 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
4377 (sc->rf_chnlbw[0] & ~0xfff) | chan |
4378 (ISSET(sc->chip, URTWN_CHIP_88E) ||
4379 ISSET(sc->chip, URTWN_CHIP_92EU) ?
4380 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20));
4381 }
4382}
4383
4384static void
4385urtwn_iq_calib(struct urtwn_softc *sc, bool inited)
4386{
4387
4388 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev),
4389 __func__, inited));
4390
4391 uint32_t addaBackup[16], iqkBackup[4], piMode;
4392
4393#ifdef notyet
4394 uint32_t odfm0_agccore_regs[3];
4395 uint32_t ant_regs[3];
4396 uint32_t rf_regs[8];
4397#endif
4398 uint32_t reg0, reg1, reg2;
4399 int i, attempt;
4400
4401#ifdef notyet
4402 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc,
4403 R92E_STBC_SETTING + 2));
4404 urtwn_write_1(sc, R92C_ACLK_MON, 0);
4405 /* Save AGCCORE regs. */
4406 for (i = 0; i < sc->nrxchains; i++) {
4407 odfm0_agccore_regs[i] = urtwn_read_4(sc,
4408 R92C_OFDM0_AGCCORE1(i));
4409 }
4410#endif
4411 /* Save BB regs. */
4412 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
4413 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
4414 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
4415
4416 /* Save adda regs to be restored when finished. */
4417 for (i = 0; i < __arraycount(addaReg); i++)
4418 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]);
4419 /* Save mac regs. */
4420 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE);
4421 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL);
4422 iqkBackup[2] = urtwn_read_1(sc, R92C_USTIME_TSF);
4423 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG);
4424
4425#ifdef notyet
4426 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A);
4427 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B);
4428
4429 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0));
4430 for (i = 0; i < sc->nrxchains; i++)
4431 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i));
4432 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING);
4433#endif
4434
4435 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) &
4436 R92C_HSSI_PARAM1_PI);
4437 if (piMode == 0) {
4438 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
4439 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))|
4440 R92C_HSSI_PARAM1_PI);
4441 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
4442 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))|
4443 R92C_HSSI_PARAM1_PI);
4444 }
4445
4446 attempt = 1;
4447
4448next_attempt:
4449
4450 /* Set mac regs for calibration. */
4451 for (i = 0; i < __arraycount(addaReg); i++) {
4452 urtwn_bb_write(sc, addaReg[i],
4453 addaReg[__arraycount(addaReg) - 1]);
4454 }
4455 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc,
4456 R92C_CCK0_AFESETTING));
4457 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA);
4458 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR);
4459 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1);
4460 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM);
4461
4462 if (sc->ntxchains > 1)
4463 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM);
4464
4465 urtwn_write_1(sc, R92C_TXPAUSE, (~TP_STOPBECON) & TP_STOPALL);
4466 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] &
4467 ~R92C_BCN_CTRL_EN_BCN));
4468 urtwn_write_1(sc, R92C_USTIME_TSF, (iqkBackup[2] & ~0x8));
4469
4470 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] &
4471 ~R92C_GPIO_MUXCFG_ENBT));
4472
4473 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT);
4474
4475 if (sc->ntxchains > 1)
4476 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT);
4477 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING);
4478 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING);
4479 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING);
4480
4481 /* Restore BB regs. */
4482 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0);
4483 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2);
4484 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1);
4485
4486 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0);
4487 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE);
4488 if (sc->nrxchains > 1)
4489 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE);
4490
4491 if (attempt-- > 0)
4492 goto next_attempt;
4493
4494 /* Restore mode. */
4495 if (piMode == 0) {
4496 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
4497 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) &
4498 ~R92C_HSSI_PARAM1_PI);
4499 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
4500 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) &
4501 ~R92C_HSSI_PARAM1_PI);
4502 }
4503
4504#ifdef notyet
4505 for (i = 0; i < sc->nrxchains; i++) {
4506 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i),
4507 odfm0_agccore_regs[i]);
4508 }
4509#endif
4510
4511 /* Restore adda regs. */
4512 for (i = 0; i < __arraycount(addaReg); i++)
4513 urtwn_bb_write(sc, addaReg[i], addaBackup[i]);
4514 /* Restore mac regs. */
4515 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]);
4516 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]);
4517 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]);
4518 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]);
4519
4520#ifdef notyet
4521 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]);
4522 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]);
4523
4524 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]);
4525 for (i = 0; i < sc->nrxchains; i++)
4526 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]);
4527 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4);
4528#endif
4529}
4530
4531static void
4532urtwn_lc_calib(struct urtwn_softc *sc)
4533{
4534 uint32_t rf_ac[2];
4535 uint8_t txmode;
4536 size_t i;
4537
4538 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
4539
4540 KASSERT(mutex_owned(&sc->sc_write_mtx));
4541
4542 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
4543 if ((txmode & 0x70) != 0) {
4544 /* Disable all continuous Tx. */
4545 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70);
4546
4547 /* Set RF mode to standby mode. */
4548 for (i = 0; i < sc->nrxchains; i++) {
4549 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC);
4550 urtwn_rf_write(sc, i, R92C_RF_AC,
4551 RW(rf_ac[i], R92C_RF_AC_MODE,
4552 R92C_RF_AC_MODE_STANDBY));
4553 }
4554 } else {
4555 /* Block all Tx queues. */
4556 urtwn_write_1(sc, R92C_TXPAUSE, 0xff);
4557 }
4558 /* Start calibration. */
4559 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
4560 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART);
4561
4562 /* Give calibration the time to complete. */
4563 urtwn_delay_ms(sc, 100);
4564
4565 /* Restore configuration. */
4566 if ((txmode & 0x70) != 0) {
4567 /* Restore Tx mode. */
4568 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode);
4569 /* Restore RF mode. */
4570 for (i = 0; i < sc->nrxchains; i++) {
4571 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]);
4572 }
4573 } else {
4574 /* Unblock all Tx queues. */
4575 urtwn_write_1(sc, R92C_TXPAUSE, 0x00);
4576 }
4577}
4578
4579static void
4580urtwn_temp_calib(struct urtwn_softc *sc)
4581{
4582 int temp, t_meter_reg;
4583
4584 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
4585
4586 KASSERT(mutex_owned(&sc->sc_write_mtx));
4587
4588 if (!ISSET(sc->chip, URTWN_CHIP_92EU))
4589 t_meter_reg = R92C_RF_T_METER;
4590 else
4591 t_meter_reg = R92E_RF_T_METER;
4592
4593 if (sc->thcal_state == 0) {
4594 /* Start measuring temperature. */
4595 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n",
4596 device_xname(sc->sc_dev), __func__));
4597 urtwn_rf_write(sc, 0, t_meter_reg, 0x60);
4598 sc->thcal_state = 1;
4599 return;
4600 }
4601 sc->thcal_state = 0;
4602
4603 /* Read measured temperature. */
4604 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f;
4605 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev),
4606 __func__, temp));
4607 if (temp == 0) /* Read failed, skip. */
4608 return;
4609
4610 /*
4611 * Redo LC calibration if temperature changed significantly since
4612 * last calibration.
4613 */
4614 if (sc->thcal_lctemp == 0) {
4615 /* First LC calibration is performed in urtwn_init(). */
4616 sc->thcal_lctemp = temp;
4617 } else if (abs(temp - sc->thcal_lctemp) > 1) {
4618 DPRINTFN(DBG_RF,
4619 ("%s: %s: LC calib triggered by temp: %d -> %d\n",
4620 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp,
4621 temp));
4622 urtwn_lc_calib(sc);
4623 /* Record temperature of last LC calibration. */
4624 sc->thcal_lctemp = temp;
4625 }
4626}
4627
4628static int
4629urtwn_init(struct ifnet *ifp)
4630{
4631 struct urtwn_softc *sc = ifp->if_softc;
4632 struct ieee80211com *ic = &sc->sc_ic;
4633 struct urtwn_rx_data *data;
4634 uint32_t reg;
4635 size_t i;
4636 int error;
4637
4638 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
4639
4640 urtwn_stop(ifp, 0);
4641
4642 mutex_enter(&sc->sc_write_mtx);
4643
4644 mutex_enter(&sc->sc_task_mtx);
4645 /* Init host async commands ring. */
4646 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0;
4647 mutex_exit(&sc->sc_task_mtx);
4648
4649 mutex_enter(&sc->sc_fwcmd_mtx);
4650 /* Init firmware commands ring. */
4651 sc->fwcur = 0;
4652 mutex_exit(&sc->sc_fwcmd_mtx);
4653
4654 /* Allocate Tx/Rx buffers. */
4655 error = urtwn_alloc_rx_list(sc);
4656 if (error != 0) {
4657 aprint_error_dev(sc->sc_dev,
4658 "could not allocate Rx buffers\n");
4659 goto fail;
4660 }
4661 error = urtwn_alloc_tx_list(sc);
4662 if (error != 0) {
4663 aprint_error_dev(sc->sc_dev,
4664 "could not allocate Tx buffers\n");
4665 goto fail;
4666 }
4667
4668 /* Power on adapter. */
4669 error = urtwn_power_on(sc);
4670 if (error != 0)
4671 goto fail;
4672
4673 /* Initialize DMA. */
4674 error = urtwn_dma_init(sc);
4675 if (error != 0)
4676 goto fail;
4677
4678 /* Set info size in Rx descriptors (in 64-bit words). */
4679 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4);
4680
4681 /* Init interrupts. */
4682 if (ISSET(sc->chip, URTWN_CHIP_88E) ||
4683 ISSET(sc->chip, URTWN_CHIP_92EU)) {
4684 urtwn_write_4(sc, R88E_HISR, 0xffffffff);
4685 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 |
4686 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT);
4687 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW |
4688 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR);
4689 if (ISSET(sc->chip, URTWN_CHIP_88E)) {
4690 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
4691 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
4692 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL);
4693 }
4694 if (ISSET(sc->chip, URTWN_CHIP_92EU))
4695 urtwn_write_1(sc, R92C_USB_HRPWM, 0);
4696 } else {
4697 urtwn_write_4(sc, R92C_HISR, 0xffffffff);
4698 urtwn_write_4(sc, R92C_HIMR, 0xffffffff);
4699 }
4700
4701 /* Set MAC address. */
4702 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl));
4703 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN);
4704
4705 /* Set initial network type. */
4706 reg = urtwn_read_4(sc, R92C_CR);
4707 switch (ic->ic_opmode) {
4708 case IEEE80211_M_STA:
4709 default:
4710 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA);
4711 break;
4712
4713 case IEEE80211_M_IBSS:
4714 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC);
4715 break;
4716 }
4717 urtwn_write_4(sc, R92C_CR, reg);
4718
4719 /* Set response rate */
4720 reg = urtwn_read_4(sc, R92C_RRSR);
4721 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M);
4722 urtwn_write_4(sc, R92C_RRSR, reg);
4723
4724 /* SIFS (used in NAV) */
4725 urtwn_write_2(sc, R92C_SPEC_SIFS,
4726 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10));
4727
4728 /* Set short/long retry limits. */
4729 urtwn_write_2(sc, R92C_RL,
4730 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30));
4731
4732 /* Initialize EDCA parameters. */
4733 urtwn_edca_init(sc);
4734
4735 /* Setup rate fallback. */
4736 if (!ISSET(sc->chip, URTWN_CHIP_88E) &&
4737 !ISSET(sc->chip, URTWN_CHIP_92EU)) {
4738 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000);
4739 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404);
4740 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201);
4741 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605);
4742 }
4743
4744 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL,
4745 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) |
4746 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW);
4747 /* Set ACK timeout. */
4748 urtwn_write_1(sc, R92C_ACKTO, 0x40);
4749
4750 /* Setup USB aggregation. */
4751 /* Tx */
4752 reg = urtwn_read_4(sc, R92C_TDECTRL);
4753 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6);
4754 urtwn_write_4(sc, R92C_TDECTRL, reg);
4755 /* Rx */
4756 urtwn_write_1(sc, R92C_TRXDMA_CTRL,
4757 urtwn_read_1(sc, R92C_TRXDMA_CTRL) |
4758 R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
4759 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
4760 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) &
4761 ~R92C_USB_SPECIAL_OPTION_AGG_EN);
4762 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
4763 if (ISSET(sc->chip, URTWN_CHIP_88E) ||
4764 ISSET(sc->chip, URTWN_CHIP_92EU))
4765 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4);
4766 else
4767 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4);
4768
4769 /* Initialize beacon parameters. */
4770 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010);
4771 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404);
4772 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRIVER_EARLY_INT_TIME);
4773 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_DMA_ATIME_INT_TIME);
4774 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f);
4775
4776 if (!ISSET(sc->chip, URTWN_CHIP_88E) &&
4777 !ISSET(sc->chip, URTWN_CHIP_92EU)) {
4778 /* Setup AMPDU aggregation. */
4779 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */
4780 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
4781 urtwn_write_2(sc, 0x4ca, 0x0708);
4782
4783 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
4784 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0);
4785 }
4786
4787 /* Load 8051 microcode. */
4788 error = urtwn_load_firmware(sc);
4789 if (error != 0)
4790 goto fail;
4791 SET(sc->sc_flags, URTWN_FLAG_FWREADY);
4792
4793 /* Initialize MAC/BB/RF blocks. */
4794 /*
4795 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM |
4796 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF.
4797 * XXX: This setting should be removed from rtl8192cu_mac[].
4798 */
4799 urtwn_mac_init(sc); // sets R92C_RCR[0:15]
4800 urtwn_rxfilter_init(sc); // reset R92C_RCR
4801 urtwn_bb_init(sc);
4802 urtwn_rf_init(sc);
4803
4804 if (ISSET(sc->chip, URTWN_CHIP_88E) ||
4805 ISSET(sc->chip, URTWN_CHIP_92EU)) {
4806 urtwn_write_2(sc, R92C_CR,
4807 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN |
4808 R92C_CR_MACRXEN);
4809 }
4810
4811 /* Turn CCK and OFDM blocks on. */
4812 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
4813 reg |= R92C_RFMOD_CCK_EN;
4814 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
4815 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
4816 reg |= R92C_RFMOD_OFDM_EN;
4817 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
4818
4819 /* Clear per-station keys table. */
4820 urtwn_cam_init(sc);
4821
4822 /* Enable hardware sequence numbering. */
4823 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff);
4824
4825 /* Perform LO and IQ calibrations. */
4826 urtwn_iq_calib(sc, sc->iqk_inited);
4827 sc->iqk_inited = true;
4828
4829 /* Perform LC calibration. */
4830 urtwn_lc_calib(sc);
4831
4832 if (!ISSET(sc->chip, URTWN_CHIP_88E) &&
4833 !ISSET(sc->chip, URTWN_CHIP_92EU)) {
4834 /* Fix USB interference issue. */
4835 urtwn_write_1(sc, 0xfe40, 0xe0);
4836 urtwn_write_1(sc, 0xfe41, 0x8d);
4837 urtwn_write_1(sc, 0xfe42, 0x80);
4838 urtwn_write_4(sc, 0x20c, 0xfd0320);
4839
4840 urtwn_pa_bias_init(sc);
4841 }
4842
4843 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) ||
4844 !(sc->chip & URTWN_CHIP_92EU)) {
4845 /* 1T1R */
4846 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0),
4847 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13));
4848 }
4849
4850 /* Initialize GPIO setting. */
4851 urtwn_write_1(sc, R92C_GPIO_MUXCFG,
4852 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT);
4853
4854 /* Fix for lower temperature. */
4855 if (!ISSET(sc->chip, URTWN_CHIP_88E) &&
4856 !ISSET(sc->chip, URTWN_CHIP_92EU))
4857 urtwn_write_1(sc, 0x15, 0xe9);
4858
4859 /* Set default channel. */
4860 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE);
4861
4862 /* Queue Rx xfers. */
4863 for (size_t j = 0; j < sc->rx_npipe; j++) {
4864 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) {
4865 data = &sc->rx_data[j][i];
4866 usbd_setup_xfer(data->xfer, data, data->buf,
4867 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT,
4868 urtwn_rxeof);
4869 error = usbd_transfer(data->xfer);
4870 if (__predict_false(error != USBD_NORMAL_COMPLETION &&
4871 error != USBD_IN_PROGRESS))
4872 goto fail;
4873 }
4874 }
4875
4876 /* We're ready to go. */
4877 ifp->if_flags &= ~IFF_OACTIVE;
4878 ifp->if_flags |= IFF_RUNNING;
4879 sc->sc_running = true;
4880
4881 mutex_exit(&sc->sc_write_mtx);
4882
4883 if (ic->ic_opmode == IEEE80211_M_MONITOR)
4884 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
4885 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
4886 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
4887 urtwn_wait_async(sc);
4888
4889 return 0;
4890
4891 fail:
4892 mutex_exit(&sc->sc_write_mtx);
4893
4894 urtwn_stop(ifp, 1);
4895 return error;
4896}
4897
4898static void
4899urtwn_stop(struct ifnet *ifp, int disable)
4900{
4901 struct urtwn_softc *sc = ifp->if_softc;
4902 struct ieee80211com *ic = &sc->sc_ic;
4903 size_t i;
4904 int s;
4905
4906 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
4907
4908 s = splusb();
4909 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
4910 urtwn_wait_async(sc);
4911 splx(s);
4912
4913 sc->tx_timer = 0;
4914 ifp->if_timer = 0;
4915 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
4916
4917 callout_stop(&sc->sc_scan_to);
4918 callout_stop(&sc->sc_calib_to);
4919
4920 /* Abort Tx. */
4921 for (i = 0; i < sc->tx_npipe; i++) {
4922 if (sc->tx_pipe[i] != NULL)
4923 usbd_abort_pipe(sc->tx_pipe[i]);
4924 }
4925
4926 /* Stop Rx pipe. */
4927 for (i = 0; i < sc->rx_npipe; i++) {
4928 if (sc->rx_pipe[i] != NULL)
4929 usbd_abort_pipe(sc->rx_pipe[i]);
4930 }
4931
4932 /* Free Tx/Rx buffers. */
4933 urtwn_free_tx_list(sc);
4934 urtwn_free_rx_list(sc);
4935
4936 sc->sc_running = false;
4937 if (disable)
4938 urtwn_chip_stop(sc);
4939}
4940
4941static int
4942urtwn_reset(struct ifnet *ifp)
4943{
4944 struct urtwn_softc *sc = ifp->if_softc;
4945 struct ieee80211com *ic = &sc->sc_ic;
4946
4947 if (ic->ic_opmode != IEEE80211_M_MONITOR)
4948 return ENETRESET;
4949
4950 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE);
4951
4952 return 0;
4953}
4954
4955static void
4956urtwn_chip_stop(struct urtwn_softc *sc)
4957{
4958 uint32_t reg;
4959 bool disabled = true;
4960
4961 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
4962
4963 if (ISSET(sc->chip, URTWN_CHIP_92EU))
4964 return;
4965
4966 mutex_enter(&sc->sc_write_mtx);
4967
4968 /*
4969 * RF Off Sequence
4970 */
4971 /* Pause MAC TX queue */
4972 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF);
4973
4974 /* Disable RF */
4975 urtwn_rf_write(sc, 0, 0, 0);
4976
4977 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF);
4978
4979 /* Reset BB state machine */
4980 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
4981 R92C_SYS_FUNC_EN_USBD |
4982 R92C_SYS_FUNC_EN_USBA |
4983 R92C_SYS_FUNC_EN_BB_GLB_RST);
4984 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
4985 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA);
4986
4987 /*
4988 * Reset digital sequence
4989 */
4990 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) {
4991 /* Reset MCU ready status */
4992 urtwn_write_1(sc, R92C_MCUFWDL, 0);
4993 /* If firmware in ram code, do reset */
4994 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) {
4995 if (ISSET(sc->chip, URTWN_CHIP_88E) ||
4996 ISSET(sc->chip, URTWN_CHIP_92EU))
4997 urtwn_r88e_fw_reset(sc);
4998 else
4999 urtwn_fw_reset(sc);
5000 CLR(sc->sc_flags, URTWN_FLAG_FWREADY);
5001 }
5002 }
5003
5004 /* Reset MAC and Enable 8051 */
5005 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54);
5006
5007 /* Reset MCU ready status */
5008 urtwn_write_1(sc, R92C_MCUFWDL, 0);
5009
5010 if (disabled) {
5011 /* Disable MAC clock */
5012 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3);
5013 /* Disable AFE PLL */
5014 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80);
5015 /* Gated AFE DIG_CLOCK */
5016 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F);
5017 /* Isolated digital to PON */
5018 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9);
5019 }
5020
5021 /*
5022 * Pull GPIO PIN to balance level and LED control
5023 */
5024 /* 1. Disable GPIO[7:0] */
5025 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000);
5026
5027 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00;
5028 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000;
5029 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg);
5030
5031 /* Disable GPIO[10:8] */
5032 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00);
5033
5034 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0;
5035 reg |= (((reg & 0x000f) << 4) | 0x0780);
5036 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg);
5037
5038 /* Disable LED0 & 1 */
5039 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080);
5040
5041 /*
5042 * Reset digital sequence
5043 */
5044 if (disabled) {
5045 /* Disable ELDR clock */
5046 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3);
5047 /* Isolated ELDR to PON */
5048 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82);
5049 }
5050
5051 /*
5052 * Disable analog sequence
5053 */
5054 if (disabled) {
5055 /* Disable A15 power */
5056 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04);
5057 /* Disable digital core power */
5058 urtwn_write_1(sc, R92C_LDOV12D_CTRL,
5059 urtwn_read_1(sc, R92C_LDOV12D_CTRL) &
5060 ~R92C_LDOV12D_CTRL_LDV12_EN);
5061 }
5062
5063 /* Enter PFM mode */
5064 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23);
5065
5066 /* Set USB suspend */
5067 urtwn_write_2(sc, R92C_APS_FSMCO,
5068 R92C_APS_FSMCO_APDM_HOST |
5069 R92C_APS_FSMCO_AFSM_HSUS |
5070 R92C_APS_FSMCO_PFM_ALDN);
5071
5072 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E);
5073
5074 mutex_exit(&sc->sc_write_mtx);
5075}
5076
5077static void
5078urtwn_delay_ms(struct urtwn_softc *sc, int ms)
5079{
5080 if (sc->sc_running == false)
5081 DELAY(ms * 1000);
5082 else
5083 usbd_delay_ms(sc->sc_udev, ms);
5084}
5085
5086MODULE(MODULE_CLASS_DRIVER, if_urtwn, "bpf");
5087
5088#ifdef _MODULE
5089#include "ioconf.c"
5090#endif
5091
5092static int
5093if_urtwn_modcmd(modcmd_t cmd, void *aux)
5094{
5095 int error = 0;
5096
5097 switch (cmd) {
5098 case MODULE_CMD_INIT:
5099#ifdef _MODULE
5100 error = config_init_component(cfdriver_ioconf_urtwn,
5101 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn);
5102#endif
5103 return error;
5104 case MODULE_CMD_FINI:
5105#ifdef _MODULE
5106 error = config_fini_component(cfdriver_ioconf_urtwn,
5107 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn);
5108#endif
5109 return error;
5110 default:
5111 return ENOTTY;
5112 }
5113}
5114