1 | /* $NetBSD: nouveau_subdev_fb_ramnve0.c,v 1.1.1.1 2014/08/06 12:36:30 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2013 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_fb_ramnve0.c,v 1.1.1.1 2014/08/06 12:36:30 riastradh Exp $" ); |
29 | |
30 | #include <subdev/gpio.h> |
31 | |
32 | #include <subdev/bios.h> |
33 | #include <subdev/bios/pll.h> |
34 | #include <subdev/bios/init.h> |
35 | #include <subdev/bios/rammap.h> |
36 | #include <subdev/bios/timing.h> |
37 | |
38 | #include <subdev/clock.h> |
39 | #include <subdev/clock/pll.h> |
40 | |
41 | #include <subdev/timer.h> |
42 | |
43 | #include <core/option.h> |
44 | |
45 | #include "nvc0.h" |
46 | |
47 | #include "ramfuc.h" |
48 | |
49 | /* binary driver only executes this path if the condition (a) is true |
50 | * for any configuration (combination of rammap+ramcfg+timing) that |
51 | * can be reached on a given card. for now, we will execute the branch |
52 | * unconditionally in the hope that a "false everywhere" in the bios |
53 | * tables doesn't actually mean "don't touch this". |
54 | */ |
55 | #define NOTE00(a) 1 |
56 | |
57 | struct nve0_ramfuc { |
58 | struct ramfuc base; |
59 | |
60 | struct nvbios_pll refpll; |
61 | struct nvbios_pll mempll; |
62 | |
63 | struct ramfuc_reg r_gpioMV; |
64 | u32 r_funcMV[2]; |
65 | struct ramfuc_reg r_gpio2E; |
66 | u32 r_func2E[2]; |
67 | struct ramfuc_reg r_gpiotrig; |
68 | |
69 | struct ramfuc_reg r_0x132020; |
70 | struct ramfuc_reg r_0x132028; |
71 | struct ramfuc_reg r_0x132024; |
72 | struct ramfuc_reg r_0x132030; |
73 | struct ramfuc_reg r_0x132034; |
74 | struct ramfuc_reg r_0x132000; |
75 | struct ramfuc_reg r_0x132004; |
76 | struct ramfuc_reg r_0x132040; |
77 | |
78 | struct ramfuc_reg r_0x10f248; |
79 | struct ramfuc_reg r_0x10f290; |
80 | struct ramfuc_reg r_0x10f294; |
81 | struct ramfuc_reg r_0x10f298; |
82 | struct ramfuc_reg r_0x10f29c; |
83 | struct ramfuc_reg r_0x10f2a0; |
84 | struct ramfuc_reg r_0x10f2a4; |
85 | struct ramfuc_reg r_0x10f2a8; |
86 | struct ramfuc_reg r_0x10f2ac; |
87 | struct ramfuc_reg r_0x10f2cc; |
88 | struct ramfuc_reg r_0x10f2e8; |
89 | struct ramfuc_reg r_0x10f250; |
90 | struct ramfuc_reg r_0x10f24c; |
91 | struct ramfuc_reg r_0x10fec4; |
92 | struct ramfuc_reg r_0x10fec8; |
93 | struct ramfuc_reg r_0x10f604; |
94 | struct ramfuc_reg r_0x10f614; |
95 | struct ramfuc_reg r_0x10f610; |
96 | struct ramfuc_reg r_0x100770; |
97 | struct ramfuc_reg r_0x100778; |
98 | struct ramfuc_reg r_0x10f224; |
99 | |
100 | struct ramfuc_reg r_0x10f870; |
101 | struct ramfuc_reg r_0x10f698; |
102 | struct ramfuc_reg r_0x10f694; |
103 | struct ramfuc_reg r_0x10f6b8; |
104 | struct ramfuc_reg r_0x10f808; |
105 | struct ramfuc_reg r_0x10f670; |
106 | struct ramfuc_reg r_0x10f60c; |
107 | struct ramfuc_reg r_0x10f830; |
108 | struct ramfuc_reg r_0x1373ec; |
109 | struct ramfuc_reg r_0x10f800; |
110 | struct ramfuc_reg r_0x10f82c; |
111 | |
112 | struct ramfuc_reg r_0x10f978; |
113 | struct ramfuc_reg r_0x10f910; |
114 | struct ramfuc_reg r_0x10f914; |
115 | |
116 | struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */ |
117 | |
118 | struct ramfuc_reg r_0x62c000; |
119 | |
120 | struct ramfuc_reg r_0x10f200; |
121 | |
122 | struct ramfuc_reg r_0x10f210; |
123 | struct ramfuc_reg r_0x10f310; |
124 | struct ramfuc_reg r_0x10f314; |
125 | struct ramfuc_reg r_0x10f318; |
126 | struct ramfuc_reg r_0x10f090; |
127 | struct ramfuc_reg r_0x10f69c; |
128 | struct ramfuc_reg r_0x10f824; |
129 | struct ramfuc_reg r_0x1373f0; |
130 | struct ramfuc_reg r_0x1373f4; |
131 | struct ramfuc_reg r_0x137320; |
132 | struct ramfuc_reg r_0x10f65c; |
133 | struct ramfuc_reg r_0x10f6bc; |
134 | struct ramfuc_reg r_0x100710; |
135 | struct ramfuc_reg r_0x100750; |
136 | }; |
137 | |
138 | struct nve0_ram { |
139 | struct nouveau_ram base; |
140 | struct nve0_ramfuc fuc; |
141 | |
142 | u32 parts; |
143 | u32 pmask; |
144 | u32 pnuts; |
145 | |
146 | int from; |
147 | int mode; |
148 | int N1, fN1, M1, P1; |
149 | int N2, M2, P2; |
150 | }; |
151 | |
152 | /******************************************************************************* |
153 | * GDDR5 |
154 | ******************************************************************************/ |
155 | static void |
156 | nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data) |
157 | { |
158 | struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); |
159 | u32 addr = 0x110974, i; |
160 | |
161 | ram_mask(fuc, 0x10f910, mask, data); |
162 | ram_mask(fuc, 0x10f914, mask, data); |
163 | |
164 | for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) { |
165 | if (ram->pmask & (1 << i)) |
166 | continue; |
167 | ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000); |
168 | } |
169 | } |
170 | |
171 | static void |
172 | r1373f4_init(struct nve0_ramfuc *fuc) |
173 | { |
174 | struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); |
175 | const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2); |
176 | const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); |
177 | const u32 runk0 = ram->fN1 << 16; |
178 | const u32 runk1 = ram->fN1; |
179 | |
180 | if (ram->from == 2) { |
181 | ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100); |
182 | ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010); |
183 | } else { |
184 | ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); |
185 | } |
186 | |
187 | ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); |
188 | ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); |
189 | |
190 | /* (re)program refpll, if required */ |
191 | if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef || |
192 | (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) { |
193 | ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); |
194 | ram_mask(fuc, 0x132020, 0x00000001, 0x00000000); |
195 | ram_wr32(fuc, 0x137320, 0x00000000); |
196 | ram_mask(fuc, 0x132030, 0xffff0000, runk0); |
197 | ram_mask(fuc, 0x132034, 0x0000ffff, runk1); |
198 | ram_wr32(fuc, 0x132024, rcoef); |
199 | ram_mask(fuc, 0x132028, 0x00080000, 0x00080000); |
200 | ram_mask(fuc, 0x132020, 0x00000001, 0x00000001); |
201 | ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); |
202 | ram_mask(fuc, 0x132028, 0x00080000, 0x00000000); |
203 | } |
204 | |
205 | /* (re)program mempll, if required */ |
206 | if (ram->mode == 2) { |
207 | ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); |
208 | ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); |
209 | ram_mask(fuc, 0x132004, 0x103fffff, mcoef); |
210 | ram_mask(fuc, 0x132000, 0x00000001, 0x00000001); |
211 | ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000); |
212 | ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100); |
213 | } else { |
214 | ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100); |
215 | } |
216 | |
217 | ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010); |
218 | } |
219 | |
220 | static void |
221 | r1373f4_fini(struct nve0_ramfuc *fuc) |
222 | { |
223 | struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); |
224 | struct nouveau_ram_data *next = ram->base.next; |
225 | u8 v0 = next->bios.ramcfg_11_03_c0; |
226 | u8 v1 = next->bios.ramcfg_11_03_30; |
227 | u32 tmp; |
228 | |
229 | tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000; |
230 | ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16)); |
231 | ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000); |
232 | if (ram->mode == 2) { |
233 | ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000002); |
234 | ram_mask(fuc, 0x1373f4, 0x00001100, 0x000000000); |
235 | } else { |
236 | ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000001); |
237 | ram_mask(fuc, 0x1373f4, 0x00010000, 0x000000000); |
238 | } |
239 | ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4); |
240 | } |
241 | |
242 | static void |
243 | nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg, |
244 | u32 _mask, u32 _data, u32 _copy) |
245 | { |
246 | struct nve0_fb_priv *priv = (void *)nouveau_fb(ram); |
247 | struct ramfuc *fuc = &ram->fuc.base; |
248 | u32 addr = 0x110000 + (reg->addr[0] & 0xfff); |
249 | u32 mask = _mask | _copy; |
250 | u32 data = (_data & _mask) | (reg->data & _copy); |
251 | u32 i; |
252 | |
253 | for (i = 0; i < 16; i++, addr += 0x1000) { |
254 | if (ram->pnuts & (1 << i)) { |
255 | u32 prev = nv_rd32(priv, addr); |
256 | u32 next = (prev & ~mask) | data; |
257 | nouveau_memx_wr32(fuc->memx, addr, next); |
258 | } |
259 | } |
260 | } |
261 | #define ram_nuts(s,r,m,d,c) \ |
262 | nve0_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c)) |
263 | |
264 | static int |
265 | nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) |
266 | { |
267 | struct nve0_ram *ram = (void *)pfb->ram; |
268 | struct nve0_ramfuc *fuc = &ram->fuc; |
269 | struct nouveau_ram_data *next = ram->base.next; |
270 | int vc = !(next->bios.ramcfg_11_02_08); |
271 | int mv = !(next->bios.ramcfg_11_02_04); |
272 | u32 mask, data; |
273 | |
274 | ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); |
275 | ram_wr32(fuc, 0x62c000, 0x0f0f0000); |
276 | |
277 | /* MR1: turn termination on early, for some reason.. */ |
278 | if ((ram->base.mr[1] & 0x03c) != 0x030) { |
279 | ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c); |
280 | ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000); |
281 | } |
282 | |
283 | if (vc == 1 && ram_have(fuc, gpio2E)) { |
284 | u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]); |
285 | if (temp != ram_rd32(fuc, gpio2E)) { |
286 | ram_wr32(fuc, gpiotrig, 1); |
287 | ram_nsec(fuc, 20000); |
288 | } |
289 | } |
290 | |
291 | ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); |
292 | |
293 | nve0_ram_train(fuc, 0x01020000, 0x000c0000); |
294 | |
295 | ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ |
296 | ram_nsec(fuc, 1000); |
297 | ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ |
298 | ram_nsec(fuc, 1000); |
299 | |
300 | ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); |
301 | ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ |
302 | ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); |
303 | ram_wr32(fuc, 0x10f090, 0x00000061); |
304 | ram_wr32(fuc, 0x10f090, 0xc000007f); |
305 | ram_nsec(fuc, 1000); |
306 | |
307 | ram_wr32(fuc, 0x10f698, 0x00000000); |
308 | ram_wr32(fuc, 0x10f69c, 0x00000000); |
309 | |
310 | /*XXX: there does appear to be some kind of condition here, simply |
311 | * modifying these bits in the vbios from the default pl0 |
312 | * entries shows no change. however, the data does appear to |
313 | * be correct and may be required for the transition back |
314 | */ |
315 | mask = 0x800f07e0; |
316 | data = 0x00030000; |
317 | if (ram_rd32(fuc, 0x10f978) & 0x00800000) |
318 | data |= 0x00040000; |
319 | |
320 | if (1) { |
321 | data |= 0x800807e0; |
322 | switch (next->bios.ramcfg_11_03_c0) { |
323 | case 3: data &= ~0x00000040; break; |
324 | case 2: data &= ~0x00000100; break; |
325 | case 1: data &= ~0x80000000; break; |
326 | case 0: data &= ~0x00000400; break; |
327 | } |
328 | |
329 | switch (next->bios.ramcfg_11_03_30) { |
330 | case 3: data &= ~0x00000020; break; |
331 | case 2: data &= ~0x00000080; break; |
332 | case 1: data &= ~0x00080000; break; |
333 | case 0: data &= ~0x00000200; break; |
334 | } |
335 | } |
336 | |
337 | if (next->bios.ramcfg_11_02_80) |
338 | mask |= 0x03000000; |
339 | if (next->bios.ramcfg_11_02_40) |
340 | mask |= 0x00002000; |
341 | if (next->bios.ramcfg_11_07_10) |
342 | mask |= 0x00004000; |
343 | if (next->bios.ramcfg_11_07_08) |
344 | mask |= 0x00000003; |
345 | else { |
346 | mask |= 0x34000000; |
347 | if (ram_rd32(fuc, 0x10f978) & 0x00800000) |
348 | mask |= 0x40000000; |
349 | } |
350 | ram_mask(fuc, 0x10f824, mask, data); |
351 | |
352 | ram_mask(fuc, 0x132040, 0x00010000, 0x00000000); |
353 | |
354 | if (ram->from == 2 && ram->mode != 2) { |
355 | ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000); |
356 | ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000); |
357 | ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004); |
358 | ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010); |
359 | ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); |
360 | r1373f4_init(fuc); |
361 | ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001); |
362 | r1373f4_fini(fuc); |
363 | ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001); |
364 | } else |
365 | if (ram->from != 2 && ram->mode != 2) { |
366 | r1373f4_init(fuc); |
367 | r1373f4_fini(fuc); |
368 | } |
369 | |
370 | if (ram_have(fuc, gpioMV)) { |
371 | u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]); |
372 | if (temp != ram_rd32(fuc, gpioMV)) { |
373 | ram_wr32(fuc, gpiotrig, 1); |
374 | ram_nsec(fuc, 64000); |
375 | } |
376 | } |
377 | |
378 | if ( (next->bios.ramcfg_11_02_40) || |
379 | (next->bios.ramcfg_11_07_10)) { |
380 | ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); |
381 | ram_nsec(fuc, 20000); |
382 | } |
383 | |
384 | if (ram->from != 2 && ram->mode == 2) { |
385 | if (0 /*XXX: Titan */) |
386 | ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000); |
387 | ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); |
388 | ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002); |
389 | ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010); |
390 | r1373f4_init(fuc); |
391 | r1373f4_fini(fuc); |
392 | ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000); |
393 | ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000); |
394 | } else |
395 | if (ram->from == 2 && ram->mode == 2) { |
396 | ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); |
397 | r1373f4_init(fuc); |
398 | r1373f4_fini(fuc); |
399 | } |
400 | |
401 | if (ram->mode != 2) /*XXX*/ { |
402 | if (next->bios.ramcfg_11_07_40) |
403 | ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); |
404 | } |
405 | |
406 | ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c); |
407 | ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09); |
408 | ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09); |
409 | |
410 | if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) { |
411 | ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04); |
412 | ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04); |
413 | } else |
414 | if (!next->bios.ramcfg_11_07_08) { |
415 | ram_wr32(fuc, 0x10f698, 0x00000000); |
416 | ram_wr32(fuc, 0x10f69c, 0x00000000); |
417 | } |
418 | |
419 | if (ram->mode != 2) { |
420 | u32 data = 0x01000100 * next->bios.ramcfg_11_04; |
421 | ram_nuke(fuc, 0x10f694); |
422 | ram_mask(fuc, 0x10f694, 0xff00ff00, data); |
423 | } |
424 | |
425 | if (ram->mode == 2 && (next->bios.ramcfg_11_08_10)) |
426 | data = 0x00000080; |
427 | else |
428 | data = 0x00000000; |
429 | ram_mask(fuc, 0x10f60c, 0x00000080, data); |
430 | |
431 | mask = 0x00070000; |
432 | data = 0x00000000; |
433 | if (!(next->bios.ramcfg_11_02_80)) |
434 | data |= 0x03000000; |
435 | if (!(next->bios.ramcfg_11_02_40)) |
436 | data |= 0x00002000; |
437 | if (!(next->bios.ramcfg_11_07_10)) |
438 | data |= 0x00004000; |
439 | if (!(next->bios.ramcfg_11_07_08)) |
440 | data |= 0x00000003; |
441 | else |
442 | data |= 0x74000000; |
443 | ram_mask(fuc, 0x10f824, mask, data); |
444 | |
445 | if (next->bios.ramcfg_11_01_08) |
446 | data = 0x00000000; |
447 | else |
448 | data = 0x00001000; |
449 | ram_mask(fuc, 0x10f200, 0x00001000, data); |
450 | |
451 | if (ram_rd32(fuc, 0x10f670) & 0x80000000) { |
452 | ram_nsec(fuc, 10000); |
453 | ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000); |
454 | } |
455 | |
456 | if (next->bios.ramcfg_11_08_01) |
457 | data = 0x00100000; |
458 | else |
459 | data = 0x00000000; |
460 | ram_mask(fuc, 0x10f82c, 0x00100000, data); |
461 | |
462 | data = 0x00000000; |
463 | if (next->bios.ramcfg_11_08_08) |
464 | data |= 0x00002000; |
465 | if (next->bios.ramcfg_11_08_04) |
466 | data |= 0x00001000; |
467 | if (next->bios.ramcfg_11_08_02) |
468 | data |= 0x00004000; |
469 | ram_mask(fuc, 0x10f830, 0x00007000, data); |
470 | |
471 | /* PFB timing */ |
472 | ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); |
473 | ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); |
474 | ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); |
475 | ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); |
476 | ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); |
477 | ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); |
478 | ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); |
479 | ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); |
480 | ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); |
481 | ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); |
482 | ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); |
483 | |
484 | data = mask = 0x00000000; |
485 | if (NOTE00(ramcfg_08_20)) { |
486 | if (next->bios.ramcfg_11_08_20) |
487 | data |= 0x01000000; |
488 | mask |= 0x01000000; |
489 | } |
490 | ram_mask(fuc, 0x10f200, mask, data); |
491 | |
492 | data = mask = 0x00000000; |
493 | if (NOTE00(ramcfg_02_03 != 0)) { |
494 | data |= (next->bios.ramcfg_11_02_03) << 8; |
495 | mask |= 0x00000300; |
496 | } |
497 | if (NOTE00(ramcfg_01_10)) { |
498 | if (next->bios.ramcfg_11_01_10) |
499 | data |= 0x70000000; |
500 | mask |= 0x70000000; |
501 | } |
502 | ram_mask(fuc, 0x10f604, mask, data); |
503 | |
504 | data = mask = 0x00000000; |
505 | if (NOTE00(timing_30_07 != 0)) { |
506 | data |= (next->bios.timing_20_30_07) << 28; |
507 | mask |= 0x70000000; |
508 | } |
509 | if (NOTE00(ramcfg_01_01)) { |
510 | if (next->bios.ramcfg_11_01_01) |
511 | data |= 0x00000100; |
512 | mask |= 0x00000100; |
513 | } |
514 | ram_mask(fuc, 0x10f614, mask, data); |
515 | |
516 | data = mask = 0x00000000; |
517 | if (NOTE00(timing_30_07 != 0)) { |
518 | data |= (next->bios.timing_20_30_07) << 28; |
519 | mask |= 0x70000000; |
520 | } |
521 | if (NOTE00(ramcfg_01_02)) { |
522 | if (next->bios.ramcfg_11_01_02) |
523 | data |= 0x00000100; |
524 | mask |= 0x00000100; |
525 | } |
526 | ram_mask(fuc, 0x10f610, mask, data); |
527 | |
528 | mask = 0x33f00000; |
529 | data = 0x00000000; |
530 | if (!(next->bios.ramcfg_11_01_04)) |
531 | data |= 0x20200000; |
532 | if (!(next->bios.ramcfg_11_07_80)) |
533 | data |= 0x12800000; |
534 | /*XXX: see note above about there probably being some condition |
535 | * for the 10f824 stuff that uses ramcfg 3... |
536 | */ |
537 | if ( (next->bios.ramcfg_11_03_f0)) { |
538 | if (next->bios.rammap_11_08_0c) { |
539 | if (!(next->bios.ramcfg_11_07_80)) |
540 | mask |= 0x00000020; |
541 | else |
542 | data |= 0x00000020; |
543 | mask |= 0x00000004; |
544 | } |
545 | } else { |
546 | mask |= 0x40000020; |
547 | data |= 0x00000004; |
548 | } |
549 | |
550 | ram_mask(fuc, 0x10f808, mask, data); |
551 | |
552 | ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); |
553 | |
554 | data = mask = 0x00000000; |
555 | if (NOTE00(ramcfg_02_03 != 0)) { |
556 | data |= next->bios.ramcfg_11_02_03; |
557 | mask |= 0x00000003; |
558 | } |
559 | if (NOTE00(ramcfg_01_10)) { |
560 | if (next->bios.ramcfg_11_01_10) |
561 | data |= 0x00000004; |
562 | mask |= 0x00000004; |
563 | } |
564 | |
565 | if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) { |
566 | ram_mask(fuc, 0x100750, 0x00000008, 0x00000008); |
567 | ram_wr32(fuc, 0x100710, 0x00000000); |
568 | ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000); |
569 | } |
570 | |
571 | data = (next->bios.timing_20_30_07) << 8; |
572 | if (next->bios.ramcfg_11_01_01) |
573 | data |= 0x80000000; |
574 | ram_mask(fuc, 0x100778, 0x00000700, data); |
575 | |
576 | ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4); |
577 | data = (next->bios.timing[10] & 0x7f000000) >> 24; |
578 | if (data < next->bios.timing_20_2c_1fc0) |
579 | data = next->bios.timing_20_2c_1fc0; |
580 | ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); |
581 | ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16); |
582 | |
583 | ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 | |
584 | next->bios.timing_20_31_0780 << 17 | |
585 | next->bios.timing_20_31_0078 << 8 | |
586 | next->bios.timing_20_31_0007); |
587 | ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 | |
588 | next->bios.timing_20_31_7000); |
589 | |
590 | ram_wr32(fuc, 0x10f090, 0x4000007e); |
591 | ram_nsec(fuc, 2000); |
592 | ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ |
593 | ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ |
594 | ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ |
595 | |
596 | if ((next->bios.ramcfg_11_08_10) && (ram->mode == 2) /*XXX*/) { |
597 | u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); |
598 | nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ |
599 | ram_nsec(fuc, 1000); |
600 | ram_wr32(fuc, 0x10f294, temp); |
601 | } |
602 | |
603 | ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]); |
604 | ram_wr32(fuc, mr[0], ram->base.mr[0]); |
605 | ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]); |
606 | ram_nsec(fuc, 1000); |
607 | ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]); |
608 | ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */ |
609 | ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]); |
610 | ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]); |
611 | |
612 | if (vc == 0 && ram_have(fuc, gpio2E)) { |
613 | u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]); |
614 | if (temp != ram_rd32(fuc, gpio2E)) { |
615 | ram_wr32(fuc, gpiotrig, 1); |
616 | ram_nsec(fuc, 20000); |
617 | } |
618 | } |
619 | |
620 | ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); |
621 | ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */ |
622 | ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); |
623 | ram_nsec(fuc, 1000); |
624 | ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800); |
625 | |
626 | data = ram_rd32(fuc, 0x10f978); |
627 | data &= ~0x00046144; |
628 | data |= 0x0000000b; |
629 | if (!(next->bios.ramcfg_11_07_08)) { |
630 | if (!(next->bios.ramcfg_11_07_04)) |
631 | data |= 0x0000200c; |
632 | else |
633 | data |= 0x00000000; |
634 | } else { |
635 | data |= 0x00040044; |
636 | } |
637 | ram_wr32(fuc, 0x10f978, data); |
638 | |
639 | if (ram->mode == 1) { |
640 | data = ram_rd32(fuc, 0x10f830) | 0x00000001; |
641 | ram_wr32(fuc, 0x10f830, data); |
642 | } |
643 | |
644 | if (!(next->bios.ramcfg_11_07_08)) { |
645 | data = 0x88020000; |
646 | if ( (next->bios.ramcfg_11_07_04)) |
647 | data |= 0x10000000; |
648 | if (!(next->bios.rammap_11_08_10)) |
649 | data |= 0x00080000; |
650 | } else { |
651 | data = 0xa40e0000; |
652 | } |
653 | nve0_ram_train(fuc, 0xbc0f0000, data); |
654 | if (1) /* XXX: not always? */ |
655 | ram_nsec(fuc, 1000); |
656 | |
657 | if (ram->mode == 2) { /*XXX*/ |
658 | ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004); |
659 | } |
660 | |
661 | /* LP3 */ |
662 | if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5]) |
663 | ram_nsec(fuc, 1000); |
664 | |
665 | if (ram->mode != 2) { |
666 | ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000); |
667 | ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); |
668 | } |
669 | |
670 | if (next->bios.ramcfg_11_07_02) |
671 | nve0_ram_train(fuc, 0x80020000, 0x01000000); |
672 | |
673 | ram_wr32(fuc, 0x62c000, 0x0f0f0f00); |
674 | |
675 | if (next->bios.rammap_11_08_01) |
676 | data = 0x00000800; |
677 | else |
678 | data = 0x00000000; |
679 | ram_mask(fuc, 0x10f200, 0x00000800, data); |
680 | ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800); |
681 | return 0; |
682 | } |
683 | |
684 | /******************************************************************************* |
685 | * DDR3 |
686 | ******************************************************************************/ |
687 | |
688 | static int |
689 | nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) |
690 | { |
691 | struct nve0_ram *ram = (void *)pfb->ram; |
692 | struct nve0_ramfuc *fuc = &ram->fuc; |
693 | const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); |
694 | const u32 runk0 = ram->fN1 << 16; |
695 | const u32 runk1 = ram->fN1; |
696 | struct nouveau_ram_data *next = ram->base.next; |
697 | int vc = !(next->bios.ramcfg_11_02_08); |
698 | int mv = !(next->bios.ramcfg_11_02_04); |
699 | u32 mask, data; |
700 | |
701 | ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); |
702 | ram_wr32(fuc, 0x62c000, 0x0f0f0000); |
703 | |
704 | if (vc == 1 && ram_have(fuc, gpio2E)) { |
705 | u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]); |
706 | if (temp != ram_rd32(fuc, gpio2E)) { |
707 | ram_wr32(fuc, gpiotrig, 1); |
708 | ram_nsec(fuc, 20000); |
709 | } |
710 | } |
711 | |
712 | ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); |
713 | if ((next->bios.ramcfg_11_03_f0)) |
714 | ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000); |
715 | |
716 | ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ |
717 | ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ |
718 | ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ |
719 | ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); |
720 | ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ |
721 | ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); |
722 | ram_nsec(fuc, 1000); |
723 | |
724 | ram_wr32(fuc, 0x10f090, 0x00000060); |
725 | ram_wr32(fuc, 0x10f090, 0xc000007e); |
726 | |
727 | /*XXX: there does appear to be some kind of condition here, simply |
728 | * modifying these bits in the vbios from the default pl0 |
729 | * entries shows no change. however, the data does appear to |
730 | * be correct and may be required for the transition back |
731 | */ |
732 | mask = 0x00010000; |
733 | data = 0x00010000; |
734 | |
735 | if (1) { |
736 | mask |= 0x800807e0; |
737 | data |= 0x800807e0; |
738 | switch (next->bios.ramcfg_11_03_c0) { |
739 | case 3: data &= ~0x00000040; break; |
740 | case 2: data &= ~0x00000100; break; |
741 | case 1: data &= ~0x80000000; break; |
742 | case 0: data &= ~0x00000400; break; |
743 | } |
744 | |
745 | switch (next->bios.ramcfg_11_03_30) { |
746 | case 3: data &= ~0x00000020; break; |
747 | case 2: data &= ~0x00000080; break; |
748 | case 1: data &= ~0x00080000; break; |
749 | case 0: data &= ~0x00000200; break; |
750 | } |
751 | } |
752 | |
753 | if (next->bios.ramcfg_11_02_80) |
754 | mask |= 0x03000000; |
755 | if (next->bios.ramcfg_11_02_40) |
756 | mask |= 0x00002000; |
757 | if (next->bios.ramcfg_11_07_10) |
758 | mask |= 0x00004000; |
759 | if (next->bios.ramcfg_11_07_08) |
760 | mask |= 0x00000003; |
761 | else |
762 | mask |= 0x14000000; |
763 | ram_mask(fuc, 0x10f824, mask, data); |
764 | |
765 | ram_mask(fuc, 0x132040, 0x00010000, 0x00000000); |
766 | |
767 | ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); |
768 | data = ram_rd32(fuc, 0x1373ec) & ~0x00030000; |
769 | data |= (next->bios.ramcfg_11_03_30) << 12; |
770 | ram_wr32(fuc, 0x1373ec, data); |
771 | ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); |
772 | ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); |
773 | |
774 | /* (re)program refpll, if required */ |
775 | if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef || |
776 | (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) { |
777 | ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); |
778 | ram_mask(fuc, 0x132020, 0x00000001, 0x00000000); |
779 | ram_wr32(fuc, 0x137320, 0x00000000); |
780 | ram_mask(fuc, 0x132030, 0xffff0000, runk0); |
781 | ram_mask(fuc, 0x132034, 0x0000ffff, runk1); |
782 | ram_wr32(fuc, 0x132024, rcoef); |
783 | ram_mask(fuc, 0x132028, 0x00080000, 0x00080000); |
784 | ram_mask(fuc, 0x132020, 0x00000001, 0x00000001); |
785 | ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); |
786 | ram_mask(fuc, 0x132028, 0x00080000, 0x00000000); |
787 | } |
788 | |
789 | ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010); |
790 | ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001); |
791 | ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); |
792 | |
793 | if (ram_have(fuc, gpioMV)) { |
794 | u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]); |
795 | if (temp != ram_rd32(fuc, gpioMV)) { |
796 | ram_wr32(fuc, gpiotrig, 1); |
797 | ram_nsec(fuc, 64000); |
798 | } |
799 | } |
800 | |
801 | if ( (next->bios.ramcfg_11_02_40) || |
802 | (next->bios.ramcfg_11_07_10)) { |
803 | ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); |
804 | ram_nsec(fuc, 20000); |
805 | } |
806 | |
807 | if (ram->mode != 2) /*XXX*/ { |
808 | if (next->bios.ramcfg_11_07_40) |
809 | ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); |
810 | } |
811 | |
812 | ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c); |
813 | ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09); |
814 | ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09); |
815 | |
816 | mask = 0x00010000; |
817 | data = 0x00000000; |
818 | if (!(next->bios.ramcfg_11_02_80)) |
819 | data |= 0x03000000; |
820 | if (!(next->bios.ramcfg_11_02_40)) |
821 | data |= 0x00002000; |
822 | if (!(next->bios.ramcfg_11_07_10)) |
823 | data |= 0x00004000; |
824 | if (!(next->bios.ramcfg_11_07_08)) |
825 | data |= 0x00000003; |
826 | else |
827 | data |= 0x14000000; |
828 | ram_mask(fuc, 0x10f824, mask, data); |
829 | ram_nsec(fuc, 1000); |
830 | |
831 | if (next->bios.ramcfg_11_08_01) |
832 | data = 0x00100000; |
833 | else |
834 | data = 0x00000000; |
835 | ram_mask(fuc, 0x10f82c, 0x00100000, data); |
836 | |
837 | /* PFB timing */ |
838 | ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); |
839 | ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); |
840 | ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); |
841 | ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); |
842 | ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); |
843 | ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); |
844 | ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); |
845 | ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); |
846 | ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); |
847 | ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); |
848 | ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); |
849 | |
850 | mask = 0x33f00000; |
851 | data = 0x00000000; |
852 | if (!(next->bios.ramcfg_11_01_04)) |
853 | data |= 0x20200000; |
854 | if (!(next->bios.ramcfg_11_07_80)) |
855 | data |= 0x12800000; |
856 | /*XXX: see note above about there probably being some condition |
857 | * for the 10f824 stuff that uses ramcfg 3... |
858 | */ |
859 | if ( (next->bios.ramcfg_11_03_f0)) { |
860 | if (next->bios.rammap_11_08_0c) { |
861 | if (!(next->bios.ramcfg_11_07_80)) |
862 | mask |= 0x00000020; |
863 | else |
864 | data |= 0x00000020; |
865 | mask |= 0x08000004; |
866 | } |
867 | data |= 0x04000000; |
868 | } else { |
869 | mask |= 0x44000020; |
870 | data |= 0x08000004; |
871 | } |
872 | |
873 | ram_mask(fuc, 0x10f808, mask, data); |
874 | |
875 | ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); |
876 | |
877 | ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4); |
878 | |
879 | data = (next->bios.timing[10] & 0x7f000000) >> 24; |
880 | if (data < next->bios.timing_20_2c_1fc0) |
881 | data = next->bios.timing_20_2c_1fc0; |
882 | ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); |
883 | |
884 | ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8); |
885 | |
886 | ram_wr32(fuc, 0x10f090, 0x4000007f); |
887 | ram_nsec(fuc, 1000); |
888 | |
889 | ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ |
890 | ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ |
891 | ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ |
892 | ram_nsec(fuc, 1000); |
893 | |
894 | ram_nuke(fuc, mr[0]); |
895 | ram_mask(fuc, mr[0], 0x100, 0x100); |
896 | ram_mask(fuc, mr[0], 0x100, 0x000); |
897 | |
898 | ram_mask(fuc, mr[2], 0xfff, ram->base.mr[2]); |
899 | ram_wr32(fuc, mr[0], ram->base.mr[0]); |
900 | ram_nsec(fuc, 1000); |
901 | |
902 | ram_nuke(fuc, mr[0]); |
903 | ram_mask(fuc, mr[0], 0x100, 0x100); |
904 | ram_mask(fuc, mr[0], 0x100, 0x000); |
905 | |
906 | if (vc == 0 && ram_have(fuc, gpio2E)) { |
907 | u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]); |
908 | if (temp != ram_rd32(fuc, gpio2E)) { |
909 | ram_wr32(fuc, gpiotrig, 1); |
910 | ram_nsec(fuc, 20000); |
911 | } |
912 | } |
913 | |
914 | if (ram->mode != 2) { |
915 | ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000); |
916 | ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); |
917 | } |
918 | |
919 | ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); |
920 | ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */ |
921 | ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); |
922 | ram_nsec(fuc, 1000); |
923 | |
924 | ram_wr32(fuc, 0x62c000, 0x0f0f0f00); |
925 | |
926 | if (next->bios.rammap_11_08_01) |
927 | data = 0x00000800; |
928 | else |
929 | data = 0x00000000; |
930 | ram_mask(fuc, 0x10f200, 0x00000800, data); |
931 | return 0; |
932 | } |
933 | |
934 | /******************************************************************************* |
935 | * main hooks |
936 | ******************************************************************************/ |
937 | |
938 | static int |
939 | nve0_ram_calc_data(struct nouveau_fb *pfb, u32 freq, |
940 | struct nouveau_ram_data *data) |
941 | { |
942 | struct nouveau_bios *bios = nouveau_bios(pfb); |
943 | struct nve0_ram *ram = (void *)pfb->ram; |
944 | u8 strap, cnt, len; |
945 | |
946 | /* lookup memory config data relevant to the target frequency */ |
947 | ram->base.rammap.data = nvbios_rammapEp(bios, freq / 1000, |
948 | &ram->base.rammap.version, |
949 | &ram->base.rammap.size, |
950 | &cnt, &len, &data->bios); |
951 | if (!ram->base.rammap.data || ram->base.rammap.version != 0x11 || |
952 | ram->base.rammap.size < 0x09) { |
953 | nv_error(pfb, "invalid/missing rammap entry\n" ); |
954 | return -EINVAL; |
955 | } |
956 | |
957 | /* locate specific data set for the attached memory */ |
958 | strap = nvbios_ramcfg_index(nv_subdev(pfb)); |
959 | ram->base.ramcfg.data = nvbios_rammapSp(bios, ram->base.rammap.data, |
960 | ram->base.rammap.version, |
961 | ram->base.rammap.size, |
962 | cnt, len, strap, |
963 | &ram->base.ramcfg.version, |
964 | &ram->base.ramcfg.size, |
965 | &data->bios); |
966 | if (!ram->base.ramcfg.data || ram->base.ramcfg.version != 0x11 || |
967 | ram->base.ramcfg.size < 0x08) { |
968 | nv_error(pfb, "invalid/missing ramcfg entry\n" ); |
969 | return -EINVAL; |
970 | } |
971 | |
972 | /* lookup memory timings, if bios says they're present */ |
973 | strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00); |
974 | if (strap != 0xff) { |
975 | ram->base.timing.data = |
976 | nvbios_timingEp(bios, strap, &ram->base.timing.version, |
977 | &ram->base.timing.size, &cnt, &len, |
978 | &data->bios); |
979 | if (!ram->base.timing.data || |
980 | ram->base.timing.version != 0x20 || |
981 | ram->base.timing.size < 0x33) { |
982 | nv_error(pfb, "invalid/missing timing entry\n" ); |
983 | return -EINVAL; |
984 | } |
985 | } else { |
986 | ram->base.timing.data = 0; |
987 | } |
988 | |
989 | data->freq = freq; |
990 | return 0; |
991 | } |
992 | |
993 | static int |
994 | nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) |
995 | { |
996 | struct nve0_ram *ram = (void *)pfb->ram; |
997 | struct nve0_ramfuc *fuc = &ram->fuc; |
998 | int refclk, i; |
999 | int ret; |
1000 | |
1001 | ret = ram_init(fuc, pfb); |
1002 | if (ret) |
1003 | return ret; |
1004 | |
1005 | ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1; |
1006 | ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f; |
1007 | |
1008 | /* XXX: this is *not* what nvidia do. on fermi nvidia generally |
1009 | * select, based on some unknown condition, one of the two possible |
1010 | * reference frequencies listed in the vbios table for mempll and |
1011 | * program refpll to that frequency. |
1012 | * |
1013 | * so far, i've seen very weird values being chosen by nvidia on |
1014 | * kepler boards, no idea how/why they're chosen. |
1015 | */ |
1016 | refclk = next->freq; |
1017 | if (ram->mode == 2) |
1018 | refclk = fuc->mempll.refclk; |
1019 | |
1020 | /* calculate refpll coefficients */ |
1021 | ret = nva3_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1, |
1022 | &ram->fN1, &ram->M1, &ram->P1); |
1023 | fuc->mempll.refclk = ret; |
1024 | if (ret <= 0) { |
1025 | nv_error(pfb, "unable to calc refpll\n" ); |
1026 | return -EINVAL; |
1027 | } |
1028 | |
1029 | /* calculate mempll coefficients, if we're using it */ |
1030 | if (ram->mode == 2) { |
1031 | /* post-divider doesn't work... the reg takes the values but |
1032 | * appears to completely ignore it. there *is* a bit at |
1033 | * bit 28 that appears to divide the clock by 2 if set. |
1034 | */ |
1035 | fuc->mempll.min_p = 1; |
1036 | fuc->mempll.max_p = 2; |
1037 | |
1038 | ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq, |
1039 | &ram->N2, NULL, &ram->M2, &ram->P2); |
1040 | if (ret <= 0) { |
1041 | nv_error(pfb, "unable to calc mempll\n" ); |
1042 | return -EINVAL; |
1043 | } |
1044 | } |
1045 | |
1046 | for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) { |
1047 | if (ram_have(fuc, mr[i])) |
1048 | ram->base.mr[i] = ram_rd32(fuc, mr[i]); |
1049 | } |
1050 | ram->base.freq = next->freq; |
1051 | |
1052 | switch (ram->base.type) { |
1053 | case NV_MEM_TYPE_DDR3: |
1054 | ret = nouveau_sddr3_calc(&ram->base); |
1055 | if (ret == 0) |
1056 | ret = nve0_ram_calc_sddr3(pfb, next->freq); |
1057 | break; |
1058 | case NV_MEM_TYPE_GDDR5: |
1059 | ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0); |
1060 | if (ret == 0) |
1061 | ret = nve0_ram_calc_gddr5(pfb, next->freq); |
1062 | break; |
1063 | default: |
1064 | ret = -ENOSYS; |
1065 | break; |
1066 | } |
1067 | |
1068 | return ret; |
1069 | } |
1070 | |
1071 | static int |
1072 | nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) |
1073 | { |
1074 | struct nouveau_clock *clk = nouveau_clock(pfb); |
1075 | struct nve0_ram *ram = (void *)pfb->ram; |
1076 | struct nouveau_ram_data *xits = &ram->base.xition; |
1077 | struct nouveau_ram_data *copy; |
1078 | int ret; |
1079 | |
1080 | if (ram->base.next == NULL) { |
1081 | ret = nve0_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem), |
1082 | &ram->base.former); |
1083 | if (ret) |
1084 | return ret; |
1085 | |
1086 | ret = nve0_ram_calc_data(pfb, freq, &ram->base.target); |
1087 | if (ret) |
1088 | return ret; |
1089 | |
1090 | if (ram->base.target.freq < ram->base.former.freq) { |
1091 | *xits = ram->base.target; |
1092 | copy = &ram->base.former; |
1093 | } else { |
1094 | *xits = ram->base.former; |
1095 | copy = &ram->base.target; |
1096 | } |
1097 | |
1098 | xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04; |
1099 | xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03; |
1100 | xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07; |
1101 | |
1102 | ram->base.next = &ram->base.target; |
1103 | if (memcmp(xits, &ram->base.former, sizeof(xits->bios))) |
1104 | ram->base.next = &ram->base.xition; |
1105 | } else { |
1106 | BUG_ON(ram->base.next != &ram->base.xition); |
1107 | ram->base.next = &ram->base.target; |
1108 | } |
1109 | |
1110 | return nve0_ram_calc_xits(pfb, ram->base.next); |
1111 | } |
1112 | |
1113 | static int |
1114 | nve0_ram_prog(struct nouveau_fb *pfb) |
1115 | { |
1116 | struct nouveau_device *device = nv_device(pfb); |
1117 | struct nve0_ram *ram = (void *)pfb->ram; |
1118 | struct nve0_ramfuc *fuc = &ram->fuc; |
1119 | ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec" , false)); |
1120 | return (ram->base.next == &ram->base.xition); |
1121 | } |
1122 | |
1123 | static void |
1124 | nve0_ram_tidy(struct nouveau_fb *pfb) |
1125 | { |
1126 | struct nve0_ram *ram = (void *)pfb->ram; |
1127 | struct nve0_ramfuc *fuc = &ram->fuc; |
1128 | ram->base.next = NULL; |
1129 | ram_exec(fuc, false); |
1130 | } |
1131 | |
1132 | int |
1133 | nve0_ram_init(struct nouveau_object *object) |
1134 | { |
1135 | struct nouveau_fb *pfb = (void *)object->parent; |
1136 | struct nve0_ram *ram = (void *)object; |
1137 | struct nouveau_bios *bios = nouveau_bios(pfb); |
1138 | static const u8 train0[] = { |
1139 | 0x00, 0xff, 0xff, 0x00, 0xff, 0x00, |
1140 | 0x00, 0xff, 0xff, 0x00, 0xff, 0x00, |
1141 | }; |
1142 | static const u32 train1[] = { |
1143 | 0x00000000, 0xffffffff, |
1144 | 0x55555555, 0xaaaaaaaa, |
1145 | 0x33333333, 0xcccccccc, |
1146 | 0xf0f0f0f0, 0x0f0f0f0f, |
1147 | 0x00ff00ff, 0xff00ff00, |
1148 | 0x0000ffff, 0xffff0000, |
1149 | }; |
1150 | u8 ver, hdr, cnt, len, snr, ssz; |
1151 | u32 data, save; |
1152 | int ret, i; |
1153 | |
1154 | ret = nouveau_ram_init(&ram->base); |
1155 | if (ret) |
1156 | return ret; |
1157 | |
1158 | /* run a bunch of tables from rammap table. there's actually |
1159 | * individual pointers for each rammap entry too, but, nvidia |
1160 | * seem to just run the last two entries' scripts early on in |
1161 | * their init, and never again.. we'll just run 'em all once |
1162 | * for now. |
1163 | * |
1164 | * i strongly suspect that each script is for a separate mode |
1165 | * (likely selected by 0x10f65c's lower bits?), and the |
1166 | * binary driver skips the one that's already been setup by |
1167 | * the init tables. |
1168 | */ |
1169 | data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz); |
1170 | if (!data || hdr < 0x15) |
1171 | return -EINVAL; |
1172 | |
1173 | cnt = nv_ro08(bios, data + 0x14); /* guess at count */ |
1174 | data = nv_ro32(bios, data + 0x10); /* guess u32... */ |
1175 | save = nv_rd32(pfb, 0x10f65c); |
1176 | for (i = 0; i < cnt; i++) { |
1177 | nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4); |
1178 | nvbios_exec(&(struct nvbios_init) { |
1179 | .subdev = nv_subdev(pfb), |
1180 | .bios = bios, |
1181 | .offset = nv_ro32(bios, data), /* guess u32 */ |
1182 | .execute = 1, |
1183 | }); |
1184 | data += 4; |
1185 | } |
1186 | nv_wr32(pfb, 0x10f65c, save); |
1187 | nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000); |
1188 | |
1189 | switch (ram->base.type) { |
1190 | case NV_MEM_TYPE_GDDR5: |
1191 | for (i = 0; i < 0x30; i++) { |
1192 | nv_wr32(pfb, 0x10f968, 0x00000000 | (i << 8)); |
1193 | nv_wr32(pfb, 0x10f920, 0x00000000 | train0[i % 12]); |
1194 | nv_wr32(pfb, 0x10f918, train1[i % 12]); |
1195 | nv_wr32(pfb, 0x10f920, 0x00000100 | train0[i % 12]); |
1196 | nv_wr32(pfb, 0x10f918, train1[i % 12]); |
1197 | |
1198 | nv_wr32(pfb, 0x10f96c, 0x00000000 | (i << 8)); |
1199 | nv_wr32(pfb, 0x10f924, 0x00000000 | train0[i % 12]); |
1200 | nv_wr32(pfb, 0x10f91c, train1[i % 12]); |
1201 | nv_wr32(pfb, 0x10f924, 0x00000100 | train0[i % 12]); |
1202 | nv_wr32(pfb, 0x10f91c, train1[i % 12]); |
1203 | } |
1204 | |
1205 | for (i = 0; i < 0x100; i++) { |
1206 | nv_wr32(pfb, 0x10f968, i); |
1207 | nv_wr32(pfb, 0x10f900, train1[2 + (i & 1)]); |
1208 | } |
1209 | |
1210 | for (i = 0; i < 0x100; i++) { |
1211 | nv_wr32(pfb, 0x10f96c, i); |
1212 | nv_wr32(pfb, 0x10f900, train1[2 + (i & 1)]); |
1213 | } |
1214 | break; |
1215 | default: |
1216 | break; |
1217 | } |
1218 | |
1219 | return 0; |
1220 | } |
1221 | |
1222 | static int |
1223 | nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
1224 | struct nouveau_oclass *oclass, void *data, u32 size, |
1225 | struct nouveau_object **pobject) |
1226 | { |
1227 | struct nouveau_fb *pfb = nouveau_fb(parent); |
1228 | struct nouveau_bios *bios = nouveau_bios(pfb); |
1229 | struct nouveau_gpio *gpio = nouveau_gpio(pfb); |
1230 | struct dcb_gpio_func func; |
1231 | struct nve0_ram *ram; |
1232 | int ret, i; |
1233 | u32 tmp; |
1234 | |
1235 | ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram); |
1236 | *pobject = nv_object(ram); |
1237 | if (ret) |
1238 | return ret; |
1239 | |
1240 | switch (ram->base.type) { |
1241 | case NV_MEM_TYPE_DDR3: |
1242 | case NV_MEM_TYPE_GDDR5: |
1243 | ram->base.calc = nve0_ram_calc; |
1244 | ram->base.prog = nve0_ram_prog; |
1245 | ram->base.tidy = nve0_ram_tidy; |
1246 | break; |
1247 | default: |
1248 | nv_warn(pfb, "reclocking of this RAM type is unsupported\n" ); |
1249 | break; |
1250 | } |
1251 | |
1252 | /* calculate a mask of differently configured memory partitions, |
1253 | * because, of course reclocking wasn't complicated enough |
1254 | * already without having to treat some of them differently to |
1255 | * the others.... |
1256 | */ |
1257 | ram->parts = nv_rd32(pfb, 0x022438); |
1258 | ram->pmask = nv_rd32(pfb, 0x022554); |
1259 | ram->pnuts = 0; |
1260 | for (i = 0, tmp = 0; i < ram->parts; i++) { |
1261 | if (!(ram->pmask & (1 << i))) { |
1262 | u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000)); |
1263 | if (tmp && tmp != cfg1) { |
1264 | ram->pnuts |= (1 << i); |
1265 | continue; |
1266 | } |
1267 | tmp = cfg1; |
1268 | } |
1269 | } |
1270 | |
1271 | // parse bios data for both pll's |
1272 | ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll); |
1273 | if (ret) { |
1274 | nv_error(pfb, "mclk refpll data not found\n" ); |
1275 | return ret; |
1276 | } |
1277 | |
1278 | ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll); |
1279 | if (ret) { |
1280 | nv_error(pfb, "mclk pll data not found\n" ); |
1281 | return ret; |
1282 | } |
1283 | |
1284 | ret = gpio->find(gpio, 0, 0x18, DCB_GPIO_UNUSED, &func); |
1285 | if (ret == 0) { |
1286 | ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (func.line * 0x04)); |
1287 | ram->fuc.r_funcMV[0] = (func.log[0] ^ 2) << 12; |
1288 | ram->fuc.r_funcMV[1] = (func.log[1] ^ 2) << 12; |
1289 | } |
1290 | |
1291 | ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func); |
1292 | if (ret == 0) { |
1293 | ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (func.line * 0x04)); |
1294 | ram->fuc.r_func2E[0] = (func.log[0] ^ 2) << 12; |
1295 | ram->fuc.r_func2E[1] = (func.log[1] ^ 2) << 12; |
1296 | } |
1297 | |
1298 | ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604); |
1299 | |
1300 | ram->fuc.r_0x132020 = ramfuc_reg(0x132020); |
1301 | ram->fuc.r_0x132028 = ramfuc_reg(0x132028); |
1302 | ram->fuc.r_0x132024 = ramfuc_reg(0x132024); |
1303 | ram->fuc.r_0x132030 = ramfuc_reg(0x132030); |
1304 | ram->fuc.r_0x132034 = ramfuc_reg(0x132034); |
1305 | ram->fuc.r_0x132000 = ramfuc_reg(0x132000); |
1306 | ram->fuc.r_0x132004 = ramfuc_reg(0x132004); |
1307 | ram->fuc.r_0x132040 = ramfuc_reg(0x132040); |
1308 | |
1309 | ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248); |
1310 | ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290); |
1311 | ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294); |
1312 | ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298); |
1313 | ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c); |
1314 | ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0); |
1315 | ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4); |
1316 | ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8); |
1317 | ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac); |
1318 | ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc); |
1319 | ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8); |
1320 | ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250); |
1321 | ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c); |
1322 | ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4); |
1323 | ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8); |
1324 | ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604); |
1325 | ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614); |
1326 | ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610); |
1327 | ram->fuc.r_0x100770 = ramfuc_reg(0x100770); |
1328 | ram->fuc.r_0x100778 = ramfuc_reg(0x100778); |
1329 | ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224); |
1330 | |
1331 | ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870); |
1332 | ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698); |
1333 | ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694); |
1334 | ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8); |
1335 | ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808); |
1336 | ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670); |
1337 | ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c); |
1338 | ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830); |
1339 | ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec); |
1340 | ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800); |
1341 | ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c); |
1342 | |
1343 | ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978); |
1344 | ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910); |
1345 | ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914); |
1346 | |
1347 | switch (ram->base.type) { |
1348 | case NV_MEM_TYPE_GDDR5: |
1349 | ram->fuc.r_mr[0] = ramfuc_reg(0x10f300); |
1350 | ram->fuc.r_mr[1] = ramfuc_reg(0x10f330); |
1351 | ram->fuc.r_mr[2] = ramfuc_reg(0x10f334); |
1352 | ram->fuc.r_mr[3] = ramfuc_reg(0x10f338); |
1353 | ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c); |
1354 | ram->fuc.r_mr[5] = ramfuc_reg(0x10f340); |
1355 | ram->fuc.r_mr[6] = ramfuc_reg(0x10f344); |
1356 | ram->fuc.r_mr[7] = ramfuc_reg(0x10f348); |
1357 | ram->fuc.r_mr[8] = ramfuc_reg(0x10f354); |
1358 | ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c); |
1359 | break; |
1360 | case NV_MEM_TYPE_DDR3: |
1361 | ram->fuc.r_mr[0] = ramfuc_reg(0x10f300); |
1362 | ram->fuc.r_mr[2] = ramfuc_reg(0x10f320); |
1363 | break; |
1364 | default: |
1365 | break; |
1366 | } |
1367 | |
1368 | ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000); |
1369 | ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200); |
1370 | ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210); |
1371 | ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310); |
1372 | ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314); |
1373 | ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318); |
1374 | ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090); |
1375 | ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c); |
1376 | ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824); |
1377 | ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0); |
1378 | ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4); |
1379 | ram->fuc.r_0x137320 = ramfuc_reg(0x137320); |
1380 | ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c); |
1381 | ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc); |
1382 | ram->fuc.r_0x100710 = ramfuc_reg(0x100710); |
1383 | ram->fuc.r_0x100750 = ramfuc_reg(0x100750); |
1384 | return 0; |
1385 | } |
1386 | |
1387 | struct nouveau_oclass |
1388 | nve0_ram_oclass = { |
1389 | .handle = 0, |
1390 | .ofuncs = &(struct nouveau_ofuncs) { |
1391 | .ctor = nve0_ram_ctor, |
1392 | .dtor = _nouveau_ram_dtor, |
1393 | .init = nve0_ram_init, |
1394 | .fini = _nouveau_ram_fini, |
1395 | } |
1396 | }; |
1397 | |