1 | /* $NetBSD: nouveau_engine_device_nv30.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_device_nv30.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $" ); |
29 | |
30 | #include <subdev/bios.h> |
31 | #include <subdev/bus.h> |
32 | #include <subdev/gpio.h> |
33 | #include <subdev/i2c.h> |
34 | #include <subdev/clock.h> |
35 | #include <subdev/devinit.h> |
36 | #include <subdev/mc.h> |
37 | #include <subdev/timer.h> |
38 | #include <subdev/fb.h> |
39 | #include <subdev/instmem.h> |
40 | #include <subdev/vm.h> |
41 | |
42 | #include <engine/device.h> |
43 | #include <engine/dmaobj.h> |
44 | #include <engine/fifo.h> |
45 | #include <engine/software.h> |
46 | #include <engine/graph.h> |
47 | #include <engine/mpeg.h> |
48 | #include <engine/disp.h> |
49 | |
50 | int |
51 | nv30_identify(struct nouveau_device *device) |
52 | { |
53 | switch (device->chipset) { |
54 | case 0x30: |
55 | device->cname = "NV30" ; |
56 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
57 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
58 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
59 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
60 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
61 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
62 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
63 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
64 | device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; |
65 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
66 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
67 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
68 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
69 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
70 | device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; |
71 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
72 | break; |
73 | case 0x35: |
74 | device->cname = "NV35" ; |
75 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
76 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
77 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
78 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
79 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
80 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
81 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
82 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
83 | device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; |
84 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
85 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
86 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
87 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
88 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
89 | device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; |
90 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
91 | break; |
92 | case 0x31: |
93 | device->cname = "NV31" ; |
94 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
95 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
96 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
97 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
98 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
99 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
100 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
101 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
102 | device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; |
103 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
104 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
105 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
106 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
107 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
108 | device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; |
109 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; |
110 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
111 | break; |
112 | case 0x36: |
113 | device->cname = "NV36" ; |
114 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
115 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
116 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
117 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
118 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
119 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
120 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
121 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
122 | device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; |
123 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
124 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
125 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
126 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
127 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
128 | device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; |
129 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; |
130 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
131 | break; |
132 | case 0x34: |
133 | device->cname = "NV34" ; |
134 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
135 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
136 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
137 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
138 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
139 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
140 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
141 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
142 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
143 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
144 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
145 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
146 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
147 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
148 | device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass; |
149 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; |
150 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
151 | break; |
152 | default: |
153 | nv_fatal(device, "unknown Rankine chipset\n" ); |
154 | return -EINVAL; |
155 | } |
156 | |
157 | return 0; |
158 | } |
159 | |