1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <asm/io.h>
31#include <linux/irqflags.h>
32#include "i915_drv.h"
33
34static const char *yesno(int v)
35{
36 return v ? "yes" : "no";
37}
38
39static const char *ring_str(int ring)
40{
41 switch (ring) {
42 case RCS: return "render";
43 case VCS: return "bsd";
44 case BCS: return "blt";
45 case VECS: return "vebox";
46 default: return "";
47 }
48}
49
50static const char *pin_flag(int pinned)
51{
52 if (pinned > 0)
53 return " P";
54 else if (pinned < 0)
55 return " p";
56 else
57 return "";
58}
59
60static const char *tiling_flag(int tiling)
61{
62 switch (tiling) {
63 default:
64 case I915_TILING_NONE: return "";
65 case I915_TILING_X: return " X";
66 case I915_TILING_Y: return " Y";
67 }
68}
69
70static const char *dirty_flag(int dirty)
71{
72 return dirty ? " dirty" : "";
73}
74
75static const char *purgeable_flag(int purgeable)
76{
77 return purgeable ? " purgeable" : "";
78}
79
80static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
81{
82
83 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
84 e->err = -ENOSPC;
85 return false;
86 }
87
88 if (e->bytes == e->size - 1 || e->err)
89 return false;
90
91 return true;
92}
93
94static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
95 unsigned len)
96{
97 if (e->pos + len <= e->start) {
98 e->pos += len;
99 return false;
100 }
101
102 /* First vsnprintf needs to fit in its entirety for memmove */
103 if (len >= e->size) {
104 e->err = -EIO;
105 return false;
106 }
107
108 return true;
109}
110
111static void __i915_error_advance(struct drm_i915_error_state_buf *e,
112 unsigned len)
113{
114 /* If this is first printf in this window, adjust it so that
115 * start position matches start of the buffer
116 */
117
118 if (e->pos < e->start) {
119 const size_t off = e->start - e->pos;
120
121 /* Should not happen but be paranoid */
122 if (off > len || e->bytes) {
123 e->err = -EIO;
124 return;
125 }
126
127 memmove(e->buf, e->buf + off, len - off);
128 e->bytes = len - off;
129 e->pos = e->start;
130 return;
131 }
132
133 e->bytes += len;
134 e->pos += len;
135}
136
137static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
138 const char *f, va_list args)
139{
140 unsigned len;
141
142 if (!__i915_error_ok(e))
143 return;
144
145 /* Seek the first printf which is hits start position */
146 if (e->pos < e->start) {
147 va_list tmp;
148
149 va_copy(tmp, args);
150 len = vsnprintf(NULL, 0, f, tmp);
151 va_end(tmp);
152
153 if (!__i915_error_seek(e, len))
154 return;
155 }
156
157 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
158 if (len >= e->size - e->bytes)
159 len = e->size - e->bytes - 1;
160
161 __i915_error_advance(e, len);
162}
163
164static void i915_error_puts(struct drm_i915_error_state_buf *e,
165 const char *str)
166{
167 unsigned len;
168
169 if (!__i915_error_ok(e))
170 return;
171
172 len = strlen(str);
173
174 /* Seek the first printf which is hits start position */
175 if (e->pos < e->start) {
176 if (!__i915_error_seek(e, len))
177 return;
178 }
179
180 if (len >= e->size - e->bytes)
181 len = e->size - e->bytes - 1;
182 memcpy(e->buf + e->bytes, str, len);
183
184 __i915_error_advance(e, len);
185}
186
187#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
188#define err_puts(e, s) i915_error_puts(e, s)
189
190static void print_error_buffers(struct drm_i915_error_state_buf *m,
191 const char *name,
192 struct drm_i915_error_buffer *err,
193 int count)
194{
195 err_printf(m, "%s [%d]:\n", name, count);
196
197 while (count--) {
198 err_printf(m, " %08x %8u %02x %02x %x %x",
199 err->gtt_offset,
200 err->size,
201 err->read_domains,
202 err->write_domain,
203 err->rseqno, err->wseqno);
204 err_puts(m, pin_flag(err->pinned));
205 err_puts(m, tiling_flag(err->tiling));
206 err_puts(m, dirty_flag(err->dirty));
207 err_puts(m, purgeable_flag(err->purgeable));
208 err_puts(m, err->ring != -1 ? " " : "");
209 err_puts(m, ring_str(err->ring));
210 err_puts(m, i915_cache_level_str(err->cache_level));
211
212 if (err->name)
213 err_printf(m, " (name: %d)", err->name);
214 if (err->fence_reg != I915_FENCE_REG_NONE)
215 err_printf(m, " (fence: %d)", err->fence_reg);
216
217 err_puts(m, "\n");
218 err++;
219 }
220}
221
222static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
223{
224 switch (a) {
225 case HANGCHECK_IDLE:
226 return "idle";
227 case HANGCHECK_WAIT:
228 return "wait";
229 case HANGCHECK_ACTIVE:
230 return "active";
231 case HANGCHECK_KICK:
232 return "kick";
233 case HANGCHECK_HUNG:
234 return "hung";
235 }
236
237 return "unknown";
238}
239
240static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
241 struct drm_device *dev,
242 struct drm_i915_error_ring *ring)
243{
244 if (!ring->valid)
245 return;
246
247 err_printf(m, " HEAD: 0x%08x\n", ring->head);
248 err_printf(m, " TAIL: 0x%08x\n", ring->tail);
249 err_printf(m, " CTL: 0x%08x\n", ring->ctl);
250 err_printf(m, " HWS: 0x%08x\n", ring->hws);
251 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
252 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
253 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
254 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
255 if (INTEL_INFO(dev)->gen >= 4) {
256 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
257 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
258 err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
259 }
260 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
261 err_printf(m, " FADDR: 0x%08x\n", ring->faddr);
262 if (INTEL_INFO(dev)->gen >= 6) {
263 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
264 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
265 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
266 ring->semaphore_mboxes[0],
267 ring->semaphore_seqno[0]);
268 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
269 ring->semaphore_mboxes[1],
270 ring->semaphore_seqno[1]);
271 if (HAS_VEBOX(dev)) {
272 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
273 ring->semaphore_mboxes[2],
274 ring->semaphore_seqno[2]);
275 }
276 }
277 if (USES_PPGTT(dev)) {
278 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
279
280 if (INTEL_INFO(dev)->gen >= 8) {
281 int i;
282 for (i = 0; i < 4; i++)
283 err_printf(m, " PDP%d: 0x%016"PRIx64"\n",
284 i, ring->vm_info.pdp[i]);
285 } else {
286 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
287 ring->vm_info.pp_dir_base);
288 }
289 }
290 err_printf(m, " seqno: 0x%08x\n", ring->seqno);
291 err_printf(m, " waiting: %s\n", yesno(ring->waiting));
292 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
293 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
294 err_printf(m, " hangcheck: %s [%d]\n",
295 hangcheck_action_to_str(ring->hangcheck_action),
296 ring->hangcheck_score);
297}
298
299void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
300{
301 va_list args;
302
303 va_start(args, f);
304 i915_error_vprintf(e, f, args);
305 va_end(args);
306}
307
308static void print_error_obj(struct drm_i915_error_state_buf *m,
309 struct drm_i915_error_object *obj)
310{
311 int page, offset, elt;
312
313 for (page = offset = 0; page < obj->page_count; page++) {
314 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
315 err_printf(m, "%08x : %08x\n", offset,
316 obj->pages[page][elt]);
317 offset += 4;
318 }
319 }
320}
321
322int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
323 const struct i915_error_state_file_priv *error_priv)
324{
325 struct drm_device *dev = error_priv->dev;
326 struct drm_i915_private *dev_priv = dev->dev_private;
327 struct drm_i915_error_state *error = error_priv->error;
328 int i, j, offset, elt;
329 int max_hangcheck_score;
330
331 if (!error) {
332 err_printf(m, "no error state collected\n");
333 goto out;
334 }
335
336 err_printf(m, "%s\n", error->error_msg);
337 err_printf(m, "Time: %"PRIdMAX" s %ld us\n", (intmax_t)error->time.tv_sec,
338 (long)error->time.tv_usec);
339#ifndef __NetBSD__ /* XXX kernel version */
340 err_printf(m, "Kernel: " UTS_RELEASE "\n");
341#endif
342 max_hangcheck_score = 0;
343 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
344 if (error->ring[i].hangcheck_score > max_hangcheck_score)
345 max_hangcheck_score = error->ring[i].hangcheck_score;
346 }
347 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
348 if (error->ring[i].hangcheck_score == max_hangcheck_score &&
349 error->ring[i].pid != -1) {
350 err_printf(m, "Active process (on ring %s): %s [%d]\n",
351 ring_str(i),
352 error->ring[i].comm,
353 error->ring[i].pid);
354 }
355 }
356 err_printf(m, "Reset count: %u\n", error->reset_count);
357 err_printf(m, "Suspend count: %u\n", error->suspend_count);
358 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
359 err_printf(m, "EIR: 0x%08x\n", error->eir);
360 err_printf(m, "IER: 0x%08x\n", error->ier);
361 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
362 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
363 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
364 err_printf(m, "CCID: 0x%08x\n", error->ccid);
365 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
366
367 for (i = 0; i < dev_priv->num_fence_regs; i++)
368 err_printf(m, " fence[%d] = %08"PRIx64"\n", i, error->fence[i]);
369
370 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
371 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
372 error->extra_instdone[i]);
373
374 if (INTEL_INFO(dev)->gen >= 6) {
375 err_printf(m, "ERROR: 0x%08x\n", error->error);
376 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
377 }
378
379 if (INTEL_INFO(dev)->gen == 7)
380 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
381
382 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
383 err_printf(m, "%s command stream:\n", ring_str(i));
384 i915_ring_error_state(m, dev, &error->ring[i]);
385 }
386
387 if (error->active_bo)
388 print_error_buffers(m, "Active",
389 error->active_bo[0],
390 error->active_bo_count[0]);
391
392 if (error->pinned_bo)
393 print_error_buffers(m, "Pinned",
394 error->pinned_bo[0],
395 error->pinned_bo_count[0]);
396
397 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
398 struct drm_i915_error_object *obj;
399
400 obj = error->ring[i].batchbuffer;
401 if (obj) {
402 err_puts(m, dev_priv->ring[i].name);
403 if (error->ring[i].pid != -1)
404 err_printf(m, " (submitted by %s [%d])",
405 error->ring[i].comm,
406 error->ring[i].pid);
407 err_printf(m, " --- gtt_offset = 0x%08x\n",
408 obj->gtt_offset);
409 print_error_obj(m, obj);
410 }
411
412 obj = error->ring[i].wa_batchbuffer;
413 if (obj) {
414 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
415 dev_priv->ring[i].name, obj->gtt_offset);
416 print_error_obj(m, obj);
417 }
418
419 if (error->ring[i].num_requests) {
420 err_printf(m, "%s --- %d requests\n",
421 dev_priv->ring[i].name,
422 error->ring[i].num_requests);
423 for (j = 0; j < error->ring[i].num_requests; j++) {
424 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
425 error->ring[i].requests[j].seqno,
426 error->ring[i].requests[j].jiffies,
427 error->ring[i].requests[j].tail);
428 }
429 }
430
431 if ((obj = error->ring[i].ringbuffer)) {
432 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
433 dev_priv->ring[i].name,
434 obj->gtt_offset);
435 print_error_obj(m, obj);
436 }
437
438 if ((obj = error->ring[i].hws_page)) {
439 err_printf(m, "%s --- HW Status = 0x%08x\n",
440 dev_priv->ring[i].name,
441 obj->gtt_offset);
442 offset = 0;
443 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
444 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
445 offset,
446 obj->pages[0][elt],
447 obj->pages[0][elt+1],
448 obj->pages[0][elt+2],
449 obj->pages[0][elt+3]);
450 offset += 16;
451 }
452 }
453
454 if ((obj = error->ring[i].ctx)) {
455 err_printf(m, "%s --- HW Context = 0x%08x\n",
456 dev_priv->ring[i].name,
457 obj->gtt_offset);
458 offset = 0;
459 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
460 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
461 offset,
462 obj->pages[0][elt],
463 obj->pages[0][elt+1],
464 obj->pages[0][elt+2],
465 obj->pages[0][elt+3]);
466 offset += 16;
467 }
468 }
469 }
470
471 if (error->overlay)
472 intel_overlay_print_error_state(m, error->overlay);
473
474 if (error->display)
475 intel_display_print_error_state(m, dev, error->display);
476
477out:
478 if (m->bytes == 0 && m->err)
479 return m->err;
480
481 return 0;
482}
483
484int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
485 size_t count, loff_t pos)
486{
487 memset(ebuf, 0, sizeof(*ebuf));
488
489 /* We need to have enough room to store any i915_error_state printf
490 * so that we can move it to start position.
491 */
492 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
493 ebuf->buf = kmalloc(ebuf->size,
494 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
495
496 if (ebuf->buf == NULL) {
497 ebuf->size = PAGE_SIZE;
498 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
499 }
500
501 if (ebuf->buf == NULL) {
502 ebuf->size = 128;
503 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
504 }
505
506 if (ebuf->buf == NULL)
507 return -ENOMEM;
508
509 ebuf->start = pos;
510
511 return 0;
512}
513
514static void i915_error_object_free(struct drm_i915_error_object *obj)
515{
516 int page;
517
518 if (obj == NULL)
519 return;
520
521 for (page = 0; page < obj->page_count; page++)
522 kfree(obj->pages[page]);
523
524 kfree(obj);
525}
526
527static void i915_error_state_free(struct kref *error_ref)
528{
529 struct drm_i915_error_state *error = container_of(error_ref,
530 typeof(*error), ref);
531 int i;
532
533 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
534 i915_error_object_free(error->ring[i].batchbuffer);
535 i915_error_object_free(error->ring[i].ringbuffer);
536 i915_error_object_free(error->ring[i].hws_page);
537 i915_error_object_free(error->ring[i].ctx);
538 kfree(error->ring[i].requests);
539 }
540
541 kfree(error->active_bo);
542 kfree(error->overlay);
543 kfree(error->display);
544 kfree(error);
545}
546
547#ifdef __NetBSD__
548# define __aperture_iomem
549# define __iomem __aperture_iomem
550#endif
551
552static struct drm_i915_error_object *
553i915_error_object_create_sized(struct drm_i915_private *dev_priv,
554 struct drm_i915_gem_object *src,
555 struct i915_address_space *vm,
556 const int num_pages)
557{
558 struct drm_i915_error_object *dst;
559 int i;
560 u32 reloc_offset;
561
562 if (src == NULL || src->pages == NULL)
563 return NULL;
564
565 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
566 if (dst == NULL)
567 return NULL;
568
569 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm);
570 for (i = 0; i < num_pages; i++) {
571 unsigned long flags;
572 void *d;
573
574 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
575 if (d == NULL)
576 goto unwind;
577
578 local_irq_save(flags);
579 if (src->cache_level == I915_CACHE_NONE &&
580 reloc_offset < dev_priv->gtt.mappable_end &&
581 src->has_global_gtt_mapping &&
582 i915_is_ggtt(vm)) {
583 void __iomem *s;
584
585 /* Simply ignore tiling or any overlapping fence.
586 * It's part of the error state, and this hopefully
587 * captures what the GPU read.
588 */
589
590 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
591 reloc_offset);
592 memcpy_fromio(d, s, PAGE_SIZE);
593#ifdef __NetBSD__
594 io_mapping_unmap_atomic(dev_priv->gtt.mappable, s);
595#else
596 io_mapping_unmap_atomic(s);
597#endif
598 } else if (src->stolen) {
599 unsigned long offset;
600
601 offset = dev_priv->mm.stolen_base;
602 offset += src->stolen->start;
603 offset += i << PAGE_SHIFT;
604
605 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
606 } else {
607
608 if (cpu_intr_p() || cpu_softintr_p() ||
609 (curlwp->l_pflag & LP_INTR) != 0) {
610 /*
611 * We can't take locks during interrupts
612 * and finding the page from uvm requires
613 * taking a lock. Checking for an interrupt
614 * context is bogus, but this is the least
615 * intrusive change. Zero the result, doesn't
616 * matter much, because this is only used
617 * for diagnostics.
618 */
619 memset(d, 0, PAGE_SIZE);
620 } else {
621 struct page *page;
622 void *s;
623
624 page = i915_gem_object_get_page(src, i);
625
626 drm_clflush_pages(&page, 1);
627
628 s = kmap_atomic(page);
629 memcpy(d, s, PAGE_SIZE);
630 kunmap_atomic(s);
631
632 drm_clflush_pages(&page, 1);
633 }
634 }
635 local_irq_restore(flags);
636
637 dst->pages[i] = d;
638
639 reloc_offset += PAGE_SIZE;
640 }
641 dst->page_count = num_pages;
642
643 return dst;
644
645unwind:
646 while (i--)
647 kfree(dst->pages[i]);
648 kfree(dst);
649 return NULL;
650}
651#define i915_error_object_create(dev_priv, src, vm) \
652 i915_error_object_create_sized((dev_priv), (src), (vm), \
653 (src)->base.size>>PAGE_SHIFT)
654
655#define i915_error_ggtt_object_create(dev_priv, src) \
656 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \
657 (src)->base.size>>PAGE_SHIFT)
658
659#ifdef __NetBSD__
660# undef __iomem
661# undef __aperture_iomem
662#endif
663
664static void capture_bo(struct drm_i915_error_buffer *err,
665 struct drm_i915_gem_object *obj)
666{
667 err->size = obj->base.size;
668 err->name = obj->base.name;
669 err->rseqno = obj->last_read_seqno;
670 err->wseqno = obj->last_write_seqno;
671 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
672 err->read_domains = obj->base.read_domains;
673 err->write_domain = obj->base.write_domain;
674 err->fence_reg = obj->fence_reg;
675 err->pinned = 0;
676 if (i915_gem_obj_is_pinned(obj))
677 err->pinned = 1;
678 if (obj->user_pin_count > 0)
679 err->pinned = -1;
680 err->tiling = obj->tiling_mode;
681 err->dirty = obj->dirty;
682 err->purgeable = obj->madv != I915_MADV_WILLNEED;
683 err->ring = obj->ring ? obj->ring->id : -1;
684 err->cache_level = obj->cache_level;
685}
686
687static u32 capture_active_bo(struct drm_i915_error_buffer *err,
688 int count, struct list_head *head)
689{
690 struct i915_vma *vma;
691 int i = 0;
692
693 list_for_each_entry(vma, head, mm_list) {
694 capture_bo(err++, vma->obj);
695 if (++i == count)
696 break;
697 }
698
699 return i;
700}
701
702static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
703 int count, struct list_head *head)
704{
705 struct drm_i915_gem_object *obj;
706 int i = 0;
707
708 list_for_each_entry(obj, head, global_list) {
709 if (!i915_gem_obj_is_pinned(obj))
710 continue;
711
712 capture_bo(err++, obj);
713 if (++i == count)
714 break;
715 }
716
717 return i;
718}
719
720/* Generate a semi-unique error code. The code is not meant to have meaning, The
721 * code's only purpose is to try to prevent false duplicated bug reports by
722 * grossly estimating a GPU error state.
723 *
724 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
725 * the hang if we could strip the GTT offset information from it.
726 *
727 * It's only a small step better than a random number in its current form.
728 */
729static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
730 struct drm_i915_error_state *error,
731 int *ring_id)
732{
733 uint32_t error_code = 0;
734 int i;
735
736 /* IPEHR would be an ideal way to detect errors, as it's the gross
737 * measure of "the command that hung." However, has some very common
738 * synchronization commands which almost always appear in the case
739 * strictly a client bug. Use instdone to differentiate those some.
740 */
741 for (i = 0; i < I915_NUM_RINGS; i++) {
742 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
743 if (ring_id)
744 *ring_id = i;
745
746 return error->ring[i].ipehr ^ error->ring[i].instdone;
747 }
748 }
749
750 return error_code;
751}
752
753static void i915_gem_record_fences(struct drm_device *dev,
754 struct drm_i915_error_state *error)
755{
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 int i;
758
759 /* Fences */
760 switch (INTEL_INFO(dev)->gen) {
761 case 8:
762 case 7:
763 case 6:
764 for (i = 0; i < dev_priv->num_fence_regs; i++)
765 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
766 break;
767 case 5:
768 case 4:
769 for (i = 0; i < 16; i++)
770 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
771 break;
772 case 3:
773 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
774 for (i = 0; i < 8; i++)
775 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
776 case 2:
777 for (i = 0; i < 8; i++)
778 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
779 break;
780
781 default:
782 BUG();
783 }
784}
785
786static void i915_record_ring_state(struct drm_device *dev,
787 struct intel_ring_buffer *ring,
788 struct drm_i915_error_ring *ering)
789{
790 struct drm_i915_private *dev_priv = dev->dev_private;
791
792 if (INTEL_INFO(dev)->gen >= 6) {
793 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
794 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
795 ering->semaphore_mboxes[0]
796 = I915_READ(RING_SYNC_0(ring->mmio_base));
797 ering->semaphore_mboxes[1]
798 = I915_READ(RING_SYNC_1(ring->mmio_base));
799 ering->semaphore_seqno[0] = ring->sync_seqno[0];
800 ering->semaphore_seqno[1] = ring->sync_seqno[1];
801 }
802
803 if (HAS_VEBOX(dev)) {
804 ering->semaphore_mboxes[2] =
805 I915_READ(RING_SYNC_2(ring->mmio_base));
806 ering->semaphore_seqno[2] = ring->sync_seqno[2];
807 }
808
809 if (INTEL_INFO(dev)->gen >= 4) {
810 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
811 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
812 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
813 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
814 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
815 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
816 if (INTEL_INFO(dev)->gen >= 8)
817 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
818 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
819 } else {
820 ering->faddr = I915_READ(DMA_FADD_I8XX);
821 ering->ipeir = I915_READ(IPEIR);
822 ering->ipehr = I915_READ(IPEHR);
823 ering->instdone = I915_READ(INSTDONE);
824 }
825
826#ifdef __NetBSD__
827 ering->waiting = DRM_SPIN_WAITERS_P(&ring->irq_queue,
828 &dev_priv->irq_lock);
829#else
830 ering->waiting = waitqueue_active(&ring->irq_queue);
831#endif
832 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
833 ering->seqno = ring->get_seqno(ring, false);
834 ering->acthd = intel_ring_get_active_head(ring);
835 ering->head = I915_READ_HEAD(ring);
836 ering->tail = I915_READ_TAIL(ring);
837 ering->ctl = I915_READ_CTL(ring);
838
839 if (I915_NEED_GFX_HWS(dev)) {
840 int mmio;
841
842 if (IS_GEN7(dev)) {
843 switch (ring->id) {
844 default:
845 case RCS:
846 mmio = RENDER_HWS_PGA_GEN7;
847 break;
848 case BCS:
849 mmio = BLT_HWS_PGA_GEN7;
850 break;
851 case VCS:
852 mmio = BSD_HWS_PGA_GEN7;
853 break;
854 case VECS:
855 mmio = VEBOX_HWS_PGA_GEN7;
856 break;
857 }
858 } else if (IS_GEN6(ring->dev)) {
859 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
860 } else {
861 /* XXX: gen8 returns to sanity */
862 mmio = RING_HWS_PGA(ring->mmio_base);
863 }
864
865 ering->hws = I915_READ(mmio);
866 }
867
868 ering->cpu_ring_head = ring->head;
869 ering->cpu_ring_tail = ring->tail;
870
871 ering->hangcheck_score = ring->hangcheck.score;
872 ering->hangcheck_action = ring->hangcheck.action;
873
874 if (USES_PPGTT(dev)) {
875 int i;
876
877 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
878
879 switch (INTEL_INFO(dev)->gen) {
880 case 8:
881 for (i = 0; i < 4; i++) {
882 ering->vm_info.pdp[i] =
883 I915_READ(GEN8_RING_PDP_UDW(ring, i));
884 ering->vm_info.pdp[i] <<= 32;
885 ering->vm_info.pdp[i] |=
886 I915_READ(GEN8_RING_PDP_LDW(ring, i));
887 }
888 break;
889 case 7:
890 ering->vm_info.pp_dir_base =
891 I915_READ(RING_PP_DIR_BASE(ring));
892 break;
893 case 6:
894 ering->vm_info.pp_dir_base =
895 I915_READ(RING_PP_DIR_BASE_READ(ring));
896 break;
897 }
898 }
899}
900
901
902static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
903 struct drm_i915_error_state *error,
904 struct drm_i915_error_ring *ering)
905{
906 struct drm_i915_private *dev_priv = ring->dev->dev_private;
907 struct drm_i915_gem_object *obj;
908
909 /* Currently render ring is the only HW context user */
910 if (ring->id != RCS || !error->ccid)
911 return;
912
913 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
914 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
915 ering->ctx = i915_error_object_create_sized(dev_priv,
916 obj,
917 &dev_priv->gtt.base,
918 1);
919 break;
920 }
921 }
922}
923
924static void i915_gem_record_rings(struct drm_device *dev,
925 struct drm_i915_error_state *error)
926{
927 struct drm_i915_private *dev_priv = dev->dev_private;
928 struct drm_i915_gem_request *request;
929 int i, count;
930
931 for (i = 0; i < I915_NUM_RINGS; i++) {
932 struct intel_ring_buffer *ring = &dev_priv->ring[i];
933
934 if (ring->dev == NULL)
935 continue;
936
937 error->ring[i].valid = true;
938
939 i915_record_ring_state(dev, ring, &error->ring[i]);
940
941 error->ring[i].pid = -1;
942 request = i915_gem_find_active_request(ring);
943 if (request) {
944 /* We need to copy these to an anonymous buffer
945 * as the simplest method to avoid being overwritten
946 * by userspace.
947 */
948 error->ring[i].batchbuffer =
949 i915_error_object_create(dev_priv,
950 request->batch_obj,
951 request->ctx ?
952 request->ctx->vm :
953 &dev_priv->gtt.base);
954
955 if (HAS_BROKEN_CS_TLB(dev_priv->dev) &&
956 ring->scratch.obj)
957 error->ring[i].wa_batchbuffer =
958 i915_error_ggtt_object_create(dev_priv,
959 ring->scratch.obj);
960
961#ifndef __NetBSD__ /* XXX not a clue */
962 if (request->file_priv) {
963 struct task_struct *task;
964
965 rcu_read_lock();
966 task = pid_task(request->file_priv->file->pid,
967 PIDTYPE_PID);
968 if (task) {
969 strcpy(error->ring[i].comm, task->comm);
970 error->ring[i].pid = task->pid;
971 }
972 rcu_read_unlock();
973 }
974#endif
975 }
976
977 error->ring[i].ringbuffer =
978 i915_error_ggtt_object_create(dev_priv, ring->obj);
979
980 if (ring->status_page.obj)
981 error->ring[i].hws_page =
982 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
983
984 i915_gem_record_active_context(ring, error, &error->ring[i]);
985
986 count = 0;
987 list_for_each_entry(request, &ring->request_list, list)
988 count++;
989
990 error->ring[i].num_requests = count;
991 error->ring[i].requests =
992 kcalloc(count, sizeof(*error->ring[i].requests),
993 GFP_ATOMIC);
994 if (error->ring[i].requests == NULL) {
995 error->ring[i].num_requests = 0;
996 continue;
997 }
998
999 count = 0;
1000 list_for_each_entry(request, &ring->request_list, list) {
1001 struct drm_i915_error_request *erq;
1002
1003 erq = &error->ring[i].requests[count++];
1004 erq->seqno = request->seqno;
1005 erq->jiffies = request->emitted_jiffies;
1006 erq->tail = request->tail;
1007 }
1008 }
1009}
1010
1011/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
1012 * VM.
1013 */
1014static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1015 struct drm_i915_error_state *error,
1016 struct i915_address_space *vm,
1017 const int ndx)
1018{
1019 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
1020 struct drm_i915_gem_object *obj;
1021 struct i915_vma *vma;
1022 int i;
1023
1024 i = 0;
1025 list_for_each_entry(vma, &vm->active_list, mm_list)
1026 i++;
1027 error->active_bo_count[ndx] = i;
1028 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1029 if (i915_gem_obj_is_pinned(obj))
1030 i++;
1031 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
1032
1033 if (i) {
1034 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
1035 if (active_bo)
1036 pinned_bo = active_bo + error->active_bo_count[ndx];
1037 }
1038
1039 if (active_bo)
1040 error->active_bo_count[ndx] =
1041 capture_active_bo(active_bo,
1042 error->active_bo_count[ndx],
1043 &vm->active_list);
1044
1045 if (pinned_bo)
1046 error->pinned_bo_count[ndx] =
1047 capture_pinned_bo(pinned_bo,
1048 error->pinned_bo_count[ndx],
1049 &dev_priv->mm.bound_list);
1050 error->active_bo[ndx] = active_bo;
1051 error->pinned_bo[ndx] = pinned_bo;
1052}
1053
1054static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1055 struct drm_i915_error_state *error)
1056{
1057 struct i915_address_space *vm;
1058 int cnt = 0, i = 0;
1059
1060 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1061 cnt++;
1062
1063 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1064 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1065 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1066 GFP_ATOMIC);
1067 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1068 GFP_ATOMIC);
1069
1070 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1071 i915_gem_capture_vm(dev_priv, error, vm, i++);
1072}
1073
1074/* Capture all registers which don't fit into another category. */
1075static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1076 struct drm_i915_error_state *error)
1077{
1078 struct drm_device *dev = dev_priv->dev;
1079 int pipe;
1080
1081 /* General organization
1082 * 1. Registers specific to a single generation
1083 * 2. Registers which belong to multiple generations
1084 * 3. Feature specific registers.
1085 * 4. Everything else
1086 * Please try to follow the order.
1087 */
1088
1089 /* 1: Registers specific to a single generation */
1090 if (IS_VALLEYVIEW(dev)) {
1091 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1092 error->forcewake = I915_READ(FORCEWAKE_VLV);
1093 }
1094
1095 if (IS_GEN7(dev))
1096 error->err_int = I915_READ(GEN7_ERR_INT);
1097
1098 if (IS_GEN6(dev)) {
1099 error->forcewake = I915_READ(FORCEWAKE);
1100 error->gab_ctl = I915_READ(GAB_CTL);
1101 error->gfx_mode = I915_READ(GFX_MODE);
1102 }
1103
1104 if (IS_GEN2(dev))
1105 error->ier = I915_READ16(IER);
1106
1107 /* 2: Registers which belong to multiple generations */
1108 if (INTEL_INFO(dev)->gen >= 7)
1109 error->forcewake = I915_READ(FORCEWAKE_MT);
1110
1111 if (INTEL_INFO(dev)->gen >= 6) {
1112 error->derrmr = I915_READ(DERRMR);
1113 error->error = I915_READ(ERROR_GEN6);
1114 error->done_reg = I915_READ(DONE_REG);
1115 }
1116
1117 /* 3: Feature specific registers */
1118 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1119 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1120 error->gac_eco = I915_READ(GAC_ECO_BITS);
1121 }
1122
1123 /* 4: Everything else */
1124 if (HAS_HW_CONTEXTS(dev))
1125 error->ccid = I915_READ(CCID);
1126
1127 if (HAS_PCH_SPLIT(dev))
1128 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1129 else {
1130 error->ier = I915_READ(IER);
1131 for_each_pipe(pipe)
1132 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1133 }
1134
1135 /* 4: Everything else */
1136 error->eir = I915_READ(EIR);
1137 error->pgtbl_er = I915_READ(PGTBL_ER);
1138
1139 i915_get_extra_instdone(dev, error->extra_instdone);
1140}
1141
1142static void i915_error_capture_msg(struct drm_device *dev,
1143 struct drm_i915_error_state *error,
1144 bool wedged,
1145 const char *error_msg)
1146{
1147 struct drm_i915_private *dev_priv = dev->dev_private;
1148 u32 ecode;
1149 int ring_id = -1, len;
1150
1151 ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1152
1153 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1154 "GPU HANG: ecode %d:0x%08x", ring_id, ecode);
1155
1156 if (ring_id != -1 && error->ring[ring_id].pid != -1)
1157 len += scnprintf(error->error_msg + len,
1158 sizeof(error->error_msg) - len,
1159 ", in %s [%d]",
1160 error->ring[ring_id].comm,
1161 error->ring[ring_id].pid);
1162
1163 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1164 ", reason: %s, action: %s",
1165 error_msg,
1166 wedged ? "reset" : "continue");
1167}
1168
1169static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1170 struct drm_i915_error_state *error)
1171{
1172 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1173 error->suspend_count = dev_priv->suspend_count;
1174}
1175
1176/**
1177 * i915_capture_error_state - capture an error record for later analysis
1178 * @dev: drm device
1179 *
1180 * Should be called when an error is detected (either a hang or an error
1181 * interrupt) to capture error state from the time of the error. Fills
1182 * out a structure which becomes available in debugfs for user level tools
1183 * to pick up.
1184 */
1185void i915_capture_error_state(struct drm_device *dev, bool wedged,
1186 const char *error_msg)
1187{
1188 static bool warned;
1189 struct drm_i915_private *dev_priv = dev->dev_private;
1190 struct drm_i915_error_state *error;
1191 unsigned long flags;
1192
1193 /* Account for pipe specific data like PIPE*STAT */
1194 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1195 if (!error) {
1196 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1197 return;
1198 }
1199
1200 kref_init(&error->ref);
1201
1202 i915_capture_gen_state(dev_priv, error);
1203 i915_capture_reg_state(dev_priv, error);
1204 i915_gem_capture_buffers(dev_priv, error);
1205 i915_gem_record_fences(dev, error);
1206 i915_gem_record_rings(dev, error);
1207
1208 do_gettimeofday(&error->time);
1209
1210 error->overlay = intel_overlay_capture_error_state(dev);
1211 error->display = intel_display_capture_error_state(dev);
1212
1213 i915_error_capture_msg(dev, error, wedged, error_msg);
1214 DRM_INFO("%s\n", error->error_msg);
1215
1216 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1217 if (dev_priv->gpu_error.first_error == NULL) {
1218 dev_priv->gpu_error.first_error = error;
1219 error = NULL;
1220 }
1221 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1222
1223 if (error) {
1224 i915_error_state_free(&error->ref);
1225 return;
1226 }
1227
1228 if (!warned) {
1229 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1230 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1231 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1232 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1233 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1234 warned = true;
1235 }
1236}
1237
1238void i915_error_state_get(struct drm_device *dev,
1239 struct i915_error_state_file_priv *error_priv)
1240{
1241 struct drm_i915_private *dev_priv = dev->dev_private;
1242 unsigned long flags;
1243
1244 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1245 error_priv->error = dev_priv->gpu_error.first_error;
1246 if (error_priv->error)
1247 kref_get(&error_priv->error->ref);
1248 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1249
1250}
1251
1252void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1253{
1254 if (error_priv->error)
1255 kref_put(&error_priv->error->ref, i915_error_state_free);
1256}
1257
1258void i915_destroy_error_state(struct drm_device *dev)
1259{
1260 struct drm_i915_private *dev_priv = dev->dev_private;
1261 struct drm_i915_error_state *error;
1262 unsigned long flags;
1263
1264 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1265 error = dev_priv->gpu_error.first_error;
1266 dev_priv->gpu_error.first_error = NULL;
1267 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1268
1269 if (error)
1270 kref_put(&error->ref, i915_error_state_free);
1271}
1272
1273const char *i915_cache_level_str(int type)
1274{
1275 switch (type) {
1276 case I915_CACHE_NONE: return " uncached";
1277 case I915_CACHE_LLC: return " snooped or LLC";
1278 case I915_CACHE_L3_LLC: return " L3+LLC";
1279 case I915_CACHE_WT: return " WT";
1280 default: return "";
1281 }
1282}
1283
1284/* NB: please notice the memset */
1285void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1286{
1287 struct drm_i915_private *dev_priv = dev->dev_private;
1288 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1289
1290 switch (INTEL_INFO(dev)->gen) {
1291 case 2:
1292 case 3:
1293 instdone[0] = I915_READ(INSTDONE);
1294 break;
1295 case 4:
1296 case 5:
1297 case 6:
1298 instdone[0] = I915_READ(INSTDONE_I965);
1299 instdone[1] = I915_READ(INSTDONE1);
1300 break;
1301 default:
1302 WARN_ONCE(1, "Unsupported platform\n");
1303 case 7:
1304 case 8:
1305 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1306 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1307 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1308 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1309 break;
1310 }
1311}
1312