1 | /* $NetBSD: nouveau_dispnv04_crtc.c,v 1.1.1.1 2014/08/06 12:36:32 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 1993-2003 NVIDIA, Corporation |
5 | * Copyright 2006 Dave Airlie |
6 | * Copyright 2007 Maarten Maathuis |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a |
9 | * copy of this software and associated documentation files (the "Software"), |
10 | * to deal in the Software without restriction, including without limitation |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
12 | * and/or sell copies of the Software, and to permit persons to whom the |
13 | * Software is furnished to do so, subject to the following conditions: |
14 | * |
15 | * The above copyright notice and this permission notice (including the next |
16 | * paragraph) shall be included in all copies or substantial portions of the |
17 | * Software. |
18 | * |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
24 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
25 | * DEALINGS IN THE SOFTWARE. |
26 | */ |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_dispnv04_crtc.c,v 1.1.1.1 2014/08/06 12:36:32 riastradh Exp $" ); |
29 | |
30 | #include <linux/pm_runtime.h> |
31 | |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc_helper.h> |
34 | |
35 | #include "nouveau_drm.h" |
36 | #include "nouveau_reg.h" |
37 | #include "nouveau_bo.h" |
38 | #include "nouveau_gem.h" |
39 | #include "nouveau_encoder.h" |
40 | #include "nouveau_connector.h" |
41 | #include "nouveau_crtc.h" |
42 | #include "hw.h" |
43 | #include "nvreg.h" |
44 | #include "nouveau_fbcon.h" |
45 | #include "disp.h" |
46 | |
47 | #include <subdev/bios/pll.h> |
48 | #include <subdev/clock.h> |
49 | |
50 | static int |
51 | nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
52 | struct drm_framebuffer *old_fb); |
53 | |
54 | static void |
55 | crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) |
56 | { |
57 | NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, |
58 | crtcstate->CRTC[index]); |
59 | } |
60 | |
61 | static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) |
62 | { |
63 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
64 | struct drm_device *dev = crtc->dev; |
65 | struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; |
66 | |
67 | regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; |
68 | if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { |
69 | regp->CRTC[NV_CIO_CRE_CSB] = 0x80; |
70 | regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; |
71 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); |
72 | } |
73 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); |
74 | } |
75 | |
76 | static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) |
77 | { |
78 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
79 | struct drm_device *dev = crtc->dev; |
80 | struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; |
81 | |
82 | nv_crtc->sharpness = level; |
83 | if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ |
84 | level += 0x40; |
85 | regp->ramdac_634 = level; |
86 | NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); |
87 | } |
88 | |
89 | #define PLLSEL_VPLL1_MASK \ |
90 | (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \ |
91 | | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2) |
92 | #define PLLSEL_VPLL2_MASK \ |
93 | (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \ |
94 | | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2) |
95 | #define PLLSEL_TV_MASK \ |
96 | (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \ |
97 | | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \ |
98 | | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \ |
99 | | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2) |
100 | |
101 | /* NV4x 0x40.. pll notes: |
102 | * gpu pll: 0x4000 + 0x4004 |
103 | * ?gpu? pll: 0x4008 + 0x400c |
104 | * vpll1: 0x4010 + 0x4014 |
105 | * vpll2: 0x4018 + 0x401c |
106 | * mpll: 0x4020 + 0x4024 |
107 | * mpll: 0x4038 + 0x403c |
108 | * |
109 | * the first register of each pair has some unknown details: |
110 | * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?) |
111 | * bits 20-23: (mpll) something to do with post divider? |
112 | * bits 28-31: related to single stage mode? (bit 8/12) |
113 | */ |
114 | |
115 | static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock) |
116 | { |
117 | struct drm_device *dev = crtc->dev; |
118 | struct nouveau_drm *drm = nouveau_drm(dev); |
119 | struct nouveau_bios *bios = nouveau_bios(drm->device); |
120 | struct nouveau_clock *clk = nouveau_clock(drm->device); |
121 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
122 | struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; |
123 | struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; |
124 | struct nouveau_pll_vals *pv = ®p->pllvals; |
125 | struct nvbios_pll pll_lim; |
126 | |
127 | if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, |
128 | &pll_lim)) |
129 | return; |
130 | |
131 | /* NM2 == 0 is used to determine single stage mode on two stage plls */ |
132 | pv->NM2 = 0; |
133 | |
134 | /* for newer nv4x the blob uses only the first stage of the vpll below a |
135 | * certain clock. for a certain nv4b this is 150MHz. since the max |
136 | * output frequency of the first stage for this card is 300MHz, it is |
137 | * assumed the threshold is given by vco1 maxfreq/2 |
138 | */ |
139 | /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6, |
140 | * not 8, others unknown), the blob always uses both plls. no problem |
141 | * has yet been observed in allowing the use a single stage pll on all |
142 | * nv43 however. the behaviour of single stage use is untested on nv40 |
143 | */ |
144 | if (nv_device(drm->device)->chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) |
145 | memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); |
146 | |
147 | |
148 | if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv)) |
149 | return; |
150 | |
151 | state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; |
152 | |
153 | /* The blob uses this always, so let's do the same */ |
154 | if (nv_device(drm->device)->card_type == NV_40) |
155 | state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; |
156 | /* again nv40 and some nv43 act more like nv3x as described above */ |
157 | if (nv_device(drm->device)->chipset < 0x41) |
158 | state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | |
159 | NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; |
160 | state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; |
161 | |
162 | if (pv->NM2) |
163 | NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n" , |
164 | pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); |
165 | else |
166 | NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n" , |
167 | pv->N1, pv->M1, pv->log2P); |
168 | |
169 | nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); |
170 | } |
171 | |
172 | static void |
173 | nv_crtc_dpms(struct drm_crtc *crtc, int mode) |
174 | { |
175 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
176 | struct drm_device *dev = crtc->dev; |
177 | struct nouveau_drm *drm = nouveau_drm(dev); |
178 | unsigned char seq1 = 0, crtc17 = 0; |
179 | unsigned char crtc1A; |
180 | |
181 | NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n" , mode, |
182 | nv_crtc->index); |
183 | |
184 | if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ |
185 | return; |
186 | |
187 | nv_crtc->last_dpms = mode; |
188 | |
189 | if (nv_two_heads(dev)) |
190 | NVSetOwner(dev, nv_crtc->index); |
191 | |
192 | /* nv4ref indicates these two RPC1 bits inhibit h/v sync */ |
193 | crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, |
194 | NV_CIO_CRE_RPC1_INDEX) & ~0xC0; |
195 | switch (mode) { |
196 | case DRM_MODE_DPMS_STANDBY: |
197 | /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ |
198 | seq1 = 0x20; |
199 | crtc17 = 0x80; |
200 | crtc1A |= 0x80; |
201 | break; |
202 | case DRM_MODE_DPMS_SUSPEND: |
203 | /* Screen: Off; HSync: On, VSync: Off -- Not Supported */ |
204 | seq1 = 0x20; |
205 | crtc17 = 0x80; |
206 | crtc1A |= 0x40; |
207 | break; |
208 | case DRM_MODE_DPMS_OFF: |
209 | /* Screen: Off; HSync: Off, VSync: Off */ |
210 | seq1 = 0x20; |
211 | crtc17 = 0x00; |
212 | crtc1A |= 0xC0; |
213 | break; |
214 | case DRM_MODE_DPMS_ON: |
215 | default: |
216 | /* Screen: On; HSync: On, VSync: On */ |
217 | seq1 = 0x00; |
218 | crtc17 = 0x80; |
219 | break; |
220 | } |
221 | |
222 | NVVgaSeqReset(dev, nv_crtc->index, true); |
223 | /* Each head has it's own sequencer, so we can turn it off when we want */ |
224 | seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); |
225 | NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); |
226 | crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); |
227 | mdelay(10); |
228 | NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); |
229 | NVVgaSeqReset(dev, nv_crtc->index, false); |
230 | |
231 | NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); |
232 | } |
233 | |
234 | static bool |
235 | nv_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, |
236 | struct drm_display_mode *adjusted_mode) |
237 | { |
238 | return true; |
239 | } |
240 | |
241 | static void |
242 | nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) |
243 | { |
244 | struct drm_device *dev = crtc->dev; |
245 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
246 | struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; |
247 | struct drm_framebuffer *fb = crtc->primary->fb; |
248 | |
249 | /* Calculate our timings */ |
250 | int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; |
251 | int horizStart = (mode->crtc_hsync_start >> 3) + 1; |
252 | int horizEnd = (mode->crtc_hsync_end >> 3) + 1; |
253 | int horizTotal = (mode->crtc_htotal >> 3) - 5; |
254 | int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1; |
255 | int horizBlankEnd = (mode->crtc_htotal >> 3) - 1; |
256 | int vertDisplay = mode->crtc_vdisplay - 1; |
257 | int vertStart = mode->crtc_vsync_start - 1; |
258 | int vertEnd = mode->crtc_vsync_end - 1; |
259 | int vertTotal = mode->crtc_vtotal - 2; |
260 | int vertBlankStart = mode->crtc_vdisplay - 1; |
261 | int vertBlankEnd = mode->crtc_vtotal - 1; |
262 | |
263 | struct drm_encoder *encoder; |
264 | bool fp_output = false; |
265 | |
266 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
267 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
268 | |
269 | if (encoder->crtc == crtc && |
270 | (nv_encoder->dcb->type == DCB_OUTPUT_LVDS || |
271 | nv_encoder->dcb->type == DCB_OUTPUT_TMDS)) |
272 | fp_output = true; |
273 | } |
274 | |
275 | if (fp_output) { |
276 | vertStart = vertTotal - 3; |
277 | vertEnd = vertTotal - 2; |
278 | vertBlankStart = vertStart; |
279 | horizStart = horizTotal - 5; |
280 | horizEnd = horizTotal - 2; |
281 | horizBlankEnd = horizTotal + 4; |
282 | #if 0 |
283 | if (dev->overlayAdaptor && nv_device(drm->device)->card_type >= NV_10) |
284 | /* This reportedly works around some video overlay bandwidth problems */ |
285 | horizTotal += 2; |
286 | #endif |
287 | } |
288 | |
289 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
290 | vertTotal |= 1; |
291 | |
292 | #if 0 |
293 | ErrorF("horizDisplay: 0x%X \n" , horizDisplay); |
294 | ErrorF("horizStart: 0x%X \n" , horizStart); |
295 | ErrorF("horizEnd: 0x%X \n" , horizEnd); |
296 | ErrorF("horizTotal: 0x%X \n" , horizTotal); |
297 | ErrorF("horizBlankStart: 0x%X \n" , horizBlankStart); |
298 | ErrorF("horizBlankEnd: 0x%X \n" , horizBlankEnd); |
299 | ErrorF("vertDisplay: 0x%X \n" , vertDisplay); |
300 | ErrorF("vertStart: 0x%X \n" , vertStart); |
301 | ErrorF("vertEnd: 0x%X \n" , vertEnd); |
302 | ErrorF("vertTotal: 0x%X \n" , vertTotal); |
303 | ErrorF("vertBlankStart: 0x%X \n" , vertBlankStart); |
304 | ErrorF("vertBlankEnd: 0x%X \n" , vertBlankEnd); |
305 | #endif |
306 | |
307 | /* |
308 | * compute correct Hsync & Vsync polarity |
309 | */ |
310 | if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)) |
311 | && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) { |
312 | |
313 | regp->MiscOutReg = 0x23; |
314 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
315 | regp->MiscOutReg |= 0x40; |
316 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
317 | regp->MiscOutReg |= 0x80; |
318 | } else { |
319 | int vdisplay = mode->vdisplay; |
320 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
321 | vdisplay *= 2; |
322 | if (mode->vscan > 1) |
323 | vdisplay *= mode->vscan; |
324 | if (vdisplay < 400) |
325 | regp->MiscOutReg = 0xA3; /* +hsync -vsync */ |
326 | else if (vdisplay < 480) |
327 | regp->MiscOutReg = 0x63; /* -hsync +vsync */ |
328 | else if (vdisplay < 768) |
329 | regp->MiscOutReg = 0xE3; /* -hsync -vsync */ |
330 | else |
331 | regp->MiscOutReg = 0x23; /* +hsync +vsync */ |
332 | } |
333 | |
334 | /* |
335 | * Time Sequencer |
336 | */ |
337 | regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; |
338 | /* 0x20 disables the sequencer */ |
339 | if (mode->flags & DRM_MODE_FLAG_CLKDIV2) |
340 | regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; |
341 | else |
342 | regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; |
343 | regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; |
344 | regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; |
345 | regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; |
346 | |
347 | /* |
348 | * CRTC |
349 | */ |
350 | regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; |
351 | regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; |
352 | regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; |
353 | regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | |
354 | XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0); |
355 | regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; |
356 | regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | |
357 | XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0); |
358 | regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; |
359 | regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | |
360 | XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) | |
361 | XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) | |
362 | (1 << 4) | |
363 | XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) | |
364 | XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) | |
365 | XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) | |
366 | XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8); |
367 | regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; |
368 | regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | |
369 | 1 << 6 | |
370 | XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9); |
371 | regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; |
372 | regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; |
373 | regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; |
374 | regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; |
375 | regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; |
376 | regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; |
377 | regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; |
378 | regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); |
379 | regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; |
380 | /* framebuffer can be larger than crtc scanout area. */ |
381 | regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; |
382 | regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; |
383 | regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; |
384 | regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; |
385 | regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; |
386 | regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; |
387 | |
388 | /* |
389 | * Some extended CRTC registers (they are not saved with the rest of the vga regs). |
390 | */ |
391 | |
392 | /* framebuffer can be larger than crtc scanout area. */ |
393 | regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = |
394 | XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); |
395 | regp->CRTC[NV_CIO_CRE_42] = |
396 | XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); |
397 | regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? |
398 | MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; |
399 | regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | |
400 | XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) | |
401 | XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) | |
402 | XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) | |
403 | XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10); |
404 | regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | |
405 | XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) | |
406 | XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) | |
407 | XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8); |
408 | regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | |
409 | XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) | |
410 | XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) | |
411 | XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11); |
412 | |
413 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
414 | horizTotal = (horizTotal >> 1) & ~1; |
415 | regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; |
416 | regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); |
417 | } else |
418 | regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ |
419 | |
420 | /* |
421 | * Graphics Display Controller |
422 | */ |
423 | regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; |
424 | regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; |
425 | regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; |
426 | regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; |
427 | regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; |
428 | regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ |
429 | regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ |
430 | regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; |
431 | regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; |
432 | |
433 | regp->Attribute[0] = 0x00; /* standard colormap translation */ |
434 | regp->Attribute[1] = 0x01; |
435 | regp->Attribute[2] = 0x02; |
436 | regp->Attribute[3] = 0x03; |
437 | regp->Attribute[4] = 0x04; |
438 | regp->Attribute[5] = 0x05; |
439 | regp->Attribute[6] = 0x06; |
440 | regp->Attribute[7] = 0x07; |
441 | regp->Attribute[8] = 0x08; |
442 | regp->Attribute[9] = 0x09; |
443 | regp->Attribute[10] = 0x0A; |
444 | regp->Attribute[11] = 0x0B; |
445 | regp->Attribute[12] = 0x0C; |
446 | regp->Attribute[13] = 0x0D; |
447 | regp->Attribute[14] = 0x0E; |
448 | regp->Attribute[15] = 0x0F; |
449 | regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ |
450 | /* Non-vga */ |
451 | regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; |
452 | regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ |
453 | regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; |
454 | regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; |
455 | } |
456 | |
457 | /** |
458 | * Sets up registers for the given mode/adjusted_mode pair. |
459 | * |
460 | * The clocks, CRTCs and outputs attached to this CRTC must be off. |
461 | * |
462 | * This shouldn't enable any clocks, CRTCs, or outputs, but they should |
463 | * be easily turned on/off after this. |
464 | */ |
465 | static void |
466 | nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) |
467 | { |
468 | struct drm_device *dev = crtc->dev; |
469 | struct nouveau_drm *drm = nouveau_drm(dev); |
470 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
471 | struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; |
472 | struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; |
473 | struct drm_encoder *encoder; |
474 | bool lvds_output = false, tmds_output = false, tv_output = false, |
475 | off_chip_digital = false; |
476 | |
477 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
478 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
479 | bool digital = false; |
480 | |
481 | if (encoder->crtc != crtc) |
482 | continue; |
483 | |
484 | if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) |
485 | digital = lvds_output = true; |
486 | if (nv_encoder->dcb->type == DCB_OUTPUT_TV) |
487 | tv_output = true; |
488 | if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) |
489 | digital = tmds_output = true; |
490 | if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) |
491 | off_chip_digital = true; |
492 | } |
493 | |
494 | /* Registers not directly related to the (s)vga mode */ |
495 | |
496 | /* What is the meaning of this register? */ |
497 | /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ |
498 | regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); |
499 | |
500 | regp->crtc_eng_ctrl = 0; |
501 | /* Except for rare conditions I2C is enabled on the primary crtc */ |
502 | if (nv_crtc->index == 0) |
503 | regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; |
504 | #if 0 |
505 | /* Set overlay to desired crtc. */ |
506 | if (dev->overlayAdaptor) { |
507 | NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev); |
508 | if (pPriv->overlayCRTC == nv_crtc->index) |
509 | regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY; |
510 | } |
511 | #endif |
512 | |
513 | /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */ |
514 | regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | |
515 | NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | |
516 | NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; |
517 | if (nv_device(drm->device)->chipset >= 0x11) |
518 | regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; |
519 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
520 | regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; |
521 | |
522 | /* Unblock some timings */ |
523 | regp->CRTC[NV_CIO_CRE_53] = 0; |
524 | regp->CRTC[NV_CIO_CRE_54] = 0; |
525 | |
526 | /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ |
527 | if (lvds_output) |
528 | regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; |
529 | else if (tmds_output) |
530 | regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; |
531 | else |
532 | regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; |
533 | |
534 | /* These values seem to vary */ |
535 | /* This register seems to be used by the bios to make certain decisions on some G70 cards? */ |
536 | regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; |
537 | |
538 | nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); |
539 | |
540 | /* probably a scratch reg, but kept for cargo-cult purposes: |
541 | * bit0: crtc0?, head A |
542 | * bit6: lvds, head A |
543 | * bit7: (only in X), head A |
544 | */ |
545 | if (nv_crtc->index == 0) |
546 | regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; |
547 | |
548 | /* The blob seems to take the current value from crtc 0, add 4 to that |
549 | * and reuse the old value for crtc 1 */ |
550 | regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY]; |
551 | if (!nv_crtc->index) |
552 | regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; |
553 | |
554 | /* the blob sometimes sets |= 0x10 (which is the same as setting |= |
555 | * 1 << 30 on 0x60.830), for no apparent reason */ |
556 | regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; |
557 | |
558 | if (nv_device(drm->device)->card_type >= NV_30) |
559 | regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; |
560 | |
561 | regp->crtc_830 = mode->crtc_vdisplay - 3; |
562 | regp->crtc_834 = mode->crtc_vdisplay - 1; |
563 | |
564 | if (nv_device(drm->device)->card_type == NV_40) |
565 | /* This is what the blob does */ |
566 | regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); |
567 | |
568 | if (nv_device(drm->device)->card_type >= NV_30) |
569 | regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); |
570 | |
571 | if (nv_device(drm->device)->card_type >= NV_10) |
572 | regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; |
573 | else |
574 | regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; |
575 | |
576 | /* Some misc regs */ |
577 | if (nv_device(drm->device)->card_type == NV_40) { |
578 | regp->CRTC[NV_CIO_CRE_85] = 0xFF; |
579 | regp->CRTC[NV_CIO_CRE_86] = 0x1; |
580 | } |
581 | |
582 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->primary->fb->depth + 1) / 8; |
583 | /* Enable slaved mode (called MODE_TV in nv4ref.h) */ |
584 | if (lvds_output || tmds_output || tv_output) |
585 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); |
586 | |
587 | /* Generic PRAMDAC regs */ |
588 | |
589 | if (nv_device(drm->device)->card_type >= NV_10) |
590 | /* Only bit that bios and blob set. */ |
591 | regp->nv10_cursync = (1 << 25); |
592 | |
593 | regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | |
594 | NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | |
595 | NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; |
596 | if (crtc->primary->fb->depth == 16) |
597 | regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; |
598 | if (nv_device(drm->device)->chipset >= 0x11) |
599 | regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; |
600 | |
601 | regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ |
602 | regp->tv_setup = 0; |
603 | |
604 | nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); |
605 | |
606 | /* Some values the blob sets */ |
607 | regp->ramdac_8c0 = 0x100; |
608 | regp->ramdac_a20 = 0x0; |
609 | regp->ramdac_a24 = 0xfffff; |
610 | regp->ramdac_a34 = 0x1; |
611 | } |
612 | |
613 | static int |
614 | nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) |
615 | { |
616 | struct nv04_display *disp = nv04_display(crtc->dev); |
617 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); |
618 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
619 | int ret; |
620 | |
621 | ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM); |
622 | if (ret == 0) { |
623 | if (disp->image[nv_crtc->index]) |
624 | nouveau_bo_unpin(disp->image[nv_crtc->index]); |
625 | nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]); |
626 | } |
627 | |
628 | return ret; |
629 | } |
630 | |
631 | /** |
632 | * Sets up registers for the given mode/adjusted_mode pair. |
633 | * |
634 | * The clocks, CRTCs and outputs attached to this CRTC must be off. |
635 | * |
636 | * This shouldn't enable any clocks, CRTCs, or outputs, but they should |
637 | * be easily turned on/off after this. |
638 | */ |
639 | static int |
640 | nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, |
641 | struct drm_display_mode *adjusted_mode, |
642 | int x, int y, struct drm_framebuffer *old_fb) |
643 | { |
644 | struct drm_device *dev = crtc->dev; |
645 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
646 | struct nouveau_drm *drm = nouveau_drm(dev); |
647 | int ret; |
648 | |
649 | NV_DEBUG(drm, "CTRC mode on CRTC %d:\n" , nv_crtc->index); |
650 | drm_mode_debug_printmodeline(adjusted_mode); |
651 | |
652 | ret = nv_crtc_swap_fbs(crtc, old_fb); |
653 | if (ret) |
654 | return ret; |
655 | |
656 | /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ |
657 | nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); |
658 | |
659 | nv_crtc_mode_set_vga(crtc, adjusted_mode); |
660 | /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ |
661 | if (nv_device(drm->device)->card_type == NV_40) |
662 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); |
663 | nv_crtc_mode_set_regs(crtc, adjusted_mode); |
664 | nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); |
665 | return 0; |
666 | } |
667 | |
668 | static void nv_crtc_save(struct drm_crtc *crtc) |
669 | { |
670 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
671 | struct drm_device *dev = crtc->dev; |
672 | struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; |
673 | struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; |
674 | struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg; |
675 | struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; |
676 | |
677 | if (nv_two_heads(crtc->dev)) |
678 | NVSetOwner(crtc->dev, nv_crtc->index); |
679 | |
680 | nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); |
681 | |
682 | /* init some state to saved value */ |
683 | state->sel_clk = saved->sel_clk & ~(0x5 << 16); |
684 | crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; |
685 | state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK); |
686 | crtc_state->gpio_ext = crtc_saved->gpio_ext; |
687 | } |
688 | |
689 | static void nv_crtc_restore(struct drm_crtc *crtc) |
690 | { |
691 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
692 | struct drm_device *dev = crtc->dev; |
693 | int head = nv_crtc->index; |
694 | uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; |
695 | |
696 | if (nv_two_heads(crtc->dev)) |
697 | NVSetOwner(crtc->dev, head); |
698 | |
699 | nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg); |
700 | nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); |
701 | |
702 | nv_crtc->last_dpms = NV_DPMS_CLEARED; |
703 | } |
704 | |
705 | static void nv_crtc_prepare(struct drm_crtc *crtc) |
706 | { |
707 | struct drm_device *dev = crtc->dev; |
708 | struct nouveau_drm *drm = nouveau_drm(dev); |
709 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
710 | struct drm_crtc_helper_funcs *funcs = crtc->helper_private; |
711 | |
712 | if (nv_two_heads(dev)) |
713 | NVSetOwner(dev, nv_crtc->index); |
714 | |
715 | drm_vblank_pre_modeset(dev, nv_crtc->index); |
716 | funcs->dpms(crtc, DRM_MODE_DPMS_OFF); |
717 | |
718 | NVBlankScreen(dev, nv_crtc->index, true); |
719 | |
720 | /* Some more preparation. */ |
721 | NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); |
722 | if (nv_device(drm->device)->card_type == NV_40) { |
723 | uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); |
724 | NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); |
725 | } |
726 | } |
727 | |
728 | static void nv_crtc_commit(struct drm_crtc *crtc) |
729 | { |
730 | struct drm_device *dev = crtc->dev; |
731 | struct drm_crtc_helper_funcs *funcs = crtc->helper_private; |
732 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
733 | |
734 | nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); |
735 | nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); |
736 | |
737 | #ifdef __BIG_ENDIAN |
738 | /* turn on LFB swapping */ |
739 | { |
740 | uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); |
741 | tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); |
742 | NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); |
743 | } |
744 | #endif |
745 | |
746 | funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
747 | drm_vblank_post_modeset(dev, nv_crtc->index); |
748 | } |
749 | |
750 | static void nv_crtc_destroy(struct drm_crtc *crtc) |
751 | { |
752 | struct nv04_display *disp = nv04_display(crtc->dev); |
753 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
754 | |
755 | if (!nv_crtc) |
756 | return; |
757 | |
758 | drm_crtc_cleanup(crtc); |
759 | |
760 | if (disp->image[nv_crtc->index]) |
761 | nouveau_bo_unpin(disp->image[nv_crtc->index]); |
762 | nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); |
763 | |
764 | nouveau_bo_unmap(nv_crtc->cursor.nvbo); |
765 | nouveau_bo_unpin(nv_crtc->cursor.nvbo); |
766 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); |
767 | kfree(nv_crtc); |
768 | } |
769 | |
770 | static void |
771 | nv_crtc_gamma_load(struct drm_crtc *crtc) |
772 | { |
773 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
774 | struct drm_device *dev = nv_crtc->base.dev; |
775 | struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs; |
776 | int i; |
777 | |
778 | rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; |
779 | for (i = 0; i < 256; i++) { |
780 | rgbs[i].r = nv_crtc->lut.r[i] >> 8; |
781 | rgbs[i].g = nv_crtc->lut.g[i] >> 8; |
782 | rgbs[i].b = nv_crtc->lut.b[i] >> 8; |
783 | } |
784 | |
785 | nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); |
786 | } |
787 | |
788 | static void |
789 | nv_crtc_disable(struct drm_crtc *crtc) |
790 | { |
791 | struct nv04_display *disp = nv04_display(crtc->dev); |
792 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
793 | if (disp->image[nv_crtc->index]) |
794 | nouveau_bo_unpin(disp->image[nv_crtc->index]); |
795 | nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); |
796 | } |
797 | |
798 | static void |
799 | nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start, |
800 | uint32_t size) |
801 | { |
802 | int end = (start + size > 256) ? 256 : start + size, i; |
803 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
804 | |
805 | for (i = start; i < end; i++) { |
806 | nv_crtc->lut.r[i] = r[i]; |
807 | nv_crtc->lut.g[i] = g[i]; |
808 | nv_crtc->lut.b[i] = b[i]; |
809 | } |
810 | |
811 | /* We need to know the depth before we upload, but it's possible to |
812 | * get called before a framebuffer is bound. If this is the case, |
813 | * mark the lut values as dirty by setting depth==0, and it'll be |
814 | * uploaded on the first mode_set_base() |
815 | */ |
816 | if (!nv_crtc->base.primary->fb) { |
817 | nv_crtc->lut.depth = 0; |
818 | return; |
819 | } |
820 | |
821 | nv_crtc_gamma_load(crtc); |
822 | } |
823 | |
824 | static int |
825 | nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, |
826 | struct drm_framebuffer *passed_fb, |
827 | int x, int y, bool atomic) |
828 | { |
829 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
830 | struct drm_device *dev = crtc->dev; |
831 | struct nouveau_drm *drm = nouveau_drm(dev); |
832 | struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; |
833 | struct drm_framebuffer *drm_fb; |
834 | struct nouveau_framebuffer *fb; |
835 | int arb_burst, arb_lwm; |
836 | |
837 | NV_DEBUG(drm, "index %d\n" , nv_crtc->index); |
838 | |
839 | /* no fb bound */ |
840 | if (!atomic && !crtc->primary->fb) { |
841 | NV_DEBUG(drm, "No FB bound\n" ); |
842 | return 0; |
843 | } |
844 | |
845 | /* If atomic, we want to switch to the fb we were passed, so |
846 | * now we update pointers to do that. |
847 | */ |
848 | if (atomic) { |
849 | drm_fb = passed_fb; |
850 | fb = nouveau_framebuffer(passed_fb); |
851 | } else { |
852 | drm_fb = crtc->primary->fb; |
853 | fb = nouveau_framebuffer(crtc->primary->fb); |
854 | } |
855 | |
856 | nv_crtc->fb.offset = fb->nvbo->bo.offset; |
857 | |
858 | if (nv_crtc->lut.depth != drm_fb->depth) { |
859 | nv_crtc->lut.depth = drm_fb->depth; |
860 | nv_crtc_gamma_load(crtc); |
861 | } |
862 | |
863 | /* Update the framebuffer format. */ |
864 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; |
865 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->primary->fb->depth + 1) / 8; |
866 | regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; |
867 | if (crtc->primary->fb->depth == 16) |
868 | regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; |
869 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); |
870 | NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, |
871 | regp->ramdac_gen_ctrl); |
872 | |
873 | regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; |
874 | regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = |
875 | XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); |
876 | regp->CRTC[NV_CIO_CRE_42] = |
877 | XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); |
878 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); |
879 | crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); |
880 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); |
881 | |
882 | /* Update the framebuffer location. */ |
883 | regp->fb_start = nv_crtc->fb.offset & ~3; |
884 | regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->bits_per_pixel / 8); |
885 | nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); |
886 | |
887 | /* Update the arbitration parameters. */ |
888 | nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel, |
889 | &arb_burst, &arb_lwm); |
890 | |
891 | regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; |
892 | regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; |
893 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); |
894 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); |
895 | |
896 | if (nv_device(drm->device)->card_type >= NV_20) { |
897 | regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; |
898 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); |
899 | } |
900 | |
901 | return 0; |
902 | } |
903 | |
904 | static int |
905 | nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
906 | struct drm_framebuffer *old_fb) |
907 | { |
908 | int ret = nv_crtc_swap_fbs(crtc, old_fb); |
909 | if (ret) |
910 | return ret; |
911 | return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false); |
912 | } |
913 | |
914 | static int |
915 | nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc, |
916 | struct drm_framebuffer *fb, |
917 | int x, int y, enum mode_set_atomic state) |
918 | { |
919 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); |
920 | struct drm_device *dev = drm->dev; |
921 | |
922 | if (state == ENTER_ATOMIC_MODE_SET) |
923 | nouveau_fbcon_save_disable_accel(dev); |
924 | else |
925 | nouveau_fbcon_restore_accel(dev); |
926 | |
927 | return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true); |
928 | } |
929 | |
930 | static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, |
931 | struct nouveau_bo *dst) |
932 | { |
933 | int width = nv_cursor_width(dev); |
934 | uint32_t pixel; |
935 | int i, j; |
936 | |
937 | for (i = 0; i < width; i++) { |
938 | for (j = 0; j < width; j++) { |
939 | pixel = nouveau_bo_rd32(src, i*64 + j); |
940 | |
941 | nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 |
942 | | (pixel & 0xf80000) >> 9 |
943 | | (pixel & 0xf800) >> 6 |
944 | | (pixel & 0xf8) >> 3); |
945 | } |
946 | } |
947 | } |
948 | |
949 | static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, |
950 | struct nouveau_bo *dst) |
951 | { |
952 | uint32_t pixel; |
953 | int alpha, i; |
954 | |
955 | /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha |
956 | * cursors (though NPM in combination with fp dithering may not work on |
957 | * nv11, from "nv" driver history) |
958 | * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the |
959 | * blob uses, however we get given PM cursors so we use PM mode |
960 | */ |
961 | for (i = 0; i < 64 * 64; i++) { |
962 | pixel = nouveau_bo_rd32(src, i); |
963 | |
964 | /* hw gets unhappy if alpha <= rgb values. for a PM image "less |
965 | * than" shouldn't happen; fix "equal to" case by adding one to |
966 | * alpha channel (slightly inaccurate, but so is attempting to |
967 | * get back to NPM images, due to limits of integer precision) |
968 | */ |
969 | alpha = pixel >> 24; |
970 | if (alpha > 0 && alpha < 255) |
971 | pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); |
972 | |
973 | #ifdef __BIG_ENDIAN |
974 | { |
975 | struct nouveau_drm *drm = nouveau_drm(dev); |
976 | |
977 | if (nv_device(drm->device)->chipset == 0x11) { |
978 | pixel = ((pixel & 0x000000ff) << 24) | |
979 | ((pixel & 0x0000ff00) << 8) | |
980 | ((pixel & 0x00ff0000) >> 8) | |
981 | ((pixel & 0xff000000) >> 24); |
982 | } |
983 | } |
984 | #endif |
985 | |
986 | nouveau_bo_wr32(dst, i, pixel); |
987 | } |
988 | } |
989 | |
990 | static int |
991 | nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, |
992 | uint32_t buffer_handle, uint32_t width, uint32_t height) |
993 | { |
994 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); |
995 | struct drm_device *dev = drm->dev; |
996 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
997 | struct nouveau_bo *cursor = NULL; |
998 | struct drm_gem_object *gem; |
999 | int ret = 0; |
1000 | |
1001 | if (!buffer_handle) { |
1002 | nv_crtc->cursor.hide(nv_crtc, true); |
1003 | return 0; |
1004 | } |
1005 | |
1006 | if (width != 64 || height != 64) |
1007 | return -EINVAL; |
1008 | |
1009 | gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); |
1010 | if (!gem) |
1011 | return -ENOENT; |
1012 | cursor = nouveau_gem_object(gem); |
1013 | |
1014 | ret = nouveau_bo_map(cursor); |
1015 | if (ret) |
1016 | goto out; |
1017 | |
1018 | if (nv_device(drm->device)->chipset >= 0x11) |
1019 | nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); |
1020 | else |
1021 | nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); |
1022 | |
1023 | nouveau_bo_unmap(cursor); |
1024 | nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset; |
1025 | nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); |
1026 | nv_crtc->cursor.show(nv_crtc, true); |
1027 | out: |
1028 | drm_gem_object_unreference_unlocked(gem); |
1029 | return ret; |
1030 | } |
1031 | |
1032 | static int |
1033 | nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
1034 | { |
1035 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1036 | |
1037 | nv_crtc->cursor.set_pos(nv_crtc, x, y); |
1038 | return 0; |
1039 | } |
1040 | |
1041 | int |
1042 | nouveau_crtc_set_config(struct drm_mode_set *set) |
1043 | { |
1044 | struct drm_device *dev; |
1045 | struct nouveau_drm *drm; |
1046 | int ret; |
1047 | struct drm_crtc *crtc; |
1048 | bool active = false; |
1049 | if (!set || !set->crtc) |
1050 | return -EINVAL; |
1051 | |
1052 | dev = set->crtc->dev; |
1053 | |
1054 | /* get a pm reference here */ |
1055 | ret = pm_runtime_get_sync(dev->dev); |
1056 | if (ret < 0 && ret != -EACCES) |
1057 | return ret; |
1058 | |
1059 | ret = drm_crtc_helper_set_config(set); |
1060 | |
1061 | drm = nouveau_drm(dev); |
1062 | |
1063 | /* if we get here with no crtcs active then we can drop a reference */ |
1064 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
1065 | if (crtc->enabled) |
1066 | active = true; |
1067 | } |
1068 | |
1069 | pm_runtime_mark_last_busy(dev->dev); |
1070 | /* if we have active crtcs and we don't have a power ref, |
1071 | take the current one */ |
1072 | if (active && !drm->have_disp_power_ref) { |
1073 | drm->have_disp_power_ref = true; |
1074 | return ret; |
1075 | } |
1076 | /* if we have no active crtcs, then drop the power ref |
1077 | we got before */ |
1078 | if (!active && drm->have_disp_power_ref) { |
1079 | pm_runtime_put_autosuspend(dev->dev); |
1080 | drm->have_disp_power_ref = false; |
1081 | } |
1082 | /* drop the power reference we got coming in here */ |
1083 | pm_runtime_put_autosuspend(dev->dev); |
1084 | return ret; |
1085 | } |
1086 | |
1087 | static const struct drm_crtc_funcs nv04_crtc_funcs = { |
1088 | .save = nv_crtc_save, |
1089 | .restore = nv_crtc_restore, |
1090 | .cursor_set = nv04_crtc_cursor_set, |
1091 | .cursor_move = nv04_crtc_cursor_move, |
1092 | .gamma_set = nv_crtc_gamma_set, |
1093 | .set_config = nouveau_crtc_set_config, |
1094 | .page_flip = nouveau_crtc_page_flip, |
1095 | .destroy = nv_crtc_destroy, |
1096 | }; |
1097 | |
1098 | static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { |
1099 | .dpms = nv_crtc_dpms, |
1100 | .prepare = nv_crtc_prepare, |
1101 | .commit = nv_crtc_commit, |
1102 | .mode_fixup = nv_crtc_mode_fixup, |
1103 | .mode_set = nv_crtc_mode_set, |
1104 | .mode_set_base = nv04_crtc_mode_set_base, |
1105 | .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic, |
1106 | .load_lut = nv_crtc_gamma_load, |
1107 | .disable = nv_crtc_disable, |
1108 | }; |
1109 | |
1110 | int |
1111 | nv04_crtc_create(struct drm_device *dev, int crtc_num) |
1112 | { |
1113 | struct nouveau_crtc *nv_crtc; |
1114 | int ret, i; |
1115 | |
1116 | nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); |
1117 | if (!nv_crtc) |
1118 | return -ENOMEM; |
1119 | |
1120 | for (i = 0; i < 256; i++) { |
1121 | nv_crtc->lut.r[i] = i << 8; |
1122 | nv_crtc->lut.g[i] = i << 8; |
1123 | nv_crtc->lut.b[i] = i << 8; |
1124 | } |
1125 | nv_crtc->lut.depth = 0; |
1126 | |
1127 | nv_crtc->index = crtc_num; |
1128 | nv_crtc->last_dpms = NV_DPMS_CLEARED; |
1129 | |
1130 | drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs); |
1131 | drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); |
1132 | drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); |
1133 | |
1134 | ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM, |
1135 | 0, 0x0000, NULL, &nv_crtc->cursor.nvbo); |
1136 | if (!ret) { |
1137 | ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); |
1138 | if (!ret) { |
1139 | ret = nouveau_bo_map(nv_crtc->cursor.nvbo); |
1140 | if (ret) |
1141 | nouveau_bo_unpin(nv_crtc->cursor.nvbo); |
1142 | } |
1143 | if (ret) |
1144 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); |
1145 | } |
1146 | |
1147 | nv04_cursor_init(nv_crtc); |
1148 | |
1149 | return 0; |
1150 | } |
1151 | |