1/* $NetBSD: pccbb.c,v 1.210 2016/07/07 06:55:41 msaitoh Exp $ */
2
3/*
4 * Copyright (c) 1998, 1999 and 2000
5 * HAYAKAWA Koichi. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.210 2016/07/07 06:55:41 msaitoh Exp $");
30
31/*
32#define CBB_DEBUG
33#define SHOW_REGS
34*/
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/kernel.h>
39#include <sys/errno.h>
40#include <sys/ioctl.h>
41#include <sys/reboot.h> /* for bootverbose */
42#include <sys/syslog.h>
43#include <sys/device.h>
44#include <sys/malloc.h>
45#include <sys/proc.h>
46
47#include <sys/intr.h>
48#include <sys/bus.h>
49
50#include <dev/pci/pcivar.h>
51#include <dev/pci/pcireg.h>
52#include <dev/pci/pcidevs.h>
53
54#include <dev/pci/pccbbreg.h>
55
56#include <dev/cardbus/cardslotvar.h>
57
58#include <dev/cardbus/cardbusvar.h>
59
60#include <dev/pcmcia/pcmciareg.h>
61#include <dev/pcmcia/pcmciavar.h>
62
63#include <dev/ic/i82365reg.h>
64#include <dev/pci/pccbbvar.h>
65
66#ifndef __NetBSD_Version__
67struct cfdriver cbb_cd = {
68 NULL, "cbb", DV_DULL
69};
70#endif
71
72#ifdef CBB_DEBUG
73#define DPRINTF(x) printf x
74#define STATIC
75#else
76#define DPRINTF(x)
77#define STATIC static
78#endif
79
80int pccbb_burstup = 1;
81
82/*
83 * delay_ms() is wait in milliseconds. It should be used instead
84 * of delay() if you want to wait more than 1 ms.
85 */
86static inline void
87delay_ms(int millis, struct pccbb_softc *sc)
88{
89 if (cold)
90 delay(millis * 1000);
91 else
92 kpause("pccbb", false, mstohz(millis), NULL);
93}
94
95int pcicbbmatch(device_t, cfdata_t, void *);
96void pccbbattach(device_t, device_t, void *);
97void pccbbchilddet(device_t, device_t);
98int pccbbdetach(device_t, int);
99int pccbbintr(void *);
100static void pci113x_insert(void *);
101static int pccbbintr_function(struct pccbb_softc *);
102
103static int pccbb_detect_card(struct pccbb_softc *);
104
105static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t);
106static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int);
107#define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg))
108#define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val))
109
110STATIC int cb_reset(struct pccbb_softc *);
111STATIC int cb_detect_voltage(struct pccbb_softc *);
112STATIC int cbbprint(void *, const char *);
113
114static int cb_chipset(u_int32_t, int *);
115STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *,
116 struct pcmciabus_attach_args *);
117
118STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int);
119STATIC int pccbb_power(struct pccbb_softc *sc, int);
120STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int);
121STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function);
122static void *pccbb_intr_establish(struct pccbb_softc *,
123 int level, int (*ih) (void *), void *sc);
124static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih);
125
126static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t,
127 int level, int (*ih) (void *), void *sc);
128static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih);
129
130static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int);
131static pcireg_t pccbb_conf_read(cardbus_chipset_tag_t, pcitag_t, int);
132static void pccbb_conf_write(cardbus_chipset_tag_t, pcitag_t, int,
133 pcireg_t);
134static void pccbb_chipinit(struct pccbb_softc *);
135static void pccbb_intrinit(struct pccbb_softc *);
136
137STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t,
138 struct pcmcia_mem_handle *);
139STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t,
140 struct pcmcia_mem_handle *);
141STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t,
142 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *);
143STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int);
144STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t,
145 bus_size_t, bus_size_t, struct pcmcia_io_handle *);
146STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t,
147 struct pcmcia_io_handle *);
148STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t,
149 bus_size_t, struct pcmcia_io_handle *, int *);
150STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int);
151STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t,
152 struct pcmcia_function *, int, int (*)(void *), void *);
153STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *);
154STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t);
155STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t);
156STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int);
157STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch);
158
159static int pccbb_pcmcia_wait_ready(struct pccbb_softc *);
160static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *);
161
162static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int);
163static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int);
164
165/* bus-space allocation and deallocation functions */
166
167static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t,
168 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align,
169 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp);
170static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t,
171 bus_space_handle_t, bus_size_t);
172
173
174
175static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t,
176 bus_addr_t, bus_size_t, bus_space_handle_t, int flags);
177static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t,
178 bus_space_handle_t, bus_size_t);
179static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t,
180 bus_size_t, bus_space_handle_t, int);
181static int pccbb_winlist_delete(struct pccbb_win_chain_head *,
182 bus_space_handle_t, bus_size_t);
183static void pccbb_winset(bus_addr_t align, struct pccbb_softc *,
184 bus_space_tag_t);
185void pccbb_winlist_show(struct pccbb_win_chain *);
186
187
188/* for config_defer */
189static void pccbb_pci_callback(device_t);
190
191static bool pccbb_suspend(device_t, const pmf_qual_t *);
192static bool pccbb_resume(device_t, const pmf_qual_t *);
193
194#if defined SHOW_REGS
195static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag,
196 bus_space_tag_t memt, bus_space_handle_t memh);
197#endif
198
199CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc),
200 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, pccbbchilddet,
201 DVF_DETACH_SHUTDOWN);
202
203static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = {
204 pccbb_pcmcia_mem_alloc,
205 pccbb_pcmcia_mem_free,
206 pccbb_pcmcia_mem_map,
207 pccbb_pcmcia_mem_unmap,
208 pccbb_pcmcia_io_alloc,
209 pccbb_pcmcia_io_free,
210 pccbb_pcmcia_io_map,
211 pccbb_pcmcia_io_unmap,
212 pccbb_pcmcia_intr_establish,
213 pccbb_pcmcia_intr_disestablish,
214 pccbb_pcmcia_socket_enable,
215 pccbb_pcmcia_socket_disable,
216 pccbb_pcmcia_socket_settype,
217 pccbb_pcmcia_card_detect
218};
219
220static const struct cardbus_functions pccbb_funcs = {
221 pccbb_rbus_cb_space_alloc,
222 pccbb_rbus_cb_space_free,
223 pccbb_cb_intr_establish,
224 pccbb_cb_intr_disestablish,
225 pccbb_ctrl,
226 pccbb_power_ct,
227 pccbb_make_tag,
228 pccbb_conf_read,
229 pccbb_conf_write,
230};
231
232int
233pcicbbmatch(device_t parent, cfdata_t match, void *aux)
234{
235 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
236
237 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
238 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS &&
239 PCI_INTERFACE(pa->pa_class) == 0) {
240 return 1;
241 }
242
243 return 0;
244}
245
246#define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \
247 | ((prod) << PCI_PRODUCT_SHIFT))
248
249const struct yenta_chipinfo {
250 pcireg_t yc_id; /* vendor tag | product tag */
251 int yc_chiptype;
252 int yc_flags;
253} yc_chipsets[] = {
254 /* Texas Instruments chips */
255 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X,
256 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
257 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X,
258 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
259 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X,
260 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
261 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX,
262 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
263 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX,
264 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
265 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX,
266 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
267 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X,
268 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
269 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X,
270 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
271 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX,
272 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
273 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX,
274 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
275 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420,
276 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
277 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X,
278 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
279 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX,
280 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
281 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX,
282 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
283 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX,
284 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX,
286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX,
288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX,
290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
291
292 /* Ricoh chips */
293 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X,
294 PCCBB_PCMCIA_MEM_32},
295 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X,
296 PCCBB_PCMCIA_MEM_32},
297 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X,
298 PCCBB_PCMCIA_MEM_32},
299 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X,
300 PCCBB_PCMCIA_MEM_32},
301 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X,
302 PCCBB_PCMCIA_MEM_32},
303 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X,
304 PCCBB_PCMCIA_MEM_32},
305
306 /* Toshiba products */
307 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95),
308 CB_TOPIC95, PCCBB_PCMCIA_MEM_32},
309 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B),
310 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32},
311 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97),
312 CB_TOPIC97, PCCBB_PCMCIA_MEM_32},
313 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100),
314 CB_TOPIC97, PCCBB_PCMCIA_MEM_32},
315
316 /* Cirrus Logic products */
317 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832),
318 CB_CIRRUS, PCCBB_PCMCIA_MEM_32},
319 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833),
320 CB_CIRRUS, PCCBB_PCMCIA_MEM_32},
321
322 /* O2 Micro products */
323 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729),
324 CB_O2MICRO, PCCBB_PCMCIA_MEM_32},
325 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730),
326 CB_O2MICRO, PCCBB_PCMCIA_MEM_32},
327 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832),
328 CB_O2MICRO, PCCBB_PCMCIA_MEM_32},
329 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836),
330 CB_O2MICRO, PCCBB_PCMCIA_MEM_32},
331 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872),
332 CB_O2MICRO, PCCBB_PCMCIA_MEM_32},
333 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922),
334 CB_O2MICRO, PCCBB_PCMCIA_MEM_32},
335 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933),
336 CB_O2MICRO, PCCBB_PCMCIA_MEM_32},
337 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972),
338 CB_O2MICRO, PCCBB_PCMCIA_MEM_32},
339 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223),
340 CB_O2MICRO, PCCBB_PCMCIA_MEM_32},
341
342 /* sentinel, or Generic chip */
343 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32},
344};
345
346static int
347cb_chipset(u_int32_t pci_id, int *flagp)
348{
349 const struct yenta_chipinfo *yc;
350
351 /* Loop over except the last default entry. */
352 for (yc = yc_chipsets; yc < yc_chipsets +
353 __arraycount(yc_chipsets) - 1; yc++)
354 if (pci_id == yc->yc_id)
355 break;
356
357 if (flagp != NULL)
358 *flagp = yc->yc_flags;
359
360 return (yc->yc_chiptype);
361}
362
363void
364pccbbchilddet(device_t self, device_t child)
365{
366 struct pccbb_softc *sc = device_private(self);
367 int s;
368
369 KASSERT(sc->sc_csc == device_private(child));
370
371 s = splbio();
372 if (sc->sc_csc == device_private(child))
373 sc->sc_csc = NULL;
374 splx(s);
375}
376
377void
378pccbbattach(device_t parent, device_t self, void *aux)
379{
380 struct pccbb_softc *sc = device_private(self);
381 struct pci_attach_args *pa = aux;
382 pci_chipset_tag_t pc = pa->pa_pc;
383 pcireg_t reg, sock_base;
384 bus_addr_t sockbase;
385 int flags;
386
387#ifdef __HAVE_PCCBB_ATTACH_HOOK
388 pccbb_attach_hook(parent, self, pa);
389#endif
390
391 sc->sc_dev = self;
392
393 mutex_init(&sc->sc_pwr_mtx, MUTEX_DEFAULT, IPL_BIO);
394 cv_init(&sc->sc_pwr_cv, "pccpwr");
395
396 callout_init(&sc->sc_insert_ch, 0);
397 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc);
398
399 sc->sc_chipset = cb_chipset(pa->pa_id, &flags);
400
401 pci_aprint_devinfo(pa, NULL);
402 DPRINTF(("(chipflags %x)", flags));
403
404 TAILQ_INIT(&sc->sc_memwindow);
405 TAILQ_INIT(&sc->sc_iowindow);
406
407 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa);
408 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa);
409
410#if 0
411 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n",
412 pa->pa_memt, sc->sc_rbus_memt->rb_bt);
413#endif
414
415 sc->sc_flags &= ~CBB_MEMHMAPPED;
416
417 /*
418 * MAP socket registers and ExCA registers on memory-space
419 * When no valid address is set on socket base registers (on pci
420 * config space), get it not polite way.
421 */
422 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE);
423
424 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 &&
425 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) {
426 /* The address must be valid. */
427 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0,
428 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase,
429 &sc->sc_base_size)) {
430 aprint_error_dev(self,
431 "can't map socket base address 0x%lx\n",
432 (unsigned long)sock_base);
433 /*
434 * I think it's funny: socket base registers must be
435 * mapped on memory space, but ...
436 */
437 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO,
438 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase,
439 &sc->sc_base_size)) {
440 aprint_error_dev(self,
441 "can't map socket base address"
442 " 0x%lx: io mode\n",
443 (unsigned long)sockbase);
444 /* give up... allocate reg space via rbus. */
445 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0);
446 } else
447 sc->sc_flags |= CBB_MEMHMAPPED;
448 } else {
449 DPRINTF(("%s: socket base address 0x%lx\n",
450 device_xname(self),
451 (unsigned long)sockbase));
452 sc->sc_flags |= CBB_MEMHMAPPED;
453 }
454 }
455
456 sc->sc_mem_start = 0; /* XXX */
457 sc->sc_mem_end = 0xffffffff; /* XXX */
458
459 /* pccbb_machdep.c end */
460
461#if defined CBB_DEBUG
462 {
463 static const char *intrname[] = { "NON", "A", "B", "C", "D" };
464 aprint_debug_dev(self, "intrpin %s, intrtag %d\n",
465 intrname[pa->pa_intrpin], pa->pa_intrline);
466 }
467#endif
468
469 /* setup softc */
470 sc->sc_pc = pc;
471 sc->sc_iot = pa->pa_iot;
472 sc->sc_memt = pa->pa_memt;
473 sc->sc_dmat = pa->pa_dmat;
474 sc->sc_tag = pa->pa_tag;
475
476 memcpy(&sc->sc_pa, pa, sizeof(*pa));
477
478 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */
479
480 /* Disable legacy register mapping. */
481 switch (sc->sc_chipset) {
482 case CB_RX5C46X: /* fallthrough */
483#if 0
484 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */
485 case CB_RX5C47X:
486#endif
487 /*
488 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges
489 * cannot be disabled by substituting 0 into PCI_LEGACY
490 * register. Ricoh CardBus bridges have special bits on Bridge
491 * control reg (addr 0x3e on PCI config space).
492 */
493 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG);
494 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA);
495 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg);
496 break;
497
498 default:
499 /* XXX I don't know proper way to kill legacy I/O. */
500 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0);
501 break;
502 }
503
504 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume))
505 aprint_error_dev(self, "couldn't establish power handler\n");
506
507 config_defer(self, pccbb_pci_callback);
508}
509
510int
511pccbbdetach(device_t self, int flags)
512{
513 struct pccbb_softc *sc = device_private(self);
514 pci_chipset_tag_t pc = sc->sc_pa.pa_pc;
515 bus_space_tag_t bmt = sc->sc_base_memt;
516 bus_space_handle_t bmh = sc->sc_base_memh;
517 uint32_t sockmask;
518 int rc;
519
520 if ((rc = config_detach_children(self, flags)) != 0)
521 return rc;
522
523 if (!LIST_EMPTY(&sc->sc_pil)) {
524 panic("%s: interrupt handlers still registered",
525 device_xname(self));
526 return EBUSY;
527 }
528
529 if (sc->sc_ih != NULL) {
530 pci_intr_disestablish(pc, sc->sc_ih);
531 sc->sc_ih = NULL;
532 }
533
534 /* CSC Interrupt: turn off card detect and power cycle interrupts */
535 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK);
536 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD |
537 CB_SOCKET_MASK_POWER);
538 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask);
539 /* reset interrupt */
540 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT,
541 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT));
542
543 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) {
544 case CBB_MEMHMAPPED:
545 bus_space_unmap(bmt, bmh, sc->sc_base_size);
546 break;
547 case CBB_MEMHMAPPED|CBB_SPECMAPPED:
548#if rbus
549 {
550 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000,
551 NULL);
552 }
553#else
554 bus_space_free(bmt, bmh, 0x1000);
555#endif
556 }
557 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED);
558
559 if (!TAILQ_EMPTY(&sc->sc_iowindow))
560 aprint_error_dev(self, "i/o windows not empty\n");
561 if (!TAILQ_EMPTY(&sc->sc_memwindow))
562 aprint_error_dev(self, "memory windows not empty\n");
563
564 callout_halt(&sc->sc_insert_ch, NULL);
565 callout_destroy(&sc->sc_insert_ch);
566
567 mutex_destroy(&sc->sc_pwr_mtx);
568 cv_destroy(&sc->sc_pwr_cv);
569
570 return 0;
571}
572
573/*
574 * static void pccbb_pci_callback(device_t self)
575 *
576 * The actual attach routine: get memory space for YENTA register
577 * space, setup YENTA register and route interrupt.
578 *
579 * This function should be deferred because this device may obtain
580 * memory space dynamically. This function must avoid obtaining
581 * memory area which has already kept for another device.
582 */
583static void
584pccbb_pci_callback(device_t self)
585{
586 struct pccbb_softc *sc = device_private(self);
587 pci_chipset_tag_t pc = sc->sc_pc;
588 bus_addr_t sockbase;
589 struct cbslot_attach_args cba;
590 struct pcmciabus_attach_args paa;
591 struct cardslot_attach_args caa;
592 device_t csc;
593
594 if (!(sc->sc_flags & CBB_MEMHMAPPED)) {
595 /* The socket registers aren't mapped correctly. */
596#if rbus
597 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff,
598 (sc->sc_chipset == CB_RX5C47X
599 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000,
600 0, &sockbase, &sc->sc_base_memh)) {
601 return;
602 }
603 sc->sc_base_memt = sc->sc_memt;
604 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase);
605 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n",
606 device_xname(self), (unsigned long)sockbase,
607 (unsigned long)pci_conf_read(pc, sc->sc_tag,
608 PCI_SOCKBASE)));
609#else
610 sc->sc_base_memt = sc->sc_memt;
611#if !defined CBB_PCI_BASE
612#define CBB_PCI_BASE 0x20000000
613#endif
614 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff,
615 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) {
616 /* cannot allocate memory space */
617 return;
618 }
619 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase);
620 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n",
621 device_xname(self), (unsigned long)sock_base,
622 (unsigned long)pci_conf_read(pc,
623 sc->sc_tag, PCI_SOCKBASE)));
624#endif
625 sc->sc_flags |= CBB_MEMHMAPPED|CBB_SPECMAPPED;
626 }
627
628 /* clear data structure for child device interrupt handlers */
629 LIST_INIT(&sc->sc_pil);
630
631 /* bus bridge initialization */
632 pccbb_chipinit(sc);
633
634 sc->sc_pil_intr_enable = true;
635
636 {
637 u_int32_t sockstat;
638
639 sockstat = bus_space_read_4(sc->sc_base_memt,
640 sc->sc_base_memh, CB_SOCKET_STAT);
641 if (0 == (sockstat & CB_SOCKET_STAT_CD)) {
642 sc->sc_flags |= CBB_CARDEXIST;
643 }
644 }
645
646 /*
647 * attach cardbus
648 */
649 {
650 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM);
651 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG);
652
653 /* initialize cbslot_attach */
654 cba.cba_iot = sc->sc_iot;
655 cba.cba_memt = sc->sc_memt;
656 cba.cba_dmat = sc->sc_dmat;
657 cba.cba_bus = (busreg >> 8) & 0x0ff;
658 cba.cba_cc = (void *)sc;
659 cba.cba_cf = &pccbb_funcs;
660
661#if rbus
662 cba.cba_rbus_iot = sc->sc_rbus_iot;
663 cba.cba_rbus_memt = sc->sc_rbus_memt;
664#endif
665
666 cba.cba_cacheline = PCI_CACHELINE(bhlc);
667 cba.cba_max_lattimer = PCI_LATTIMER(bhlc);
668
669 aprint_verbose_dev(self,
670 "cacheline 0x%x lattimer 0x%x\n",
671 cba.cba_cacheline,
672 cba.cba_max_lattimer);
673 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc);
674#if defined SHOW_REGS
675 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt,
676 sc->sc_base_memh);
677#endif
678 }
679
680 pccbb_pcmcia_attach_setup(sc, &paa);
681 caa.caa_cb_attach = NULL;
682 if (cba.cba_bus == 0)
683 aprint_error_dev(self,
684 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n");
685 else
686 caa.caa_cb_attach = &cba;
687 caa.caa_16_attach = &paa;
688
689 pccbb_intrinit(sc);
690
691 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa,
692 cbbprint))) {
693 DPRINTF(("%s: found cardslot\n", __func__));
694 sc->sc_csc = device_private(csc);
695 }
696
697 return;
698}
699
700
701
702
703
704/*
705 * static void pccbb_chipinit(struct pccbb_softc *sc)
706 *
707 * This function initialize YENTA chip registers listed below:
708 * 1) PCI command reg,
709 * 2) PCI and CardBus latency timer,
710 * 3) route PCI interrupt,
711 * 4) close all memory and io windows.
712 * 5) turn off bus power.
713 * 6) card detect and power cycle interrupts on.
714 * 7) clear interrupt
715 */
716static void
717pccbb_chipinit(struct pccbb_softc *sc)
718{
719 pci_chipset_tag_t pc = sc->sc_pc;
720 pcitag_t tag = sc->sc_tag;
721 bus_space_tag_t bmt = sc->sc_base_memt;
722 bus_space_handle_t bmh = sc->sc_base_memh;
723 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl,
724 sysctrl;
725
726 /*
727 * Set PCI command reg.
728 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip.
729 */
730 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
731 /* I believe it is harmless. */
732 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
733 PCI_COMMAND_MASTER_ENABLE);
734
735 /* All O2 Micro chips have broken parity-error reporting
736 * until proven otherwise. The OZ6933 PCI-CardBus Bridge
737 * is known to have the defect---see PR kern/38698.
738 */
739 if (sc->sc_chipset != CB_O2MICRO)
740 csr |= PCI_COMMAND_PARITY_ENABLE;
741
742 csr |= PCI_COMMAND_SERR_ENABLE;
743 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
744
745 /*
746 * Set CardBus latency timer.
747 */
748 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG);
749 if (PCI_CB_LATENCY(lscp) < 0x20) {
750 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT);
751 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT);
752 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp);
753 }
754 DPRINTF(("CardBus latency timer 0x%x (%x)\n",
755 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG)));
756
757 /*
758 * Set PCI latency timer.
759 */
760 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
761 if (PCI_LATTIMER(bhlc) < 0x10) {
762 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
763 bhlc |= (0x10 << PCI_LATTIMER_SHIFT);
764 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
765 }
766 DPRINTF(("PCI latency timer 0x%x (%x)\n",
767 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG)));
768
769
770 /* Route functional interrupts to PCI. */
771 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG);
772 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */
773 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */
774 /* assert reset */
775 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT;
776 /* Set master abort mode to 1, forward SERR# from secondary
777 * to primary, and detect parity errors on secondary.
778 */
779 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT;
780 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT;
781 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT;
782 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr);
783
784 switch (sc->sc_chipset) {
785 case CB_TI113X:
786 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL);
787 /* This bit is shared, but may read as 0 on some chips, so set
788 it explicitly on both functions. */
789 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA;
790 /* CSC intr enable */
791 cbctl |= PCI113X_CBCTRL_PCI_CSC;
792 /* functional intr prohibit | prohibit ISA routing */
793 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK);
794 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl);
795 break;
796
797 case CB_TI1420:
798 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL);
799 mrburst = pccbb_burstup
800 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN;
801 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) {
802 printf("%s: %swrite bursts enabled\n",
803 device_xname(sc->sc_dev),
804 pccbb_burstup ? "read/" : "");
805 } else if (pccbb_burstup) {
806 printf("%s: enabling read/write bursts\n",
807 device_xname(sc->sc_dev));
808 sysctrl |= PCI1420_SYSCTRL_MRBURST;
809 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl);
810 } else {
811 printf("%s: disabling read bursts, "
812 "enabling write bursts\n",
813 device_xname(sc->sc_dev));
814 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN;
815 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP;
816 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl);
817 }
818 /*FALLTHROUGH*/
819 case CB_TI12XX:
820 /*
821 * Some TI 12xx (and [14][45]xx) based pci cards
822 * sometimes have issues with the MFUNC register not
823 * being initialized due to a bad EEPROM on board.
824 * Laptops that this matters on have this register
825 * properly initialized.
826 *
827 * The TI125X parts have a different register.
828 */
829 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC);
830 if ((mfunc & (PCI12XX_MFUNC_PIN0 | PCI12XX_MFUNC_PIN1)) == 0) {
831 /* Enable PCI interrupt /INTA */
832 mfunc |= PCI12XX_MFUNC_PIN0_INTA;
833
834 /* XXX this is TI1520 only */
835 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) &
836 PCI12XX_SYSCTRL_INTRTIE) == 0)
837 /* Enable PCI interrupt /INTB */
838 mfunc |= PCI12XX_MFUNC_PIN1_INTB;
839
840 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc);
841 }
842 /* fallthrough */
843
844 case CB_TI125X:
845 /*
846 * Disable zoom video. Some machines initialize this
847 * improperly and experience has shown that this helps
848 * prevent strange behavior.
849 */
850 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0);
851
852 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL);
853 sysctrl |= PCI12XX_SYSCTRL_VCCPROT;
854 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl);
855 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL);
856 cbctl |= PCI12XX_CBCTRL_CSC;
857 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl);
858 break;
859
860 case CB_TOPIC95B:
861 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL);
862 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;
863 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl);
864 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL);
865 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ",
866 device_xname(sc->sc_dev), slotctl));
867 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
868 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
869 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT;
870 DPRINTF(("0x%x\n", slotctl));
871 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl);
872 break;
873
874 case CB_TOPIC97:
875 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL);
876 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ",
877 device_xname(sc->sc_dev), slotctl));
878 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
879 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
880 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT;
881 slotctl |= TOPIC97_SLOT_CTRL_PCIINT;
882 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP);
883 DPRINTF(("0x%x\n", slotctl));
884 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl);
885 /* make sure to assert LV card support bits */
886 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh,
887 0x800 + 0x3e,
888 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh,
889 0x800 + 0x3e) | 0x03);
890 break;
891 }
892
893 /* Close all memory and I/O windows. */
894 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff);
895 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0);
896 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff);
897 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0);
898 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff);
899 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0);
900 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff);
901 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0);
902
903 /* reset 16-bit pcmcia bus */
904 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR,
905 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET);
906
907 /* turn off power */
908 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
909}
910
911static void
912pccbb_intrinit(struct pccbb_softc *sc)
913{
914 pcireg_t sockmask;
915 const char *intrstr = NULL;
916 pci_intr_handle_t ih;
917 pci_chipset_tag_t pc = sc->sc_pc;
918 bus_space_tag_t bmt = sc->sc_base_memt;
919 bus_space_handle_t bmh = sc->sc_base_memh;
920 char intrbuf[PCI_INTRSTR_LEN];
921
922 /* Map and establish the interrupt. */
923 if (pci_intr_map(&sc->sc_pa, &ih)) {
924 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n");
925 return;
926 }
927 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
928
929 /*
930 * XXX pccbbintr should be called under the priority lower
931 * than any other hard interrupts.
932 */
933 KASSERT(sc->sc_ih == NULL);
934 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc);
935
936 if (sc->sc_ih == NULL) {
937 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt");
938 if (intrstr != NULL)
939 aprint_error(" at %s\n", intrstr);
940 else
941 aprint_error("\n");
942 return;
943 }
944
945 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
946
947 /* CSC Interrupt: Card detect and power cycle interrupts on */
948 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK);
949 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD |
950 CB_SOCKET_MASK_POWER;
951 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask);
952 /* reset interrupt */
953 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT,
954 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT));
955}
956
957/*
958 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc,
959 * struct pcmciabus_attach_args *paa)
960 *
961 * This function attaches 16-bit PCcard bus.
962 */
963STATIC void
964pccbb_pcmcia_attach_setup(struct pccbb_softc *sc,
965 struct pcmciabus_attach_args *paa)
966{
967 /*
968 * We need to do a few things here:
969 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by
970 * setting the IRQ numbers to 0.
971 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable
972 * routing of CSC interrupts (e.g. card removal) to PCI while in
973 * PCMCIA mode. We just leave this set all the time.
974 * 3) Enable card insertion/removal interrupts in case the chip also
975 * needs that while in PCMCIA mode.
976 * 4) Clear any pending CSC interrupt.
977 */
978 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE);
979 if (sc->sc_chipset == CB_TI113X) {
980 Pcic_write(sc, PCIC_CSC_INTR, 0);
981 } else {
982 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE);
983 Pcic_read(sc, PCIC_CSC);
984 }
985
986 /* initialize pcmcia bus attachment */
987 paa->paa_busname = "pcmcia";
988 paa->pct = &pccbb_pcmcia_funcs;
989 paa->pch = sc;
990 return;
991}
992
993/*
994 * int pccbbintr(arg)
995 * void *arg;
996 * This routine handles the interrupt from Yenta PCI-CardBus bridge
997 * itself.
998 */
999int
1000pccbbintr(void *arg)
1001{
1002 struct pccbb_softc *sc = (struct pccbb_softc *)arg;
1003 struct cardslot_softc *csc;
1004 u_int32_t sockevent, sockstate;
1005 bus_space_tag_t memt = sc->sc_base_memt;
1006 bus_space_handle_t memh = sc->sc_base_memh;
1007
1008 if (!device_has_power(sc->sc_dev))
1009 return 0;
1010
1011 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT);
1012 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent);
1013 Pcic_read(sc, PCIC_CSC);
1014
1015 if (sockevent != 0) {
1016 DPRINTF(("%s: enter sockevent %" PRIx32 "\n",
1017 __func__, sockevent));
1018 }
1019
1020 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER
1021 * does occur in the wild. Check for a _POWER event before
1022 * possibly exiting because of an _CSTS event.
1023 */
1024 if (sockevent & CB_SOCKET_EVENT_POWER) {
1025 DPRINTF(("Powercycling because of socket event\n"));
1026 /* XXX: Does not happen when attaching a 16-bit card */
1027 mutex_enter(&sc->sc_pwr_mtx);
1028 sc->sc_pwrcycle++;
1029 cv_signal(&sc->sc_pwr_cv);
1030 mutex_exit(&sc->sc_pwr_mtx);
1031 }
1032
1033 /* Sometimes a change of CSTSCHG# accompanies the first
1034 * interrupt from an Atheros WLAN. That generates a
1035 * CB_SOCKET_EVENT_CSTS event on the bridge. The event
1036 * isn't interesting to pccbb(4), so we used to ignore the
1037 * interrupt. Now, let the child devices try to handle
1038 * the interrupt, instead. The Atheros NIC produces
1039 * interrupts more reliably, now: used to be that it would
1040 * only interrupt if the driver avoided powering down the
1041 * NIC's cardslot, and then the NIC would only work after
1042 * it was reset a second time.
1043 */
1044 if (sockevent == 0 ||
1045 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) {
1046 /* This intr is not for me: it may be for my child devices. */
1047 if (sc->sc_pil_intr_enable) {
1048 return pccbbintr_function(sc);
1049 } else {
1050 return 0;
1051 }
1052 }
1053
1054 if (sockevent & CB_SOCKET_EVENT_CD) {
1055 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
1056 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) {
1057 /* A card should be removed. */
1058 if (sc->sc_flags & CBB_CARDEXIST) {
1059 DPRINTF(("%s: 0x%08x",
1060 device_xname(sc->sc_dev), sockevent));
1061 DPRINTF((" card removed, 0x%08x\n", sockstate));
1062 sc->sc_flags &= ~CBB_CARDEXIST;
1063 if ((csc = sc->sc_csc) == NULL)
1064 ;
1065 else if (csc->sc_status &
1066 CARDSLOT_STATUS_CARD_16) {
1067 cardslot_event_throw(csc,
1068 CARDSLOT_EVENT_REMOVAL_16);
1069 } else if (csc->sc_status &
1070 CARDSLOT_STATUS_CARD_CB) {
1071 /* Cardbus intr removed */
1072 cardslot_event_throw(csc,
1073 CARDSLOT_EVENT_REMOVAL_CB);
1074 }
1075 } else if (sc->sc_flags & CBB_INSERTING) {
1076 sc->sc_flags &= ~CBB_INSERTING;
1077 callout_stop(&sc->sc_insert_ch);
1078 }
1079 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) &&
1080 /*
1081 * The pccbbintr may called from powerdown hook when
1082 * the system resumed, to detect the card
1083 * insertion/removal during suspension.
1084 */
1085 (sc->sc_flags & CBB_CARDEXIST) == 0) {
1086 if (sc->sc_flags & CBB_INSERTING) {
1087 callout_stop(&sc->sc_insert_ch);
1088 }
1089 callout_schedule(&sc->sc_insert_ch, mstohz(200));
1090 sc->sc_flags |= CBB_INSERTING;
1091 }
1092 }
1093
1094 return (1);
1095}
1096
1097/*
1098 * static int pccbbintr_function(struct pccbb_softc *sc)
1099 *
1100 * This function calls each interrupt handler registered at the
1101 * bridge. The interrupt handlers are called in registered order.
1102 */
1103static int
1104pccbbintr_function(struct pccbb_softc *sc)
1105{
1106 int retval = 0, val;
1107 struct pccbb_intrhand_list *pil;
1108 int s;
1109
1110 LIST_FOREACH(pil, &sc->sc_pil, pil_next) {
1111 s = splraiseipl(pil->pil_icookie);
1112 val = (*pil->pil_func)(pil->pil_arg);
1113 splx(s);
1114
1115 retval = retval == 1 ? 1 :
1116 retval == 0 ? val : val != 0 ? val : retval;
1117 }
1118
1119 return retval;
1120}
1121
1122static void
1123pci113x_insert(void *arg)
1124{
1125 struct pccbb_softc *sc = arg;
1126 struct cardslot_softc *csc;
1127 u_int32_t sockevent, sockstate;
1128
1129 if (!(sc->sc_flags & CBB_INSERTING)) {
1130 /* We add a card only under inserting state. */
1131 return;
1132 }
1133 sc->sc_flags &= ~CBB_INSERTING;
1134
1135 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
1136 CB_SOCKET_EVENT);
1137 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
1138 CB_SOCKET_STAT);
1139
1140 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */
1141#ifdef CBB_DEBUG
1142 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent));
1143#else
1144 __USE(sockevent);
1145#endif
1146
1147 DPRINTF((" card inserted, 0x%08x\n", sockstate));
1148 sc->sc_flags |= CBB_CARDEXIST;
1149 /* call pccard interrupt handler here */
1150 if ((csc = sc->sc_csc) == NULL)
1151 ;
1152 else if (sockstate & CB_SOCKET_STAT_16BIT) {
1153 /* 16-bit card found */
1154 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_16);
1155 } else if (sockstate & CB_SOCKET_STAT_CB) {
1156 /* cardbus card found */
1157 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_CB);
1158 } else {
1159 /* who are you? */
1160 }
1161 } else {
1162 callout_schedule(&sc->sc_insert_ch, mstohz(100));
1163 }
1164}
1165
1166#define PCCBB_PCMCIA_OFFSET 0x800
1167static u_int8_t
1168pccbb_pcmcia_read(struct pccbb_softc *sc, int reg)
1169{
1170 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh,
1171 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ);
1172
1173 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh,
1174 PCCBB_PCMCIA_OFFSET + reg);
1175}
1176
1177static void
1178pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val)
1179{
1180 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh,
1181 PCCBB_PCMCIA_OFFSET + reg, val);
1182
1183 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh,
1184 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE);
1185}
1186
1187/*
1188 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int)
1189 */
1190STATIC int
1191pccbb_ctrl(cardbus_chipset_tag_t ct, int command)
1192{
1193 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1194
1195 switch (command) {
1196 case CARDBUS_CD:
1197 if (2 == pccbb_detect_card(sc)) {
1198 int retval = 0;
1199 int status = cb_detect_voltage(sc);
1200 if (PCCARD_VCC_5V & status) {
1201 retval |= CARDBUS_5V_CARD;
1202 }
1203 if (PCCARD_VCC_3V & status) {
1204 retval |= CARDBUS_3V_CARD;
1205 }
1206 if (PCCARD_VCC_XV & status) {
1207 retval |= CARDBUS_XV_CARD;
1208 }
1209 if (PCCARD_VCC_YV & status) {
1210 retval |= CARDBUS_YV_CARD;
1211 }
1212 return retval;
1213 } else {
1214 return 0;
1215 }
1216 case CARDBUS_RESET:
1217 return cb_reset(sc);
1218 case CARDBUS_IO_ENABLE: /* fallthrough */
1219 case CARDBUS_IO_DISABLE: /* fallthrough */
1220 case CARDBUS_MEM_ENABLE: /* fallthrough */
1221 case CARDBUS_MEM_DISABLE: /* fallthrough */
1222 case CARDBUS_BM_ENABLE: /* fallthrough */
1223 case CARDBUS_BM_DISABLE: /* fallthrough */
1224 /* XXX: I think we don't need to call this function below. */
1225 return pccbb_cardenable(sc, command);
1226 }
1227
1228 return 0;
1229}
1230
1231STATIC int
1232pccbb_power_ct(cardbus_chipset_tag_t ct, int command)
1233{
1234 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1235
1236 return pccbb_power(sc, command);
1237}
1238
1239/*
1240 * STATIC int pccbb_power(cardbus_chipset_tag_t, int)
1241 * This function returns true when it succeeds and returns false when
1242 * it fails.
1243 */
1244STATIC int
1245pccbb_power(struct pccbb_softc *sc, int command)
1246{
1247 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl;
1248 bus_space_tag_t memt = sc->sc_base_memt;
1249 bus_space_handle_t memh = sc->sc_base_memh;
1250 int on = 0, pwrcycle, times;
1251 struct timeval before, after, diff;
1252
1253 DPRINTF(("pccbb_power: %s and %s [0x%x]\n",
1254 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" :
1255 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" :
1256 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" :
1257 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" :
1258 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" :
1259 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" :
1260 "UNKNOWN",
1261 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" :
1262 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" :
1263 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" :
1264 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" :
1265 "UNKNOWN", command));
1266
1267 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
1268 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL);
1269
1270 switch (command & CARDBUS_VCCMASK) {
1271 case CARDBUS_VCC_UC:
1272 break;
1273 case CARDBUS_VCC_5V:
1274 on++;
1275 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */
1276 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;
1277 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V;
1278 } else {
1279 aprint_error_dev(sc->sc_dev,
1280 "BAD voltage request: no 5 V card\n");
1281 return 0;
1282 }
1283 break;
1284 case CARDBUS_VCC_3V:
1285 on++;
1286 if (CB_SOCKET_STAT_3VCARD & status) {
1287 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;
1288 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V;
1289 } else {
1290 aprint_error_dev(sc->sc_dev,
1291 "BAD voltage request: no 3.3 V card\n");
1292 return 0;
1293 }
1294 break;
1295 case CARDBUS_VCC_0V:
1296 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;
1297 break;
1298 default:
1299 return 0; /* power NEVER changed */
1300 }
1301
1302 switch (command & CARDBUS_VPPMASK) {
1303 case CARDBUS_VPP_UC:
1304 break;
1305 case CARDBUS_VPP_0V:
1306 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;
1307 break;
1308 case CARDBUS_VPP_VCC:
1309 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;
1310 sock_ctrl |= ((sock_ctrl >> 4) & 0x07);
1311 break;
1312 case CARDBUS_VPP_12V:
1313 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;
1314 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V;
1315 break;
1316 }
1317 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32
1318 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl);
1319
1320 microtime(&before);
1321 mutex_enter(&sc->sc_pwr_mtx);
1322 pwrcycle = sc->sc_pwrcycle;
1323
1324 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl);
1325
1326 /*
1327 * Wait as long as 200ms for a power-cycle interrupt. If
1328 * interrupts are enabled, but the socket has already
1329 * changed to the desired status, keep waiting for the
1330 * interrupt. "Consuming" the interrupt in this way keeps
1331 * the interrupt from prematurely waking some subsequent
1332 * pccbb_power call.
1333 *
1334 * XXX Not every bridge interrupts on the ->OFF transition.
1335 * XXX That's ok, we will time-out after 200ms.
1336 *
1337 * XXX The power cycle event will never happen when attaching
1338 * XXX a 16-bit card. That's ok, we will time-out after
1339 * XXX 200ms.
1340 */
1341 for (times = 5; --times >= 0; ) {
1342 if (cold)
1343 DELAY(40 * 1000);
1344 else {
1345 (void)cv_timedwait(&sc->sc_pwr_cv, &sc->sc_pwr_mtx,
1346 mstohz(40));
1347 if (pwrcycle == sc->sc_pwrcycle)
1348 continue;
1349 }
1350 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
1351 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on)
1352 break;
1353 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on)
1354 break;
1355 }
1356 mutex_exit(&sc->sc_pwr_mtx);
1357 microtime(&after);
1358 timersub(&after, &before, &diff);
1359 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n",
1360 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec,
1361 (long)diff.tv_usec);
1362
1363 /*
1364 * Ok, wait a bit longer for things to settle.
1365 */
1366 if (on && sc->sc_chipset == CB_TOPIC95B)
1367 delay_ms(100, sc);
1368
1369 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
1370
1371 if (on && sc->sc_chipset != CB_TOPIC95B) {
1372 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0)
1373 aprint_error_dev(sc->sc_dev, "power on failed?\n");
1374 }
1375
1376 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */
1377 aprint_error_dev(sc->sc_dev,
1378 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n",
1379 sock_ctrl, status);
1380 aprint_error_dev(sc->sc_dev, "disabling socket\n");
1381 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;
1382 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;
1383 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl);
1384 status &= ~CB_SOCKET_STAT_BADVCC;
1385 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status);
1386 printf("new status 0x%x\n", bus_space_read_4(memt, memh,
1387 CB_SOCKET_STAT));
1388 return 0;
1389 }
1390
1391 if (sc->sc_chipset == CB_TOPIC97) {
1392 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL);
1393 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE;
1394 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V)
1395 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA;
1396 else
1397 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA;
1398 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl);
1399 }
1400
1401 return 1; /* power changed correctly */
1402}
1403
1404/*
1405 * static int pccbb_detect_card(struct pccbb_softc *sc)
1406 * return value: 0 if no card exists.
1407 * 1 if 16-bit card exists.
1408 * 2 if cardbus card exists.
1409 */
1410static int
1411pccbb_detect_card(struct pccbb_softc *sc)
1412{
1413 bus_space_handle_t base_memh = sc->sc_base_memh;
1414 bus_space_tag_t base_memt = sc->sc_base_memt;
1415 u_int32_t sockstat =
1416 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT);
1417 int retval = 0;
1418
1419 /* CD1 and CD2 asserted */
1420 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) {
1421 /* card must be present */
1422 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) {
1423 /* NOTACARD DEASSERTED */
1424 if (CB_SOCKET_STAT_CB & sockstat) {
1425 /* CardBus mode */
1426 retval = 2;
1427 } else if (CB_SOCKET_STAT_16BIT & sockstat) {
1428 /* 16-bit mode */
1429 retval = 1;
1430 }
1431 }
1432 }
1433 return retval;
1434}
1435
1436/*
1437 * STATIC int cb_reset(struct pccbb_softc *sc)
1438 * This function resets CardBus card.
1439 */
1440STATIC int
1441cb_reset(struct pccbb_softc *sc)
1442{
1443 /*
1444 * Reset Assert at least 20 ms
1445 * Some machines request longer duration.
1446 */
1447 int reset_duration =
1448 (sc->sc_chipset == CB_RX5C47X ? 400 : 50);
1449 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag,
1450 PCI_BRIDGE_CONTROL_REG);
1451 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr);
1452
1453 /* Reset bit Assert (bit 6 at 0x3E) */
1454 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT;
1455 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr);
1456 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr);
1457 delay_ms(reset_duration, sc);
1458
1459 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */
1460 /* Reset bit Deassert (bit 6 at 0x3E) */
1461 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT);
1462 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG,
1463 bcr);
1464 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr);
1465 delay_ms(reset_duration, sc);
1466 aprint_debug("%s: end of delay\n", __func__);
1467 }
1468 /* No card found on the slot. Keep Reset. */
1469 return 1;
1470}
1471
1472/*
1473 * STATIC int cb_detect_voltage(struct pccbb_softc *sc)
1474 * This function detect card Voltage.
1475 */
1476STATIC int
1477cb_detect_voltage(struct pccbb_softc *sc)
1478{
1479 u_int32_t psr; /* socket present-state reg */
1480 bus_space_tag_t iot = sc->sc_base_memt;
1481 bus_space_handle_t ioh = sc->sc_base_memh;
1482 int vol = PCCARD_VCC_UKN; /* set 0 */
1483
1484 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT);
1485
1486 if (0x400u & psr) {
1487 vol |= PCCARD_VCC_5V;
1488 }
1489 if (0x800u & psr) {
1490 vol |= PCCARD_VCC_3V;
1491 }
1492
1493 return vol;
1494}
1495
1496STATIC int
1497cbbprint(void *aux, const char *pcic)
1498{
1499#if 0
1500 struct cbslot_attach_args *cba = aux;
1501
1502 if (cba->cba_slot >= 0) {
1503 aprint_normal(" slot %d", cba->cba_slot);
1504 }
1505#endif
1506 return UNCONF;
1507}
1508
1509/*
1510 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function)
1511 * This function enables and disables the card
1512 */
1513STATIC int
1514pccbb_cardenable(struct pccbb_softc *sc, int function)
1515{
1516 u_int32_t command =
1517 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
1518
1519 DPRINTF(("pccbb_cardenable:"));
1520 switch (function) {
1521 case CARDBUS_IO_ENABLE:
1522 command |= PCI_COMMAND_IO_ENABLE;
1523 break;
1524 case CARDBUS_IO_DISABLE:
1525 command &= ~PCI_COMMAND_IO_ENABLE;
1526 break;
1527 case CARDBUS_MEM_ENABLE:
1528 command |= PCI_COMMAND_MEM_ENABLE;
1529 break;
1530 case CARDBUS_MEM_DISABLE:
1531 command &= ~PCI_COMMAND_MEM_ENABLE;
1532 break;
1533 case CARDBUS_BM_ENABLE:
1534 command |= PCI_COMMAND_MASTER_ENABLE;
1535 break;
1536 case CARDBUS_BM_DISABLE:
1537 command &= ~PCI_COMMAND_MASTER_ENABLE;
1538 break;
1539 default:
1540 return 0;
1541 }
1542
1543 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command);
1544 DPRINTF((" command reg 0x%x\n", command));
1545 return 1;
1546}
1547
1548#if !rbus
1549static int
1550pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end)
1551{
1552 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1553 int basereg;
1554 int limitreg;
1555
1556 if ((win < 0) || (win > 2)) {
1557#if defined DIAGNOSTIC
1558 printf("cardbus_io_open: window out of range %d\n", win);
1559#endif
1560 return 0;
1561 }
1562
1563 basereg = win * 8 + PCI_CB_IOBASE0;
1564 limitreg = win * 8 + PCI_CB_IOLIMIT0;
1565
1566 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n",
1567 start, basereg, end, limitreg));
1568
1569 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start);
1570 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end);
1571 return 1;
1572}
1573
1574/*
1575 * int pccbb_io_close(cardbus_chipset_tag_t, int)
1576 */
1577static int
1578pccbb_io_close(cardbus_chipset_tag_t ct, int win)
1579{
1580 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1581 int basereg;
1582 int limitreg;
1583
1584 if ((win < 0) || (win > 2)) {
1585#if defined DIAGNOSTIC
1586 printf("cardbus_io_close: window out of range %d\n", win);
1587#endif
1588 return 0;
1589 }
1590
1591 basereg = win * 8 + PCI_CB_IOBASE0;
1592 limitreg = win * 8 + PCI_CB_IOLIMIT0;
1593
1594 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0);
1595 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0);
1596 return 1;
1597}
1598
1599static int
1600pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end)
1601{
1602 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1603 int basereg;
1604 int limitreg;
1605
1606 if ((win < 0) || (win > 2)) {
1607#if defined DIAGNOSTIC
1608 printf("cardbus_mem_open: window out of range %d\n", win);
1609#endif
1610 return 0;
1611 }
1612
1613 basereg = win * 8 + PCI_CB_MEMBASE0;
1614 limitreg = win * 8 + PCI_CB_MEMLIMIT0;
1615
1616 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start);
1617 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end);
1618 return 1;
1619}
1620
1621static int
1622pccbb_mem_close(cardbus_chipset_tag_t ct, int win)
1623{
1624 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1625 int basereg;
1626 int limitreg;
1627
1628 if ((win < 0) || (win > 2)) {
1629#if defined DIAGNOSTIC
1630 printf("cardbus_mem_close: window out of range %d\n", win);
1631#endif
1632 return 0;
1633 }
1634
1635 basereg = win * 8 + PCI_CB_MEMBASE0;
1636 limitreg = win * 8 + PCI_CB_MEMLIMIT0;
1637
1638 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0);
1639 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0);
1640 return 1;
1641}
1642#endif
1643
1644/*
1645 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct,
1646 * int level,
1647 * int (* func)(void *),
1648 * void *arg)
1649 *
1650 * This function registers an interrupt handler at the bridge, in
1651 * order not to call the interrupt handlers of child devices when
1652 * a card-deletion interrupt occurs.
1653 *
1654 * The argument level is not used.
1655 */
1656static void *
1657pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int level,
1658 int (*func)(void *), void *arg)
1659{
1660 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1661
1662 return pccbb_intr_establish(sc, level, func, arg);
1663}
1664
1665
1666/*
1667 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct,
1668 * void *ih)
1669 *
1670 * This function removes an interrupt handler pointed by ih.
1671 */
1672static void
1673pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih)
1674{
1675 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1676
1677 pccbb_intr_disestablish(sc, ih);
1678}
1679
1680
1681void
1682pccbb_intr_route(struct pccbb_softc *sc)
1683{
1684 pcireg_t bcr, cbctrl;
1685
1686 /* initialize bridge intr routing */
1687 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG);
1688 bcr &= ~CB_BCR_INTR_IREQ_ENABLE;
1689 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr);
1690
1691 switch (sc->sc_chipset) {
1692 case CB_TI113X:
1693 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);
1694 /* functional intr enabled */
1695 cbctrl |= PCI113X_CBCTRL_PCI_INTR;
1696 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl);
1697 break;
1698 default:
1699 break;
1700 }
1701}
1702
1703/*
1704 * static void *pccbb_intr_establish(struct pccbb_softc *sc,
1705 * int irq,
1706 * int level,
1707 * int (* func)(void *),
1708 * void *arg)
1709 *
1710 * This function registers an interrupt handler at the bridge, in
1711 * order not to call the interrupt handlers of child devices when
1712 * a card-deletion interrupt occurs.
1713 *
1714 */
1715static void *
1716pccbb_intr_establish(struct pccbb_softc *sc, int level,
1717 int (*func)(void *), void *arg)
1718{
1719 struct pccbb_intrhand_list *pil, *newpil;
1720
1721 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil)));
1722
1723 if (LIST_EMPTY(&sc->sc_pil)) {
1724 pccbb_intr_route(sc);
1725 }
1726
1727 /*
1728 * Allocate a room for interrupt handler structure.
1729 */
1730 if (NULL == (newpil =
1731 (struct pccbb_intrhand_list *)malloc(sizeof(struct
1732 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) {
1733 return NULL;
1734 }
1735
1736 newpil->pil_func = func;
1737 newpil->pil_arg = arg;
1738 newpil->pil_icookie = makeiplcookie(level);
1739
1740 if (LIST_EMPTY(&sc->sc_pil)) {
1741 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next);
1742 } else {
1743 for (pil = LIST_FIRST(&sc->sc_pil);
1744 LIST_NEXT(pil, pil_next) != NULL;
1745 pil = LIST_NEXT(pil, pil_next));
1746 LIST_INSERT_AFTER(pil, newpil, pil_next);
1747 }
1748
1749 DPRINTF(("pccbb_intr_establish add pil. %p\n",
1750 LIST_FIRST(&sc->sc_pil)));
1751
1752 return newpil;
1753}
1754
1755/*
1756 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc,
1757 * void *ih)
1758 *
1759 * This function removes an interrupt handler pointed by ih. ih
1760 * should be the value returned by cardbus_intr_establish() or
1761 * NULL.
1762 *
1763 * When ih is NULL, this function will do nothing.
1764 */
1765static void
1766pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih)
1767{
1768 struct pccbb_intrhand_list *pil;
1769 pcireg_t reg;
1770
1771 DPRINTF(("pccbb_intr_disestablish start. %p\n",
1772 LIST_FIRST(&sc->sc_pil)));
1773
1774 if (ih == NULL) {
1775 /* intr handler is not set */
1776 DPRINTF(("pccbb_intr_disestablish: no ih\n"));
1777 return;
1778 }
1779
1780#ifdef DIAGNOSTIC
1781 LIST_FOREACH(pil, &sc->sc_pil, pil_next) {
1782 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil));
1783 if (pil == ih) {
1784 DPRINTF(("pccbb_intr_disestablish frees one pil\n"));
1785 break;
1786 }
1787 }
1788 if (pil == NULL) {
1789 panic("pccbb_intr_disestablish: %s cannot find pil %p",
1790 device_xname(sc->sc_dev), ih);
1791 }
1792#endif
1793
1794 pil = (struct pccbb_intrhand_list *)ih;
1795 LIST_REMOVE(pil, pil_next);
1796 free(pil, M_DEVBUF);
1797 DPRINTF(("pccbb_intr_disestablish frees one pil\n"));
1798
1799 if (LIST_EMPTY(&sc->sc_pil)) {
1800 /* No interrupt handlers */
1801
1802 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n"));
1803
1804 /* stop routing PCI intr */
1805 reg = pci_conf_read(sc->sc_pc, sc->sc_tag,
1806 PCI_BRIDGE_CONTROL_REG);
1807 reg |= CB_BCR_INTR_IREQ_ENABLE;
1808 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG,
1809 reg);
1810
1811 switch (sc->sc_chipset) {
1812 case CB_TI113X:
1813 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);
1814 /* functional intr disabled */
1815 reg &= ~PCI113X_CBCTRL_PCI_INTR;
1816 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);
1817 break;
1818 default:
1819 break;
1820 }
1821 }
1822}
1823
1824#if defined SHOW_REGS
1825static void
1826cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt,
1827 bus_space_handle_t memh)
1828{
1829 int i;
1830 printf("PCI config regs:");
1831 for (i = 0; i < 0x50; i += 4) {
1832 if (i % 16 == 0)
1833 printf("\n 0x%02x:", i);
1834 printf(" %08x", pci_conf_read(pc, tag, i));
1835 }
1836 for (i = 0x80; i < 0xb0; i += 4) {
1837 if (i % 16 == 0)
1838 printf("\n 0x%02x:", i);
1839 printf(" %08x", pci_conf_read(pc, tag, i));
1840 }
1841
1842 if (memh == 0) {
1843 printf("\n");
1844 return;
1845 }
1846
1847 printf("\nsocket regs:");
1848 for (i = 0; i <= 0x10; i += 0x04)
1849 printf(" %08x", bus_space_read_4(memt, memh, i));
1850 printf("\nExCA regs:");
1851 for (i = 0; i < 0x08; ++i)
1852 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i));
1853 printf("\n");
1854 return;
1855}
1856#endif
1857
1858/*
1859 * static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t cc,
1860 * int busno, int function)
1861 * This is the function to make a tag to access config space of
1862 * a CardBus Card. It works same as pci_conf_read.
1863 */
1864static pcitag_t
1865pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function)
1866{
1867 struct pccbb_softc *sc = (struct pccbb_softc *)cc;
1868
1869 return pci_make_tag(sc->sc_pc, busno, 0, function);
1870}
1871
1872/*
1873 * pccbb_conf_read
1874 *
1875 * This is the function to read the config space of a CardBus card.
1876 * It works the same as pci_conf_read(9).
1877 */
1878static pcireg_t
1879pccbb_conf_read(cardbus_chipset_tag_t cc, pcitag_t tag, int offset)
1880{
1881 struct pccbb_softc *sc = (struct pccbb_softc *)cc;
1882 pcitag_t brtag = sc->sc_tag;
1883 pcireg_t reg;
1884
1885 /*
1886 * clear cardbus master abort status; it is OK to write without
1887 * reading before because all bits are r/o or w1tc
1888 */
1889 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS,
1890 CBB_SECSTATUS_CBMABORT);
1891 reg = pci_conf_read(sc->sc_pc, tag, offset);
1892 /* check cardbus master abort status */
1893 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS)
1894 & CBB_SECSTATUS_CBMABORT)
1895 return (0xffffffff);
1896 return reg;
1897}
1898
1899/*
1900 * pccbb_conf_write
1901 *
1902 * This is the function to write the config space of a CardBus
1903 * card. It works the same as pci_conf_write(9).
1904 */
1905static void
1906pccbb_conf_write(cardbus_chipset_tag_t cc, pcitag_t tag, int reg, pcireg_t val)
1907{
1908 struct pccbb_softc *sc = (struct pccbb_softc *)cc;
1909
1910 pci_conf_write(sc->sc_pc, tag, reg, val);
1911}
1912
1913#if 0
1914STATIC int
1915pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch,
1916 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask,
1917 int speed, int flags,
1918 bus_space_handle_t * iohp)
1919#endif
1920/*
1921 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch,
1922 * bus_addr_t start, bus_size_t size,
1923 * bus_size_t align,
1924 * struct pcmcia_io_handle *pcihp
1925 *
1926 * This function only allocates I/O region for pccard. This function
1927 * never maps the allocated region to pccard I/O area.
1928 *
1929 * XXX: The interface of this function is not very good, I believe.
1930 */
1931STATIC int
1932pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start,
1933 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp)
1934{
1935 struct pccbb_softc *sc = (struct pccbb_softc *)pch;
1936 bus_addr_t ioaddr;
1937 int flags = 0;
1938 bus_space_tag_t iot;
1939 bus_space_handle_t ioh;
1940 bus_addr_t mask;
1941#if rbus
1942 rbus_tag_t rb;
1943#endif
1944 if (align == 0) {
1945 align = size; /* XXX: funny??? */
1946 }
1947
1948 if (start != 0) {
1949 /* XXX: assume all card decode lower 10 bits by its hardware */
1950 mask = 0x3ff;
1951 /* enforce to use only masked address */
1952 start &= mask;
1953 } else {
1954 /*
1955 * calculate mask:
1956 * 1. get the most significant bit of size (call it msb).
1957 * 2. compare msb with the value of size.
1958 * 3. if size is larger, shift msb left once.
1959 * 4. obtain mask value to decrement msb.
1960 */
1961 bus_size_t size_tmp = size;
1962 int shifts = 0;
1963
1964 mask = 1;
1965 while (size_tmp) {
1966 ++shifts;
1967 size_tmp >>= 1;
1968 }
1969 mask = (1 << shifts);
1970 if (mask < size) {
1971 mask <<= 1;
1972 }
1973 --mask;
1974 }
1975
1976 /*
1977 * Allocate some arbitrary I/O space.
1978 */
1979
1980 iot = sc->sc_iot;
1981
1982#if rbus
1983 rb = sc->sc_rbus_iot;
1984 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) {
1985 return 1;
1986 }
1987 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n",
1988 (u_long) ioaddr, (u_long) size));
1989#else
1990 if (start) {
1991 ioaddr = start;
1992 if (bus_space_map(iot, start, size, 0, &ioh)) {
1993 return 1;
1994 }
1995 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n",
1996 (u_long) ioaddr, (u_long) size));
1997 } else {
1998 flags |= PCMCIA_IO_ALLOCATED;
1999 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ ,
2000 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */
2001 size, align, 0, 0, &ioaddr, &ioh)) {
2002 /* No room be able to be get. */
2003 return 1;
2004 }
2005 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n",
2006 (u_long) ioaddr, (u_long) size));
2007 }
2008#endif
2009
2010 pcihp->iot = iot;
2011 pcihp->ioh = ioh;
2012 pcihp->addr = ioaddr;
2013 pcihp->size = size;
2014 pcihp->flags = flags;
2015
2016 return 0;
2017}
2018
2019/*
2020 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch,
2021 * struct pcmcia_io_handle *pcihp)
2022 *
2023 * This function only frees I/O region for pccard.
2024 *
2025 * XXX: The interface of this function is not very good, I believe.
2026 */
2027void
2028pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch,
2029 struct pcmcia_io_handle *pcihp)
2030{
2031 struct pccbb_softc *sc = (struct pccbb_softc *)pch;
2032#if !rbus
2033 bus_space_tag_t iot = pcihp->iot;
2034#endif
2035 bus_space_handle_t ioh = pcihp->ioh;
2036 bus_size_t size = pcihp->size;
2037
2038#if rbus
2039 rbus_tag_t rb = sc->sc_rbus_iot;
2040
2041 rbus_space_free(rb, ioh, size, NULL);
2042#else
2043 if (pcihp->flags & PCMCIA_IO_ALLOCATED)
2044 bus_space_free(iot, ioh, size);
2045 else
2046 bus_space_unmap(iot, ioh, size);
2047#endif
2048}
2049
2050/*
2051 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width,
2052 * bus_addr_t offset, bus_size_t size,
2053 * struct pcmcia_io_handle *pcihp,
2054 * int *windowp)
2055 *
2056 * This function maps the allocated I/O region to pccard. This function
2057 * never allocates any I/O region for pccard I/O area. I don't
2058 * understand why the original authors of pcmciabus separated alloc and
2059 * map. I believe the two must be unite.
2060 *
2061 * XXX: no wait timing control?
2062 */
2063int
2064pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset,
2065 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp)
2066{
2067 struct pccbb_softc *sc = (struct pccbb_softc *)pch;
2068 struct pcic_handle *ph = &sc->sc_pcmcia_h;
2069 bus_addr_t ioaddr = pcihp->addr + offset;
2070 int i, win;
2071#if defined CBB_DEBUG
2072 static const char *width_names[] = { "dynamic", "io8", "io16" };
2073#endif
2074
2075 /* Sanity check I/O handle. */
2076
2077 if (!bus_space_is_equal(sc->sc_iot, pcihp->iot)) {
2078 panic("pccbb_pcmcia_io_map iot is bogus");
2079 }
2080
2081 /* XXX Sanity check offset/size. */
2082
2083 win = -1;
2084 for (i = 0; i < PCIC_IO_WINS; i++) {
2085 if ((ph->ioalloc & (1 << i)) == 0) {
2086 win = i;
2087 ph->ioalloc |= (1 << i);
2088 break;
2089 }
2090 }
2091
2092 if (win == -1) {
2093 return 1;
2094 }
2095
2096 *windowp = win;
2097
2098 /* XXX this is pretty gross */
2099
2100 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n",
2101 win, width_names[width], (u_long) ioaddr, (u_long) size));
2102
2103 /* XXX wtf is this doing here? */
2104
2105#if 0
2106 printf(" port 0x%lx", (u_long) ioaddr);
2107 if (size > 1) {
2108 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1);
2109 }
2110#endif
2111
2112 ph->io[win].addr = ioaddr;
2113 ph->io[win].size = size;
2114 ph->io[win].width = width;
2115
2116 /* actual dirty register-value changing in the function below. */
2117 pccbb_pcmcia_do_io_map(sc, win);
2118
2119 return 0;
2120}
2121
2122/*
2123 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win)
2124 *
2125 * This function changes register-value to map I/O region for pccard.
2126 */
2127static void
2128pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win)
2129{
2130 static u_int8_t pcic_iowidth[3] = {
2131 PCIC_IOCTL_IO0_IOCS16SRC_CARD,
2132 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
2133 PCIC_IOCTL_IO0_DATASIZE_8BIT,
2134 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
2135 PCIC_IOCTL_IO0_DATASIZE_16BIT,
2136 };
2137
2138#define PCIC_SIA_START_LOW 0
2139#define PCIC_SIA_START_HIGH 1
2140#define PCIC_SIA_STOP_LOW 2
2141#define PCIC_SIA_STOP_HIGH 3
2142
2143 int regbase_win = 0x8 + win * 0x04;
2144 u_int8_t ioctl, enable;
2145 struct pcic_handle *ph = &sc->sc_pcmcia_h;
2146
2147 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx "
2148 "width %d\n", win, (unsigned long)ph->io[win].addr,
2149 (unsigned long)ph->io[win].size, ph->io[win].width * 8));
2150
2151 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW,
2152 ph->io[win].addr & 0xff);
2153 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH,
2154 (ph->io[win].addr >> 8) & 0xff);
2155
2156 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW,
2157 (ph->io[win].addr + ph->io[win].size - 1) & 0xff);
2158 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH,
2159 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff);
2160
2161 ioctl = Pcic_read(sc, PCIC_IOCTL);
2162 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE);
2163 switch (win) {
2164 case 0:
2165 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT |
2166 PCIC_IOCTL_IO0_IOCS16SRC_MASK |
2167 PCIC_IOCTL_IO0_DATASIZE_MASK);
2168 ioctl |= pcic_iowidth[ph->io[win].width];
2169 enable |= PCIC_ADDRWIN_ENABLE_IO0;
2170 break;
2171 case 1:
2172 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT |
2173 PCIC_IOCTL_IO1_IOCS16SRC_MASK |
2174 PCIC_IOCTL_IO1_DATASIZE_MASK);
2175 ioctl |= (pcic_iowidth[ph->io[win].width] << 4);
2176 enable |= PCIC_ADDRWIN_ENABLE_IO1;
2177 break;
2178 }
2179 Pcic_write(sc, PCIC_IOCTL, ioctl);
2180 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable);
2181#if defined(CBB_DEBUG)
2182 {
2183 u_int8_t start_low =
2184 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW);
2185 u_int8_t start_high =
2186 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH);
2187 u_int8_t stop_low =
2188 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW);
2189 u_int8_t stop_high =
2190 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH);
2191 printf("pccbb_pcmcia_do_io_map start %02x %02x, "
2192 "stop %02x %02x, ioctl %02x enable %02x\n",
2193 start_low, start_high, stop_low, stop_high, ioctl, enable);
2194 }
2195#endif
2196}
2197
2198/*
2199 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win)
2200 *
2201 * This function unmaps I/O region. No return value.
2202 */
2203STATIC void
2204pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win)
2205{
2206 struct pccbb_softc *sc = (struct pccbb_softc *)pch;
2207 struct pcic_handle *ph = &sc->sc_pcmcia_h;
2208 int reg;
2209
2210 if (win >= PCIC_IO_WINS || win < 0) {
2211 panic("pccbb_pcmcia_io_unmap: window out of range");
2212 }
2213
2214 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE);
2215 switch (win) {
2216 case 0:
2217 reg &= ~PCIC_ADDRWIN_ENABLE_IO0;
2218 break;
2219 case 1:
2220 reg &= ~PCIC_ADDRWIN_ENABLE_IO1;
2221 break;
2222 }
2223 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg);
2224
2225 ph->ioalloc &= ~(1 << win);
2226}
2227
2228static int
2229pccbb_pcmcia_wait_ready(struct pccbb_softc *sc)
2230{
2231 u_int8_t stat;
2232 int i;
2233
2234 /* wait an initial 10ms for quick cards */
2235 stat = Pcic_read(sc, PCIC_IF_STATUS);
2236 if (stat & PCIC_IF_STATUS_READY)
2237 return (0);
2238 pccbb_pcmcia_delay(sc, 10, "pccwr0");
2239 for (i = 0; i < 50; i++) {
2240 stat = Pcic_read(sc, PCIC_IF_STATUS);
2241 if (stat & PCIC_IF_STATUS_READY)
2242 return (0);
2243 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) !=
2244 PCIC_IF_STATUS_CARDDETECT_PRESENT)
2245 return (ENXIO);
2246 /* wait .1s (100ms) each iteration now */
2247 pccbb_pcmcia_delay(sc, 100, "pccwr1");
2248 }
2249
2250 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n",
2251 stat);
2252 return (EWOULDBLOCK);
2253}
2254
2255/*
2256 * Perform long (msec order) delay. timo is in milliseconds.
2257 */
2258static void
2259pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg)
2260{
2261#ifdef DIAGNOSTIC
2262 if (timo <= 0)
2263 panic("pccbb_pcmcia_delay: called with timeout %d", timo);
2264 if (!curlwp)
2265 panic("pccbb_pcmcia_delay: called in interrupt context");
2266#endif
2267 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo));
2268 kpause(wmesg, false, max(mstohz(timo), 1), NULL);
2269}
2270
2271/*
2272 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch)
2273 *
2274 * This function enables the card. All information is stored in
2275 * the first argument, pcmcia_chipset_handle_t.
2276 */
2277STATIC void
2278pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch)
2279{
2280 struct pccbb_softc *sc = (struct pccbb_softc *)pch;
2281 struct pcic_handle *ph = &sc->sc_pcmcia_h;
2282 pcireg_t spsr;
2283 int voltage;
2284 int win;
2285 u_int8_t power, intr;
2286#ifdef DIAGNOSTIC
2287 int reg;
2288#endif
2289
2290 /* this bit is mostly stolen from pcic_attach_card */
2291
2292 DPRINTF(("pccbb_pcmcia_socket_enable: "));
2293
2294 /* get card Vcc info */
2295 spsr =
2296 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
2297 CB_SOCKET_STAT);
2298 if (spsr & CB_SOCKET_STAT_5VCARD) {
2299 DPRINTF(("5V card\n"));
2300 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC;
2301 } else if (spsr & CB_SOCKET_STAT_3VCARD) {
2302 DPRINTF(("3V card\n"));
2303 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC;
2304 } else {
2305 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */
2306 return;
2307 }
2308
2309 /* disable interrupts; assert RESET */
2310 intr = Pcic_read(sc, PCIC_INTR);
2311 intr &= PCIC_INTR_ENABLE;
2312 Pcic_write(sc, PCIC_INTR, intr);
2313
2314 /* zero out the address windows */
2315 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0);
2316
2317 /* power down the socket to reset it, clear the card reset pin */
2318 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
2319
2320 /* power off; assert output enable bit */
2321 power = PCIC_PWRCTL_OE;
2322 Pcic_write(sc, PCIC_PWRCTL, power);
2323
2324 /* power up the socket */
2325 if (pccbb_power(sc, voltage) == 0)
2326 return;
2327
2328 /*
2329 * Table 4-18 and figure 4-6 of the PC Card specifiction say:
2330 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above)
2331 * RESET Width (Th (Hi-z RESET)) = 1ms
2332 * RESET Width (Tw (RESET)) = 10us
2333 *
2334 * some machines require some more time to be settled
2335 * for example old toshiba topic bridges!
2336 * (100ms is added here).
2337 */
2338 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1");
2339
2340 /* negate RESET */
2341 intr |= PCIC_INTR_RESET;
2342 Pcic_write(sc, PCIC_INTR, intr);
2343
2344 /*
2345 * RESET Setup Time (Tsu (RESET)) = 20ms
2346 */
2347 pccbb_pcmcia_delay(sc, 20, "pccen2");
2348
2349#ifdef DIAGNOSTIC
2350 reg = Pcic_read(sc, PCIC_IF_STATUS);
2351 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0)
2352 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n",
2353 reg);
2354#endif
2355
2356 /* wait for the chip to finish initializing */
2357 if (pccbb_pcmcia_wait_ready(sc)) {
2358#ifdef DIAGNOSTIC
2359 printf("pccbb_pcmcia_socket_enable: never became ready\n");
2360#endif
2361 /* XXX return a failure status?? */
2362 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
2363 Pcic_write(sc, PCIC_PWRCTL, 0);
2364 return;
2365 }
2366
2367 /* reinstall all the memory and io mappings */
2368 for (win = 0; win < PCIC_MEM_WINS; ++win)
2369 if (ph->memalloc & (1 << win))
2370 pccbb_pcmcia_do_mem_map(sc, win);
2371 for (win = 0; win < PCIC_IO_WINS; ++win)
2372 if (ph->ioalloc & (1 << win))
2373 pccbb_pcmcia_do_io_map(sc, win);
2374}
2375
2376/*
2377 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph)
2378 *
2379 * This function disables the card. All information is stored in
2380 * the first argument, pcmcia_chipset_handle_t.
2381 */
2382STATIC void
2383pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch)
2384{
2385 struct pccbb_softc *sc = (struct pccbb_softc *)pch;
2386 u_int8_t intr;
2387
2388 DPRINTF(("pccbb_pcmcia_socket_disable\n"));
2389
2390 /* disable interrupts; assert RESET */
2391 intr = Pcic_read(sc, PCIC_INTR);
2392 intr &= PCIC_INTR_ENABLE;
2393 Pcic_write(sc, PCIC_INTR, intr);
2394
2395 /* zero out the address windows */
2396 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0);
2397
2398 /* power down the socket to reset it, clear the card reset pin */
2399 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
2400
2401 /* disable socket: negate output enable bit and power off */
2402 Pcic_write(sc, PCIC_PWRCTL, 0);
2403
2404 /*
2405 * Vcc Falling Time (Tpf) = 300ms
2406 */
2407 pccbb_pcmcia_delay(sc, 300, "pccwr1");
2408}
2409
2410STATIC void
2411pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type)
2412{
2413 struct pccbb_softc *sc = (struct pccbb_softc *)pch;
2414 u_int8_t intr;
2415
2416 /* set the card type */
2417
2418 intr = Pcic_read(sc, PCIC_INTR);
2419 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK);
2420 if (type == PCMCIA_IFTYPE_IO)
2421 intr |= PCIC_INTR_CARDTYPE_IO;
2422 else
2423 intr |= PCIC_INTR_CARDTYPE_MEM;
2424 Pcic_write(sc, PCIC_INTR, intr);
2425
2426 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n",
2427 device_xname(sc->sc_dev),
2428 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr));
2429}
2430
2431/*
2432 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph)
2433 *
2434 * This function detects whether a card is in the slot or not.
2435 * If a card is inserted, return 1. Otherwise, return 0.
2436 */
2437STATIC int
2438pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch)
2439{
2440 struct pccbb_softc *sc = (struct pccbb_softc *)pch;
2441
2442 DPRINTF(("pccbb_pcmcia_card_detect\n"));
2443 return pccbb_detect_card(sc) == 1 ? 1 : 0;
2444}
2445
2446#if 0
2447STATIC int
2448pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch,
2449 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags,
2450 bus_space_tag_t * memtp bus_space_handle_t * memhp)
2451#endif
2452/*
2453 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch,
2454 * bus_size_t size,
2455 * struct pcmcia_mem_handle *pcmhp)
2456 *
2457 * This function only allocates memory region for pccard. This
2458 * function never maps the allocated region to pccard memory area.
2459 *
2460 * XXX: Why the argument of start address is not in?
2461 */
2462STATIC int
2463pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size,
2464 struct pcmcia_mem_handle *pcmhp)
2465{
2466 struct pccbb_softc *sc = (struct pccbb_softc *)pch;
2467 bus_space_handle_t memh;
2468 bus_addr_t addr;
2469 bus_size_t sizepg;
2470#if rbus
2471 rbus_tag_t rb;
2472#endif
2473
2474 /* Check that the card is still there. */
2475 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) !=
2476 PCIC_IF_STATUS_CARDDETECT_PRESENT)
2477 return 1;
2478
2479 /* out of sc->memh, allocate as many pages as necessary */
2480
2481 /* convert size to PCIC pages */
2482 /*
2483 * This is not enough; when the requested region is on the page
2484 * boundaries, this may calculate wrong result.
2485 */
2486 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE;
2487#if 0
2488 if (sizepg > PCIC_MAX_MEM_PAGES) {
2489 return 1;
2490 }
2491#endif
2492
2493 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) {
2494 return 1;
2495 }
2496
2497 addr = 0; /* XXX gcc -Wuninitialized */
2498
2499#if rbus
2500 rb = sc->sc_rbus_memt;
2501 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE,
2502 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0,
2503 &addr, &memh)) {
2504 return 1;
2505 }
2506#else
2507 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end,
2508 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE,
2509 0, /* boundary */
2510 0, /* flags */
2511 &addr, &memh)) {
2512 return 1;
2513 }
2514#endif
2515
2516 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, "
2517 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size,
2518 (unsigned long)sizepg * PCIC_MEM_PAGESIZE));
2519
2520 pcmhp->memt = sc->sc_memt;
2521 pcmhp->memh = memh;
2522 pcmhp->addr = addr;
2523 pcmhp->size = size;
2524 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE;
2525 /* What is mhandle? I feel it is very dirty and it must go trush. */
2526 pcmhp->mhandle = 0;
2527 /* No offset??? Funny. */
2528
2529 return 0;
2530}
2531
2532/*
2533 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch,
2534 * struct pcmcia_mem_handle *pcmhp)
2535 *
2536 * This function release the memory space allocated by the function
2537 * pccbb_pcmcia_mem_alloc().
2538 */
2539STATIC void
2540pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch,
2541 struct pcmcia_mem_handle *pcmhp)
2542{
2543#if rbus
2544 struct pccbb_softc *sc = (struct pccbb_softc *)pch;
2545
2546 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL);
2547#else
2548 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize);
2549#endif
2550}
2551
2552/*
2553 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win)
2554 *
2555 * This function release the memory space allocated by the function
2556 * pccbb_pcmcia_mem_alloc().
2557 */
2558STATIC void
2559pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win)
2560{
2561 int regbase_win;
2562 bus_addr_t phys_addr;
2563 bus_addr_t phys_end;
2564 struct pcic_handle *ph = &sc->sc_pcmcia_h;
2565
2566#define PCIC_SMM_START_LOW 0
2567#define PCIC_SMM_START_HIGH 1
2568#define PCIC_SMM_STOP_LOW 2
2569#define PCIC_SMM_STOP_HIGH 3
2570#define PCIC_CMA_LOW 4
2571#define PCIC_CMA_HIGH 5
2572
2573 u_int8_t start_low, start_high = 0;
2574 u_int8_t stop_low, stop_high;
2575 u_int8_t off_low, off_high;
2576 u_int8_t mem_window;
2577 int reg;
2578
2579 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK;
2580 int mem8 =
2581 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8
2582 || (kind == PCMCIA_MEM_ATTR);
2583
2584 regbase_win = 0x10 + win * 0x08;
2585
2586 phys_addr = ph->mem[win].addr;
2587 phys_end = phys_addr + ph->mem[win].size;
2588
2589 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n",
2590 (unsigned long)phys_addr, (unsigned long)phys_end,
2591 (unsigned long)ph->mem[win].offset));
2592
2593#define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT
2594#define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8)
2595#define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12)
2596
2597 /* bit 19:12 */
2598 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff;
2599 /* bit 23:20 and bit 7 on */
2600 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f)
2601 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT);
2602 /* bit 31:24, for 32-bit address */
2603 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff;
2604
2605 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low);
2606 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high);
2607
2608 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) {
2609 Pcic_write(sc, 0x40 + win, mem_window);
2610 }
2611
2612 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff;
2613 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f)
2614 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */
2615 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */
2616
2617 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low);
2618 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high);
2619
2620 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff;
2621 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8))
2622 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK)
2623 | ((kind == PCMCIA_MEM_ATTR) ?
2624 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0);
2625
2626 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low);
2627 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high);
2628
2629 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE);
2630 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16);
2631 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg);
2632
2633#if defined(CBB_DEBUG)
2634 {
2635 int r1, r2, r3, r4, r5, r6, r7 = 0;
2636
2637 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW);
2638 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH);
2639 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW);
2640 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH);
2641 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW);
2642 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH);
2643 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) {
2644 r7 = Pcic_read(sc, 0x40 + win);
2645 }
2646
2647 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x "
2648 "%02x%02x", win, r1, r2, r3, r4, r5, r6);
2649 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) {
2650 printf(" %02x", r7);
2651 }
2652 printf("\n");
2653 }
2654#endif
2655}
2656
2657/*
2658 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind,
2659 * bus_addr_t card_addr, bus_size_t size,
2660 * struct pcmcia_mem_handle *pcmhp,
2661 * bus_addr_t *offsetp, int *windowp)
2662 *
2663 * This function maps memory space allocated by the function
2664 * pccbb_pcmcia_mem_alloc().
2665 */
2666STATIC int
2667pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind,
2668 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp,
2669 bus_size_t *offsetp, int *windowp)
2670{
2671 struct pccbb_softc *sc = (struct pccbb_softc *)pch;
2672 struct pcic_handle *ph = &sc->sc_pcmcia_h;
2673 bus_addr_t busaddr;
2674 long card_offset;
2675 int win;
2676
2677 /* Check that the card is still there. */
2678 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) !=
2679 PCIC_IF_STATUS_CARDDETECT_PRESENT)
2680 return 1;
2681
2682 for (win = 0; win < PCIC_MEM_WINS; ++win) {
2683 if ((ph->memalloc & (1 << win)) == 0) {
2684 ph->memalloc |= (1 << win);
2685 break;
2686 }
2687 }
2688
2689 if (win == PCIC_MEM_WINS) {
2690 return 1;
2691 }
2692
2693 *windowp = win;
2694
2695 /* XXX this is pretty gross */
2696
2697 if (!bus_space_is_equal(sc->sc_memt, pcmhp->memt)) {
2698 panic("pccbb_pcmcia_mem_map memt is bogus");
2699 }
2700
2701 busaddr = pcmhp->addr;
2702
2703 /*
2704 * compute the address offset to the pcmcia address space for the
2705 * pcic. this is intentionally signed. The masks and shifts below
2706 * will cause TRT to happen in the pcic registers. Deal with making
2707 * sure the address is aligned, and return the alignment offset.
2708 */
2709
2710 *offsetp = card_addr % PCIC_MEM_PAGESIZE;
2711 card_addr -= *offsetp;
2712
2713 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr "
2714 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size,
2715 (u_long) card_addr));
2716
2717 /*
2718 * include the offset in the size, and decrement size by one, since
2719 * the hw wants start/stop
2720 */
2721 size += *offsetp - 1;
2722
2723 card_offset = (((long)card_addr) - ((long)busaddr));
2724
2725 ph->mem[win].addr = busaddr;
2726 ph->mem[win].size = size;
2727 ph->mem[win].offset = card_offset;
2728 ph->mem[win].kind = kind;
2729
2730 pccbb_pcmcia_do_mem_map(sc, win);
2731
2732 return 0;
2733}
2734
2735/*
2736 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch,
2737 * int window)
2738 *
2739 * This function unmaps memory space which mapped by the function
2740 * pccbb_pcmcia_mem_map().
2741 */
2742STATIC void
2743pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window)
2744{
2745 struct pccbb_softc *sc = (struct pccbb_softc *)pch;
2746 struct pcic_handle *ph = &sc->sc_pcmcia_h;
2747 int reg;
2748
2749 if (window >= PCIC_MEM_WINS) {
2750 panic("pccbb_pcmcia_mem_unmap: window out of range");
2751 }
2752
2753 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE);
2754 reg &= ~(1 << window);
2755 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg);
2756
2757 ph->memalloc &= ~(1 << window);
2758}
2759
2760/*
2761 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch,
2762 * struct pcmcia_function *pf,
2763 * int ipl,
2764 * int (*func)(void *),
2765 * void *arg);
2766 *
2767 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line.
2768 */
2769STATIC void *
2770pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch,
2771 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg)
2772{
2773 struct pccbb_softc *sc = (struct pccbb_softc *)pch;
2774
2775 if (!(pf->cfe->flags & (PCMCIA_CFE_IRQLEVEL|PCMCIA_CFE_IRQPULSE))) {
2776 /*
2777 * XXX Noooooo! The interrupt flag must set properly!!
2778 * dumb pcmcia driver!!
2779 */
2780 DPRINTF(("%s does not provide edge nor pulse interrupt\n",
2781 device_xname(sc->sc_dev)));
2782 return NULL;
2783 }
2784
2785 return pccbb_intr_establish(sc, ipl, func, arg);
2786}
2787
2788/*
2789 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch,
2790 * void *ih)
2791 *
2792 * This function disables PC-Card interrupt.
2793 */
2794STATIC void
2795pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih)
2796{
2797 struct pccbb_softc *sc = (struct pccbb_softc *)pch;
2798
2799 pccbb_intr_disestablish(sc, ih);
2800}
2801
2802#if rbus
2803/*
2804 * static int
2805 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb,
2806 * bus_addr_t addr, bus_size_t size,
2807 * bus_addr_t mask, bus_size_t align,
2808 * int flags, bus_addr_t *addrp;
2809 * bus_space_handle_t *bshp)
2810 *
2811 * This function allocates a portion of memory or io space for
2812 * clients. This function is called from CardBus card drivers.
2813 */
2814static int
2815pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb,
2816 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align,
2817 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp)
2818{
2819 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
2820
2821 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, "
2822 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr,
2823 (unsigned long)size, (unsigned long)mask, (unsigned long)align));
2824
2825 if (align == 0) {
2826 align = size;
2827 }
2828
2829 if (bus_space_is_equal(rb->rb_bt, sc->sc_memt)) {
2830 if (align < 16) {
2831 return 1;
2832 }
2833 /*
2834 * XXX: align more than 0x1000 to avoid overwrapping
2835 * memory windows for two or more devices. 0x1000
2836 * means memory window's granularity.
2837 *
2838 * Two or more devices should be able to share same
2839 * memory window region. However, overrapping memory
2840 * window is not good because some devices, such as
2841 * 3Com 3C575[BC], have a broken address decoder and
2842 * intrude other's memory region.
2843 */
2844 if (align < 0x1000) {
2845 align = 0x1000;
2846 }
2847 } else if (bus_space_is_equal(rb->rb_bt, sc->sc_iot)) {
2848 if (align < 4) {
2849 return 1;
2850 }
2851 /* XXX: hack for avoiding ISA image */
2852 if (mask < 0x0100) {
2853 mask = 0x3ff;
2854 addr = 0x300;
2855 }
2856
2857 } else {
2858 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is "
2859 "NOT used. io: 0x%lx, mem: 0x%lx\n",
2860 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot,
2861 (unsigned long)sc->sc_memt));
2862 return 1;
2863 /* XXX: panic here? */
2864 }
2865
2866 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) {
2867 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n");
2868 return 1;
2869 }
2870
2871 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0);
2872
2873 return 0;
2874}
2875
2876/*
2877 * static int
2878 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb,
2879 * bus_space_handle_t *bshp, bus_size_t size);
2880 *
2881 * This function is called from CardBus card drivers.
2882 */
2883static int
2884pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb,
2885 bus_space_handle_t bsh, bus_size_t size)
2886{
2887 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
2888 bus_space_tag_t bt = rb->rb_bt;
2889
2890 pccbb_close_win(sc, bt, bsh, size);
2891
2892 if (bus_space_is_equal(bt, sc->sc_memt)) {
2893 } else if (bus_space_is_equal(bt, sc->sc_iot)) {
2894 } else {
2895 return 1;
2896 /* XXX: panic here? */
2897 }
2898
2899 return rbus_space_free(rb, bsh, size, NULL);
2900}
2901#endif /* rbus */
2902
2903#if rbus
2904
2905static int
2906pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr,
2907 bus_size_t size, bus_space_handle_t bsh, int flags)
2908{
2909 struct pccbb_win_chain_head *head;
2910 bus_addr_t align;
2911
2912 head = &sc->sc_iowindow;
2913 align = 0x04;
2914 if (bus_space_is_equal(sc->sc_memt, bst)) {
2915 head = &sc->sc_memwindow;
2916 align = 0x1000;
2917 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n",
2918 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt,
2919 (unsigned long)bst));
2920 }
2921
2922 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) {
2923 aprint_error_dev(sc->sc_dev,
2924 "pccbb_open_win: %s winlist insert failed\n",
2925 (head == &sc->sc_memwindow) ? "mem" : "io");
2926 }
2927 pccbb_winset(align, sc, bst);
2928
2929 return 0;
2930}
2931
2932static int
2933pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst,
2934 bus_space_handle_t bsh, bus_size_t size)
2935{
2936 struct pccbb_win_chain_head *head;
2937 bus_addr_t align;
2938
2939 head = &sc->sc_iowindow;
2940 align = 0x04;
2941 if (bus_space_is_equal(sc->sc_memt, bst)) {
2942 head = &sc->sc_memwindow;
2943 align = 0x1000;
2944 }
2945
2946 if (pccbb_winlist_delete(head, bsh, size)) {
2947 aprint_error_dev(sc->sc_dev,
2948 "pccbb_close_win: %s winlist delete failed\n",
2949 (head == &sc->sc_memwindow) ? "mem" : "io");
2950 }
2951 pccbb_winset(align, sc, bst);
2952
2953 return 0;
2954}
2955
2956static int
2957pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start,
2958 bus_size_t size, bus_space_handle_t bsh, int flags)
2959{
2960 struct pccbb_win_chain *chainp, *elem;
2961
2962 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF,
2963 M_NOWAIT)) == NULL)
2964 return (1); /* fail */
2965
2966 elem->wc_start = start;
2967 elem->wc_end = start + (size - 1);
2968 elem->wc_handle = bsh;
2969 elem->wc_flags = flags;
2970
2971 TAILQ_FOREACH(chainp, head, wc_list) {
2972 if (chainp->wc_end >= start)
2973 break;
2974 }
2975 if (chainp != NULL)
2976 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list);
2977 else
2978 TAILQ_INSERT_TAIL(head, elem, wc_list);
2979 return (0);
2980}
2981
2982static int
2983pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh,
2984 bus_size_t size)
2985{
2986 struct pccbb_win_chain *chainp;
2987
2988 TAILQ_FOREACH(chainp, head, wc_list) {
2989 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0)
2990 break;
2991 }
2992 if (chainp == NULL)
2993 return 1; /* fail: no candidate to remove */
2994
2995 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) {
2996 printf("pccbb_winlist_delete: window 0x%lx size "
2997 "inconsistent: 0x%lx, 0x%lx\n",
2998 (unsigned long)chainp->wc_start,
2999 (unsigned long)(chainp->wc_end - chainp->wc_start),
3000 (unsigned long)(size - 1));
3001 return 1;
3002 }
3003
3004 TAILQ_REMOVE(head, chainp, wc_list);
3005 free(chainp, M_DEVBUF);
3006
3007 return 0;
3008}
3009
3010static void
3011pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst)
3012{
3013 pci_chipset_tag_t pc;
3014 pcitag_t tag;
3015 bus_addr_t mask = ~(align - 1);
3016 struct {
3017 pcireg_t win_start;
3018 pcireg_t win_limit;
3019 int win_flags;
3020 } win[2];
3021 struct pccbb_win_chain *chainp;
3022 int offs;
3023
3024 win[0].win_start = win[1].win_start = 0xffffffff;
3025 win[0].win_limit = win[1].win_limit = 0;
3026 win[0].win_flags = win[1].win_flags = 0;
3027
3028 chainp = TAILQ_FIRST(&sc->sc_iowindow);
3029 offs = PCI_CB_IOBASE0;
3030 if (bus_space_is_equal(sc->sc_memt, bst)) {
3031 chainp = TAILQ_FIRST(&sc->sc_memwindow);
3032 offs = PCI_CB_MEMBASE0;
3033 }
3034
3035 if (chainp != NULL) {
3036 win[0].win_start = chainp->wc_start & mask;
3037 win[0].win_limit = chainp->wc_end & mask;
3038 win[0].win_flags = chainp->wc_flags;
3039 chainp = TAILQ_NEXT(chainp, wc_list);
3040 }
3041
3042 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) {
3043 if (win[1].win_start == 0xffffffff) {
3044 /* window 1 is not used */
3045 if ((win[0].win_flags == chainp->wc_flags) &&
3046 (win[0].win_limit + align >=
3047 (chainp->wc_start & mask))) {
3048 /* concatenate */
3049 win[0].win_limit = chainp->wc_end & mask;
3050 } else {
3051 /* make new window */
3052 win[1].win_start = chainp->wc_start & mask;
3053 win[1].win_limit = chainp->wc_end & mask;
3054 win[1].win_flags = chainp->wc_flags;
3055 }
3056 continue;
3057 }
3058
3059 /* Both windows are engaged. */
3060 if (win[0].win_flags == win[1].win_flags) {
3061 /* same flags */
3062 if (win[0].win_flags == chainp->wc_flags) {
3063 if (win[1].win_start - (win[0].win_limit +
3064 align) <
3065 (chainp->wc_start & mask) -
3066 ((chainp->wc_end & mask) + align)) {
3067 /*
3068 * merge window 0 and 1, and set win1
3069 * to chainp
3070 */
3071 win[0].win_limit = win[1].win_limit;
3072 win[1].win_start =
3073 chainp->wc_start & mask;
3074 win[1].win_limit =
3075 chainp->wc_end & mask;
3076 } else {
3077 win[1].win_limit =
3078 chainp->wc_end & mask;
3079 }
3080 } else {
3081 /* different flags */
3082
3083 /* concatenate win0 and win1 */
3084 win[0].win_limit = win[1].win_limit;
3085 /* allocate win[1] to new space */
3086 win[1].win_start = chainp->wc_start & mask;
3087 win[1].win_limit = chainp->wc_end & mask;
3088 win[1].win_flags = chainp->wc_flags;
3089 }
3090 } else {
3091 /* the flags of win[0] and win[1] is different */
3092 if (win[0].win_flags == chainp->wc_flags) {
3093 win[0].win_limit = chainp->wc_end & mask;
3094 /*
3095 * XXX this creates overlapping windows, so
3096 * what should the poor bridge do if one is
3097 * cachable, and the other is not?
3098 */
3099 aprint_error_dev(sc->sc_dev,
3100 "overlapping windows\n");
3101 } else {
3102 win[1].win_limit = chainp->wc_end & mask;
3103 }
3104 }
3105 }
3106
3107 pc = sc->sc_pc;
3108 tag = sc->sc_tag;
3109 pci_conf_write(pc, tag, offs, win[0].win_start);
3110 pci_conf_write(pc, tag, offs + 4, win[0].win_limit);
3111 pci_conf_write(pc, tag, offs + 8, win[1].win_start);
3112 pci_conf_write(pc, tag, offs + 12, win[1].win_limit);
3113 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n",
3114 (unsigned long)pci_conf_read(pc, tag, offs),
3115 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align,
3116 (unsigned long)pci_conf_read(pc, tag, offs + 8),
3117 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align));
3118
3119 if (bus_space_is_equal(bst, sc->sc_memt)) {
3120 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG);
3121
3122 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1);
3123 if (win[0].win_flags & PCCBB_MEM_CACHABLE)
3124 bcr |= CB_BCR_PREFETCH_MEMWIN0;
3125 if (win[1].win_flags & PCCBB_MEM_CACHABLE)
3126 bcr |= CB_BCR_PREFETCH_MEMWIN1;
3127 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr);
3128 }
3129}
3130
3131#endif /* rbus */
3132
3133static bool
3134pccbb_suspend(device_t dv, const pmf_qual_t *qual)
3135{
3136 struct pccbb_softc *sc = device_private(dv);
3137 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */
3138 bus_space_handle_t base_memh = sc->sc_base_memh;
3139 pcireg_t reg;
3140
3141 if (sc->sc_pil_intr_enable)
3142 (void)pccbbintr_function(sc);
3143 sc->sc_pil_intr_enable = false;
3144
3145 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK);
3146 /* Disable interrupts. */
3147 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER);
3148 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg);
3149 /* XXX joerg Disable power to the socket? */
3150
3151 /* XXX flush PCI write */
3152 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT);
3153
3154 /* reset interrupt */
3155 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT,
3156 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT));
3157 /* XXX flush PCI write */
3158 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT);
3159
3160 if (sc->sc_ih != NULL) {
3161 pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
3162 sc->sc_ih = NULL;
3163 }
3164
3165 return true;
3166}
3167
3168static bool
3169pccbb_resume(device_t dv, const pmf_qual_t *qual)
3170{
3171 struct pccbb_softc *sc = device_private(dv);
3172 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */
3173 bus_space_handle_t base_memh = sc->sc_base_memh;
3174 pcireg_t reg;
3175
3176 pccbb_chipinit(sc);
3177 pccbb_intrinit(sc);
3178 /* setup memory and io space window for CB */
3179 pccbb_winset(0x1000, sc, sc->sc_memt);
3180 pccbb_winset(0x04, sc, sc->sc_iot);
3181
3182 /* CSC Interrupt: Card detect interrupt on */
3183 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK);
3184 /* Card detect intr is turned on. */
3185 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER;
3186 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg);
3187 /* reset interrupt */
3188 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT);
3189 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg);
3190
3191 /*
3192 * check for card insertion or removal during suspend period.
3193 * XXX: the code can't cope with card swap (remove then
3194 * insert). how can we detect such situation?
3195 */
3196 (void)pccbbintr(sc);
3197
3198 sc->sc_pil_intr_enable = true;
3199
3200 return true;
3201}
3202