1/* $NetBSD: rtl8169.c,v 1.147 2016/06/10 13:27:13 ozaki-r Exp $ */
2
3/*
4 * Copyright (c) 1997, 1998-2003
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <sys/cdefs.h>
36__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.147 2016/06/10 13:27:13 ozaki-r Exp $");
37/* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */
38
39/*
40 * RealTek 8139C+/8169/8169S/8168/8110S PCI NIC driver
41 *
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
44 * Wind River Systems
45 */
46
47/*
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * six devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168 and the RTL8111.
52 *
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
57 *
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
60 * any byte boundary.
61 *
62 * o 64-bit DMA
63 *
64 * o TCP/IP checksum offload for both RX and TX
65 *
66 * o High and normal priority transmit DMA rings
67 *
68 * o VLAN tag insertion and extraction
69 *
70 * o TCP large send (segmentation offload)
71 *
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
75 * chips.
76 *
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
80 *
81 * o 1000Mbps mode
82 *
83 * o Jumbo frames
84 *
85 * o GMII and TBI ports/registers for interfacing with copper
86 * or fiber PHYs
87 *
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
90 *
91 * o Slight differences in register layout from the 8139C+
92 *
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
97 * copper gigE PHY.
98 *
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
104 *
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7.5K, so the max MTU possible with this
111 * driver is 7500 bytes.
112 */
113
114
115#include <sys/param.h>
116#include <sys/endian.h>
117#include <sys/systm.h>
118#include <sys/sockio.h>
119#include <sys/mbuf.h>
120#include <sys/malloc.h>
121#include <sys/kernel.h>
122#include <sys/socket.h>
123#include <sys/device.h>
124
125#include <net/if.h>
126#include <net/if_arp.h>
127#include <net/if_dl.h>
128#include <net/if_ether.h>
129#include <net/if_media.h>
130#include <net/if_vlanvar.h>
131
132#include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */
133#include <netinet/in.h> /* XXX for IP_MAXPACKET */
134#include <netinet/ip.h> /* XXX for IP_MAXPACKET */
135
136#include <net/bpf.h>
137#include <sys/rndsource.h>
138
139#include <sys/bus.h>
140
141#include <dev/mii/mii.h>
142#include <dev/mii/miivar.h>
143
144#include <dev/ic/rtl81x9reg.h>
145#include <dev/ic/rtl81x9var.h>
146
147#include <dev/ic/rtl8169var.h>
148
149static inline void re_set_bufaddr(struct re_desc *, bus_addr_t);
150
151static int re_newbuf(struct rtk_softc *, int, struct mbuf *);
152static int re_rx_list_init(struct rtk_softc *);
153static int re_tx_list_init(struct rtk_softc *);
154static void re_rxeof(struct rtk_softc *);
155static void re_txeof(struct rtk_softc *);
156static void re_tick(void *);
157static void re_start(struct ifnet *);
158static int re_ioctl(struct ifnet *, u_long, void *);
159static int re_init(struct ifnet *);
160static void re_stop(struct ifnet *, int);
161static void re_watchdog(struct ifnet *);
162
163static int re_enable(struct rtk_softc *);
164static void re_disable(struct rtk_softc *);
165
166static int re_gmii_readreg(device_t, int, int);
167static void re_gmii_writereg(device_t, int, int, int);
168
169static int re_miibus_readreg(device_t, int, int);
170static void re_miibus_writereg(device_t, int, int, int);
171static void re_miibus_statchg(struct ifnet *);
172
173static void re_reset(struct rtk_softc *);
174
175static inline void
176re_set_bufaddr(struct re_desc *d, bus_addr_t addr)
177{
178
179 d->re_bufaddr_lo = htole32((uint32_t)addr);
180 if (sizeof(bus_addr_t) == sizeof(uint64_t))
181 d->re_bufaddr_hi = htole32((uint64_t)addr >> 32);
182 else
183 d->re_bufaddr_hi = 0;
184}
185
186static int
187re_gmii_readreg(device_t dev, int phy, int reg)
188{
189 struct rtk_softc *sc = device_private(dev);
190 uint32_t rval;
191 int i;
192
193 if (phy != 7)
194 return 0;
195
196 /* Let the rgephy driver read the GMEDIASTAT register */
197
198 if (reg == RTK_GMEDIASTAT) {
199 rval = CSR_READ_1(sc, RTK_GMEDIASTAT);
200 return rval;
201 }
202
203 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16);
204 DELAY(1000);
205
206 for (i = 0; i < RTK_TIMEOUT; i++) {
207 rval = CSR_READ_4(sc, RTK_PHYAR);
208 if (rval & RTK_PHYAR_BUSY)
209 break;
210 DELAY(100);
211 }
212
213 if (i == RTK_TIMEOUT) {
214 printf("%s: PHY read failed\n", device_xname(sc->sc_dev));
215 return 0;
216 }
217
218 return rval & RTK_PHYAR_PHYDATA;
219}
220
221static void
222re_gmii_writereg(device_t dev, int phy, int reg, int data)
223{
224 struct rtk_softc *sc = device_private(dev);
225 uint32_t rval;
226 int i;
227
228 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) |
229 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY);
230 DELAY(1000);
231
232 for (i = 0; i < RTK_TIMEOUT; i++) {
233 rval = CSR_READ_4(sc, RTK_PHYAR);
234 if (!(rval & RTK_PHYAR_BUSY))
235 break;
236 DELAY(100);
237 }
238
239 if (i == RTK_TIMEOUT) {
240 printf("%s: PHY write reg %x <- %x failed\n",
241 device_xname(sc->sc_dev), reg, data);
242 }
243}
244
245static int
246re_miibus_readreg(device_t dev, int phy, int reg)
247{
248 struct rtk_softc *sc = device_private(dev);
249 uint16_t rval = 0;
250 uint16_t re8139_reg = 0;
251 int s;
252
253 s = splnet();
254
255 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
256 rval = re_gmii_readreg(dev, phy, reg);
257 splx(s);
258 return rval;
259 }
260
261 /* Pretend the internal PHY is only at address 0 */
262 if (phy) {
263 splx(s);
264 return 0;
265 }
266 switch (reg) {
267 case MII_BMCR:
268 re8139_reg = RTK_BMCR;
269 break;
270 case MII_BMSR:
271 re8139_reg = RTK_BMSR;
272 break;
273 case MII_ANAR:
274 re8139_reg = RTK_ANAR;
275 break;
276 case MII_ANER:
277 re8139_reg = RTK_ANER;
278 break;
279 case MII_ANLPAR:
280 re8139_reg = RTK_LPAR;
281 break;
282 case MII_PHYIDR1:
283 case MII_PHYIDR2:
284 splx(s);
285 return 0;
286 /*
287 * Allow the rlphy driver to read the media status
288 * register. If we have a link partner which does not
289 * support NWAY, this is the register which will tell
290 * us the results of parallel detection.
291 */
292 case RTK_MEDIASTAT:
293 rval = CSR_READ_1(sc, RTK_MEDIASTAT);
294 splx(s);
295 return rval;
296 default:
297 printf("%s: bad phy register\n", device_xname(sc->sc_dev));
298 splx(s);
299 return 0;
300 }
301 rval = CSR_READ_2(sc, re8139_reg);
302 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) {
303 /* 8139C+ has different bit layout. */
304 rval &= ~(BMCR_LOOP | BMCR_ISO);
305 }
306 splx(s);
307 return rval;
308}
309
310static void
311re_miibus_writereg(device_t dev, int phy, int reg, int data)
312{
313 struct rtk_softc *sc = device_private(dev);
314 uint16_t re8139_reg = 0;
315 int s;
316
317 s = splnet();
318
319 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
320 re_gmii_writereg(dev, phy, reg, data);
321 splx(s);
322 return;
323 }
324
325 /* Pretend the internal PHY is only at address 0 */
326 if (phy) {
327 splx(s);
328 return;
329 }
330 switch (reg) {
331 case MII_BMCR:
332 re8139_reg = RTK_BMCR;
333 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) {
334 /* 8139C+ has different bit layout. */
335 data &= ~(BMCR_LOOP | BMCR_ISO);
336 }
337 break;
338 case MII_BMSR:
339 re8139_reg = RTK_BMSR;
340 break;
341 case MII_ANAR:
342 re8139_reg = RTK_ANAR;
343 break;
344 case MII_ANER:
345 re8139_reg = RTK_ANER;
346 break;
347 case MII_ANLPAR:
348 re8139_reg = RTK_LPAR;
349 break;
350 case MII_PHYIDR1:
351 case MII_PHYIDR2:
352 splx(s);
353 return;
354 break;
355 default:
356 printf("%s: bad phy register\n", device_xname(sc->sc_dev));
357 splx(s);
358 return;
359 }
360 CSR_WRITE_2(sc, re8139_reg, data);
361 splx(s);
362 return;
363}
364
365static void
366re_miibus_statchg(struct ifnet *ifp)
367{
368
369 return;
370}
371
372static void
373re_reset(struct rtk_softc *sc)
374{
375 int i;
376
377 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET);
378
379 for (i = 0; i < RTK_TIMEOUT; i++) {
380 DELAY(10);
381 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0)
382 break;
383 }
384 if (i == RTK_TIMEOUT)
385 printf("%s: reset never completed!\n",
386 device_xname(sc->sc_dev));
387
388 /*
389 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3,
390 * but also says "Rtl8169s sigle chip detected".
391 */
392 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0)
393 CSR_WRITE_1(sc, RTK_LDPS, 1);
394
395}
396
397/*
398 * The following routine is designed to test for a defect on some
399 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
400 * lines connected to the bus, however for a 32-bit only card, they
401 * should be pulled high. The result of this defect is that the
402 * NIC will not work right if you plug it into a 64-bit slot: DMA
403 * operations will be done with 64-bit transfers, which will fail
404 * because the 64-bit data lines aren't connected.
405 *
406 * There's no way to work around this (short of talking a soldering
407 * iron to the board), however we can detect it. The method we use
408 * here is to put the NIC into digital loopback mode, set the receiver
409 * to promiscuous mode, and then try to send a frame. We then compare
410 * the frame data we sent to what was received. If the data matches,
411 * then the NIC is working correctly, otherwise we know the user has
412 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
413 * slot. In the latter case, there's no way the NIC can work correctly,
414 * so we print out a message on the console and abort the device attach.
415 */
416
417int
418re_diag(struct rtk_softc *sc)
419{
420 struct ifnet *ifp = &sc->ethercom.ec_if;
421 struct mbuf *m0;
422 struct ether_header *eh;
423 struct re_rxsoft *rxs;
424 struct re_desc *cur_rx;
425 bus_dmamap_t dmamap;
426 uint16_t status;
427 uint32_t rxstat;
428 int total_len, i, s, error = 0;
429 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
430 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
431
432 /* Allocate a single mbuf */
433
434 MGETHDR(m0, M_DONTWAIT, MT_DATA);
435 if (m0 == NULL)
436 return ENOBUFS;
437
438 /*
439 * Initialize the NIC in test mode. This sets the chip up
440 * so that it can send and receive frames, but performs the
441 * following special functions:
442 * - Puts receiver in promiscuous mode
443 * - Enables digital loopback mode
444 * - Leaves interrupts turned off
445 */
446
447 ifp->if_flags |= IFF_PROMISC;
448 sc->re_testmode = 1;
449 re_init(ifp);
450 re_stop(ifp, 0);
451 DELAY(100000);
452 re_init(ifp);
453
454 /* Put some data in the mbuf */
455
456 eh = mtod(m0, struct ether_header *);
457 memcpy(eh->ether_dhost, &dst, ETHER_ADDR_LEN);
458 memcpy(eh->ether_shost, &src, ETHER_ADDR_LEN);
459 eh->ether_type = htons(ETHERTYPE_IP);
460 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
461
462 /*
463 * Queue the packet, start transmission.
464 */
465
466 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
467 s = splnet();
468 IF_ENQUEUE(&ifp->if_snd, m0);
469 re_start(ifp);
470 splx(s);
471 m0 = NULL;
472
473 /* Wait for it to propagate through the chip */
474
475 DELAY(100000);
476 for (i = 0; i < RTK_TIMEOUT; i++) {
477 status = CSR_READ_2(sc, RTK_ISR);
478 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) ==
479 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK))
480 break;
481 DELAY(10);
482 }
483 if (i == RTK_TIMEOUT) {
484 aprint_error_dev(sc->sc_dev,
485 "diagnostic failed, failed to receive packet "
486 "in loopback mode\n");
487 error = EIO;
488 goto done;
489 }
490
491 /*
492 * The packet should have been dumped into the first
493 * entry in the RX DMA ring. Grab it from there.
494 */
495
496 rxs = &sc->re_ldata.re_rxsoft[0];
497 dmamap = rxs->rxs_dmamap;
498 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
499 BUS_DMASYNC_POSTREAD);
500 bus_dmamap_unload(sc->sc_dmat, dmamap);
501
502 m0 = rxs->rxs_mbuf;
503 rxs->rxs_mbuf = NULL;
504 eh = mtod(m0, struct ether_header *);
505
506 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
507 cur_rx = &sc->re_ldata.re_rx_list[0];
508 rxstat = le32toh(cur_rx->re_cmdstat);
509 total_len = rxstat & sc->re_rxlenmask;
510
511 if (total_len != ETHER_MIN_LEN) {
512 aprint_error_dev(sc->sc_dev,
513 "diagnostic failed, received short packet\n");
514 error = EIO;
515 goto done;
516 }
517
518 /* Test that the received packet data matches what we sent. */
519
520 if (memcmp(&eh->ether_dhost, &dst, ETHER_ADDR_LEN) ||
521 memcmp(&eh->ether_shost, &src, ETHER_ADDR_LEN) ||
522 ntohs(eh->ether_type) != ETHERTYPE_IP) {
523 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n"
524 "expected TX data: %s/%s/0x%x\n"
525 "received RX data: %s/%s/0x%x\n"
526 "You may have a defective 32-bit NIC plugged "
527 "into a 64-bit PCI slot.\n"
528 "Please re-install the NIC in a 32-bit slot "
529 "for proper operation.\n"
530 "Read the re(4) man page for more details.\n" ,
531 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP,
532 ether_sprintf(eh->ether_dhost),
533 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type));
534 error = EIO;
535 }
536
537 done:
538 /* Turn interface off, release resources */
539
540 sc->re_testmode = 0;
541 ifp->if_flags &= ~IFF_PROMISC;
542 re_stop(ifp, 0);
543 if (m0 != NULL)
544 m_freem(m0);
545
546 return error;
547}
548
549
550/*
551 * Attach the interface. Allocate softc structures, do ifmedia
552 * setup and ethernet/BPF attach.
553 */
554void
555re_attach(struct rtk_softc *sc)
556{
557 uint8_t eaddr[ETHER_ADDR_LEN];
558 struct ifnet *ifp;
559 int error = 0, i;
560
561 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
562 uint32_t hwrev;
563
564 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */
565 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV;
566 switch (hwrev) {
567 case RTK_HWREV_8169:
568 sc->sc_quirk |= RTKQ_8169NONS;
569 break;
570 case RTK_HWREV_8169S:
571 case RTK_HWREV_8110S:
572 case RTK_HWREV_8169_8110SB:
573 case RTK_HWREV_8169_8110SBL:
574 case RTK_HWREV_8169_8110SC:
575 sc->sc_quirk |= RTKQ_MACLDPS;
576 break;
577 case RTK_HWREV_8168_SPIN1:
578 case RTK_HWREV_8168_SPIN2:
579 case RTK_HWREV_8168_SPIN3:
580 sc->sc_quirk |= RTKQ_MACSTAT;
581 break;
582 case RTK_HWREV_8168C:
583 case RTK_HWREV_8168C_SPIN2:
584 case RTK_HWREV_8168CP:
585 case RTK_HWREV_8168D:
586 case RTK_HWREV_8168DP:
587 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
588 RTKQ_MACSTAT | RTKQ_CMDSTOP;
589 /*
590 * From FreeBSD driver:
591 *
592 * These (8168/8111) controllers support jumbo frame
593 * but it seems that enabling it requires touching
594 * additional magic registers. Depending on MAC
595 * revisions some controllers need to disable
596 * checksum offload. So disable jumbo frame until
597 * I have better idea what it really requires to
598 * make it support.
599 * RTL8168C/CP : supports up to 6KB jumbo frame.
600 * RTL8111C/CP : supports up to 9KB jumbo frame.
601 */
602 sc->sc_quirk |= RTKQ_NOJUMBO;
603 break;
604 case RTK_HWREV_8168E:
605 case RTK_HWREV_8168H:
606 case RTK_HWREV_8168H_SPIN1:
607 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
608 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM |
609 RTKQ_NOJUMBO;
610 break;
611 case RTK_HWREV_8168E_VL:
612 case RTK_HWREV_8168F:
613 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
614 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO;
615 break;
616 case RTK_HWREV_8168G:
617 case RTK_HWREV_8168G_SPIN1:
618 case RTK_HWREV_8168G_SPIN2:
619 case RTK_HWREV_8168G_SPIN4:
620 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
621 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO |
622 RTKQ_RXDV_GATED;
623 break;
624 case RTK_HWREV_8100E:
625 case RTK_HWREV_8100E_SPIN2:
626 case RTK_HWREV_8101E:
627 sc->sc_quirk |= RTKQ_NOJUMBO;
628 break;
629 case RTK_HWREV_8102E:
630 case RTK_HWREV_8102EL:
631 case RTK_HWREV_8103E:
632 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
633 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO;
634 break;
635 default:
636 aprint_normal_dev(sc->sc_dev,
637 "Unknown revision (0x%08x)\n", hwrev);
638 /* assume the latest features */
639 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD;
640 sc->sc_quirk |= RTKQ_NOJUMBO;
641 }
642
643 /* Set RX length mask */
644 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
645 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169;
646 } else {
647 sc->sc_quirk |= RTKQ_NOJUMBO;
648
649 /* Set RX length mask */
650 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
651 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139;
652 }
653
654 /* Reset the adapter. */
655 re_reset(sc);
656
657 /*
658 * RTL81x9 chips automatically read EEPROM to init MAC address,
659 * and some NAS override its MAC address per own configuration,
660 * so no need to explicitely read EEPROM and set ID registers.
661 */
662#ifdef RE_USE_EECMD
663 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) {
664 /*
665 * Get station address from ID registers.
666 */
667 for (i = 0; i < ETHER_ADDR_LEN; i++)
668 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
669 } else {
670 uint16_t val;
671 int addr_len;
672
673 /*
674 * Get station address from the EEPROM.
675 */
676 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129)
677 addr_len = RTK_EEADDR_LEN1;
678 else
679 addr_len = RTK_EEADDR_LEN0;
680
681 /*
682 * Get station address from the EEPROM.
683 */
684 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
685 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len);
686 eaddr[(i * 2) + 0] = val & 0xff;
687 eaddr[(i * 2) + 1] = val >> 8;
688 }
689 }
690#else
691 /*
692 * Get station address from ID registers.
693 */
694 for (i = 0; i < ETHER_ADDR_LEN; i++)
695 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
696#endif
697
698 /* Take PHY out of power down mode. */
699 if ((sc->sc_quirk & RTKQ_PHYWAKE_PM) != 0)
700 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80);
701
702 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
703 ether_sprintf(eaddr));
704
705 if (sc->re_ldata.re_tx_desc_cnt >
706 PAGE_SIZE / sizeof(struct re_desc)) {
707 sc->re_ldata.re_tx_desc_cnt =
708 PAGE_SIZE / sizeof(struct re_desc);
709 }
710
711 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n",
712 sc->re_ldata.re_tx_desc_cnt);
713 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0);
714
715 /* Allocate DMA'able memory for the TX ring */
716 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc),
717 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1,
718 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) {
719 aprint_error_dev(sc->sc_dev,
720 "can't allocate tx listseg, error = %d\n", error);
721 goto fail_0;
722 }
723
724 /* Load the map for the TX ring. */
725 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg,
726 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc),
727 (void **)&sc->re_ldata.re_tx_list,
728 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) {
729 aprint_error_dev(sc->sc_dev,
730 "can't map tx list, error = %d\n", error);
731 goto fail_1;
732 }
733 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc));
734
735 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1,
736 RE_TX_LIST_SZ(sc), 0, 0,
737 &sc->re_ldata.re_tx_list_map)) != 0) {
738 aprint_error_dev(sc->sc_dev,
739 "can't create tx list map, error = %d\n", error);
740 goto fail_2;
741 }
742
743
744 if ((error = bus_dmamap_load(sc->sc_dmat,
745 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
746 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) {
747 aprint_error_dev(sc->sc_dev,
748 "can't load tx list, error = %d\n", error);
749 goto fail_3;
750 }
751
752 /* Create DMA maps for TX buffers */
753 for (i = 0; i < RE_TX_QLEN; i++) {
754 error = bus_dmamap_create(sc->sc_dmat,
755 round_page(IP_MAXPACKET),
756 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN,
757 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap);
758 if (error) {
759 aprint_error_dev(sc->sc_dev,
760 "can't create DMA map for TX\n");
761 goto fail_4;
762 }
763 }
764
765 /* Allocate DMA'able memory for the RX ring */
766 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */
767 if ((error = bus_dmamem_alloc(sc->sc_dmat,
768 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1,
769 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) {
770 aprint_error_dev(sc->sc_dev,
771 "can't allocate rx listseg, error = %d\n", error);
772 goto fail_4;
773 }
774
775 /* Load the map for the RX ring. */
776 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg,
777 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ,
778 (void **)&sc->re_ldata.re_rx_list,
779 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) {
780 aprint_error_dev(sc->sc_dev,
781 "can't map rx list, error = %d\n", error);
782 goto fail_5;
783 }
784 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ);
785
786 if ((error = bus_dmamap_create(sc->sc_dmat,
787 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0,
788 &sc->re_ldata.re_rx_list_map)) != 0) {
789 aprint_error_dev(sc->sc_dev,
790 "can't create rx list map, error = %d\n", error);
791 goto fail_6;
792 }
793
794 if ((error = bus_dmamap_load(sc->sc_dmat,
795 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
796 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) {
797 aprint_error_dev(sc->sc_dev,
798 "can't load rx list, error = %d\n", error);
799 goto fail_7;
800 }
801
802 /* Create DMA maps for RX buffers */
803 for (i = 0; i < RE_RX_DESC_CNT; i++) {
804 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
805 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap);
806 if (error) {
807 aprint_error_dev(sc->sc_dev,
808 "can't create DMA map for RX\n");
809 goto fail_8;
810 }
811 }
812
813 /*
814 * Record interface as attached. From here, we should not fail.
815 */
816 sc->sc_flags |= RTK_ATTACHED;
817
818 ifp = &sc->ethercom.ec_if;
819 ifp->if_softc = sc;
820 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
821 ifp->if_mtu = ETHERMTU;
822 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
823 ifp->if_ioctl = re_ioctl;
824 sc->ethercom.ec_capabilities |=
825 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
826 ifp->if_start = re_start;
827 ifp->if_stop = re_stop;
828
829 /*
830 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets,
831 * so we have a workaround to handle the bug by padding
832 * such packets manually.
833 */
834 ifp->if_capabilities |=
835 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
836 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
837 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
838 IFCAP_TSOv4;
839
840 /*
841 * XXX
842 * Still have no idea how to make TSO work on 8168C, 8168CP,
843 * 8102E, 8111C and 8111CP.
844 */
845 if ((sc->sc_quirk & RTKQ_DESCV2) != 0)
846 ifp->if_capabilities &= ~IFCAP_TSOv4;
847
848 ifp->if_watchdog = re_watchdog;
849 ifp->if_init = re_init;
850 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN;
851 ifp->if_capenable = ifp->if_capabilities;
852 IFQ_SET_READY(&ifp->if_snd);
853
854 callout_init(&sc->rtk_tick_ch, 0);
855
856 /* Do MII setup */
857 sc->mii.mii_ifp = ifp;
858 sc->mii.mii_readreg = re_miibus_readreg;
859 sc->mii.mii_writereg = re_miibus_writereg;
860 sc->mii.mii_statchg = re_miibus_statchg;
861 sc->ethercom.ec_mii = &sc->mii;
862 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange,
863 ether_mediastatus);
864 mii_attach(sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY,
865 MII_OFFSET_ANY, 0);
866 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO);
867
868 /*
869 * Call MI attach routine.
870 */
871 if_attach(ifp);
872 ether_ifattach(ifp, eaddr);
873
874 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
875 RND_TYPE_NET, RND_FLAG_DEFAULT);
876
877 if (pmf_device_register(sc->sc_dev, NULL, NULL))
878 pmf_class_network_register(sc->sc_dev, ifp);
879 else
880 aprint_error_dev(sc->sc_dev,
881 "couldn't establish power handler\n");
882
883 return;
884
885 fail_8:
886 /* Destroy DMA maps for RX buffers. */
887 for (i = 0; i < RE_RX_DESC_CNT; i++)
888 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL)
889 bus_dmamap_destroy(sc->sc_dmat,
890 sc->re_ldata.re_rxsoft[i].rxs_dmamap);
891
892 /* Free DMA'able memory for the RX ring. */
893 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
894 fail_7:
895 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
896 fail_6:
897 bus_dmamem_unmap(sc->sc_dmat,
898 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ);
899 fail_5:
900 bus_dmamem_free(sc->sc_dmat,
901 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg);
902
903 fail_4:
904 /* Destroy DMA maps for TX buffers. */
905 for (i = 0; i < RE_TX_QLEN; i++)
906 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL)
907 bus_dmamap_destroy(sc->sc_dmat,
908 sc->re_ldata.re_txq[i].txq_dmamap);
909
910 /* Free DMA'able memory for the TX ring. */
911 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
912 fail_3:
913 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
914 fail_2:
915 bus_dmamem_unmap(sc->sc_dmat,
916 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
917 fail_1:
918 bus_dmamem_free(sc->sc_dmat,
919 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg);
920 fail_0:
921 return;
922}
923
924
925/*
926 * re_activate:
927 * Handle device activation/deactivation requests.
928 */
929int
930re_activate(device_t self, enum devact act)
931{
932 struct rtk_softc *sc = device_private(self);
933
934 switch (act) {
935 case DVACT_DEACTIVATE:
936 if_deactivate(&sc->ethercom.ec_if);
937 return 0;
938 default:
939 return EOPNOTSUPP;
940 }
941}
942
943/*
944 * re_detach:
945 * Detach a rtk interface.
946 */
947int
948re_detach(struct rtk_softc *sc)
949{
950 struct ifnet *ifp = &sc->ethercom.ec_if;
951 int i;
952
953 /*
954 * Succeed now if there isn't any work to do.
955 */
956 if ((sc->sc_flags & RTK_ATTACHED) == 0)
957 return 0;
958
959 /* Unhook our tick handler. */
960 callout_stop(&sc->rtk_tick_ch);
961
962 /* Detach all PHYs. */
963 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY);
964
965 /* Delete all remaining media. */
966 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY);
967
968 rnd_detach_source(&sc->rnd_source);
969 ether_ifdetach(ifp);
970 if_detach(ifp);
971
972 /* Destroy DMA maps for RX buffers. */
973 for (i = 0; i < RE_RX_DESC_CNT; i++)
974 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL)
975 bus_dmamap_destroy(sc->sc_dmat,
976 sc->re_ldata.re_rxsoft[i].rxs_dmamap);
977
978 /* Free DMA'able memory for the RX ring. */
979 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
980 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
981 bus_dmamem_unmap(sc->sc_dmat,
982 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ);
983 bus_dmamem_free(sc->sc_dmat,
984 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg);
985
986 /* Destroy DMA maps for TX buffers. */
987 for (i = 0; i < RE_TX_QLEN; i++)
988 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL)
989 bus_dmamap_destroy(sc->sc_dmat,
990 sc->re_ldata.re_txq[i].txq_dmamap);
991
992 /* Free DMA'able memory for the TX ring. */
993 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
994 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
995 bus_dmamem_unmap(sc->sc_dmat,
996 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
997 bus_dmamem_free(sc->sc_dmat,
998 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg);
999
1000 pmf_device_deregister(sc->sc_dev);
1001
1002 /* we don't want to run again */
1003 sc->sc_flags &= ~RTK_ATTACHED;
1004
1005 return 0;
1006}
1007
1008/*
1009 * re_enable:
1010 * Enable the RTL81X9 chip.
1011 */
1012static int
1013re_enable(struct rtk_softc *sc)
1014{
1015
1016 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) {
1017 if ((*sc->sc_enable)(sc) != 0) {
1018 printf("%s: device enable failed\n",
1019 device_xname(sc->sc_dev));
1020 return EIO;
1021 }
1022 sc->sc_flags |= RTK_ENABLED;
1023 }
1024 return 0;
1025}
1026
1027/*
1028 * re_disable:
1029 * Disable the RTL81X9 chip.
1030 */
1031static void
1032re_disable(struct rtk_softc *sc)
1033{
1034
1035 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) {
1036 (*sc->sc_disable)(sc);
1037 sc->sc_flags &= ~RTK_ENABLED;
1038 }
1039}
1040
1041static int
1042re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m)
1043{
1044 struct mbuf *n = NULL;
1045 bus_dmamap_t map;
1046 struct re_desc *d;
1047 struct re_rxsoft *rxs;
1048 uint32_t cmdstat;
1049 int error;
1050
1051 if (m == NULL) {
1052 MGETHDR(n, M_DONTWAIT, MT_DATA);
1053 if (n == NULL)
1054 return ENOBUFS;
1055
1056 MCLGET(n, M_DONTWAIT);
1057 if ((n->m_flags & M_EXT) == 0) {
1058 m_freem(n);
1059 return ENOBUFS;
1060 }
1061 m = n;
1062 } else
1063 m->m_data = m->m_ext.ext_buf;
1064
1065 /*
1066 * Initialize mbuf length fields and fixup
1067 * alignment so that the frame payload is
1068 * longword aligned.
1069 */
1070 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN;
1071 m->m_data += RE_ETHER_ALIGN;
1072
1073 rxs = &sc->re_ldata.re_rxsoft[idx];
1074 map = rxs->rxs_dmamap;
1075 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
1076 BUS_DMA_READ|BUS_DMA_NOWAIT);
1077
1078 if (error)
1079 goto out;
1080
1081 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1082 BUS_DMASYNC_PREREAD);
1083
1084 d = &sc->re_ldata.re_rx_list[idx];
1085#ifdef DIAGNOSTIC
1086 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1087 cmdstat = le32toh(d->re_cmdstat);
1088 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD);
1089 if (cmdstat & RE_RDESC_STAT_OWN) {
1090 panic("%s: tried to map busy RX descriptor",
1091 device_xname(sc->sc_dev));
1092 }
1093#endif
1094
1095 rxs->rxs_mbuf = m;
1096
1097 d->re_vlanctl = 0;
1098 cmdstat = map->dm_segs[0].ds_len;
1099 if (idx == (RE_RX_DESC_CNT - 1))
1100 cmdstat |= RE_RDESC_CMD_EOR;
1101 re_set_bufaddr(d, map->dm_segs[0].ds_addr);
1102 d->re_cmdstat = htole32(cmdstat);
1103 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1104 cmdstat |= RE_RDESC_CMD_OWN;
1105 d->re_cmdstat = htole32(cmdstat);
1106 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1107
1108 return 0;
1109 out:
1110 if (n != NULL)
1111 m_freem(n);
1112 return ENOMEM;
1113}
1114
1115static int
1116re_tx_list_init(struct rtk_softc *sc)
1117{
1118 int i;
1119
1120 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc));
1121 for (i = 0; i < RE_TX_QLEN; i++) {
1122 sc->re_ldata.re_txq[i].txq_mbuf = NULL;
1123 }
1124
1125 bus_dmamap_sync(sc->sc_dmat,
1126 sc->re_ldata.re_tx_list_map, 0,
1127 sc->re_ldata.re_tx_list_map->dm_mapsize,
1128 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1129 sc->re_ldata.re_txq_prodidx = 0;
1130 sc->re_ldata.re_txq_considx = 0;
1131 sc->re_ldata.re_txq_free = RE_TX_QLEN;
1132 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc);
1133 sc->re_ldata.re_tx_nextfree = 0;
1134
1135 return 0;
1136}
1137
1138static int
1139re_rx_list_init(struct rtk_softc *sc)
1140{
1141 int i;
1142
1143 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ);
1144
1145 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1146 if (re_newbuf(sc, i, NULL) == ENOBUFS)
1147 return ENOBUFS;
1148 }
1149
1150 sc->re_ldata.re_rx_prodidx = 0;
1151 sc->re_head = sc->re_tail = NULL;
1152
1153 return 0;
1154}
1155
1156/*
1157 * RX handler for C+ and 8169. For the gigE chips, we support
1158 * the reception of jumbo frames that have been fragmented
1159 * across multiple 2K mbuf cluster buffers.
1160 */
1161static void
1162re_rxeof(struct rtk_softc *sc)
1163{
1164 struct mbuf *m;
1165 struct ifnet *ifp;
1166 int i, total_len;
1167 struct re_desc *cur_rx;
1168 struct re_rxsoft *rxs;
1169 uint32_t rxstat, rxvlan;
1170
1171 ifp = &sc->ethercom.ec_if;
1172
1173 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) {
1174 cur_rx = &sc->re_ldata.re_rx_list[i];
1175 RE_RXDESCSYNC(sc, i,
1176 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1177 rxstat = le32toh(cur_rx->re_cmdstat);
1178 rxvlan = le32toh(cur_rx->re_vlanctl);
1179 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD);
1180 if ((rxstat & RE_RDESC_STAT_OWN) != 0) {
1181 break;
1182 }
1183 total_len = rxstat & sc->re_rxlenmask;
1184 rxs = &sc->re_ldata.re_rxsoft[i];
1185 m = rxs->rxs_mbuf;
1186
1187 /* Invalidate the RX mbuf and unload its map */
1188
1189 bus_dmamap_sync(sc->sc_dmat,
1190 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize,
1191 BUS_DMASYNC_POSTREAD);
1192 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
1193
1194 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1195 m->m_len = MCLBYTES - RE_ETHER_ALIGN;
1196 if (sc->re_head == NULL)
1197 sc->re_head = sc->re_tail = m;
1198 else {
1199 m->m_flags &= ~M_PKTHDR;
1200 sc->re_tail->m_next = m;
1201 sc->re_tail = m;
1202 }
1203 re_newbuf(sc, i, NULL);
1204 continue;
1205 }
1206
1207 /*
1208 * NOTE: for the 8139C+, the frame length field
1209 * is always 12 bits in size, but for the gigE chips,
1210 * it is 13 bits (since the max RX frame length is 16K).
1211 * Unfortunately, all 32 bits in the status word
1212 * were already used, so to make room for the extra
1213 * length bit, RealTek took out the 'frame alignment
1214 * error' bit and shifted the other status bits
1215 * over one slot. The OWN, EOR, FS and LS bits are
1216 * still in the same places. We have already extracted
1217 * the frame length and checked the OWN bit, so rather
1218 * than using an alternate bit mapping, we shift the
1219 * status bits one space to the right so we can evaluate
1220 * them using the 8169 status as though it was in the
1221 * same format as that of the 8139C+.
1222 */
1223 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0)
1224 rxstat >>= 1;
1225
1226 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) {
1227#ifdef RE_DEBUG
1228 printf("%s: RX error (rxstat = 0x%08x)",
1229 device_xname(sc->sc_dev), rxstat);
1230 if (rxstat & RE_RDESC_STAT_FRALIGN)
1231 printf(", frame alignment error");
1232 if (rxstat & RE_RDESC_STAT_BUFOFLOW)
1233 printf(", out of buffer space");
1234 if (rxstat & RE_RDESC_STAT_FIFOOFLOW)
1235 printf(", FIFO overrun");
1236 if (rxstat & RE_RDESC_STAT_GIANT)
1237 printf(", giant packet");
1238 if (rxstat & RE_RDESC_STAT_RUNT)
1239 printf(", runt packet");
1240 if (rxstat & RE_RDESC_STAT_CRCERR)
1241 printf(", CRC error");
1242 printf("\n");
1243#endif
1244 ifp->if_ierrors++;
1245 /*
1246 * If this is part of a multi-fragment packet,
1247 * discard all the pieces.
1248 */
1249 if (sc->re_head != NULL) {
1250 m_freem(sc->re_head);
1251 sc->re_head = sc->re_tail = NULL;
1252 }
1253 re_newbuf(sc, i, m);
1254 continue;
1255 }
1256
1257 /*
1258 * If allocating a replacement mbuf fails,
1259 * reload the current one.
1260 */
1261
1262 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) {
1263 ifp->if_ierrors++;
1264 if (sc->re_head != NULL) {
1265 m_freem(sc->re_head);
1266 sc->re_head = sc->re_tail = NULL;
1267 }
1268 re_newbuf(sc, i, m);
1269 continue;
1270 }
1271
1272 if (sc->re_head != NULL) {
1273 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN);
1274 /*
1275 * Special case: if there's 4 bytes or less
1276 * in this buffer, the mbuf can be discarded:
1277 * the last 4 bytes is the CRC, which we don't
1278 * care about anyway.
1279 */
1280 if (m->m_len <= ETHER_CRC_LEN) {
1281 sc->re_tail->m_len -=
1282 (ETHER_CRC_LEN - m->m_len);
1283 m_freem(m);
1284 } else {
1285 m->m_len -= ETHER_CRC_LEN;
1286 m->m_flags &= ~M_PKTHDR;
1287 sc->re_tail->m_next = m;
1288 }
1289 m = sc->re_head;
1290 sc->re_head = sc->re_tail = NULL;
1291 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1292 } else
1293 m->m_pkthdr.len = m->m_len =
1294 (total_len - ETHER_CRC_LEN);
1295
1296 ifp->if_ipackets++;
1297 m_set_rcvif(m, ifp);
1298
1299 /* Do RX checksumming */
1300 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) {
1301 /* Check IP header checksum */
1302 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) {
1303 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1304 if (rxstat & RE_RDESC_STAT_IPSUMBAD)
1305 m->m_pkthdr.csum_flags |=
1306 M_CSUM_IPv4_BAD;
1307
1308 /* Check TCP/UDP checksum */
1309 if (RE_TCPPKT(rxstat)) {
1310 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1311 if (rxstat & RE_RDESC_STAT_TCPSUMBAD)
1312 m->m_pkthdr.csum_flags |=
1313 M_CSUM_TCP_UDP_BAD;
1314 } else if (RE_UDPPKT(rxstat)) {
1315 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1316 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) {
1317 /*
1318 * XXX: 8139C+ thinks UDP csum
1319 * 0xFFFF is bad, force software
1320 * calculation.
1321 */
1322 if (sc->sc_quirk & RTKQ_8139CPLUS)
1323 m->m_pkthdr.csum_flags
1324 &= ~M_CSUM_UDPv4;
1325 else
1326 m->m_pkthdr.csum_flags
1327 |= M_CSUM_TCP_UDP_BAD;
1328 }
1329 }
1330 }
1331 } else {
1332 /* Check IPv4 header checksum */
1333 if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) {
1334 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1335 if (rxstat & RE_RDESC_STAT_IPSUMBAD)
1336 m->m_pkthdr.csum_flags |=
1337 M_CSUM_IPv4_BAD;
1338
1339 /* Check TCPv4/UDPv4 checksum */
1340 if (RE_TCPPKT(rxstat)) {
1341 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1342 if (rxstat & RE_RDESC_STAT_TCPSUMBAD)
1343 m->m_pkthdr.csum_flags |=
1344 M_CSUM_TCP_UDP_BAD;
1345 } else if (RE_UDPPKT(rxstat)) {
1346 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1347 if (rxstat & RE_RDESC_STAT_UDPSUMBAD)
1348 m->m_pkthdr.csum_flags |=
1349 M_CSUM_TCP_UDP_BAD;
1350 }
1351 }
1352 /* XXX Check TCPv6/UDPv6 checksum? */
1353 }
1354
1355 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
1356 VLAN_INPUT_TAG(ifp, m,
1357 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA),
1358 continue);
1359 }
1360 bpf_mtap(ifp, m);
1361 if_percpuq_enqueue(ifp->if_percpuq, m);
1362 }
1363
1364 sc->re_ldata.re_rx_prodidx = i;
1365}
1366
1367static void
1368re_txeof(struct rtk_softc *sc)
1369{
1370 struct ifnet *ifp;
1371 struct re_txq *txq;
1372 uint32_t txstat;
1373 int idx, descidx;
1374
1375 ifp = &sc->ethercom.ec_if;
1376
1377 for (idx = sc->re_ldata.re_txq_considx;
1378 sc->re_ldata.re_txq_free < RE_TX_QLEN;
1379 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) {
1380 txq = &sc->re_ldata.re_txq[idx];
1381 KASSERT(txq->txq_mbuf != NULL);
1382
1383 descidx = txq->txq_descidx;
1384 RE_TXDESCSYNC(sc, descidx,
1385 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1386 txstat =
1387 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat);
1388 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD);
1389 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0);
1390 if (txstat & RE_TDESC_CMD_OWN) {
1391 break;
1392 }
1393
1394 sc->re_ldata.re_tx_free += txq->txq_nsegs;
1395 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc));
1396 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap,
1397 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1398 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap);
1399 m_freem(txq->txq_mbuf);
1400 txq->txq_mbuf = NULL;
1401
1402 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT))
1403 ifp->if_collisions++;
1404 if (txstat & RE_TDESC_STAT_TXERRSUM)
1405 ifp->if_oerrors++;
1406 else
1407 ifp->if_opackets++;
1408 }
1409
1410 sc->re_ldata.re_txq_considx = idx;
1411
1412 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD)
1413 ifp->if_flags &= ~IFF_OACTIVE;
1414
1415 /*
1416 * If not all descriptors have been released reaped yet,
1417 * reload the timer so that we will eventually get another
1418 * interrupt that will cause us to re-enter this routine.
1419 * This is done in case the transmitter has gone idle.
1420 */
1421 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) {
1422 CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
1423 if ((sc->sc_quirk & RTKQ_PCIE) != 0) {
1424 /*
1425 * Some chips will ignore a second TX request
1426 * issued while an existing transmission is in
1427 * progress. If the transmitter goes idle but
1428 * there are still packets waiting to be sent,
1429 * we need to restart the channel here to flush
1430 * them out. This only seems to be required with
1431 * the PCIe devices.
1432 */
1433 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START);
1434 }
1435 } else
1436 ifp->if_timer = 0;
1437}
1438
1439static void
1440re_tick(void *arg)
1441{
1442 struct rtk_softc *sc = arg;
1443 int s;
1444
1445 /* XXX: just return for 8169S/8110S with rev 2 or newer phy */
1446 s = splnet();
1447
1448 mii_tick(&sc->mii);
1449 splx(s);
1450
1451 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc);
1452}
1453
1454int
1455re_intr(void *arg)
1456{
1457 struct rtk_softc *sc = arg;
1458 struct ifnet *ifp;
1459 uint16_t status;
1460 int handled = 0;
1461
1462 if (!device_has_power(sc->sc_dev))
1463 return 0;
1464
1465 ifp = &sc->ethercom.ec_if;
1466
1467 if ((ifp->if_flags & IFF_UP) == 0)
1468 return 0;
1469
1470 for (;;) {
1471
1472 status = CSR_READ_2(sc, RTK_ISR);
1473 /* If the card has gone away the read returns 0xffff. */
1474 if (status == 0xffff)
1475 break;
1476 if (status) {
1477 handled = 1;
1478 CSR_WRITE_2(sc, RTK_ISR, status);
1479 }
1480
1481 if ((status & RTK_INTRS_CPLUS) == 0)
1482 break;
1483
1484 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR))
1485 re_rxeof(sc);
1486
1487 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR |
1488 RTK_ISR_TX_DESC_UNAVAIL))
1489 re_txeof(sc);
1490
1491 if (status & RTK_ISR_SYSTEM_ERR) {
1492 re_init(ifp);
1493 }
1494
1495 if (status & RTK_ISR_LINKCHG) {
1496 callout_stop(&sc->rtk_tick_ch);
1497 re_tick(sc);
1498 }
1499 }
1500
1501 if (handled && !IFQ_IS_EMPTY(&ifp->if_snd))
1502 re_start(ifp);
1503
1504 rnd_add_uint32(&sc->rnd_source, status);
1505
1506 return handled;
1507}
1508
1509
1510
1511/*
1512 * Main transmit routine for C+ and gigE NICs.
1513 */
1514
1515static void
1516re_start(struct ifnet *ifp)
1517{
1518 struct rtk_softc *sc;
1519 struct mbuf *m;
1520 bus_dmamap_t map;
1521 struct re_txq *txq;
1522 struct re_desc *d;
1523 struct m_tag *mtag;
1524 uint32_t cmdstat, re_flags, vlanctl;
1525 int ofree, idx, error, nsegs, seg;
1526 int startdesc, curdesc, lastdesc;
1527 bool pad;
1528
1529 sc = ifp->if_softc;
1530 ofree = sc->re_ldata.re_txq_free;
1531
1532 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) {
1533
1534 IFQ_POLL(&ifp->if_snd, m);
1535 if (m == NULL)
1536 break;
1537
1538 if (sc->re_ldata.re_txq_free == 0 ||
1539 sc->re_ldata.re_tx_free == 0) {
1540 /* no more free slots left */
1541 ifp->if_flags |= IFF_OACTIVE;
1542 break;
1543 }
1544
1545 /*
1546 * Set up checksum offload. Note: checksum offload bits must
1547 * appear in all descriptors of a multi-descriptor transmit
1548 * attempt. (This is according to testing done with an 8169
1549 * chip. I'm not sure if this is a requirement or a bug.)
1550 */
1551
1552 vlanctl = 0;
1553 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) {
1554 uint32_t segsz = m->m_pkthdr.segsz;
1555
1556 re_flags = RE_TDESC_CMD_LGSEND |
1557 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT);
1558 } else {
1559 /*
1560 * set RE_TDESC_CMD_IPCSUM if any checksum offloading
1561 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/
1562 * RE_TDESC_CMD_UDPCSUM doesn't make effects.
1563 */
1564 re_flags = 0;
1565 if ((m->m_pkthdr.csum_flags &
1566 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4))
1567 != 0) {
1568 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) {
1569 re_flags |= RE_TDESC_CMD_IPCSUM;
1570 if (m->m_pkthdr.csum_flags &
1571 M_CSUM_TCPv4) {
1572 re_flags |=
1573 RE_TDESC_CMD_TCPCSUM;
1574 } else if (m->m_pkthdr.csum_flags &
1575 M_CSUM_UDPv4) {
1576 re_flags |=
1577 RE_TDESC_CMD_UDPCSUM;
1578 }
1579 } else {
1580 vlanctl |= RE_TDESC_VLANCTL_IPCSUM;
1581 if (m->m_pkthdr.csum_flags &
1582 M_CSUM_TCPv4) {
1583 vlanctl |=
1584 RE_TDESC_VLANCTL_TCPCSUM;
1585 } else if (m->m_pkthdr.csum_flags &
1586 M_CSUM_UDPv4) {
1587 vlanctl |=
1588 RE_TDESC_VLANCTL_UDPCSUM;
1589 }
1590 }
1591 }
1592 }
1593
1594 txq = &sc->re_ldata.re_txq[idx];
1595 map = txq->txq_dmamap;
1596 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
1597 BUS_DMA_WRITE|BUS_DMA_NOWAIT);
1598
1599 if (__predict_false(error)) {
1600 /* XXX try to defrag if EFBIG? */
1601 printf("%s: can't map mbuf (error %d)\n",
1602 device_xname(sc->sc_dev), error);
1603
1604 IFQ_DEQUEUE(&ifp->if_snd, m);
1605 m_freem(m);
1606 ifp->if_oerrors++;
1607 continue;
1608 }
1609
1610 nsegs = map->dm_nsegs;
1611 pad = false;
1612 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN &&
1613 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 &&
1614 (sc->sc_quirk & RTKQ_DESCV2) == 0)) {
1615 pad = true;
1616 nsegs++;
1617 }
1618
1619 if (nsegs > sc->re_ldata.re_tx_free) {
1620 /*
1621 * Not enough free descriptors to transmit this packet.
1622 */
1623 ifp->if_flags |= IFF_OACTIVE;
1624 bus_dmamap_unload(sc->sc_dmat, map);
1625 break;
1626 }
1627
1628 IFQ_DEQUEUE(&ifp->if_snd, m);
1629
1630 /*
1631 * Make sure that the caches are synchronized before we
1632 * ask the chip to start DMA for the packet data.
1633 */
1634 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1635 BUS_DMASYNC_PREWRITE);
1636
1637 /*
1638 * Set up hardware VLAN tagging. Note: vlan tag info must
1639 * appear in all descriptors of a multi-descriptor
1640 * transmission attempt.
1641 */
1642 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL)
1643 vlanctl |= bswap16(VLAN_TAG_VALUE(mtag)) |
1644 RE_TDESC_VLANCTL_TAG;
1645
1646 /*
1647 * Map the segment array into descriptors.
1648 * Note that we set the start-of-frame and
1649 * end-of-frame markers for either TX or RX,
1650 * but they really only have meaning in the TX case.
1651 * (In the RX case, it's the chip that tells us
1652 * where packets begin and end.)
1653 * We also keep track of the end of the ring
1654 * and set the end-of-ring bits as needed,
1655 * and we set the ownership bits in all except
1656 * the very first descriptor. (The caller will
1657 * set this descriptor later when it start
1658 * transmission or reception.)
1659 */
1660 curdesc = startdesc = sc->re_ldata.re_tx_nextfree;
1661 lastdesc = -1;
1662 for (seg = 0; seg < map->dm_nsegs;
1663 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) {
1664 d = &sc->re_ldata.re_tx_list[curdesc];
1665#ifdef DIAGNOSTIC
1666 RE_TXDESCSYNC(sc, curdesc,
1667 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1668 cmdstat = le32toh(d->re_cmdstat);
1669 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD);
1670 if (cmdstat & RE_TDESC_STAT_OWN) {
1671 panic("%s: tried to map busy TX descriptor",
1672 device_xname(sc->sc_dev));
1673 }
1674#endif
1675
1676 d->re_vlanctl = htole32(vlanctl);
1677 re_set_bufaddr(d, map->dm_segs[seg].ds_addr);
1678 cmdstat = re_flags | map->dm_segs[seg].ds_len;
1679 if (seg == 0)
1680 cmdstat |= RE_TDESC_CMD_SOF;
1681 else
1682 cmdstat |= RE_TDESC_CMD_OWN;
1683 if (curdesc == (RE_TX_DESC_CNT(sc) - 1))
1684 cmdstat |= RE_TDESC_CMD_EOR;
1685 if (seg == nsegs - 1) {
1686 cmdstat |= RE_TDESC_CMD_EOF;
1687 lastdesc = curdesc;
1688 }
1689 d->re_cmdstat = htole32(cmdstat);
1690 RE_TXDESCSYNC(sc, curdesc,
1691 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1692 }
1693 if (__predict_false(pad)) {
1694 d = &sc->re_ldata.re_tx_list[curdesc];
1695 d->re_vlanctl = htole32(vlanctl);
1696 re_set_bufaddr(d, RE_TXPADDADDR(sc));
1697 cmdstat = re_flags |
1698 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF |
1699 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len);
1700 if (curdesc == (RE_TX_DESC_CNT(sc) - 1))
1701 cmdstat |= RE_TDESC_CMD_EOR;
1702 d->re_cmdstat = htole32(cmdstat);
1703 RE_TXDESCSYNC(sc, curdesc,
1704 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1705 lastdesc = curdesc;
1706 curdesc = RE_NEXT_TX_DESC(sc, curdesc);
1707 }
1708 KASSERT(lastdesc != -1);
1709
1710 /* Transfer ownership of packet to the chip. */
1711
1712 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |=
1713 htole32(RE_TDESC_CMD_OWN);
1714 RE_TXDESCSYNC(sc, startdesc,
1715 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1716
1717 /* update info of TX queue and descriptors */
1718 txq->txq_mbuf = m;
1719 txq->txq_descidx = lastdesc;
1720 txq->txq_nsegs = nsegs;
1721
1722 sc->re_ldata.re_txq_free--;
1723 sc->re_ldata.re_tx_free -= nsegs;
1724 sc->re_ldata.re_tx_nextfree = curdesc;
1725
1726 /*
1727 * If there's a BPF listener, bounce a copy of this frame
1728 * to him.
1729 */
1730 bpf_mtap(ifp, m);
1731 }
1732
1733 if (sc->re_ldata.re_txq_free < ofree) {
1734 /*
1735 * TX packets are enqueued.
1736 */
1737 sc->re_ldata.re_txq_prodidx = idx;
1738
1739 /*
1740 * Start the transmitter to poll.
1741 *
1742 * RealTek put the TX poll request register in a different
1743 * location on the 8169 gigE chip. I don't know why.
1744 */
1745 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0)
1746 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START);
1747 else
1748 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START);
1749
1750 /*
1751 * Use the countdown timer for interrupt moderation.
1752 * 'TX done' interrupts are disabled. Instead, we reset the
1753 * countdown timer, which will begin counting until it hits
1754 * the value in the TIMERINT register, and then trigger an
1755 * interrupt. Each time we write to the TIMERCNT register,
1756 * the timer count is reset to 0.
1757 */
1758 CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
1759
1760 /*
1761 * Set a timeout in case the chip goes out to lunch.
1762 */
1763 ifp->if_timer = 5;
1764 }
1765}
1766
1767static int
1768re_init(struct ifnet *ifp)
1769{
1770 struct rtk_softc *sc = ifp->if_softc;
1771 uint32_t rxcfg = 0;
1772 uint16_t cfg;
1773 int error;
1774#ifdef RE_USE_EECMD
1775 const uint8_t *enaddr;
1776 uint32_t reg;
1777#endif
1778
1779 if ((error = re_enable(sc)) != 0)
1780 goto out;
1781
1782 /*
1783 * Cancel pending I/O and free all RX/TX buffers.
1784 */
1785 re_stop(ifp, 0);
1786
1787 re_reset(sc);
1788
1789 /*
1790 * Enable C+ RX and TX mode, as well as VLAN stripping and
1791 * RX checksum offload. We must configure the C+ register
1792 * before all others.
1793 */
1794 cfg = RE_CPLUSCMD_PCI_MRW;
1795
1796 /*
1797 * XXX: For old 8169 set bit 14.
1798 * For 8169S/8110S and above, do not set bit 14.
1799 */
1800 if ((sc->sc_quirk & RTKQ_8169NONS) != 0)
1801 cfg |= (0x1 << 14);
1802
1803 if ((sc->ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) != 0)
1804 cfg |= RE_CPLUSCMD_VLANSTRIP;
1805 if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx |
1806 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0)
1807 cfg |= RE_CPLUSCMD_RXCSUM_ENB;
1808 if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) {
1809 cfg |= RE_CPLUSCMD_MACSTAT_DIS;
1810 cfg |= RE_CPLUSCMD_TXENB;
1811 } else
1812 cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB;
1813
1814 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg);
1815
1816 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */
1817 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0)
1818 CSR_WRITE_2(sc, RTK_IM, 0x0000);
1819
1820 DELAY(10000);
1821
1822#ifdef RE_USE_EECMD
1823 /*
1824 * Init our MAC address. Even though the chipset
1825 * documentation doesn't mention it, we need to enter "Config
1826 * register write enable" mode to modify the ID registers.
1827 */
1828 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG);
1829 enaddr = CLLADDR(ifp->if_sadl);
1830 reg = enaddr[0] | (enaddr[1] << 8) |
1831 (enaddr[2] << 16) | (enaddr[3] << 24);
1832 CSR_WRITE_4(sc, RTK_IDR0, reg);
1833 reg = enaddr[4] | (enaddr[5] << 8);
1834 CSR_WRITE_4(sc, RTK_IDR4, reg);
1835 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF);
1836#endif
1837
1838 /*
1839 * For C+ mode, initialize the RX descriptors and mbufs.
1840 */
1841 re_rx_list_init(sc);
1842 re_tx_list_init(sc);
1843
1844 /*
1845 * Load the addresses of the RX and TX lists into the chip.
1846 */
1847 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI,
1848 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr));
1849 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO,
1850 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr));
1851
1852 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI,
1853 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr));
1854 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO,
1855 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr));
1856
1857 if (sc->sc_quirk & RTKQ_RXDV_GATED) {
1858 CSR_WRITE_4(sc, RTK_MISC,
1859 CSR_READ_4(sc, RTK_MISC) & ~RTK_MISC_RXDV_GATED_EN);
1860 }
1861
1862 /*
1863 * Enable transmit and receive.
1864 */
1865 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
1866
1867 /*
1868 * Set the initial TX and RX configuration.
1869 */
1870 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) {
1871 /* test mode is needed only for old 8169 */
1872 CSR_WRITE_4(sc, RTK_TXCFG,
1873 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON);
1874 } else
1875 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG);
1876
1877 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16);
1878
1879 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG);
1880
1881 /* Set the individual bit to receive frames for this host only. */
1882 rxcfg = CSR_READ_4(sc, RTK_RXCFG);
1883 rxcfg |= RTK_RXCFG_RX_INDIV;
1884
1885 /* If we want promiscuous mode, set the allframes bit. */
1886 if (ifp->if_flags & IFF_PROMISC)
1887 rxcfg |= RTK_RXCFG_RX_ALLPHYS;
1888 else
1889 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS;
1890 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1891
1892 /*
1893 * Set capture broadcast bit to capture broadcast frames.
1894 */
1895 if (ifp->if_flags & IFF_BROADCAST)
1896 rxcfg |= RTK_RXCFG_RX_BROAD;
1897 else
1898 rxcfg &= ~RTK_RXCFG_RX_BROAD;
1899 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1900
1901 /*
1902 * Program the multicast filter, if necessary.
1903 */
1904 rtk_setmulti(sc);
1905
1906 /*
1907 * Enable interrupts.
1908 */
1909 if (sc->re_testmode)
1910 CSR_WRITE_2(sc, RTK_IMR, 0);
1911 else
1912 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS);
1913
1914 /* Start RX/TX process. */
1915 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0);
1916#ifdef notdef
1917 /* Enable receiver and transmitter. */
1918 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
1919#endif
1920
1921 /*
1922 * Initialize the timer interrupt register so that
1923 * a timer interrupt will be generated once the timer
1924 * reaches a certain number of ticks. The timer is
1925 * reloaded on each transmit. This gives us TX interrupt
1926 * moderation, which dramatically improves TX frame rate.
1927 */
1928
1929 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0)
1930 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400);
1931 else {
1932 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800);
1933
1934 /*
1935 * For 8169 gigE NICs, set the max allowed RX packet
1936 * size so we can receive jumbo frames.
1937 */
1938 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383);
1939 }
1940
1941 if (sc->re_testmode)
1942 return 0;
1943
1944 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD);
1945
1946 ifp->if_flags |= IFF_RUNNING;
1947 ifp->if_flags &= ~IFF_OACTIVE;
1948
1949 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc);
1950
1951 out:
1952 if (error) {
1953 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1954 ifp->if_timer = 0;
1955 printf("%s: interface not running\n",
1956 device_xname(sc->sc_dev));
1957 }
1958
1959 return error;
1960}
1961
1962static int
1963re_ioctl(struct ifnet *ifp, u_long command, void *data)
1964{
1965 struct rtk_softc *sc = ifp->if_softc;
1966 struct ifreq *ifr = data;
1967 int s, error = 0;
1968
1969 s = splnet();
1970
1971 switch (command) {
1972 case SIOCSIFMTU:
1973 /*
1974 * Disable jumbo frames if it's not supported.
1975 */
1976 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 &&
1977 ifr->ifr_mtu > ETHERMTU) {
1978 error = EINVAL;
1979 break;
1980 }
1981
1982 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO)
1983 error = EINVAL;
1984 else if ((error = ifioctl_common(ifp, command, data)) ==
1985 ENETRESET)
1986 error = 0;
1987 break;
1988 default:
1989 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET)
1990 break;
1991
1992 error = 0;
1993
1994 if (command == SIOCSIFCAP)
1995 error = (*ifp->if_init)(ifp);
1996 else if (command != SIOCADDMULTI && command != SIOCDELMULTI)
1997 ;
1998 else if (ifp->if_flags & IFF_RUNNING)
1999 rtk_setmulti(sc);
2000 break;
2001 }
2002
2003 splx(s);
2004
2005 return error;
2006}
2007
2008static void
2009re_watchdog(struct ifnet *ifp)
2010{
2011 struct rtk_softc *sc;
2012 int s;
2013
2014 sc = ifp->if_softc;
2015 s = splnet();
2016 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev));
2017 ifp->if_oerrors++;
2018
2019 re_txeof(sc);
2020 re_rxeof(sc);
2021
2022 re_init(ifp);
2023
2024 splx(s);
2025}
2026
2027/*
2028 * Stop the adapter and free any mbufs allocated to the
2029 * RX and TX lists.
2030 */
2031static void
2032re_stop(struct ifnet *ifp, int disable)
2033{
2034 int i;
2035 struct rtk_softc *sc = ifp->if_softc;
2036
2037 callout_stop(&sc->rtk_tick_ch);
2038
2039 mii_down(&sc->mii);
2040
2041 if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0)
2042 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB |
2043 RTK_CMD_RX_ENB);
2044 else
2045 CSR_WRITE_1(sc, RTK_COMMAND, 0x00);
2046 DELAY(1000);
2047 CSR_WRITE_2(sc, RTK_IMR, 0x0000);
2048 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
2049
2050 if (sc->re_head != NULL) {
2051 m_freem(sc->re_head);
2052 sc->re_head = sc->re_tail = NULL;
2053 }
2054
2055 /* Free the TX list buffers. */
2056 for (i = 0; i < RE_TX_QLEN; i++) {
2057 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) {
2058 bus_dmamap_unload(sc->sc_dmat,
2059 sc->re_ldata.re_txq[i].txq_dmamap);
2060 m_freem(sc->re_ldata.re_txq[i].txq_mbuf);
2061 sc->re_ldata.re_txq[i].txq_mbuf = NULL;
2062 }
2063 }
2064
2065 /* Free the RX list buffers. */
2066 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2067 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) {
2068 bus_dmamap_unload(sc->sc_dmat,
2069 sc->re_ldata.re_rxsoft[i].rxs_dmamap);
2070 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf);
2071 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL;
2072 }
2073 }
2074
2075 if (disable)
2076 re_disable(sc);
2077
2078 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2079 ifp->if_timer = 0;
2080}
2081