1 | /* $NetBSD: nouveau_subdev_bios_timing.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2013 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_bios_timing.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $" ); |
29 | |
30 | #include <subdev/bios.h> |
31 | #include <subdev/bios/bit.h> |
32 | #include <subdev/bios/ramcfg.h> |
33 | #include <subdev/bios/timing.h> |
34 | |
35 | u16 |
36 | nvbios_timingTe(struct nouveau_bios *bios, |
37 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) |
38 | { |
39 | struct bit_entry bit_P; |
40 | u16 timing = 0x0000; |
41 | |
42 | if (!bit_entry(bios, 'P', &bit_P)) { |
43 | if (bit_P.version == 1) |
44 | timing = nv_ro16(bios, bit_P.offset + 4); |
45 | else |
46 | if (bit_P.version == 2) |
47 | timing = nv_ro16(bios, bit_P.offset + 8); |
48 | |
49 | if (timing) { |
50 | *ver = nv_ro08(bios, timing + 0); |
51 | switch (*ver) { |
52 | case 0x10: |
53 | *hdr = nv_ro08(bios, timing + 1); |
54 | *cnt = nv_ro08(bios, timing + 2); |
55 | *len = nv_ro08(bios, timing + 3); |
56 | *snr = 0; |
57 | *ssz = 0; |
58 | return timing; |
59 | case 0x20: |
60 | *hdr = nv_ro08(bios, timing + 1); |
61 | *cnt = nv_ro08(bios, timing + 5); |
62 | *len = nv_ro08(bios, timing + 2); |
63 | *snr = nv_ro08(bios, timing + 4); |
64 | *ssz = nv_ro08(bios, timing + 3); |
65 | return timing; |
66 | default: |
67 | break; |
68 | } |
69 | } |
70 | } |
71 | |
72 | return 0x0000; |
73 | } |
74 | |
75 | u16 |
76 | nvbios_timingEe(struct nouveau_bios *bios, int idx, |
77 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len) |
78 | { |
79 | u8 snr, ssz; |
80 | u16 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); |
81 | if (timing && idx < *cnt) { |
82 | timing += *hdr + idx * (*len + (snr * ssz)); |
83 | *hdr = *len; |
84 | *cnt = snr; |
85 | *len = ssz; |
86 | return timing; |
87 | } |
88 | return 0x0000; |
89 | } |
90 | |
91 | u16 |
92 | nvbios_timingEp(struct nouveau_bios *bios, int idx, |
93 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, |
94 | struct nvbios_ramcfg *p) |
95 | { |
96 | u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp; |
97 | switch (!!data * *ver) { |
98 | case 0x20: |
99 | p->timing[0] = nv_ro32(bios, data + 0x00); |
100 | p->timing[1] = nv_ro32(bios, data + 0x04); |
101 | p->timing[2] = nv_ro32(bios, data + 0x08); |
102 | p->timing[3] = nv_ro32(bios, data + 0x0c); |
103 | p->timing[4] = nv_ro32(bios, data + 0x10); |
104 | p->timing[5] = nv_ro32(bios, data + 0x14); |
105 | p->timing[6] = nv_ro32(bios, data + 0x18); |
106 | p->timing[7] = nv_ro32(bios, data + 0x1c); |
107 | p->timing[8] = nv_ro32(bios, data + 0x20); |
108 | p->timing[9] = nv_ro32(bios, data + 0x24); |
109 | p->timing[10] = nv_ro32(bios, data + 0x28); |
110 | p->timing_20_2e_03 = (nv_ro08(bios, data + 0x2e) & 0x03) >> 0; |
111 | p->timing_20_2e_30 = (nv_ro08(bios, data + 0x2e) & 0x30) >> 4; |
112 | p->timing_20_2e_c0 = (nv_ro08(bios, data + 0x2e) & 0xc0) >> 6; |
113 | p->timing_20_2f_03 = (nv_ro08(bios, data + 0x2f) & 0x03) >> 0; |
114 | temp = nv_ro16(bios, data + 0x2c); |
115 | p->timing_20_2c_003f = (temp & 0x003f) >> 0; |
116 | p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6; |
117 | p->timing_20_30_07 = (nv_ro08(bios, data + 0x30) & 0x07) >> 0; |
118 | p->timing_20_30_f8 = (nv_ro08(bios, data + 0x30) & 0xf8) >> 3; |
119 | temp = nv_ro16(bios, data + 0x31); |
120 | p->timing_20_31_0007 = (temp & 0x0007) >> 0; |
121 | p->timing_20_31_0078 = (temp & 0x0078) >> 3; |
122 | p->timing_20_31_0780 = (temp & 0x0780) >> 7; |
123 | p->timing_20_31_0800 = (temp & 0x0800) >> 11; |
124 | p->timing_20_31_7000 = (temp & 0x7000) >> 12; |
125 | p->timing_20_31_8000 = (temp & 0x8000) >> 15; |
126 | break; |
127 | default: |
128 | data = 0; |
129 | break; |
130 | } |
131 | return data; |
132 | } |
133 | |