1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> |
3 | * Copyright © 2006-2008,2010 Intel Corporation |
4 | * Jesse Barnes <jesse.barnes@intel.com> |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice (including the next |
14 | * paragraph) shall be included in all copies or substantial portions of the |
15 | * Software. |
16 | * |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
23 | * DEALINGS IN THE SOFTWARE. |
24 | * |
25 | * Authors: |
26 | * Eric Anholt <eric@anholt.net> |
27 | * Chris Wilson <chris@chris-wilson.co.uk> |
28 | */ |
29 | #include <linux/i2c.h> |
30 | #include <linux/i2c-algo-bit.h> |
31 | #include <linux/export.h> |
32 | #include <linux/module.h> |
33 | #include <drm/drmP.h> |
34 | #include "intel_drv.h" |
35 | #include <drm/i915_drm.h> |
36 | #include "i915_drv.h" |
37 | |
38 | enum disp_clk { |
39 | CDCLK, |
40 | CZCLK |
41 | }; |
42 | |
43 | struct gmbus_port { |
44 | const char *name; |
45 | int reg; |
46 | }; |
47 | |
48 | static const struct gmbus_port gmbus_ports[] = { |
49 | { "ssc" , GPIOB }, |
50 | { "vga" , GPIOA }, |
51 | { "panel" , GPIOC }, |
52 | { "dpc" , GPIOD }, |
53 | { "dpb" , GPIOE }, |
54 | { "dpd" , GPIOF }, |
55 | }; |
56 | |
57 | /* Intel GPIO access functions */ |
58 | |
59 | #define I2C_RISEFALL_TIME 10 |
60 | |
61 | static inline struct intel_gmbus * |
62 | to_intel_gmbus(struct i2c_adapter *i2c) |
63 | { |
64 | return container_of(i2c, struct intel_gmbus, adapter); |
65 | } |
66 | |
67 | static int get_disp_clk_div(struct drm_i915_private *dev_priv, |
68 | enum disp_clk clk) |
69 | { |
70 | u32 reg_val; |
71 | int clk_ratio; |
72 | |
73 | reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO); |
74 | |
75 | if (clk == CDCLK) |
76 | clk_ratio = |
77 | ((reg_val & CDCLK_FREQ_MASK) >> CDCLK_FREQ_SHIFT) + 1; |
78 | else |
79 | clk_ratio = (reg_val & CZCLK_FREQ_MASK) + 1; |
80 | |
81 | return clk_ratio; |
82 | } |
83 | |
84 | static void gmbus_set_freq(struct drm_i915_private *dev_priv) |
85 | { |
86 | int vco, gmbus_freq = 0, cdclk_div; |
87 | |
88 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); |
89 | |
90 | vco = valleyview_get_vco(dev_priv); |
91 | |
92 | /* Get the CDCLK divide ratio */ |
93 | cdclk_div = get_disp_clk_div(dev_priv, CDCLK); |
94 | |
95 | /* |
96 | * Program the gmbus_freq based on the cdclk frequency. |
97 | * BSpec erroneously claims we should aim for 4MHz, but |
98 | * in fact 1MHz is the correct frequency. |
99 | */ |
100 | if (cdclk_div) |
101 | gmbus_freq = (vco << 1) / cdclk_div; |
102 | |
103 | if (WARN_ON(gmbus_freq == 0)) |
104 | return; |
105 | |
106 | I915_WRITE(GMBUSFREQ_VLV, gmbus_freq); |
107 | } |
108 | |
109 | void |
110 | intel_i2c_reset(struct drm_device *dev) |
111 | { |
112 | struct drm_i915_private *dev_priv = dev->dev_private; |
113 | |
114 | /* |
115 | * In BIOS-less system, program the correct gmbus frequency |
116 | * before reading edid. |
117 | */ |
118 | if (IS_VALLEYVIEW(dev)) |
119 | gmbus_set_freq(dev_priv); |
120 | |
121 | I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); |
122 | I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); |
123 | } |
124 | |
125 | static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) |
126 | { |
127 | u32 val; |
128 | |
129 | /* When using bit bashing for I2C, this bit needs to be set to 1 */ |
130 | if (!IS_PINEVIEW(dev_priv->dev)) |
131 | return; |
132 | |
133 | val = I915_READ(DSPCLK_GATE_D); |
134 | if (enable) |
135 | val |= DPCUNIT_CLOCK_GATE_DISABLE; |
136 | else |
137 | val &= ~DPCUNIT_CLOCK_GATE_DISABLE; |
138 | I915_WRITE(DSPCLK_GATE_D, val); |
139 | } |
140 | |
141 | static u32 get_reserved(struct intel_gmbus *bus) |
142 | { |
143 | struct drm_i915_private *dev_priv = bus->dev_priv; |
144 | struct drm_device *dev = dev_priv->dev; |
145 | u32 reserved = 0; |
146 | |
147 | /* On most chips, these bits must be preserved in software. */ |
148 | if (!IS_I830(dev) && !IS_845G(dev)) |
149 | reserved = I915_READ_NOTRACE(bus->gpio_reg) & |
150 | (GPIO_DATA_PULLUP_DISABLE | |
151 | GPIO_CLOCK_PULLUP_DISABLE); |
152 | |
153 | return reserved; |
154 | } |
155 | |
156 | static int get_clock(void *data) |
157 | { |
158 | struct intel_gmbus *bus = data; |
159 | struct drm_i915_private *dev_priv = bus->dev_priv; |
160 | u32 reserved = get_reserved(bus); |
161 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); |
162 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); |
163 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; |
164 | } |
165 | |
166 | static int get_data(void *data) |
167 | { |
168 | struct intel_gmbus *bus = data; |
169 | struct drm_i915_private *dev_priv = bus->dev_priv; |
170 | u32 reserved = get_reserved(bus); |
171 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); |
172 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); |
173 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; |
174 | } |
175 | |
176 | static void set_clock(void *data, int state_high) |
177 | { |
178 | struct intel_gmbus *bus = data; |
179 | struct drm_i915_private *dev_priv = bus->dev_priv; |
180 | u32 reserved = get_reserved(bus); |
181 | u32 clock_bits; |
182 | |
183 | if (state_high) |
184 | clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; |
185 | else |
186 | clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | |
187 | GPIO_CLOCK_VAL_MASK; |
188 | |
189 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); |
190 | POSTING_READ(bus->gpio_reg); |
191 | } |
192 | |
193 | static void set_data(void *data, int state_high) |
194 | { |
195 | struct intel_gmbus *bus = data; |
196 | struct drm_i915_private *dev_priv = bus->dev_priv; |
197 | u32 reserved = get_reserved(bus); |
198 | u32 data_bits; |
199 | |
200 | if (state_high) |
201 | data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; |
202 | else |
203 | data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | |
204 | GPIO_DATA_VAL_MASK; |
205 | |
206 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); |
207 | POSTING_READ(bus->gpio_reg); |
208 | } |
209 | |
210 | static int |
211 | intel_gpio_pre_xfer(struct i2c_adapter *adapter) |
212 | { |
213 | struct intel_gmbus *bus = container_of(adapter, |
214 | struct intel_gmbus, |
215 | adapter); |
216 | struct drm_i915_private *dev_priv = bus->dev_priv; |
217 | |
218 | intel_i2c_reset(dev_priv->dev); |
219 | intel_i2c_quirk_set(dev_priv, true); |
220 | set_data(bus, 1); |
221 | set_clock(bus, 1); |
222 | udelay(I2C_RISEFALL_TIME); |
223 | return 0; |
224 | } |
225 | |
226 | static void |
227 | intel_gpio_post_xfer(struct i2c_adapter *adapter) |
228 | { |
229 | struct intel_gmbus *bus = container_of(adapter, |
230 | struct intel_gmbus, |
231 | adapter); |
232 | struct drm_i915_private *dev_priv = bus->dev_priv; |
233 | |
234 | set_data(bus, 1); |
235 | set_clock(bus, 1); |
236 | intel_i2c_quirk_set(dev_priv, false); |
237 | } |
238 | |
239 | static void |
240 | intel_gpio_setup(struct intel_gmbus *bus, u32 pin) |
241 | { |
242 | struct drm_i915_private *dev_priv = bus->dev_priv; |
243 | struct i2c_algo_bit_data *algo; |
244 | |
245 | algo = &bus->bit_algo; |
246 | |
247 | /* -1 to map pin pair to gmbus index */ |
248 | bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg; |
249 | |
250 | bus->adapter.algo_data = algo; |
251 | algo->setsda = set_data; |
252 | algo->setscl = set_clock; |
253 | algo->getsda = get_data; |
254 | algo->getscl = get_clock; |
255 | algo->pre_xfer = intel_gpio_pre_xfer; |
256 | algo->post_xfer = intel_gpio_post_xfer; |
257 | algo->udelay = I2C_RISEFALL_TIME; |
258 | algo->timeout = usecs_to_jiffies(2200); |
259 | algo->data = bus; |
260 | } |
261 | |
262 | static int |
263 | gmbus_wait_hw_status(struct drm_i915_private *dev_priv, |
264 | u32 gmbus2_status, |
265 | u32 gmbus4_irq_en) |
266 | { |
267 | int i; |
268 | int reg_offset = dev_priv->gpio_mmio_base; |
269 | u32 gmbus2 = 0; |
270 | #ifndef __NetBSD__ |
271 | DEFINE_WAIT(wait); |
272 | #endif |
273 | |
274 | #ifdef __NetBSD__ |
275 | if (cold || !HAS_GMBUS_IRQ(dev_priv->dev)) |
276 | gmbus4_irq_en = 0; |
277 | #else |
278 | if (!HAS_GMBUS_IRQ(dev_priv->dev)) |
279 | gmbus4_irq_en = 0; |
280 | #endif |
281 | |
282 | /* Important: The hw handles only the first bit, so set only one! Since |
283 | * we also need to check for NAKs besides the hw ready/idle signal, we |
284 | * need to wake up periodically and check that ourselves. */ |
285 | I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); |
286 | |
287 | #ifdef __NetBSD__ |
288 | if (cold) { |
289 | i = 50; |
290 | do { |
291 | gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset); |
292 | if (ISSET(gmbus2, (GMBUS_SATOER | gmbus2_status))) |
293 | break; |
294 | DELAY(1000); |
295 | } while (i-- > 0); |
296 | } else { |
297 | i = mstohz(50); |
298 | do { |
299 | int ret; |
300 | |
301 | spin_lock(&dev_priv->gmbus_wait_lock); |
302 | DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL(ret, |
303 | &dev_priv->gmbus_wait_queue, |
304 | &dev_priv->gmbus_wait_lock, |
305 | 1, |
306 | (gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset), |
307 | ISSET(gmbus2, |
308 | (GMBUS_SATOER | gmbus2_status)))); |
309 | spin_unlock(&dev_priv->gmbus_wait_lock); |
310 | if (ret) |
311 | break; |
312 | } while (i-- > 0); |
313 | } |
314 | #else |
315 | for (i = 0; i < msecs_to_jiffies_timeout(50); i++) { |
316 | prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, |
317 | TASK_UNINTERRUPTIBLE); |
318 | |
319 | gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset); |
320 | if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) |
321 | break; |
322 | |
323 | schedule_timeout(1); |
324 | } |
325 | finish_wait(&dev_priv->gmbus_wait_queue, &wait); |
326 | #endif |
327 | |
328 | I915_WRITE(GMBUS4 + reg_offset, 0); |
329 | |
330 | if (gmbus2 & GMBUS_SATOER) |
331 | return -ENXIO; |
332 | if (gmbus2 & gmbus2_status) |
333 | return 0; |
334 | return -ETIMEDOUT; |
335 | } |
336 | |
337 | static int |
338 | gmbus_wait_idle(struct drm_i915_private *dev_priv) |
339 | { |
340 | int ret; |
341 | int reg_offset = dev_priv->gpio_mmio_base; |
342 | |
343 | #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) |
344 | |
345 | #ifdef __NetBSD__ |
346 | if (cold || !HAS_GMBUS_IRQ(dev_priv->dev)) |
347 | return wait_for(C, 10); |
348 | #else |
349 | if (!HAS_GMBUS_IRQ(dev_priv->dev)) |
350 | return wait_for(C, 10); |
351 | #endif |
352 | |
353 | /* Important: The hw handles only the first bit, so set only one! */ |
354 | I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); |
355 | |
356 | #ifdef __NetBSD__ |
357 | spin_lock(&dev_priv->gmbus_wait_lock); |
358 | DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL(ret, &dev_priv->gmbus_wait_queue, |
359 | &dev_priv->gmbus_wait_lock, msecs_to_jiffies_timeout(10), |
360 | C); |
361 | spin_unlock(&dev_priv->gmbus_wait_lock); |
362 | #else |
363 | ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
364 | msecs_to_jiffies_timeout(10)); |
365 | #endif |
366 | |
367 | I915_WRITE(GMBUS4 + reg_offset, 0); |
368 | |
369 | if (ret) |
370 | return 0; |
371 | else |
372 | return -ETIMEDOUT; |
373 | #undef C |
374 | } |
375 | |
376 | static int |
377 | gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, |
378 | u32 gmbus1_index) |
379 | { |
380 | int reg_offset = dev_priv->gpio_mmio_base; |
381 | u16 len = msg->len; |
382 | u8 *buf = msg->buf; |
383 | |
384 | I915_WRITE(GMBUS1 + reg_offset, |
385 | gmbus1_index | |
386 | GMBUS_CYCLE_WAIT | |
387 | (len << GMBUS_BYTE_COUNT_SHIFT) | |
388 | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | |
389 | GMBUS_SLAVE_READ | GMBUS_SW_RDY); |
390 | while (len) { |
391 | int ret; |
392 | u32 val, loop = 0; |
393 | |
394 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, |
395 | GMBUS_HW_RDY_EN); |
396 | if (ret) |
397 | return ret; |
398 | |
399 | val = I915_READ(GMBUS3 + reg_offset); |
400 | do { |
401 | *buf++ = val & 0xff; |
402 | val >>= 8; |
403 | } while (--len && ++loop < 4); |
404 | } |
405 | |
406 | return 0; |
407 | } |
408 | |
409 | static int |
410 | gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) |
411 | { |
412 | int reg_offset = dev_priv->gpio_mmio_base; |
413 | u16 len = msg->len; |
414 | u8 *buf = msg->buf; |
415 | u32 val, loop; |
416 | |
417 | val = loop = 0; |
418 | while (len && loop < 4) { |
419 | val |= *buf++ << (8 * loop++); |
420 | len -= 1; |
421 | } |
422 | |
423 | I915_WRITE(GMBUS3 + reg_offset, val); |
424 | I915_WRITE(GMBUS1 + reg_offset, |
425 | GMBUS_CYCLE_WAIT | |
426 | (msg->len << GMBUS_BYTE_COUNT_SHIFT) | |
427 | (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) | |
428 | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); |
429 | while (len) { |
430 | int ret; |
431 | |
432 | val = loop = 0; |
433 | do { |
434 | val |= *buf++ << (8 * loop); |
435 | } while (--len && ++loop < 4); |
436 | |
437 | I915_WRITE(GMBUS3 + reg_offset, val); |
438 | |
439 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, |
440 | GMBUS_HW_RDY_EN); |
441 | if (ret) |
442 | return ret; |
443 | } |
444 | return 0; |
445 | } |
446 | |
447 | /* |
448 | * The gmbus controller can combine a 1 or 2 byte write with a read that |
449 | * immediately follows it by using an "INDEX" cycle. |
450 | */ |
451 | static bool |
452 | gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) |
453 | { |
454 | return (i + 1 < num && |
455 | !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && |
456 | (msgs[i + 1].flags & I2C_M_RD)); |
457 | } |
458 | |
459 | static int |
460 | gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) |
461 | { |
462 | int reg_offset = dev_priv->gpio_mmio_base; |
463 | u32 gmbus1_index = 0; |
464 | u32 gmbus5 = 0; |
465 | int ret; |
466 | |
467 | if (msgs[0].len == 2) |
468 | gmbus5 = GMBUS_2BYTE_INDEX_EN | |
469 | msgs[0].buf[1] | (msgs[0].buf[0] << 8); |
470 | if (msgs[0].len == 1) |
471 | gmbus1_index = GMBUS_CYCLE_INDEX | |
472 | (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); |
473 | |
474 | /* GMBUS5 holds 16-bit index */ |
475 | if (gmbus5) |
476 | I915_WRITE(GMBUS5 + reg_offset, gmbus5); |
477 | |
478 | ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); |
479 | |
480 | /* Clear GMBUS5 after each index transfer */ |
481 | if (gmbus5) |
482 | I915_WRITE(GMBUS5 + reg_offset, 0); |
483 | |
484 | return ret; |
485 | } |
486 | |
487 | static int |
488 | gmbus_xfer(struct i2c_adapter *adapter, |
489 | struct i2c_msg *msgs, |
490 | int num) |
491 | { |
492 | struct intel_gmbus *bus = container_of(adapter, |
493 | struct intel_gmbus, |
494 | adapter); |
495 | struct drm_i915_private *dev_priv = bus->dev_priv; |
496 | int i, reg_offset; |
497 | int ret = 0; |
498 | |
499 | intel_aux_display_runtime_get(dev_priv); |
500 | mutex_lock(&dev_priv->gmbus_mutex); |
501 | |
502 | if (bus->force_bit) { |
503 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
504 | goto out; |
505 | } |
506 | |
507 | reg_offset = dev_priv->gpio_mmio_base; |
508 | |
509 | I915_WRITE(GMBUS0 + reg_offset, bus->reg0); |
510 | |
511 | for (i = 0; i < num; i++) { |
512 | if (gmbus_is_index_read(msgs, i, num)) { |
513 | ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); |
514 | i += 1; /* set i to the index of the read xfer */ |
515 | } else if (msgs[i].flags & I2C_M_RD) { |
516 | ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); |
517 | } else { |
518 | ret = gmbus_xfer_write(dev_priv, &msgs[i]); |
519 | } |
520 | |
521 | if (ret == -ETIMEDOUT) |
522 | goto timeout; |
523 | if (ret == -ENXIO) |
524 | goto clear_err; |
525 | |
526 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, |
527 | GMBUS_HW_WAIT_EN); |
528 | if (ret == -ENXIO) |
529 | goto clear_err; |
530 | if (ret) |
531 | goto timeout; |
532 | } |
533 | |
534 | /* Generate a STOP condition on the bus. Note that gmbus can't generata |
535 | * a STOP on the very first cycle. To simplify the code we |
536 | * unconditionally generate the STOP condition with an additional gmbus |
537 | * cycle. */ |
538 | I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); |
539 | |
540 | /* Mark the GMBUS interface as disabled after waiting for idle. |
541 | * We will re-enable it at the start of the next xfer, |
542 | * till then let it sleep. |
543 | */ |
544 | if (gmbus_wait_idle(dev_priv)) { |
545 | DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n" , |
546 | adapter->name); |
547 | ret = -ETIMEDOUT; |
548 | } |
549 | I915_WRITE(GMBUS0 + reg_offset, 0); |
550 | ret = ret ?: i; |
551 | goto out; |
552 | |
553 | clear_err: |
554 | /* |
555 | * Wait for bus to IDLE before clearing NAK. |
556 | * If we clear the NAK while bus is still active, then it will stay |
557 | * active and the next transaction may fail. |
558 | * |
559 | * If no ACK is received during the address phase of a transaction, the |
560 | * adapter must report -ENXIO. It is not clear what to return if no ACK |
561 | * is received at other times. But we have to be careful to not return |
562 | * spurious -ENXIO because that will prevent i2c and drm edid functions |
563 | * from retrying. So return -ENXIO only when gmbus properly quiescents - |
564 | * timing out seems to happen when there _is_ a ddc chip present, but |
565 | * it's slow responding and only answers on the 2nd retry. |
566 | */ |
567 | ret = -ENXIO; |
568 | if (gmbus_wait_idle(dev_priv)) { |
569 | DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n" , |
570 | adapter->name); |
571 | ret = -ETIMEDOUT; |
572 | } |
573 | |
574 | /* Toggle the Software Clear Interrupt bit. This has the effect |
575 | * of resetting the GMBUS controller and so clearing the |
576 | * BUS_ERROR raised by the slave's NAK. |
577 | */ |
578 | I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); |
579 | I915_WRITE(GMBUS1 + reg_offset, 0); |
580 | I915_WRITE(GMBUS0 + reg_offset, 0); |
581 | |
582 | DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n" , |
583 | adapter->name, msgs[i].addr, |
584 | (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); |
585 | |
586 | goto out; |
587 | |
588 | timeout: |
589 | DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n" , |
590 | bus->adapter.name, bus->reg0 & 0xff); |
591 | I915_WRITE(GMBUS0 + reg_offset, 0); |
592 | |
593 | /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ |
594 | bus->force_bit = 1; |
595 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
596 | |
597 | out: |
598 | mutex_unlock(&dev_priv->gmbus_mutex); |
599 | intel_aux_display_runtime_put(dev_priv); |
600 | return ret; |
601 | } |
602 | |
603 | static u32 gmbus_func(struct i2c_adapter *adapter) |
604 | { |
605 | return i2c_bit_algo.functionality(adapter) & |
606 | (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
607 | /* I2C_FUNC_10BIT_ADDR | */ |
608 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | |
609 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL); |
610 | } |
611 | |
612 | static const struct i2c_algorithm gmbus_algorithm = { |
613 | .master_xfer = gmbus_xfer, |
614 | .functionality = gmbus_func |
615 | }; |
616 | |
617 | /** |
618 | * intel_gmbus_setup - instantiate all Intel i2c GMBuses |
619 | * @dev: DRM device |
620 | */ |
621 | int intel_setup_gmbus(struct drm_device *dev) |
622 | { |
623 | struct drm_i915_private *dev_priv = dev->dev_private; |
624 | int ret, i; |
625 | |
626 | if (HAS_PCH_NOP(dev)) |
627 | return 0; |
628 | else if (HAS_PCH_SPLIT(dev)) |
629 | dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; |
630 | else if (IS_VALLEYVIEW(dev)) |
631 | dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; |
632 | else |
633 | dev_priv->gpio_mmio_base = 0; |
634 | |
635 | #ifdef __NetBSD__ |
636 | linux_mutex_init(&dev_priv->gmbus_mutex); |
637 | #else |
638 | mutex_init(&dev_priv->gmbus_mutex); |
639 | #endif |
640 | |
641 | #ifdef __NetBSD__ |
642 | spin_lock_init(&dev_priv->gmbus_wait_lock); |
643 | DRM_INIT_WAITQUEUE(&dev_priv->gmbus_wait_queue, "i915i2c" ); |
644 | #else |
645 | init_waitqueue_head(&dev_priv->gmbus_wait_queue); |
646 | #endif |
647 | |
648 | for (i = 0; i < GMBUS_NUM_PORTS; i++) { |
649 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
650 | u32 port = i + 1; /* +1 to map gmbus index to pin pair */ |
651 | |
652 | bus->adapter.owner = THIS_MODULE; |
653 | bus->adapter.class = I2C_CLASS_DDC; |
654 | snprintf(bus->adapter.name, |
655 | sizeof(bus->adapter.name), |
656 | "i915 gmbus %s" , |
657 | gmbus_ports[i].name); |
658 | |
659 | bus->adapter.dev.parent = dev->dev; |
660 | bus->dev_priv = dev_priv; |
661 | |
662 | bus->adapter.algo = &gmbus_algorithm; |
663 | |
664 | /* By default use a conservative clock rate */ |
665 | bus->reg0 = port | GMBUS_RATE_100KHZ; |
666 | |
667 | /* gmbus seems to be broken on i830 */ |
668 | if (IS_I830(dev)) |
669 | bus->force_bit = 1; |
670 | |
671 | intel_gpio_setup(bus, port); |
672 | |
673 | ret = i2c_add_adapter(&bus->adapter); |
674 | if (ret) |
675 | goto err; |
676 | } |
677 | |
678 | intel_i2c_reset(dev_priv->dev); |
679 | |
680 | return 0; |
681 | |
682 | err: |
683 | while (--i) { |
684 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
685 | i2c_del_adapter(&bus->adapter); |
686 | } |
687 | return ret; |
688 | } |
689 | |
690 | struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, |
691 | unsigned port) |
692 | { |
693 | WARN_ON(!intel_gmbus_is_port_valid(port)); |
694 | /* -1 to map pin pair to gmbus index */ |
695 | return (intel_gmbus_is_port_valid(port)) ? |
696 | &dev_priv->gmbus[port - 1].adapter : NULL; |
697 | } |
698 | |
699 | void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) |
700 | { |
701 | struct intel_gmbus *bus = to_intel_gmbus(adapter); |
702 | |
703 | bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; |
704 | } |
705 | |
706 | void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) |
707 | { |
708 | struct intel_gmbus *bus = to_intel_gmbus(adapter); |
709 | |
710 | bus->force_bit += force_bit ? 1 : -1; |
711 | DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n" , |
712 | force_bit ? "en" : "dis" , adapter->name, |
713 | bus->force_bit); |
714 | } |
715 | |
716 | void intel_teardown_gmbus(struct drm_device *dev) |
717 | { |
718 | struct drm_i915_private *dev_priv = dev->dev_private; |
719 | int i; |
720 | |
721 | for (i = 0; i < GMBUS_NUM_PORTS; i++) { |
722 | struct intel_gmbus *bus = &dev_priv->gmbus[i]; |
723 | i2c_del_adapter(&bus->adapter); |
724 | } |
725 | |
726 | #ifdef __NetBSD__ |
727 | DRM_DESTROY_WAITQUEUE(&dev_priv->gmbus_wait_queue); |
728 | spin_lock_destroy(&dev_priv->gmbus_wait_lock); |
729 | linux_mutex_destroy(&dev_priv->gmbus_mutex); |
730 | #endif |
731 | } |
732 | |