1 | /* $NetBSD: nouveau_subdev_devinit_nva3.c,v 1.1.1.1 2014/08/06 12:36:30 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2013 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_devinit_nva3.c,v 1.1.1.1 2014/08/06 12:36:30 riastradh Exp $" ); |
29 | |
30 | #include "nv50.h" |
31 | |
32 | int |
33 | nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) |
34 | { |
35 | struct nv50_devinit_priv *priv = (void *)devinit; |
36 | struct nouveau_bios *bios = nouveau_bios(priv); |
37 | struct nvbios_pll info; |
38 | int N, fN, M, P; |
39 | int ret; |
40 | |
41 | ret = nvbios_pll_parse(bios, type, &info); |
42 | if (ret) |
43 | return ret; |
44 | |
45 | ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P); |
46 | if (ret < 0) |
47 | return ret; |
48 | |
49 | switch (info.type) { |
50 | case PLL_VPLL0: |
51 | case PLL_VPLL1: |
52 | nv_wr32(priv, info.reg + 0, 0x50000610); |
53 | nv_mask(priv, info.reg + 4, 0x003fffff, |
54 | (P << 16) | (M << 8) | N); |
55 | nv_wr32(priv, info.reg + 8, fN); |
56 | break; |
57 | default: |
58 | nv_warn(priv, "0x%08x/%dKhz unimplemented\n" , type, freq); |
59 | ret = -EINVAL; |
60 | break; |
61 | } |
62 | |
63 | return ret; |
64 | } |
65 | |
66 | static u64 |
67 | nva3_devinit_disable(struct nouveau_devinit *devinit) |
68 | { |
69 | struct nv50_devinit_priv *priv = (void *)devinit; |
70 | u32 r001540 = nv_rd32(priv, 0x001540); |
71 | u32 r00154c = nv_rd32(priv, 0x00154c); |
72 | u64 disable = 0ULL; |
73 | |
74 | if (!(r001540 & 0x40000000)) { |
75 | disable |= (1ULL << NVDEV_ENGINE_VP); |
76 | disable |= (1ULL << NVDEV_ENGINE_PPP); |
77 | } |
78 | |
79 | if (!(r00154c & 0x00000004)) |
80 | disable |= (1ULL << NVDEV_ENGINE_DISP); |
81 | if (!(r00154c & 0x00000020)) |
82 | disable |= (1ULL << NVDEV_ENGINE_BSP); |
83 | if (!(r00154c & 0x00000200)) |
84 | disable |= (1ULL << NVDEV_ENGINE_COPY0); |
85 | |
86 | return disable; |
87 | } |
88 | |
89 | static u32 |
90 | nva3_devinit_mmio_part[] = { |
91 | 0x100720, 0x1008bc, 4, |
92 | 0x100a20, 0x100adc, 4, |
93 | 0x100d80, 0x100ddc, 4, |
94 | 0x110000, 0x110f9c, 4, |
95 | 0x111000, 0x11103c, 8, |
96 | 0x111080, 0x1110fc, 4, |
97 | 0x111120, 0x1111fc, 4, |
98 | 0x111300, 0x1114bc, 4, |
99 | 0, |
100 | }; |
101 | |
102 | static u32 |
103 | nva3_devinit_mmio(struct nouveau_devinit *devinit, u32 addr) |
104 | { |
105 | struct nv50_devinit_priv *priv = (void *)devinit; |
106 | u32 *mmio = nva3_devinit_mmio_part; |
107 | |
108 | /* the init tables on some boards have INIT_RAM_RESTRICT_ZM_REG_GROUP |
109 | * instructions which touch registers that may not even exist on |
110 | * some configurations (Quadro 400), which causes the register |
111 | * interface to screw up for some amount of time after attempting to |
112 | * write to one of these, and results in all sorts of things going |
113 | * horribly wrong. |
114 | * |
115 | * the binary driver avoids touching these registers at all, however, |
116 | * the video bios doesn't care and does what the scripts say. it's |
117 | * presumed that the io-port access to priv registers isn't effected |
118 | * by the screw-up bug mentioned above. |
119 | * |
120 | * really, a new opcode should've been invented to handle these |
121 | * requirements, but whatever, it's too late for that now. |
122 | */ |
123 | while (mmio[0]) { |
124 | if (addr >= mmio[0] && addr <= mmio[1]) { |
125 | u32 part = (addr / mmio[2]) & 7; |
126 | if (!priv->r001540) |
127 | priv->r001540 = nv_rd32(priv, 0x001540); |
128 | if (part >= hweight8((priv->r001540 >> 16) & 0xff)) |
129 | return ~0; |
130 | return addr; |
131 | } |
132 | mmio += 3; |
133 | } |
134 | |
135 | return addr; |
136 | } |
137 | |
138 | struct nouveau_oclass * |
139 | nva3_devinit_oclass = &(struct nouveau_devinit_impl) { |
140 | .base.handle = NV_SUBDEV(DEVINIT, 0xa3), |
141 | .base.ofuncs = &(struct nouveau_ofuncs) { |
142 | .ctor = nv50_devinit_ctor, |
143 | .dtor = _nouveau_devinit_dtor, |
144 | .init = nv50_devinit_init, |
145 | .fini = _nouveau_devinit_fini, |
146 | }, |
147 | .pll_set = nva3_devinit_pll_set, |
148 | .disable = nva3_devinit_disable, |
149 | .mmio = nva3_devinit_mmio, |
150 | }.base; |
151 | |