1/* $NetBSD: nouveau_dispnv04_tvnv17.c,v 1.3 2014/08/23 08:03:34 riastradh Exp $ */
2
3/*
4 * Copyright (C) 2009 Francisco Jerez.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sublicense, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: nouveau_dispnv04_tvnv17.c,v 1.3 2014/08/23 08:03:34 riastradh Exp $");
31
32#include <drm/drmP.h>
33#include <drm/drm_crtc_helper.h>
34#include "nouveau_drm.h"
35#include "nouveau_reg.h"
36#include "nouveau_encoder.h"
37#include "nouveau_connector.h"
38#include "nouveau_crtc.h"
39#include "hw.h"
40#include "tvnv17.h"
41
42#include <core/device.h>
43
44#include <subdev/bios/gpio.h>
45#include <subdev/gpio.h>
46
47MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
48 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
49 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
50 "\t\tDefault: PAL\n"
51 "\t\t*NOTE* Ignored for cards with external TV encoders.");
52static char *nouveau_tv_norm;
53module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
54
55static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
56{
57 struct drm_device *dev = encoder->dev;
58 struct nouveau_drm *drm = nouveau_drm(dev);
59 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
60 uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
61 uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
62 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
63 uint32_t sample = 0;
64 int head;
65
66#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
67 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
68 if (drm->vbios.tvdactestval)
69 testval = drm->vbios.tvdactestval;
70
71 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
72 head = (dacclk & 0x100) >> 8;
73
74 /* Save the previous state. */
75 gpio1 = gpio->get(gpio, 0, DCB_GPIO_TVDAC1, 0xff);
76 gpio0 = gpio->get(gpio, 0, DCB_GPIO_TVDAC0, 0xff);
77 fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
78 fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
79 fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
80 fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
81 test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
82 ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
83 ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
84 ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
85
86 /* Prepare the DAC for load detection. */
87 gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, true);
88 gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, true);
89
90 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
91 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
92 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
93 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
94 NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
95 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
96 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
97 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
98 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
99
100 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
101
102 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
103 (dacclk & ~0xff) | 0x22);
104 msleep(1);
105 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
106 (dacclk & ~0xff) | 0x21);
107
108 NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
109 NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
110
111 /* Sample pin 0x4 (usually S-video luma). */
112 NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
113 msleep(20);
114 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
115 & 0x4 << 28;
116
117 /* Sample the remaining pins. */
118 NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
119 msleep(20);
120 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
121 & 0xa << 28;
122
123 /* Restore the previous state. */
124 NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
125 NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
126 NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
127 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
128 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
129 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
130 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
131 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
132 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
133 gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, gpio1);
134 gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, gpio0);
135
136 return sample;
137}
138
139static bool
140get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
141{
142 struct nouveau_drm *drm = nouveau_drm(dev);
143 struct nouveau_object *device = drm->device;
144
145 /* Zotac FX5200 */
146 if (nv_device_match(device, 0x0322, 0x19da, 0x1035) ||
147 nv_device_match(device, 0x0322, 0x19da, 0x2035)) {
148 *pin_mask = 0xc;
149 return false;
150 }
151
152 /* MSI nForce2 IGP */
153 if (nv_device_match(device, 0x01f0, 0x1462, 0x5710)) {
154 *pin_mask = 0xc;
155 return false;
156 }
157
158 return true;
159}
160
161static enum drm_connector_status
162nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
163{
164 struct drm_device *dev = encoder->dev;
165 struct nouveau_drm *drm = nouveau_drm(dev);
166 struct drm_mode_config *conf = &dev->mode_config;
167 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
168 struct dcb_output *dcb = tv_enc->base.dcb;
169 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
170
171 if (nv04_dac_in_use(encoder))
172 return connector_status_disconnected;
173
174 if (reliable) {
175 if (nv_device(drm->device)->chipset == 0x42 ||
176 nv_device(drm->device)->chipset == 0x43)
177 tv_enc->pin_mask =
178 nv42_tv_sample_load(encoder) >> 28 & 0xe;
179 else
180 tv_enc->pin_mask =
181 nv17_dac_sample_load(encoder) >> 28 & 0xe;
182 }
183
184 switch (tv_enc->pin_mask) {
185 case 0x2:
186 case 0x4:
187 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite;
188 break;
189 case 0xc:
190 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
191 break;
192 case 0xe:
193 if (dcb->tvconf.has_component_output)
194 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
195 else
196 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
197 break;
198 default:
199 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
200 break;
201 }
202
203 drm_object_property_set_value(&connector->base,
204 conf->tv_subconnector_property,
205 tv_enc->subconnector);
206
207 if (!reliable) {
208 return connector_status_unknown;
209 } else if (tv_enc->subconnector) {
210 NV_INFO(drm, "Load detected on output %c\n",
211 '@' + ffs(dcb->or));
212 return connector_status_connected;
213 } else {
214 return connector_status_disconnected;
215 }
216}
217
218static int nv17_tv_get_ld_modes(struct drm_encoder *encoder,
219 struct drm_connector *connector)
220{
221 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
222 const struct drm_display_mode *tv_mode;
223 int n = 0;
224
225 for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) {
226 struct drm_display_mode *mode;
227
228 mode = drm_mode_duplicate(encoder->dev, tv_mode);
229
230 mode->clock = tv_norm->tv_enc_mode.vrefresh *
231 mode->htotal / 1000 *
232 mode->vtotal / 1000;
233
234 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
235 mode->clock *= 2;
236
237 if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay &&
238 mode->vdisplay == tv_norm->tv_enc_mode.vdisplay)
239 mode->type |= DRM_MODE_TYPE_PREFERRED;
240
241 drm_mode_probed_add(connector, mode);
242 n++;
243 }
244
245 return n;
246}
247
248static int nv17_tv_get_hd_modes(struct drm_encoder *encoder,
249 struct drm_connector *connector)
250{
251 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
252 const struct drm_display_mode *output_mode = &tv_norm->ctv_enc_mode.mode;
253 struct drm_display_mode *mode;
254 const struct {
255 int hdisplay;
256 int vdisplay;
257 } modes[] = {
258 { 640, 400 },
259 { 640, 480 },
260 { 720, 480 },
261 { 720, 576 },
262 { 800, 600 },
263 { 1024, 768 },
264 { 1280, 720 },
265 { 1280, 1024 },
266 { 1920, 1080 }
267 };
268 int i, n = 0;
269
270 for (i = 0; i < ARRAY_SIZE(modes); i++) {
271 if (modes[i].hdisplay > output_mode->hdisplay ||
272 modes[i].vdisplay > output_mode->vdisplay)
273 continue;
274
275 if (modes[i].hdisplay == output_mode->hdisplay &&
276 modes[i].vdisplay == output_mode->vdisplay) {
277 mode = drm_mode_duplicate(encoder->dev, output_mode);
278 mode->type |= DRM_MODE_TYPE_PREFERRED;
279
280 } else {
281 mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay,
282 modes[i].vdisplay, 60, false,
283 (output_mode->flags &
284 DRM_MODE_FLAG_INTERLACE), false);
285 }
286
287 /* CVT modes are sometimes unsuitable... */
288 if (output_mode->hdisplay <= 720
289 || output_mode->hdisplay >= 1920) {
290 mode->htotal = output_mode->htotal;
291 mode->hsync_start = (mode->hdisplay + (mode->htotal
292 - mode->hdisplay) * 9 / 10) & ~7;
293 mode->hsync_end = mode->hsync_start + 8;
294 }
295
296 if (output_mode->vdisplay >= 1024) {
297 mode->vtotal = output_mode->vtotal;
298 mode->vsync_start = output_mode->vsync_start;
299 mode->vsync_end = output_mode->vsync_end;
300 }
301
302 mode->type |= DRM_MODE_TYPE_DRIVER;
303 drm_mode_probed_add(connector, mode);
304 n++;
305 }
306
307 return n;
308}
309
310static int nv17_tv_get_modes(struct drm_encoder *encoder,
311 struct drm_connector *connector)
312{
313 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
314
315 if (tv_norm->kind == CTV_ENC_MODE)
316 return nv17_tv_get_hd_modes(encoder, connector);
317 else
318 return nv17_tv_get_ld_modes(encoder, connector);
319}
320
321static int nv17_tv_mode_valid(struct drm_encoder *encoder,
322 struct drm_display_mode *mode)
323{
324 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
325
326 if (tv_norm->kind == CTV_ENC_MODE) {
327 const struct drm_display_mode *output_mode =
328 &tv_norm->ctv_enc_mode.mode;
329
330 if (mode->clock > 400000)
331 return MODE_CLOCK_HIGH;
332
333 if (mode->hdisplay > output_mode->hdisplay ||
334 mode->vdisplay > output_mode->vdisplay)
335 return MODE_BAD;
336
337 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) !=
338 (output_mode->flags & DRM_MODE_FLAG_INTERLACE))
339 return MODE_NO_INTERLACE;
340
341 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
342 return MODE_NO_DBLESCAN;
343
344 } else {
345 const int vsync_tolerance = 600;
346
347 if (mode->clock > 70000)
348 return MODE_CLOCK_HIGH;
349
350 if (abs(drm_mode_vrefresh(mode) * 1000 -
351 tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance)
352 return MODE_VSYNC;
353
354 /* The encoder takes care of the actual interlacing */
355 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
356 return MODE_NO_INTERLACE;
357 }
358
359 return MODE_OK;
360}
361
362static bool nv17_tv_mode_fixup(struct drm_encoder *encoder,
363 const struct drm_display_mode *mode,
364 struct drm_display_mode *adjusted_mode)
365{
366 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
367
368 if (nv04_dac_in_use(encoder))
369 return false;
370
371 if (tv_norm->kind == CTV_ENC_MODE)
372 adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock;
373 else
374 adjusted_mode->clock = 90000;
375
376 return true;
377}
378
379static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
380{
381 struct drm_device *dev = encoder->dev;
382 struct nouveau_drm *drm = nouveau_drm(dev);
383 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
384 struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
385 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
386
387 if (nouveau_encoder(encoder)->last_dpms == mode)
388 return;
389 nouveau_encoder(encoder)->last_dpms = mode;
390
391 NV_INFO(drm, "Setting dpms mode %d on TV encoder (output %d)\n",
392 mode, nouveau_encoder(encoder)->dcb->index);
393
394 regs->ptv_200 &= ~1;
395
396 if (tv_norm->kind == CTV_ENC_MODE) {
397 nv04_dfp_update_fp_control(encoder, mode);
398
399 } else {
400 nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF);
401
402 if (mode == DRM_MODE_DPMS_ON)
403 regs->ptv_200 |= 1;
404 }
405
406 nv_load_ptv(dev, regs, 200);
407
408 gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, mode == DRM_MODE_DPMS_ON);
409 gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, mode == DRM_MODE_DPMS_ON);
410
411 nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
412}
413
414static void nv17_tv_prepare(struct drm_encoder *encoder)
415{
416 struct drm_device *dev = encoder->dev;
417 struct nouveau_drm *drm = nouveau_drm(dev);
418 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
419 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
420 int head = nouveau_crtc(encoder->crtc)->index;
421 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[
422 NV_CIO_CRE_LCD__INDEX];
423 uint32_t dacclk_off = NV_PRAMDAC_DACCLK +
424 nv04_dac_output_offset(encoder);
425 uint32_t dacclk;
426
427 helper->dpms(encoder, DRM_MODE_DPMS_OFF);
428
429 nv04_dfp_disable(dev, head);
430
431 /* Unbind any FP encoders from this head if we need the FP
432 * stuff enabled. */
433 if (tv_norm->kind == CTV_ENC_MODE) {
434 struct drm_encoder *enc;
435
436 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
437 struct dcb_output *dcb = nouveau_encoder(enc)->dcb;
438
439 if ((dcb->type == DCB_OUTPUT_TMDS ||
440 dcb->type == DCB_OUTPUT_LVDS) &&
441 !enc->crtc &&
442 nv04_dfp_get_bound_head(dev, dcb) == head) {
443 nv04_dfp_bind_head(dev, dcb, head ^ 1,
444 drm->vbios.fp.dual_link);
445 }
446 }
447
448 }
449
450 if (tv_norm->kind == CTV_ENC_MODE)
451 *cr_lcd |= 0x1 | (head ? 0x0 : 0x8);
452
453 /* Set the DACCLK register */
454 dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
455
456 if (nv_device(drm->device)->card_type == NV_40)
457 dacclk |= 0x1a << 16;
458
459 if (tv_norm->kind == CTV_ENC_MODE) {
460 dacclk |= 0x20;
461
462 if (head)
463 dacclk |= 0x100;
464 else
465 dacclk &= ~0x100;
466
467 } else {
468 dacclk |= 0x10;
469
470 }
471
472 NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
473}
474
475static void nv17_tv_mode_set(struct drm_encoder *encoder,
476 struct drm_display_mode *drm_mode,
477 struct drm_display_mode *adjusted_mode)
478{
479 struct drm_device *dev = encoder->dev;
480 struct nouveau_drm *drm = nouveau_drm(dev);
481 int head = nouveau_crtc(encoder->crtc)->index;
482 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];
483 struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
484 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
485 int i;
486
487 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
488 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
489 regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */
490 regs->tv_setup = 1;
491 regs->ramdac_8c0 = 0x0;
492
493 if (tv_norm->kind == TV_ENC_MODE) {
494 tv_regs->ptv_200 = 0x13111100;
495 if (head)
496 tv_regs->ptv_200 |= 0x10;
497
498 tv_regs->ptv_20c = 0x808010;
499 tv_regs->ptv_304 = 0x2d00000;
500 tv_regs->ptv_600 = 0x0;
501 tv_regs->ptv_60c = 0x0;
502 tv_regs->ptv_610 = 0x1e00000;
503
504 if (tv_norm->tv_enc_mode.vdisplay == 576) {
505 tv_regs->ptv_508 = 0x1200000;
506 tv_regs->ptv_614 = 0x33;
507
508 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
509 tv_regs->ptv_508 = 0xf00000;
510 tv_regs->ptv_614 = 0x13;
511 }
512
513 if (nv_device(drm->device)->card_type >= NV_30) {
514 tv_regs->ptv_500 = 0xe8e0;
515 tv_regs->ptv_504 = 0x1710;
516 tv_regs->ptv_604 = 0x0;
517 tv_regs->ptv_608 = 0x0;
518 } else {
519 if (tv_norm->tv_enc_mode.vdisplay == 576) {
520 tv_regs->ptv_604 = 0x20;
521 tv_regs->ptv_608 = 0x10;
522 tv_regs->ptv_500 = 0x19710;
523 tv_regs->ptv_504 = 0x68f0;
524
525 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
526 tv_regs->ptv_604 = 0x10;
527 tv_regs->ptv_608 = 0x20;
528 tv_regs->ptv_500 = 0x4b90;
529 tv_regs->ptv_504 = 0x1b480;
530 }
531 }
532
533 for (i = 0; i < 0x40; i++)
534 tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i];
535
536 } else {
537 const struct drm_display_mode *output_mode =
538 &tv_norm->ctv_enc_mode.mode;
539
540 /* The registers in PRAMDAC+0xc00 control some timings and CSC
541 * parameters for the CTV encoder (It's only used for "HD" TV
542 * modes, I don't think I have enough working to guess what
543 * they exactly mean...), it's probably connected at the
544 * output of the FP encoder, but it also needs the analog
545 * encoder in its OR enabled and routed to the head it's
546 * using. It's enabled with the DACCLK register, bits [5:4].
547 */
548 for (i = 0; i < 38; i++)
549 regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i];
550
551 regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
552 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
553 regs->fp_horiz_regs[FP_SYNC_START] =
554 output_mode->hsync_start - 1;
555 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
556 regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay +
557 max((output_mode->hdisplay-600)/40 - 1, 1);
558
559 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
560 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
561 regs->fp_vert_regs[FP_SYNC_START] =
562 output_mode->vsync_start - 1;
563 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
564 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;
565
566 regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
567 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
568 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
569
570 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
571 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
572 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
573 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
574
575 regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
576 NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
577 NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
578 NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
579 NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
580 NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
581 NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
582
583 regs->fp_debug_2 = 0;
584
585 regs->fp_margin_color = 0x801080;
586
587 }
588}
589
590static void nv17_tv_commit(struct drm_encoder *encoder)
591{
592 struct drm_device *dev = encoder->dev;
593 struct nouveau_drm *drm = nouveau_drm(dev);
594 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
595 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
596 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
597
598 if (get_tv_norm(encoder)->kind == TV_ENC_MODE) {
599 nv17_tv_update_rescaler(encoder);
600 nv17_tv_update_properties(encoder);
601 } else {
602 nv17_ctv_update_rescaler(encoder);
603 }
604
605 nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
606
607 /* This could use refinement for flatpanels, but it should work */
608 if (nv_device(drm->device)->chipset < 0x44)
609 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
610 nv04_dac_output_offset(encoder),
611 0xf0000000);
612 else
613 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
614 nv04_dac_output_offset(encoder),
615 0x00100000);
616
617 helper->dpms(encoder, DRM_MODE_DPMS_ON);
618
619 NV_INFO(drm, "Output %s is running on CRTC %d using output %c\n",
620 drm_get_connector_name(
621 &nouveau_encoder_connector_get(nv_encoder)->base),
622 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
623}
624
625static void nv17_tv_save(struct drm_encoder *encoder)
626{
627 struct drm_device *dev = encoder->dev;
628 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
629
630 nouveau_encoder(encoder)->restore.output =
631 NVReadRAMDAC(dev, 0,
632 NV_PRAMDAC_DACCLK +
633 nv04_dac_output_offset(encoder));
634
635 nv17_tv_state_save(dev, &tv_enc->saved_state);
636
637 tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200;
638}
639
640static void nv17_tv_restore(struct drm_encoder *encoder)
641{
642 struct drm_device *dev = encoder->dev;
643
644 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
645 nv04_dac_output_offset(encoder),
646 nouveau_encoder(encoder)->restore.output);
647
648 nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
649
650 nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED;
651}
652
653static int nv17_tv_create_resources(struct drm_encoder *encoder,
654 struct drm_connector *connector)
655{
656 struct drm_device *dev = encoder->dev;
657 struct nouveau_drm *drm = nouveau_drm(dev);
658 struct drm_mode_config *conf = &dev->mode_config;
659 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
660 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
661 int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS :
662 NUM_LD_TV_NORMS;
663 int i;
664
665 if (nouveau_tv_norm) {
666 for (i = 0; i < num_tv_norms; i++) {
667 if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) {
668 tv_enc->tv_norm = i;
669 break;
670 }
671 }
672
673 if (i == num_tv_norms)
674 NV_WARN(drm, "Invalid TV norm setting \"%s\"\n",
675 nouveau_tv_norm);
676 }
677
678 drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names);
679
680 drm_object_attach_property(&connector->base,
681 conf->tv_select_subconnector_property,
682 tv_enc->select_subconnector);
683 drm_object_attach_property(&connector->base,
684 conf->tv_subconnector_property,
685 tv_enc->subconnector);
686 drm_object_attach_property(&connector->base,
687 conf->tv_mode_property,
688 tv_enc->tv_norm);
689 drm_object_attach_property(&connector->base,
690 conf->tv_flicker_reduction_property,
691 tv_enc->flicker);
692 drm_object_attach_property(&connector->base,
693 conf->tv_saturation_property,
694 tv_enc->saturation);
695 drm_object_attach_property(&connector->base,
696 conf->tv_hue_property,
697 tv_enc->hue);
698 drm_object_attach_property(&connector->base,
699 conf->tv_overscan_property,
700 tv_enc->overscan);
701
702 return 0;
703}
704
705static int nv17_tv_set_property(struct drm_encoder *encoder,
706 struct drm_connector *connector,
707 struct drm_property *property,
708 uint64_t val)
709{
710 struct drm_mode_config *conf = &encoder->dev->mode_config;
711 struct drm_crtc *crtc = encoder->crtc;
712 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
713 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
714 bool modes_changed = false;
715
716 if (property == conf->tv_overscan_property) {
717 tv_enc->overscan = val;
718 if (encoder->crtc) {
719 if (tv_norm->kind == CTV_ENC_MODE)
720 nv17_ctv_update_rescaler(encoder);
721 else
722 nv17_tv_update_rescaler(encoder);
723 }
724
725 } else if (property == conf->tv_saturation_property) {
726 if (tv_norm->kind != TV_ENC_MODE)
727 return -EINVAL;
728
729 tv_enc->saturation = val;
730 nv17_tv_update_properties(encoder);
731
732 } else if (property == conf->tv_hue_property) {
733 if (tv_norm->kind != TV_ENC_MODE)
734 return -EINVAL;
735
736 tv_enc->hue = val;
737 nv17_tv_update_properties(encoder);
738
739 } else if (property == conf->tv_flicker_reduction_property) {
740 if (tv_norm->kind != TV_ENC_MODE)
741 return -EINVAL;
742
743 tv_enc->flicker = val;
744 if (encoder->crtc)
745 nv17_tv_update_rescaler(encoder);
746
747 } else if (property == conf->tv_mode_property) {
748 if (connector->dpms != DRM_MODE_DPMS_OFF)
749 return -EINVAL;
750
751 tv_enc->tv_norm = val;
752
753 modes_changed = true;
754
755 } else if (property == conf->tv_select_subconnector_property) {
756 if (tv_norm->kind != TV_ENC_MODE)
757 return -EINVAL;
758
759 tv_enc->select_subconnector = val;
760 nv17_tv_update_properties(encoder);
761
762 } else {
763 return -EINVAL;
764 }
765
766 if (modes_changed) {
767 drm_helper_probe_single_connector_modes(connector, 0, 0);
768
769 /* Disable the crtc to ensure a full modeset is
770 * performed whenever it's turned on again. */
771 if (crtc) {
772 struct drm_mode_set modeset = {
773 .crtc = crtc,
774 };
775
776 drm_mode_set_config_internal(&modeset);
777 }
778 }
779
780 return 0;
781}
782
783static void nv17_tv_destroy(struct drm_encoder *encoder)
784{
785 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
786
787 drm_encoder_cleanup(encoder);
788 kfree(tv_enc);
789}
790
791static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
792 .dpms = nv17_tv_dpms,
793 .save = nv17_tv_save,
794 .restore = nv17_tv_restore,
795 .mode_fixup = nv17_tv_mode_fixup,
796 .prepare = nv17_tv_prepare,
797 .commit = nv17_tv_commit,
798 .mode_set = nv17_tv_mode_set,
799 .detect = nv17_tv_detect,
800};
801
802static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
803 .get_modes = nv17_tv_get_modes,
804 .mode_valid = nv17_tv_mode_valid,
805 .create_resources = nv17_tv_create_resources,
806 .set_property = nv17_tv_set_property,
807};
808
809static struct drm_encoder_funcs nv17_tv_funcs = {
810 .destroy = nv17_tv_destroy,
811};
812
813int
814nv17_tv_create(struct drm_connector *connector, struct dcb_output *entry)
815{
816 struct drm_device *dev = connector->dev;
817 struct drm_encoder *encoder;
818 struct nv17_tv_encoder *tv_enc = NULL;
819
820 tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL);
821 if (!tv_enc)
822 return -ENOMEM;
823
824 tv_enc->overscan = 50;
825 tv_enc->flicker = 50;
826 tv_enc->saturation = 50;
827 tv_enc->hue = 0;
828 tv_enc->tv_norm = TV_NORM_PAL;
829 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
830 tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic;
831 tv_enc->pin_mask = 0;
832
833 encoder = to_drm_encoder(&tv_enc->base);
834
835 tv_enc->base.dcb = entry;
836 tv_enc->base.or = ffs(entry->or) - 1;
837
838 drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC);
839 drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs);
840 to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs;
841
842 encoder->possible_crtcs = entry->heads;
843 encoder->possible_clones = 0;
844
845 nv17_tv_create_resources(encoder, connector);
846 drm_mode_connector_attach_encoder(connector, encoder);
847 return 0;
848}
849