1/* $NetBSD: if_etreg.h,v 1.1 2010/11/13 00:47:25 jnemeth Exp $ */
2/* $OpenBSD: if_etreg.h,v 1.3 2008/06/08 06:18:07 jsg Exp $ */
3
4/*
5 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
6 *
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in
18 * the documentation and/or other materials provided with the
19 * distribution.
20 * 3. Neither the name of The DragonFly Project nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific, prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
28 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
29 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
30 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
32 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * $DragonFly: src/sys/dev/netif/et/if_etreg.h,v 1.1 2007/10/12 14:12:42 sephe Exp $
38 */
39
40#ifndef _IF_ETREG_H
41#define _IF_ETREG_H
42
43#define ET_INTERN_MEM_SIZE 0x400
44#define ET_INTERN_MEM_END (ET_INTERN_MEM_SIZE - 1)
45
46/*
47 * PCI registers
48 *
49 * ET_PCIV_ACK_LATENCY_{128,256} are from
50 * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-5
51 *
52 * ET_PCIV_REPLAY_TIMER_{128,256} are from
53 * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-4
54 */
55#define ET_PCIR_BAR 0x10
56
57#define ET_PCIR_DEVICE_CAPS 0x4c
58#define ET_PCIM_DEVICE_CAPS_MAX_PLSZ 0x7 /* Max playload size */
59#define ET_PCIV_DEVICE_CAPS_PLSZ_128 0x0
60#define ET_PCIV_DEVICE_CAPS_PLSZ_256 0x1
61
62#define ET_PCIR_DEVICE_CTRL 0x50
63#define ET_PCIM_DEVICE_CTRL_MAX_RRSZ 0x7000 /* Max read request size */
64#define ET_PCIV_DEVICE_CTRL_RRSZ_2K 0x4000
65
66#define ET_PCIR_MACADDR_LO 0xa4
67#define ET_PCIR_MACADDR_HI 0xa8
68
69#define ET_PCIR_EEPROM_MISC 0xb0
70#define ET_PCIR_EEPROM_STATUS_MASK 0x0000ff00
71#define ET_PCIM_EEPROM_STATUS_ERROR 0x00004c00
72
73#define ET_PCIR_ACK_LATENCY 0xc0
74#define ET_PCIV_ACK_LATENCY_128 237
75#define ET_PCIV_ACK_LATENCY_256 416
76
77#define ET_PCIR_REPLAY_TIMER 0xc2
78#define ET_REPLAY_TIMER_RX_L0S_ADJ 250 /* XXX infered from default */
79#define ET_PCIV_REPLAY_TIMER_128 (711 + ET_REPLAY_TIMER_RX_L0S_ADJ)
80#define ET_PCIV_REPLAY_TIMER_256 (1248 + ET_REPLAY_TIMER_RX_L0S_ADJ)
81
82#define ET_PCIR_L0S_L1_LATENCY 0xcf
83#define ET_PCIM_L0S_LATENCY (7 << 0)
84#define ET_PCIM_L1_LATENCY (7 << 3)
85
86/*
87 * CSR
88 */
89#define ET_TXQ_START 0x0000
90#define ET_TXQ_END 0x0004
91#define ET_RXQ_START 0x0008
92#define ET_RXQ_END 0x000c
93
94#define ET_PM 0x0010
95#define ET_PM_SYSCLK_GATE (1 << 3)
96#define ET_PM_TXCLK_GATE (1 << 4)
97#define ET_PM_RXCLK_GATE (1 << 5)
98
99#define ET_INTR_STATUS 0x0018
100#define ET_INTR_MASK 0x001c
101
102#define ET_SWRST 0x0028
103#define ET_SWRST_TXDMA (1 << 0)
104#define ET_SWRST_RXDMA (1 << 1)
105#define ET_SWRST_TXMAC (1 << 2)
106#define ET_SWRST_RXMAC (1 << 3)
107#define ET_SWRST_MAC (1 << 4)
108#define ET_SWRST_MAC_STAT (1 << 5)
109#define ET_SWRST_MMC (1 << 6)
110#define ET_SWRST_SELFCLR_DISABLE (1 << 31)
111
112#define ET_MSI_CFG 0x0030
113
114#define ET_LOOPBACK 0x0034
115
116#define ET_TIMER 0x0038
117
118#define ET_TXDMA_CTRL 0x1000
119#define ET_TXDMA_CTRL_HALT (1 << 0)
120#define ET_TXDMA_CTRL_CACHE_THR 0xf0
121#define ET_TXDMA_CTRL_SINGLE_EPKT (1 << 8)
122
123#define ET_TX_RING_HI 0x1004
124#define ET_TX_RING_LO 0x1008
125#define ET_TX_RING_CNT 0x100c
126
127#define ET_TX_STATUS_HI 0x101c
128#define ET_TX_STATUS_LO 0x1020
129
130#define ET_TX_READY_POS 0x1024
131#define ET_TX_READY_POS_INDEX 0x03ff
132#define ET_TX_READY_POS_WRAP (1 << 10)
133
134#define ET_TX_DONE_POS 0x1060
135#define ET_TX_DONE_POS_INDEX 0x03ff
136#define ET_TX_DONE_POS_WRAP (1 << 10)
137
138#define ET_RXDMA_CTRL 0x2000
139#define ET_RXDMA_CTRL_HALT (1 << 0)
140#define ET_RXDMA_CTRL_RING0_SIZE (3 << 8)
141#define ET_RXDMA_CTRL_RING0_ENABLE (1 << 10)
142#define ET_RXDMA_CTRL_RING1_SIZE (3 << 11)
143#define ET_RXDMA_CTRL_RING1_ENABLE (1 << 13)
144#define ET_RXDMA_CTRL_HALTED (1 << 17)
145
146#define ET_RX_STATUS_LO 0x2004
147#define ET_RX_STATUS_HI 0x2008
148
149#define ET_RX_INTR_NPKTS 0x200c
150#define ET_RX_INTR_DELAY 0x2010
151
152#define ET_RXSTAT_LO 0x2020
153#define ET_RXSTAT_HI 0x2024
154#define ET_RXSTAT_CNT 0x2028
155
156#define ET_RXSTAT_POS 0x2030
157#define ET_RXSTAT_POS_INDEX 0x0fff
158#define ET_RXSTAT_POS_WRAP (1 << 12)
159
160#define ET_RXSTAT_MINCNT 0x2038
161
162#define ET_RX_RING0_LO 0x203c
163#define ET_RX_RING0_HI 0x2040
164#define ET_RX_RING0_CNT 0x2044
165
166#define ET_RX_RING0_POS 0x204c
167#define ET_RX_RING0_POS_INDEX 0x03ff
168#define ET_RX_RING0_POS_WRAP (1 << 10)
169
170#define ET_RX_RING0_MINCNT 0x2054
171
172#define ET_RX_RING1_LO 0x2058
173#define ET_RX_RING1_HI 0x205c
174#define ET_RX_RING1_CNT 0x2060
175
176#define ET_RX_RING1_POS 0x2068
177#define ET_RX_RING1_POS_INDEX 0x03ff
178#define ET_RX_RING1_POS_WRAP (1 << 10)
179
180#define ET_RX_RING1_MINCNT 0x2070
181
182#define ET_TXMAC_CTRL 0x3000
183#define ET_TXMAC_CTRL_ENABLE (1 << 0)
184#define ET_TXMAC_CTRL_FC_DISABLE (1 << 3)
185
186#define ET_TXMAC_FLOWCTRL 0x3010
187
188#define ET_RXMAC_CTRL 0x4000
189#define ET_RXMAC_CTRL_ENABLE (1 << 0)
190#define ET_RXMAC_CTRL_NO_PKTFILT (1 << 2)
191#define ET_RXMAC_CTRL_WOL_DISABLE (1 << 3)
192
193#define ET_WOL_CRC 0x4004
194#define ET_WOL_SA_LO 0x4010
195#define ET_WOL_SA_HI 0x4014
196#define ET_WOL_MASK 0x4018
197
198#define ET_UCAST_FILTADDR1 0x4068
199#define ET_UCAST_FILTADDR2 0x406c
200#define ET_UCAST_FILTADDR3 0x4070
201
202#define ET_MULTI_HASH 0x4074
203
204#define ET_PKTFILT 0x4084
205#define ET_PKTFILT_BCAST (1 << 0)
206#define ET_PKTFILT_MCAST (1 << 1)
207#define ET_PKTFILT_UCAST (1 << 2)
208#define ET_PKTFILT_FRAG (1 << 3)
209#define ET_PKTFILT_MINLEN 0x7f0000
210
211#define ET_RXMAC_MC_SEGSZ 0x4088
212#define ET_RXMAC_MC_SEGSZ_ENABLE (1 << 0)
213#define ET_RXMAC_MC_SEGSZ_FC (1 << 1)
214#define ET_RXMAC_MC_SEGSZ_MAX 0x03fc
215
216#define ET_RXMAC_MC_WATERMARK 0x408c
217#define ET_RXMAC_SPACE_AVL 0x4094
218
219#define ET_RXMAC_MGT 0x4098
220#define ET_RXMAC_MGT_PASS_ECRC (1 << 4)
221#define ET_RXMAC_MGT_PASS_ELEN (1 << 5)
222#define ET_RXMAC_MGT_PASS_ETRUNC (1 << 16)
223#define ET_RXMAC_MGT_CHECK_PKT (1 << 17)
224
225#define ET_MAC_CFG1 0x5000
226#define ET_MAC_CFG1_TXEN (1 << 0)
227#define ET_MAC_CFG1_SYNC_TXEN (1 << 1)
228#define ET_MAC_CFG1_RXEN (1 << 2)
229#define ET_MAC_CFG1_SYNC_RXEN (1 << 3)
230#define ET_MAC_CFG1_TXFLOW (1 << 4)
231#define ET_MAC_CFG1_RXFLOW (1 << 5)
232#define ET_MAC_CFG1_LOOPBACK (1 << 8)
233#define ET_MAC_CFG1_RST_TXFUNC (1 << 16)
234#define ET_MAC_CFG1_RST_RXFUNC (1 << 17)
235#define ET_MAC_CFG1_RST_TXMC (1 << 18)
236#define ET_MAC_CFG1_RST_RXMC (1 << 19)
237#define ET_MAC_CFG1_SIM_RST (1 << 30)
238#define ET_MAC_CFG1_SOFT_RST (1 << 31)
239
240#define ET_MAC_CFG2 0x5004
241#define ET_MAC_CFG2_FDX (1 << 0)
242#define ET_MAC_CFG2_CRC (1 << 1)
243#define ET_MAC_CFG2_PADCRC (1 << 2)
244#define ET_MAC_CFG2_LENCHK (1 << 4)
245#define ET_MAC_CFG2_BIGFRM (1 << 5)
246#define ET_MAC_CFG2_MODE_MII (1 << 8)
247#define ET_MAC_CFG2_MODE_GMII (1 << 9)
248#define ET_MAC_CFG2_PREAMBLE_LEN 0xf000
249
250#define ET_IPG 0x5008
251#define ET_IPG_B2B 0x0000007f
252#define ET_IPG_MINIFG 0x0000ff00
253#define ET_IPG_NONB2B_2 0x007f0000
254#define ET_IPG_NONB2B_1 0x7f000000
255
256#define ET_MAC_HDX 0x500c
257#define ET_MAC_HDX_COLLWIN 0x0003ff
258#define ET_MAC_HDX_REXMIT_MAX 0x00f000
259#define ET_MAC_HDX_REXMIT_MAX 0x00f000
260#define ET_MAC_HDX_EXC_DEFER (1 << 16)
261#define ET_MAC_HDX_NOBACKOFF (1 << 17)
262#define ET_MAC_HDX_BP_NOBACKOFF (1 << 18)
263#define ET_MAC_HDX_ALT_BEB (1 << 19)
264#define ET_MAC_HDX_ALT_BEB_TRUNC 0xf00000
265
266#define ET_MAX_FRMLEN 0x5010
267
268#define ET_MII_CFG 0x5020
269#define ET_MII_CFG_CLKRST (7 << 0)
270#define ET_MII_CFG_PREAMBLE_SUP (1 << 4)
271#define ET_MII_CFG_SCAN_AUTOINC (1 << 5)
272#define ET_MII_CFG_RST (1 << 31)
273
274#define ET_MII_CMD 0x5024
275#define ET_MII_CMD_READ (1 << 0)
276
277#define ET_MII_ADDR 0x5028
278#define ET_MII_ADDR_REG 0x001f
279#define ET_MII_ADDR_PHY 0x1f00
280#define ET_MII_ADDR_SHIFT 8
281
282
283#define ET_MII_CTRL 0x502c
284#define ET_MII_CTRL_VALUE 0xffff
285
286#define ET_MII_STAT 0x5030
287#define ET_MII_STAT_VALUE 0xffff
288
289#define ET_MII_IND 0x5034
290#define ET_MII_IND_BUSY (1 << 0)
291#define ET_MII_IND_INVALID (1 << 2)
292
293#define ET_MAC_CTRL 0x5038
294#define ET_MAC_CTRL_MODE_MII (1 << 24)
295#define ET_MAC_CTRL_LHDX (1 << 25)
296#define ET_MAC_CTRL_GHDX (1 << 26)
297
298#define ET_MAC_ADDR1 0x5040
299#define ET_MAC_ADDR2 0x5044
300
301#define ET_MMC_CTRL 0x7000
302#define ET_MMC_CTRL_ENABLE (1 << 0)
303#define ET_MMC_CTRL_ARB_DISABLE (1 << 1)
304#define ET_MMC_CTRL_RXMAC_DISABLE (1 << 2)
305#define ET_MMC_CTRL_TXMAC_DISABLE (1 << 3)
306#define ET_MMC_CTRL_TXDMA_DISABLE (1 << 4)
307#define ET_MMC_CTRL_RXDMA_DISABLE (1 << 5)
308#define ET_MMC_CTRL_FORCE_CE (1 << 6)
309
310/*
311 * Interrupts
312 */
313#define ET_INTR_TXEOF (1 << 3)
314#define ET_INTR_TXDMA_ERROR (1 << 4)
315#define ET_INTR_RXEOF (1 << 5)
316#define ET_INTR_RXRING0_LOW (1 << 6)
317#define ET_INTR_RXRING1_LOW (1 << 7)
318#define ET_INTR_RXSTAT_LOW (1 << 8)
319#define ET_INTR_RXDMA_ERROR (1 << 9)
320#define ET_INTR_TIMER (1 << 10)
321#define ET_INTR_WOL (1 << 15)
322#define ET_INTR_PHY (1 << 16)
323#define ET_INTR_TXMAC (1 << 17)
324#define ET_INTR_RXMAC (1 << 18)
325#define ET_INTR_MAC_STATS (1 << 19)
326#define ET_INTR_SLAVE_TO (1 << 20)
327
328#define ET_INTRS (ET_INTR_TXEOF | \
329 ET_INTR_RXEOF | \
330 ET_INTR_TIMER)
331
332/*
333 * RX ring position uses same layout
334 */
335#define ET_RX_RING_POS_INDEX (0x03ff << 0)
336#define ET_RX_RING_POS_WRAP (1 << 10)
337
338
339/* $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.1 2007/10/12 14:12:42 sephe Exp $ */
340
341#define ET_ALIGN 0x1000
342#define ET_NSEG_MAX 32 /* XXX no limit actually */
343#define ET_NSEG_SPARE 5
344
345#define ET_TX_NDESC 512
346#define ET_RX_NDESC 512
347#define ET_RX_NRING 2
348#define ET_RX_NSTAT (ET_RX_NRING * ET_RX_NDESC)
349
350#define ET_TX_RING_SIZE (ET_TX_NDESC * sizeof(struct et_txdesc))
351#define ET_RX_RING_SIZE (ET_RX_NDESC * sizeof(struct et_rxdesc))
352#define ET_RXSTAT_RING_SIZE (ET_RX_NSTAT * sizeof(struct et_rxstat))
353
354#define CSR_WRITE_4(sc, reg, val) \
355 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
356#define CSR_READ_4(sc, reg) \
357 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
358
359#define ET_ADDR_HI(addr) ((uint64_t) (addr) >> 32)
360#define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff)
361
362struct et_txdesc {
363 uint32_t td_addr_hi;
364 uint32_t td_addr_lo;
365 uint32_t td_ctrl1; /* ET_TDCTRL1_ */
366 uint32_t td_ctrl2; /* ET_TDCTRL2_ */
367} __packed;
368
369#define ET_TDCTRL1_LEN 0xffff
370
371#define ET_TDCTRL2_LAST_FRAG (1 << 0)
372#define ET_TDCTRL2_FIRST_FRAG (1 << 1)
373#define ET_TDCTRL2_INTR (1 << 2)
374
375struct et_rxdesc {
376 uint32_t rd_addr_lo;
377 uint32_t rd_addr_hi;
378 uint32_t rd_ctrl; /* ET_RDCTRL_ */
379} __packed;
380
381#define ET_RDCTRL_BUFIDX 0x03ff
382
383struct et_rxstat {
384 uint32_t rxst_info1;
385 uint32_t rxst_info2; /* ET_RXST_INFO2_ */
386} __packed;
387
388#define ET_RXST_INFO2_LEN 0x000ffff
389#define ET_RXST_INFO2_BUFIDX 0x3ff0000
390#define ET_RXST_INFO2_RINGIDX (3 << 26)
391
392struct et_rxstatus {
393 uint32_t rxs_ring;
394 uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */
395} __packed;
396
397#define ET_RXS_STATRING_INDEX 0xfff0000
398#define ET_RXS_STATRING_WRAP (1 << 28)
399
400struct et_txbuf {
401 struct mbuf *tb_mbuf;
402 bus_dmamap_t tb_dmap;
403 bus_dma_segment_t tb_seg;
404};
405
406struct et_rxbuf {
407 struct mbuf *rb_mbuf;
408 bus_dmamap_t rb_dmap;
409 bus_dma_segment_t rb_seg;
410 bus_addr_t rb_paddr;
411};
412
413struct et_txstatus_data {
414 uint32_t *txsd_status;
415 bus_addr_t txsd_paddr;
416 bus_dma_tag_t txsd_dtag;
417 bus_dmamap_t txsd_dmap;
418 bus_dma_segment_t txsd_seg;
419};
420
421struct et_rxstatus_data {
422 struct et_rxstatus *rxsd_status;
423 bus_addr_t rxsd_paddr;
424 bus_dma_tag_t rxsd_dtag;
425 bus_dmamap_t rxsd_dmap;
426 bus_dma_segment_t rxsd_seg;
427};
428
429struct et_rxstat_ring {
430 struct et_rxstat *rsr_stat;
431 bus_addr_t rsr_paddr;
432 bus_dma_tag_t rsr_dtag;
433 bus_dmamap_t rsr_dmap;
434 bus_dma_segment_t rsr_seg;
435
436 int rsr_index;
437 int rsr_wrap;
438};
439
440struct et_txdesc_ring {
441 struct et_txdesc *tr_desc;
442 bus_addr_t tr_paddr;
443 bus_dma_tag_t tr_dtag;
444 bus_dmamap_t tr_dmap;
445 bus_dma_segment_t tr_seg;
446
447 int tr_ready_index;
448 int tr_ready_wrap;
449};
450
451struct et_rxdesc_ring {
452 struct et_rxdesc *rr_desc;
453 bus_addr_t rr_paddr;
454 bus_dma_tag_t rr_dtag;
455 bus_dmamap_t rr_dmap;
456 bus_dma_segment_t rr_seg;
457
458 uint32_t rr_posreg;
459 int rr_index;
460 int rr_wrap;
461};
462
463struct et_txbuf_data {
464 struct et_txbuf tbd_buf[ET_TX_NDESC];
465
466 int tbd_start_index;
467 int tbd_start_wrap;
468 int tbd_used;
469};
470
471struct et_softc;
472struct et_rxbuf_data;
473typedef int (*et_newbuf_t)(struct et_rxbuf_data *, int, int);
474
475struct et_rxbuf_data {
476 struct et_rxbuf rbd_buf[ET_RX_NDESC];
477
478 struct et_softc *rbd_softc;
479 struct et_rxdesc_ring *rbd_ring;
480
481 int rbd_bufsize;
482 et_newbuf_t rbd_newbuf;
483};
484
485struct et_softc {
486 device_t sc_dev;
487 struct ethercom sc_ethercom;
488 uint8_t sc_enaddr[ETHER_ADDR_LEN];
489 int sc_if_flags;
490
491 int sc_mem_rid;
492 struct resource *sc_mem_res;
493 bus_space_tag_t sc_mem_bt;
494 bus_space_handle_t sc_mem_bh;
495 bus_size_t sc_mem_size;
496 bus_dma_tag_t sc_dmat;
497 pci_chipset_tag_t sc_pct;
498 pcitag_t sc_pcitag;
499
500 int sc_irq_rid;
501 struct resource *sc_irq_res;
502 void *sc_irq_handle;
503
504 struct mii_data sc_miibus;
505 callout_t sc_tick;
506
507 struct et_rxdesc_ring sc_rx_ring[ET_RX_NRING];
508 struct et_rxstat_ring sc_rxstat_ring;
509 struct et_rxstatus_data sc_rx_status;
510
511 struct et_txdesc_ring sc_tx_ring;
512 struct et_txstatus_data sc_tx_status;
513 callout_t sc_txtick;
514
515 bus_dmamap_t sc_mbuf_tmp_dmap;
516 struct et_rxbuf_data sc_rx_data[ET_RX_NRING];
517 struct et_txbuf_data sc_tx_data;
518
519 uint32_t sc_tx;
520 uint32_t sc_tx_intr;
521
522 /*
523 * Sysctl variables
524 */
525 int sc_rx_intr_npkts;
526 int sc_rx_intr_delay;
527 int sc_tx_intr_nsegs;
528 uint32_t sc_timer;
529};
530
531#endif /* !_IF_ETREG_H */
532