1 | /* $NetBSD: piixide.c,v 1.65 2016/02/01 08:28:48 msaitoh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
9 | * 1. Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * 2. Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
14 | * |
15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
18 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
22 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.65 2016/02/01 08:28:48 msaitoh Exp $" ); |
29 | |
30 | #include <sys/param.h> |
31 | #include <sys/systm.h> |
32 | |
33 | #include <dev/pci/pcivar.h> |
34 | #include <dev/pci/pcidevs.h> |
35 | #include <dev/pci/pciidereg.h> |
36 | #include <dev/pci/pciidevar.h> |
37 | #include <dev/pci/pciide_piix_reg.h> |
38 | |
39 | static void piix_chip_map(struct pciide_softc*, |
40 | const struct pci_attach_args *); |
41 | static void piix_setup_channel(struct ata_channel *); |
42 | static void piix3_4_setup_channel(struct ata_channel *); |
43 | static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); |
44 | static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); |
45 | static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); |
46 | static void piixsata_chip_map(struct pciide_softc*, |
47 | const struct pci_attach_args *); |
48 | static int piix_dma_init(void *, int, int, void *, size_t, int); |
49 | |
50 | static bool piixide_resume(device_t, const pmf_qual_t *); |
51 | static bool piixide_suspend(device_t, const pmf_qual_t *); |
52 | static int piixide_match(device_t, cfdata_t, void *); |
53 | static void piixide_attach(device_t, device_t, void *); |
54 | |
55 | static const struct pciide_product_desc pciide_intel_products[] = { |
56 | { PCI_PRODUCT_INTEL_82092AA, |
57 | 0, |
58 | "Intel 82092AA IDE controller" , |
59 | default_chip_map, |
60 | }, |
61 | { PCI_PRODUCT_INTEL_82371FB_IDE, |
62 | 0, |
63 | "Intel 82371FB IDE controller (PIIX)" , |
64 | piix_chip_map, |
65 | }, |
66 | { PCI_PRODUCT_INTEL_82371SB_IDE, |
67 | 0, |
68 | "Intel 82371SB IDE Interface (PIIX3)" , |
69 | piix_chip_map, |
70 | }, |
71 | { PCI_PRODUCT_INTEL_82371AB_IDE, |
72 | 0, |
73 | "Intel 82371AB IDE controller (PIIX4)" , |
74 | piix_chip_map, |
75 | }, |
76 | { PCI_PRODUCT_INTEL_82440MX_IDE, |
77 | 0, |
78 | "Intel 82440MX IDE controller" , |
79 | piix_chip_map |
80 | }, |
81 | { PCI_PRODUCT_INTEL_82801AA_IDE, |
82 | 0, |
83 | "Intel 82801AA IDE Controller (ICH)" , |
84 | piix_chip_map, |
85 | }, |
86 | { PCI_PRODUCT_INTEL_82801AB_IDE, |
87 | 0, |
88 | "Intel 82801AB IDE Controller (ICH0)" , |
89 | piix_chip_map, |
90 | }, |
91 | { PCI_PRODUCT_INTEL_82801BA_IDE, |
92 | 0, |
93 | "Intel 82801BA IDE Controller (ICH2)" , |
94 | piix_chip_map, |
95 | }, |
96 | { PCI_PRODUCT_INTEL_82801BAM_IDE, |
97 | 0, |
98 | "Intel 82801BAM IDE Controller (ICH2-M)" , |
99 | piix_chip_map, |
100 | }, |
101 | { PCI_PRODUCT_INTEL_82801CA_IDE_1, |
102 | 0, |
103 | "Intel 82801CA IDE Controller (ICH3)" , |
104 | piix_chip_map, |
105 | }, |
106 | { PCI_PRODUCT_INTEL_82801CA_IDE_2, |
107 | 0, |
108 | "Intel 82801CA IDE Controller (ICH3)" , |
109 | piix_chip_map, |
110 | }, |
111 | { PCI_PRODUCT_INTEL_82801DB_IDE, |
112 | 0, |
113 | "Intel 82801DB IDE Controller (ICH4)" , |
114 | piix_chip_map, |
115 | }, |
116 | { PCI_PRODUCT_INTEL_82801DBM_IDE, |
117 | 0, |
118 | "Intel 82801DBM IDE Controller (ICH4-M)" , |
119 | piix_chip_map, |
120 | }, |
121 | { PCI_PRODUCT_INTEL_82801EB_IDE, |
122 | 0, |
123 | "Intel 82801EB IDE Controller (ICH5)" , |
124 | piix_chip_map, |
125 | }, |
126 | { PCI_PRODUCT_INTEL_82801EB_SATA, |
127 | 0, |
128 | "Intel 82801EB Serial ATA Controller" , |
129 | piixsata_chip_map, |
130 | }, |
131 | { PCI_PRODUCT_INTEL_82801ER_SATA, |
132 | 0, |
133 | "Intel 82801ER Serial ATA/Raid Controller" , |
134 | piixsata_chip_map, |
135 | }, |
136 | { PCI_PRODUCT_INTEL_6300ESB_IDE, |
137 | 0, |
138 | "Intel 6300ESB IDE Controller (ICH5)" , |
139 | piix_chip_map, |
140 | }, |
141 | { PCI_PRODUCT_INTEL_6300ESB_SATA, |
142 | 0, |
143 | "Intel 6300ESB Serial ATA Controller" , |
144 | piixsata_chip_map, |
145 | }, |
146 | { PCI_PRODUCT_INTEL_6300ESB_RAID, |
147 | 0, |
148 | "Intel 6300ESB Serial ATA/RAID Controller" , |
149 | piixsata_chip_map, |
150 | }, |
151 | { PCI_PRODUCT_INTEL_82801FB_IDE, |
152 | 0, |
153 | "Intel 82801FB IDE Controller (ICH6)" , |
154 | piix_chip_map, |
155 | }, |
156 | { PCI_PRODUCT_INTEL_82801FB_SATA, |
157 | 0, |
158 | "Intel 82801FB Serial ATA/Raid Controller" , |
159 | piixsata_chip_map, |
160 | }, |
161 | { PCI_PRODUCT_INTEL_82801FR_SATA, |
162 | 0, |
163 | "Intel 82801FR Serial ATA/Raid Controller" , |
164 | piixsata_chip_map, |
165 | }, |
166 | { PCI_PRODUCT_INTEL_82801FBM_SATA, |
167 | 0, |
168 | "Intel 82801FBM Serial ATA Controller (ICH6)" , |
169 | piixsata_chip_map, |
170 | }, |
171 | { PCI_PRODUCT_INTEL_82801G_IDE, |
172 | 0, |
173 | "Intel 82801GB/GR IDE Controller (ICH7)" , |
174 | piix_chip_map, |
175 | }, |
176 | { PCI_PRODUCT_INTEL_82801G_SATA, |
177 | 0, |
178 | "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)" , |
179 | piixsata_chip_map, |
180 | }, |
181 | { PCI_PRODUCT_INTEL_82801GBM_SATA, |
182 | 0, |
183 | "Intel 82801GBM/GHM Serial ATA Controller (ICH7)" , |
184 | piixsata_chip_map, |
185 | }, |
186 | { PCI_PRODUCT_INTEL_82801H_SATA_1, |
187 | 0, |
188 | "Intel 82801H Serial ATA Controller (ICH8)" , |
189 | piixsata_chip_map, |
190 | }, |
191 | { PCI_PRODUCT_INTEL_82801H_SATA_RAID, |
192 | 0, |
193 | "Intel 82801H Serial ATA RAID Controller (ICH8)" , |
194 | piixsata_chip_map, |
195 | }, |
196 | { PCI_PRODUCT_INTEL_82801H_SATA_2, |
197 | 0, |
198 | "Intel 82801H Serial ATA Controller (ICH8)" , |
199 | piixsata_chip_map, |
200 | }, |
201 | { PCI_PRODUCT_INTEL_82801HBM_IDE, |
202 | 0, |
203 | "Intel 82801HBM IDE Controller (ICH8M)" , |
204 | piix_chip_map, |
205 | }, |
206 | { PCI_PRODUCT_INTEL_82801HBM_SATA_AHCI, |
207 | 0, |
208 | "Intel 82801HBM Serial ATA AHCI Controller (ICH8M)" , |
209 | piixsata_chip_map, |
210 | }, |
211 | { PCI_PRODUCT_INTEL_82801HBM_SATA_RAID, |
212 | 0, |
213 | "Intel 82801HBM Serial ATA RAID Controller (ICH8M)" , |
214 | piixsata_chip_map, |
215 | }, |
216 | { PCI_PRODUCT_INTEL_82801HEM_SATA, |
217 | 0, |
218 | "Intel 82801HEM Serial ATA Controller (ICH8M)" , |
219 | piixsata_chip_map, |
220 | }, |
221 | { PCI_PRODUCT_INTEL_63XXESB_IDE, |
222 | 0, |
223 | "Intel 631xESB/632xESB IDE Controller" , |
224 | piix_chip_map, |
225 | }, |
226 | { PCI_PRODUCT_INTEL_82801I_SATA_1, |
227 | 0, |
228 | "Intel 82801I Serial ATA Controller (ICH9)" , |
229 | piixsata_chip_map, |
230 | }, |
231 | { PCI_PRODUCT_INTEL_82801I_SATA_2, |
232 | 0, |
233 | "Intel 82801I Serial ATA Controller (ICH9)" , |
234 | piixsata_chip_map, |
235 | }, |
236 | { PCI_PRODUCT_INTEL_82801I_SATA_3, |
237 | 0, |
238 | "Intel 82801I Serial ATA Controller (ICH9)" , |
239 | piixsata_chip_map, |
240 | }, |
241 | { PCI_PRODUCT_INTEL_82801I_SATA_4, |
242 | 0, |
243 | "Intel 82801I Mobile Serial ATA Controller (ICH9)" , |
244 | piixsata_chip_map, |
245 | }, |
246 | { PCI_PRODUCT_INTEL_82801I_SATA_5, |
247 | 0, |
248 | "Intel 82801I Mobile Serial ATA Controller (ICH9)" , |
249 | piixsata_chip_map, |
250 | }, |
251 | { PCI_PRODUCT_INTEL_82801I_SATA_6, |
252 | 0, |
253 | "Intel 82801I Mobile Serial ATA Controller (ICH9)" , |
254 | piixsata_chip_map, |
255 | }, |
256 | { PCI_PRODUCT_INTEL_82801I_SATA_7, |
257 | 0, |
258 | "Intel 82801I Mobile Serial ATA Controller (ICH9)" , |
259 | piixsata_chip_map, |
260 | }, |
261 | { PCI_PRODUCT_INTEL_63XXESB_SATA, |
262 | 0, |
263 | "Intel 631xESB/632xESB Serial ATA Controller" , |
264 | piixsata_chip_map, |
265 | }, |
266 | { PCI_PRODUCT_INTEL_82801JD_SATA_IDE2, |
267 | 0, |
268 | "Intel 82801JD Serial ATA Controller (ICH10)" , |
269 | piixsata_chip_map, |
270 | }, |
271 | { PCI_PRODUCT_INTEL_82801JI_SATA_IDE2, |
272 | 0, |
273 | "Intel 82801JI Serial ATA Controller (ICH10)" , |
274 | piixsata_chip_map, |
275 | }, |
276 | { PCI_PRODUCT_INTEL_82801JD_SATA_IDE, |
277 | 0, |
278 | "Intel 82801JD Serial ATA Controller (ICH10)" , |
279 | piixsata_chip_map, |
280 | }, |
281 | { PCI_PRODUCT_INTEL_82801JI_SATA_IDE, |
282 | 0, |
283 | "Intel 82801JI Serial ATA Controller (ICH10)" , |
284 | piixsata_chip_map, |
285 | }, |
286 | { |
287 | PCI_PRODUCT_INTEL_82965PM_IDE, |
288 | 0, |
289 | "Intel 82965PM IDE controller" , |
290 | piixsata_chip_map, |
291 | }, |
292 | { |
293 | PCI_PRODUCT_INTEL_3400_SATA_1, |
294 | 0, |
295 | "Intel 3400 Serial ATA Controller" , |
296 | piixsata_chip_map, |
297 | }, |
298 | { |
299 | PCI_PRODUCT_INTEL_3400_SATA_1, |
300 | 0, |
301 | "Intel 3400 Serial ATA Controller" , |
302 | piixsata_chip_map, |
303 | }, |
304 | { |
305 | PCI_PRODUCT_INTEL_3400_SATA_2, |
306 | 0, |
307 | "Intel 3400 Serial ATA Controller" , |
308 | piixsata_chip_map, |
309 | }, |
310 | { |
311 | PCI_PRODUCT_INTEL_3400_SATA_3, |
312 | 0, |
313 | "Intel 3400 Serial ATA Controller" , |
314 | piixsata_chip_map, |
315 | }, |
316 | { |
317 | PCI_PRODUCT_INTEL_3400_SATA_4, |
318 | 0, |
319 | "Intel 3400 Serial ATA Controller" , |
320 | piixsata_chip_map, |
321 | }, |
322 | { |
323 | PCI_PRODUCT_INTEL_3400_SATA_5, |
324 | 0, |
325 | "Intel 3400 Serial ATA Controller" , |
326 | piixsata_chip_map, |
327 | }, |
328 | { |
329 | PCI_PRODUCT_INTEL_3400_SATA_6, |
330 | 0, |
331 | "Intel 3400 Serial ATA Controller" , |
332 | piixsata_chip_map, |
333 | }, |
334 | { |
335 | PCI_PRODUCT_INTEL_6SERIES_SATA_1, |
336 | 0, |
337 | "Intel 6 Series Serial ATA Controller" , |
338 | piixsata_chip_map, |
339 | }, |
340 | { |
341 | PCI_PRODUCT_INTEL_6SERIES_SATA_2, |
342 | 0, |
343 | "Intel 6 Series Serial ATA Controller" , |
344 | piixsata_chip_map, |
345 | }, |
346 | { |
347 | PCI_PRODUCT_INTEL_6SERIES_SATA_3, |
348 | 0, |
349 | "Intel 6 Series Serial ATA Controller" , |
350 | piixsata_chip_map, |
351 | }, |
352 | { |
353 | PCI_PRODUCT_INTEL_6SERIES_SATA_4, |
354 | 0, |
355 | "Intel 6 Series Serial ATA Controller" , |
356 | piixsata_chip_map, |
357 | }, |
358 | { 0, |
359 | 0, |
360 | NULL, |
361 | NULL |
362 | } |
363 | }; |
364 | |
365 | CFATTACH_DECL_NEW(piixide, sizeof(struct pciide_softc), |
366 | piixide_match, piixide_attach, pciide_detach, NULL); |
367 | |
368 | static int |
369 | piixide_match(device_t parent, cfdata_t match, void *aux) |
370 | { |
371 | struct pci_attach_args *pa = aux; |
372 | |
373 | if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { |
374 | if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) |
375 | return (2); |
376 | } |
377 | return (0); |
378 | } |
379 | |
380 | static void |
381 | piixide_attach(device_t parent, device_t self, void *aux) |
382 | { |
383 | struct pci_attach_args *pa = aux; |
384 | struct pciide_softc *sc = device_private(self); |
385 | |
386 | sc->sc_wdcdev.sc_atac.atac_dev = self; |
387 | |
388 | pciide_common_attach(sc, pa, |
389 | pciide_lookup_product(pa->pa_id, pciide_intel_products)); |
390 | |
391 | if (!pmf_device_register(self, piixide_suspend, piixide_resume)) |
392 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
393 | } |
394 | |
395 | static bool |
396 | piixide_resume(device_t dv, const pmf_qual_t *qual) |
397 | { |
398 | struct pciide_softc *sc = device_private(dv); |
399 | |
400 | pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, |
401 | sc->sc_pm_reg[0]); |
402 | pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, |
403 | sc->sc_pm_reg[1]); |
404 | |
405 | return true; |
406 | } |
407 | |
408 | static bool |
409 | piixide_suspend(device_t dv, const pmf_qual_t *qual) |
410 | { |
411 | struct pciide_softc *sc = device_private(dv); |
412 | |
413 | sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, |
414 | PIIX_IDETIM); |
415 | sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, |
416 | PIIX_UDMAREG); |
417 | |
418 | return true; |
419 | } |
420 | |
421 | static void |
422 | piix_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) |
423 | { |
424 | struct pciide_channel *cp; |
425 | int channel; |
426 | u_int32_t idetim; |
427 | pcireg_t interface = PCI_INTERFACE(pa->pa_class); |
428 | |
429 | if (pciide_chipen(sc, pa) == 0) |
430 | return; |
431 | |
432 | aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
433 | "bus-master DMA support present" ); |
434 | pciide_mapreg_dma(sc, pa); |
435 | aprint_verbose("\n" ); |
436 | sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; |
437 | if (sc->sc_dma_ok) { |
438 | sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; |
439 | sc->sc_wdcdev.irqack = pciide_irqack; |
440 | /* Do all revisions require DMA alignment workaround? */ |
441 | sc->sc_wdcdev.dma_init = piix_dma_init; |
442 | switch(sc->sc_pp->ide_product) { |
443 | case PCI_PRODUCT_INTEL_82371AB_IDE: |
444 | case PCI_PRODUCT_INTEL_82440MX_IDE: |
445 | case PCI_PRODUCT_INTEL_82801AA_IDE: |
446 | case PCI_PRODUCT_INTEL_82801AB_IDE: |
447 | case PCI_PRODUCT_INTEL_82801BA_IDE: |
448 | case PCI_PRODUCT_INTEL_82801BAM_IDE: |
449 | case PCI_PRODUCT_INTEL_82801CA_IDE_1: |
450 | case PCI_PRODUCT_INTEL_82801CA_IDE_2: |
451 | case PCI_PRODUCT_INTEL_82801DB_IDE: |
452 | case PCI_PRODUCT_INTEL_82801DBM_IDE: |
453 | case PCI_PRODUCT_INTEL_82801EB_IDE: |
454 | case PCI_PRODUCT_INTEL_6300ESB_IDE: |
455 | case PCI_PRODUCT_INTEL_82801FB_IDE: |
456 | case PCI_PRODUCT_INTEL_82801G_IDE: |
457 | case PCI_PRODUCT_INTEL_82801HBM_IDE: |
458 | sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; |
459 | } |
460 | } |
461 | sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; |
462 | sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; |
463 | switch(sc->sc_pp->ide_product) { |
464 | case PCI_PRODUCT_INTEL_82801AA_IDE: |
465 | sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; |
466 | break; |
467 | case PCI_PRODUCT_INTEL_82801BA_IDE: |
468 | case PCI_PRODUCT_INTEL_82801BAM_IDE: |
469 | case PCI_PRODUCT_INTEL_82801CA_IDE_1: |
470 | case PCI_PRODUCT_INTEL_82801CA_IDE_2: |
471 | case PCI_PRODUCT_INTEL_82801DB_IDE: |
472 | case PCI_PRODUCT_INTEL_82801DBM_IDE: |
473 | case PCI_PRODUCT_INTEL_82801EB_IDE: |
474 | case PCI_PRODUCT_INTEL_6300ESB_IDE: |
475 | case PCI_PRODUCT_INTEL_82801FB_IDE: |
476 | case PCI_PRODUCT_INTEL_82801G_IDE: |
477 | case PCI_PRODUCT_INTEL_82801HBM_IDE: |
478 | sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; |
479 | break; |
480 | default: |
481 | sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; |
482 | } |
483 | if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) |
484 | sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; |
485 | else |
486 | sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; |
487 | sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; |
488 | sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; |
489 | sc->sc_wdcdev.wdc_maxdrives = 2; |
490 | |
491 | ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x" , |
492 | pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), |
493 | DEBUG_PROBE); |
494 | if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { |
495 | ATADEBUG_PRINT((", sidetim=0x%x" , |
496 | pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), |
497 | DEBUG_PROBE); |
498 | if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { |
499 | ATADEBUG_PRINT((", udamreg 0x%x" , |
500 | pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), |
501 | DEBUG_PROBE); |
502 | } |
503 | if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || |
504 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || |
505 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || |
506 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || |
507 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || |
508 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || |
509 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || |
510 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || |
511 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || |
512 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || |
513 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || |
514 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || |
515 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { |
516 | ATADEBUG_PRINT((", IDE_CONTROL 0x%x" , |
517 | pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), |
518 | DEBUG_PROBE); |
519 | } |
520 | |
521 | } |
522 | ATADEBUG_PRINT(("\n" ), DEBUG_PROBE); |
523 | |
524 | wdc_allocate_regs(&sc->sc_wdcdev); |
525 | |
526 | for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; |
527 | channel++) { |
528 | cp = &sc->pciide_channels[channel]; |
529 | if (pciide_chansetup(sc, channel, interface) == 0) |
530 | continue; |
531 | idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); |
532 | if ((PIIX_IDETIM_READ(idetim, channel) & |
533 | PIIX_IDETIM_IDE) == 0) { |
534 | #if 1 |
535 | aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
536 | "%s channel ignored (disabled)\n" , cp->name); |
537 | cp->ata_channel.ch_flags |= ATACH_DISABLED; |
538 | continue; |
539 | #else |
540 | pcireg_t interface; |
541 | |
542 | idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, |
543 | channel); |
544 | pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, |
545 | idetim); |
546 | interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, |
547 | sc->sc_tag, PCI_CLASS_REG)); |
548 | aprint_normal("channel %d idetim=%08x interface=%02x\n" , |
549 | channel, idetim, interface); |
550 | #endif |
551 | } |
552 | pciide_mapchan(pa, cp, interface, pciide_pci_intr); |
553 | } |
554 | |
555 | ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x" , |
556 | pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), |
557 | DEBUG_PROBE); |
558 | if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { |
559 | ATADEBUG_PRINT((", sidetim=0x%x" , |
560 | pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), |
561 | DEBUG_PROBE); |
562 | if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { |
563 | ATADEBUG_PRINT((", udamreg 0x%x" , |
564 | pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), |
565 | DEBUG_PROBE); |
566 | } |
567 | if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || |
568 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || |
569 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || |
570 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || |
571 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || |
572 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || |
573 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || |
574 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || |
575 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || |
576 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || |
577 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || |
578 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || |
579 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { |
580 | ATADEBUG_PRINT((", IDE_CONTROL 0x%x" , |
581 | pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), |
582 | DEBUG_PROBE); |
583 | } |
584 | } |
585 | ATADEBUG_PRINT(("\n" ), DEBUG_PROBE); |
586 | } |
587 | |
588 | static void |
589 | piix_setup_channel(struct ata_channel *chp) |
590 | { |
591 | u_int8_t mode[2], drive; |
592 | u_int32_t oidetim, idetim, idedma_ctl; |
593 | struct pciide_channel *cp = CHAN_TO_PCHAN(chp); |
594 | struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); |
595 | struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; |
596 | |
597 | oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); |
598 | idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); |
599 | idedma_ctl = 0; |
600 | |
601 | /* set up new idetim: Enable IDE registers decode */ |
602 | idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, |
603 | chp->ch_channel); |
604 | |
605 | /* setup DMA */ |
606 | pciide_channel_dma_setup(cp); |
607 | |
608 | /* |
609 | * Here we have to mess up with drives mode: PIIX can't have |
610 | * different timings for master and slave drives. |
611 | * We need to find the best combination. |
612 | */ |
613 | |
614 | /* If both drives supports DMA, take the lower mode */ |
615 | if ((drvp[0].drive_flags & ATA_DRIVE_DMA) && |
616 | (drvp[1].drive_flags & ATA_DRIVE_DMA)) { |
617 | mode[0] = mode[1] = |
618 | min(drvp[0].DMA_mode, drvp[1].DMA_mode); |
619 | drvp[0].DMA_mode = mode[0]; |
620 | drvp[1].DMA_mode = mode[1]; |
621 | goto ok; |
622 | } |
623 | /* |
624 | * If only one drive supports DMA, use its mode, and |
625 | * put the other one in PIO mode 0 if mode not compatible |
626 | */ |
627 | if (drvp[0].drive_flags & ATA_DRIVE_DMA) { |
628 | mode[0] = drvp[0].DMA_mode; |
629 | mode[1] = drvp[1].PIO_mode; |
630 | if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || |
631 | piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) |
632 | mode[1] = drvp[1].PIO_mode = 0; |
633 | goto ok; |
634 | } |
635 | if (drvp[1].drive_flags & ATA_DRIVE_DMA) { |
636 | mode[1] = drvp[1].DMA_mode; |
637 | mode[0] = drvp[0].PIO_mode; |
638 | if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || |
639 | piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) |
640 | mode[0] = drvp[0].PIO_mode = 0; |
641 | goto ok; |
642 | } |
643 | /* |
644 | * If both drives are not DMA, takes the lower mode, unless |
645 | * one of them is PIO mode < 2 |
646 | */ |
647 | if (drvp[0].PIO_mode < 2) { |
648 | mode[0] = drvp[0].PIO_mode = 0; |
649 | mode[1] = drvp[1].PIO_mode; |
650 | } else if (drvp[1].PIO_mode < 2) { |
651 | mode[1] = drvp[1].PIO_mode = 0; |
652 | mode[0] = drvp[0].PIO_mode; |
653 | } else { |
654 | mode[0] = mode[1] = |
655 | min(drvp[1].PIO_mode, drvp[0].PIO_mode); |
656 | drvp[0].PIO_mode = mode[0]; |
657 | drvp[1].PIO_mode = mode[1]; |
658 | } |
659 | ok: /* The modes are setup */ |
660 | for (drive = 0; drive < 2; drive++) { |
661 | if (drvp[drive].drive_flags & ATA_DRIVE_DMA) { |
662 | idetim |= piix_setup_idetim_timings( |
663 | mode[drive], 1, chp->ch_channel); |
664 | goto end; |
665 | } |
666 | } |
667 | /* If we are there, none of the drives are DMA */ |
668 | if (mode[0] >= 2) |
669 | idetim |= piix_setup_idetim_timings( |
670 | mode[0], 0, chp->ch_channel); |
671 | else |
672 | idetim |= piix_setup_idetim_timings( |
673 | mode[1], 0, chp->ch_channel); |
674 | end: /* |
675 | * timing mode is now set up in the controller. Enable |
676 | * it per-drive |
677 | */ |
678 | for (drive = 0; drive < 2; drive++) { |
679 | /* If no drive, skip */ |
680 | if (drvp[drive].drive_type == ATA_DRIVET_NONE) |
681 | continue; |
682 | idetim |= piix_setup_idetim_drvs(&drvp[drive]); |
683 | if (drvp[drive].drive_flags & ATA_DRIVE_DMA) |
684 | idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); |
685 | } |
686 | if (idedma_ctl != 0) { |
687 | /* Add software bits in status register */ |
688 | bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, |
689 | idedma_ctl); |
690 | } |
691 | pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); |
692 | } |
693 | |
694 | static void |
695 | piix3_4_setup_channel(struct ata_channel *chp) |
696 | { |
697 | struct ata_drive_datas *drvp; |
698 | u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; |
699 | struct pciide_channel *cp = CHAN_TO_PCHAN(chp); |
700 | struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); |
701 | struct wdc_softc *wdc = &sc->sc_wdcdev; |
702 | int drive, s; |
703 | int channel = chp->ch_channel; |
704 | |
705 | oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); |
706 | sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); |
707 | udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); |
708 | ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); |
709 | idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); |
710 | sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | |
711 | PIIX_SIDETIM_RTC_MASK(channel)); |
712 | idedma_ctl = 0; |
713 | |
714 | /* set up new idetim: Enable IDE registers decode */ |
715 | idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); |
716 | |
717 | /* setup DMA if needed */ |
718 | pciide_channel_dma_setup(cp); |
719 | |
720 | for (drive = 0; drive < 2; drive++) { |
721 | udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | |
722 | PIIX_UDMATIM_SET(0x3, channel, drive)); |
723 | drvp = &chp->ch_drive[drive]; |
724 | /* If no drive, skip */ |
725 | if (drvp->drive_type == ATA_DRIVET_NONE) |
726 | continue; |
727 | if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && |
728 | (drvp->drive_flags & ATA_DRIVE_UDMA) == 0)) |
729 | goto pio; |
730 | |
731 | if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || |
732 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || |
733 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || |
734 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || |
735 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || |
736 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || |
737 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || |
738 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || |
739 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || |
740 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || |
741 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || |
742 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || |
743 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { |
744 | ideconf |= PIIX_CONFIG_PINGPONG; |
745 | } |
746 | if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || |
747 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || |
748 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || |
749 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || |
750 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || |
751 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || |
752 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || |
753 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || |
754 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || |
755 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || |
756 | sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { |
757 | /* setup Ultra/100 */ |
758 | if (drvp->UDMA_mode > 2 && |
759 | (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) |
760 | drvp->UDMA_mode = 2; |
761 | if (drvp->UDMA_mode > 4) { |
762 | ideconf |= PIIX_CONFIG_UDMA100(channel, drive); |
763 | } else { |
764 | ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); |
765 | if (drvp->UDMA_mode > 2) { |
766 | ideconf |= PIIX_CONFIG_UDMA66(channel, |
767 | drive); |
768 | } else { |
769 | ideconf &= ~PIIX_CONFIG_UDMA66(channel, |
770 | drive); |
771 | } |
772 | } |
773 | } |
774 | if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { |
775 | /* setup Ultra/66 */ |
776 | if (drvp->UDMA_mode > 2 && |
777 | (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) |
778 | drvp->UDMA_mode = 2; |
779 | if (drvp->UDMA_mode > 2) |
780 | ideconf |= PIIX_CONFIG_UDMA66(channel, drive); |
781 | else |
782 | ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); |
783 | } |
784 | if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && |
785 | (drvp->drive_flags & ATA_DRIVE_UDMA)) { |
786 | /* use Ultra/DMA */ |
787 | s = splbio(); |
788 | drvp->drive_flags &= ~ATA_DRIVE_DMA; |
789 | splx(s); |
790 | udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); |
791 | udmareg |= PIIX_UDMATIM_SET( |
792 | piix4_sct_udma[drvp->UDMA_mode], channel, drive); |
793 | } else { |
794 | /* use Multiword DMA */ |
795 | s = splbio(); |
796 | drvp->drive_flags &= ~ATA_DRIVE_UDMA; |
797 | splx(s); |
798 | if (drive == 0) { |
799 | idetim |= piix_setup_idetim_timings( |
800 | drvp->DMA_mode, 1, channel); |
801 | } else { |
802 | sidetim |= piix_setup_sidetim_timings( |
803 | drvp->DMA_mode, 1, channel); |
804 | idetim =PIIX_IDETIM_SET(idetim, |
805 | PIIX_IDETIM_SITRE, channel); |
806 | } |
807 | } |
808 | idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); |
809 | |
810 | pio: /* use PIO mode */ |
811 | idetim |= piix_setup_idetim_drvs(drvp); |
812 | if (drive == 0) { |
813 | idetim |= piix_setup_idetim_timings( |
814 | drvp->PIO_mode, 0, channel); |
815 | } else { |
816 | sidetim |= piix_setup_sidetim_timings( |
817 | drvp->PIO_mode, 0, channel); |
818 | idetim =PIIX_IDETIM_SET(idetim, |
819 | PIIX_IDETIM_SITRE, channel); |
820 | } |
821 | } |
822 | if (idedma_ctl != 0) { |
823 | /* Add software bits in status register */ |
824 | bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, |
825 | idedma_ctl); |
826 | } |
827 | pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); |
828 | pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); |
829 | pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); |
830 | pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); |
831 | } |
832 | |
833 | |
834 | /* setup ISP and RTC fields, based on mode */ |
835 | static u_int32_t |
836 | piix_setup_idetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel) |
837 | { |
838 | |
839 | if (dma) |
840 | return PIIX_IDETIM_SET(0, |
841 | PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | |
842 | PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), |
843 | channel); |
844 | else |
845 | return PIIX_IDETIM_SET(0, |
846 | PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | |
847 | PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), |
848 | channel); |
849 | } |
850 | |
851 | /* setup DTE, PPE, IE and TIME field based on PIO mode */ |
852 | static u_int32_t |
853 | piix_setup_idetim_drvs(struct ata_drive_datas *drvp) |
854 | { |
855 | u_int32_t ret = 0; |
856 | struct ata_channel *chp = drvp->chnl_softc; |
857 | u_int8_t channel = chp->ch_channel; |
858 | u_int8_t drive = drvp->drive; |
859 | |
860 | /* |
861 | * If drive is using UDMA, timings setups are independent |
862 | * So just check DMA and PIO here. |
863 | */ |
864 | if (drvp->drive_flags & ATA_DRIVE_DMA) { |
865 | /* if mode = DMA mode 0, use compatible timings */ |
866 | if ((drvp->drive_flags & ATA_DRIVE_DMA) && |
867 | drvp->DMA_mode == 0) { |
868 | drvp->PIO_mode = 0; |
869 | return ret; |
870 | } |
871 | ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); |
872 | /* |
873 | * PIO and DMA timings are the same, use fast timings for PIO |
874 | * too, else use compat timings. |
875 | */ |
876 | if ((piix_isp_pio[drvp->PIO_mode] != |
877 | piix_isp_dma[drvp->DMA_mode]) || |
878 | (piix_rtc_pio[drvp->PIO_mode] != |
879 | piix_rtc_dma[drvp->DMA_mode])) |
880 | drvp->PIO_mode = 0; |
881 | /* if PIO mode <= 2, use compat timings for PIO */ |
882 | if (drvp->PIO_mode <= 2) { |
883 | ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), |
884 | channel); |
885 | return ret; |
886 | } |
887 | } |
888 | |
889 | /* |
890 | * Now setup PIO modes. If mode < 2, use compat timings. |
891 | * Else enable fast timings. Enable IORDY and prefetch/post |
892 | * if PIO mode >= 3. |
893 | */ |
894 | |
895 | if (drvp->PIO_mode < 2) |
896 | return ret; |
897 | |
898 | ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); |
899 | if (drvp->PIO_mode >= 3) { |
900 | ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); |
901 | ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); |
902 | } |
903 | return ret; |
904 | } |
905 | |
906 | /* setup values in SIDETIM registers, based on mode */ |
907 | static u_int32_t |
908 | piix_setup_sidetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel) |
909 | { |
910 | if (dma) |
911 | return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | |
912 | PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); |
913 | else |
914 | return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | |
915 | PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); |
916 | } |
917 | |
918 | static void |
919 | piixsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) |
920 | { |
921 | struct pciide_channel *cp; |
922 | pcireg_t interface, cmdsts; |
923 | int channel; |
924 | |
925 | if (pciide_chipen(sc, pa) == 0) |
926 | return; |
927 | |
928 | aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
929 | "bus-master DMA support present" ); |
930 | pciide_mapreg_dma(sc, pa); |
931 | aprint_verbose("\n" ); |
932 | |
933 | sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; |
934 | sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; |
935 | if (sc->sc_dma_ok) { |
936 | sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; |
937 | sc->sc_wdcdev.irqack = pciide_irqack; |
938 | /* Do all revisions require DMA alignment workaround? */ |
939 | sc->sc_wdcdev.dma_init = piix_dma_init; |
940 | sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; |
941 | sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; |
942 | } |
943 | sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; |
944 | |
945 | sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; |
946 | sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; |
947 | sc->sc_wdcdev.wdc_maxdrives = 2; |
948 | |
949 | cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); |
950 | cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; |
951 | pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); |
952 | |
953 | if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && |
954 | PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) |
955 | sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; |
956 | |
957 | interface = PCI_INTERFACE(pa->pa_class); |
958 | |
959 | wdc_allocate_regs(&sc->sc_wdcdev); |
960 | |
961 | for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; |
962 | channel++) { |
963 | cp = &sc->pciide_channels[channel]; |
964 | if (pciide_chansetup(sc, channel, interface) == 0) |
965 | continue; |
966 | pciide_mapchan(pa, cp, interface, pciide_pci_intr); |
967 | } |
968 | } |
969 | |
970 | static int |
971 | piix_dma_init(void *v, int channel, int drive, void *databuf, |
972 | size_t datalen, int flags) |
973 | { |
974 | |
975 | /* use PIO for unaligned transfer */ |
976 | if (((uintptr_t)databuf) & 0x1) |
977 | return EINVAL; |
978 | |
979 | return pciide_dma_init(v, channel, drive, databuf, datalen, flags); |
980 | } |
981 | |