1 | /* $NetBSD: nouveau_nv50_display.c,v 1.5 2016/02/05 23:46:40 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2011 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_nv50_display.c,v 1.5 2016/02/05 23:46:40 riastradh Exp $" ); |
29 | |
30 | #include <linux/dma-mapping.h> |
31 | #include <linux/err.h> |
32 | |
33 | #include <drm/drmP.h> |
34 | #include <drm/drm_crtc_helper.h> |
35 | |
36 | #include "nouveau_drm.h" |
37 | #include "nouveau_dma.h" |
38 | #include "nouveau_gem.h" |
39 | #include "nouveau_connector.h" |
40 | #include "nouveau_encoder.h" |
41 | #include "nouveau_crtc.h" |
42 | #include "nouveau_fence.h" |
43 | #include "nv50_display.h" |
44 | |
45 | #include <core/client.h> |
46 | #include <core/gpuobj.h> |
47 | #include <core/class.h> |
48 | |
49 | #include <subdev/timer.h> |
50 | #include <subdev/bar.h> |
51 | #include <subdev/fb.h> |
52 | #include <subdev/i2c.h> |
53 | |
54 | #ifdef __NetBSD__ |
55 | /* |
56 | * XXX Can't use bus_space here because this is all mapped through the |
57 | * nvbo_kmap abstraction. Can't assume we're x86 because this is |
58 | * Nouveau, not Intel. |
59 | */ |
60 | |
61 | # define __iomem volatile |
62 | # define writew fake_writew |
63 | |
64 | static inline void |
65 | fake_writew(uint16_t v, void __iomem *ptr) |
66 | { |
67 | |
68 | membar_producer(); |
69 | *(uint16_t __iomem *)ptr = v; |
70 | } |
71 | #endif |
72 | |
73 | #define EVO_DMA_NR 9 |
74 | |
75 | #define EVO_MASTER (0x00) |
76 | #define EVO_FLIP(c) (0x01 + (c)) |
77 | #define EVO_OVLY(c) (0x05 + (c)) |
78 | #define EVO_OIMM(c) (0x09 + (c)) |
79 | #define EVO_CURS(c) (0x0d + (c)) |
80 | |
81 | /* offsets in shared sync bo of various structures */ |
82 | #define EVO_SYNC(c, o) ((c) * 0x0100 + (o)) |
83 | #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00) |
84 | #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00) |
85 | #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10) |
86 | |
87 | #define EVO_CORE_HANDLE (0xd1500000) |
88 | #define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i)) |
89 | #define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff)) |
90 | #define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) | \ |
91 | (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8)) |
92 | |
93 | /****************************************************************************** |
94 | * EVO channel |
95 | *****************************************************************************/ |
96 | |
97 | struct nv50_chan { |
98 | struct nouveau_object *user; |
99 | u32 handle; |
100 | }; |
101 | |
102 | static int |
103 | nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head, |
104 | void *data, u32 size, struct nv50_chan *chan) |
105 | { |
106 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); |
107 | const u32 oclass = EVO_CHAN_OCLASS(bclass, core); |
108 | const u32 handle = EVO_CHAN_HANDLE(bclass, head); |
109 | int ret; |
110 | |
111 | ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle, |
112 | oclass, data, size, &chan->user); |
113 | if (ret) |
114 | return ret; |
115 | |
116 | chan->handle = handle; |
117 | return 0; |
118 | } |
119 | |
120 | static void |
121 | nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan) |
122 | { |
123 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); |
124 | if (chan->handle) |
125 | nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle); |
126 | } |
127 | |
128 | /****************************************************************************** |
129 | * PIO EVO channel |
130 | *****************************************************************************/ |
131 | |
132 | struct nv50_pioc { |
133 | struct nv50_chan base; |
134 | }; |
135 | |
136 | static void |
137 | nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc) |
138 | { |
139 | nv50_chan_destroy(core, &pioc->base); |
140 | } |
141 | |
142 | static int |
143 | nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head, |
144 | void *data, u32 size, struct nv50_pioc *pioc) |
145 | { |
146 | return nv50_chan_create(core, bclass, head, data, size, &pioc->base); |
147 | } |
148 | |
149 | /****************************************************************************** |
150 | * DMA EVO channel |
151 | *****************************************************************************/ |
152 | |
153 | struct nv50_dmac { |
154 | struct nv50_chan base; |
155 | #ifdef __NetBSD__ |
156 | bus_dma_segment_t dmaseg; |
157 | bus_dmamap_t dmamap; |
158 | void *dmakva; |
159 | #endif |
160 | dma_addr_t handle; |
161 | u32 *ptr; |
162 | |
163 | /* Protects against concurrent pushbuf access to this channel, lock is |
164 | * grabbed by evo_wait (if the pushbuf reservation is successful) and |
165 | * dropped again by evo_kick. */ |
166 | struct mutex lock; |
167 | }; |
168 | |
169 | static void |
170 | nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac) |
171 | { |
172 | if (dmac->ptr) { |
173 | struct pci_dev *pdev = nv_device(core)->pdev; |
174 | #ifdef __NetBSD__ |
175 | const bus_dma_tag_t dmat = pci_dma64_available(&pdev->pd_pa) ? |
176 | pdev->pd_pa.pa_dmat64 : pdev->pd_pa.pa_dmat; |
177 | |
178 | bus_dmamap_unload(dmat, dmac->dmamap); |
179 | bus_dmamem_unmap(dmat, dmac->dmakva, PAGE_SIZE); |
180 | bus_dmamap_destroy(dmat, dmac->dmamap); |
181 | bus_dmamem_free(dmat, &dmac->dmaseg, 1); |
182 | dmac->handle = 0; |
183 | dmac->ptr = NULL; |
184 | #else |
185 | pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle); |
186 | #endif |
187 | } |
188 | |
189 | #ifdef __NetBSD__ |
190 | linux_mutex_destroy(&dmac->lock); |
191 | #endif |
192 | |
193 | nv50_chan_destroy(core, &dmac->base); |
194 | } |
195 | |
196 | static int |
197 | nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent) |
198 | { |
199 | struct nouveau_fb *pfb = nouveau_fb(core); |
200 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); |
201 | struct nouveau_object *object; |
202 | int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP, |
203 | NV_DMA_IN_MEMORY_CLASS, |
204 | &(struct nv_dma_class) { |
205 | .flags = NV_DMA_TARGET_VRAM | |
206 | NV_DMA_ACCESS_RDWR, |
207 | .start = 0, |
208 | .limit = pfb->ram->size - 1, |
209 | .conf0 = NV50_DMA_CONF0_ENABLE | |
210 | NV50_DMA_CONF0_PART_256, |
211 | }, sizeof(struct nv_dma_class), &object); |
212 | if (ret) |
213 | return ret; |
214 | |
215 | ret = nouveau_object_new(client, parent, NvEvoFB16, |
216 | NV_DMA_IN_MEMORY_CLASS, |
217 | &(struct nv_dma_class) { |
218 | .flags = NV_DMA_TARGET_VRAM | |
219 | NV_DMA_ACCESS_RDWR, |
220 | .start = 0, |
221 | .limit = pfb->ram->size - 1, |
222 | .conf0 = NV50_DMA_CONF0_ENABLE | 0x70 | |
223 | NV50_DMA_CONF0_PART_256, |
224 | }, sizeof(struct nv_dma_class), &object); |
225 | if (ret) |
226 | return ret; |
227 | |
228 | ret = nouveau_object_new(client, parent, NvEvoFB32, |
229 | NV_DMA_IN_MEMORY_CLASS, |
230 | &(struct nv_dma_class) { |
231 | .flags = NV_DMA_TARGET_VRAM | |
232 | NV_DMA_ACCESS_RDWR, |
233 | .start = 0, |
234 | .limit = pfb->ram->size - 1, |
235 | .conf0 = NV50_DMA_CONF0_ENABLE | 0x7a | |
236 | NV50_DMA_CONF0_PART_256, |
237 | }, sizeof(struct nv_dma_class), &object); |
238 | return ret; |
239 | } |
240 | |
241 | static int |
242 | nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent) |
243 | { |
244 | struct nouveau_fb *pfb = nouveau_fb(core); |
245 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); |
246 | struct nouveau_object *object; |
247 | int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP, |
248 | NV_DMA_IN_MEMORY_CLASS, |
249 | &(struct nv_dma_class) { |
250 | .flags = NV_DMA_TARGET_VRAM | |
251 | NV_DMA_ACCESS_RDWR, |
252 | .start = 0, |
253 | .limit = pfb->ram->size - 1, |
254 | .conf0 = NVC0_DMA_CONF0_ENABLE, |
255 | }, sizeof(struct nv_dma_class), &object); |
256 | if (ret) |
257 | return ret; |
258 | |
259 | ret = nouveau_object_new(client, parent, NvEvoFB16, |
260 | NV_DMA_IN_MEMORY_CLASS, |
261 | &(struct nv_dma_class) { |
262 | .flags = NV_DMA_TARGET_VRAM | |
263 | NV_DMA_ACCESS_RDWR, |
264 | .start = 0, |
265 | .limit = pfb->ram->size - 1, |
266 | .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe, |
267 | }, sizeof(struct nv_dma_class), &object); |
268 | if (ret) |
269 | return ret; |
270 | |
271 | ret = nouveau_object_new(client, parent, NvEvoFB32, |
272 | NV_DMA_IN_MEMORY_CLASS, |
273 | &(struct nv_dma_class) { |
274 | .flags = NV_DMA_TARGET_VRAM | |
275 | NV_DMA_ACCESS_RDWR, |
276 | .start = 0, |
277 | .limit = pfb->ram->size - 1, |
278 | .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe, |
279 | }, sizeof(struct nv_dma_class), &object); |
280 | return ret; |
281 | } |
282 | |
283 | static int |
284 | nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent) |
285 | { |
286 | struct nouveau_fb *pfb = nouveau_fb(core); |
287 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); |
288 | struct nouveau_object *object; |
289 | int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP, |
290 | NV_DMA_IN_MEMORY_CLASS, |
291 | &(struct nv_dma_class) { |
292 | .flags = NV_DMA_TARGET_VRAM | |
293 | NV_DMA_ACCESS_RDWR, |
294 | .start = 0, |
295 | .limit = pfb->ram->size - 1, |
296 | .conf0 = NVD0_DMA_CONF0_ENABLE | |
297 | NVD0_DMA_CONF0_PAGE_LP, |
298 | }, sizeof(struct nv_dma_class), &object); |
299 | if (ret) |
300 | return ret; |
301 | |
302 | ret = nouveau_object_new(client, parent, NvEvoFB32, |
303 | NV_DMA_IN_MEMORY_CLASS, |
304 | &(struct nv_dma_class) { |
305 | .flags = NV_DMA_TARGET_VRAM | |
306 | NV_DMA_ACCESS_RDWR, |
307 | .start = 0, |
308 | .limit = pfb->ram->size - 1, |
309 | .conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe | |
310 | NVD0_DMA_CONF0_PAGE_LP, |
311 | }, sizeof(struct nv_dma_class), &object); |
312 | return ret; |
313 | } |
314 | |
315 | static int |
316 | nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head, |
317 | void *data, u32 size, u64 syncbuf, |
318 | struct nv50_dmac *dmac) |
319 | { |
320 | struct nouveau_fb *pfb = nouveau_fb(core); |
321 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); |
322 | struct nouveau_object *object; |
323 | u32 pushbuf = *(u32 *)data; |
324 | int ret; |
325 | |
326 | #ifdef __NetBSD__ |
327 | linux_mutex_init(&dmac->lock); |
328 | #else |
329 | mutex_init(&dmac->lock); |
330 | #endif |
331 | |
332 | #ifdef __NetBSD__ |
333 | { |
334 | struct nouveau_device *device = nv_device(core); |
335 | const bus_dma_tag_t dmat = pci_dma64_available(&device->pdev->pd_pa) ? |
336 | device->pdev->pd_pa.pa_dmat64 : device->pdev->pd_pa.pa_dmat; |
337 | |
338 | int rsegs; |
339 | |
340 | /* XXX errno NetBSD->Linux */ |
341 | ret = -bus_dmamem_alloc(dmat, PAGE_SIZE, PAGE_SIZE, 0, &dmac->dmaseg, |
342 | 1, &rsegs, BUS_DMA_WAITOK); |
343 | if (ret) |
344 | return ret; |
345 | KASSERT(rsegs == 1); |
346 | /* XXX errno NetBSD->Linux */ |
347 | ret = -bus_dmamap_create(dmat, PAGE_SIZE, 1, PAGE_SIZE, 0, |
348 | BUS_DMA_WAITOK, &dmac->dmamap); |
349 | if (ret) { |
350 | bus_dmamem_free(dmat, &dmac->dmaseg, 1); |
351 | return ret; |
352 | } |
353 | /* XXX errno NetBSD->Linux */ |
354 | ret = -bus_dmamem_map(dmat, &dmac->dmaseg, 1, PAGE_SIZE, &dmac->dmakva, |
355 | BUS_DMA_WAITOK); |
356 | if (ret) { |
357 | bus_dmamap_destroy(dmat, dmac->dmamap); |
358 | bus_dmamem_free(dmat, &dmac->dmaseg, 1); |
359 | return ret; |
360 | } |
361 | ret = -bus_dmamap_load(dmat, dmac->dmamap, dmac->dmakva, PAGE_SIZE, |
362 | NULL, BUS_DMA_WAITOK); |
363 | if (ret) { |
364 | bus_dmamem_unmap(dmat, dmac->dmakva, PAGE_SIZE); |
365 | bus_dmamap_destroy(dmat, dmac->dmamap); |
366 | bus_dmamem_free(dmat, &dmac->dmaseg, 1); |
367 | return ret; |
368 | } |
369 | |
370 | dmac->handle = dmac->dmamap->dm_segs[0].ds_addr; |
371 | dmac->ptr = dmac->dmakva; |
372 | } |
373 | #else |
374 | dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE, |
375 | &dmac->handle); |
376 | if (!dmac->ptr) |
377 | return -ENOMEM; |
378 | #endif |
379 | |
380 | ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf, |
381 | NV_DMA_FROM_MEMORY_CLASS, |
382 | &(struct nv_dma_class) { |
383 | .flags = NV_DMA_TARGET_PCI_US | |
384 | NV_DMA_ACCESS_RD, |
385 | .start = dmac->handle + 0x0000, |
386 | .limit = dmac->handle + 0x0fff, |
387 | }, sizeof(struct nv_dma_class), &object); |
388 | if (ret) |
389 | return ret; |
390 | |
391 | ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base); |
392 | if (ret) |
393 | return ret; |
394 | |
395 | ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync, |
396 | NV_DMA_IN_MEMORY_CLASS, |
397 | &(struct nv_dma_class) { |
398 | .flags = NV_DMA_TARGET_VRAM | |
399 | NV_DMA_ACCESS_RDWR, |
400 | .start = syncbuf + 0x0000, |
401 | .limit = syncbuf + 0x0fff, |
402 | }, sizeof(struct nv_dma_class), &object); |
403 | if (ret) |
404 | return ret; |
405 | |
406 | ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM, |
407 | NV_DMA_IN_MEMORY_CLASS, |
408 | &(struct nv_dma_class) { |
409 | .flags = NV_DMA_TARGET_VRAM | |
410 | NV_DMA_ACCESS_RDWR, |
411 | .start = 0, |
412 | .limit = pfb->ram->size - 1, |
413 | }, sizeof(struct nv_dma_class), &object); |
414 | if (ret) |
415 | return ret; |
416 | |
417 | if (nv_device(core)->card_type < NV_C0) |
418 | ret = nv50_dmac_create_fbdma(core, dmac->base.handle); |
419 | else |
420 | if (nv_device(core)->card_type < NV_D0) |
421 | ret = nvc0_dmac_create_fbdma(core, dmac->base.handle); |
422 | else |
423 | ret = nvd0_dmac_create_fbdma(core, dmac->base.handle); |
424 | return ret; |
425 | } |
426 | |
427 | struct nv50_mast { |
428 | struct nv50_dmac base; |
429 | }; |
430 | |
431 | struct nv50_curs { |
432 | struct nv50_pioc base; |
433 | }; |
434 | |
435 | struct nv50_sync { |
436 | struct nv50_dmac base; |
437 | u32 addr; |
438 | u32 data; |
439 | }; |
440 | |
441 | struct nv50_ovly { |
442 | struct nv50_dmac base; |
443 | }; |
444 | |
445 | struct nv50_oimm { |
446 | struct nv50_pioc base; |
447 | }; |
448 | |
449 | struct nv50_head { |
450 | struct nouveau_crtc base; |
451 | struct nouveau_bo *image; |
452 | struct nv50_curs curs; |
453 | struct nv50_sync sync; |
454 | struct nv50_ovly ovly; |
455 | struct nv50_oimm oimm; |
456 | }; |
457 | |
458 | #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c)) |
459 | #define nv50_curs(c) (&nv50_head(c)->curs) |
460 | #define nv50_sync(c) (&nv50_head(c)->sync) |
461 | #define nv50_ovly(c) (&nv50_head(c)->ovly) |
462 | #define nv50_oimm(c) (&nv50_head(c)->oimm) |
463 | #define nv50_chan(c) (&(c)->base.base) |
464 | #define nv50_vers(c) nv_mclass(nv50_chan(c)->user) |
465 | |
466 | struct nv50_disp { |
467 | struct nouveau_object *core; |
468 | struct nv50_mast mast; |
469 | |
470 | u32 modeset; |
471 | |
472 | struct nouveau_bo *sync; |
473 | }; |
474 | |
475 | static struct nv50_disp * |
476 | nv50_disp(struct drm_device *dev) |
477 | { |
478 | return nouveau_display(dev)->priv; |
479 | } |
480 | |
481 | #define nv50_mast(d) (&nv50_disp(d)->mast) |
482 | |
483 | static struct drm_crtc * |
484 | nv50_display_crtc_get(struct drm_encoder *encoder) |
485 | { |
486 | return nouveau_encoder(encoder)->crtc; |
487 | } |
488 | |
489 | /****************************************************************************** |
490 | * EVO channel helpers |
491 | *****************************************************************************/ |
492 | static u32 * |
493 | evo_wait(void *evoc, int nr) |
494 | { |
495 | struct nv50_dmac *dmac = evoc; |
496 | u32 put = nv_ro32(dmac->base.user, 0x0000) / 4; |
497 | |
498 | mutex_lock(&dmac->lock); |
499 | if (put + nr >= (PAGE_SIZE / 4) - 8) { |
500 | dmac->ptr[put] = 0x20000000; |
501 | |
502 | nv_wo32(dmac->base.user, 0x0000, 0x00000000); |
503 | if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) { |
504 | mutex_unlock(&dmac->lock); |
505 | NV_ERROR(dmac->base.user, "channel stalled\n" ); |
506 | return NULL; |
507 | } |
508 | |
509 | put = 0; |
510 | } |
511 | |
512 | return dmac->ptr + put; |
513 | } |
514 | |
515 | static void |
516 | evo_kick(u32 *push, void *evoc) |
517 | { |
518 | struct nv50_dmac *dmac = evoc; |
519 | nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2); |
520 | mutex_unlock(&dmac->lock); |
521 | } |
522 | |
523 | #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m)) |
524 | #define evo_data(p,d) *((p)++) = (d) |
525 | |
526 | static bool |
527 | evo_sync_wait(void *data) |
528 | { |
529 | if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000) |
530 | return true; |
531 | usleep_range(1, 2); |
532 | return false; |
533 | } |
534 | |
535 | static int |
536 | evo_sync(struct drm_device *dev) |
537 | { |
538 | struct nouveau_device *device = nouveau_dev(dev); |
539 | struct nv50_disp *disp = nv50_disp(dev); |
540 | struct nv50_mast *mast = nv50_mast(dev); |
541 | u32 *push = evo_wait(mast, 8); |
542 | if (push) { |
543 | nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000); |
544 | evo_mthd(push, 0x0084, 1); |
545 | evo_data(push, 0x80000000 | EVO_MAST_NTFY); |
546 | evo_mthd(push, 0x0080, 2); |
547 | evo_data(push, 0x00000000); |
548 | evo_data(push, 0x00000000); |
549 | evo_kick(push, mast); |
550 | if (nv_wait_cb(device, evo_sync_wait, disp->sync)) |
551 | return 0; |
552 | } |
553 | |
554 | return -EBUSY; |
555 | } |
556 | |
557 | /****************************************************************************** |
558 | * Page flipping channel |
559 | *****************************************************************************/ |
560 | struct nouveau_bo * |
561 | nv50_display_crtc_sema(struct drm_device *dev, int crtc) |
562 | { |
563 | return nv50_disp(dev)->sync; |
564 | } |
565 | |
566 | struct nv50_display_flip { |
567 | struct nv50_disp *disp; |
568 | struct nv50_sync *chan; |
569 | }; |
570 | |
571 | static bool |
572 | nv50_display_flip_wait(void *data) |
573 | { |
574 | struct nv50_display_flip *flip = data; |
575 | if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) == |
576 | flip->chan->data) |
577 | return true; |
578 | usleep_range(1, 2); |
579 | return false; |
580 | } |
581 | |
582 | void |
583 | nv50_display_flip_stop(struct drm_crtc *crtc) |
584 | { |
585 | struct nouveau_device *device = nouveau_dev(crtc->dev); |
586 | struct nv50_display_flip flip = { |
587 | .disp = nv50_disp(crtc->dev), |
588 | .chan = nv50_sync(crtc), |
589 | }; |
590 | u32 *push; |
591 | |
592 | push = evo_wait(flip.chan, 8); |
593 | if (push) { |
594 | evo_mthd(push, 0x0084, 1); |
595 | evo_data(push, 0x00000000); |
596 | evo_mthd(push, 0x0094, 1); |
597 | evo_data(push, 0x00000000); |
598 | evo_mthd(push, 0x00c0, 1); |
599 | evo_data(push, 0x00000000); |
600 | evo_mthd(push, 0x0080, 1); |
601 | evo_data(push, 0x00000000); |
602 | evo_kick(push, flip.chan); |
603 | } |
604 | |
605 | nv_wait_cb(device, nv50_display_flip_wait, &flip); |
606 | } |
607 | |
608 | int |
609 | nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
610 | struct nouveau_channel *chan, u32 swap_interval) |
611 | { |
612 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); |
613 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
614 | struct nv50_head *head = nv50_head(crtc); |
615 | struct nv50_sync *sync = nv50_sync(crtc); |
616 | u32 *push; |
617 | int ret; |
618 | |
619 | swap_interval <<= 4; |
620 | if (swap_interval == 0) |
621 | swap_interval |= 0x100; |
622 | if (chan == NULL) |
623 | evo_sync(crtc->dev); |
624 | |
625 | push = evo_wait(sync, 128); |
626 | if (unlikely(push == NULL)) |
627 | return -EBUSY; |
628 | |
629 | if (chan && nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) { |
630 | ret = RING_SPACE(chan, 8); |
631 | if (ret) |
632 | return ret; |
633 | |
634 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2); |
635 | OUT_RING (chan, NvEvoSema0 + nv_crtc->index); |
636 | OUT_RING (chan, sync->addr ^ 0x10); |
637 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1); |
638 | OUT_RING (chan, sync->data + 1); |
639 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2); |
640 | OUT_RING (chan, sync->addr); |
641 | OUT_RING (chan, sync->data); |
642 | } else |
643 | if (chan && nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) { |
644 | u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; |
645 | ret = RING_SPACE(chan, 12); |
646 | if (ret) |
647 | return ret; |
648 | |
649 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); |
650 | OUT_RING (chan, chan->vram); |
651 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
652 | OUT_RING (chan, upper_32_bits(addr ^ 0x10)); |
653 | OUT_RING (chan, lower_32_bits(addr ^ 0x10)); |
654 | OUT_RING (chan, sync->data + 1); |
655 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); |
656 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
657 | OUT_RING (chan, upper_32_bits(addr)); |
658 | OUT_RING (chan, lower_32_bits(addr)); |
659 | OUT_RING (chan, sync->data); |
660 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL); |
661 | } else |
662 | if (chan) { |
663 | u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; |
664 | ret = RING_SPACE(chan, 10); |
665 | if (ret) |
666 | return ret; |
667 | |
668 | BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
669 | OUT_RING (chan, upper_32_bits(addr ^ 0x10)); |
670 | OUT_RING (chan, lower_32_bits(addr ^ 0x10)); |
671 | OUT_RING (chan, sync->data + 1); |
672 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG | |
673 | NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); |
674 | BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
675 | OUT_RING (chan, upper_32_bits(addr)); |
676 | OUT_RING (chan, lower_32_bits(addr)); |
677 | OUT_RING (chan, sync->data); |
678 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL | |
679 | NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); |
680 | } |
681 | |
682 | if (chan) { |
683 | sync->addr ^= 0x10; |
684 | sync->data++; |
685 | FIRE_RING (chan); |
686 | } |
687 | |
688 | /* queue the flip */ |
689 | evo_mthd(push, 0x0100, 1); |
690 | evo_data(push, 0xfffe0000); |
691 | evo_mthd(push, 0x0084, 1); |
692 | evo_data(push, swap_interval); |
693 | if (!(swap_interval & 0x00000100)) { |
694 | evo_mthd(push, 0x00e0, 1); |
695 | evo_data(push, 0x40000000); |
696 | } |
697 | evo_mthd(push, 0x0088, 4); |
698 | evo_data(push, sync->addr); |
699 | evo_data(push, sync->data++); |
700 | evo_data(push, sync->data); |
701 | evo_data(push, NvEvoSync); |
702 | evo_mthd(push, 0x00a0, 2); |
703 | evo_data(push, 0x00000000); |
704 | evo_data(push, 0x00000000); |
705 | evo_mthd(push, 0x00c0, 1); |
706 | evo_data(push, nv_fb->r_dma); |
707 | evo_mthd(push, 0x0110, 2); |
708 | evo_data(push, 0x00000000); |
709 | evo_data(push, 0x00000000); |
710 | if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) { |
711 | evo_mthd(push, 0x0800, 5); |
712 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); |
713 | evo_data(push, 0); |
714 | evo_data(push, (fb->height << 16) | fb->width); |
715 | evo_data(push, nv_fb->r_pitch); |
716 | evo_data(push, nv_fb->r_format); |
717 | } else { |
718 | evo_mthd(push, 0x0400, 5); |
719 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); |
720 | evo_data(push, 0); |
721 | evo_data(push, (fb->height << 16) | fb->width); |
722 | evo_data(push, nv_fb->r_pitch); |
723 | evo_data(push, nv_fb->r_format); |
724 | } |
725 | evo_mthd(push, 0x0080, 1); |
726 | evo_data(push, 0x00000000); |
727 | evo_kick(push, sync); |
728 | |
729 | nouveau_bo_ref(nv_fb->nvbo, &head->image); |
730 | return 0; |
731 | } |
732 | |
733 | /****************************************************************************** |
734 | * CRTC |
735 | *****************************************************************************/ |
736 | static int |
737 | nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) |
738 | { |
739 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
740 | struct nouveau_connector *nv_connector; |
741 | struct drm_connector *connector; |
742 | u32 *push, mode = 0x00; |
743 | |
744 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
745 | connector = &nv_connector->base; |
746 | if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { |
747 | if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3) |
748 | mode = DITHERING_MODE_DYNAMIC2X2; |
749 | } else { |
750 | mode = nv_connector->dithering_mode; |
751 | } |
752 | |
753 | if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) { |
754 | if (connector->display_info.bpc >= 8) |
755 | mode |= DITHERING_DEPTH_8BPC; |
756 | } else { |
757 | mode |= nv_connector->dithering_depth; |
758 | } |
759 | |
760 | push = evo_wait(mast, 4); |
761 | if (push) { |
762 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
763 | evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1); |
764 | evo_data(push, mode); |
765 | } else |
766 | if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) { |
767 | evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1); |
768 | evo_data(push, mode); |
769 | } else { |
770 | evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1); |
771 | evo_data(push, mode); |
772 | } |
773 | |
774 | if (update) { |
775 | evo_mthd(push, 0x0080, 1); |
776 | evo_data(push, 0x00000000); |
777 | } |
778 | evo_kick(push, mast); |
779 | } |
780 | |
781 | return 0; |
782 | } |
783 | |
784 | static int |
785 | nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) |
786 | { |
787 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
788 | struct drm_display_mode *omode, *umode = &nv_crtc->base.mode; |
789 | struct drm_crtc *crtc = &nv_crtc->base; |
790 | struct nouveau_connector *nv_connector; |
791 | int mode = DRM_MODE_SCALE_NONE; |
792 | u32 oX, oY, *push; |
793 | |
794 | /* start off at the resolution we programmed the crtc for, this |
795 | * effectively handles NONE/FULL scaling |
796 | */ |
797 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
798 | if (nv_connector && nv_connector->native_mode) |
799 | mode = nv_connector->scaling_mode; |
800 | |
801 | if (mode != DRM_MODE_SCALE_NONE) |
802 | omode = nv_connector->native_mode; |
803 | else |
804 | omode = umode; |
805 | |
806 | oX = omode->hdisplay; |
807 | oY = omode->vdisplay; |
808 | if (omode->flags & DRM_MODE_FLAG_DBLSCAN) |
809 | oY *= 2; |
810 | |
811 | /* add overscan compensation if necessary, will keep the aspect |
812 | * ratio the same as the backend mode unless overridden by the |
813 | * user setting both hborder and vborder properties. |
814 | */ |
815 | if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || |
816 | (nv_connector->underscan == UNDERSCAN_AUTO && |
817 | nv_connector->edid && |
818 | drm_detect_hdmi_monitor(nv_connector->edid)))) { |
819 | u32 bX = nv_connector->underscan_hborder; |
820 | u32 bY = nv_connector->underscan_vborder; |
821 | u32 aspect = (oY << 19) / oX; |
822 | |
823 | if (bX) { |
824 | oX -= (bX * 2); |
825 | if (bY) oY -= (bY * 2); |
826 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; |
827 | } else { |
828 | oX -= (oX >> 4) + 32; |
829 | if (bY) oY -= (bY * 2); |
830 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; |
831 | } |
832 | } |
833 | |
834 | /* handle CENTER/ASPECT scaling, taking into account the areas |
835 | * removed already for overscan compensation |
836 | */ |
837 | switch (mode) { |
838 | case DRM_MODE_SCALE_CENTER: |
839 | oX = min((u32)umode->hdisplay, oX); |
840 | oY = min((u32)umode->vdisplay, oY); |
841 | /* fall-through */ |
842 | case DRM_MODE_SCALE_ASPECT: |
843 | if (oY < oX) { |
844 | u32 aspect = (umode->hdisplay << 19) / umode->vdisplay; |
845 | oX = ((oY * aspect) + (aspect / 2)) >> 19; |
846 | } else { |
847 | u32 aspect = (umode->vdisplay << 19) / umode->hdisplay; |
848 | oY = ((oX * aspect) + (aspect / 2)) >> 19; |
849 | } |
850 | break; |
851 | default: |
852 | break; |
853 | } |
854 | |
855 | push = evo_wait(mast, 8); |
856 | if (push) { |
857 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
858 | /*XXX: SCALE_CTRL_ACTIVE??? */ |
859 | evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2); |
860 | evo_data(push, (oY << 16) | oX); |
861 | evo_data(push, (oY << 16) | oX); |
862 | evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1); |
863 | evo_data(push, 0x00000000); |
864 | evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1); |
865 | evo_data(push, umode->vdisplay << 16 | umode->hdisplay); |
866 | } else { |
867 | evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3); |
868 | evo_data(push, (oY << 16) | oX); |
869 | evo_data(push, (oY << 16) | oX); |
870 | evo_data(push, (oY << 16) | oX); |
871 | evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1); |
872 | evo_data(push, 0x00000000); |
873 | evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1); |
874 | evo_data(push, umode->vdisplay << 16 | umode->hdisplay); |
875 | } |
876 | |
877 | evo_kick(push, mast); |
878 | |
879 | if (update) { |
880 | nv50_display_flip_stop(crtc); |
881 | nv50_display_flip_next(crtc, crtc->primary->fb, |
882 | NULL, 1); |
883 | } |
884 | } |
885 | |
886 | return 0; |
887 | } |
888 | |
889 | static int |
890 | nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update) |
891 | { |
892 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
893 | u32 *push, hue, vib; |
894 | int adj; |
895 | |
896 | adj = (nv_crtc->color_vibrance > 0) ? 50 : 0; |
897 | vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff; |
898 | hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff; |
899 | |
900 | push = evo_wait(mast, 16); |
901 | if (push) { |
902 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
903 | evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1); |
904 | evo_data(push, (hue << 20) | (vib << 8)); |
905 | } else { |
906 | evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1); |
907 | evo_data(push, (hue << 20) | (vib << 8)); |
908 | } |
909 | |
910 | if (update) { |
911 | evo_mthd(push, 0x0080, 1); |
912 | evo_data(push, 0x00000000); |
913 | } |
914 | evo_kick(push, mast); |
915 | } |
916 | |
917 | return 0; |
918 | } |
919 | |
920 | static int |
921 | nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb, |
922 | int x, int y, bool update) |
923 | { |
924 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb); |
925 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
926 | u32 *push; |
927 | |
928 | push = evo_wait(mast, 16); |
929 | if (push) { |
930 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
931 | evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1); |
932 | evo_data(push, nvfb->nvbo->bo.offset >> 8); |
933 | evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3); |
934 | evo_data(push, (fb->height << 16) | fb->width); |
935 | evo_data(push, nvfb->r_pitch); |
936 | evo_data(push, nvfb->r_format); |
937 | evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1); |
938 | evo_data(push, (y << 16) | x); |
939 | if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) { |
940 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
941 | evo_data(push, nvfb->r_dma); |
942 | } |
943 | } else { |
944 | evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1); |
945 | evo_data(push, nvfb->nvbo->bo.offset >> 8); |
946 | evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4); |
947 | evo_data(push, (fb->height << 16) | fb->width); |
948 | evo_data(push, nvfb->r_pitch); |
949 | evo_data(push, nvfb->r_format); |
950 | evo_data(push, nvfb->r_dma); |
951 | evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1); |
952 | evo_data(push, (y << 16) | x); |
953 | } |
954 | |
955 | if (update) { |
956 | evo_mthd(push, 0x0080, 1); |
957 | evo_data(push, 0x00000000); |
958 | } |
959 | evo_kick(push, mast); |
960 | } |
961 | |
962 | nv_crtc->fb.tile_flags = nvfb->r_dma; |
963 | return 0; |
964 | } |
965 | |
966 | static void |
967 | nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc) |
968 | { |
969 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
970 | u32 *push = evo_wait(mast, 16); |
971 | if (push) { |
972 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
973 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); |
974 | evo_data(push, 0x85000000); |
975 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); |
976 | } else |
977 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
978 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); |
979 | evo_data(push, 0x85000000); |
980 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); |
981 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); |
982 | evo_data(push, NvEvoVRAM); |
983 | } else { |
984 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2); |
985 | evo_data(push, 0x85000000); |
986 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); |
987 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); |
988 | evo_data(push, NvEvoVRAM); |
989 | } |
990 | evo_kick(push, mast); |
991 | } |
992 | } |
993 | |
994 | static void |
995 | nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc) |
996 | { |
997 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
998 | u32 *push = evo_wait(mast, 16); |
999 | if (push) { |
1000 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
1001 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); |
1002 | evo_data(push, 0x05000000); |
1003 | } else |
1004 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
1005 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); |
1006 | evo_data(push, 0x05000000); |
1007 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); |
1008 | evo_data(push, 0x00000000); |
1009 | } else { |
1010 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1); |
1011 | evo_data(push, 0x05000000); |
1012 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); |
1013 | evo_data(push, 0x00000000); |
1014 | } |
1015 | evo_kick(push, mast); |
1016 | } |
1017 | } |
1018 | |
1019 | static void |
1020 | nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update) |
1021 | { |
1022 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
1023 | |
1024 | if (show) |
1025 | nv50_crtc_cursor_show(nv_crtc); |
1026 | else |
1027 | nv50_crtc_cursor_hide(nv_crtc); |
1028 | |
1029 | if (update) { |
1030 | u32 *push = evo_wait(mast, 2); |
1031 | if (push) { |
1032 | evo_mthd(push, 0x0080, 1); |
1033 | evo_data(push, 0x00000000); |
1034 | evo_kick(push, mast); |
1035 | } |
1036 | } |
1037 | } |
1038 | |
1039 | static void |
1040 | nv50_crtc_dpms(struct drm_crtc *crtc, int mode) |
1041 | { |
1042 | } |
1043 | |
1044 | static void |
1045 | nv50_crtc_prepare(struct drm_crtc *crtc) |
1046 | { |
1047 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1048 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
1049 | u32 *push; |
1050 | |
1051 | nv50_display_flip_stop(crtc); |
1052 | |
1053 | push = evo_wait(mast, 2); |
1054 | if (push) { |
1055 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
1056 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
1057 | evo_data(push, 0x00000000); |
1058 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); |
1059 | evo_data(push, 0x40000000); |
1060 | } else |
1061 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
1062 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
1063 | evo_data(push, 0x00000000); |
1064 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); |
1065 | evo_data(push, 0x40000000); |
1066 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); |
1067 | evo_data(push, 0x00000000); |
1068 | } else { |
1069 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); |
1070 | evo_data(push, 0x00000000); |
1071 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1); |
1072 | evo_data(push, 0x03000000); |
1073 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); |
1074 | evo_data(push, 0x00000000); |
1075 | } |
1076 | |
1077 | evo_kick(push, mast); |
1078 | } |
1079 | |
1080 | nv50_crtc_cursor_show_hide(nv_crtc, false, false); |
1081 | } |
1082 | |
1083 | static void |
1084 | nv50_crtc_commit(struct drm_crtc *crtc) |
1085 | { |
1086 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1087 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
1088 | u32 *push; |
1089 | |
1090 | push = evo_wait(mast, 32); |
1091 | if (push) { |
1092 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
1093 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
1094 | evo_data(push, NvEvoVRAM_LP); |
1095 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); |
1096 | evo_data(push, 0xc0000000); |
1097 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); |
1098 | } else |
1099 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
1100 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
1101 | evo_data(push, nv_crtc->fb.tile_flags); |
1102 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); |
1103 | evo_data(push, 0xc0000000); |
1104 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); |
1105 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); |
1106 | evo_data(push, NvEvoVRAM); |
1107 | } else { |
1108 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); |
1109 | evo_data(push, nv_crtc->fb.tile_flags); |
1110 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4); |
1111 | evo_data(push, 0x83000000); |
1112 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); |
1113 | evo_data(push, 0x00000000); |
1114 | evo_data(push, 0x00000000); |
1115 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); |
1116 | evo_data(push, NvEvoVRAM); |
1117 | evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1); |
1118 | evo_data(push, 0xffffff00); |
1119 | } |
1120 | |
1121 | evo_kick(push, mast); |
1122 | } |
1123 | |
1124 | nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true); |
1125 | nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1); |
1126 | } |
1127 | |
1128 | static bool |
1129 | nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, |
1130 | struct drm_display_mode *adjusted_mode) |
1131 | { |
1132 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
1133 | return true; |
1134 | } |
1135 | |
1136 | static int |
1137 | nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) |
1138 | { |
1139 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); |
1140 | struct nv50_head *head = nv50_head(crtc); |
1141 | int ret; |
1142 | |
1143 | ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM); |
1144 | if (ret == 0) { |
1145 | if (head->image) |
1146 | nouveau_bo_unpin(head->image); |
1147 | nouveau_bo_ref(nvfb->nvbo, &head->image); |
1148 | } |
1149 | |
1150 | return ret; |
1151 | } |
1152 | |
1153 | static int |
1154 | nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode, |
1155 | struct drm_display_mode *mode, int x, int y, |
1156 | struct drm_framebuffer *old_fb) |
1157 | { |
1158 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
1159 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1160 | struct nouveau_connector *nv_connector; |
1161 | u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1; |
1162 | u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1; |
1163 | u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks; |
1164 | u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks; |
1165 | u32 vblan2e = 0, vblan2s = 1; |
1166 | u32 *push; |
1167 | int ret; |
1168 | |
1169 | hactive = mode->htotal; |
1170 | hsynce = mode->hsync_end - mode->hsync_start - 1; |
1171 | hbackp = mode->htotal - mode->hsync_end; |
1172 | hblanke = hsynce + hbackp; |
1173 | hfrontp = mode->hsync_start - mode->hdisplay; |
1174 | hblanks = mode->htotal - hfrontp - 1; |
1175 | |
1176 | vactive = mode->vtotal * vscan / ilace; |
1177 | vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; |
1178 | vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; |
1179 | vblanke = vsynce + vbackp; |
1180 | vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; |
1181 | vblanks = vactive - vfrontp - 1; |
1182 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
1183 | vblan2e = vactive + vsynce + vbackp; |
1184 | vblan2s = vblan2e + (mode->vdisplay * vscan / ilace); |
1185 | vactive = (vactive * 2) + 1; |
1186 | } |
1187 | |
1188 | ret = nv50_crtc_swap_fbs(crtc, old_fb); |
1189 | if (ret) |
1190 | return ret; |
1191 | |
1192 | push = evo_wait(mast, 64); |
1193 | if (push) { |
1194 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
1195 | evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2); |
1196 | evo_data(push, 0x00800000 | mode->clock); |
1197 | evo_data(push, (ilace == 2) ? 2 : 0); |
1198 | evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6); |
1199 | evo_data(push, 0x00000000); |
1200 | evo_data(push, (vactive << 16) | hactive); |
1201 | evo_data(push, ( vsynce << 16) | hsynce); |
1202 | evo_data(push, (vblanke << 16) | hblanke); |
1203 | evo_data(push, (vblanks << 16) | hblanks); |
1204 | evo_data(push, (vblan2e << 16) | vblan2s); |
1205 | evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1); |
1206 | evo_data(push, 0x00000000); |
1207 | evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2); |
1208 | evo_data(push, 0x00000311); |
1209 | evo_data(push, 0x00000100); |
1210 | } else { |
1211 | evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6); |
1212 | evo_data(push, 0x00000000); |
1213 | evo_data(push, (vactive << 16) | hactive); |
1214 | evo_data(push, ( vsynce << 16) | hsynce); |
1215 | evo_data(push, (vblanke << 16) | hblanke); |
1216 | evo_data(push, (vblanks << 16) | hblanks); |
1217 | evo_data(push, (vblan2e << 16) | vblan2s); |
1218 | evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1); |
1219 | evo_data(push, 0x00000000); /* ??? */ |
1220 | evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3); |
1221 | evo_data(push, mode->clock * 1000); |
1222 | evo_data(push, 0x00200000); /* ??? */ |
1223 | evo_data(push, mode->clock * 1000); |
1224 | evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2); |
1225 | evo_data(push, 0x00000311); |
1226 | evo_data(push, 0x00000100); |
1227 | } |
1228 | |
1229 | evo_kick(push, mast); |
1230 | } |
1231 | |
1232 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
1233 | nv50_crtc_set_dither(nv_crtc, false); |
1234 | nv50_crtc_set_scale(nv_crtc, false); |
1235 | nv50_crtc_set_color_vibrance(nv_crtc, false); |
1236 | nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false); |
1237 | return 0; |
1238 | } |
1239 | |
1240 | static int |
1241 | nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
1242 | struct drm_framebuffer *old_fb) |
1243 | { |
1244 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); |
1245 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1246 | int ret; |
1247 | |
1248 | if (!crtc->primary->fb) { |
1249 | NV_DEBUG(drm, "No FB bound\n" ); |
1250 | return 0; |
1251 | } |
1252 | |
1253 | ret = nv50_crtc_swap_fbs(crtc, old_fb); |
1254 | if (ret) |
1255 | return ret; |
1256 | |
1257 | nv50_display_flip_stop(crtc); |
1258 | nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true); |
1259 | nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1); |
1260 | return 0; |
1261 | } |
1262 | |
1263 | static int |
1264 | nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc, |
1265 | struct drm_framebuffer *fb, int x, int y, |
1266 | enum mode_set_atomic state) |
1267 | { |
1268 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1269 | nv50_display_flip_stop(crtc); |
1270 | nv50_crtc_set_image(nv_crtc, fb, x, y, true); |
1271 | return 0; |
1272 | } |
1273 | |
1274 | static void |
1275 | nv50_crtc_lut_load(struct drm_crtc *crtc) |
1276 | { |
1277 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
1278 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1279 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); |
1280 | int i; |
1281 | |
1282 | for (i = 0; i < 256; i++) { |
1283 | u16 r = nv_crtc->lut.r[i] >> 2; |
1284 | u16 g = nv_crtc->lut.g[i] >> 2; |
1285 | u16 b = nv_crtc->lut.b[i] >> 2; |
1286 | |
1287 | if (nv_mclass(disp->core) < NVD0_DISP_CLASS) { |
1288 | writew(r + 0x0000, (char __iomem *)lut + (i * 0x08) + 0); |
1289 | writew(g + 0x0000, (char __iomem *)lut + (i * 0x08) + 2); |
1290 | writew(b + 0x0000, (char __iomem *)lut + (i * 0x08) + 4); |
1291 | } else { |
1292 | writew(r + 0x6000, (char __iomem *)lut + (i * 0x20) + 0); |
1293 | writew(g + 0x6000, (char __iomem *)lut + (i * 0x20) + 2); |
1294 | writew(b + 0x6000, (char __iomem *)lut + (i * 0x20) + 4); |
1295 | } |
1296 | } |
1297 | } |
1298 | |
1299 | static void |
1300 | nv50_crtc_disable(struct drm_crtc *crtc) |
1301 | { |
1302 | struct nv50_head *head = nv50_head(crtc); |
1303 | if (head->image) |
1304 | nouveau_bo_unpin(head->image); |
1305 | nouveau_bo_ref(NULL, &head->image); |
1306 | } |
1307 | |
1308 | static int |
1309 | nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, |
1310 | uint32_t handle, uint32_t width, uint32_t height) |
1311 | { |
1312 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1313 | struct drm_device *dev = crtc->dev; |
1314 | struct drm_gem_object *gem; |
1315 | struct nouveau_bo *nvbo; |
1316 | bool visible = (handle != 0); |
1317 | int i, ret = 0; |
1318 | |
1319 | if (visible) { |
1320 | if (width != 64 || height != 64) |
1321 | return -EINVAL; |
1322 | |
1323 | gem = drm_gem_object_lookup(dev, file_priv, handle); |
1324 | if (unlikely(!gem)) |
1325 | return -ENOENT; |
1326 | nvbo = nouveau_gem_object(gem); |
1327 | |
1328 | ret = nouveau_bo_map(nvbo); |
1329 | if (ret == 0) { |
1330 | for (i = 0; i < 64 * 64; i++) { |
1331 | u32 v = nouveau_bo_rd32(nvbo, i); |
1332 | nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v); |
1333 | } |
1334 | nouveau_bo_unmap(nvbo); |
1335 | } |
1336 | |
1337 | drm_gem_object_unreference_unlocked(gem); |
1338 | } |
1339 | |
1340 | if (visible != nv_crtc->cursor.visible) { |
1341 | nv50_crtc_cursor_show_hide(nv_crtc, visible, true); |
1342 | nv_crtc->cursor.visible = visible; |
1343 | } |
1344 | |
1345 | return ret; |
1346 | } |
1347 | |
1348 | static int |
1349 | nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
1350 | { |
1351 | struct nv50_curs *curs = nv50_curs(crtc); |
1352 | struct nv50_chan *chan = nv50_chan(curs); |
1353 | nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff)); |
1354 | nv_wo32(chan->user, 0x0080, 0x00000000); |
1355 | return 0; |
1356 | } |
1357 | |
1358 | static void |
1359 | nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, |
1360 | uint32_t start, uint32_t size) |
1361 | { |
1362 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1363 | u32 end = min_t(u32, start + size, 256); |
1364 | u32 i; |
1365 | |
1366 | for (i = start; i < end; i++) { |
1367 | nv_crtc->lut.r[i] = r[i]; |
1368 | nv_crtc->lut.g[i] = g[i]; |
1369 | nv_crtc->lut.b[i] = b[i]; |
1370 | } |
1371 | |
1372 | nv50_crtc_lut_load(crtc); |
1373 | } |
1374 | |
1375 | static void |
1376 | nv50_crtc_destroy(struct drm_crtc *crtc) |
1377 | { |
1378 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1379 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
1380 | struct nv50_head *head = nv50_head(crtc); |
1381 | |
1382 | nv50_dmac_destroy(disp->core, &head->ovly.base); |
1383 | nv50_pioc_destroy(disp->core, &head->oimm.base); |
1384 | nv50_dmac_destroy(disp->core, &head->sync.base); |
1385 | nv50_pioc_destroy(disp->core, &head->curs.base); |
1386 | |
1387 | /*XXX: this shouldn't be necessary, but the core doesn't call |
1388 | * disconnect() during the cleanup paths |
1389 | */ |
1390 | if (head->image) |
1391 | nouveau_bo_unpin(head->image); |
1392 | nouveau_bo_ref(NULL, &head->image); |
1393 | |
1394 | nouveau_bo_unmap(nv_crtc->cursor.nvbo); |
1395 | if (nv_crtc->cursor.nvbo) |
1396 | nouveau_bo_unpin(nv_crtc->cursor.nvbo); |
1397 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); |
1398 | |
1399 | nouveau_bo_unmap(nv_crtc->lut.nvbo); |
1400 | if (nv_crtc->lut.nvbo) |
1401 | nouveau_bo_unpin(nv_crtc->lut.nvbo); |
1402 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); |
1403 | |
1404 | drm_crtc_cleanup(crtc); |
1405 | kfree(crtc); |
1406 | } |
1407 | |
1408 | static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = { |
1409 | .dpms = nv50_crtc_dpms, |
1410 | .prepare = nv50_crtc_prepare, |
1411 | .commit = nv50_crtc_commit, |
1412 | .mode_fixup = nv50_crtc_mode_fixup, |
1413 | .mode_set = nv50_crtc_mode_set, |
1414 | .mode_set_base = nv50_crtc_mode_set_base, |
1415 | .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic, |
1416 | .load_lut = nv50_crtc_lut_load, |
1417 | .disable = nv50_crtc_disable, |
1418 | }; |
1419 | |
1420 | static const struct drm_crtc_funcs nv50_crtc_func = { |
1421 | .cursor_set = nv50_crtc_cursor_set, |
1422 | .cursor_move = nv50_crtc_cursor_move, |
1423 | .gamma_set = nv50_crtc_gamma_set, |
1424 | .set_config = nouveau_crtc_set_config, |
1425 | .destroy = nv50_crtc_destroy, |
1426 | .page_flip = nouveau_crtc_page_flip, |
1427 | }; |
1428 | |
1429 | static void |
1430 | nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) |
1431 | { |
1432 | } |
1433 | |
1434 | static void |
1435 | nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) |
1436 | { |
1437 | } |
1438 | |
1439 | static int |
1440 | nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index) |
1441 | { |
1442 | struct nv50_disp *disp = nv50_disp(dev); |
1443 | struct nv50_head *head; |
1444 | struct drm_crtc *crtc; |
1445 | int ret, i; |
1446 | |
1447 | head = kzalloc(sizeof(*head), GFP_KERNEL); |
1448 | if (!head) |
1449 | return -ENOMEM; |
1450 | |
1451 | head->base.index = index; |
1452 | head->base.set_dither = nv50_crtc_set_dither; |
1453 | head->base.set_scale = nv50_crtc_set_scale; |
1454 | head->base.set_color_vibrance = nv50_crtc_set_color_vibrance; |
1455 | head->base.color_vibrance = 50; |
1456 | head->base.vibrant_hue = 0; |
1457 | head->base.cursor.set_offset = nv50_cursor_set_offset; |
1458 | head->base.cursor.set_pos = nv50_cursor_set_pos; |
1459 | for (i = 0; i < 256; i++) { |
1460 | head->base.lut.r[i] = i << 8; |
1461 | head->base.lut.g[i] = i << 8; |
1462 | head->base.lut.b[i] = i << 8; |
1463 | } |
1464 | |
1465 | crtc = &head->base.base; |
1466 | drm_crtc_init(dev, crtc, &nv50_crtc_func); |
1467 | drm_crtc_helper_add(crtc, &nv50_crtc_hfunc); |
1468 | drm_mode_crtc_set_gamma_size(crtc, 256); |
1469 | |
1470 | ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM, |
1471 | 0, 0x0000, NULL, &head->base.lut.nvbo); |
1472 | if (!ret) { |
1473 | ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM); |
1474 | if (!ret) { |
1475 | ret = nouveau_bo_map(head->base.lut.nvbo); |
1476 | if (ret) |
1477 | nouveau_bo_unpin(head->base.lut.nvbo); |
1478 | } |
1479 | if (ret) |
1480 | nouveau_bo_ref(NULL, &head->base.lut.nvbo); |
1481 | } |
1482 | |
1483 | if (ret) |
1484 | goto out; |
1485 | |
1486 | nv50_crtc_lut_load(crtc); |
1487 | |
1488 | /* allocate cursor resources */ |
1489 | ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index, |
1490 | &(struct nv50_display_curs_class) { |
1491 | .head = index, |
1492 | }, sizeof(struct nv50_display_curs_class), |
1493 | &head->curs.base); |
1494 | if (ret) |
1495 | goto out; |
1496 | |
1497 | ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM, |
1498 | 0, 0x0000, NULL, &head->base.cursor.nvbo); |
1499 | if (!ret) { |
1500 | ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM); |
1501 | if (!ret) { |
1502 | ret = nouveau_bo_map(head->base.cursor.nvbo); |
1503 | if (ret) |
1504 | nouveau_bo_unpin(head->base.lut.nvbo); |
1505 | } |
1506 | if (ret) |
1507 | nouveau_bo_ref(NULL, &head->base.cursor.nvbo); |
1508 | } |
1509 | |
1510 | if (ret) |
1511 | goto out; |
1512 | |
1513 | /* allocate page flip / sync resources */ |
1514 | ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index, |
1515 | &(struct nv50_display_sync_class) { |
1516 | .pushbuf = EVO_PUSH_HANDLE(SYNC, index), |
1517 | .head = index, |
1518 | }, sizeof(struct nv50_display_sync_class), |
1519 | disp->sync->bo.offset, &head->sync.base); |
1520 | if (ret) |
1521 | goto out; |
1522 | |
1523 | head->sync.addr = EVO_FLIP_SEM0(index); |
1524 | head->sync.data = 0x00000000; |
1525 | |
1526 | /* allocate overlay resources */ |
1527 | ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index, |
1528 | &(struct nv50_display_oimm_class) { |
1529 | .head = index, |
1530 | }, sizeof(struct nv50_display_oimm_class), |
1531 | &head->oimm.base); |
1532 | if (ret) |
1533 | goto out; |
1534 | |
1535 | ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index, |
1536 | &(struct nv50_display_ovly_class) { |
1537 | .pushbuf = EVO_PUSH_HANDLE(OVLY, index), |
1538 | .head = index, |
1539 | }, sizeof(struct nv50_display_ovly_class), |
1540 | disp->sync->bo.offset, &head->ovly.base); |
1541 | if (ret) |
1542 | goto out; |
1543 | |
1544 | out: |
1545 | if (ret) |
1546 | nv50_crtc_destroy(crtc); |
1547 | return ret; |
1548 | } |
1549 | |
1550 | /****************************************************************************** |
1551 | * DAC |
1552 | *****************************************************************************/ |
1553 | static void |
1554 | nv50_dac_dpms(struct drm_encoder *encoder, int mode) |
1555 | { |
1556 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1557 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1558 | int or = nv_encoder->or; |
1559 | u32 dpms_ctrl; |
1560 | |
1561 | dpms_ctrl = 0x00000000; |
1562 | if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF) |
1563 | dpms_ctrl |= 0x00000001; |
1564 | if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF) |
1565 | dpms_ctrl |= 0x00000004; |
1566 | |
1567 | nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl); |
1568 | } |
1569 | |
1570 | static bool |
1571 | nv50_dac_mode_fixup(struct drm_encoder *encoder, |
1572 | const struct drm_display_mode *mode, |
1573 | struct drm_display_mode *adjusted_mode) |
1574 | { |
1575 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1576 | struct nouveau_connector *nv_connector; |
1577 | |
1578 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
1579 | if (nv_connector && nv_connector->native_mode) { |
1580 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { |
1581 | int id = adjusted_mode->base.id; |
1582 | *adjusted_mode = *nv_connector->native_mode; |
1583 | adjusted_mode->base.id = id; |
1584 | } |
1585 | } |
1586 | |
1587 | return true; |
1588 | } |
1589 | |
1590 | static void |
1591 | nv50_dac_commit(struct drm_encoder *encoder) |
1592 | { |
1593 | } |
1594 | |
1595 | static void |
1596 | nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
1597 | struct drm_display_mode *adjusted_mode) |
1598 | { |
1599 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
1600 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1601 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
1602 | u32 *push; |
1603 | |
1604 | nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
1605 | |
1606 | push = evo_wait(mast, 8); |
1607 | if (push) { |
1608 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
1609 | u32 syncs = 0x00000000; |
1610 | |
1611 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
1612 | syncs |= 0x00000001; |
1613 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
1614 | syncs |= 0x00000002; |
1615 | |
1616 | evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2); |
1617 | evo_data(push, 1 << nv_crtc->index); |
1618 | evo_data(push, syncs); |
1619 | } else { |
1620 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); |
1621 | u32 syncs = 0x00000001; |
1622 | |
1623 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
1624 | syncs |= 0x00000008; |
1625 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
1626 | syncs |= 0x00000010; |
1627 | |
1628 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
1629 | magic |= 0x00000001; |
1630 | |
1631 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); |
1632 | evo_data(push, syncs); |
1633 | evo_data(push, magic); |
1634 | evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1); |
1635 | evo_data(push, 1 << nv_crtc->index); |
1636 | } |
1637 | |
1638 | evo_kick(push, mast); |
1639 | } |
1640 | |
1641 | nv_encoder->crtc = encoder->crtc; |
1642 | } |
1643 | |
1644 | static void |
1645 | nv50_dac_disconnect(struct drm_encoder *encoder) |
1646 | { |
1647 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1648 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
1649 | const int or = nv_encoder->or; |
1650 | u32 *push; |
1651 | |
1652 | if (nv_encoder->crtc) { |
1653 | nv50_crtc_prepare(nv_encoder->crtc); |
1654 | |
1655 | push = evo_wait(mast, 4); |
1656 | if (push) { |
1657 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
1658 | evo_mthd(push, 0x0400 + (or * 0x080), 1); |
1659 | evo_data(push, 0x00000000); |
1660 | } else { |
1661 | evo_mthd(push, 0x0180 + (or * 0x020), 1); |
1662 | evo_data(push, 0x00000000); |
1663 | } |
1664 | evo_kick(push, mast); |
1665 | } |
1666 | } |
1667 | |
1668 | nv_encoder->crtc = NULL; |
1669 | } |
1670 | |
1671 | static enum drm_connector_status |
1672 | nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
1673 | { |
1674 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1675 | int ret, or = nouveau_encoder(encoder)->or; |
1676 | u32 load = nouveau_drm(encoder->dev)->vbios.dactestval; |
1677 | if (load == 0) |
1678 | load = 340; |
1679 | |
1680 | ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load)); |
1681 | if (ret || !load) |
1682 | return connector_status_disconnected; |
1683 | |
1684 | return connector_status_connected; |
1685 | } |
1686 | |
1687 | static void |
1688 | nv50_dac_destroy(struct drm_encoder *encoder) |
1689 | { |
1690 | drm_encoder_cleanup(encoder); |
1691 | kfree(encoder); |
1692 | } |
1693 | |
1694 | static const struct drm_encoder_helper_funcs nv50_dac_hfunc = { |
1695 | .dpms = nv50_dac_dpms, |
1696 | .mode_fixup = nv50_dac_mode_fixup, |
1697 | .prepare = nv50_dac_disconnect, |
1698 | .commit = nv50_dac_commit, |
1699 | .mode_set = nv50_dac_mode_set, |
1700 | .disable = nv50_dac_disconnect, |
1701 | .get_crtc = nv50_display_crtc_get, |
1702 | .detect = nv50_dac_detect |
1703 | }; |
1704 | |
1705 | static const struct drm_encoder_funcs nv50_dac_func = { |
1706 | .destroy = nv50_dac_destroy, |
1707 | }; |
1708 | |
1709 | static int |
1710 | nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) |
1711 | { |
1712 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
1713 | struct nouveau_i2c *i2c = nouveau_i2c(drm->device); |
1714 | struct nouveau_encoder *nv_encoder; |
1715 | struct drm_encoder *encoder; |
1716 | int type = DRM_MODE_ENCODER_DAC; |
1717 | |
1718 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); |
1719 | if (!nv_encoder) |
1720 | return -ENOMEM; |
1721 | nv_encoder->dcb = dcbe; |
1722 | nv_encoder->or = ffs(dcbe->or) - 1; |
1723 | nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index); |
1724 | |
1725 | encoder = to_drm_encoder(nv_encoder); |
1726 | encoder->possible_crtcs = dcbe->heads; |
1727 | encoder->possible_clones = 0; |
1728 | drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type); |
1729 | drm_encoder_helper_add(encoder, &nv50_dac_hfunc); |
1730 | |
1731 | drm_mode_connector_attach_encoder(connector, encoder); |
1732 | return 0; |
1733 | } |
1734 | |
1735 | /****************************************************************************** |
1736 | * Audio |
1737 | *****************************************************************************/ |
1738 | static void |
1739 | nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) |
1740 | { |
1741 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1742 | struct nouveau_connector *nv_connector; |
1743 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1744 | |
1745 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
1746 | if (!drm_detect_monitor_audio(nv_connector->edid)) |
1747 | return; |
1748 | |
1749 | drm_edid_to_eld(&nv_connector->base, nv_connector->edid); |
1750 | |
1751 | nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, |
1752 | nv_connector->base.eld, |
1753 | nv_connector->base.eld[2] * 4); |
1754 | } |
1755 | |
1756 | static void |
1757 | nv50_audio_disconnect(struct drm_encoder *encoder) |
1758 | { |
1759 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1760 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1761 | |
1762 | nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0); |
1763 | } |
1764 | |
1765 | /****************************************************************************** |
1766 | * HDMI |
1767 | *****************************************************************************/ |
1768 | static void |
1769 | nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) |
1770 | { |
1771 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1772 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
1773 | struct nouveau_connector *nv_connector; |
1774 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1775 | const u32 moff = (nv_crtc->index << 3) | nv_encoder->or; |
1776 | u32 rekey = 56; /* binary driver, and tegra constant */ |
1777 | u32 max_ac_packet; |
1778 | |
1779 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
1780 | if (!drm_detect_hdmi_monitor(nv_connector->edid)) |
1781 | return; |
1782 | |
1783 | max_ac_packet = mode->htotal - mode->hdisplay; |
1784 | max_ac_packet -= rekey; |
1785 | max_ac_packet -= 18; /* constant from tegra */ |
1786 | max_ac_packet /= 32; |
1787 | |
1788 | nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, |
1789 | NV84_DISP_SOR_HDMI_PWR_STATE_ON | |
1790 | (max_ac_packet << 16) | rekey); |
1791 | |
1792 | nv50_audio_mode_set(encoder, mode); |
1793 | } |
1794 | |
1795 | static void |
1796 | nv50_hdmi_disconnect(struct drm_encoder *encoder) |
1797 | { |
1798 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1799 | struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); |
1800 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1801 | const u32 moff = (nv_crtc->index << 3) | nv_encoder->or; |
1802 | |
1803 | nv50_audio_disconnect(encoder); |
1804 | |
1805 | nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000); |
1806 | } |
1807 | |
1808 | /****************************************************************************** |
1809 | * SOR |
1810 | *****************************************************************************/ |
1811 | static void |
1812 | nv50_sor_dpms(struct drm_encoder *encoder, int mode) |
1813 | { |
1814 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1815 | struct drm_device *dev = encoder->dev; |
1816 | struct nv50_disp *disp = nv50_disp(dev); |
1817 | struct drm_encoder *partner; |
1818 | int or = nv_encoder->or; |
1819 | |
1820 | nv_encoder->last_dpms = mode; |
1821 | |
1822 | list_for_each_entry(partner, &dev->mode_config.encoder_list, head) { |
1823 | struct nouveau_encoder *nv_partner = nouveau_encoder(partner); |
1824 | |
1825 | if (partner->encoder_type != DRM_MODE_ENCODER_TMDS) |
1826 | continue; |
1827 | |
1828 | if (nv_partner != nv_encoder && |
1829 | nv_partner->dcb->or == nv_encoder->dcb->or) { |
1830 | if (nv_partner->last_dpms == DRM_MODE_DPMS_ON) |
1831 | return; |
1832 | break; |
1833 | } |
1834 | } |
1835 | |
1836 | nv_call(disp->core, NV50_DISP_SOR_PWR + or, (mode == DRM_MODE_DPMS_ON)); |
1837 | } |
1838 | |
1839 | static bool |
1840 | nv50_sor_mode_fixup(struct drm_encoder *encoder, |
1841 | const struct drm_display_mode *mode, |
1842 | struct drm_display_mode *adjusted_mode) |
1843 | { |
1844 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1845 | struct nouveau_connector *nv_connector; |
1846 | |
1847 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
1848 | if (nv_connector && nv_connector->native_mode) { |
1849 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { |
1850 | int id = adjusted_mode->base.id; |
1851 | *adjusted_mode = *nv_connector->native_mode; |
1852 | adjusted_mode->base.id = id; |
1853 | } |
1854 | } |
1855 | |
1856 | return true; |
1857 | } |
1858 | |
1859 | static void |
1860 | nv50_sor_disconnect(struct drm_encoder *encoder) |
1861 | { |
1862 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1863 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
1864 | const int or = nv_encoder->or; |
1865 | u32 *push; |
1866 | |
1867 | if (nv_encoder->crtc) { |
1868 | nv50_crtc_prepare(nv_encoder->crtc); |
1869 | |
1870 | push = evo_wait(mast, 4); |
1871 | if (push) { |
1872 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
1873 | evo_mthd(push, 0x0600 + (or * 0x40), 1); |
1874 | evo_data(push, 0x00000000); |
1875 | } else { |
1876 | evo_mthd(push, 0x0200 + (or * 0x20), 1); |
1877 | evo_data(push, 0x00000000); |
1878 | } |
1879 | evo_kick(push, mast); |
1880 | } |
1881 | |
1882 | nv50_hdmi_disconnect(encoder); |
1883 | } |
1884 | |
1885 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; |
1886 | nv_encoder->crtc = NULL; |
1887 | } |
1888 | |
1889 | static void |
1890 | nv50_sor_commit(struct drm_encoder *encoder) |
1891 | { |
1892 | } |
1893 | |
1894 | static void |
1895 | nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, |
1896 | struct drm_display_mode *mode) |
1897 | { |
1898 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1899 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
1900 | struct drm_device *dev = encoder->dev; |
1901 | struct nouveau_drm *drm = nouveau_drm(dev); |
1902 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1903 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
1904 | struct nouveau_connector *nv_connector; |
1905 | struct nvbios *bios = &drm->vbios; |
1906 | u32 *push, lvds = 0; |
1907 | u8 owner = 1 << nv_crtc->index; |
1908 | u8 proto = 0xf; |
1909 | u8 depth = 0x0; |
1910 | |
1911 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
1912 | switch (nv_encoder->dcb->type) { |
1913 | case DCB_OUTPUT_TMDS: |
1914 | if (nv_encoder->dcb->sorconf.link & 1) { |
1915 | if (mode->clock < 165000) |
1916 | proto = 0x1; |
1917 | else |
1918 | proto = 0x5; |
1919 | } else { |
1920 | proto = 0x2; |
1921 | } |
1922 | |
1923 | nv50_hdmi_mode_set(encoder, mode); |
1924 | break; |
1925 | case DCB_OUTPUT_LVDS: |
1926 | proto = 0x0; |
1927 | |
1928 | if (bios->fp_no_ddc) { |
1929 | if (bios->fp.dual_link) |
1930 | lvds |= 0x0100; |
1931 | if (bios->fp.if_is_24bit) |
1932 | lvds |= 0x0200; |
1933 | } else { |
1934 | if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { |
1935 | if (((u8 *)nv_connector->edid)[121] == 2) |
1936 | lvds |= 0x0100; |
1937 | } else |
1938 | if (mode->clock >= bios->fp.duallink_transition_clk) { |
1939 | lvds |= 0x0100; |
1940 | } |
1941 | |
1942 | if (lvds & 0x0100) { |
1943 | if (bios->fp.strapless_is_24bit & 2) |
1944 | lvds |= 0x0200; |
1945 | } else { |
1946 | if (bios->fp.strapless_is_24bit & 1) |
1947 | lvds |= 0x0200; |
1948 | } |
1949 | |
1950 | if (nv_connector->base.display_info.bpc == 8) |
1951 | lvds |= 0x0200; |
1952 | } |
1953 | |
1954 | nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds); |
1955 | break; |
1956 | case DCB_OUTPUT_DP: |
1957 | if (nv_connector->base.display_info.bpc == 6) { |
1958 | nv_encoder->dp.datarate = mode->clock * 18 / 8; |
1959 | depth = 0x2; |
1960 | } else |
1961 | if (nv_connector->base.display_info.bpc == 8) { |
1962 | nv_encoder->dp.datarate = mode->clock * 24 / 8; |
1963 | depth = 0x5; |
1964 | } else { |
1965 | nv_encoder->dp.datarate = mode->clock * 30 / 8; |
1966 | depth = 0x6; |
1967 | } |
1968 | |
1969 | if (nv_encoder->dcb->sorconf.link & 1) |
1970 | proto = 0x8; |
1971 | else |
1972 | proto = 0x9; |
1973 | break; |
1974 | default: |
1975 | BUG_ON(1); |
1976 | break; |
1977 | } |
1978 | |
1979 | nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON); |
1980 | |
1981 | push = evo_wait(nv50_mast(dev), 8); |
1982 | if (push) { |
1983 | if (nv50_vers(mast) < NVD0_DISP_CLASS) { |
1984 | u32 ctrl = (depth << 16) | (proto << 8) | owner; |
1985 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
1986 | ctrl |= 0x00001000; |
1987 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
1988 | ctrl |= 0x00002000; |
1989 | evo_mthd(push, 0x0600 + (nv_encoder->or * 0x040), 1); |
1990 | evo_data(push, ctrl); |
1991 | } else { |
1992 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); |
1993 | u32 syncs = 0x00000001; |
1994 | |
1995 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
1996 | syncs |= 0x00000008; |
1997 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
1998 | syncs |= 0x00000010; |
1999 | |
2000 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
2001 | magic |= 0x00000001; |
2002 | |
2003 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); |
2004 | evo_data(push, syncs | (depth << 6)); |
2005 | evo_data(push, magic); |
2006 | evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 1); |
2007 | evo_data(push, owner | (proto << 8)); |
2008 | } |
2009 | |
2010 | evo_kick(push, mast); |
2011 | } |
2012 | |
2013 | nv_encoder->crtc = encoder->crtc; |
2014 | } |
2015 | |
2016 | static void |
2017 | nv50_sor_destroy(struct drm_encoder *encoder) |
2018 | { |
2019 | drm_encoder_cleanup(encoder); |
2020 | kfree(encoder); |
2021 | } |
2022 | |
2023 | static const struct drm_encoder_helper_funcs nv50_sor_hfunc = { |
2024 | .dpms = nv50_sor_dpms, |
2025 | .mode_fixup = nv50_sor_mode_fixup, |
2026 | .prepare = nv50_sor_disconnect, |
2027 | .commit = nv50_sor_commit, |
2028 | .mode_set = nv50_sor_mode_set, |
2029 | .disable = nv50_sor_disconnect, |
2030 | .get_crtc = nv50_display_crtc_get, |
2031 | }; |
2032 | |
2033 | static const struct drm_encoder_funcs nv50_sor_func = { |
2034 | .destroy = nv50_sor_destroy, |
2035 | }; |
2036 | |
2037 | static int |
2038 | nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) |
2039 | { |
2040 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
2041 | struct nouveau_i2c *i2c = nouveau_i2c(drm->device); |
2042 | struct nouveau_encoder *nv_encoder; |
2043 | struct drm_encoder *encoder; |
2044 | int type; |
2045 | |
2046 | switch (dcbe->type) { |
2047 | case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; |
2048 | case DCB_OUTPUT_TMDS: |
2049 | case DCB_OUTPUT_DP: |
2050 | default: |
2051 | type = DRM_MODE_ENCODER_TMDS; |
2052 | break; |
2053 | } |
2054 | |
2055 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); |
2056 | if (!nv_encoder) |
2057 | return -ENOMEM; |
2058 | nv_encoder->dcb = dcbe; |
2059 | nv_encoder->or = ffs(dcbe->or) - 1; |
2060 | nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index); |
2061 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; |
2062 | |
2063 | encoder = to_drm_encoder(nv_encoder); |
2064 | encoder->possible_crtcs = dcbe->heads; |
2065 | encoder->possible_clones = 0; |
2066 | drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type); |
2067 | drm_encoder_helper_add(encoder, &nv50_sor_hfunc); |
2068 | |
2069 | drm_mode_connector_attach_encoder(connector, encoder); |
2070 | return 0; |
2071 | } |
2072 | |
2073 | /****************************************************************************** |
2074 | * PIOR |
2075 | *****************************************************************************/ |
2076 | |
2077 | static void |
2078 | nv50_pior_dpms(struct drm_encoder *encoder, int mode) |
2079 | { |
2080 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
2081 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
2082 | u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or; |
2083 | u32 ctrl = (mode == DRM_MODE_DPMS_ON); |
2084 | nv_call(disp->core, NV50_DISP_PIOR_PWR + mthd, ctrl); |
2085 | } |
2086 | |
2087 | static bool |
2088 | nv50_pior_mode_fixup(struct drm_encoder *encoder, |
2089 | const struct drm_display_mode *mode, |
2090 | struct drm_display_mode *adjusted_mode) |
2091 | { |
2092 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
2093 | struct nouveau_connector *nv_connector; |
2094 | |
2095 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
2096 | if (nv_connector && nv_connector->native_mode) { |
2097 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { |
2098 | int id = adjusted_mode->base.id; |
2099 | *adjusted_mode = *nv_connector->native_mode; |
2100 | adjusted_mode->base.id = id; |
2101 | } |
2102 | } |
2103 | |
2104 | adjusted_mode->clock *= 2; |
2105 | return true; |
2106 | } |
2107 | |
2108 | static void |
2109 | nv50_pior_commit(struct drm_encoder *encoder) |
2110 | { |
2111 | } |
2112 | |
2113 | static void |
2114 | nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
2115 | struct drm_display_mode *adjusted_mode) |
2116 | { |
2117 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
2118 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
2119 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
2120 | struct nouveau_connector *nv_connector; |
2121 | u8 owner = 1 << nv_crtc->index; |
2122 | u8 proto, depth; |
2123 | u32 *push; |
2124 | |
2125 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
2126 | switch (nv_connector->base.display_info.bpc) { |
2127 | case 10: depth = 0x6; break; |
2128 | case 8: depth = 0x5; break; |
2129 | case 6: depth = 0x2; break; |
2130 | default: depth = 0x0; break; |
2131 | } |
2132 | |
2133 | switch (nv_encoder->dcb->type) { |
2134 | case DCB_OUTPUT_TMDS: |
2135 | case DCB_OUTPUT_DP: |
2136 | proto = 0x0; |
2137 | break; |
2138 | default: |
2139 | BUG_ON(1); |
2140 | break; |
2141 | } |
2142 | |
2143 | nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON); |
2144 | |
2145 | push = evo_wait(mast, 8); |
2146 | if (push) { |
2147 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
2148 | u32 ctrl = (depth << 16) | (proto << 8) | owner; |
2149 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
2150 | ctrl |= 0x00001000; |
2151 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
2152 | ctrl |= 0x00002000; |
2153 | evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1); |
2154 | evo_data(push, ctrl); |
2155 | } |
2156 | |
2157 | evo_kick(push, mast); |
2158 | } |
2159 | |
2160 | nv_encoder->crtc = encoder->crtc; |
2161 | } |
2162 | |
2163 | static void |
2164 | nv50_pior_disconnect(struct drm_encoder *encoder) |
2165 | { |
2166 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
2167 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
2168 | const int or = nv_encoder->or; |
2169 | u32 *push; |
2170 | |
2171 | if (nv_encoder->crtc) { |
2172 | nv50_crtc_prepare(nv_encoder->crtc); |
2173 | |
2174 | push = evo_wait(mast, 4); |
2175 | if (push) { |
2176 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
2177 | evo_mthd(push, 0x0700 + (or * 0x040), 1); |
2178 | evo_data(push, 0x00000000); |
2179 | } |
2180 | evo_kick(push, mast); |
2181 | } |
2182 | } |
2183 | |
2184 | nv_encoder->crtc = NULL; |
2185 | } |
2186 | |
2187 | static void |
2188 | nv50_pior_destroy(struct drm_encoder *encoder) |
2189 | { |
2190 | drm_encoder_cleanup(encoder); |
2191 | kfree(encoder); |
2192 | } |
2193 | |
2194 | static const struct drm_encoder_helper_funcs nv50_pior_hfunc = { |
2195 | .dpms = nv50_pior_dpms, |
2196 | .mode_fixup = nv50_pior_mode_fixup, |
2197 | .prepare = nv50_pior_disconnect, |
2198 | .commit = nv50_pior_commit, |
2199 | .mode_set = nv50_pior_mode_set, |
2200 | .disable = nv50_pior_disconnect, |
2201 | .get_crtc = nv50_display_crtc_get, |
2202 | }; |
2203 | |
2204 | static const struct drm_encoder_funcs nv50_pior_func = { |
2205 | .destroy = nv50_pior_destroy, |
2206 | }; |
2207 | |
2208 | static int |
2209 | nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) |
2210 | { |
2211 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
2212 | struct nouveau_i2c *i2c = nouveau_i2c(drm->device); |
2213 | struct nouveau_i2c_port *ddc = NULL; |
2214 | struct nouveau_encoder *nv_encoder; |
2215 | struct drm_encoder *encoder; |
2216 | int type; |
2217 | |
2218 | switch (dcbe->type) { |
2219 | case DCB_OUTPUT_TMDS: |
2220 | ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev)); |
2221 | type = DRM_MODE_ENCODER_TMDS; |
2222 | break; |
2223 | case DCB_OUTPUT_DP: |
2224 | ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev)); |
2225 | type = DRM_MODE_ENCODER_TMDS; |
2226 | break; |
2227 | default: |
2228 | return -ENODEV; |
2229 | } |
2230 | |
2231 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); |
2232 | if (!nv_encoder) |
2233 | return -ENOMEM; |
2234 | nv_encoder->dcb = dcbe; |
2235 | nv_encoder->or = ffs(dcbe->or) - 1; |
2236 | nv_encoder->i2c = ddc; |
2237 | |
2238 | encoder = to_drm_encoder(nv_encoder); |
2239 | encoder->possible_crtcs = dcbe->heads; |
2240 | encoder->possible_clones = 0; |
2241 | drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type); |
2242 | drm_encoder_helper_add(encoder, &nv50_pior_hfunc); |
2243 | |
2244 | drm_mode_connector_attach_encoder(connector, encoder); |
2245 | return 0; |
2246 | } |
2247 | |
2248 | /****************************************************************************** |
2249 | * Init |
2250 | *****************************************************************************/ |
2251 | void |
2252 | nv50_display_fini(struct drm_device *dev) |
2253 | { |
2254 | } |
2255 | |
2256 | int |
2257 | nv50_display_init(struct drm_device *dev) |
2258 | { |
2259 | struct nv50_disp *disp = nv50_disp(dev); |
2260 | struct drm_crtc *crtc; |
2261 | u32 *push; |
2262 | |
2263 | push = evo_wait(nv50_mast(dev), 32); |
2264 | if (!push) |
2265 | return -EBUSY; |
2266 | |
2267 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2268 | struct nv50_sync *sync = nv50_sync(crtc); |
2269 | nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data); |
2270 | } |
2271 | |
2272 | evo_mthd(push, 0x0088, 1); |
2273 | evo_data(push, NvEvoSync); |
2274 | evo_kick(push, nv50_mast(dev)); |
2275 | return 0; |
2276 | } |
2277 | |
2278 | void |
2279 | nv50_display_destroy(struct drm_device *dev) |
2280 | { |
2281 | struct nv50_disp *disp = nv50_disp(dev); |
2282 | |
2283 | nv50_dmac_destroy(disp->core, &disp->mast.base); |
2284 | |
2285 | nouveau_bo_unmap(disp->sync); |
2286 | if (disp->sync) |
2287 | nouveau_bo_unpin(disp->sync); |
2288 | nouveau_bo_ref(NULL, &disp->sync); |
2289 | |
2290 | nouveau_display(dev)->priv = NULL; |
2291 | kfree(disp); |
2292 | } |
2293 | |
2294 | int |
2295 | nv50_display_create(struct drm_device *dev) |
2296 | { |
2297 | struct nouveau_device *device = nouveau_dev(dev); |
2298 | struct nouveau_drm *drm = nouveau_drm(dev); |
2299 | struct dcb_table *dcb = &drm->vbios.dcb; |
2300 | struct drm_connector *connector, *tmp; |
2301 | struct nv50_disp *disp; |
2302 | struct dcb_output *dcbe; |
2303 | int crtcs, ret, i; |
2304 | |
2305 | disp = kzalloc(sizeof(*disp), GFP_KERNEL); |
2306 | if (!disp) |
2307 | return -ENOMEM; |
2308 | |
2309 | nouveau_display(dev)->priv = disp; |
2310 | nouveau_display(dev)->dtor = nv50_display_destroy; |
2311 | nouveau_display(dev)->init = nv50_display_init; |
2312 | nouveau_display(dev)->fini = nv50_display_fini; |
2313 | disp->core = nouveau_display(dev)->core; |
2314 | |
2315 | /* small shared memory area we use for notifiers and semaphores */ |
2316 | ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, |
2317 | 0, 0x0000, NULL, &disp->sync); |
2318 | if (!ret) { |
2319 | ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM); |
2320 | if (!ret) { |
2321 | ret = nouveau_bo_map(disp->sync); |
2322 | if (ret) |
2323 | nouveau_bo_unpin(disp->sync); |
2324 | } |
2325 | if (ret) |
2326 | nouveau_bo_ref(NULL, &disp->sync); |
2327 | } |
2328 | |
2329 | if (ret) |
2330 | goto out; |
2331 | |
2332 | /* allocate master evo channel */ |
2333 | ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0, |
2334 | &(struct nv50_display_mast_class) { |
2335 | .pushbuf = EVO_PUSH_HANDLE(MAST, 0), |
2336 | }, sizeof(struct nv50_display_mast_class), |
2337 | disp->sync->bo.offset, &disp->mast.base); |
2338 | if (ret) |
2339 | goto out; |
2340 | |
2341 | /* create crtc objects to represent the hw heads */ |
2342 | if (nv_mclass(disp->core) >= NVD0_DISP_CLASS) |
2343 | crtcs = nv_rd32(device, 0x022448); |
2344 | else |
2345 | crtcs = 2; |
2346 | |
2347 | for (i = 0; i < crtcs; i++) { |
2348 | ret = nv50_crtc_create(dev, disp->core, i); |
2349 | if (ret) |
2350 | goto out; |
2351 | } |
2352 | |
2353 | /* create encoder/connector objects based on VBIOS DCB table */ |
2354 | for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { |
2355 | connector = nouveau_connector_create(dev, dcbe->connector); |
2356 | if (IS_ERR(connector)) |
2357 | continue; |
2358 | |
2359 | if (dcbe->location == DCB_LOC_ON_CHIP) { |
2360 | switch (dcbe->type) { |
2361 | case DCB_OUTPUT_TMDS: |
2362 | case DCB_OUTPUT_LVDS: |
2363 | case DCB_OUTPUT_DP: |
2364 | ret = nv50_sor_create(connector, dcbe); |
2365 | break; |
2366 | case DCB_OUTPUT_ANALOG: |
2367 | ret = nv50_dac_create(connector, dcbe); |
2368 | break; |
2369 | default: |
2370 | ret = -ENODEV; |
2371 | break; |
2372 | } |
2373 | } else { |
2374 | ret = nv50_pior_create(connector, dcbe); |
2375 | } |
2376 | |
2377 | if (ret) { |
2378 | NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n" , |
2379 | dcbe->location, dcbe->type, |
2380 | ffs(dcbe->or) - 1, ret); |
2381 | ret = 0; |
2382 | } |
2383 | } |
2384 | |
2385 | /* cull any connectors we created that don't have an encoder */ |
2386 | list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { |
2387 | if (connector->encoder_ids[0]) |
2388 | continue; |
2389 | |
2390 | NV_WARN(drm, "%s has no encoders, removing\n" , |
2391 | drm_get_connector_name(connector)); |
2392 | connector->funcs->destroy(connector); |
2393 | } |
2394 | |
2395 | out: |
2396 | if (ret) |
2397 | nv50_display_destroy(dev); |
2398 | return ret; |
2399 | } |
2400 | |