1 | /* $NetBSD: if_vrreg.h,v 1.16 2006/11/05 13:05:18 tsutsui Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1997, 1998 |
5 | * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * 3. All advertising materials mentioning features or use of this software |
16 | * must display the following acknowledgement: |
17 | * This product includes software developed by Bill Paul. |
18 | * 4. Neither the name of the author nor the names of any co-contributors |
19 | * may be used to endorse or promote products derived from this software |
20 | * without specific prior written permission. |
21 | * |
22 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
23 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
25 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
26 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
29 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
30 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
31 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
32 | * THE POSSIBILITY OF SUCH DAMAGE. |
33 | * |
34 | * $FreeBSD: if_vrreg.h,v 1.2 1999/01/10 18:51:49 wpaul Exp $ |
35 | */ |
36 | |
37 | /* |
38 | * Rhine register definitions. |
39 | */ |
40 | |
41 | #define VR_PAR0 0x00 /* node address 0 to 4 */ |
42 | #define VR_PAR1 0x04 /* node address 2 to 6 */ |
43 | #define VR_RXCFG 0x06 /* receiver config register */ |
44 | #define VR_TXCFG 0x07 /* transmit config register */ |
45 | #define VR_COMMAND 0x08 /* command register */ |
46 | #define VR_ISR 0x0C /* interrupt/status register */ |
47 | #define VR_IMR 0x0E /* interrupt mask register */ |
48 | #define VR_MAR0 0x10 /* multicast hash 0 */ |
49 | #define VR_MAR1 0x14 /* multicast hash 1 */ |
50 | #define VR_RXADDR 0x18 /* rx descriptor list start addr */ |
51 | #define VR_TXADDR 0x1C /* tx descriptor list start addr */ |
52 | #define VR_CURRXDESC0 0x20 |
53 | #define VR_CURRXDESC1 0x24 |
54 | #define VR_CURRXDESC2 0x28 |
55 | #define VR_CURRXDESC3 0x2C |
56 | #define VR_NEXTRXDESC0 0x30 |
57 | #define VR_NEXTRXDESC1 0x34 |
58 | #define VR_NEXTRXDESC2 0x38 |
59 | #define VR_NEXTRXDESC3 0x3C |
60 | #define VR_CURTXDESC0 0x40 |
61 | #define VR_CURTXDESC1 0x44 |
62 | #define VR_CURTXDESC2 0x48 |
63 | #define VR_CURTXDESC3 0x4C |
64 | #define VR_NEXTTXDESC0 0x50 |
65 | #define VR_NEXTTXDESC1 0x54 |
66 | #define VR_NEXTTXDESC2 0x58 |
67 | #define VR_NEXTTXDESC3 0x5C |
68 | #define VR_CURRXDMA 0x60 /* current RX DMA address */ |
69 | #define VR_CURTXDMA 0x64 /* current TX DMA address */ |
70 | #define VR_TALLYCNT 0x68 /* tally counter test register */ |
71 | #define VR_PHYADDR 0x6C |
72 | #define VR_MIISTAT 0x6D |
73 | #define VR_BCR0 0x6E |
74 | #define VR_BCR1 0x6F |
75 | #define VR_MIICMD 0x70 |
76 | #define VR_MIIADDR 0x71 |
77 | #define VR_MIIDATA 0x72 |
78 | #define VR_EECSR 0x74 |
79 | #define VR_TEST 0x75 |
80 | #define VR_GPIO 0x76 |
81 | #define VR_CONFIG 0x78 |
82 | #define VR_MPA_CNT 0x7C |
83 | #define VR_CRC_CNT 0x7E |
84 | #define VR_STICKHW 0x83 |
85 | |
86 | /* Misc Registers */ |
87 | #define VR_MISC_CR1 0x81 |
88 | #define VR_MISCCR1_FORSRST 0x40 |
89 | |
90 | /* |
91 | * RX config bits. |
92 | */ |
93 | #define VR_RXCFG_RX_ERRPKTS 0x01 |
94 | #define VR_RXCFG_RX_RUNT 0x02 |
95 | #define VR_RXCFG_RX_MULTI 0x04 |
96 | #define VR_RXCFG_RX_BROAD 0x08 |
97 | #define VR_RXCFG_RX_PROMISC 0x10 |
98 | #define VR_RXCFG_RX_THRESH 0xE0 |
99 | |
100 | #define VR_RXTHRESH_32BYTES 0x00 |
101 | #define VR_RXTHRESH_64BYTES 0x20 |
102 | #define VR_RXTHRESH_128BYTES 0x40 |
103 | #define VR_RXTHRESH_256BYTES 0x60 |
104 | #define VR_RXTHRESH_512BYTES 0x80 |
105 | #define VR_RXTHRESH_768BYTES 0xA0 |
106 | #define VR_RXTHRESH_1024BYTES 0xC0 |
107 | #define VR_RXTHRESH_STORENFWD 0xE0 |
108 | |
109 | /* |
110 | * TX config bits. |
111 | */ |
112 | #define VR_TXCFG_RSVD0 0x01 |
113 | #define VR_TXCFG_LOOPBKMODE 0x06 |
114 | #define VR_TXCFG_BACKOFF 0x08 |
115 | #define VR_TXCFG_RSVD1 0x10 |
116 | #define VR_TXCFG_TX_THRESH 0xE0 |
117 | |
118 | #define VR_TXTHRESH_32BYTES 0x00 |
119 | #define VR_TXTHRESH_64BYTES 0x20 |
120 | #define VR_TXTHRESH_128BYTES 0x40 |
121 | #define VR_TXTHRESH_256BYTES 0x60 |
122 | #define VR_TXTHRESH_512BYTES 0x80 |
123 | #define VR_TXTHRESH_768BYTES 0xA0 |
124 | #define VR_TXTHRESH_1024BYTES 0xC0 |
125 | #define VR_TXTHRESH_STORENFWD 0xE0 |
126 | |
127 | /* |
128 | * Command register bits. |
129 | */ |
130 | #define VR_CMD_INIT 0x0001 |
131 | #define VR_CMD_START 0x0002 |
132 | #define VR_CMD_STOP 0x0004 |
133 | #define VR_CMD_RX_ON 0x0008 |
134 | #define VR_CMD_TX_ON 0x0010 |
135 | #define VR_CMD_TX_GO 0x0020 |
136 | #define VR_CMD_RX_GO 0x0040 |
137 | #define VR_CMD_RSVD 0x0080 |
138 | #define VR_CMD_RX_EARLY 0x0100 |
139 | #define VR_CMD_TX_EARLY 0x0200 |
140 | #define VR_CMD_FULLDUPLEX 0x0400 |
141 | #define VR_CMD_TX_NOPOLL 0x0800 |
142 | |
143 | #define VR_CMD_RESET 0x8000 |
144 | |
145 | /* |
146 | * Interrupt status bits. |
147 | */ |
148 | #define VR_ISR_RX_OK 0x0001 /* packet rx ok */ |
149 | #define VR_ISR_TX_OK 0x0002 /* packet tx ok */ |
150 | #define VR_ISR_RX_ERR 0x0004 /* packet rx with err */ |
151 | #define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ |
152 | #define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ |
153 | #define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */ |
154 | #define VR_ISR_BUSERR 0x0040 /* PCI bus error */ |
155 | #define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */ |
156 | #define VR_ISR_RX_EARLY 0x0100 /* rx early */ |
157 | #define VR_ISR_LINKSTAT 0x0200 /* MII status change */ |
158 | #define VR_ISR_TX_ETI 0x0200 /* TX early (3043/3071) */ |
159 | #define VR_ISR_TX_UDFI 0x0200 /* TX FIFO underflow (3065) */ |
160 | #define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */ |
161 | #define VR_ISR_RX_DROPPED 0x0800 |
162 | #define VR_ISR_RX_NOBUF2 0x1000 |
163 | #define VR_ISR_TX_ABRT2 0x2000 |
164 | #define VR_ISR_LINKSTAT2 0x4000 |
165 | #define VR_ISR_MAGICPACKET 0x8000 |
166 | |
167 | /* |
168 | * Interrupt mask bits. |
169 | */ |
170 | #define VR_IMR_RX_OK 0x0001 /* packet rx ok */ |
171 | #define VR_IMR_TX_OK 0x0002 /* packet tx ok */ |
172 | #define VR_IMR_RX_ERR 0x0004 /* packet rx with err */ |
173 | #define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ |
174 | #define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ |
175 | #define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */ |
176 | #define VR_IMR_BUSERR 0x0040 /* PCI bus error */ |
177 | #define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */ |
178 | #define VR_IMR_RX_EARLY 0x0100 /* rx early */ |
179 | #define VR_IMR_LINKSTAT 0x0200 /* MII status change */ |
180 | #define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */ |
181 | #define VR_IMR_RX_DROPPED 0x0800 |
182 | #define VR_IMR_RX_NOBUF2 0x1000 |
183 | #define VR_IMR_TX_ABRT2 0x2000 |
184 | #define VR_IMR_LINKSTAT2 0x4000 |
185 | #define VR_IMR_MAGICPACKET 0x8000 |
186 | |
187 | #define VR_INTRS \ |
188 | (VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \ |
189 | VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \ |
190 | VR_IMR_RX_ERR|VR_ISR_RX_DROPPED) |
191 | |
192 | /* |
193 | * MII status register. |
194 | */ |
195 | |
196 | #define VR_MIISTAT_SPEED 0x01 |
197 | #define VR_MIISTAT_LINKFAULT 0x02 |
198 | #define VR_MIISTAT_MGTREADERR 0x04 |
199 | #define VR_MIISTAT_MIIERR 0x08 |
200 | #define VR_MIISTAT_PHYOPT 0x10 |
201 | #define VR_MIISTAT_MDC_SPEED 0x20 |
202 | #define VR_MIISTAT_RSVD 0x40 |
203 | #define VR_MIISTAT_GPIO1POLL 0x80 |
204 | |
205 | /* |
206 | * MII command register bits. |
207 | */ |
208 | #define VR_MIICMD_CLK 0x01 |
209 | #define VR_MIICMD_DATAIN 0x02 |
210 | #define VR_MIICMD_DATAOUT 0x04 |
211 | #define VR_MIICMD_DIR 0x08 |
212 | #define VR_MIICMD_DIRECTPGM 0x10 |
213 | #define VR_MIICMD_WRITE_ENB 0x20 |
214 | #define VR_MIICMD_READ_ENB 0x40 |
215 | #define VR_MIICMD_AUTOPOLL 0x80 |
216 | |
217 | /* |
218 | * EEPROM control bits. |
219 | */ |
220 | #define VR_EECSR_DATAIN 0x01 /* data out */ |
221 | #define VR_EECSR_DATAOUT 0x02 /* data in */ |
222 | #define VR_EECSR_CLK 0x04 /* clock */ |
223 | #define VR_EECSR_CS 0x08 /* chip select */ |
224 | #define VR_EECSR_DPM 0x10 |
225 | #define VR_EECSR_LOAD 0x20 |
226 | #define VR_EECSR_EMBP 0x40 |
227 | #define VR_EECSR_EEPR 0x80 |
228 | |
229 | #define VR_EECMD_WRITE 0x140 |
230 | #define VR_EECMD_READ 0x180 |
231 | #define VR_EECMD_ERASE 0x1c0 |
232 | |
233 | /* |
234 | * Test register bits. |
235 | */ |
236 | #define VR_TEST_TEST0 0x01 |
237 | #define VR_TEST_TEST1 0x02 |
238 | #define VR_TEST_TEST2 0x04 |
239 | #define VR_TEST_TSTUD 0x08 |
240 | #define VR_TEST_TSTOV 0x10 |
241 | #define VR_TEST_BKOFF 0x20 |
242 | #define VR_TEST_FCOL 0x40 |
243 | #define VR_TEST_HBDES 0x80 |
244 | |
245 | /* |
246 | * Config register bits. |
247 | */ |
248 | #define VR_CFG_GPIO2OUTENB 0x00000001 |
249 | #define VR_CFG_GPIO2OUT 0x00000002 /* gen. purp. pin */ |
250 | #define VR_CFG_GPIO2IN 0x00000004 /* gen. purp. pin */ |
251 | #define VR_CFG_AUTOOPT 0x00000008 /* enable rx/tx autopoll */ |
252 | #define VR_CFG_MIIOPT 0x00000010 |
253 | #define VR_CFG_MMIENB 0x00000020 /* memory mapped mode enb */ |
254 | #define VR_CFG_JUMPER 0x00000040 /* PHY and oper. mode select */ |
255 | #define VR_CFG_EELOAD 0x00000080 /* enable EEPROM programming */ |
256 | #define VR_CFG_LATMENB 0x00000100 /* larency timer effect enb. */ |
257 | #define VR_CFG_MRREADWAIT 0x00000200 |
258 | #define VR_CFG_MRWRITEWAIT 0x00000400 |
259 | #define VR_CFG_RX_ARB 0x00000800 |
260 | #define VR_CFG_TX_ARB 0x00001000 |
261 | #define VR_CFG_READMULTI 0x00002000 |
262 | #define VR_CFG_TX_PACE 0x00004000 |
263 | #define VR_CFG_TX_QDIS 0x00008000 |
264 | #define VR_CFG_ROMSEL0 0x00010000 |
265 | #define VR_CFG_ROMSEL1 0x00020000 |
266 | #define VR_CFG_ROMSEL2 0x00040000 |
267 | #define VR_CFG_ROMTIMESEL 0x00080000 |
268 | #define VR_CFG_RSVD0 0x00100000 |
269 | #define VR_CFG_ROMDLY 0x00200000 |
270 | #define VR_CFG_ROMOPT 0x00400000 |
271 | #define VR_CFG_RSVD1 0x00800000 |
272 | #define VR_CFG_BACKOFFOPT 0x01000000 |
273 | #define VR_CFG_BACKOFFMOD 0x02000000 |
274 | #define VR_CFG_CAPEFFECT 0x04000000 |
275 | #define VR_CFG_BACKOFFRAND 0x08000000 |
276 | #define VR_CFG_MAGICKPACKET 0x10000000 |
277 | #define VR_CFG_PCIREADLINE 0x20000000 |
278 | #define VR_CFG_DIAG 0x40000000 |
279 | #define VR_CFG_GPIOEN 0x80000000 |
280 | |
281 | /* Sticky HW bits */ |
282 | #define VR_STICKHW_DS0 0x01 |
283 | #define VR_STICKHW_DS1 0x02 |
284 | #define VR_STICKHW_WOL_ENB 0x04 |
285 | #define VR_STICKHW_WOL_STS 0x08 |
286 | #define VR_STICKHW_LEGWOL_ENB 0x80 |
287 | |
288 | /* |
289 | * BCR0 register bits. |
290 | */ |
291 | #define VR_BCR0_DMA_LENGTH 0x07 |
292 | #define VR_BCR0_DMA_32BYTES 0x00 |
293 | #define VR_BCR0_DMA_64BYTES 0x01 |
294 | #define VR_BCR0_DMA_128BYTES 0x02 |
295 | #define VR_BCR0_DMA_256BYTES 0x03 |
296 | #define VR_BCR0_DMA_512BYTES 0x04 |
297 | #define VR_BCR0_DMA_1024BYTES 0x05 |
298 | #define VR_BCR0_DMA_STORENFWD 0x07 |
299 | |
300 | #define VR_BCR0_RX_THRESH 0x38 |
301 | #define VR_BCR0_RXTH_CFG 0x00 |
302 | #define VR_BCR0_RXTH_64BYTES 0x08 |
303 | #define VR_BCR0_RXTH_128BYTES 0x10 |
304 | #define VR_BCR0_RXTH_256BYTES 0x18 |
305 | #define VR_BCR0_RXTH_512BYTES 0x20 |
306 | #define VR_BCR0_RXTH_1024BYTES 0x28 |
307 | #define VR_BCR0_RXTH_STORENFWD 0x38 |
308 | |
309 | #define VR_BCR0_EXTLED 0x40 |
310 | #define VR_BCR0_MED2 0x80 |
311 | |
312 | /* |
313 | * BCR1 register bits. |
314 | */ |
315 | #define VR_BCR1_POT0 0x01 |
316 | #define VR_BCR1_POT1 0x02 |
317 | #define VR_BCR1_POT2 0x04 |
318 | |
319 | #define VR_BCR1_TX_THRESH 0x38 |
320 | #define VR_BCR1_TXTH_CFG 0x00 |
321 | #define VR_BCR1_TXTH_64BYTES 0x08 |
322 | #define VR_BCR1_TXTH_128BYTES 0x10 |
323 | #define VR_BCR1_TXTH_256BYTES 0x18 |
324 | #define VR_BCR1_TXTH_512BYTES 0x20 |
325 | #define VR_BCR1_TXTH_1024BYTES 0x28 |
326 | #define VR_BCR1_TXTH_STORENFWD 0x38 |
327 | |
328 | /* |
329 | * Rhine TX/RX list structure. |
330 | */ |
331 | |
332 | struct vr_desc { |
333 | volatile uint32_t vr_status; |
334 | volatile uint32_t vr_ctl; |
335 | volatile uint32_t vr_ptr1; |
336 | volatile uint32_t vr_ptr2; |
337 | }; |
338 | |
339 | #define vr_data vr_ptr1 |
340 | #define vr_next vr_ptr2 |
341 | |
342 | |
343 | #define VR_RXSTAT_RXERR 0x00000001 |
344 | #define VR_RXSTAT_CRCERR 0x00000002 |
345 | #define VR_RXSTAT_FRAMEALIGNERR 0x00000004 |
346 | #define VR_RXSTAT_FIFOOFLOW 0x00000008 |
347 | #define VR_RXSTAT_GIANT 0x00000010 |
348 | #define VR_RXSTAT_RUNT 0x00000020 |
349 | #define VR_RXSTAT_BUSERR 0x00000040 |
350 | #define VR_RXSTAT_BUFFERR 0x00000080 |
351 | #define VR_RXSTAT_LASTFRAG 0x00000100 |
352 | #define VR_RXSTAT_FIRSTFRAG 0x00000200 |
353 | #define VR_RXSTAT_RLINK 0x00000400 |
354 | #define VR_RXSTAT_RX_PHYS 0x00000800 |
355 | #define VR_RXSTAT_RX_BROAD 0x00001000 |
356 | #define VR_RXSTAT_RX_MULTI 0x00002000 |
357 | #define VR_RXSTAT_RX_OK 0x00004000 |
358 | #define VR_RXSTAT_RXLEN 0x07FF0000 |
359 | #define VR_RXSTAT_RXLEN_EXT 0x78000000 |
360 | #define VR_RXSTAT_OWN 0x80000000 |
361 | |
362 | #define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16) |
363 | |
364 | #define VR_RXCTL_BUFLEN 0x000007FF |
365 | #define VR_RXCTL_BUFLEN_EXT 0x00007800 |
366 | #define VR_RXCTL_CHAIN 0x00008000 |
367 | #define VR_RXCTL_RX_INTR 0x00800000 |
368 | |
369 | #define VR_TXSTAT_DEFER 0x00000001 |
370 | #define VR_TXSTAT_UNDERRUN 0x00000002 |
371 | #define VR_TXSTAT_COLLCNT 0x00000078 |
372 | #define VR_TXSTAT_SQE 0x00000080 |
373 | #define VR_TXSTAT_ABRT 0x00000100 |
374 | #define VR_TXSTAT_LATECOLL 0x00000200 |
375 | #define VR_TXSTAT_CARRLOST 0x00000400 |
376 | #define VR_TXSTAT_UDF 0x00000800 |
377 | #define VR_TXSTAT_BUSERR 0x00002000 |
378 | #define VR_TXSTAT_JABTIMEO 0x00004000 |
379 | #define VR_TXSTAT_ERRSUM 0x00008000 |
380 | #define VR_TXSTAT_OWN 0x80000000 |
381 | |
382 | #define VR_TXCTL_BUFLEN 0x000007FF |
383 | #define VR_TXCTL_BUFLEN_EXT 0x00007800 |
384 | #define VR_TXCTL_TLINK 0x00008000 |
385 | #define VR_TXCTL_FIRSTFRAG 0x00200000 |
386 | #define VR_TXCTL_LASTFRAG 0x00400000 |
387 | #define VR_TXCTL_FINT 0x00800000 |
388 | |
389 | |
390 | #define VR_MIN_FRAMELEN 60 |
391 | |
392 | /* |
393 | * VIA Rhine revision IDs |
394 | */ |
395 | |
396 | #define REV_ID_VT3043_E 0x04 |
397 | #define REV_ID_VT3071_A 0x20 |
398 | #define REV_ID_VT3071_B 0x21 |
399 | #define REV_ID_VT3065_A 0x40 |
400 | #define REV_ID_VT3065_B 0x41 |
401 | #define REV_ID_VT3065_C 0x42 |
402 | #define REV_ID_VT3106 0x80 |
403 | #define REV_ID_VT3106_J 0x80 /* 0x80-0x8F */ |
404 | #define REV_ID_VT3106_S 0x90 /* 0x90-0xA0 */ |
405 | |
406 | /* |
407 | * PCI low memory base and low I/O base register, and |
408 | * other PCI registers. |
409 | */ |
410 | |
411 | #define VR_PCI_LOIO 0x10 |
412 | #define VR_PCI_LOMEM 0x14 |
413 | #define VR_PCI_RESETOPT 0x48 |
414 | #define VR_PCI_EEPROM_DATA 0x4C |
415 | |