1 | /* |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
3 | * VA Linux Systems Inc., Fremont, California. |
4 | * Copyright 2008 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Original Authors: |
25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane |
26 | * |
27 | * Kernel port Author: Dave Airlie |
28 | */ |
29 | |
30 | #ifndef RADEON_MODE_H |
31 | #define RADEON_MODE_H |
32 | |
33 | #include <drm/drm_crtc.h> |
34 | #include <drm/drm_edid.h> |
35 | #include <drm/drm_dp_helper.h> |
36 | #include <drm/drm_fixed.h> |
37 | #include <drm/drm_crtc_helper.h> |
38 | #include <linux/i2c.h> |
39 | #include <linux/i2c-algo-bit.h> |
40 | |
41 | struct radeon_bo; |
42 | struct radeon_device; |
43 | |
44 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) |
45 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) |
46 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) |
47 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) |
48 | |
49 | enum radeon_rmx_type { |
50 | RMX_OFF, |
51 | RMX_FULL, |
52 | RMX_CENTER, |
53 | RMX_ASPECT |
54 | }; |
55 | |
56 | enum radeon_tv_std { |
57 | TV_STD_NTSC, |
58 | TV_STD_PAL, |
59 | TV_STD_PAL_M, |
60 | TV_STD_PAL_60, |
61 | TV_STD_NTSC_J, |
62 | TV_STD_SCART_PAL, |
63 | TV_STD_SECAM, |
64 | TV_STD_PAL_CN, |
65 | TV_STD_PAL_N, |
66 | }; |
67 | |
68 | enum radeon_underscan_type { |
69 | UNDERSCAN_OFF, |
70 | UNDERSCAN_ON, |
71 | UNDERSCAN_AUTO, |
72 | }; |
73 | |
74 | enum radeon_hpd_id { |
75 | RADEON_HPD_1 = 0, |
76 | RADEON_HPD_2, |
77 | RADEON_HPD_3, |
78 | RADEON_HPD_4, |
79 | RADEON_HPD_5, |
80 | RADEON_HPD_6, |
81 | RADEON_HPD_NONE = 0xff, |
82 | }; |
83 | |
84 | #define RADEON_MAX_I2C_BUS 16 |
85 | |
86 | /* radeon gpio-based i2c |
87 | * 1. "mask" reg and bits |
88 | * grabs the gpio pins for software use |
89 | * 0=not held 1=held |
90 | * 2. "a" reg and bits |
91 | * output pin value |
92 | * 0=low 1=high |
93 | * 3. "en" reg and bits |
94 | * sets the pin direction |
95 | * 0=input 1=output |
96 | * 4. "y" reg and bits |
97 | * input pin value |
98 | * 0=low 1=high |
99 | */ |
100 | struct radeon_i2c_bus_rec { |
101 | bool valid; |
102 | /* id used by atom */ |
103 | uint8_t i2c_id; |
104 | /* id used by atom */ |
105 | enum radeon_hpd_id hpd; |
106 | /* can be used with hw i2c engine */ |
107 | bool hw_capable; |
108 | /* uses multi-media i2c engine */ |
109 | bool mm_i2c; |
110 | /* regs and bits */ |
111 | uint32_t mask_clk_reg; |
112 | uint32_t mask_data_reg; |
113 | uint32_t a_clk_reg; |
114 | uint32_t a_data_reg; |
115 | uint32_t en_clk_reg; |
116 | uint32_t en_data_reg; |
117 | uint32_t y_clk_reg; |
118 | uint32_t y_data_reg; |
119 | uint32_t mask_clk_mask; |
120 | uint32_t mask_data_mask; |
121 | uint32_t a_clk_mask; |
122 | uint32_t a_data_mask; |
123 | uint32_t en_clk_mask; |
124 | uint32_t en_data_mask; |
125 | uint32_t y_clk_mask; |
126 | uint32_t y_data_mask; |
127 | }; |
128 | |
129 | struct radeon_tmds_pll { |
130 | uint32_t freq; |
131 | uint32_t value; |
132 | }; |
133 | |
134 | #define RADEON_MAX_BIOS_CONNECTOR 16 |
135 | |
136 | /* pll flags */ |
137 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
138 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) |
139 | #define RADEON_PLL_USE_REF_DIV (1 << 2) |
140 | #define RADEON_PLL_LEGACY (1 << 3) |
141 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) |
142 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) |
143 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) |
144 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) |
145 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) |
146 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
147 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
148 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
149 | #define RADEON_PLL_USE_POST_DIV (1 << 12) |
150 | #define RADEON_PLL_IS_LCD (1 << 13) |
151 | #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) |
152 | |
153 | struct radeon_pll { |
154 | /* reference frequency */ |
155 | uint32_t reference_freq; |
156 | |
157 | /* fixed dividers */ |
158 | uint32_t reference_div; |
159 | uint32_t post_div; |
160 | |
161 | /* pll in/out limits */ |
162 | uint32_t pll_in_min; |
163 | uint32_t pll_in_max; |
164 | uint32_t pll_out_min; |
165 | uint32_t pll_out_max; |
166 | uint32_t lcd_pll_out_min; |
167 | uint32_t lcd_pll_out_max; |
168 | uint32_t best_vco; |
169 | |
170 | /* divider limits */ |
171 | uint32_t min_ref_div; |
172 | uint32_t max_ref_div; |
173 | uint32_t min_post_div; |
174 | uint32_t max_post_div; |
175 | uint32_t min_feedback_div; |
176 | uint32_t max_feedback_div; |
177 | uint32_t min_frac_feedback_div; |
178 | uint32_t max_frac_feedback_div; |
179 | |
180 | /* flags for the current clock */ |
181 | uint32_t flags; |
182 | |
183 | /* pll id */ |
184 | uint32_t id; |
185 | }; |
186 | |
187 | struct radeon_i2c_chan { |
188 | struct i2c_adapter adapter; |
189 | struct drm_device *dev; |
190 | struct i2c_algo_bit_data bit; |
191 | struct radeon_i2c_bus_rec rec; |
192 | struct drm_dp_aux aux; |
193 | bool has_aux; |
194 | }; |
195 | |
196 | /* mostly for macs, but really any system without connector tables */ |
197 | enum radeon_connector_table { |
198 | CT_NONE = 0, |
199 | CT_GENERIC, |
200 | CT_IBOOK, |
201 | CT_POWERBOOK_EXTERNAL, |
202 | CT_POWERBOOK_INTERNAL, |
203 | CT_POWERBOOK_VGA, |
204 | CT_MINI_EXTERNAL, |
205 | CT_MINI_INTERNAL, |
206 | CT_IMAC_G5_ISIGHT, |
207 | CT_EMAC, |
208 | CT_RN50_POWER, |
209 | CT_MAC_X800, |
210 | CT_MAC_G5_9600, |
211 | CT_SAM440EP, |
212 | CT_MAC_G4_SILVER |
213 | }; |
214 | |
215 | enum radeon_dvo_chip { |
216 | DVO_SIL164, |
217 | DVO_SIL1178, |
218 | }; |
219 | |
220 | struct radeon_fbdev; |
221 | |
222 | struct radeon_afmt { |
223 | bool enabled; |
224 | int offset; |
225 | bool last_buffer_filled_status; |
226 | int id; |
227 | struct r600_audio_pin *pin; |
228 | }; |
229 | |
230 | struct radeon_mode_info { |
231 | struct atom_context *atom_context; |
232 | struct card_info *atom_card_info; |
233 | enum radeon_connector_table connector_table; |
234 | bool mode_config_initialized; |
235 | struct radeon_crtc *crtcs[6]; |
236 | struct radeon_afmt *afmt[7]; |
237 | /* DVI-I properties */ |
238 | struct drm_property *coherent_mode_property; |
239 | /* DAC enable load detect */ |
240 | struct drm_property *load_detect_property; |
241 | /* TV standard */ |
242 | struct drm_property *tv_std_property; |
243 | /* legacy TMDS PLL detect */ |
244 | struct drm_property *tmds_pll_property; |
245 | /* underscan */ |
246 | struct drm_property *underscan_property; |
247 | struct drm_property *underscan_hborder_property; |
248 | struct drm_property *underscan_vborder_property; |
249 | /* audio */ |
250 | struct drm_property *audio_property; |
251 | /* FMT dithering */ |
252 | struct drm_property *dither_property; |
253 | /* hardcoded DFP edid from BIOS */ |
254 | struct edid *bios_hardcoded_edid; |
255 | int bios_hardcoded_edid_size; |
256 | |
257 | /* pointer to fbdev info structure */ |
258 | struct radeon_fbdev *rfbdev; |
259 | /* firmware flags */ |
260 | u16 firmware_flags; |
261 | /* pointer to backlight encoder */ |
262 | struct radeon_encoder *bl_encoder; |
263 | }; |
264 | |
265 | #define RADEON_MAX_BL_LEVEL 0xFF |
266 | |
267 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
268 | |
269 | struct radeon_backlight_privdata { |
270 | struct radeon_encoder *encoder; |
271 | uint8_t negative; |
272 | }; |
273 | |
274 | #endif |
275 | |
276 | #define MAX_H_CODE_TIMING_LEN 32 |
277 | #define MAX_V_CODE_TIMING_LEN 32 |
278 | |
279 | /* need to store these as reading |
280 | back code tables is excessive */ |
281 | struct radeon_tv_regs { |
282 | uint32_t tv_uv_adr; |
283 | uint32_t timing_cntl; |
284 | uint32_t hrestart; |
285 | uint32_t vrestart; |
286 | uint32_t frestart; |
287 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; |
288 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; |
289 | }; |
290 | |
291 | struct radeon_atom_ss { |
292 | uint16_t percentage; |
293 | uint16_t percentage_divider; |
294 | uint8_t type; |
295 | uint16_t step; |
296 | uint8_t delay; |
297 | uint8_t range; |
298 | uint8_t refdiv; |
299 | /* asic_ss */ |
300 | uint16_t rate; |
301 | uint16_t amount; |
302 | }; |
303 | |
304 | struct radeon_crtc { |
305 | struct drm_crtc base; |
306 | int crtc_id; |
307 | u16 lut_r[256], lut_g[256], lut_b[256]; |
308 | bool enabled; |
309 | bool can_tile; |
310 | uint32_t crtc_offset; |
311 | struct drm_gem_object *cursor_bo; |
312 | uint64_t cursor_addr; |
313 | int cursor_width; |
314 | int cursor_height; |
315 | int max_cursor_width; |
316 | int max_cursor_height; |
317 | uint32_t legacy_display_base_addr; |
318 | uint32_t legacy_cursor_offset; |
319 | enum radeon_rmx_type rmx_type; |
320 | u8 h_border; |
321 | u8 v_border; |
322 | fixed20_12 vsc; |
323 | fixed20_12 hsc; |
324 | struct drm_display_mode native_mode; |
325 | int pll_id; |
326 | /* page flipping */ |
327 | struct radeon_unpin_work *unpin_work; |
328 | int deferred_flip_completion; |
329 | /* pll sharing */ |
330 | struct radeon_atom_ss ss; |
331 | bool ss_enabled; |
332 | u32 adjusted_clock; |
333 | int bpc; |
334 | u32 pll_reference_div; |
335 | u32 pll_post_div; |
336 | u32 pll_flags; |
337 | struct drm_encoder *encoder; |
338 | struct drm_connector *connector; |
339 | /* for dpm */ |
340 | u32 line_time; |
341 | u32 wm_low; |
342 | u32 wm_high; |
343 | struct drm_display_mode hw_mode; |
344 | }; |
345 | |
346 | struct radeon_encoder_primary_dac { |
347 | /* legacy primary dac */ |
348 | uint32_t ps2_pdac_adj; |
349 | }; |
350 | |
351 | struct radeon_encoder_lvds { |
352 | /* legacy lvds */ |
353 | uint16_t panel_vcc_delay; |
354 | uint8_t panel_pwr_delay; |
355 | uint8_t panel_digon_delay; |
356 | uint8_t panel_blon_delay; |
357 | uint16_t panel_ref_divider; |
358 | uint8_t panel_post_divider; |
359 | uint16_t panel_fb_divider; |
360 | bool use_bios_dividers; |
361 | uint32_t lvds_gen_cntl; |
362 | /* panel mode */ |
363 | struct drm_display_mode native_mode; |
364 | struct backlight_device *bl_dev; |
365 | int dpms_mode; |
366 | uint8_t backlight_level; |
367 | }; |
368 | |
369 | struct radeon_encoder_tv_dac { |
370 | /* legacy tv dac */ |
371 | uint32_t ps2_tvdac_adj; |
372 | uint32_t ntsc_tvdac_adj; |
373 | uint32_t pal_tvdac_adj; |
374 | |
375 | int h_pos; |
376 | int v_pos; |
377 | int h_size; |
378 | int supported_tv_stds; |
379 | bool tv_on; |
380 | enum radeon_tv_std tv_std; |
381 | struct radeon_tv_regs tv; |
382 | }; |
383 | |
384 | struct radeon_encoder_int_tmds { |
385 | /* legacy int tmds */ |
386 | struct radeon_tmds_pll tmds_pll[4]; |
387 | }; |
388 | |
389 | struct radeon_encoder_ext_tmds { |
390 | /* tmds over dvo */ |
391 | struct radeon_i2c_chan *i2c_bus; |
392 | uint8_t slave_addr; |
393 | enum radeon_dvo_chip dvo_chip; |
394 | }; |
395 | |
396 | /* spread spectrum */ |
397 | struct radeon_encoder_atom_dig { |
398 | bool linkb; |
399 | /* atom dig */ |
400 | bool coherent_mode; |
401 | int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ |
402 | /* atom lvds/edp */ |
403 | uint32_t lcd_misc; |
404 | uint16_t panel_pwr_delay; |
405 | uint32_t lcd_ss_id; |
406 | /* panel mode */ |
407 | struct drm_display_mode native_mode; |
408 | struct backlight_device *bl_dev; |
409 | int dpms_mode; |
410 | uint8_t backlight_level; |
411 | int panel_mode; |
412 | struct radeon_afmt *afmt; |
413 | }; |
414 | |
415 | struct radeon_encoder_atom_dac { |
416 | enum radeon_tv_std tv_std; |
417 | }; |
418 | |
419 | struct radeon_encoder { |
420 | struct drm_encoder base; |
421 | uint32_t encoder_enum; |
422 | uint32_t encoder_id; |
423 | uint32_t devices; |
424 | uint32_t active_device; |
425 | uint32_t flags; |
426 | uint32_t pixel_clock; |
427 | enum radeon_rmx_type rmx_type; |
428 | enum radeon_underscan_type underscan_type; |
429 | uint32_t underscan_hborder; |
430 | uint32_t underscan_vborder; |
431 | struct drm_display_mode native_mode; |
432 | void *enc_priv; |
433 | int audio_polling_active; |
434 | bool is_ext_encoder; |
435 | u16 caps; |
436 | }; |
437 | |
438 | struct radeon_connector_atom_dig { |
439 | uint32_t igp_lane_info; |
440 | /* displayport */ |
441 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
442 | u8 dp_sink_type; |
443 | int dp_clock; |
444 | int dp_lane_count; |
445 | bool edp_on; |
446 | }; |
447 | |
448 | struct radeon_gpio_rec { |
449 | bool valid; |
450 | u8 id; |
451 | u32 reg; |
452 | u32 mask; |
453 | }; |
454 | |
455 | struct radeon_hpd { |
456 | enum radeon_hpd_id hpd; |
457 | u8 plugged_state; |
458 | struct radeon_gpio_rec gpio; |
459 | }; |
460 | |
461 | struct radeon_router { |
462 | u32 router_id; |
463 | struct radeon_i2c_bus_rec i2c_info; |
464 | u8 i2c_addr; |
465 | /* i2c mux */ |
466 | bool ddc_valid; |
467 | u8 ddc_mux_type; |
468 | u8 ddc_mux_control_pin; |
469 | u8 ddc_mux_state; |
470 | /* clock/data mux */ |
471 | bool cd_valid; |
472 | u8 cd_mux_type; |
473 | u8 cd_mux_control_pin; |
474 | u8 cd_mux_state; |
475 | }; |
476 | |
477 | enum radeon_connector_audio { |
478 | RADEON_AUDIO_DISABLE = 0, |
479 | RADEON_AUDIO_ENABLE = 1, |
480 | RADEON_AUDIO_AUTO = 2 |
481 | }; |
482 | |
483 | enum radeon_connector_dither { |
484 | RADEON_FMT_DITHER_DISABLE = 0, |
485 | RADEON_FMT_DITHER_ENABLE = 1, |
486 | }; |
487 | |
488 | struct radeon_connector { |
489 | struct drm_connector base; |
490 | uint32_t connector_id; |
491 | uint32_t devices; |
492 | struct radeon_i2c_chan *ddc_bus; |
493 | /* some systems have an hdmi and vga port with a shared ddc line */ |
494 | bool shared_ddc; |
495 | bool use_digital; |
496 | /* we need to mind the EDID between detect |
497 | and get modes due to analog/digital/tvencoder */ |
498 | struct edid *edid; |
499 | void *con_priv; |
500 | bool dac_load_detect; |
501 | bool detected_by_load; /* if the connection status was determined by load */ |
502 | uint16_t connector_object_id; |
503 | struct radeon_hpd hpd; |
504 | struct radeon_router router; |
505 | struct radeon_i2c_chan *router_bus; |
506 | enum radeon_connector_audio audio; |
507 | enum radeon_connector_dither dither; |
508 | }; |
509 | |
510 | struct radeon_framebuffer { |
511 | struct drm_framebuffer base; |
512 | struct drm_gem_object *obj; |
513 | }; |
514 | |
515 | #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ |
516 | ((em) == ATOM_ENCODER_MODE_DP_MST)) |
517 | |
518 | struct atom_clock_dividers { |
519 | u32 post_div; |
520 | union { |
521 | struct { |
522 | #ifdef __BIG_ENDIAN |
523 | u32 reserved : 6; |
524 | u32 whole_fb_div : 12; |
525 | u32 frac_fb_div : 14; |
526 | #else |
527 | u32 frac_fb_div : 14; |
528 | u32 whole_fb_div : 12; |
529 | u32 reserved : 6; |
530 | #endif |
531 | }; |
532 | u32 fb_div; |
533 | }; |
534 | u32 ref_div; |
535 | bool enable_post_div; |
536 | bool enable_dithen; |
537 | u32 vco_mode; |
538 | u32 real_clock; |
539 | /* added for CI */ |
540 | u32 post_divider; |
541 | u32 flags; |
542 | }; |
543 | |
544 | struct atom_mpll_param { |
545 | union { |
546 | struct { |
547 | #ifdef __BIG_ENDIAN |
548 | u32 reserved : 8; |
549 | u32 clkfrac : 12; |
550 | u32 clkf : 12; |
551 | #else |
552 | u32 clkf : 12; |
553 | u32 clkfrac : 12; |
554 | u32 reserved : 8; |
555 | #endif |
556 | }; |
557 | u32 fb_div; |
558 | }; |
559 | u32 post_div; |
560 | u32 bwcntl; |
561 | u32 dll_speed; |
562 | u32 vco_mode; |
563 | u32 yclk_sel; |
564 | u32 qdr; |
565 | u32 half_rate; |
566 | }; |
567 | |
568 | #define MEM_TYPE_GDDR5 0x50 |
569 | #define MEM_TYPE_GDDR4 0x40 |
570 | #define MEM_TYPE_GDDR3 0x30 |
571 | #define MEM_TYPE_DDR2 0x20 |
572 | #define MEM_TYPE_GDDR1 0x10 |
573 | #define MEM_TYPE_DDR3 0xb0 |
574 | #define MEM_TYPE_MASK 0xf0 |
575 | |
576 | struct atom_memory_info { |
577 | u8 mem_vendor; |
578 | u8 mem_type; |
579 | }; |
580 | |
581 | #define MAX_AC_TIMING_ENTRIES 16 |
582 | |
583 | struct atom_memory_clock_range_table |
584 | { |
585 | u8 num_entries; |
586 | u8 rsv[3]; |
587 | u32 mclk[MAX_AC_TIMING_ENTRIES]; |
588 | }; |
589 | |
590 | #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 |
591 | #define VBIOS_MAX_AC_TIMING_ENTRIES 20 |
592 | |
593 | struct atom_mc_reg_entry { |
594 | u32 mclk_max; |
595 | u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; |
596 | }; |
597 | |
598 | struct atom_mc_register_address { |
599 | u16 s1; |
600 | u8 pre_reg_data; |
601 | }; |
602 | |
603 | struct atom_mc_reg_table { |
604 | u8 last; |
605 | u8 num_entries; |
606 | struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; |
607 | struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; |
608 | }; |
609 | |
610 | #define MAX_VOLTAGE_ENTRIES 32 |
611 | |
612 | struct atom_voltage_table_entry |
613 | { |
614 | u16 value; |
615 | u32 smio_low; |
616 | }; |
617 | |
618 | struct atom_voltage_table |
619 | { |
620 | u32 count; |
621 | u32 mask_low; |
622 | u32 phase_delay; |
623 | struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; |
624 | }; |
625 | |
626 | |
627 | extern void |
628 | radeon_add_atom_connector(struct drm_device *dev, |
629 | uint32_t connector_id, |
630 | uint32_t supported_device, |
631 | int connector_type, |
632 | struct radeon_i2c_bus_rec *i2c_bus, |
633 | uint32_t igp_lane_info, |
634 | uint16_t connector_object_id, |
635 | struct radeon_hpd *hpd, |
636 | struct radeon_router *router); |
637 | extern void |
638 | radeon_add_legacy_connector(struct drm_device *dev, |
639 | uint32_t connector_id, |
640 | uint32_t supported_device, |
641 | int connector_type, |
642 | struct radeon_i2c_bus_rec *i2c_bus, |
643 | uint16_t connector_object_id, |
644 | struct radeon_hpd *hpd); |
645 | extern uint32_t |
646 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, |
647 | uint8_t dac); |
648 | extern void radeon_link_encoder_connector(struct drm_device *dev); |
649 | |
650 | extern enum radeon_tv_std |
651 | radeon_combios_get_tv_info(struct radeon_device *rdev); |
652 | extern enum radeon_tv_std |
653 | radeon_atombios_get_tv_info(struct radeon_device *rdev); |
654 | extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, |
655 | u16 *vddc, u16 *vddci, u16 *mvdd); |
656 | |
657 | extern void |
658 | radeon_combios_connected_scratch_regs(struct drm_connector *connector, |
659 | struct drm_encoder *encoder, |
660 | bool connected); |
661 | extern void |
662 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, |
663 | struct drm_encoder *encoder, |
664 | bool connected); |
665 | |
666 | extern struct drm_connector * |
667 | radeon_get_connector_for_encoder(struct drm_encoder *encoder); |
668 | extern struct drm_connector * |
669 | radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); |
670 | extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, |
671 | u32 pixel_clock); |
672 | |
673 | extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); |
674 | extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); |
675 | extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); |
676 | extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); |
677 | extern int radeon_get_monitor_bpc(struct drm_connector *connector); |
678 | |
679 | extern void radeon_connector_hotplug(struct drm_connector *connector); |
680 | extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
681 | struct drm_display_mode *mode); |
682 | extern void radeon_dp_set_link_config(struct drm_connector *connector, |
683 | const struct drm_display_mode *mode); |
684 | extern void radeon_dp_link_train(struct drm_encoder *encoder, |
685 | struct drm_connector *connector); |
686 | extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); |
687 | extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); |
688 | extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); |
689 | extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
690 | struct drm_connector *connector); |
691 | extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, |
692 | u8 power_state); |
693 | extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); |
694 | extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); |
695 | extern void radeon_atom_encoder_init(struct radeon_device *rdev); |
696 | extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); |
697 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, |
698 | int action, uint8_t lane_num, |
699 | uint8_t lane_set); |
700 | extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); |
701 | extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); |
702 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); |
703 | |
704 | extern void radeon_i2c_init(struct radeon_device *rdev); |
705 | extern void radeon_i2c_fini(struct radeon_device *rdev); |
706 | extern void radeon_combios_i2c_init(struct radeon_device *rdev); |
707 | extern void radeon_atombios_i2c_init(struct radeon_device *rdev); |
708 | extern void radeon_i2c_add(struct radeon_device *rdev, |
709 | struct radeon_i2c_bus_rec *rec, |
710 | const char *name); |
711 | extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, |
712 | struct radeon_i2c_bus_rec *i2c_bus); |
713 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
714 | struct radeon_i2c_bus_rec *rec, |
715 | const char *name); |
716 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); |
717 | extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
718 | u8 slave_addr, |
719 | u8 addr, |
720 | u8 *val); |
721 | extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, |
722 | u8 slave_addr, |
723 | u8 addr, |
724 | u8 val); |
725 | extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); |
726 | extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); |
727 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); |
728 | extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); |
729 | |
730 | extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); |
731 | |
732 | extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, |
733 | struct radeon_atom_ss *ss, |
734 | int id); |
735 | extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, |
736 | struct radeon_atom_ss *ss, |
737 | int id, u32 clock); |
738 | |
739 | extern void radeon_compute_pll_legacy(struct radeon_pll *pll, |
740 | uint64_t freq, |
741 | uint32_t *dot_clock_p, |
742 | uint32_t *fb_div_p, |
743 | uint32_t *frac_fb_div_p, |
744 | uint32_t *ref_div_p, |
745 | uint32_t *post_div_p); |
746 | |
747 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, |
748 | u32 freq, |
749 | u32 *dot_clock_p, |
750 | u32 *fb_div_p, |
751 | u32 *frac_fb_div_p, |
752 | u32 *ref_div_p, |
753 | u32 *post_div_p); |
754 | |
755 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
756 | |
757 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
758 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
759 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
760 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); |
761 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); |
762 | extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); |
763 | extern void atombios_digital_setup(struct drm_encoder *encoder, int action); |
764 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
765 | extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); |
766 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
767 | |
768 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); |
769 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
770 | struct drm_framebuffer *old_fb); |
771 | extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
772 | struct drm_framebuffer *fb, |
773 | int x, int y, |
774 | enum mode_set_atomic state); |
775 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
776 | struct drm_display_mode *mode, |
777 | struct drm_display_mode *adjusted_mode, |
778 | int x, int y, |
779 | struct drm_framebuffer *old_fb); |
780 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); |
781 | |
782 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
783 | struct drm_framebuffer *old_fb); |
784 | extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, |
785 | struct drm_framebuffer *fb, |
786 | int x, int y, |
787 | enum mode_set_atomic state); |
788 | extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, |
789 | struct drm_framebuffer *fb, |
790 | int x, int y, int atomic); |
791 | extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, |
792 | struct drm_file *file_priv, |
793 | uint32_t handle, |
794 | uint32_t width, |
795 | uint32_t height); |
796 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
797 | int x, int y); |
798 | |
799 | extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, |
800 | unsigned int flags, |
801 | int *vpos, int *hpos, ktime_t *stime, |
802 | ktime_t *etime); |
803 | |
804 | extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); |
805 | extern struct edid * |
806 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); |
807 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
808 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); |
809 | extern struct radeon_encoder_atom_dig * |
810 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); |
811 | extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
812 | struct radeon_encoder_int_tmds *tmds); |
813 | extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
814 | struct radeon_encoder_int_tmds *tmds); |
815 | extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
816 | struct radeon_encoder_int_tmds *tmds); |
817 | extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, |
818 | struct radeon_encoder_ext_tmds *tmds); |
819 | extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, |
820 | struct radeon_encoder_ext_tmds *tmds); |
821 | extern struct radeon_encoder_primary_dac * |
822 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); |
823 | extern struct radeon_encoder_tv_dac * |
824 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); |
825 | extern struct radeon_encoder_lvds * |
826 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); |
827 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
828 | extern struct radeon_encoder_tv_dac * |
829 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); |
830 | extern struct radeon_encoder_primary_dac * |
831 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); |
832 | extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); |
833 | extern void radeon_external_tmds_setup(struct drm_encoder *encoder); |
834 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
835 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); |
836 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); |
837 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); |
838 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
839 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); |
840 | extern void |
841 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
842 | extern void |
843 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
844 | extern void |
845 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
846 | extern void |
847 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
848 | extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
849 | u16 blue, int regno); |
850 | extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
851 | u16 *blue, int regno); |
852 | int radeon_framebuffer_init(struct drm_device *dev, |
853 | struct radeon_framebuffer *rfb, |
854 | struct drm_mode_fb_cmd2 *mode_cmd, |
855 | struct drm_gem_object *obj); |
856 | |
857 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
858 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); |
859 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); |
860 | void radeon_atombios_init_crtc(struct drm_device *dev, |
861 | struct radeon_crtc *radeon_crtc); |
862 | void radeon_legacy_init_crtc(struct drm_device *dev, |
863 | struct radeon_crtc *radeon_crtc); |
864 | |
865 | void radeon_get_clock_info(struct drm_device *dev); |
866 | |
867 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); |
868 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); |
869 | |
870 | void radeon_enc_destroy(struct drm_encoder *encoder); |
871 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
872 | void radeon_combios_asic_init(struct drm_device *dev); |
873 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
874 | const struct drm_display_mode *mode, |
875 | struct drm_display_mode *adjusted_mode); |
876 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
877 | struct drm_display_mode *adjusted_mode); |
878 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
879 | |
880 | /* legacy tv */ |
881 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, |
882 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, |
883 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); |
884 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, |
885 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, |
886 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); |
887 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, |
888 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, |
889 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); |
890 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, |
891 | struct drm_display_mode *mode, |
892 | struct drm_display_mode *adjusted_mode); |
893 | |
894 | /* fmt blocks */ |
895 | void avivo_program_fmt(struct drm_encoder *encoder); |
896 | void dce3_program_fmt(struct drm_encoder *encoder); |
897 | void dce4_program_fmt(struct drm_encoder *encoder); |
898 | void dce8_program_fmt(struct drm_encoder *encoder); |
899 | |
900 | /* fbdev layer */ |
901 | int radeon_fbdev_init(struct radeon_device *rdev); |
902 | void radeon_fbdev_fini(struct radeon_device *rdev); |
903 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); |
904 | int radeon_fbdev_total_size(struct radeon_device *rdev); |
905 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); |
906 | |
907 | void radeon_fb_output_poll_changed(struct radeon_device *rdev); |
908 | |
909 | void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); |
910 | |
911 | int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); |
912 | |
913 | #ifdef __NetBSD__ |
914 | struct drm_fb_helper; |
915 | struct drm_fb_helper_surface_size; |
916 | int radeon_genfb_attach(struct drm_device *, struct drm_fb_helper *, |
917 | const struct drm_fb_helper_surface_size *, struct radeon_bo *); |
918 | #endif |
919 | |
920 | #endif |
921 | |