1 | /* $NetBSD: nouveau_engine_device_nv50.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_device_nv50.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $" ); |
29 | |
30 | #include <subdev/bios.h> |
31 | #include <subdev/bus.h> |
32 | #include <subdev/gpio.h> |
33 | #include <subdev/i2c.h> |
34 | #include <subdev/clock.h> |
35 | #include <subdev/therm.h> |
36 | #include <subdev/mxm.h> |
37 | #include <subdev/devinit.h> |
38 | #include <subdev/mc.h> |
39 | #include <subdev/timer.h> |
40 | #include <subdev/fb.h> |
41 | #include <subdev/instmem.h> |
42 | #include <subdev/vm.h> |
43 | #include <subdev/bar.h> |
44 | #include <subdev/pwr.h> |
45 | #include <subdev/volt.h> |
46 | |
47 | #include <engine/device.h> |
48 | #include <engine/dmaobj.h> |
49 | #include <engine/fifo.h> |
50 | #include <engine/software.h> |
51 | #include <engine/graph.h> |
52 | #include <engine/mpeg.h> |
53 | #include <engine/vp.h> |
54 | #include <engine/crypt.h> |
55 | #include <engine/bsp.h> |
56 | #include <engine/ppp.h> |
57 | #include <engine/copy.h> |
58 | #include <engine/disp.h> |
59 | #include <engine/perfmon.h> |
60 | |
61 | int |
62 | nv50_identify(struct nouveau_device *device) |
63 | { |
64 | switch (device->chipset) { |
65 | case 0x50: |
66 | device->cname = "G80" ; |
67 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
68 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
69 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass; |
70 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass; |
71 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; |
72 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
73 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass; |
74 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; |
75 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
76 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
77 | device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; |
78 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
79 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
80 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
81 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
82 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; |
83 | device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; |
84 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
85 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
86 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; |
87 | device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass; |
88 | device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass; |
89 | break; |
90 | case 0x84: |
91 | device->cname = "G84" ; |
92 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
93 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
94 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass; |
95 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
96 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
97 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
98 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
99 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; |
100 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
101 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
102 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
103 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
104 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
105 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
106 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
107 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; |
108 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
109 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
110 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
111 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; |
112 | device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; |
113 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; |
114 | device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; |
115 | device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; |
116 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
117 | break; |
118 | case 0x86: |
119 | device->cname = "G86" ; |
120 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
121 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
122 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass; |
123 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
124 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
125 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
126 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
127 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; |
128 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
129 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
130 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
131 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
132 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
133 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
134 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
135 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; |
136 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
137 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
138 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
139 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; |
140 | device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; |
141 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; |
142 | device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; |
143 | device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; |
144 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
145 | break; |
146 | case 0x92: |
147 | device->cname = "G92" ; |
148 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
149 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
150 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass; |
151 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
152 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
153 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
154 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
155 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; |
156 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
157 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
158 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
159 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
160 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
161 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
162 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
163 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; |
164 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
165 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
166 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
167 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; |
168 | device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; |
169 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; |
170 | device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; |
171 | device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; |
172 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
173 | break; |
174 | case 0x94: |
175 | device->cname = "G94" ; |
176 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
177 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
178 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass; |
179 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
180 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
181 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
182 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
183 | device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; |
184 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
185 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
186 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
187 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
188 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
189 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
190 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
191 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; |
192 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
193 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
194 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
195 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; |
196 | device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; |
197 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; |
198 | device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; |
199 | device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; |
200 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
201 | break; |
202 | case 0x96: |
203 | device->cname = "G96" ; |
204 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
205 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
206 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass; |
207 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
208 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
209 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
210 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
211 | device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; |
212 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
213 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
214 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
215 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
216 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
217 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
218 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
219 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; |
220 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
221 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
222 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
223 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; |
224 | device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; |
225 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; |
226 | device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; |
227 | device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; |
228 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
229 | break; |
230 | case 0x98: |
231 | device->cname = "G98" ; |
232 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
233 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
234 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass; |
235 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
236 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
237 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
238 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; |
239 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
240 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
241 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
242 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
243 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
244 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
245 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
246 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
247 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; |
248 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
249 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
250 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
251 | device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; |
252 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; |
253 | device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; |
254 | device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; |
255 | device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; |
256 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
257 | break; |
258 | case 0xa0: |
259 | device->cname = "G200" ; |
260 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
261 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
262 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass; |
263 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
264 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
265 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
266 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
267 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
268 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
269 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
270 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
271 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
272 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
273 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
274 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
275 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; |
276 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
277 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
278 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
279 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; |
280 | device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; |
281 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; |
282 | device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; |
283 | device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass; |
284 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
285 | break; |
286 | case 0xaa: |
287 | device->cname = "MCP77/MCP78" ; |
288 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
289 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
290 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass; |
291 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; |
292 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
293 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
294 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; |
295 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
296 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
297 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
298 | device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; |
299 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
300 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
301 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
302 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
303 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; |
304 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
305 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
306 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
307 | device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; |
308 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; |
309 | device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; |
310 | device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; |
311 | device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; |
312 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
313 | break; |
314 | case 0xac: |
315 | device->cname = "MCP79/MCP7A" ; |
316 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
317 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
318 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass; |
319 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; |
320 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
321 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
322 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; |
323 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
324 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
325 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
326 | device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; |
327 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
328 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
329 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
330 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
331 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; |
332 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
333 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
334 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
335 | device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; |
336 | device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; |
337 | device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; |
338 | device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; |
339 | device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; |
340 | device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; |
341 | break; |
342 | case 0xa3: |
343 | device->cname = "GT215" ; |
344 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
345 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
346 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass; |
347 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; |
348 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
349 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
350 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; |
351 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
352 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
353 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
354 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; |
355 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
356 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
357 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
358 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; |
359 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
360 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; |
361 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
362 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
363 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
364 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; |
365 | device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; |
366 | device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; |
367 | device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; |
368 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; |
369 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
370 | device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; |
371 | break; |
372 | case 0xa5: |
373 | device->cname = "GT216" ; |
374 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
375 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
376 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass; |
377 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; |
378 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
379 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
380 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; |
381 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
382 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
383 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
384 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; |
385 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
386 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
387 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
388 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; |
389 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
390 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; |
391 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
392 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
393 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
394 | device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; |
395 | device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; |
396 | device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; |
397 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; |
398 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
399 | device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; |
400 | break; |
401 | case 0xa8: |
402 | device->cname = "GT218" ; |
403 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
404 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
405 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass; |
406 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; |
407 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
408 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
409 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; |
410 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
411 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
412 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
413 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; |
414 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
415 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
416 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
417 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; |
418 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
419 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; |
420 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
421 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
422 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
423 | device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; |
424 | device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; |
425 | device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; |
426 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; |
427 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
428 | device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; |
429 | break; |
430 | case 0xaf: |
431 | device->cname = "MCP89" ; |
432 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
433 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
434 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass; |
435 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; |
436 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
437 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
438 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass; |
439 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
440 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
441 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
442 | device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass; |
443 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
444 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
445 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
446 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; |
447 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
448 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; |
449 | device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; |
450 | device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; |
451 | device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; |
452 | device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; |
453 | device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; |
454 | device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; |
455 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; |
456 | device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; |
457 | device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; |
458 | break; |
459 | default: |
460 | nv_fatal(device, "unknown Tesla chipset\n" ); |
461 | return -EINVAL; |
462 | } |
463 | |
464 | return 0; |
465 | } |
466 | |