1 | /* $NetBSD: siisatareg.h,v 1.7 2011/11/02 16:03:01 jakllsch Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 2007, 2008, 2009, 2010, 2011 Jonathan A. Kollasch. |
5 | * All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * |
16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * |
27 | */ |
28 | |
29 | #ifndef _IC_SIISATAREG_H_ |
30 | #define _IC_SIISATAREG_H_ |
31 | |
32 | /* Silicon Image SATA 2 controller register defines */ |
33 | |
34 | #include <sys/cdefs.h> |
35 | |
36 | /* the SiI3124 has 4 ports, all others so far have less */ |
37 | #define SIISATA_MAX_PORTS 4 |
38 | /* all parts have a full complement of slots (so far) */ |
39 | #define SIISATA_MAX_SLOTS 31 |
40 | |
41 | /* structures */ |
42 | |
43 | /* Scatter/Gather Entry */ |
44 | struct siisata_sge { |
45 | #if 0 |
46 | uint32_t sge_dal; /* data address low */ |
47 | uint32_t sge_dah; /* " " high */ |
48 | #else |
49 | uint64_t sge_da; |
50 | #endif |
51 | uint32_t sge_dc; /* data count (bytes) */ |
52 | uint32_t sge_flags; /* */ |
53 | #define SGE_FLAG_TRM __BIT(31) |
54 | #define SGE_FLAG_LNK __BIT(30) |
55 | #define SGE_FLAG_DRD __BIT(29) |
56 | #define SGE_FLAG_XCF __BIT(28) |
57 | } __packed __aligned(8); |
58 | |
59 | /* Scatter/Gather Table */ |
60 | /* must be aligned to 64-bit boundary */ |
61 | struct siisata_sgt { |
62 | struct siisata_sge sgt_sge[4]; |
63 | } __packed __aligned(8); |
64 | |
65 | /* Port Request Block */ |
66 | struct siisata_prb { |
67 | uint16_t prb_control; /* Control Field */ |
68 | #define PRB_CF_PROTOCOL_OVERRIDE __BIT(0) |
69 | #define PRB_CF_RETRANSMIT __BIT(1) |
70 | #define PRB_CF_EXTERNAL_COMMAND __BIT(2) |
71 | #define PRB_CF_RECEIVE __BIT(3) |
72 | #define PRB_CF_PACKET_READ __BIT(4) |
73 | #define PRB_CF_PACKET_WRITE __BIT(5) |
74 | #define PRB_CF_INTERRUPT_MASK __BIT(6) |
75 | #define PRB_CF_SOFT_RESET __BIT(7) |
76 | uint16_t prb_protocol_override; |
77 | #define PRB_PO_PACKET __BIT(0) |
78 | #define PRB_PO_LCQ __BIT(1) |
79 | #define PRB_PO_NCQ __BIT(2) |
80 | #define PRB_PO_READ __BIT(3) |
81 | #define PRB_PO_WRITE __BIT(4) |
82 | #define PRB_PO_TRANSPARENT __BIT(5) |
83 | uint32_t prb_transfer_count; |
84 | uint8_t prb_fis[20]; |
85 | uint32_t prb_reserved_0x1C; /* "must be zero" */ |
86 | /* First SGE in PRB is always reserved for ATAPI in this implementation. */ |
87 | uint8_t prb_atapi[16]; /* zero for non-ATAPI */ |
88 | struct siisata_sge prb_sge[1]; /* extended to NSGE */ |
89 | } __packed __aligned(8); |
90 | |
91 | |
92 | #define SIISATA_NSGE ((MAXPHYS/PAGE_SIZE) + 1) |
93 | #define SIISATA_CMD_ALIGN 0x7f |
94 | #define SIISATA_CMD_SIZE \ |
95 | ( ( sizeof(struct siisata_prb) + (SIISATA_NSGE - 1) * sizeof(struct siisata_sge) + SIISATA_CMD_ALIGN ) & ~SIISATA_CMD_ALIGN ) |
96 | |
97 | /* PCI stuff */ |
98 | #define SIISATA_PCI_BAR0 0x10 |
99 | #define SIISATA_PCI_BAR1 0x18 |
100 | #define SIISATA_PCI_BAR2 0x20 |
101 | |
102 | /* Cardbus stuff */ |
103 | #define SIISATA_CARDBUS_BAR0 SIISATA_PCI_BAR0 |
104 | #define SIISATA_CARDBUS_BAR1 SIISATA_PCI_BAR1 |
105 | #define SIISATA_CARDBUS_BAR2 SIISATA_PCI_BAR2 |
106 | |
107 | /* BAR 0 */ |
108 | |
109 | /* port n slot status */ |
110 | #define GR_PXSS(n) (n*4) |
111 | /* global control */ |
112 | #define GR_GC 0x40 |
113 | /* global interrupt status */ |
114 | #define GR_GIS 0x44 |
115 | /* phy config - don't touch */ |
116 | #define GR_PHYC 0x48 |
117 | /* BIST */ |
118 | #define GR_BIST_CONTROL 0x50 |
119 | #define GR_BIST_PATTERN 0x54 |
120 | #define GR_BIST_STATUS 0x58 |
121 | /* I2C SiI3132 */ |
122 | #define GR_SII3132_IICCONTROL 0x60 |
123 | #define GR_SII3132_IICSTATUS 0x64 |
124 | #define GR_SII3132_IICSLAVEADDR 0x68 |
125 | #define GR_SII3132_IICDATA 0x6c |
126 | /* Flash */ |
127 | #define GR_FLSHADDR 0x70 |
128 | #define GR_FLSHDATA 0x74 |
129 | /* I2C SiI3124 */ |
130 | #define GR_SII3124_IICADDR 0x78 |
131 | #define GR_SII3124_IICDATA 0x7c |
132 | |
133 | |
134 | /* GR_GC bits */ |
135 | #define GR_GC_GLBLRST __BIT(31) |
136 | #define GR_GC_MSIACK __BIT(30) |
137 | #define GR_GC_I2CINTEN __BIT(29) |
138 | #define GR_GC_PERRRPTDSBL __BIT(28) |
139 | #define GR_GC_3GBPS __BIT(24) |
140 | #define GR_GC_REQ64 __BIT(20) |
141 | #define GR_GC_DEVSEL __BIT(19) |
142 | #define GR_GC_STOP __BIT(18) |
143 | #define GR_GC_TRDY __BIT(17) |
144 | #define GR_GC_M66EN __BIT(16) |
145 | #define GR_GC_PXIE_MASK __BITS(SIISATA_MAX_PORTS - 1, 0) |
146 | #define GR_GC_PXIE(n) __SHIFTIN(__BIT(n), GR_GC_PXIE_MASK) |
147 | |
148 | /* GR_GIS bits */ |
149 | #define GR_GIS_I2C __BIT(29) |
150 | #define GR_GIS_PXIS_MASK __BITS(SIISATA_MAX_PORTS - 1, 0) |
151 | #define GR_GIS_PXIS(n) __SHIFTIN(__BIT(n), GR_GIS_PXIS_MASK) |
152 | |
153 | |
154 | /* BAR 1 */ |
155 | |
156 | /* hmm, this could use a better name */ |
157 | #define PR_PORT_SIZE 0x2000 |
158 | #define PR_SLOT_SIZE 0x80 |
159 | /* get the register by port number and offset */ |
160 | #define PRO(p) (PR_PORT_SIZE * p) |
161 | #define PRX(p,r) (PRO(p) + r) |
162 | #define PRSX(p,s,o) (PRX(p, PR_SLOT_SIZE * s + o)) |
163 | |
164 | #define PRSO_RTC 0x04 /* recieved transfer count */ |
165 | #define PRSO_FIS 0x08 /* base of FIS */ |
166 | |
167 | #define PRO_PCS 0x1000 /* (write) port control set */ |
168 | #define PRO_PS PRO_PCS /* (read) port status */ |
169 | #define PRO_PCC 0x1004 /* port control clear */ |
170 | #define PRO_PIS 0x1008 /* port interrupt status */ |
171 | #define PRO_PIES 0x1010 /* port interrupt enable set */ |
172 | #define PRO_PIEC 0x1014 /* port interrupt enable clear */ |
173 | #define PRO_32BAUA 0x101c /* 32-bit activation upper address */ |
174 | #define PRO_PCEF 0x1020 /* port command execution fifo */ |
175 | #define PRO_PCE 0x1024 /* port command error */ |
176 | #define PRO_PFISC 0x1028 /* port FIS config */ |
177 | #define PRO_PCIRFIFOT 0x102c /* pci request fifo threshhold */ |
178 | #define PRO_P8B10BDEC 0x1040 /* port 8B/10B decode error counter */ |
179 | #define PRO_PCRCEC 0x1044 /* port crc error count */ |
180 | #define PRO_PHEC 0x1048 /* port handshake error count */ |
181 | #define PRO_PPHYC 0x1050 /* phy config */ |
182 | #define PRO_PSS 0x1800 /* port slot status */ |
183 | /* technically this is a shadow of the CAR */ |
184 | #define PRO_CAR 0x1c00 |
185 | |
186 | #define PRO_CARX(p,s) (PRX(p, PRO_CAR) + s * sizeof(uint64_t)) |
187 | |
188 | #define PRO_PCR 0x1e04 /* port context register */ |
189 | #define PRO_SCONTROL 0x1f00 /* SControl */ |
190 | #define PRO_SSTATUS 0x1f04 /* SStatus */ |
191 | #define PRO_SERROR 0x1f08 /* SError */ |
192 | #define PRO_SACTIVE 0x1f0c /* SActive */ |
193 | |
194 | |
195 | /* Port Command Error */ |
196 | #define PR_PCE_DEVICEERROR 1 |
197 | #define PR_PCE_SDBERROR 2 |
198 | #define PR_PCE_DATAFISERROR 3 |
199 | #define PR_PCE_SENDFISERROR 4 |
200 | #define PR_PCE_INCONSISTENTSTATE 5 |
201 | #define PR_PCE_DIRECTIONERROR 6 |
202 | #define PR_PCE_UNDERRUNERROR 7 |
203 | #define PR_PCE_OVERRUNERROR 8 |
204 | #define PR_PCE_LINKFIFOOVERRUN 9 |
205 | #define PR_PCE_PACKETPROTOCOLERROR 11 |
206 | #define PR_PCE_PLDSGTERRORBOUNDARY 16 |
207 | #define PR_PCE_PLDSGTERRORTARGETABORT 17 |
208 | #define PR_PCE_PLDSGTERRORMASTERABORT 18 |
209 | #define PR_PCE_PLDSGTERRORPCIPERR 19 |
210 | #define PR_PCE_PLDCMDERRORBOUNDARY 24 |
211 | #define PR_PCE_PLDCMDERRORTARGETABORT 25 |
212 | #define PR_PCE_PLDCMDERRORMASTERABORT 26 |
213 | #define PR_PCE_PLDCMDERRORPCIPERR 27 |
214 | #define PR_PCE_PSDERRORTARGETABORT 33 |
215 | #define PR_PCE_PSDERRORMASTERABORT 34 |
216 | #define PR_PCE_PSDERRORPCIPERR 35 |
217 | #define PR_PCE_SENDSERVICEERROROR 36 |
218 | |
219 | |
220 | #define PR_PIS_UNMASKED_SHIFT 16 |
221 | #define PR_PIS_CMDCMPL __BIT(0) /* command completion */ |
222 | #define PR_PIS_CMDERRR __BIT(1) /* command error */ |
223 | #define PR_PIS_PRTRDY __BIT(2) /* port ready */ |
224 | #define PR_PIS_PMCHNG __BIT(3) /* power management state change */ |
225 | #define PR_PIS_PHYRDYCHG __BIT(4) |
226 | #define PR_PIS_COMWAKE __BIT(5) |
227 | #define PR_PIS_UNRECFIS __BIT(6) |
228 | #define PR_PIS_DEVEXCHG __BIT(7) |
229 | #define PR_PIS_8B10BDET __BIT(8) |
230 | #define PR_PIS_CRCET __BIT(9) |
231 | #define PR_PIS_HET __BIT(10) |
232 | #define PR_PIS_SDBN __BIT(11) |
233 | |
234 | #define PR_PC_PORT_RESET __BIT(0) |
235 | #define PR_PC_DEVICE_RESET __BIT(1) |
236 | #define PR_PC_PORT_INITIALIZE __BIT(2) |
237 | #define PR_PC_INCOR __BIT(3) |
238 | #define PR_PC_LED_DISABLE __BIT(4) |
239 | #define PR_PC_PACKET_LENGTH __BIT(5) |
240 | #define PR_PC_RESUME __BIT(6) |
241 | #define PR_PC_TXBIST __BIT(7) |
242 | #define PR_PC_CONT_DISABLE __BIT(8) |
243 | #define PR_PC_SCRAMBLER_DISABLE __BIT(9) |
244 | #define PR_PC_32BA __BIT(10) |
245 | #define PR_PC_INTERLOCK_REJECT __BIT(11) |
246 | #define PR_PC_INTERLOCK_ACCEPT __BIT(12) |
247 | #define PR_PC_PMP_ENABLE __BIT(13) |
248 | #define PR_PC_AIA __BIT(14) |
249 | #define PR_PC_LED_ON __BIT(15) |
250 | #define PR_PC_OOB_BYPASS __BIT(25) |
251 | #define PR_PS_PORT_READY __BIT(31) |
252 | |
253 | #define PR_PSS_ATTENTION __BIT(31) |
254 | #define PR_PSS_SLOT_MASK __BITS(30, 0) |
255 | #define PR_PXSS(n) __SHIFTIN(__BIT(n), PR_PSS_SLOT_MASK) |
256 | |
257 | #endif /* !_IC_SIISATAREG_H_ */ |
258 | |