1 | /* $NetBSD: if_dge.c,v 1.45 2016/07/07 06:55:41 msaitoh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 2004, SUNET, Swedish University Computer Network. |
5 | * All rights reserved. |
6 | * |
7 | * Written by Anders Magnusson for SUNET, Swedish University Computer Network. |
8 | * |
9 | * Redistribution and use in source and binary forms, with or without |
10 | * modification, are permitted provided that the following conditions |
11 | * are met: |
12 | * 1. Redistributions of source code must retain the above copyright |
13 | * notice, this list of conditions and the following disclaimer. |
14 | * 2. Redistributions in binary form must reproduce the above copyright |
15 | * notice, this list of conditions and the following disclaimer in the |
16 | * documentation and/or other materials provided with the distribution. |
17 | * 3. All advertising materials mentioning features or use of this software |
18 | * must display the following acknowledgement: |
19 | * This product includes software developed for the NetBSD Project by |
20 | * SUNET, Swedish University Computer Network. |
21 | * 4. The name of SUNET may not be used to endorse or promote products |
22 | * derived from this software without specific prior written permission. |
23 | * |
24 | * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND |
25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
26 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
27 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC |
28 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
34 | * POSSIBILITY OF SUCH DAMAGE. |
35 | */ |
36 | |
37 | /* |
38 | * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. |
39 | * All rights reserved. |
40 | * |
41 | * Written by Jason R. Thorpe for Wasabi Systems, Inc. |
42 | * |
43 | * Redistribution and use in source and binary forms, with or without |
44 | * modification, are permitted provided that the following conditions |
45 | * are met: |
46 | * 1. Redistributions of source code must retain the above copyright |
47 | * notice, this list of conditions and the following disclaimer. |
48 | * 2. Redistributions in binary form must reproduce the above copyright |
49 | * notice, this list of conditions and the following disclaimer in the |
50 | * documentation and/or other materials provided with the distribution. |
51 | * 3. All advertising materials mentioning features or use of this software |
52 | * must display the following acknowledgement: |
53 | * This product includes software developed for the NetBSD Project by |
54 | * Wasabi Systems, Inc. |
55 | * 4. The name of Wasabi Systems, Inc. may not be used to endorse |
56 | * or promote products derived from this software without specific prior |
57 | * written permission. |
58 | * |
59 | * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND |
60 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
61 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
62 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC |
63 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
64 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
65 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
66 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
67 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
68 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
69 | * POSSIBILITY OF SUCH DAMAGE. |
70 | */ |
71 | |
72 | /* |
73 | * Device driver for the Intel 82597EX Ten Gigabit Ethernet controller. |
74 | * |
75 | * TODO (in no specific order): |
76 | * HW VLAN support. |
77 | * TSE offloading (needs kernel changes...) |
78 | * RAIDC (receive interrupt delay adaptation) |
79 | * Use memory > 4GB. |
80 | */ |
81 | |
82 | #include <sys/cdefs.h> |
83 | __KERNEL_RCSID(0, "$NetBSD: if_dge.c,v 1.45 2016/07/07 06:55:41 msaitoh Exp $" ); |
84 | |
85 | |
86 | |
87 | #include <sys/param.h> |
88 | #include <sys/systm.h> |
89 | #include <sys/callout.h> |
90 | #include <sys/mbuf.h> |
91 | #include <sys/malloc.h> |
92 | #include <sys/kernel.h> |
93 | #include <sys/socket.h> |
94 | #include <sys/ioctl.h> |
95 | #include <sys/errno.h> |
96 | #include <sys/device.h> |
97 | #include <sys/queue.h> |
98 | |
99 | #include <sys/rndsource.h> |
100 | |
101 | #include <net/if.h> |
102 | #include <net/if_dl.h> |
103 | #include <net/if_media.h> |
104 | #include <net/if_ether.h> |
105 | |
106 | #include <net/bpf.h> |
107 | |
108 | #include <netinet/in.h> /* XXX for struct ip */ |
109 | #include <netinet/in_systm.h> /* XXX for struct ip */ |
110 | #include <netinet/ip.h> /* XXX for struct ip */ |
111 | #include <netinet/tcp.h> /* XXX for struct tcphdr */ |
112 | |
113 | #include <sys/bus.h> |
114 | #include <sys/intr.h> |
115 | #include <machine/endian.h> |
116 | |
117 | #include <dev/mii/mii.h> |
118 | #include <dev/mii/miivar.h> |
119 | #include <dev/mii/mii_bitbang.h> |
120 | |
121 | #include <dev/pci/pcireg.h> |
122 | #include <dev/pci/pcivar.h> |
123 | #include <dev/pci/pcidevs.h> |
124 | |
125 | #include <dev/pci/if_dgereg.h> |
126 | |
127 | /* |
128 | * The receive engine may sometimes become off-by-one when writing back |
129 | * chained descriptors. Avoid this by allocating a large chunk of |
130 | * memory and use if instead (to avoid chained descriptors). |
131 | * This only happens with chained descriptors under heavy load. |
132 | */ |
133 | #define DGE_OFFBYONE_RXBUG |
134 | |
135 | #define DGE_EVENT_COUNTERS |
136 | #define DGE_DEBUG |
137 | |
138 | #ifdef DGE_DEBUG |
139 | #define DGE_DEBUG_LINK 0x01 |
140 | #define DGE_DEBUG_TX 0x02 |
141 | #define DGE_DEBUG_RX 0x04 |
142 | #define DGE_DEBUG_CKSUM 0x08 |
143 | int dge_debug = 0; |
144 | |
145 | #define DPRINTF(x, y) if (dge_debug & (x)) printf y |
146 | #else |
147 | #define DPRINTF(x, y) /* nothing */ |
148 | #endif /* DGE_DEBUG */ |
149 | |
150 | /* |
151 | * Transmit descriptor list size. We allow up to 100 DMA segments per |
152 | * packet (Intel reports of jumbo frame packets with as |
153 | * many as 80 DMA segments when using 16k buffers). |
154 | */ |
155 | #define DGE_NTXSEGS 100 |
156 | #define DGE_IFQUEUELEN 20000 |
157 | #define DGE_TXQUEUELEN 2048 |
158 | #define DGE_TXQUEUELEN_MASK (DGE_TXQUEUELEN - 1) |
159 | #define DGE_TXQUEUE_GC (DGE_TXQUEUELEN / 8) |
160 | #define DGE_NTXDESC 1024 |
161 | #define DGE_NTXDESC_MASK (DGE_NTXDESC - 1) |
162 | #define DGE_NEXTTX(x) (((x) + 1) & DGE_NTXDESC_MASK) |
163 | #define DGE_NEXTTXS(x) (((x) + 1) & DGE_TXQUEUELEN_MASK) |
164 | |
165 | /* |
166 | * Receive descriptor list size. |
167 | * Packet is of size MCLBYTES, and for jumbo packets buffers may |
168 | * be chained. Due to the nature of the card (high-speed), keep this |
169 | * ring large. With 2k buffers the ring can store 400 jumbo packets, |
170 | * which at full speed will be received in just under 3ms. |
171 | */ |
172 | #define DGE_NRXDESC 2048 |
173 | #define DGE_NRXDESC_MASK (DGE_NRXDESC - 1) |
174 | #define DGE_NEXTRX(x) (((x) + 1) & DGE_NRXDESC_MASK) |
175 | /* |
176 | * # of descriptors between head and written descriptors. |
177 | * This is to work-around two erratas. |
178 | */ |
179 | #define DGE_RXSPACE 10 |
180 | #define DGE_PREVRX(x) (((x) - DGE_RXSPACE) & DGE_NRXDESC_MASK) |
181 | /* |
182 | * Receive descriptor fetch threshholds. These are values recommended |
183 | * by Intel, do not touch them unless you know what you are doing. |
184 | */ |
185 | #define RXDCTL_PTHRESH_VAL 128 |
186 | #define RXDCTL_HTHRESH_VAL 16 |
187 | #define RXDCTL_WTHRESH_VAL 16 |
188 | |
189 | |
190 | /* |
191 | * Tweakable parameters; default values. |
192 | */ |
193 | #define FCRTH 0x30000 /* Send XOFF water mark */ |
194 | #define FCRTL 0x28000 /* Send XON water mark */ |
195 | #define RDTR 0x20 /* Interrupt delay after receive, .8192us units */ |
196 | #define TIDV 0x20 /* Interrupt delay after send, .8192us units */ |
197 | |
198 | /* |
199 | * Control structures are DMA'd to the i82597 chip. We allocate them in |
200 | * a single clump that maps to a single DMA segment to make serveral things |
201 | * easier. |
202 | */ |
203 | struct dge_control_data { |
204 | /* |
205 | * The transmit descriptors. |
206 | */ |
207 | struct dge_tdes wcd_txdescs[DGE_NTXDESC]; |
208 | |
209 | /* |
210 | * The receive descriptors. |
211 | */ |
212 | struct dge_rdes wcd_rxdescs[DGE_NRXDESC]; |
213 | }; |
214 | |
215 | #define DGE_CDOFF(x) offsetof(struct dge_control_data, x) |
216 | #define DGE_CDTXOFF(x) DGE_CDOFF(wcd_txdescs[(x)]) |
217 | #define DGE_CDRXOFF(x) DGE_CDOFF(wcd_rxdescs[(x)]) |
218 | |
219 | /* |
220 | * The DGE interface have a higher max MTU size than normal jumbo frames. |
221 | */ |
222 | #define DGE_MAX_MTU 16288 /* Max MTU size for this interface */ |
223 | |
224 | /* |
225 | * Software state for transmit jobs. |
226 | */ |
227 | struct dge_txsoft { |
228 | struct mbuf *txs_mbuf; /* head of our mbuf chain */ |
229 | bus_dmamap_t txs_dmamap; /* our DMA map */ |
230 | int txs_firstdesc; /* first descriptor in packet */ |
231 | int txs_lastdesc; /* last descriptor in packet */ |
232 | int txs_ndesc; /* # of descriptors used */ |
233 | }; |
234 | |
235 | /* |
236 | * Software state for receive buffers. Each descriptor gets a |
237 | * 2k (MCLBYTES) buffer and a DMA map. For packets which fill |
238 | * more than one buffer, we chain them together. |
239 | */ |
240 | struct dge_rxsoft { |
241 | struct mbuf *rxs_mbuf; /* head of our mbuf chain */ |
242 | bus_dmamap_t rxs_dmamap; /* our DMA map */ |
243 | }; |
244 | |
245 | /* |
246 | * Software state per device. |
247 | */ |
248 | struct dge_softc { |
249 | device_t sc_dev; /* generic device information */ |
250 | bus_space_tag_t sc_st; /* bus space tag */ |
251 | bus_space_handle_t sc_sh; /* bus space handle */ |
252 | bus_dma_tag_t sc_dmat; /* bus DMA tag */ |
253 | struct ethercom sc_ethercom; /* ethernet common data */ |
254 | |
255 | int sc_flags; /* flags; see below */ |
256 | int sc_bus_speed; /* PCI/PCIX bus speed */ |
257 | int sc_pcix_offset; /* PCIX capability register offset */ |
258 | |
259 | const struct dge_product *sc_dgep; /* Pointer to the dge_product entry */ |
260 | pci_chipset_tag_t sc_pc; |
261 | pcitag_t sc_pt; |
262 | int sc_mmrbc; /* Max PCIX memory read byte count */ |
263 | |
264 | void *sc_ih; /* interrupt cookie */ |
265 | |
266 | struct ifmedia sc_media; |
267 | |
268 | bus_dmamap_t sc_cddmamap; /* control data DMA map */ |
269 | #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr |
270 | |
271 | int sc_align_tweak; |
272 | |
273 | /* |
274 | * Software state for the transmit and receive descriptors. |
275 | */ |
276 | struct dge_txsoft sc_txsoft[DGE_TXQUEUELEN]; |
277 | struct dge_rxsoft sc_rxsoft[DGE_NRXDESC]; |
278 | |
279 | /* |
280 | * Control data structures. |
281 | */ |
282 | struct dge_control_data *sc_control_data; |
283 | #define sc_txdescs sc_control_data->wcd_txdescs |
284 | #define sc_rxdescs sc_control_data->wcd_rxdescs |
285 | |
286 | #ifdef DGE_EVENT_COUNTERS |
287 | /* Event counters. */ |
288 | struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ |
289 | struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ |
290 | struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ |
291 | struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ |
292 | struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ |
293 | struct evcnt sc_ev_rxintr; /* Rx interrupts */ |
294 | struct evcnt sc_ev_linkintr; /* Link interrupts */ |
295 | |
296 | struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ |
297 | struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ |
298 | struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ |
299 | struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ |
300 | |
301 | struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ |
302 | struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ |
303 | struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ |
304 | |
305 | struct evcnt sc_ev_txseg[DGE_NTXSEGS]; /* Tx packets w/ N segments */ |
306 | struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ |
307 | #endif /* DGE_EVENT_COUNTERS */ |
308 | |
309 | int sc_txfree; /* number of free Tx descriptors */ |
310 | int sc_txnext; /* next ready Tx descriptor */ |
311 | |
312 | int sc_txsfree; /* number of free Tx jobs */ |
313 | int sc_txsnext; /* next free Tx job */ |
314 | int sc_txsdirty; /* dirty Tx jobs */ |
315 | |
316 | uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ |
317 | uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ |
318 | |
319 | int sc_rxptr; /* next ready Rx descriptor/queue ent */ |
320 | int sc_rxdiscard; |
321 | int sc_rxlen; |
322 | struct mbuf *sc_rxhead; |
323 | struct mbuf *sc_rxtail; |
324 | struct mbuf **sc_rxtailp; |
325 | |
326 | uint32_t sc_ctrl0; /* prototype CTRL0 register */ |
327 | uint32_t sc_icr; /* prototype interrupt bits */ |
328 | uint32_t sc_tctl; /* prototype TCTL register */ |
329 | uint32_t sc_rctl; /* prototype RCTL register */ |
330 | |
331 | int sc_mchash_type; /* multicast filter offset */ |
332 | |
333 | uint16_t sc_eeprom[EEPROM_SIZE]; |
334 | |
335 | krndsource_t rnd_source; /* random source */ |
336 | #ifdef DGE_OFFBYONE_RXBUG |
337 | void *sc_bugbuf; |
338 | SLIST_HEAD(, rxbugentry) sc_buglist; |
339 | bus_dmamap_t sc_bugmap; |
340 | struct rxbugentry *sc_entry; |
341 | #endif |
342 | }; |
343 | |
344 | #define DGE_RXCHAIN_RESET(sc) \ |
345 | do { \ |
346 | (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ |
347 | *(sc)->sc_rxtailp = NULL; \ |
348 | (sc)->sc_rxlen = 0; \ |
349 | } while (/*CONSTCOND*/0) |
350 | |
351 | #define DGE_RXCHAIN_LINK(sc, m) \ |
352 | do { \ |
353 | *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ |
354 | (sc)->sc_rxtailp = &(m)->m_next; \ |
355 | } while (/*CONSTCOND*/0) |
356 | |
357 | /* sc_flags */ |
358 | #define DGE_F_BUS64 0x20 /* bus is 64-bit */ |
359 | #define DGE_F_PCIX 0x40 /* bus is PCI-X */ |
360 | |
361 | #ifdef DGE_EVENT_COUNTERS |
362 | #define DGE_EVCNT_INCR(ev) (ev)->ev_count++ |
363 | #else |
364 | #define DGE_EVCNT_INCR(ev) /* nothing */ |
365 | #endif |
366 | |
367 | #define CSR_READ(sc, reg) \ |
368 | bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) |
369 | #define CSR_WRITE(sc, reg, val) \ |
370 | bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) |
371 | |
372 | #define DGE_CDTXADDR(sc, x) ((sc)->sc_cddma + DGE_CDTXOFF((x))) |
373 | #define DGE_CDRXADDR(sc, x) ((sc)->sc_cddma + DGE_CDRXOFF((x))) |
374 | |
375 | #define DGE_CDTXSYNC(sc, x, n, ops) \ |
376 | do { \ |
377 | int __x, __n; \ |
378 | \ |
379 | __x = (x); \ |
380 | __n = (n); \ |
381 | \ |
382 | /* If it will wrap around, sync to the end of the ring. */ \ |
383 | if ((__x + __n) > DGE_NTXDESC) { \ |
384 | bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ |
385 | DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * \ |
386 | (DGE_NTXDESC - __x), (ops)); \ |
387 | __n -= (DGE_NTXDESC - __x); \ |
388 | __x = 0; \ |
389 | } \ |
390 | \ |
391 | /* Now sync whatever is left. */ \ |
392 | bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ |
393 | DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * __n, (ops)); \ |
394 | } while (/*CONSTCOND*/0) |
395 | |
396 | #define DGE_CDRXSYNC(sc, x, ops) \ |
397 | do { \ |
398 | bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ |
399 | DGE_CDRXOFF((x)), sizeof(struct dge_rdes), (ops)); \ |
400 | } while (/*CONSTCOND*/0) |
401 | |
402 | #ifdef DGE_OFFBYONE_RXBUG |
403 | #define DGE_INIT_RXDESC(sc, x) \ |
404 | do { \ |
405 | struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ |
406 | struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ |
407 | struct mbuf *__m = __rxs->rxs_mbuf; \ |
408 | \ |
409 | __rxd->dr_baddrl = htole32(sc->sc_bugmap->dm_segs[0].ds_addr + \ |
410 | (mtod((__m), char *) - (char *)sc->sc_bugbuf)); \ |
411 | __rxd->dr_baddrh = 0; \ |
412 | __rxd->dr_len = 0; \ |
413 | __rxd->dr_cksum = 0; \ |
414 | __rxd->dr_status = 0; \ |
415 | __rxd->dr_errors = 0; \ |
416 | __rxd->dr_special = 0; \ |
417 | DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ |
418 | \ |
419 | CSR_WRITE((sc), DGE_RDT, (x)); \ |
420 | } while (/*CONSTCOND*/0) |
421 | #else |
422 | #define DGE_INIT_RXDESC(sc, x) \ |
423 | do { \ |
424 | struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ |
425 | struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ |
426 | struct mbuf *__m = __rxs->rxs_mbuf; \ |
427 | \ |
428 | /* \ |
429 | * Note: We scoot the packet forward 2 bytes in the buffer \ |
430 | * so that the payload after the Ethernet header is aligned \ |
431 | * to a 4-byte boundary. \ |
432 | * \ |
433 | * XXX BRAINDAMAGE ALERT! \ |
434 | * The stupid chip uses the same size for every buffer, which \ |
435 | * is set in the Receive Control register. We are using the 2K \ |
436 | * size option, but what we REALLY want is (2K - 2)! For this \ |
437 | * reason, we can't "scoot" packets longer than the standard \ |
438 | * Ethernet MTU. On strict-alignment platforms, if the total \ |
439 | * size exceeds (2K - 2) we set align_tweak to 0 and let \ |
440 | * the upper layer copy the headers. \ |
441 | */ \ |
442 | __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ |
443 | \ |
444 | __rxd->dr_baddrl = \ |
445 | htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + \ |
446 | (sc)->sc_align_tweak); \ |
447 | __rxd->dr_baddrh = 0; \ |
448 | __rxd->dr_len = 0; \ |
449 | __rxd->dr_cksum = 0; \ |
450 | __rxd->dr_status = 0; \ |
451 | __rxd->dr_errors = 0; \ |
452 | __rxd->dr_special = 0; \ |
453 | DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ |
454 | \ |
455 | CSR_WRITE((sc), DGE_RDT, (x)); \ |
456 | } while (/*CONSTCOND*/0) |
457 | #endif |
458 | |
459 | #ifdef DGE_OFFBYONE_RXBUG |
460 | /* |
461 | * Allocation constants. Much memory may be used for this. |
462 | */ |
463 | #ifndef DGE_BUFFER_SIZE |
464 | #define DGE_BUFFER_SIZE DGE_MAX_MTU |
465 | #endif |
466 | #define DGE_NBUFFERS (4*DGE_NRXDESC) |
467 | #define DGE_RXMEM (DGE_NBUFFERS*DGE_BUFFER_SIZE) |
468 | |
469 | struct rxbugentry { |
470 | SLIST_ENTRY(rxbugentry) rb_entry; |
471 | int rb_slot; |
472 | }; |
473 | |
474 | static int |
475 | dge_alloc_rcvmem(struct dge_softc *sc) |
476 | { |
477 | char *kva; |
478 | bus_dma_segment_t seg; |
479 | int i, rseg, state, error; |
480 | struct rxbugentry *entry; |
481 | |
482 | state = error = 0; |
483 | |
484 | if (bus_dmamem_alloc(sc->sc_dmat, DGE_RXMEM, PAGE_SIZE, 0, |
485 | &seg, 1, &rseg, BUS_DMA_NOWAIT)) { |
486 | aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n" ); |
487 | return ENOBUFS; |
488 | } |
489 | |
490 | state = 1; |
491 | if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, DGE_RXMEM, (void **)&kva, |
492 | BUS_DMA_NOWAIT)) { |
493 | aprint_error_dev(sc->sc_dev, "can't map DMA buffers (%d bytes)\n" , |
494 | (int)DGE_RXMEM); |
495 | error = ENOBUFS; |
496 | goto out; |
497 | } |
498 | |
499 | state = 2; |
500 | if (bus_dmamap_create(sc->sc_dmat, DGE_RXMEM, 1, DGE_RXMEM, 0, |
501 | BUS_DMA_NOWAIT, &sc->sc_bugmap)) { |
502 | aprint_error_dev(sc->sc_dev, "can't create DMA map\n" ); |
503 | error = ENOBUFS; |
504 | goto out; |
505 | } |
506 | |
507 | state = 3; |
508 | if (bus_dmamap_load(sc->sc_dmat, sc->sc_bugmap, |
509 | kva, DGE_RXMEM, NULL, BUS_DMA_NOWAIT)) { |
510 | aprint_error_dev(sc->sc_dev, "can't load DMA map\n" ); |
511 | error = ENOBUFS; |
512 | goto out; |
513 | } |
514 | |
515 | state = 4; |
516 | sc->sc_bugbuf = (void *)kva; |
517 | SLIST_INIT(&sc->sc_buglist); |
518 | |
519 | /* |
520 | * Now divide it up into DGE_BUFFER_SIZE pieces and save the addresses |
521 | * in an array. |
522 | */ |
523 | if ((entry = malloc(sizeof(*entry) * DGE_NBUFFERS, |
524 | M_DEVBUF, M_NOWAIT)) == NULL) { |
525 | error = ENOBUFS; |
526 | goto out; |
527 | } |
528 | sc->sc_entry = entry; |
529 | for (i = 0; i < DGE_NBUFFERS; i++) { |
530 | entry[i].rb_slot = i; |
531 | SLIST_INSERT_HEAD(&sc->sc_buglist, &entry[i], rb_entry); |
532 | } |
533 | out: |
534 | if (error != 0) { |
535 | switch (state) { |
536 | case 4: |
537 | bus_dmamap_unload(sc->sc_dmat, sc->sc_bugmap); |
538 | case 3: |
539 | bus_dmamap_destroy(sc->sc_dmat, sc->sc_bugmap); |
540 | case 2: |
541 | bus_dmamem_unmap(sc->sc_dmat, kva, DGE_RXMEM); |
542 | case 1: |
543 | bus_dmamem_free(sc->sc_dmat, &seg, rseg); |
544 | break; |
545 | default: |
546 | break; |
547 | } |
548 | } |
549 | |
550 | return error; |
551 | } |
552 | |
553 | /* |
554 | * Allocate a jumbo buffer. |
555 | */ |
556 | static void * |
557 | dge_getbuf(struct dge_softc *sc) |
558 | { |
559 | struct rxbugentry *entry; |
560 | |
561 | entry = SLIST_FIRST(&sc->sc_buglist); |
562 | |
563 | if (entry == NULL) { |
564 | printf("%s: no free RX buffers\n" , device_xname(sc->sc_dev)); |
565 | return(NULL); |
566 | } |
567 | |
568 | SLIST_REMOVE_HEAD(&sc->sc_buglist, rb_entry); |
569 | return (char *)sc->sc_bugbuf + entry->rb_slot * DGE_BUFFER_SIZE; |
570 | } |
571 | |
572 | /* |
573 | * Release a jumbo buffer. |
574 | */ |
575 | static void |
576 | dge_freebuf(struct mbuf *m, void *buf, size_t size, void *arg) |
577 | { |
578 | struct rxbugentry *entry; |
579 | struct dge_softc *sc; |
580 | int i, s; |
581 | |
582 | /* Extract the softc struct pointer. */ |
583 | sc = (struct dge_softc *)arg; |
584 | |
585 | if (sc == NULL) |
586 | panic("dge_freebuf: can't find softc pointer!" ); |
587 | |
588 | /* calculate the slot this buffer belongs to */ |
589 | |
590 | i = ((char *)buf - (char *)sc->sc_bugbuf) / DGE_BUFFER_SIZE; |
591 | |
592 | if ((i < 0) || (i >= DGE_NBUFFERS)) |
593 | panic("dge_freebuf: asked to free buffer %d!" , i); |
594 | |
595 | s = splvm(); |
596 | entry = sc->sc_entry + i; |
597 | SLIST_INSERT_HEAD(&sc->sc_buglist, entry, rb_entry); |
598 | |
599 | if (__predict_true(m != NULL)) |
600 | pool_cache_put(mb_cache, m); |
601 | splx(s); |
602 | } |
603 | #endif |
604 | |
605 | static void dge_start(struct ifnet *); |
606 | static void dge_watchdog(struct ifnet *); |
607 | static int dge_ioctl(struct ifnet *, u_long, void *); |
608 | static int dge_init(struct ifnet *); |
609 | static void dge_stop(struct ifnet *, int); |
610 | |
611 | static bool dge_shutdown(device_t, int); |
612 | |
613 | static void dge_reset(struct dge_softc *); |
614 | static void dge_rxdrain(struct dge_softc *); |
615 | static int dge_add_rxbuf(struct dge_softc *, int); |
616 | |
617 | static void dge_set_filter(struct dge_softc *); |
618 | |
619 | static int dge_intr(void *); |
620 | static void dge_txintr(struct dge_softc *); |
621 | static void dge_rxintr(struct dge_softc *); |
622 | static void dge_linkintr(struct dge_softc *, uint32_t); |
623 | |
624 | static int dge_match(device_t, cfdata_t, void *); |
625 | static void dge_attach(device_t, device_t, void *); |
626 | |
627 | static int dge_read_eeprom(struct dge_softc *sc); |
628 | static int dge_eeprom_clockin(struct dge_softc *sc); |
629 | static void dge_eeprom_clockout(struct dge_softc *sc, int bit); |
630 | static uint16_t dge_eeprom_word(struct dge_softc *sc, int addr); |
631 | static int dge_xgmii_mediachange(struct ifnet *); |
632 | static void dge_xgmii_mediastatus(struct ifnet *, struct ifmediareq *); |
633 | static void dge_xgmii_reset(struct dge_softc *); |
634 | static void dge_xgmii_writereg(struct dge_softc *, int, int, int); |
635 | |
636 | |
637 | CFATTACH_DECL_NEW(dge, sizeof(struct dge_softc), |
638 | dge_match, dge_attach, NULL, NULL); |
639 | |
640 | #ifdef DGE_EVENT_COUNTERS |
641 | #if DGE_NTXSEGS > 100 |
642 | #error Update dge_txseg_evcnt_names |
643 | #endif |
644 | static char (*dge_txseg_evcnt_names)[DGE_NTXSEGS][8 /* "txseg00" + \0 */]; |
645 | #endif /* DGE_EVENT_COUNTERS */ |
646 | |
647 | /* |
648 | * Devices supported by this driver. |
649 | */ |
650 | static const struct dge_product { |
651 | pci_vendor_id_t dgep_vendor; |
652 | pci_product_id_t dgep_product; |
653 | const char *dgep_name; |
654 | int dgep_flags; |
655 | #define DGEP_F_10G_LR 0x01 |
656 | #define DGEP_F_10G_SR 0x02 |
657 | } dge_products[] = { |
658 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX, |
659 | "Intel i82597EX 10GbE-LR Ethernet" , |
660 | DGEP_F_10G_LR }, |
661 | |
662 | { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX_SR, |
663 | "Intel i82597EX 10GbE-SR Ethernet" , |
664 | DGEP_F_10G_SR }, |
665 | |
666 | { 0, 0, |
667 | NULL, |
668 | 0 }, |
669 | }; |
670 | |
671 | static const struct dge_product * |
672 | dge_lookup(const struct pci_attach_args *pa) |
673 | { |
674 | const struct dge_product *dgep; |
675 | |
676 | for (dgep = dge_products; dgep->dgep_name != NULL; dgep++) { |
677 | if (PCI_VENDOR(pa->pa_id) == dgep->dgep_vendor && |
678 | PCI_PRODUCT(pa->pa_id) == dgep->dgep_product) |
679 | return dgep; |
680 | } |
681 | return NULL; |
682 | } |
683 | |
684 | static int |
685 | dge_match(device_t parent, cfdata_t cf, void *aux) |
686 | { |
687 | struct pci_attach_args *pa = aux; |
688 | |
689 | if (dge_lookup(pa) != NULL) |
690 | return (1); |
691 | |
692 | return (0); |
693 | } |
694 | |
695 | static void |
696 | dge_attach(device_t parent, device_t self, void *aux) |
697 | { |
698 | struct dge_softc *sc = device_private(self); |
699 | struct pci_attach_args *pa = aux; |
700 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; |
701 | pci_chipset_tag_t pc = pa->pa_pc; |
702 | pci_intr_handle_t ih; |
703 | const char *intrstr = NULL; |
704 | bus_dma_segment_t seg; |
705 | int i, rseg, error; |
706 | uint8_t enaddr[ETHER_ADDR_LEN]; |
707 | pcireg_t preg, memtype; |
708 | uint32_t reg; |
709 | char intrbuf[PCI_INTRSTR_LEN]; |
710 | const struct dge_product *dgep; |
711 | |
712 | sc->sc_dgep = dgep = dge_lookup(pa); |
713 | if (dgep == NULL) { |
714 | printf("\n" ); |
715 | panic("dge_attach: impossible" ); |
716 | } |
717 | |
718 | sc->sc_dev = self; |
719 | sc->sc_dmat = pa->pa_dmat; |
720 | sc->sc_pc = pa->pa_pc; |
721 | sc->sc_pt = pa->pa_tag; |
722 | |
723 | pci_aprint_devinfo_fancy(pa, "Ethernet controller" , |
724 | dgep->dgep_name, 1); |
725 | |
726 | memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, DGE_PCI_BAR); |
727 | if (pci_mapreg_map(pa, DGE_PCI_BAR, memtype, 0, |
728 | &sc->sc_st, &sc->sc_sh, NULL, NULL)) { |
729 | aprint_error_dev(sc->sc_dev, |
730 | "unable to map device registers\n" ); |
731 | return; |
732 | } |
733 | |
734 | /* Enable bus mastering */ |
735 | preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); |
736 | preg |= PCI_COMMAND_MASTER_ENABLE; |
737 | pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); |
738 | |
739 | /* |
740 | * Map and establish our interrupt. |
741 | */ |
742 | if (pci_intr_map(pa, &ih)) { |
743 | aprint_error_dev(sc->sc_dev, "unable to map interrupt\n" ); |
744 | return; |
745 | } |
746 | intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); |
747 | sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, dge_intr, sc); |
748 | if (sc->sc_ih == NULL) { |
749 | aprint_error_dev(sc->sc_dev, "unable to establish interrupt" ); |
750 | if (intrstr != NULL) |
751 | aprint_error(" at %s" , intrstr); |
752 | aprint_error("\n" ); |
753 | return; |
754 | } |
755 | aprint_normal_dev(sc->sc_dev, "interrupting at %s\n" , intrstr); |
756 | |
757 | /* |
758 | * Determine a few things about the bus we're connected to. |
759 | */ |
760 | reg = CSR_READ(sc, DGE_STATUS); |
761 | if (reg & STATUS_BUS64) |
762 | sc->sc_flags |= DGE_F_BUS64; |
763 | |
764 | sc->sc_flags |= DGE_F_PCIX; |
765 | if (pci_get_capability(pa->pa_pc, pa->pa_tag, |
766 | PCI_CAP_PCIX, |
767 | &sc->sc_pcix_offset, NULL) == 0) |
768 | aprint_error_dev(sc->sc_dev, "unable to find PCIX " |
769 | "capability\n" ); |
770 | |
771 | if (sc->sc_flags & DGE_F_PCIX) { |
772 | switch (reg & STATUS_PCIX_MSK) { |
773 | case STATUS_PCIX_66: |
774 | sc->sc_bus_speed = 66; |
775 | break; |
776 | case STATUS_PCIX_100: |
777 | sc->sc_bus_speed = 100; |
778 | break; |
779 | case STATUS_PCIX_133: |
780 | sc->sc_bus_speed = 133; |
781 | break; |
782 | default: |
783 | aprint_error_dev(sc->sc_dev, |
784 | "unknown PCIXSPD %d; assuming 66MHz\n" , |
785 | reg & STATUS_PCIX_MSK); |
786 | sc->sc_bus_speed = 66; |
787 | } |
788 | } else |
789 | sc->sc_bus_speed = (reg & STATUS_BUS64) ? 66 : 33; |
790 | aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n" , |
791 | (sc->sc_flags & DGE_F_BUS64) ? 64 : 32, sc->sc_bus_speed, |
792 | (sc->sc_flags & DGE_F_PCIX) ? "PCIX" : "PCI" ); |
793 | |
794 | /* |
795 | * Allocate the control data structures, and create and load the |
796 | * DMA map for it. |
797 | */ |
798 | if ((error = bus_dmamem_alloc(sc->sc_dmat, |
799 | sizeof(struct dge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, |
800 | 0)) != 0) { |
801 | aprint_error_dev(sc->sc_dev, |
802 | "unable to allocate control data, error = %d\n" , |
803 | error); |
804 | goto fail_0; |
805 | } |
806 | |
807 | if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, |
808 | sizeof(struct dge_control_data), (void **)&sc->sc_control_data, |
809 | 0)) != 0) { |
810 | aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n" , |
811 | error); |
812 | goto fail_1; |
813 | } |
814 | |
815 | if ((error = bus_dmamap_create(sc->sc_dmat, |
816 | sizeof(struct dge_control_data), 1, |
817 | sizeof(struct dge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { |
818 | aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " |
819 | "error = %d\n" , error); |
820 | goto fail_2; |
821 | } |
822 | |
823 | if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, |
824 | sc->sc_control_data, sizeof(struct dge_control_data), NULL, |
825 | 0)) != 0) { |
826 | aprint_error_dev(sc->sc_dev, |
827 | "unable to load control data DMA map, error = %d\n" , |
828 | error); |
829 | goto fail_3; |
830 | } |
831 | |
832 | #ifdef DGE_OFFBYONE_RXBUG |
833 | if (dge_alloc_rcvmem(sc) != 0) |
834 | return; /* Already complained */ |
835 | #endif |
836 | /* |
837 | * Create the transmit buffer DMA maps. |
838 | */ |
839 | for (i = 0; i < DGE_TXQUEUELEN; i++) { |
840 | if ((error = bus_dmamap_create(sc->sc_dmat, DGE_MAX_MTU, |
841 | DGE_NTXSEGS, MCLBYTES, 0, 0, |
842 | &sc->sc_txsoft[i].txs_dmamap)) != 0) { |
843 | aprint_error_dev(sc->sc_dev, "unable to create Tx DMA map %d, " |
844 | "error = %d\n" , i, error); |
845 | goto fail_4; |
846 | } |
847 | } |
848 | |
849 | /* |
850 | * Create the receive buffer DMA maps. |
851 | */ |
852 | for (i = 0; i < DGE_NRXDESC; i++) { |
853 | #ifdef DGE_OFFBYONE_RXBUG |
854 | if ((error = bus_dmamap_create(sc->sc_dmat, DGE_BUFFER_SIZE, 1, |
855 | DGE_BUFFER_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { |
856 | #else |
857 | if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, |
858 | MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { |
859 | #endif |
860 | aprint_error_dev(sc->sc_dev, "unable to create Rx DMA map %d, " |
861 | "error = %d\n" , i, error); |
862 | goto fail_5; |
863 | } |
864 | sc->sc_rxsoft[i].rxs_mbuf = NULL; |
865 | } |
866 | |
867 | /* |
868 | * Set bits in ctrl0 register. |
869 | * Should get the software defined pins out of EEPROM? |
870 | */ |
871 | sc->sc_ctrl0 |= CTRL0_RPE | CTRL0_TPE; /* XON/XOFF */ |
872 | sc->sc_ctrl0 |= CTRL0_SDP3_DIR | CTRL0_SDP2_DIR | CTRL0_SDP1_DIR | |
873 | CTRL0_SDP0_DIR | CTRL0_SDP3 | CTRL0_SDP2 | CTRL0_SDP0; |
874 | |
875 | /* |
876 | * Reset the chip to a known state. |
877 | */ |
878 | dge_reset(sc); |
879 | |
880 | /* |
881 | * Reset the PHY. |
882 | */ |
883 | dge_xgmii_reset(sc); |
884 | |
885 | /* |
886 | * Read in EEPROM data. |
887 | */ |
888 | if (dge_read_eeprom(sc)) { |
889 | aprint_error_dev(sc->sc_dev, "couldn't read EEPROM\n" ); |
890 | return; |
891 | } |
892 | |
893 | /* |
894 | * Get the ethernet address. |
895 | */ |
896 | enaddr[0] = sc->sc_eeprom[EE_ADDR01] & 0377; |
897 | enaddr[1] = sc->sc_eeprom[EE_ADDR01] >> 8; |
898 | enaddr[2] = sc->sc_eeprom[EE_ADDR23] & 0377; |
899 | enaddr[3] = sc->sc_eeprom[EE_ADDR23] >> 8; |
900 | enaddr[4] = sc->sc_eeprom[EE_ADDR45] & 0377; |
901 | enaddr[5] = sc->sc_eeprom[EE_ADDR45] >> 8; |
902 | |
903 | aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n" , |
904 | ether_sprintf(enaddr)); |
905 | |
906 | /* |
907 | * Setup media stuff. |
908 | */ |
909 | ifmedia_init(&sc->sc_media, IFM_IMASK, dge_xgmii_mediachange, |
910 | dge_xgmii_mediastatus); |
911 | if (dgep->dgep_flags & DGEP_F_10G_SR) { |
912 | ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10G_SR, 0, NULL); |
913 | ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10G_SR); |
914 | } else { /* XXX default is LR */ |
915 | ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10G_LR, 0, NULL); |
916 | ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10G_LR); |
917 | } |
918 | |
919 | ifp = &sc->sc_ethercom.ec_if; |
920 | strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); |
921 | ifp->if_softc = sc; |
922 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; |
923 | ifp->if_ioctl = dge_ioctl; |
924 | ifp->if_start = dge_start; |
925 | ifp->if_watchdog = dge_watchdog; |
926 | ifp->if_init = dge_init; |
927 | ifp->if_stop = dge_stop; |
928 | IFQ_SET_MAXLEN(&ifp->if_snd, max(DGE_IFQUEUELEN, IFQ_MAXLEN)); |
929 | IFQ_SET_READY(&ifp->if_snd); |
930 | |
931 | sc->sc_ethercom.ec_capabilities |= |
932 | ETHERCAP_JUMBO_MTU | ETHERCAP_VLAN_MTU; |
933 | |
934 | /* |
935 | * We can perform TCPv4 and UDPv4 checkums in-bound. |
936 | */ |
937 | ifp->if_capabilities |= |
938 | IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | |
939 | IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | |
940 | IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; |
941 | |
942 | /* |
943 | * Attach the interface. |
944 | */ |
945 | if_attach(ifp); |
946 | ether_ifattach(ifp, enaddr); |
947 | rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), |
948 | RND_TYPE_NET, RND_FLAG_DEFAULT); |
949 | |
950 | #ifdef DGE_EVENT_COUNTERS |
951 | /* Fix segment event naming */ |
952 | if (dge_txseg_evcnt_names == NULL) { |
953 | dge_txseg_evcnt_names = |
954 | malloc(sizeof(*dge_txseg_evcnt_names), M_DEVBUF, M_WAITOK); |
955 | for (i = 0; i < DGE_NTXSEGS; i++) |
956 | snprintf((*dge_txseg_evcnt_names)[i], |
957 | sizeof((*dge_txseg_evcnt_names)[i]), "txseg%d" , i); |
958 | } |
959 | |
960 | /* Attach event counters. */ |
961 | evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, |
962 | NULL, device_xname(sc->sc_dev), "txsstall" ); |
963 | evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, |
964 | NULL, device_xname(sc->sc_dev), "txdstall" ); |
965 | evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_MISC, |
966 | NULL, device_xname(sc->sc_dev), "txforceintr" ); |
967 | evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, |
968 | NULL, device_xname(sc->sc_dev), "txdw" ); |
969 | evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, |
970 | NULL, device_xname(sc->sc_dev), "txqe" ); |
971 | evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, |
972 | NULL, device_xname(sc->sc_dev), "rxintr" ); |
973 | evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, |
974 | NULL, device_xname(sc->sc_dev), "linkintr" ); |
975 | |
976 | evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, |
977 | NULL, device_xname(sc->sc_dev), "rxipsum" ); |
978 | evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, |
979 | NULL, device_xname(sc->sc_dev), "rxtusum" ); |
980 | evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, |
981 | NULL, device_xname(sc->sc_dev), "txipsum" ); |
982 | evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, |
983 | NULL, device_xname(sc->sc_dev), "txtusum" ); |
984 | |
985 | evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, |
986 | NULL, device_xname(sc->sc_dev), "txctx init" ); |
987 | evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, |
988 | NULL, device_xname(sc->sc_dev), "txctx hit" ); |
989 | evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, |
990 | NULL, device_xname(sc->sc_dev), "txctx miss" ); |
991 | |
992 | for (i = 0; i < DGE_NTXSEGS; i++) |
993 | evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, |
994 | NULL, device_xname(sc->sc_dev), (*dge_txseg_evcnt_names)[i]); |
995 | |
996 | evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, |
997 | NULL, device_xname(sc->sc_dev), "txdrop" ); |
998 | |
999 | #endif /* DGE_EVENT_COUNTERS */ |
1000 | |
1001 | /* |
1002 | * Make sure the interface is shutdown during reboot. |
1003 | */ |
1004 | if (pmf_device_register1(self, NULL, NULL, dge_shutdown)) |
1005 | pmf_class_network_register(self, ifp); |
1006 | else |
1007 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
1008 | |
1009 | return; |
1010 | |
1011 | /* |
1012 | * Free any resources we've allocated during the failed attach |
1013 | * attempt. Do this in reverse order and fall through. |
1014 | */ |
1015 | fail_5: |
1016 | for (i = 0; i < DGE_NRXDESC; i++) { |
1017 | if (sc->sc_rxsoft[i].rxs_dmamap != NULL) |
1018 | bus_dmamap_destroy(sc->sc_dmat, |
1019 | sc->sc_rxsoft[i].rxs_dmamap); |
1020 | } |
1021 | fail_4: |
1022 | for (i = 0; i < DGE_TXQUEUELEN; i++) { |
1023 | if (sc->sc_txsoft[i].txs_dmamap != NULL) |
1024 | bus_dmamap_destroy(sc->sc_dmat, |
1025 | sc->sc_txsoft[i].txs_dmamap); |
1026 | } |
1027 | bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); |
1028 | fail_3: |
1029 | bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); |
1030 | fail_2: |
1031 | bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, |
1032 | sizeof(struct dge_control_data)); |
1033 | fail_1: |
1034 | bus_dmamem_free(sc->sc_dmat, &seg, rseg); |
1035 | fail_0: |
1036 | return; |
1037 | } |
1038 | |
1039 | /* |
1040 | * dge_shutdown: |
1041 | * |
1042 | * Make sure the interface is stopped at reboot time. |
1043 | */ |
1044 | static bool |
1045 | dge_shutdown(device_t self, int howto) |
1046 | { |
1047 | struct dge_softc *sc; |
1048 | |
1049 | sc = device_private(self); |
1050 | dge_stop(&sc->sc_ethercom.ec_if, 1); |
1051 | |
1052 | return true; |
1053 | } |
1054 | |
1055 | /* |
1056 | * dge_tx_cksum: |
1057 | * |
1058 | * Set up TCP/IP checksumming parameters for the |
1059 | * specified packet. |
1060 | */ |
1061 | static int |
1062 | dge_tx_cksum(struct dge_softc *sc, struct dge_txsoft *txs, uint8_t *fieldsp) |
1063 | { |
1064 | struct mbuf *m0 = txs->txs_mbuf; |
1065 | struct dge_ctdes *t; |
1066 | uint32_t ipcs, tucs; |
1067 | struct ether_header *eh; |
1068 | int offset, iphl; |
1069 | uint8_t fields = 0; |
1070 | |
1071 | /* |
1072 | * XXX It would be nice if the mbuf pkthdr had offset |
1073 | * fields for the protocol headers. |
1074 | */ |
1075 | |
1076 | eh = mtod(m0, struct ether_header *); |
1077 | switch (htons(eh->ether_type)) { |
1078 | case ETHERTYPE_IP: |
1079 | offset = ETHER_HDR_LEN; |
1080 | break; |
1081 | |
1082 | case ETHERTYPE_VLAN: |
1083 | offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; |
1084 | break; |
1085 | |
1086 | default: |
1087 | /* |
1088 | * Don't support this protocol or encapsulation. |
1089 | */ |
1090 | *fieldsp = 0; |
1091 | return (0); |
1092 | } |
1093 | |
1094 | iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); |
1095 | |
1096 | /* |
1097 | * NOTE: Even if we're not using the IP or TCP/UDP checksum |
1098 | * offload feature, if we load the context descriptor, we |
1099 | * MUST provide valid values for IPCSS and TUCSS fields. |
1100 | */ |
1101 | |
1102 | if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { |
1103 | DGE_EVCNT_INCR(&sc->sc_ev_txipsum); |
1104 | fields |= TDESC_POPTS_IXSM; |
1105 | ipcs = DGE_TCPIP_IPCSS(offset) | |
1106 | DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | |
1107 | DGE_TCPIP_IPCSE(offset + iphl - 1); |
1108 | } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { |
1109 | /* Use the cached value. */ |
1110 | ipcs = sc->sc_txctx_ipcs; |
1111 | } else { |
1112 | /* Just initialize it to the likely value anyway. */ |
1113 | ipcs = DGE_TCPIP_IPCSS(offset) | |
1114 | DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | |
1115 | DGE_TCPIP_IPCSE(offset + iphl - 1); |
1116 | } |
1117 | DPRINTF(DGE_DEBUG_CKSUM, |
1118 | ("%s: CKSUM: offset %d ipcs 0x%x\n" , |
1119 | device_xname(sc->sc_dev), offset, ipcs)); |
1120 | |
1121 | offset += iphl; |
1122 | |
1123 | if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { |
1124 | DGE_EVCNT_INCR(&sc->sc_ev_txtusum); |
1125 | fields |= TDESC_POPTS_TXSM; |
1126 | tucs = DGE_TCPIP_TUCSS(offset) | |
1127 | DGE_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | |
1128 | DGE_TCPIP_TUCSE(0) /* rest of packet */; |
1129 | } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { |
1130 | /* Use the cached value. */ |
1131 | tucs = sc->sc_txctx_tucs; |
1132 | } else { |
1133 | /* Just initialize it to a valid TCP context. */ |
1134 | tucs = DGE_TCPIP_TUCSS(offset) | |
1135 | DGE_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | |
1136 | DGE_TCPIP_TUCSE(0) /* rest of packet */; |
1137 | } |
1138 | |
1139 | DPRINTF(DGE_DEBUG_CKSUM, |
1140 | ("%s: CKSUM: offset %d tucs 0x%x\n" , |
1141 | device_xname(sc->sc_dev), offset, tucs)); |
1142 | |
1143 | if (sc->sc_txctx_ipcs == ipcs && |
1144 | sc->sc_txctx_tucs == tucs) { |
1145 | /* Cached context is fine. */ |
1146 | DGE_EVCNT_INCR(&sc->sc_ev_txctx_hit); |
1147 | } else { |
1148 | /* Fill in the context descriptor. */ |
1149 | #ifdef DGE_EVENT_COUNTERS |
1150 | if (sc->sc_txctx_ipcs == 0xffffffff && |
1151 | sc->sc_txctx_tucs == 0xffffffff) |
1152 | DGE_EVCNT_INCR(&sc->sc_ev_txctx_init); |
1153 | else |
1154 | DGE_EVCNT_INCR(&sc->sc_ev_txctx_miss); |
1155 | #endif |
1156 | t = (struct dge_ctdes *)&sc->sc_txdescs[sc->sc_txnext]; |
1157 | t->dc_tcpip_ipcs = htole32(ipcs); |
1158 | t->dc_tcpip_tucs = htole32(tucs); |
1159 | t->dc_tcpip_cmdlen = htole32(TDESC_DTYP_CTD); |
1160 | t->dc_tcpip_seg = 0; |
1161 | DGE_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); |
1162 | |
1163 | sc->sc_txctx_ipcs = ipcs; |
1164 | sc->sc_txctx_tucs = tucs; |
1165 | |
1166 | sc->sc_txnext = DGE_NEXTTX(sc->sc_txnext); |
1167 | txs->txs_ndesc++; |
1168 | } |
1169 | |
1170 | *fieldsp = fields; |
1171 | |
1172 | return (0); |
1173 | } |
1174 | |
1175 | /* |
1176 | * dge_start: [ifnet interface function] |
1177 | * |
1178 | * Start packet transmission on the interface. |
1179 | */ |
1180 | static void |
1181 | dge_start(struct ifnet *ifp) |
1182 | { |
1183 | struct dge_softc *sc = ifp->if_softc; |
1184 | struct mbuf *m0; |
1185 | struct dge_txsoft *txs; |
1186 | bus_dmamap_t dmamap; |
1187 | int error, nexttx, lasttx = -1, ofree, seg; |
1188 | uint32_t cksumcmd; |
1189 | uint8_t cksumfields; |
1190 | |
1191 | if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) |
1192 | return; |
1193 | |
1194 | /* |
1195 | * Remember the previous number of free descriptors. |
1196 | */ |
1197 | ofree = sc->sc_txfree; |
1198 | |
1199 | /* |
1200 | * Loop through the send queue, setting up transmit descriptors |
1201 | * until we drain the queue, or use up all available transmit |
1202 | * descriptors. |
1203 | */ |
1204 | for (;;) { |
1205 | /* Grab a packet off the queue. */ |
1206 | IFQ_POLL(&ifp->if_snd, m0); |
1207 | if (m0 == NULL) |
1208 | break; |
1209 | |
1210 | DPRINTF(DGE_DEBUG_TX, |
1211 | ("%s: TX: have packet to transmit: %p\n" , |
1212 | device_xname(sc->sc_dev), m0)); |
1213 | |
1214 | /* Get a work queue entry. */ |
1215 | if (sc->sc_txsfree < DGE_TXQUEUE_GC) { |
1216 | dge_txintr(sc); |
1217 | if (sc->sc_txsfree == 0) { |
1218 | DPRINTF(DGE_DEBUG_TX, |
1219 | ("%s: TX: no free job descriptors\n" , |
1220 | device_xname(sc->sc_dev))); |
1221 | DGE_EVCNT_INCR(&sc->sc_ev_txsstall); |
1222 | break; |
1223 | } |
1224 | } |
1225 | |
1226 | txs = &sc->sc_txsoft[sc->sc_txsnext]; |
1227 | dmamap = txs->txs_dmamap; |
1228 | |
1229 | /* |
1230 | * Load the DMA map. If this fails, the packet either |
1231 | * didn't fit in the allotted number of segments, or we |
1232 | * were short on resources. For the too-many-segments |
1233 | * case, we simply report an error and drop the packet, |
1234 | * since we can't sanely copy a jumbo packet to a single |
1235 | * buffer. |
1236 | */ |
1237 | error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, |
1238 | BUS_DMA_WRITE|BUS_DMA_NOWAIT); |
1239 | if (error) { |
1240 | if (error == EFBIG) { |
1241 | DGE_EVCNT_INCR(&sc->sc_ev_txdrop); |
1242 | printf("%s: Tx packet consumes too many " |
1243 | "DMA segments, dropping...\n" , |
1244 | device_xname(sc->sc_dev)); |
1245 | IFQ_DEQUEUE(&ifp->if_snd, m0); |
1246 | m_freem(m0); |
1247 | continue; |
1248 | } |
1249 | /* |
1250 | * Short on resources, just stop for now. |
1251 | */ |
1252 | DPRINTF(DGE_DEBUG_TX, |
1253 | ("%s: TX: dmamap load failed: %d\n" , |
1254 | device_xname(sc->sc_dev), error)); |
1255 | break; |
1256 | } |
1257 | |
1258 | /* |
1259 | * Ensure we have enough descriptors free to describe |
1260 | * the packet. Note, we always reserve one descriptor |
1261 | * at the end of the ring due to the semantics of the |
1262 | * TDT register, plus one more in the event we need |
1263 | * to re-load checksum offload context. |
1264 | */ |
1265 | if (dmamap->dm_nsegs > (sc->sc_txfree - 2)) { |
1266 | /* |
1267 | * Not enough free descriptors to transmit this |
1268 | * packet. We haven't committed anything yet, |
1269 | * so just unload the DMA map, put the packet |
1270 | * pack on the queue, and punt. Notify the upper |
1271 | * layer that there are no more slots left. |
1272 | */ |
1273 | DPRINTF(DGE_DEBUG_TX, |
1274 | ("%s: TX: need %d descriptors, have %d\n" , |
1275 | device_xname(sc->sc_dev), dmamap->dm_nsegs, |
1276 | sc->sc_txfree - 1)); |
1277 | ifp->if_flags |= IFF_OACTIVE; |
1278 | bus_dmamap_unload(sc->sc_dmat, dmamap); |
1279 | DGE_EVCNT_INCR(&sc->sc_ev_txdstall); |
1280 | break; |
1281 | } |
1282 | |
1283 | IFQ_DEQUEUE(&ifp->if_snd, m0); |
1284 | |
1285 | /* |
1286 | * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. |
1287 | */ |
1288 | |
1289 | /* Sync the DMA map. */ |
1290 | bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, |
1291 | BUS_DMASYNC_PREWRITE); |
1292 | |
1293 | DPRINTF(DGE_DEBUG_TX, |
1294 | ("%s: TX: packet has %d DMA segments\n" , |
1295 | device_xname(sc->sc_dev), dmamap->dm_nsegs)); |
1296 | |
1297 | DGE_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); |
1298 | |
1299 | /* |
1300 | * Store a pointer to the packet so that we can free it |
1301 | * later. |
1302 | * |
1303 | * Initially, we consider the number of descriptors the |
1304 | * packet uses the number of DMA segments. This may be |
1305 | * incremented by 1 if we do checksum offload (a descriptor |
1306 | * is used to set the checksum context). |
1307 | */ |
1308 | txs->txs_mbuf = m0; |
1309 | txs->txs_firstdesc = sc->sc_txnext; |
1310 | txs->txs_ndesc = dmamap->dm_nsegs; |
1311 | |
1312 | /* |
1313 | * Set up checksum offload parameters for |
1314 | * this packet. |
1315 | */ |
1316 | if (m0->m_pkthdr.csum_flags & |
1317 | (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { |
1318 | if (dge_tx_cksum(sc, txs, &cksumfields) != 0) { |
1319 | /* Error message already displayed. */ |
1320 | bus_dmamap_unload(sc->sc_dmat, dmamap); |
1321 | continue; |
1322 | } |
1323 | } else { |
1324 | cksumfields = 0; |
1325 | } |
1326 | |
1327 | cksumcmd = TDESC_DCMD_IDE | TDESC_DTYP_DATA; |
1328 | |
1329 | /* |
1330 | * Initialize the transmit descriptor. |
1331 | */ |
1332 | for (nexttx = sc->sc_txnext, seg = 0; |
1333 | seg < dmamap->dm_nsegs; |
1334 | seg++, nexttx = DGE_NEXTTX(nexttx)) { |
1335 | /* |
1336 | * Note: we currently only use 32-bit DMA |
1337 | * addresses. |
1338 | */ |
1339 | sc->sc_txdescs[nexttx].dt_baddrh = 0; |
1340 | sc->sc_txdescs[nexttx].dt_baddrl = |
1341 | htole32(dmamap->dm_segs[seg].ds_addr); |
1342 | sc->sc_txdescs[nexttx].dt_ctl = |
1343 | htole32(cksumcmd | dmamap->dm_segs[seg].ds_len); |
1344 | sc->sc_txdescs[nexttx].dt_status = 0; |
1345 | sc->sc_txdescs[nexttx].dt_popts = cksumfields; |
1346 | sc->sc_txdescs[nexttx].dt_vlan = 0; |
1347 | lasttx = nexttx; |
1348 | |
1349 | DPRINTF(DGE_DEBUG_TX, |
1350 | ("%s: TX: desc %d: low 0x%08lx, len 0x%04lx\n" , |
1351 | device_xname(sc->sc_dev), nexttx, |
1352 | (unsigned long)le32toh(dmamap->dm_segs[seg].ds_addr), |
1353 | (unsigned long)le32toh(dmamap->dm_segs[seg].ds_len))); |
1354 | } |
1355 | |
1356 | KASSERT(lasttx != -1); |
1357 | |
1358 | /* |
1359 | * Set up the command byte on the last descriptor of |
1360 | * the packet. If we're in the interrupt delay window, |
1361 | * delay the interrupt. |
1362 | */ |
1363 | sc->sc_txdescs[lasttx].dt_ctl |= |
1364 | htole32(TDESC_DCMD_EOP | TDESC_DCMD_RS); |
1365 | |
1366 | txs->txs_lastdesc = lasttx; |
1367 | |
1368 | DPRINTF(DGE_DEBUG_TX, |
1369 | ("%s: TX: desc %d: cmdlen 0x%08x\n" , device_xname(sc->sc_dev), |
1370 | lasttx, le32toh(sc->sc_txdescs[lasttx].dt_ctl))); |
1371 | |
1372 | /* Sync the descriptors we're using. */ |
1373 | DGE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, |
1374 | BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
1375 | |
1376 | /* Give the packet to the chip. */ |
1377 | CSR_WRITE(sc, DGE_TDT, nexttx); |
1378 | |
1379 | DPRINTF(DGE_DEBUG_TX, |
1380 | ("%s: TX: TDT -> %d\n" , device_xname(sc->sc_dev), nexttx)); |
1381 | |
1382 | DPRINTF(DGE_DEBUG_TX, |
1383 | ("%s: TX: finished transmitting packet, job %d\n" , |
1384 | device_xname(sc->sc_dev), sc->sc_txsnext)); |
1385 | |
1386 | /* Advance the tx pointer. */ |
1387 | sc->sc_txfree -= txs->txs_ndesc; |
1388 | sc->sc_txnext = nexttx; |
1389 | |
1390 | sc->sc_txsfree--; |
1391 | sc->sc_txsnext = DGE_NEXTTXS(sc->sc_txsnext); |
1392 | |
1393 | /* Pass the packet to any BPF listeners. */ |
1394 | bpf_mtap(ifp, m0); |
1395 | } |
1396 | |
1397 | if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { |
1398 | /* No more slots; notify upper layer. */ |
1399 | ifp->if_flags |= IFF_OACTIVE; |
1400 | } |
1401 | |
1402 | if (sc->sc_txfree != ofree) { |
1403 | /* Set a watchdog timer in case the chip flakes out. */ |
1404 | ifp->if_timer = 5; |
1405 | } |
1406 | } |
1407 | |
1408 | /* |
1409 | * dge_watchdog: [ifnet interface function] |
1410 | * |
1411 | * Watchdog timer handler. |
1412 | */ |
1413 | static void |
1414 | dge_watchdog(struct ifnet *ifp) |
1415 | { |
1416 | struct dge_softc *sc = ifp->if_softc; |
1417 | |
1418 | /* |
1419 | * Since we're using delayed interrupts, sweep up |
1420 | * before we report an error. |
1421 | */ |
1422 | dge_txintr(sc); |
1423 | |
1424 | if (sc->sc_txfree != DGE_NTXDESC) { |
1425 | printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n" , |
1426 | device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree, |
1427 | sc->sc_txnext); |
1428 | ifp->if_oerrors++; |
1429 | |
1430 | /* Reset the interface. */ |
1431 | (void) dge_init(ifp); |
1432 | } |
1433 | |
1434 | /* Try to get more packets going. */ |
1435 | dge_start(ifp); |
1436 | } |
1437 | |
1438 | /* |
1439 | * dge_ioctl: [ifnet interface function] |
1440 | * |
1441 | * Handle control requests from the operator. |
1442 | */ |
1443 | static int |
1444 | dge_ioctl(struct ifnet *ifp, u_long cmd, void *data) |
1445 | { |
1446 | struct dge_softc *sc = ifp->if_softc; |
1447 | struct ifreq *ifr = (struct ifreq *) data; |
1448 | pcireg_t preg; |
1449 | int s, error, mmrbc; |
1450 | |
1451 | s = splnet(); |
1452 | |
1453 | switch (cmd) { |
1454 | case SIOCSIFMEDIA: |
1455 | case SIOCGIFMEDIA: |
1456 | error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); |
1457 | break; |
1458 | |
1459 | case SIOCSIFMTU: |
1460 | if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > DGE_MAX_MTU) |
1461 | error = EINVAL; |
1462 | else if ((error = ifioctl_common(ifp, cmd, data)) != ENETRESET) |
1463 | break; |
1464 | else if (ifp->if_flags & IFF_UP) |
1465 | error = (*ifp->if_init)(ifp); |
1466 | else |
1467 | error = 0; |
1468 | break; |
1469 | |
1470 | case SIOCSIFFLAGS: |
1471 | if ((error = ifioctl_common(ifp, cmd, data)) != 0) |
1472 | break; |
1473 | /* extract link flags */ |
1474 | if ((ifp->if_flags & IFF_LINK0) == 0 && |
1475 | (ifp->if_flags & IFF_LINK1) == 0) |
1476 | mmrbc = PCIX_MMRBC_512; |
1477 | else if ((ifp->if_flags & IFF_LINK0) == 0 && |
1478 | (ifp->if_flags & IFF_LINK1) != 0) |
1479 | mmrbc = PCIX_MMRBC_1024; |
1480 | else if ((ifp->if_flags & IFF_LINK0) != 0 && |
1481 | (ifp->if_flags & IFF_LINK1) == 0) |
1482 | mmrbc = PCIX_MMRBC_2048; |
1483 | else |
1484 | mmrbc = PCIX_MMRBC_4096; |
1485 | if (mmrbc != sc->sc_mmrbc) { |
1486 | preg = pci_conf_read(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD); |
1487 | preg &= ~PCIX_MMRBC_MSK; |
1488 | preg |= mmrbc; |
1489 | pci_conf_write(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD, preg); |
1490 | sc->sc_mmrbc = mmrbc; |
1491 | } |
1492 | /* FALLTHROUGH */ |
1493 | default: |
1494 | if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) |
1495 | break; |
1496 | |
1497 | error = 0; |
1498 | |
1499 | if (cmd == SIOCSIFCAP) |
1500 | error = (*ifp->if_init)(ifp); |
1501 | else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) |
1502 | ; |
1503 | else if (ifp->if_flags & IFF_RUNNING) { |
1504 | /* |
1505 | * Multicast list has changed; set the hardware filter |
1506 | * accordingly. |
1507 | */ |
1508 | dge_set_filter(sc); |
1509 | } |
1510 | break; |
1511 | } |
1512 | |
1513 | /* Try to get more packets going. */ |
1514 | dge_start(ifp); |
1515 | |
1516 | splx(s); |
1517 | return (error); |
1518 | } |
1519 | |
1520 | /* |
1521 | * dge_intr: |
1522 | * |
1523 | * Interrupt service routine. |
1524 | */ |
1525 | static int |
1526 | dge_intr(void *arg) |
1527 | { |
1528 | struct dge_softc *sc = arg; |
1529 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; |
1530 | uint32_t icr; |
1531 | int wantinit, handled = 0; |
1532 | |
1533 | for (wantinit = 0; wantinit == 0;) { |
1534 | icr = CSR_READ(sc, DGE_ICR); |
1535 | if ((icr & sc->sc_icr) == 0) |
1536 | break; |
1537 | |
1538 | rnd_add_uint32(&sc->rnd_source, icr); |
1539 | |
1540 | handled = 1; |
1541 | |
1542 | #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) |
1543 | if (icr & (ICR_RXDMT0|ICR_RXT0)) { |
1544 | DPRINTF(DGE_DEBUG_RX, |
1545 | ("%s: RX: got Rx intr 0x%08x\n" , |
1546 | device_xname(sc->sc_dev), |
1547 | icr & (ICR_RXDMT0|ICR_RXT0))); |
1548 | DGE_EVCNT_INCR(&sc->sc_ev_rxintr); |
1549 | } |
1550 | #endif |
1551 | dge_rxintr(sc); |
1552 | |
1553 | #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) |
1554 | if (icr & ICR_TXDW) { |
1555 | DPRINTF(DGE_DEBUG_TX, |
1556 | ("%s: TX: got TXDW interrupt\n" , |
1557 | device_xname(sc->sc_dev))); |
1558 | DGE_EVCNT_INCR(&sc->sc_ev_txdw); |
1559 | } |
1560 | if (icr & ICR_TXQE) |
1561 | DGE_EVCNT_INCR(&sc->sc_ev_txqe); |
1562 | #endif |
1563 | dge_txintr(sc); |
1564 | |
1565 | if (icr & (ICR_LSC|ICR_RXSEQ)) { |
1566 | DGE_EVCNT_INCR(&sc->sc_ev_linkintr); |
1567 | dge_linkintr(sc, icr); |
1568 | } |
1569 | |
1570 | if (icr & ICR_RXO) { |
1571 | printf("%s: Receive overrun\n" , device_xname(sc->sc_dev)); |
1572 | wantinit = 1; |
1573 | } |
1574 | } |
1575 | |
1576 | if (handled) { |
1577 | if (wantinit) |
1578 | dge_init(ifp); |
1579 | |
1580 | /* Try to get more packets going. */ |
1581 | dge_start(ifp); |
1582 | } |
1583 | |
1584 | return (handled); |
1585 | } |
1586 | |
1587 | /* |
1588 | * dge_txintr: |
1589 | * |
1590 | * Helper; handle transmit interrupts. |
1591 | */ |
1592 | static void |
1593 | dge_txintr(struct dge_softc *sc) |
1594 | { |
1595 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; |
1596 | struct dge_txsoft *txs; |
1597 | uint8_t status; |
1598 | int i; |
1599 | |
1600 | ifp->if_flags &= ~IFF_OACTIVE; |
1601 | |
1602 | /* |
1603 | * Go through the Tx list and free mbufs for those |
1604 | * frames which have been transmitted. |
1605 | */ |
1606 | for (i = sc->sc_txsdirty; sc->sc_txsfree != DGE_TXQUEUELEN; |
1607 | i = DGE_NEXTTXS(i), sc->sc_txsfree++) { |
1608 | txs = &sc->sc_txsoft[i]; |
1609 | |
1610 | DPRINTF(DGE_DEBUG_TX, |
1611 | ("%s: TX: checking job %d\n" , device_xname(sc->sc_dev), i)); |
1612 | |
1613 | DGE_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, |
1614 | BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); |
1615 | |
1616 | status = |
1617 | sc->sc_txdescs[txs->txs_lastdesc].dt_status; |
1618 | if ((status & TDESC_STA_DD) == 0) { |
1619 | DGE_CDTXSYNC(sc, txs->txs_lastdesc, 1, |
1620 | BUS_DMASYNC_PREREAD); |
1621 | break; |
1622 | } |
1623 | |
1624 | DPRINTF(DGE_DEBUG_TX, |
1625 | ("%s: TX: job %d done: descs %d..%d\n" , |
1626 | device_xname(sc->sc_dev), i, txs->txs_firstdesc, |
1627 | txs->txs_lastdesc)); |
1628 | |
1629 | ifp->if_opackets++; |
1630 | sc->sc_txfree += txs->txs_ndesc; |
1631 | bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, |
1632 | 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); |
1633 | bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); |
1634 | m_freem(txs->txs_mbuf); |
1635 | txs->txs_mbuf = NULL; |
1636 | } |
1637 | |
1638 | /* Update the dirty transmit buffer pointer. */ |
1639 | sc->sc_txsdirty = i; |
1640 | DPRINTF(DGE_DEBUG_TX, |
1641 | ("%s: TX: txsdirty -> %d\n" , device_xname(sc->sc_dev), i)); |
1642 | |
1643 | /* |
1644 | * If there are no more pending transmissions, cancel the watchdog |
1645 | * timer. |
1646 | */ |
1647 | if (sc->sc_txsfree == DGE_TXQUEUELEN) |
1648 | ifp->if_timer = 0; |
1649 | } |
1650 | |
1651 | /* |
1652 | * dge_rxintr: |
1653 | * |
1654 | * Helper; handle receive interrupts. |
1655 | */ |
1656 | static void |
1657 | dge_rxintr(struct dge_softc *sc) |
1658 | { |
1659 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; |
1660 | struct dge_rxsoft *rxs; |
1661 | struct mbuf *m; |
1662 | int i, len; |
1663 | uint8_t status, errors; |
1664 | |
1665 | for (i = sc->sc_rxptr;; i = DGE_NEXTRX(i)) { |
1666 | rxs = &sc->sc_rxsoft[i]; |
1667 | |
1668 | DPRINTF(DGE_DEBUG_RX, |
1669 | ("%s: RX: checking descriptor %d\n" , |
1670 | device_xname(sc->sc_dev), i)); |
1671 | |
1672 | DGE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); |
1673 | |
1674 | status = sc->sc_rxdescs[i].dr_status; |
1675 | errors = sc->sc_rxdescs[i].dr_errors; |
1676 | len = le16toh(sc->sc_rxdescs[i].dr_len); |
1677 | |
1678 | if ((status & RDESC_STS_DD) == 0) { |
1679 | /* |
1680 | * We have processed all of the receive descriptors. |
1681 | */ |
1682 | DGE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); |
1683 | break; |
1684 | } |
1685 | |
1686 | if (__predict_false(sc->sc_rxdiscard)) { |
1687 | DPRINTF(DGE_DEBUG_RX, |
1688 | ("%s: RX: discarding contents of descriptor %d\n" , |
1689 | device_xname(sc->sc_dev), i)); |
1690 | DGE_INIT_RXDESC(sc, i); |
1691 | if (status & RDESC_STS_EOP) { |
1692 | /* Reset our state. */ |
1693 | DPRINTF(DGE_DEBUG_RX, |
1694 | ("%s: RX: resetting rxdiscard -> 0\n" , |
1695 | device_xname(sc->sc_dev))); |
1696 | sc->sc_rxdiscard = 0; |
1697 | } |
1698 | continue; |
1699 | } |
1700 | |
1701 | bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, |
1702 | rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); |
1703 | |
1704 | m = rxs->rxs_mbuf; |
1705 | |
1706 | /* |
1707 | * Add a new receive buffer to the ring. |
1708 | */ |
1709 | if (dge_add_rxbuf(sc, i) != 0) { |
1710 | /* |
1711 | * Failed, throw away what we've done so |
1712 | * far, and discard the rest of the packet. |
1713 | */ |
1714 | ifp->if_ierrors++; |
1715 | bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, |
1716 | rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); |
1717 | DGE_INIT_RXDESC(sc, i); |
1718 | if ((status & RDESC_STS_EOP) == 0) |
1719 | sc->sc_rxdiscard = 1; |
1720 | if (sc->sc_rxhead != NULL) |
1721 | m_freem(sc->sc_rxhead); |
1722 | DGE_RXCHAIN_RESET(sc); |
1723 | DPRINTF(DGE_DEBUG_RX, |
1724 | ("%s: RX: Rx buffer allocation failed, " |
1725 | "dropping packet%s\n" , device_xname(sc->sc_dev), |
1726 | sc->sc_rxdiscard ? " (discard)" : "" )); |
1727 | continue; |
1728 | } |
1729 | DGE_INIT_RXDESC(sc, DGE_PREVRX(i)); /* Write the descriptor */ |
1730 | |
1731 | DGE_RXCHAIN_LINK(sc, m); |
1732 | |
1733 | m->m_len = len; |
1734 | |
1735 | DPRINTF(DGE_DEBUG_RX, |
1736 | ("%s: RX: buffer at %p len %d\n" , |
1737 | device_xname(sc->sc_dev), m->m_data, len)); |
1738 | |
1739 | /* |
1740 | * If this is not the end of the packet, keep |
1741 | * looking. |
1742 | */ |
1743 | if ((status & RDESC_STS_EOP) == 0) { |
1744 | sc->sc_rxlen += len; |
1745 | DPRINTF(DGE_DEBUG_RX, |
1746 | ("%s: RX: not yet EOP, rxlen -> %d\n" , |
1747 | device_xname(sc->sc_dev), sc->sc_rxlen)); |
1748 | continue; |
1749 | } |
1750 | |
1751 | /* |
1752 | * Okay, we have the entire packet now... |
1753 | */ |
1754 | *sc->sc_rxtailp = NULL; |
1755 | m = sc->sc_rxhead; |
1756 | len += sc->sc_rxlen; |
1757 | |
1758 | DGE_RXCHAIN_RESET(sc); |
1759 | |
1760 | DPRINTF(DGE_DEBUG_RX, |
1761 | ("%s: RX: have entire packet, len -> %d\n" , |
1762 | device_xname(sc->sc_dev), len)); |
1763 | |
1764 | /* |
1765 | * If an error occurred, update stats and drop the packet. |
1766 | */ |
1767 | if (errors & |
1768 | (RDESC_ERR_CE|RDESC_ERR_SE|RDESC_ERR_P|RDESC_ERR_RXE)) { |
1769 | ifp->if_ierrors++; |
1770 | if (errors & RDESC_ERR_SE) |
1771 | printf("%s: symbol error\n" , |
1772 | device_xname(sc->sc_dev)); |
1773 | else if (errors & RDESC_ERR_P) |
1774 | printf("%s: parity error\n" , |
1775 | device_xname(sc->sc_dev)); |
1776 | else if (errors & RDESC_ERR_CE) |
1777 | printf("%s: CRC error\n" , |
1778 | device_xname(sc->sc_dev)); |
1779 | m_freem(m); |
1780 | continue; |
1781 | } |
1782 | |
1783 | /* |
1784 | * No errors. Receive the packet. |
1785 | */ |
1786 | m_set_rcvif(m, ifp); |
1787 | m->m_pkthdr.len = len; |
1788 | |
1789 | /* |
1790 | * Set up checksum info for this packet. |
1791 | */ |
1792 | if (status & RDESC_STS_IPCS) { |
1793 | DGE_EVCNT_INCR(&sc->sc_ev_rxipsum); |
1794 | m->m_pkthdr.csum_flags |= M_CSUM_IPv4; |
1795 | if (errors & RDESC_ERR_IPE) |
1796 | m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; |
1797 | } |
1798 | if (status & RDESC_STS_TCPCS) { |
1799 | /* |
1800 | * Note: we don't know if this was TCP or UDP, |
1801 | * so we just set both bits, and expect the |
1802 | * upper layers to deal. |
1803 | */ |
1804 | DGE_EVCNT_INCR(&sc->sc_ev_rxtusum); |
1805 | m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; |
1806 | if (errors & RDESC_ERR_TCPE) |
1807 | m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; |
1808 | } |
1809 | |
1810 | ifp->if_ipackets++; |
1811 | |
1812 | /* Pass this up to any BPF listeners. */ |
1813 | bpf_mtap(ifp, m); |
1814 | |
1815 | /* Pass it on. */ |
1816 | if_percpuq_enqueue(ifp->if_percpuq, m); |
1817 | } |
1818 | |
1819 | /* Update the receive pointer. */ |
1820 | sc->sc_rxptr = i; |
1821 | |
1822 | DPRINTF(DGE_DEBUG_RX, |
1823 | ("%s: RX: rxptr -> %d\n" , device_xname(sc->sc_dev), i)); |
1824 | } |
1825 | |
1826 | /* |
1827 | * dge_linkintr: |
1828 | * |
1829 | * Helper; handle link interrupts. |
1830 | */ |
1831 | static void |
1832 | dge_linkintr(struct dge_softc *sc, uint32_t icr) |
1833 | { |
1834 | uint32_t status; |
1835 | |
1836 | if (icr & ICR_LSC) { |
1837 | status = CSR_READ(sc, DGE_STATUS); |
1838 | if (status & STATUS_LINKUP) { |
1839 | DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> up\n" , |
1840 | device_xname(sc->sc_dev))); |
1841 | } else { |
1842 | DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> down\n" , |
1843 | device_xname(sc->sc_dev))); |
1844 | } |
1845 | } else if (icr & ICR_RXSEQ) { |
1846 | DPRINTF(DGE_DEBUG_LINK, |
1847 | ("%s: LINK: Receive sequence error\n" , |
1848 | device_xname(sc->sc_dev))); |
1849 | } |
1850 | /* XXX - fix errata */ |
1851 | } |
1852 | |
1853 | /* |
1854 | * dge_reset: |
1855 | * |
1856 | * Reset the i82597 chip. |
1857 | */ |
1858 | static void |
1859 | dge_reset(struct dge_softc *sc) |
1860 | { |
1861 | int i; |
1862 | |
1863 | /* |
1864 | * Do a chip reset. |
1865 | */ |
1866 | CSR_WRITE(sc, DGE_CTRL0, CTRL0_RST | sc->sc_ctrl0); |
1867 | |
1868 | delay(10000); |
1869 | |
1870 | for (i = 0; i < 1000; i++) { |
1871 | if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0) |
1872 | break; |
1873 | delay(20); |
1874 | } |
1875 | |
1876 | if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) |
1877 | printf("%s: WARNING: reset failed to complete\n" , |
1878 | device_xname(sc->sc_dev)); |
1879 | /* |
1880 | * Reset the EEPROM logic. |
1881 | * This will cause the chip to reread its default values, |
1882 | * which doesn't happen otherwise (errata). |
1883 | */ |
1884 | CSR_WRITE(sc, DGE_CTRL1, CTRL1_EE_RST); |
1885 | delay(10000); |
1886 | } |
1887 | |
1888 | /* |
1889 | * dge_init: [ifnet interface function] |
1890 | * |
1891 | * Initialize the interface. Must be called at splnet(). |
1892 | */ |
1893 | static int |
1894 | dge_init(struct ifnet *ifp) |
1895 | { |
1896 | struct dge_softc *sc = ifp->if_softc; |
1897 | struct dge_rxsoft *rxs; |
1898 | int i, error = 0; |
1899 | uint32_t reg; |
1900 | |
1901 | /* |
1902 | * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. |
1903 | * There is a small but measurable benefit to avoiding the adjusment |
1904 | * of the descriptor so that the headers are aligned, for normal mtu, |
1905 | * on such platforms. One possibility is that the DMA itself is |
1906 | * slightly more efficient if the front of the entire packet (instead |
1907 | * of the front of the headers) is aligned. |
1908 | * |
1909 | * Note we must always set align_tweak to 0 if we are using |
1910 | * jumbo frames. |
1911 | */ |
1912 | #ifdef __NO_STRICT_ALIGNMENT |
1913 | sc->sc_align_tweak = 0; |
1914 | #else |
1915 | if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) |
1916 | sc->sc_align_tweak = 0; |
1917 | else |
1918 | sc->sc_align_tweak = 2; |
1919 | #endif /* __NO_STRICT_ALIGNMENT */ |
1920 | |
1921 | /* Cancel any pending I/O. */ |
1922 | dge_stop(ifp, 0); |
1923 | |
1924 | /* Reset the chip to a known state. */ |
1925 | dge_reset(sc); |
1926 | |
1927 | /* Initialize the transmit descriptor ring. */ |
1928 | memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); |
1929 | DGE_CDTXSYNC(sc, 0, DGE_NTXDESC, |
1930 | BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
1931 | sc->sc_txfree = DGE_NTXDESC; |
1932 | sc->sc_txnext = 0; |
1933 | |
1934 | sc->sc_txctx_ipcs = 0xffffffff; |
1935 | sc->sc_txctx_tucs = 0xffffffff; |
1936 | |
1937 | CSR_WRITE(sc, DGE_TDBAH, 0); |
1938 | CSR_WRITE(sc, DGE_TDBAL, DGE_CDTXADDR(sc, 0)); |
1939 | CSR_WRITE(sc, DGE_TDLEN, sizeof(sc->sc_txdescs)); |
1940 | CSR_WRITE(sc, DGE_TDH, 0); |
1941 | CSR_WRITE(sc, DGE_TDT, 0); |
1942 | CSR_WRITE(sc, DGE_TIDV, TIDV); |
1943 | |
1944 | #if 0 |
1945 | CSR_WRITE(sc, DGE_TXDCTL, TXDCTL_PTHRESH(0) | |
1946 | TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); |
1947 | #endif |
1948 | CSR_WRITE(sc, DGE_RXDCTL, |
1949 | RXDCTL_PTHRESH(RXDCTL_PTHRESH_VAL) | |
1950 | RXDCTL_HTHRESH(RXDCTL_HTHRESH_VAL) | |
1951 | RXDCTL_WTHRESH(RXDCTL_WTHRESH_VAL)); |
1952 | |
1953 | /* Initialize the transmit job descriptors. */ |
1954 | for (i = 0; i < DGE_TXQUEUELEN; i++) |
1955 | sc->sc_txsoft[i].txs_mbuf = NULL; |
1956 | sc->sc_txsfree = DGE_TXQUEUELEN; |
1957 | sc->sc_txsnext = 0; |
1958 | sc->sc_txsdirty = 0; |
1959 | |
1960 | /* |
1961 | * Initialize the receive descriptor and receive job |
1962 | * descriptor rings. |
1963 | */ |
1964 | CSR_WRITE(sc, DGE_RDBAH, 0); |
1965 | CSR_WRITE(sc, DGE_RDBAL, DGE_CDRXADDR(sc, 0)); |
1966 | CSR_WRITE(sc, DGE_RDLEN, sizeof(sc->sc_rxdescs)); |
1967 | CSR_WRITE(sc, DGE_RDH, DGE_RXSPACE); |
1968 | CSR_WRITE(sc, DGE_RDT, 0); |
1969 | CSR_WRITE(sc, DGE_RDTR, RDTR | 0x80000000); |
1970 | CSR_WRITE(sc, DGE_FCRTL, FCRTL | FCRTL_XONE); |
1971 | CSR_WRITE(sc, DGE_FCRTH, FCRTH); |
1972 | |
1973 | for (i = 0; i < DGE_NRXDESC; i++) { |
1974 | rxs = &sc->sc_rxsoft[i]; |
1975 | if (rxs->rxs_mbuf == NULL) { |
1976 | if ((error = dge_add_rxbuf(sc, i)) != 0) { |
1977 | printf("%s: unable to allocate or map rx " |
1978 | "buffer %d, error = %d\n" , |
1979 | device_xname(sc->sc_dev), i, error); |
1980 | /* |
1981 | * XXX Should attempt to run with fewer receive |
1982 | * XXX buffers instead of just failing. |
1983 | */ |
1984 | dge_rxdrain(sc); |
1985 | goto out; |
1986 | } |
1987 | } |
1988 | DGE_INIT_RXDESC(sc, i); |
1989 | } |
1990 | sc->sc_rxptr = DGE_RXSPACE; |
1991 | sc->sc_rxdiscard = 0; |
1992 | DGE_RXCHAIN_RESET(sc); |
1993 | |
1994 | if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) { |
1995 | sc->sc_ctrl0 |= CTRL0_JFE; |
1996 | CSR_WRITE(sc, DGE_MFS, ETHER_MAX_LEN_JUMBO << 16); |
1997 | } |
1998 | |
1999 | /* Write the control registers. */ |
2000 | CSR_WRITE(sc, DGE_CTRL0, sc->sc_ctrl0); |
2001 | |
2002 | /* |
2003 | * Set up checksum offload parameters. |
2004 | */ |
2005 | reg = CSR_READ(sc, DGE_RXCSUM); |
2006 | if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) |
2007 | reg |= RXCSUM_IPOFL; |
2008 | else |
2009 | reg &= ~RXCSUM_IPOFL; |
2010 | if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) |
2011 | reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; |
2012 | else { |
2013 | reg &= ~RXCSUM_TUOFL; |
2014 | if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) |
2015 | reg &= ~RXCSUM_IPOFL; |
2016 | } |
2017 | CSR_WRITE(sc, DGE_RXCSUM, reg); |
2018 | |
2019 | /* |
2020 | * Set up the interrupt registers. |
2021 | */ |
2022 | CSR_WRITE(sc, DGE_IMC, 0xffffffffU); |
2023 | sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | |
2024 | ICR_RXO | ICR_RXT0; |
2025 | |
2026 | CSR_WRITE(sc, DGE_IMS, sc->sc_icr); |
2027 | |
2028 | /* |
2029 | * Set up the transmit control register. |
2030 | */ |
2031 | sc->sc_tctl = TCTL_TCE|TCTL_TPDE|TCTL_TXEN; |
2032 | CSR_WRITE(sc, DGE_TCTL, sc->sc_tctl); |
2033 | |
2034 | /* |
2035 | * Set up the receive control register; we actually program |
2036 | * the register when we set the receive filter. Use multicast |
2037 | * address offset type 0. |
2038 | */ |
2039 | sc->sc_mchash_type = 0; |
2040 | |
2041 | sc->sc_rctl = RCTL_RXEN | RCTL_RDMTS_12 | RCTL_RPDA_MC | |
2042 | RCTL_CFF | RCTL_SECRC | RCTL_MO(sc->sc_mchash_type); |
2043 | |
2044 | #ifdef DGE_OFFBYONE_RXBUG |
2045 | sc->sc_rctl |= RCTL_BSIZE_16k; |
2046 | #else |
2047 | switch(MCLBYTES) { |
2048 | case 2048: |
2049 | sc->sc_rctl |= RCTL_BSIZE_2k; |
2050 | break; |
2051 | case 4096: |
2052 | sc->sc_rctl |= RCTL_BSIZE_4k; |
2053 | break; |
2054 | case 8192: |
2055 | sc->sc_rctl |= RCTL_BSIZE_8k; |
2056 | break; |
2057 | case 16384: |
2058 | sc->sc_rctl |= RCTL_BSIZE_16k; |
2059 | break; |
2060 | default: |
2061 | panic("dge_init: MCLBYTES %d unsupported" , MCLBYTES); |
2062 | } |
2063 | #endif |
2064 | |
2065 | /* Set the receive filter. */ |
2066 | /* Also sets RCTL */ |
2067 | dge_set_filter(sc); |
2068 | |
2069 | /* ...all done! */ |
2070 | ifp->if_flags |= IFF_RUNNING; |
2071 | ifp->if_flags &= ~IFF_OACTIVE; |
2072 | |
2073 | out: |
2074 | if (error) |
2075 | printf("%s: interface not running\n" , device_xname(sc->sc_dev)); |
2076 | return (error); |
2077 | } |
2078 | |
2079 | /* |
2080 | * dge_rxdrain: |
2081 | * |
2082 | * Drain the receive queue. |
2083 | */ |
2084 | static void |
2085 | dge_rxdrain(struct dge_softc *sc) |
2086 | { |
2087 | struct dge_rxsoft *rxs; |
2088 | int i; |
2089 | |
2090 | for (i = 0; i < DGE_NRXDESC; i++) { |
2091 | rxs = &sc->sc_rxsoft[i]; |
2092 | if (rxs->rxs_mbuf != NULL) { |
2093 | bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); |
2094 | m_freem(rxs->rxs_mbuf); |
2095 | rxs->rxs_mbuf = NULL; |
2096 | } |
2097 | } |
2098 | } |
2099 | |
2100 | /* |
2101 | * dge_stop: [ifnet interface function] |
2102 | * |
2103 | * Stop transmission on the interface. |
2104 | */ |
2105 | static void |
2106 | dge_stop(struct ifnet *ifp, int disable) |
2107 | { |
2108 | struct dge_softc *sc = ifp->if_softc; |
2109 | struct dge_txsoft *txs; |
2110 | int i; |
2111 | |
2112 | /* Stop the transmit and receive processes. */ |
2113 | CSR_WRITE(sc, DGE_TCTL, 0); |
2114 | CSR_WRITE(sc, DGE_RCTL, 0); |
2115 | |
2116 | /* Release any queued transmit buffers. */ |
2117 | for (i = 0; i < DGE_TXQUEUELEN; i++) { |
2118 | txs = &sc->sc_txsoft[i]; |
2119 | if (txs->txs_mbuf != NULL) { |
2120 | bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); |
2121 | m_freem(txs->txs_mbuf); |
2122 | txs->txs_mbuf = NULL; |
2123 | } |
2124 | } |
2125 | |
2126 | /* Mark the interface as down and cancel the watchdog timer. */ |
2127 | ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); |
2128 | ifp->if_timer = 0; |
2129 | |
2130 | if (disable) |
2131 | dge_rxdrain(sc); |
2132 | } |
2133 | |
2134 | /* |
2135 | * dge_add_rxbuf: |
2136 | * |
2137 | * Add a receive buffer to the indiciated descriptor. |
2138 | */ |
2139 | static int |
2140 | dge_add_rxbuf(struct dge_softc *sc, int idx) |
2141 | { |
2142 | struct dge_rxsoft *rxs = &sc->sc_rxsoft[idx]; |
2143 | struct mbuf *m; |
2144 | int error; |
2145 | #ifdef DGE_OFFBYONE_RXBUG |
2146 | void *buf; |
2147 | #endif |
2148 | |
2149 | MGETHDR(m, M_DONTWAIT, MT_DATA); |
2150 | if (m == NULL) |
2151 | return (ENOBUFS); |
2152 | |
2153 | #ifdef DGE_OFFBYONE_RXBUG |
2154 | if ((buf = dge_getbuf(sc)) == NULL) |
2155 | return ENOBUFS; |
2156 | |
2157 | m->m_len = m->m_pkthdr.len = DGE_BUFFER_SIZE; |
2158 | MEXTADD(m, buf, DGE_BUFFER_SIZE, M_DEVBUF, dge_freebuf, sc); |
2159 | m->m_flags |= M_EXT_RW; |
2160 | |
2161 | if (rxs->rxs_mbuf != NULL) |
2162 | bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); |
2163 | rxs->rxs_mbuf = m; |
2164 | |
2165 | error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, buf, |
2166 | DGE_BUFFER_SIZE, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT); |
2167 | #else |
2168 | MCLGET(m, M_DONTWAIT); |
2169 | if ((m->m_flags & M_EXT) == 0) { |
2170 | m_freem(m); |
2171 | return (ENOBUFS); |
2172 | } |
2173 | |
2174 | if (rxs->rxs_mbuf != NULL) |
2175 | bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); |
2176 | |
2177 | rxs->rxs_mbuf = m; |
2178 | |
2179 | m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; |
2180 | error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, |
2181 | BUS_DMA_READ|BUS_DMA_NOWAIT); |
2182 | #endif |
2183 | if (error) { |
2184 | printf("%s: unable to load rx DMA map %d, error = %d\n" , |
2185 | device_xname(sc->sc_dev), idx, error); |
2186 | panic("dge_add_rxbuf" ); /* XXX XXX XXX */ |
2187 | } |
2188 | bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, |
2189 | rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); |
2190 | |
2191 | return (0); |
2192 | } |
2193 | |
2194 | /* |
2195 | * dge_set_ral: |
2196 | * |
2197 | * Set an entry in the receive address list. |
2198 | */ |
2199 | static void |
2200 | dge_set_ral(struct dge_softc *sc, const uint8_t *enaddr, int idx) |
2201 | { |
2202 | uint32_t ral_lo, ral_hi; |
2203 | |
2204 | if (enaddr != NULL) { |
2205 | ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | |
2206 | (enaddr[3] << 24); |
2207 | ral_hi = enaddr[4] | (enaddr[5] << 8); |
2208 | ral_hi |= RAH_AV; |
2209 | } else { |
2210 | ral_lo = 0; |
2211 | ral_hi = 0; |
2212 | } |
2213 | CSR_WRITE(sc, RA_ADDR(DGE_RAL, idx), ral_lo); |
2214 | CSR_WRITE(sc, RA_ADDR(DGE_RAH, idx), ral_hi); |
2215 | } |
2216 | |
2217 | /* |
2218 | * dge_mchash: |
2219 | * |
2220 | * Compute the hash of the multicast address for the 4096-bit |
2221 | * multicast filter. |
2222 | */ |
2223 | static uint32_t |
2224 | dge_mchash(struct dge_softc *sc, const uint8_t *enaddr) |
2225 | { |
2226 | static const int lo_shift[4] = { 4, 3, 2, 0 }; |
2227 | static const int hi_shift[4] = { 4, 5, 6, 8 }; |
2228 | uint32_t hash; |
2229 | |
2230 | hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | |
2231 | (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); |
2232 | |
2233 | return (hash & 0xfff); |
2234 | } |
2235 | |
2236 | /* |
2237 | * dge_set_filter: |
2238 | * |
2239 | * Set up the receive filter. |
2240 | */ |
2241 | static void |
2242 | dge_set_filter(struct dge_softc *sc) |
2243 | { |
2244 | struct ethercom *ec = &sc->sc_ethercom; |
2245 | struct ifnet *ifp = &sc->sc_ethercom.ec_if; |
2246 | struct ether_multi *enm; |
2247 | struct ether_multistep step; |
2248 | uint32_t hash, reg, bit; |
2249 | int i; |
2250 | |
2251 | sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); |
2252 | |
2253 | if (ifp->if_flags & IFF_BROADCAST) |
2254 | sc->sc_rctl |= RCTL_BAM; |
2255 | if (ifp->if_flags & IFF_PROMISC) { |
2256 | sc->sc_rctl |= RCTL_UPE; |
2257 | goto allmulti; |
2258 | } |
2259 | |
2260 | /* |
2261 | * Set the station address in the first RAL slot, and |
2262 | * clear the remaining slots. |
2263 | */ |
2264 | dge_set_ral(sc, CLLADDR(ifp->if_sadl), 0); |
2265 | for (i = 1; i < RA_TABSIZE; i++) |
2266 | dge_set_ral(sc, NULL, i); |
2267 | |
2268 | /* Clear out the multicast table. */ |
2269 | for (i = 0; i < MC_TABSIZE; i++) |
2270 | CSR_WRITE(sc, DGE_MTA + (i << 2), 0); |
2271 | |
2272 | ETHER_FIRST_MULTI(step, ec, enm); |
2273 | while (enm != NULL) { |
2274 | if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { |
2275 | /* |
2276 | * We must listen to a range of multicast addresses. |
2277 | * For now, just accept all multicasts, rather than |
2278 | * trying to set only those filter bits needed to match |
2279 | * the range. (At this time, the only use of address |
2280 | * ranges is for IP multicast routing, for which the |
2281 | * range is big enough to require all bits set.) |
2282 | */ |
2283 | goto allmulti; |
2284 | } |
2285 | |
2286 | hash = dge_mchash(sc, enm->enm_addrlo); |
2287 | |
2288 | reg = (hash >> 5) & 0x7f; |
2289 | bit = hash & 0x1f; |
2290 | |
2291 | hash = CSR_READ(sc, DGE_MTA + (reg << 2)); |
2292 | hash |= 1U << bit; |
2293 | |
2294 | CSR_WRITE(sc, DGE_MTA + (reg << 2), hash); |
2295 | |
2296 | ETHER_NEXT_MULTI(step, enm); |
2297 | } |
2298 | |
2299 | ifp->if_flags &= ~IFF_ALLMULTI; |
2300 | goto setit; |
2301 | |
2302 | allmulti: |
2303 | ifp->if_flags |= IFF_ALLMULTI; |
2304 | sc->sc_rctl |= RCTL_MPE; |
2305 | |
2306 | setit: |
2307 | CSR_WRITE(sc, DGE_RCTL, sc->sc_rctl); |
2308 | } |
2309 | |
2310 | /* |
2311 | * Read in the EEPROM info and verify checksum. |
2312 | */ |
2313 | int |
2314 | dge_read_eeprom(struct dge_softc *sc) |
2315 | { |
2316 | uint16_t cksum; |
2317 | int i; |
2318 | |
2319 | cksum = 0; |
2320 | for (i = 0; i < EEPROM_SIZE; i++) { |
2321 | sc->sc_eeprom[i] = dge_eeprom_word(sc, i); |
2322 | cksum += sc->sc_eeprom[i]; |
2323 | } |
2324 | return cksum != EEPROM_CKSUM; |
2325 | } |
2326 | |
2327 | |
2328 | /* |
2329 | * Read a 16-bit word from address addr in the serial EEPROM. |
2330 | */ |
2331 | uint16_t |
2332 | dge_eeprom_word(struct dge_softc *sc, int addr) |
2333 | { |
2334 | uint32_t reg; |
2335 | uint16_t rval = 0; |
2336 | int i; |
2337 | |
2338 | reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK|EECD_DI|EECD_CS); |
2339 | |
2340 | /* Lower clock pulse (and data in to chip) */ |
2341 | CSR_WRITE(sc, DGE_EECD, reg); |
2342 | /* Select chip */ |
2343 | CSR_WRITE(sc, DGE_EECD, reg|EECD_CS); |
2344 | |
2345 | /* Send read command */ |
2346 | dge_eeprom_clockout(sc, 1); |
2347 | dge_eeprom_clockout(sc, 1); |
2348 | dge_eeprom_clockout(sc, 0); |
2349 | |
2350 | /* Send address */ |
2351 | for (i = 5; i >= 0; i--) |
2352 | dge_eeprom_clockout(sc, (addr >> i) & 1); |
2353 | |
2354 | /* Read data */ |
2355 | for (i = 0; i < 16; i++) { |
2356 | rval <<= 1; |
2357 | rval |= dge_eeprom_clockin(sc); |
2358 | } |
2359 | |
2360 | /* Deselect chip */ |
2361 | CSR_WRITE(sc, DGE_EECD, reg); |
2362 | |
2363 | return rval; |
2364 | } |
2365 | |
2366 | /* |
2367 | * Clock out a single bit to the EEPROM. |
2368 | */ |
2369 | void |
2370 | dge_eeprom_clockout(struct dge_softc *sc, int bit) |
2371 | { |
2372 | int reg; |
2373 | |
2374 | reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_SK); |
2375 | if (bit) |
2376 | reg |= EECD_DI; |
2377 | |
2378 | CSR_WRITE(sc, DGE_EECD, reg); |
2379 | delay(2); |
2380 | CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); |
2381 | delay(2); |
2382 | CSR_WRITE(sc, DGE_EECD, reg); |
2383 | delay(2); |
2384 | } |
2385 | |
2386 | /* |
2387 | * Clock in a single bit from EEPROM. |
2388 | */ |
2389 | int |
2390 | dge_eeprom_clockin(struct dge_softc *sc) |
2391 | { |
2392 | int reg, rv; |
2393 | |
2394 | reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_DO|EECD_SK); |
2395 | |
2396 | CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); /* Raise clock */ |
2397 | delay(2); |
2398 | rv = (CSR_READ(sc, DGE_EECD) & EECD_DO) != 0; /* Get bit */ |
2399 | CSR_WRITE(sc, DGE_EECD, reg); /* Lower clock */ |
2400 | delay(2); |
2401 | |
2402 | return rv; |
2403 | } |
2404 | |
2405 | static void |
2406 | dge_xgmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) |
2407 | { |
2408 | struct dge_softc *sc = ifp->if_softc; |
2409 | |
2410 | ifmr->ifm_status = IFM_AVALID; |
2411 | if (sc->sc_dgep->dgep_flags & DGEP_F_10G_SR ) { |
2412 | ifmr->ifm_active = IFM_ETHER|IFM_10G_SR; |
2413 | } else { |
2414 | ifmr->ifm_active = IFM_ETHER|IFM_10G_LR; |
2415 | } |
2416 | |
2417 | if (CSR_READ(sc, DGE_STATUS) & STATUS_LINKUP) |
2418 | ifmr->ifm_status |= IFM_ACTIVE; |
2419 | } |
2420 | |
2421 | static inline int |
2422 | phwait(struct dge_softc *sc, int p, int r, int d, int type) |
2423 | { |
2424 | int i, mdic; |
2425 | |
2426 | CSR_WRITE(sc, DGE_MDIO, |
2427 | MDIO_PHY(p) | MDIO_REG(r) | MDIO_DEV(d) | type | MDIO_CMD); |
2428 | for (i = 0; i < 10; i++) { |
2429 | delay(10); |
2430 | if (((mdic = CSR_READ(sc, DGE_MDIO)) & MDIO_CMD) == 0) |
2431 | break; |
2432 | } |
2433 | return mdic; |
2434 | } |
2435 | |
2436 | static void |
2437 | dge_xgmii_writereg(struct dge_softc *sc, int phy, int reg, int val) |
2438 | { |
2439 | int mdic; |
2440 | |
2441 | CSR_WRITE(sc, DGE_MDIRW, val); |
2442 | if (((mdic = phwait(sc, phy, reg, 1, MDIO_ADDR)) & MDIO_CMD)) { |
2443 | printf("%s: address cycle timeout; phy %d reg %d\n" , |
2444 | device_xname(sc->sc_dev), phy, reg); |
2445 | return; |
2446 | } |
2447 | if (((mdic = phwait(sc, phy, reg, 1, MDIO_WRITE)) & MDIO_CMD)) { |
2448 | printf("%s: write cycle timeout; phy %d reg %d\n" , |
2449 | device_xname(sc->sc_dev), phy, reg); |
2450 | return; |
2451 | } |
2452 | } |
2453 | |
2454 | static void |
2455 | dge_xgmii_reset(struct dge_softc *sc) |
2456 | { |
2457 | dge_xgmii_writereg(sc, 0, 0, BMCR_RESET); |
2458 | } |
2459 | |
2460 | static int |
2461 | dge_xgmii_mediachange(struct ifnet *ifp) |
2462 | { |
2463 | return 0; |
2464 | } |
2465 | |