1 | /* $NetBSD: miidevs.h,v 1.127 2015/08/14 01:26:38 knakahara Exp $ */ |
2 | |
3 | /* |
4 | * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. |
5 | * |
6 | * generated from: |
7 | * NetBSD: miidevs,v 1.124 2015/08/14 01:23:17 knakahara Exp |
8 | */ |
9 | |
10 | /*- |
11 | * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. |
12 | * All rights reserved. |
13 | * |
14 | * This code is derived from software contributed to The NetBSD Foundation |
15 | * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, |
16 | * NASA Ames Research Center. |
17 | * |
18 | * Redistribution and use in source and binary forms, with or without |
19 | * modification, are permitted provided that the following conditions |
20 | * are met: |
21 | * 1. Redistributions of source code must retain the above copyright |
22 | * notice, this list of conditions and the following disclaimer. |
23 | * 2. Redistributions in binary form must reproduce the above copyright |
24 | * notice, this list of conditions and the following disclaimer in the |
25 | * documentation and/or other materials provided with the distribution. |
26 | * |
27 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
28 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
29 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
30 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
31 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
32 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
33 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
34 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
35 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
36 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
37 | * POSSIBILITY OF SUCH DAMAGE. |
38 | */ |
39 | |
40 | /* |
41 | * List of known MII OUIs. |
42 | * For a complete list see http://standards.ieee.org/regauth/oui/ |
43 | * |
44 | * XXX Vendors do obviously not agree how OUIs (24 bit) are mapped |
45 | * to the 22 bits available in the id registers. |
46 | * IEEE 802.3u-1995, subclause 22.2.4.3.1, figure 22-12, depicts the right |
47 | * mapping; the bit positions are defined in IEEE 802-1990, figure 5.2. |
48 | * (There is a formal 802.3 interpretation, number 1-07/98 of July 09 1998, |
49 | * about this.) |
50 | * The MII_OUI() macro in "miivar.h" reflects this. |
51 | * If a vendor uses a different mapping, an "xx" prefixed OUI is defined here |
52 | * which is mangled accordingly to compensate. |
53 | */ |
54 | |
55 | /* |
56 | * Use "make -f Makefile.miidevs" to regenerate miidevs.h and miidevs_data.h |
57 | */ |
58 | |
59 | #define MII_OUI_AGERE 0x00053d /* Agere */ |
60 | #define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */ |
61 | #define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */ |
62 | #define MII_OUI_ATHEROS 0x001374 /* Atheros */ |
63 | #define MII_OUI_ATTANSIC 0x00c82e /* Attansic Technology */ |
64 | #define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */ |
65 | #define MII_OUI_BROADCOM2 0x000af7 /* Broadcom Corporation */ |
66 | #define MII_OUI_BROADCOM3 0x001be9 /* Broadcom Corporation */ |
67 | #define MII_OUI_CICADA 0x0003F1 /* Cicada Semiconductor */ |
68 | #define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */ |
69 | #define MII_OUI_ENABLESEMI 0x0010dd /* Enable Semiconductor */ |
70 | #define MII_OUI_ICPLUS 0x0090c3 /* IC Plus Corp. */ |
71 | #define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */ |
72 | #define MII_OUI_INTEL 0x00aa00 /* Intel */ |
73 | #define MII_OUI_JMICRON 0x00d831 /* JMicron */ |
74 | #define MII_OUI_LEVEL1 0x00207b /* Level 1 */ |
75 | #define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */ |
76 | #define MII_OUI_MICREL 0x0010a1 /* Micrel */ |
77 | #define MII_OUI_MYSON 0x00c0b4 /* Myson Technology */ |
78 | #define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */ |
79 | #define MII_OUI_PMCSIERRA 0x00e004 /* PMC-Sierra */ |
80 | #define MII_OUI_RDC 0x00d02d /* RDC Semiconductor */ |
81 | #define MII_OUI_REALTEK 0x00e04c /* RealTek */ |
82 | #define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */ |
83 | #define MII_OUI_SEEQ 0x00a07d /* Seeq */ |
84 | #define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */ |
85 | #define MII_OUI_SMSC 0x00800f /* SMSC */ |
86 | #define MII_OUI_TI 0x080028 /* Texas Instruments */ |
87 | #define MII_OUI_TSC 0x00c039 /* TDK Semiconductor */ |
88 | #define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */ |
89 | |
90 | /* Some Intel 82553's use an alternative OUI. */ |
91 | #define MII_OUI_xxINTEL 0x001f00 /* Intel */ |
92 | |
93 | /* Some VIA 6122's use an alternative OUI. */ |
94 | #define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor */ |
95 | |
96 | /* bad bitorder (bits "g" and "h" (= MSBs byte 1) lost) */ |
97 | #define MII_OUI_yyAMD 0x000058 /* Advanced Micro Devices */ |
98 | #define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */ |
99 | #define MII_OUI_xxBROADCOM_ALT1 0x0050ef /* Broadcom Corporation */ |
100 | #define MII_OUI_xxDAVICOM 0x000676 /* Davicom Semiconductor */ |
101 | #define MII_OUI_yyINTEL 0x005500 /* Intel */ |
102 | #define MII_OUI_xxMARVELL 0x000ac2 /* Marvell Semiconductor */ |
103 | #define MII_OUI_xxMYSON 0x00032d /* Myson Technology */ |
104 | #define MII_OUI_xxNATSEMI 0x1000e8 /* National Semiconductor */ |
105 | #define MII_OUI_xxQUALSEMI 0x00068a /* Quality Semiconductor */ |
106 | #define MII_OUI_xxTSC 0x00039c /* TDK Semiconductor */ |
107 | |
108 | /* bad byteorder (bits "q" and "r" (= LSBs byte 3) lost) */ |
109 | #define MII_OUI_xxLEVEL1 0x782000 /* Level 1 */ |
110 | #define MII_OUI_xxXAQTI 0xace000 /* XaQti Corp. */ |
111 | |
112 | /* Don't know what's going on here. */ |
113 | #define MII_OUI_xxPMCSIERRA 0x0009c0 /* PMC-Sierra */ |
114 | #define MII_OUI_xxPMCSIERRA2 0x009057 /* PMC-Sierra */ |
115 | |
116 | #define MII_OUI_xxREALTEK 0x000732 /* Realtek */ |
117 | #define MII_OUI_yyREALTEK 0x000004 /* Realtek */ |
118 | /* |
119 | * List of known models. Grouped by oui. |
120 | */ |
121 | |
122 | /* |
123 | * Agere PHYs |
124 | */ |
125 | #define MII_MODEL_AGERE_ET1011 0x0004 |
126 | #define MII_STR_AGERE_ET1011 "Agere ET1011 10/100/1000baseT PHY" |
127 | |
128 | /* Atheros PHYs */ |
129 | #define MII_MODEL_ATHEROS_F1 0x0001 |
130 | #define MII_STR_ATHEROS_F1 "F1 10/100/1000 PHY" |
131 | #define MII_MODEL_ATHEROS_F2 0x0002 |
132 | #define MII_STR_ATHEROS_F2 "F2 10/100 PHY" |
133 | |
134 | /* Attansic PHYs */ |
135 | #define MII_MODEL_ATTANSIC_L1 0x0001 |
136 | #define MII_STR_ATTANSIC_L1 "L1 10/100/1000 PHY" |
137 | #define MII_MODEL_ATTANSIC_L2 0x0002 |
138 | #define MII_STR_ATTANSIC_L2 "L2 10/100 PHY" |
139 | #define MII_MODEL_ATTANSIC_AR8021 0x0004 |
140 | #define MII_STR_ATTANSIC_AR8021 "Atheros AR8021 10/100/1000 PHY" |
141 | #define MII_MODEL_ATTANSIC_AR8035 0x0007 |
142 | #define MII_STR_ATTANSIC_AR8035 "Atheros AR8035 10/100/1000 PHY" |
143 | |
144 | /* Altima Communications PHYs */ |
145 | /* Don't know the model for ACXXX */ |
146 | #define MII_MODEL_ALTIMA_ACXXX 0x0001 |
147 | #define MII_STR_ALTIMA_ACXXX "ACXXX 10/100 media interface" |
148 | #define MII_MODEL_ALTIMA_AC101 0x0021 |
149 | #define MII_STR_ALTIMA_AC101 "AC101 10/100 media interface" |
150 | #define MII_MODEL_ALTIMA_AC101L 0x0012 |
151 | #define MII_STR_ALTIMA_AC101L "AC101L 10/100 media interface" |
152 | /* AMD Am79C87[45] have ALTIMA OUI */ |
153 | #define MII_MODEL_ALTIMA_Am79C875 0x0014 |
154 | #define MII_STR_ALTIMA_Am79C875 "Am79C875 10/100 media interface" |
155 | #define MII_MODEL_ALTIMA_Am79C874 0x0021 |
156 | #define MII_STR_ALTIMA_Am79C874 "Am79C874 10/100 media interface" |
157 | |
158 | /* Advanced Micro Devices PHYs */ |
159 | /* see Davicom DM9101 for Am79C873 */ |
160 | #define MII_MODEL_yyAMD_79C972_10T 0x0001 |
161 | #define MII_STR_yyAMD_79C972_10T "Am79C972 internal 10BASE-T interface" |
162 | #define MII_MODEL_yyAMD_79c973phy 0x0036 |
163 | #define MII_STR_yyAMD_79c973phy "Am79C973 internal 10/100 media interface" |
164 | #define MII_MODEL_yyAMD_79c901 0x0037 |
165 | #define MII_STR_yyAMD_79c901 "Am79C901 10BASE-T interface" |
166 | #define MII_MODEL_yyAMD_79c901home 0x0039 |
167 | #define MII_STR_yyAMD_79c901home "Am79C901 HomePNA 1.0 interface" |
168 | |
169 | /* Broadcom Corp. PHYs */ |
170 | #define MII_MODEL_xxBROADCOM_3C905B 0x0012 |
171 | #define MII_STR_xxBROADCOM_3C905B "Broadcom 3c905B internal PHY" |
172 | #define MII_MODEL_xxBROADCOM_3C905C 0x0017 |
173 | #define MII_STR_xxBROADCOM_3C905C "Broadcom 3c905C internal PHY" |
174 | #define MII_MODEL_xxBROADCOM_BCM5201 0x0021 |
175 | #define MII_STR_xxBROADCOM_BCM5201 "BCM5201 10/100 media interface" |
176 | #define MII_MODEL_xxBROADCOM_BCM5214 0x0028 |
177 | #define MII_STR_xxBROADCOM_BCM5214 "BCM5214 Quad 10/100 media interface" |
178 | #define MII_MODEL_xxBROADCOM_BCM5221 0x001e |
179 | #define MII_STR_xxBROADCOM_BCM5221 "BCM5221 10/100 media interface" |
180 | #define MII_MODEL_xxBROADCOM_BCM5222 0x0032 |
181 | #define MII_STR_xxBROADCOM_BCM5222 "BCM5222 Dual 10/100 media interface" |
182 | #define MII_MODEL_xxBROADCOM_BCM4401 0x0036 |
183 | #define MII_STR_xxBROADCOM_BCM4401 "BCM4401 10/100 media interface" |
184 | #define MII_MODEL_xxBROADCOM_BCM5365 0x0037 |
185 | #define MII_STR_xxBROADCOM_BCM5365 "BCM5365 10/100 5-port PHY switch" |
186 | #define MII_MODEL_BROADCOM_BCM5400 0x0004 |
187 | #define MII_STR_BROADCOM_BCM5400 "BCM5400 1000BASE-T media interface" |
188 | #define MII_MODEL_BROADCOM_BCM5401 0x0005 |
189 | #define MII_STR_BROADCOM_BCM5401 "BCM5401 1000BASE-T media interface" |
190 | #define MII_MODEL_BROADCOM_BCM5411 0x0007 |
191 | #define MII_STR_BROADCOM_BCM5411 "BCM5411 1000BASE-T media interface" |
192 | #define MII_MODEL_BROADCOM_BCM5464 0x000b |
193 | #define MII_STR_BROADCOM_BCM5464 "BCM5464 1000BASE-T media interface" |
194 | #define MII_MODEL_BROADCOM_BCM5461 0x000c |
195 | #define MII_STR_BROADCOM_BCM5461 "BCM5461 1000BASE-T media interface" |
196 | #define MII_MODEL_BROADCOM_BCM5462 0x000d |
197 | #define MII_STR_BROADCOM_BCM5462 "BCM5462 1000BASE-T media interface" |
198 | #define MII_MODEL_BROADCOM_BCM5421 0x000e |
199 | #define MII_STR_BROADCOM_BCM5421 "BCM5421 1000BASE-T media interface" |
200 | #define MII_MODEL_BROADCOM_BCM5752 0x0010 |
201 | #define MII_STR_BROADCOM_BCM5752 "BCM5752 1000BASE-T media interface" |
202 | #define MII_MODEL_BROADCOM_BCM5701 0x0011 |
203 | #define MII_STR_BROADCOM_BCM5701 "BCM5701 1000BASE-T media interface" |
204 | #define MII_MODEL_BROADCOM_BCM5706 0x0015 |
205 | #define MII_STR_BROADCOM_BCM5706 "BCM5706 1000BASE-T/SX media interface" |
206 | #define MII_MODEL_BROADCOM_BCM5703 0x0016 |
207 | #define MII_STR_BROADCOM_BCM5703 "BCM5703 1000BASE-T media interface" |
208 | #define MII_MODEL_BROADCOM_BCM5750 0x0018 |
209 | #define MII_STR_BROADCOM_BCM5750 "BCM5750 1000BASE-T media interface" |
210 | #define MII_MODEL_BROADCOM_BCM5704 0x0019 |
211 | #define MII_STR_BROADCOM_BCM5704 "BCM5704 1000BASE-T media interface" |
212 | #define MII_MODEL_BROADCOM_BCM5705 0x001a |
213 | #define MII_STR_BROADCOM_BCM5705 "BCM5705 1000BASE-T media interface" |
214 | #define MII_MODEL_BROADCOM_BCM54K2 0x002e |
215 | #define MII_STR_BROADCOM_BCM54K2 "BCM54K2 1000BASE-T media interface" |
216 | #define MII_MODEL_BROADCOM_BCM5714 0x0034 |
217 | #define MII_STR_BROADCOM_BCM5714 "BCM5714 1000BASE-T/X media interface" |
218 | #define MII_MODEL_BROADCOM_BCM5780 0x0035 |
219 | #define MII_STR_BROADCOM_BCM5780 "BCM5780 1000BASE-T/X media interface" |
220 | #define MII_MODEL_BROADCOM_BCM5708C 0x0036 |
221 | #define MII_STR_BROADCOM_BCM5708C "BCM5708C 1000BASE-T media interface" |
222 | #define MII_MODEL_BROADCOM2_BCM5325 0x0003 |
223 | #define MII_STR_BROADCOM2_BCM5325 "BCM5325 10/100 5-port PHY switch" |
224 | #define MII_MODEL_BROADCOM2_BCM5906 0x0004 |
225 | #define MII_STR_BROADCOM2_BCM5906 "BCM5906 10/100baseTX media interface" |
226 | #define MII_MODEL_BROADCOM2_BCM5481 0x000a |
227 | #define MII_STR_BROADCOM2_BCM5481 "BCM5481 1000BASE-T media interface" |
228 | #define MII_MODEL_BROADCOM2_BCM5482 0x000b |
229 | #define MII_STR_BROADCOM2_BCM5482 "BCM5482 1000BASE-T media interface" |
230 | #define MII_MODEL_BROADCOM2_BCM5755 0x000c |
231 | #define MII_STR_BROADCOM2_BCM5755 "BCM5755 1000BASE-T media interface" |
232 | #define MII_MODEL_BROADCOM2_BCM5756 0x000d |
233 | #define MII_STR_BROADCOM2_BCM5756 "BCM5756 1000BASE-T media interface XXX" |
234 | #define MII_MODEL_BROADCOM2_BCM5754 0x000e |
235 | #define MII_STR_BROADCOM2_BCM5754 "BCM5754/5787 1000BASE-T media interface" |
236 | #define MII_MODEL_BROADCOM2_BCM5708S 0x0015 |
237 | #define MII_STR_BROADCOM2_BCM5708S "BCM5708S 1000/2500baseSX PHY" |
238 | #define MII_MODEL_BROADCOM2_BCM5785 0x0016 |
239 | #define MII_STR_BROADCOM2_BCM5785 "BCM5785 1000BASE-T media interface" |
240 | #define MII_MODEL_BROADCOM2_BCM5709CAX 0x002c |
241 | #define MII_STR_BROADCOM2_BCM5709CAX "BCM5709CAX 10/100/1000baseT PHY" |
242 | #define MII_MODEL_BROADCOM2_BCM5722 0x002d |
243 | #define MII_STR_BROADCOM2_BCM5722 "BCM5722 1000BASE-T media interface" |
244 | #define MII_MODEL_BROADCOM2_BCM5784 0x003a |
245 | #define MII_STR_BROADCOM2_BCM5784 "BCM5784 10/100/1000baseT PHY" |
246 | #define MII_MODEL_BROADCOM2_BCM5709C 0x003c |
247 | #define MII_STR_BROADCOM2_BCM5709C "BCM5709 10/100/1000baseT PHY" |
248 | #define MII_MODEL_BROADCOM2_BCM5761 0x003d |
249 | #define MII_STR_BROADCOM2_BCM5761 "BCM5761 10/100/1000baseT PHY" |
250 | #define MII_MODEL_BROADCOM2_BCM5709S 0x003f |
251 | #define MII_STR_BROADCOM2_BCM5709S "BCM5709S 1000/2500baseSX PHY" |
252 | #define MII_MODEL_BROADCOM3_BCM57780 0x0019 |
253 | #define MII_STR_BROADCOM3_BCM57780 "BCM57780 1000BASE-T media interface" |
254 | #define MII_MODEL_BROADCOM3_BCM5717C 0x0020 |
255 | #define MII_STR_BROADCOM3_BCM5717C "BCM5717C 1000BASE-T media interface" |
256 | #define MII_MODEL_BROADCOM3_BCM5719C 0x0022 |
257 | #define MII_STR_BROADCOM3_BCM5719C "BCM5719C 1000BASE-T media interface" |
258 | #define MII_MODEL_BROADCOM3_BCM57765 0x0024 |
259 | #define MII_STR_BROADCOM3_BCM57765 "BCM57765 1000BASE-T media interface" |
260 | #define MII_MODEL_BROADCOM3_BCM5720C 0x0036 |
261 | #define MII_STR_BROADCOM3_BCM5720C "BCM5720C 1000BASE-T media interface" |
262 | #define MII_MODEL_xxBROADCOM_ALT1_BCM5906 0x0004 |
263 | #define MII_STR_xxBROADCOM_ALT1_BCM5906 "BCM5906 10/100baseTX media interface" |
264 | |
265 | /* Cicada Semiconductor PHYs (now owned by Vitesse?) */ |
266 | #define MII_MODEL_CICADA_CS8201 0x0001 |
267 | #define MII_STR_CICADA_CS8201 "Cicada CS8201 10/100/1000TX PHY" |
268 | #define MII_MODEL_CICADA_CS8204 0x0004 |
269 | #define MII_STR_CICADA_CS8204 "Cicada CS8204 10/100/1000TX PHY" |
270 | #define MII_MODEL_CICADA_VSC8211 0x000b |
271 | #define MII_STR_CICADA_VSC8211 "Cicada VSC8211 10/100/1000TX PHY" |
272 | #define MII_MODEL_CICADA_CS8201A 0x0020 |
273 | #define MII_STR_CICADA_CS8201A "Cicada CS8201 10/100/1000TX PHY" |
274 | #define MII_MODEL_CICADA_CS8201B 0x0021 |
275 | #define MII_STR_CICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY" |
276 | #define MII_MODEL_xxCICADA_VSC8221 0x0015 |
277 | #define MII_STR_xxCICADA_VSC8221 "Vitesse VSC8221 10/100/1000BASE-T PHY" |
278 | #define MII_MODEL_xxCICADA_VSC8244 0x002c |
279 | #define MII_STR_xxCICADA_VSC8244 "Vitesse VSC8244 Quad 10/100/1000BASE-T PHY" |
280 | #define MII_MODEL_xxCICADA_CS8201B 0x0021 |
281 | #define MII_STR_xxCICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY" |
282 | |
283 | /* Davicom Semiconductor PHYs */ |
284 | /* AMD Am79C873 seems to be a relabeled DM9101 */ |
285 | #define MII_MODEL_xxDAVICOM_DM9101 0x0000 |
286 | #define MII_STR_xxDAVICOM_DM9101 "DM9101 (AMD Am79C873) 10/100 media interface" |
287 | #define MII_MODEL_xxDAVICOM_DM9102 0x0004 |
288 | #define MII_STR_xxDAVICOM_DM9102 "DM9102 10/100 media interface" |
289 | |
290 | /* IC Plus Corp. PHYs */ |
291 | #define MII_MODEL_ICPLUS_IP100 0x0004 |
292 | #define MII_STR_ICPLUS_IP100 "IP100 10/100 PHY" |
293 | #define MII_MODEL_ICPLUS_IP101 0x0005 |
294 | #define MII_STR_ICPLUS_IP101 "IP101 10/100 PHY" |
295 | #define MII_MODEL_ICPLUS_IP1000A 0x0008 |
296 | #define MII_STR_ICPLUS_IP1000A "IP1000A 10/100/1000 PHY" |
297 | #define MII_MODEL_ICPLUS_IP1001 0x0019 |
298 | #define MII_STR_ICPLUS_IP1001 "IP1001 10/100/1000 PHY" |
299 | |
300 | /* Integrated Circuit Systems PHYs */ |
301 | #define MII_MODEL_ICS_1889 0x0001 |
302 | #define MII_STR_ICS_1889 "ICS1889 10/100 media interface" |
303 | #define MII_MODEL_ICS_1890 0x0002 |
304 | #define MII_STR_ICS_1890 "ICS1890 10/100 media interface" |
305 | #define MII_MODEL_ICS_1892 0x0003 |
306 | #define MII_STR_ICS_1892 "ICS1892 10/100 media interface" |
307 | #define MII_MODEL_ICS_1893 0x0004 |
308 | #define MII_STR_ICS_1893 "ICS1893 10/100 media interface" |
309 | |
310 | /* Intel PHYs */ |
311 | #define MII_MODEL_xxINTEL_I82553 0x0000 |
312 | #define MII_STR_xxINTEL_I82553 "i82553 10/100 media interface" |
313 | #define MII_MODEL_yyINTEL_I82555 0x0015 |
314 | #define MII_STR_yyINTEL_I82555 "i82555 10/100 media interface" |
315 | #define MII_MODEL_yyINTEL_I82562EH 0x0017 |
316 | #define MII_STR_yyINTEL_I82562EH "i82562EH HomePNA interface" |
317 | #define MII_MODEL_yyINTEL_I82562G 0x0031 |
318 | #define MII_STR_yyINTEL_I82562G "i82562G 10/100 media interface" |
319 | #define MII_MODEL_yyINTEL_I82562EM 0x0032 |
320 | #define MII_STR_yyINTEL_I82562EM "i82562EM 10/100 media interface" |
321 | #define MII_MODEL_yyINTEL_I82562ET 0x0033 |
322 | #define MII_STR_yyINTEL_I82562ET "i82562ET 10/100 media interface" |
323 | #define MII_MODEL_yyINTEL_I82553 0x0035 |
324 | #define MII_STR_yyINTEL_I82553 "i82553 10/100 media interface" |
325 | #define MII_MODEL_yyINTEL_I82566 0x0039 |
326 | #define MII_STR_yyINTEL_I82566 "i82566 10/100/1000 media interface" |
327 | #define MII_MODEL_INTEL_I82577 0x0005 |
328 | #define MII_STR_INTEL_I82577 "i82577 10/100/1000 media interface" |
329 | #define MII_MODEL_INTEL_I82579 0x0009 |
330 | #define MII_STR_INTEL_I82579 "i82579 10/100/1000 media interface" |
331 | #define MII_MODEL_INTEL_I217 0x000a |
332 | #define MII_STR_INTEL_I217 "i217 10/100/1000 media interface" |
333 | #define MII_MODEL_xxMARVELL_I210 0x0000 |
334 | #define MII_STR_xxMARVELL_I210 "I210 10/100/1000 media interface" |
335 | #define MII_MODEL_xxMARVELL_I82563 0x000a |
336 | #define MII_STR_xxMARVELL_I82563 "i82563 10/100/1000 media interface" |
337 | |
338 | #define MII_MODEL_yyINTEL_IGP01E1000 0x0038 |
339 | #define MII_STR_yyINTEL_IGP01E1000 "Intel IGP01E1000 Gigabit PHY" |
340 | |
341 | /* JMicron PHYs */ |
342 | #define MII_MODEL_JMICRON_JMC250 0x0021 |
343 | #define MII_STR_JMICRON_JMC250 "JMC250 10/100/1000 media interface" |
344 | #define MII_MODEL_JMICRON_JMC260 0x0022 |
345 | #define MII_STR_JMICRON_JMC260 "JMC260 10/100 media interface" |
346 | |
347 | /* Level 1 PHYs */ |
348 | #define MII_MODEL_xxLEVEL1_LXT970 0x0000 |
349 | #define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface" |
350 | #define MII_MODEL_LEVEL1_LXT971 0x000e |
351 | #define MII_STR_LEVEL1_LXT971 "LXT971/2 10/100 media interface" |
352 | #define MII_MODEL_LEVEL1_LXT973 0x0021 |
353 | #define MII_STR_LEVEL1_LXT973 "LXT973 10/100 Dual PHY" |
354 | #define MII_MODEL_LEVEL1_LXT974 0x0004 |
355 | #define MII_STR_LEVEL1_LXT974 "LXT974 10/100 Quad PHY" |
356 | #define MII_MODEL_LEVEL1_LXT975 0x0005 |
357 | #define MII_STR_LEVEL1_LXT975 "LXT975 10/100 Quad PHY" |
358 | #define MII_MODEL_LEVEL1_LXT1000_OLD 0x0003 |
359 | #define MII_STR_LEVEL1_LXT1000_OLD "LXT1000 1000BASE-T media interface" |
360 | #define MII_MODEL_LEVEL1_LXT1000 0x000c |
361 | #define MII_STR_LEVEL1_LXT1000 "LXT1000 1000BASE-T media interface" |
362 | |
363 | /* Marvell Semiconductor PHYs */ |
364 | #define MII_MODEL_xxMARVELL_E1000 0x0000 |
365 | #define MII_STR_xxMARVELL_E1000 "Marvell 88E1000 Gigabit PHY" |
366 | #define MII_MODEL_xxMARVELL_E1011 0x0002 |
367 | #define MII_STR_xxMARVELL_E1011 "Marvell 88E1011 Gigabit PHY" |
368 | #define MII_MODEL_xxMARVELL_E1000_3 0x0003 |
369 | #define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY" |
370 | #define MII_MODEL_xxMARVELL_E1000S 0x0004 |
371 | #define MII_STR_xxMARVELL_E1000S "Marvell 88E1000S Gigabit PHY" |
372 | #define MII_MODEL_xxMARVELL_E1000_5 0x0005 |
373 | #define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY" |
374 | #define MII_MODEL_xxMARVELL_E1101 0x0006 |
375 | #define MII_STR_xxMARVELL_E1101 "Marvell 88E1101 Gigabit PHY" |
376 | #define MII_MODEL_xxMARVELL_E3082 0x0008 |
377 | #define MII_STR_xxMARVELL_E3082 "Marvell 88E3082 10/100 Fast Ethernet PHY" |
378 | #define MII_MODEL_xxMARVELL_E1112 0x0009 |
379 | #define MII_STR_xxMARVELL_E1112 "Marvell 88E1112 Gigabit PHY" |
380 | #define MII_MODEL_xxMARVELL_E1149 0x000b |
381 | #define MII_STR_xxMARVELL_E1149 "Marvell 88E1149 Gigabit PHY" |
382 | #define MII_MODEL_xxMARVELL_E1111 0x000c |
383 | #define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY" |
384 | #define MII_MODEL_xxMARVELL_E1145 0x000d |
385 | #define MII_STR_xxMARVELL_E1145 "Marvell 88E1145 Quad Gigabit PHY" |
386 | #define MII_MODEL_xxMARVELL_E6060 0x0010 |
387 | #define MII_STR_xxMARVELL_E6060 "Marvell 88E6060 6-Port 10/100 Fast Ethernet Switch" |
388 | #define MII_MODEL_xxMARVELL_E1512 0x001d |
389 | #define MII_STR_xxMARVELL_E1512 "Marvell 88E1512 Gigabit PHY" |
390 | #define MII_MODEL_xxMARVELL_E1116 0x0021 |
391 | #define MII_STR_xxMARVELL_E1116 "Marvell 88E1116 Gigabit PHY" |
392 | #define MII_MODEL_xxMARVELL_E1118 0x0022 |
393 | #define MII_STR_xxMARVELL_E1118 "Marvell 88E1118 Gigabit PHY" |
394 | #define MII_MODEL_xxMARVELL_E1116R 0x0024 |
395 | #define MII_STR_xxMARVELL_E1116R "Marvell 88E1116R Gigabit PHY" |
396 | #define MII_MODEL_xxMARVELL_E1149R 0x0025 |
397 | #define MII_STR_xxMARVELL_E1149R "Marvell 88E1149R Quad Gigabit PHY" |
398 | #define MII_MODEL_xxMARVELL_E3016 0x0026 |
399 | #define MII_STR_xxMARVELL_E3016 "Marvell 88E3016 10/100 Fast Ethernet PHY" |
400 | #define MII_MODEL_xxMARVELL_PHYG65G 0x0027 |
401 | #define MII_STR_xxMARVELL_PHYG65G "Marvell PHYG65G Gigabit PHY" |
402 | #define MII_MODEL_xxMARVELL_E1116R_29 0x0029 |
403 | #define MII_STR_xxMARVELL_E1116R_29 "Marvell 88E1116R Gigabit PHY" |
404 | #define MII_MODEL_xxMARVELL_E1543 0x002a |
405 | #define MII_STR_xxMARVELL_E1543 "Marvell 88E1543 Alaska Quad Port Gb PHY" |
406 | #define MII_MODEL_MARVELL_E1000 0x0000 |
407 | #define MII_STR_MARVELL_E1000 "Marvell 88E1000 Gigabit PHY" |
408 | #define MII_MODEL_MARVELL_E1011 0x0002 |
409 | #define MII_STR_MARVELL_E1011 "Marvell 88E1011 Gigabit PHY" |
410 | #define MII_MODEL_MARVELL_E1000_3 0x0003 |
411 | #define MII_STR_MARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY" |
412 | #define MII_MODEL_MARVELL_E1000_5 0x0005 |
413 | #define MII_STR_MARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY" |
414 | #define MII_MODEL_MARVELL_E1111 0x000c |
415 | #define MII_STR_MARVELL_E1111 "Marvell 88E1111 Gigabit PHY" |
416 | |
417 | /* Micrel PHYs */ |
418 | #define MII_MODEL_MICREL_KSZ9021RNI 0x0021 |
419 | #define MII_STR_MICREL_KSZ9021RNI "Micrel KSZ9021RNI 10/100/1000 PHY" |
420 | |
421 | /* Myson Technology PHYs */ |
422 | #define MII_MODEL_xxMYSON_MTD972 0x0000 |
423 | #define MII_STR_xxMYSON_MTD972 "MTD972 10/100 media interface" |
424 | #define MII_MODEL_MYSON_MTD803 0x0000 |
425 | #define MII_STR_MYSON_MTD803 "MTD803 3-in-1 media interface" |
426 | |
427 | /* National Semiconductor PHYs */ |
428 | #define MII_MODEL_xxNATSEMI_DP83840 0x0000 |
429 | #define MII_STR_xxNATSEMI_DP83840 "DP83840 10/100 media interface" |
430 | #define MII_MODEL_xxNATSEMI_DP83843 0x0001 |
431 | #define MII_STR_xxNATSEMI_DP83843 "DP83843 10/100 media interface" |
432 | #define MII_MODEL_xxNATSEMI_DP83815 0x0002 |
433 | #define MII_STR_xxNATSEMI_DP83815 "DP83815 10/100 media interface" |
434 | #define MII_MODEL_xxNATSEMI_DP83847 0x0003 |
435 | #define MII_STR_xxNATSEMI_DP83847 "DP83847 10/100 media interface" |
436 | #define MII_MODEL_xxNATSEMI_DP83891 0x0005 |
437 | #define MII_STR_xxNATSEMI_DP83891 "DP83891 1000BASE-T media interface" |
438 | #define MII_MODEL_xxNATSEMI_DP83861 0x0006 |
439 | #define MII_STR_xxNATSEMI_DP83861 "DP83861 1000BASE-T media interface" |
440 | #define MII_MODEL_xxNATSEMI_DP83865 0x0007 |
441 | #define MII_STR_xxNATSEMI_DP83865 "DP83865 1000BASE-T media interface" |
442 | #define MII_MODEL_xxNATSEMI_DP83849 0x000a |
443 | #define MII_STR_xxNATSEMI_DP83849 "DP83849 10/100 media interface" |
444 | |
445 | /* PMC Sierra PHYs */ |
446 | #define MII_MODEL_xxPMCSIERRA_PM8351 0x0000 |
447 | #define MII_STR_xxPMCSIERRA_PM8351 "PM8351 OctalPHY Gigabit interface" |
448 | #define MII_MODEL_xxPMCSIERRA2_PM8352 0x0002 |
449 | #define MII_STR_xxPMCSIERRA2_PM8352 "PM8352 OctalPHY Gigabit interface" |
450 | #define MII_MODEL_xxPMCSIERRA2_PM8353 0x0003 |
451 | #define MII_STR_xxPMCSIERRA2_PM8353 "PM8353 QuadPHY Gigabit interface" |
452 | #define MII_MODEL_PMCSIERRA_PM8354 0x0004 |
453 | #define MII_STR_PMCSIERRA_PM8354 "PM8354 QuadPHY Gigabit interface" |
454 | |
455 | /* Quality Semiconductor PHYs */ |
456 | #define MII_MODEL_xxQUALSEMI_QS6612 0x0000 |
457 | #define MII_STR_xxQUALSEMI_QS6612 "QS6612 10/100 media interface" |
458 | |
459 | /* RDC Semiconductor PHYs */ |
460 | #define MII_MODEL_RDC_R6040 0x0003 |
461 | #define MII_STR_RDC_R6040 "R6040 10/100 media interface" |
462 | /* RealTek PHYs */ |
463 | #define MII_MODEL_yyREALTEK_RTL8201L 0x0020 |
464 | #define MII_STR_yyREALTEK_RTL8201L "RTL8201L 10/100 media interface" |
465 | #define MII_MODEL_xxREALTEK_RTL8169S 0x0011 |
466 | #define MII_STR_xxREALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface" |
467 | #define MII_MODEL_REALTEK_RTL8251 0x0000 |
468 | #define MII_STR_REALTEK_RTL8251 "RTL8251 1000BASE-T media interface" |
469 | #define MII_MODEL_REALTEK_RTL8169S 0x0011 |
470 | #define MII_STR_REALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface" |
471 | |
472 | /* Seeq PHYs */ |
473 | #define MII_MODEL_SEEQ_80220 0x0003 |
474 | #define MII_STR_SEEQ_80220 "Seeq 80220 10/100 media interface" |
475 | #define MII_MODEL_SEEQ_84220 0x0004 |
476 | #define MII_STR_SEEQ_84220 "Seeq 84220 10/100 media interface" |
477 | #define MII_MODEL_SEEQ_80225 0x0008 |
478 | #define MII_STR_SEEQ_80225 "Seeq 80225 10/100 media interface" |
479 | |
480 | /* Silicon Integrated Systems PHYs */ |
481 | #define MII_MODEL_SIS_900 0x0000 |
482 | #define MII_STR_SIS_900 "SiS 900 10/100 media interface" |
483 | |
484 | /* SMSC PHYs */ |
485 | #define MII_MODEL_SMSC_LAN8700 0x000c |
486 | #define MII_STR_SMSC_LAN8700 "SMSC LAN8700 10/100 Ethernet Transceiver" |
487 | #define MII_MODEL_SMSC_LAN8710_LAN8720 0x000f |
488 | #define MII_STR_SMSC_LAN8710_LAN8720 "SMSC LAN8710/LAN8720 10/100 Ethernet Transceiver" |
489 | |
490 | /* Texas Instruments PHYs */ |
491 | #define MII_MODEL_TI_TLAN10T 0x0001 |
492 | #define MII_STR_TI_TLAN10T "ThunderLAN 10BASE-T media interface" |
493 | #define MII_MODEL_TI_100VGPMI 0x0002 |
494 | #define MII_STR_TI_100VGPMI "ThunderLAN 100VG-AnyLan media interface" |
495 | #define MII_MODEL_TI_TNETE2101 0x0003 |
496 | #define MII_STR_TI_TNETE2101 "TNETE2101 media interface" |
497 | |
498 | /* TDK Semiconductor PHYs */ |
499 | #define MII_MODEL_xxTSC_78Q2120 0x0014 |
500 | #define MII_STR_xxTSC_78Q2120 "78Q2120 10/100 media interface" |
501 | #define MII_MODEL_xxTSC_78Q2121 0x0015 |
502 | #define MII_STR_xxTSC_78Q2121 "78Q2121 100BASE-TX media interface" |
503 | |
504 | /* XaQti Corp. PHYs */ |
505 | #define MII_MODEL_xxXAQTI_XMACII 0x0000 |
506 | #define MII_STR_xxXAQTI_XMACII "XaQti Corp. XMAC II gigabit interface" |
507 | |