1 | /* $NetBSD: nouveau_engine_graph_ctxnv40.c,v 1.1.1.1 2014/08/06 12:36:25 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2009 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_graph_ctxnv40.c,v 1.1.1.1 2014/08/06 12:36:25 riastradh Exp $" ); |
29 | |
30 | #include <core/gpuobj.h> |
31 | |
32 | /* NVIDIA context programs handle a number of other conditions which are |
33 | * not implemented in our versions. It's not clear why NVIDIA context |
34 | * programs have this code, nor whether it's strictly necessary for |
35 | * correct operation. We'll implement additional handling if/when we |
36 | * discover it's necessary. |
37 | * |
38 | * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state" |
39 | * flag is set, this gets saved into the context. |
40 | * - On context save, the context program for all cards load nsource |
41 | * into a flag register and check for ILLEGAL_MTHD. If it's set, |
42 | * opcode 0x60000d is called before resuming normal operation. |
43 | * - Some context programs check more conditions than the above. NV44 |
44 | * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001)) |
45 | * and calls 0x60000d before resuming normal operation. |
46 | * - At the very beginning of NVIDIA's context programs, flag 9 is checked |
47 | * and if true 0x800001 is called with count=0, pos=0, the flag is cleared |
48 | * and then the ctxprog is aborted. It looks like a complicated NOP, |
49 | * its purpose is unknown. |
50 | * - In the section of code that loads the per-vs state, NVIDIA check |
51 | * flag 10. If it's set, they only transfer the small 0x300 byte block |
52 | * of state + the state for a single vs as opposed to the state for |
53 | * all vs units. It doesn't seem likely that it'll occur in normal |
54 | * operation, especially seeing as it appears NVIDIA may have screwed |
55 | * up the ctxprogs for some cards and have an invalid instruction |
56 | * rather than a cp_lsr(ctx, dwords_for_1_vs_unit) instruction. |
57 | * - There's a number of places where context offset 0 (where we place |
58 | * the PRAMIN offset of the context) is loaded into either 0x408000, |
59 | * 0x408004 or 0x408008. Not sure what's up there either. |
60 | * - The ctxprogs for some cards save 0x400a00 again during the cleanup |
61 | * path for auto-loadctx. |
62 | */ |
63 | |
64 | #define CP_FLAG_CLEAR 0 |
65 | #define CP_FLAG_SET 1 |
66 | #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) |
67 | #define CP_FLAG_SWAP_DIRECTION_LOAD 0 |
68 | #define CP_FLAG_SWAP_DIRECTION_SAVE 1 |
69 | #define CP_FLAG_USER_SAVE ((0 * 32) + 5) |
70 | #define CP_FLAG_USER_SAVE_NOT_PENDING 0 |
71 | #define CP_FLAG_USER_SAVE_PENDING 1 |
72 | #define CP_FLAG_USER_LOAD ((0 * 32) + 6) |
73 | #define CP_FLAG_USER_LOAD_NOT_PENDING 0 |
74 | #define CP_FLAG_USER_LOAD_PENDING 1 |
75 | #define CP_FLAG_STATUS ((3 * 32) + 0) |
76 | #define CP_FLAG_STATUS_IDLE 0 |
77 | #define CP_FLAG_STATUS_BUSY 1 |
78 | #define CP_FLAG_AUTO_SAVE ((3 * 32) + 4) |
79 | #define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 |
80 | #define CP_FLAG_AUTO_SAVE_PENDING 1 |
81 | #define CP_FLAG_AUTO_LOAD ((3 * 32) + 5) |
82 | #define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 |
83 | #define CP_FLAG_AUTO_LOAD_PENDING 1 |
84 | #define CP_FLAG_UNK54 ((3 * 32) + 6) |
85 | #define CP_FLAG_UNK54_CLEAR 0 |
86 | #define CP_FLAG_UNK54_SET 1 |
87 | #define CP_FLAG_ALWAYS ((3 * 32) + 8) |
88 | #define CP_FLAG_ALWAYS_FALSE 0 |
89 | #define CP_FLAG_ALWAYS_TRUE 1 |
90 | #define CP_FLAG_UNK57 ((3 * 32) + 9) |
91 | #define CP_FLAG_UNK57_CLEAR 0 |
92 | #define CP_FLAG_UNK57_SET 1 |
93 | |
94 | #define CP_CTX 0x00100000 |
95 | #define CP_CTX_COUNT 0x000fc000 |
96 | #define CP_CTX_COUNT_SHIFT 14 |
97 | #define CP_CTX_REG 0x00003fff |
98 | #define CP_LOAD_SR 0x00200000 |
99 | #define CP_LOAD_SR_VALUE 0x000fffff |
100 | #define CP_BRA 0x00400000 |
101 | #define CP_BRA_IP 0x0000ff00 |
102 | #define CP_BRA_IP_SHIFT 8 |
103 | #define CP_BRA_IF_CLEAR 0x00000080 |
104 | #define CP_BRA_FLAG 0x0000007f |
105 | #define CP_WAIT 0x00500000 |
106 | #define CP_WAIT_SET 0x00000080 |
107 | #define CP_WAIT_FLAG 0x0000007f |
108 | #define CP_SET 0x00700000 |
109 | #define CP_SET_1 0x00000080 |
110 | #define CP_SET_FLAG 0x0000007f |
111 | #define CP_NEXT_TO_SWAP 0x00600007 |
112 | #define CP_NEXT_TO_CURRENT 0x00600009 |
113 | #define CP_SET_CONTEXT_POINTER 0x0060000a |
114 | #define CP_END 0x0060000e |
115 | #define CP_LOAD_MAGIC_UNK01 0x00800001 /* unknown */ |
116 | #define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */ |
117 | #define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */ |
118 | |
119 | #include "nv40.h" |
120 | #include "ctx.h" |
121 | |
122 | /* TODO: |
123 | * - get vs count from 0x1540 |
124 | */ |
125 | |
126 | static int |
127 | nv40_graph_vs_count(struct nouveau_device *device) |
128 | { |
129 | |
130 | switch (device->chipset) { |
131 | case 0x47: |
132 | case 0x49: |
133 | case 0x4b: |
134 | return 8; |
135 | case 0x40: |
136 | return 6; |
137 | case 0x41: |
138 | case 0x42: |
139 | return 5; |
140 | case 0x43: |
141 | case 0x44: |
142 | case 0x46: |
143 | case 0x4a: |
144 | return 3; |
145 | case 0x4c: |
146 | case 0x4e: |
147 | case 0x67: |
148 | default: |
149 | return 1; |
150 | } |
151 | } |
152 | |
153 | |
154 | enum cp_label { |
155 | cp_check_load = 1, |
156 | cp_setup_auto_load, |
157 | cp_setup_load, |
158 | cp_setup_save, |
159 | cp_swap_state, |
160 | cp_swap_state3d_3_is_save, |
161 | cp_prepare_exit, |
162 | cp_exit, |
163 | }; |
164 | |
165 | static void |
166 | nv40_graph_construct_general(struct nouveau_grctx *ctx) |
167 | { |
168 | struct nouveau_device *device = ctx->device; |
169 | int i; |
170 | |
171 | cp_ctx(ctx, 0x4000a4, 1); |
172 | gr_def(ctx, 0x4000a4, 0x00000008); |
173 | cp_ctx(ctx, 0x400144, 58); |
174 | gr_def(ctx, 0x400144, 0x00000001); |
175 | cp_ctx(ctx, 0x400314, 1); |
176 | gr_def(ctx, 0x400314, 0x00000000); |
177 | cp_ctx(ctx, 0x400400, 10); |
178 | cp_ctx(ctx, 0x400480, 10); |
179 | cp_ctx(ctx, 0x400500, 19); |
180 | gr_def(ctx, 0x400514, 0x00040000); |
181 | gr_def(ctx, 0x400524, 0x55555555); |
182 | gr_def(ctx, 0x400528, 0x55555555); |
183 | gr_def(ctx, 0x40052c, 0x55555555); |
184 | gr_def(ctx, 0x400530, 0x55555555); |
185 | cp_ctx(ctx, 0x400560, 6); |
186 | gr_def(ctx, 0x400568, 0x0000ffff); |
187 | gr_def(ctx, 0x40056c, 0x0000ffff); |
188 | cp_ctx(ctx, 0x40057c, 5); |
189 | cp_ctx(ctx, 0x400710, 3); |
190 | gr_def(ctx, 0x400710, 0x20010001); |
191 | gr_def(ctx, 0x400714, 0x0f73ef00); |
192 | cp_ctx(ctx, 0x400724, 1); |
193 | gr_def(ctx, 0x400724, 0x02008821); |
194 | cp_ctx(ctx, 0x400770, 3); |
195 | if (device->chipset == 0x40) { |
196 | cp_ctx(ctx, 0x400814, 4); |
197 | cp_ctx(ctx, 0x400828, 5); |
198 | cp_ctx(ctx, 0x400840, 5); |
199 | gr_def(ctx, 0x400850, 0x00000040); |
200 | cp_ctx(ctx, 0x400858, 4); |
201 | gr_def(ctx, 0x400858, 0x00000040); |
202 | gr_def(ctx, 0x40085c, 0x00000040); |
203 | gr_def(ctx, 0x400864, 0x80000000); |
204 | cp_ctx(ctx, 0x40086c, 9); |
205 | gr_def(ctx, 0x40086c, 0x80000000); |
206 | gr_def(ctx, 0x400870, 0x80000000); |
207 | gr_def(ctx, 0x400874, 0x80000000); |
208 | gr_def(ctx, 0x400878, 0x80000000); |
209 | gr_def(ctx, 0x400888, 0x00000040); |
210 | gr_def(ctx, 0x40088c, 0x80000000); |
211 | cp_ctx(ctx, 0x4009c0, 8); |
212 | gr_def(ctx, 0x4009cc, 0x80000000); |
213 | gr_def(ctx, 0x4009dc, 0x80000000); |
214 | } else { |
215 | cp_ctx(ctx, 0x400840, 20); |
216 | if (nv44_graph_class(ctx->device)) { |
217 | for (i = 0; i < 8; i++) |
218 | gr_def(ctx, 0x400860 + (i * 4), 0x00000001); |
219 | } |
220 | gr_def(ctx, 0x400880, 0x00000040); |
221 | gr_def(ctx, 0x400884, 0x00000040); |
222 | gr_def(ctx, 0x400888, 0x00000040); |
223 | cp_ctx(ctx, 0x400894, 11); |
224 | gr_def(ctx, 0x400894, 0x00000040); |
225 | if (!nv44_graph_class(ctx->device)) { |
226 | for (i = 0; i < 8; i++) |
227 | gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000); |
228 | } |
229 | cp_ctx(ctx, 0x4008e0, 2); |
230 | cp_ctx(ctx, 0x4008f8, 2); |
231 | if (device->chipset == 0x4c || |
232 | (device->chipset & 0xf0) == 0x60) |
233 | cp_ctx(ctx, 0x4009f8, 1); |
234 | } |
235 | cp_ctx(ctx, 0x400a00, 73); |
236 | gr_def(ctx, 0x400b0c, 0x0b0b0b0c); |
237 | cp_ctx(ctx, 0x401000, 4); |
238 | cp_ctx(ctx, 0x405004, 1); |
239 | switch (device->chipset) { |
240 | case 0x47: |
241 | case 0x49: |
242 | case 0x4b: |
243 | cp_ctx(ctx, 0x403448, 1); |
244 | gr_def(ctx, 0x403448, 0x00001010); |
245 | break; |
246 | default: |
247 | cp_ctx(ctx, 0x403440, 1); |
248 | switch (device->chipset) { |
249 | case 0x40: |
250 | gr_def(ctx, 0x403440, 0x00000010); |
251 | break; |
252 | case 0x44: |
253 | case 0x46: |
254 | case 0x4a: |
255 | gr_def(ctx, 0x403440, 0x00003010); |
256 | break; |
257 | case 0x41: |
258 | case 0x42: |
259 | case 0x43: |
260 | case 0x4c: |
261 | case 0x4e: |
262 | case 0x67: |
263 | default: |
264 | gr_def(ctx, 0x403440, 0x00001010); |
265 | break; |
266 | } |
267 | break; |
268 | } |
269 | } |
270 | |
271 | static void |
272 | nv40_graph_construct_state3d(struct nouveau_grctx *ctx) |
273 | { |
274 | struct nouveau_device *device = ctx->device; |
275 | int i; |
276 | |
277 | if (device->chipset == 0x40) { |
278 | cp_ctx(ctx, 0x401880, 51); |
279 | gr_def(ctx, 0x401940, 0x00000100); |
280 | } else |
281 | if (device->chipset == 0x46 || device->chipset == 0x47 || |
282 | device->chipset == 0x49 || device->chipset == 0x4b) { |
283 | cp_ctx(ctx, 0x401880, 32); |
284 | for (i = 0; i < 16; i++) |
285 | gr_def(ctx, 0x401880 + (i * 4), 0x00000111); |
286 | if (device->chipset == 0x46) |
287 | cp_ctx(ctx, 0x401900, 16); |
288 | cp_ctx(ctx, 0x401940, 3); |
289 | } |
290 | cp_ctx(ctx, 0x40194c, 18); |
291 | gr_def(ctx, 0x401954, 0x00000111); |
292 | gr_def(ctx, 0x401958, 0x00080060); |
293 | gr_def(ctx, 0x401974, 0x00000080); |
294 | gr_def(ctx, 0x401978, 0xffff0000); |
295 | gr_def(ctx, 0x40197c, 0x00000001); |
296 | gr_def(ctx, 0x401990, 0x46400000); |
297 | if (device->chipset == 0x40) { |
298 | cp_ctx(ctx, 0x4019a0, 2); |
299 | cp_ctx(ctx, 0x4019ac, 5); |
300 | } else { |
301 | cp_ctx(ctx, 0x4019a0, 1); |
302 | cp_ctx(ctx, 0x4019b4, 3); |
303 | } |
304 | gr_def(ctx, 0x4019bc, 0xffff0000); |
305 | switch (device->chipset) { |
306 | case 0x46: |
307 | case 0x47: |
308 | case 0x49: |
309 | case 0x4b: |
310 | cp_ctx(ctx, 0x4019c0, 18); |
311 | for (i = 0; i < 16; i++) |
312 | gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888); |
313 | break; |
314 | } |
315 | cp_ctx(ctx, 0x401a08, 8); |
316 | gr_def(ctx, 0x401a10, 0x0fff0000); |
317 | gr_def(ctx, 0x401a14, 0x0fff0000); |
318 | gr_def(ctx, 0x401a1c, 0x00011100); |
319 | cp_ctx(ctx, 0x401a2c, 4); |
320 | cp_ctx(ctx, 0x401a44, 26); |
321 | for (i = 0; i < 16; i++) |
322 | gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000); |
323 | gr_def(ctx, 0x401a8c, 0x4b7fffff); |
324 | if (device->chipset == 0x40) { |
325 | cp_ctx(ctx, 0x401ab8, 3); |
326 | } else { |
327 | cp_ctx(ctx, 0x401ab8, 1); |
328 | cp_ctx(ctx, 0x401ac0, 1); |
329 | } |
330 | cp_ctx(ctx, 0x401ad0, 8); |
331 | gr_def(ctx, 0x401ad0, 0x30201000); |
332 | gr_def(ctx, 0x401ad4, 0x70605040); |
333 | gr_def(ctx, 0x401ad8, 0xb8a89888); |
334 | gr_def(ctx, 0x401adc, 0xf8e8d8c8); |
335 | cp_ctx(ctx, 0x401b10, device->chipset == 0x40 ? 2 : 1); |
336 | gr_def(ctx, 0x401b10, 0x40100000); |
337 | cp_ctx(ctx, 0x401b18, device->chipset == 0x40 ? 6 : 5); |
338 | gr_def(ctx, 0x401b28, device->chipset == 0x40 ? |
339 | 0x00000004 : 0x00000000); |
340 | cp_ctx(ctx, 0x401b30, 25); |
341 | gr_def(ctx, 0x401b34, 0x0000ffff); |
342 | gr_def(ctx, 0x401b68, 0x435185d6); |
343 | gr_def(ctx, 0x401b6c, 0x2155b699); |
344 | gr_def(ctx, 0x401b70, 0xfedcba98); |
345 | gr_def(ctx, 0x401b74, 0x00000098); |
346 | gr_def(ctx, 0x401b84, 0xffffffff); |
347 | gr_def(ctx, 0x401b88, 0x00ff7000); |
348 | gr_def(ctx, 0x401b8c, 0x0000ffff); |
349 | if (device->chipset != 0x44 && device->chipset != 0x4a && |
350 | device->chipset != 0x4e) |
351 | cp_ctx(ctx, 0x401b94, 1); |
352 | cp_ctx(ctx, 0x401b98, 8); |
353 | gr_def(ctx, 0x401b9c, 0x00ff0000); |
354 | cp_ctx(ctx, 0x401bc0, 9); |
355 | gr_def(ctx, 0x401be0, 0x00ffff00); |
356 | cp_ctx(ctx, 0x401c00, 192); |
357 | for (i = 0; i < 16; i++) { /* fragment texture units */ |
358 | gr_def(ctx, 0x401c40 + (i * 4), 0x00018488); |
359 | gr_def(ctx, 0x401c80 + (i * 4), 0x00028202); |
360 | gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4); |
361 | gr_def(ctx, 0x401d40 + (i * 4), 0x01012000); |
362 | gr_def(ctx, 0x401d80 + (i * 4), 0x00080008); |
363 | gr_def(ctx, 0x401e00 + (i * 4), 0x00100008); |
364 | } |
365 | for (i = 0; i < 4; i++) { /* vertex texture units */ |
366 | gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80); |
367 | gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202); |
368 | gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008); |
369 | gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008); |
370 | } |
371 | cp_ctx(ctx, 0x400f5c, 3); |
372 | gr_def(ctx, 0x400f5c, 0x00000002); |
373 | cp_ctx(ctx, 0x400f84, 1); |
374 | } |
375 | |
376 | static void |
377 | nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx) |
378 | { |
379 | struct nouveau_device *device = ctx->device; |
380 | int i; |
381 | |
382 | cp_ctx(ctx, 0x402000, 1); |
383 | cp_ctx(ctx, 0x402404, device->chipset == 0x40 ? 1 : 2); |
384 | switch (device->chipset) { |
385 | case 0x40: |
386 | gr_def(ctx, 0x402404, 0x00000001); |
387 | break; |
388 | case 0x4c: |
389 | case 0x4e: |
390 | case 0x67: |
391 | gr_def(ctx, 0x402404, 0x00000020); |
392 | break; |
393 | case 0x46: |
394 | case 0x49: |
395 | case 0x4b: |
396 | gr_def(ctx, 0x402404, 0x00000421); |
397 | break; |
398 | default: |
399 | gr_def(ctx, 0x402404, 0x00000021); |
400 | } |
401 | if (device->chipset != 0x40) |
402 | gr_def(ctx, 0x402408, 0x030c30c3); |
403 | switch (device->chipset) { |
404 | case 0x44: |
405 | case 0x46: |
406 | case 0x4a: |
407 | case 0x4c: |
408 | case 0x4e: |
409 | case 0x67: |
410 | cp_ctx(ctx, 0x402440, 1); |
411 | gr_def(ctx, 0x402440, 0x00011001); |
412 | break; |
413 | default: |
414 | break; |
415 | } |
416 | cp_ctx(ctx, 0x402480, device->chipset == 0x40 ? 8 : 9); |
417 | gr_def(ctx, 0x402488, 0x3e020200); |
418 | gr_def(ctx, 0x40248c, 0x00ffffff); |
419 | switch (device->chipset) { |
420 | case 0x40: |
421 | gr_def(ctx, 0x402490, 0x60103f00); |
422 | break; |
423 | case 0x47: |
424 | gr_def(ctx, 0x402490, 0x40103f00); |
425 | break; |
426 | case 0x41: |
427 | case 0x42: |
428 | case 0x49: |
429 | case 0x4b: |
430 | gr_def(ctx, 0x402490, 0x20103f00); |
431 | break; |
432 | default: |
433 | gr_def(ctx, 0x402490, 0x0c103f00); |
434 | break; |
435 | } |
436 | gr_def(ctx, 0x40249c, device->chipset <= 0x43 ? |
437 | 0x00020000 : 0x00040000); |
438 | cp_ctx(ctx, 0x402500, 31); |
439 | gr_def(ctx, 0x402530, 0x00008100); |
440 | if (device->chipset == 0x40) |
441 | cp_ctx(ctx, 0x40257c, 6); |
442 | cp_ctx(ctx, 0x402594, 16); |
443 | cp_ctx(ctx, 0x402800, 17); |
444 | gr_def(ctx, 0x402800, 0x00000001); |
445 | switch (device->chipset) { |
446 | case 0x47: |
447 | case 0x49: |
448 | case 0x4b: |
449 | cp_ctx(ctx, 0x402864, 1); |
450 | gr_def(ctx, 0x402864, 0x00001001); |
451 | cp_ctx(ctx, 0x402870, 3); |
452 | gr_def(ctx, 0x402878, 0x00000003); |
453 | if (device->chipset != 0x47) { /* belong at end!! */ |
454 | cp_ctx(ctx, 0x402900, 1); |
455 | cp_ctx(ctx, 0x402940, 1); |
456 | cp_ctx(ctx, 0x402980, 1); |
457 | cp_ctx(ctx, 0x4029c0, 1); |
458 | cp_ctx(ctx, 0x402a00, 1); |
459 | cp_ctx(ctx, 0x402a40, 1); |
460 | cp_ctx(ctx, 0x402a80, 1); |
461 | cp_ctx(ctx, 0x402ac0, 1); |
462 | } |
463 | break; |
464 | case 0x40: |
465 | cp_ctx(ctx, 0x402844, 1); |
466 | gr_def(ctx, 0x402844, 0x00000001); |
467 | cp_ctx(ctx, 0x402850, 1); |
468 | break; |
469 | default: |
470 | cp_ctx(ctx, 0x402844, 1); |
471 | gr_def(ctx, 0x402844, 0x00001001); |
472 | cp_ctx(ctx, 0x402850, 2); |
473 | gr_def(ctx, 0x402854, 0x00000003); |
474 | break; |
475 | } |
476 | |
477 | cp_ctx(ctx, 0x402c00, 4); |
478 | gr_def(ctx, 0x402c00, device->chipset == 0x40 ? |
479 | 0x80800001 : 0x00888001); |
480 | switch (device->chipset) { |
481 | case 0x47: |
482 | case 0x49: |
483 | case 0x4b: |
484 | cp_ctx(ctx, 0x402c20, 40); |
485 | for (i = 0; i < 32; i++) |
486 | gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff); |
487 | cp_ctx(ctx, 0x4030b8, 13); |
488 | gr_def(ctx, 0x4030dc, 0x00000005); |
489 | gr_def(ctx, 0x4030e8, 0x0000ffff); |
490 | break; |
491 | default: |
492 | cp_ctx(ctx, 0x402c10, 4); |
493 | if (device->chipset == 0x40) |
494 | cp_ctx(ctx, 0x402c20, 36); |
495 | else |
496 | if (device->chipset <= 0x42) |
497 | cp_ctx(ctx, 0x402c20, 24); |
498 | else |
499 | if (device->chipset <= 0x4a) |
500 | cp_ctx(ctx, 0x402c20, 16); |
501 | else |
502 | cp_ctx(ctx, 0x402c20, 8); |
503 | cp_ctx(ctx, 0x402cb0, device->chipset == 0x40 ? 12 : 13); |
504 | gr_def(ctx, 0x402cd4, 0x00000005); |
505 | if (device->chipset != 0x40) |
506 | gr_def(ctx, 0x402ce0, 0x0000ffff); |
507 | break; |
508 | } |
509 | |
510 | cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3); |
511 | cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3); |
512 | cp_ctx(ctx, 0x403420, nv40_graph_vs_count(ctx->device)); |
513 | for (i = 0; i < nv40_graph_vs_count(ctx->device); i++) |
514 | gr_def(ctx, 0x403420 + (i * 4), 0x00005555); |
515 | |
516 | if (device->chipset != 0x40) { |
517 | cp_ctx(ctx, 0x403600, 1); |
518 | gr_def(ctx, 0x403600, 0x00000001); |
519 | } |
520 | cp_ctx(ctx, 0x403800, 1); |
521 | |
522 | cp_ctx(ctx, 0x403c18, 1); |
523 | gr_def(ctx, 0x403c18, 0x00000001); |
524 | switch (device->chipset) { |
525 | case 0x46: |
526 | case 0x47: |
527 | case 0x49: |
528 | case 0x4b: |
529 | cp_ctx(ctx, 0x405018, 1); |
530 | gr_def(ctx, 0x405018, 0x08e00001); |
531 | cp_ctx(ctx, 0x405c24, 1); |
532 | gr_def(ctx, 0x405c24, 0x000e3000); |
533 | break; |
534 | } |
535 | if (device->chipset != 0x4e) |
536 | cp_ctx(ctx, 0x405800, 11); |
537 | cp_ctx(ctx, 0x407000, 1); |
538 | } |
539 | |
540 | static void |
541 | nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx) |
542 | { |
543 | int len = nv44_graph_class(ctx->device) ? 0x0084 : 0x0684; |
544 | |
545 | cp_out (ctx, 0x300000); |
546 | cp_lsr (ctx, len - 4); |
547 | cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save); |
548 | cp_lsr (ctx, len); |
549 | cp_name(ctx, cp_swap_state3d_3_is_save); |
550 | cp_out (ctx, 0x800001); |
551 | |
552 | ctx->ctxvals_pos += len; |
553 | } |
554 | |
555 | static void |
556 | nv40_graph_construct_shader(struct nouveau_grctx *ctx) |
557 | { |
558 | struct nouveau_device *device = ctx->device; |
559 | struct nouveau_gpuobj *obj = ctx->data; |
560 | int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset; |
561 | int offset, i; |
562 | |
563 | vs_nr = nv40_graph_vs_count(ctx->device); |
564 | vs_nr_b0 = 363; |
565 | vs_nr_b1 = device->chipset == 0x40 ? 128 : 64; |
566 | if (device->chipset == 0x40) { |
567 | b0_offset = 0x2200/4; /* 33a0 */ |
568 | b1_offset = 0x55a0/4; /* 1500 */ |
569 | vs_len = 0x6aa0/4; |
570 | } else |
571 | if (device->chipset == 0x41 || device->chipset == 0x42) { |
572 | b0_offset = 0x2200/4; /* 2200 */ |
573 | b1_offset = 0x4400/4; /* 0b00 */ |
574 | vs_len = 0x4f00/4; |
575 | } else { |
576 | b0_offset = 0x1d40/4; /* 2200 */ |
577 | b1_offset = 0x3f40/4; /* 0b00 : 0a40 */ |
578 | vs_len = nv44_graph_class(device) ? 0x4980/4 : 0x4a40/4; |
579 | } |
580 | |
581 | cp_lsr(ctx, vs_len * vs_nr + 0x300/4); |
582 | cp_out(ctx, nv44_graph_class(device) ? 0x800029 : 0x800041); |
583 | |
584 | offset = ctx->ctxvals_pos; |
585 | ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len)); |
586 | |
587 | if (ctx->mode != NOUVEAU_GRCTX_VALS) |
588 | return; |
589 | |
590 | offset += 0x0280/4; |
591 | for (i = 0; i < 16; i++, offset += 2) |
592 | nv_wo32(obj, offset * 4, 0x3f800000); |
593 | |
594 | for (vs = 0; vs < vs_nr; vs++, offset += vs_len) { |
595 | for (i = 0; i < vs_nr_b0 * 6; i += 6) |
596 | nv_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001); |
597 | for (i = 0; i < vs_nr_b1 * 4; i += 4) |
598 | nv_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000); |
599 | } |
600 | } |
601 | |
602 | static void |
603 | nv40_grctx_generate(struct nouveau_grctx *ctx) |
604 | { |
605 | /* decide whether we're loading/unloading the context */ |
606 | cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); |
607 | cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); |
608 | |
609 | cp_name(ctx, cp_check_load); |
610 | cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); |
611 | cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); |
612 | cp_bra (ctx, ALWAYS, TRUE, cp_exit); |
613 | |
614 | /* setup for context load */ |
615 | cp_name(ctx, cp_setup_auto_load); |
616 | cp_wait(ctx, STATUS, IDLE); |
617 | cp_out (ctx, CP_NEXT_TO_SWAP); |
618 | cp_name(ctx, cp_setup_load); |
619 | cp_wait(ctx, STATUS, IDLE); |
620 | cp_set (ctx, SWAP_DIRECTION, LOAD); |
621 | cp_out (ctx, 0x00910880); /* ?? */ |
622 | cp_out (ctx, 0x00901ffe); /* ?? */ |
623 | cp_out (ctx, 0x01940000); /* ?? */ |
624 | cp_lsr (ctx, 0x20); |
625 | cp_out (ctx, 0x0060000b); /* ?? */ |
626 | cp_wait(ctx, UNK57, CLEAR); |
627 | cp_out (ctx, 0x0060000c); /* ?? */ |
628 | cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); |
629 | |
630 | /* setup for context save */ |
631 | cp_name(ctx, cp_setup_save); |
632 | cp_set (ctx, SWAP_DIRECTION, SAVE); |
633 | |
634 | /* general PGRAPH state */ |
635 | cp_name(ctx, cp_swap_state); |
636 | cp_pos (ctx, 0x00020/4); |
637 | nv40_graph_construct_general(ctx); |
638 | cp_wait(ctx, STATUS, IDLE); |
639 | |
640 | /* 3D state, block 1 */ |
641 | cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit); |
642 | nv40_graph_construct_state3d(ctx); |
643 | cp_wait(ctx, STATUS, IDLE); |
644 | |
645 | /* 3D state, block 2 */ |
646 | nv40_graph_construct_state3d_2(ctx); |
647 | |
648 | /* Some other block of "random" state */ |
649 | nv40_graph_construct_state3d_3(ctx); |
650 | |
651 | /* Per-vertex shader state */ |
652 | cp_pos (ctx, ctx->ctxvals_pos); |
653 | nv40_graph_construct_shader(ctx); |
654 | |
655 | /* pre-exit state updates */ |
656 | cp_name(ctx, cp_prepare_exit); |
657 | cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); |
658 | cp_bra (ctx, USER_SAVE, PENDING, cp_exit); |
659 | cp_out (ctx, CP_NEXT_TO_CURRENT); |
660 | |
661 | cp_name(ctx, cp_exit); |
662 | cp_set (ctx, USER_SAVE, NOT_PENDING); |
663 | cp_set (ctx, USER_LOAD, NOT_PENDING); |
664 | cp_out (ctx, CP_END); |
665 | } |
666 | |
667 | void |
668 | nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) |
669 | { |
670 | nv40_grctx_generate(&(struct nouveau_grctx) { |
671 | .device = device, |
672 | .mode = NOUVEAU_GRCTX_VALS, |
673 | .data = mem, |
674 | }); |
675 | } |
676 | |
677 | int |
678 | nv40_grctx_init(struct nouveau_device *device, u32 *size) |
679 | { |
680 | u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i; |
681 | struct nouveau_grctx ctx = { |
682 | .device = device, |
683 | .mode = NOUVEAU_GRCTX_PROG, |
684 | .data = ctxprog, |
685 | .ctxprog_max = 256, |
686 | }; |
687 | |
688 | if (!ctxprog) |
689 | return -ENOMEM; |
690 | |
691 | nv40_grctx_generate(&ctx); |
692 | |
693 | nv_wr32(device, 0x400324, 0); |
694 | for (i = 0; i < ctx.ctxprog_len; i++) |
695 | nv_wr32(device, 0x400328, ctxprog[i]); |
696 | *size = ctx.ctxvals_pos * 4; |
697 | |
698 | kfree(ctxprog); |
699 | return 0; |
700 | } |
701 | |