1 | /* |
2 | * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting |
3 | * Copyright (c) 2002-2006 Atheros Communications, Inc. |
4 | * |
5 | * Permission to use, copy, modify, and/or distribute this software for any |
6 | * purpose with or without fee is hereby granted, provided that the above |
7 | * copyright notice and this permission notice appear in all copies. |
8 | * |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
16 | * |
17 | * $Id: ar5211_keycache.c,v 1.1.1.1 2008/12/11 04:46:31 alc Exp $ |
18 | */ |
19 | #include "opt_ah.h" |
20 | |
21 | #include "ah.h" |
22 | #include "ah_internal.h" |
23 | |
24 | #include "ar5211/ar5211.h" |
25 | #include "ar5211/ar5211reg.h" |
26 | |
27 | /* |
28 | * Chips-specific key cache routines. |
29 | */ |
30 | |
31 | #define AR_KEYTABLE_SIZE 128 |
32 | #define KEY_XOR 0xaa |
33 | |
34 | /* |
35 | * Return the size of the hardware key cache. |
36 | */ |
37 | uint32_t |
38 | ar5211GetKeyCacheSize(struct ath_hal *ah) |
39 | { |
40 | return AR_KEYTABLE_SIZE; |
41 | } |
42 | |
43 | /* |
44 | * Return true if the specific key cache entry is valid. |
45 | */ |
46 | HAL_BOOL |
47 | ar5211IsKeyCacheEntryValid(struct ath_hal *ah, uint16_t entry) |
48 | { |
49 | if (entry < AR_KEYTABLE_SIZE) { |
50 | uint32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); |
51 | if (val & AR_KEYTABLE_VALID) |
52 | return AH_TRUE; |
53 | } |
54 | return AH_FALSE; |
55 | } |
56 | |
57 | /* |
58 | * Clear the specified key cache entry |
59 | */ |
60 | HAL_BOOL |
61 | ar5211ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry) |
62 | { |
63 | if (entry < AR_KEYTABLE_SIZE) { |
64 | OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); |
65 | OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); |
66 | OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); |
67 | OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); |
68 | OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); |
69 | OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), 0); |
70 | OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); |
71 | OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); |
72 | return AH_TRUE; |
73 | } |
74 | return AH_FALSE; |
75 | } |
76 | |
77 | /* |
78 | * Sets the mac part of the specified key cache entry and mark it valid. |
79 | */ |
80 | HAL_BOOL |
81 | ar5211SetKeyCacheEntryMac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac) |
82 | { |
83 | uint32_t macHi, macLo; |
84 | |
85 | if (entry >= AR_KEYTABLE_SIZE) { |
86 | HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n" , |
87 | __func__, entry); |
88 | return AH_FALSE; |
89 | } |
90 | |
91 | /* |
92 | * Set MAC address -- shifted right by 1. MacLo is |
93 | * the 4 MSBs, and MacHi is the 2 LSBs. |
94 | */ |
95 | if (mac != AH_NULL) { |
96 | macHi = (mac[5] << 8) | mac[4]; |
97 | macLo = (mac[3] << 24)| (mac[2] << 16) |
98 | | (mac[1] << 8) | mac[0]; |
99 | macLo >>= 1; |
100 | macLo |= (macHi & 1) << 31; /* carry */ |
101 | macHi >>= 1; |
102 | } else { |
103 | macLo = macHi = 0; |
104 | } |
105 | |
106 | OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); |
107 | OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); |
108 | return AH_TRUE; |
109 | } |
110 | |
111 | /* |
112 | * Sets the contents of the specified key cache entry. |
113 | */ |
114 | HAL_BOOL |
115 | ar5211SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, |
116 | const HAL_KEYVAL *k, const uint8_t *mac, |
117 | int xorKey) |
118 | { |
119 | uint32_t key0, key1, key2, key3, key4; |
120 | uint32_t keyType; |
121 | uint32_t xorMask= xorKey ? |
122 | (KEY_XOR << 24 | KEY_XOR << 16 | KEY_XOR << 8 | KEY_XOR) : 0; |
123 | |
124 | if (entry >= AR_KEYTABLE_SIZE) { |
125 | HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n" , |
126 | __func__, entry); |
127 | return AH_FALSE; |
128 | } |
129 | switch (k->kv_type) { |
130 | case HAL_CIPHER_AES_OCB: |
131 | keyType = AR_KEYTABLE_TYPE_AES; |
132 | break; |
133 | case HAL_CIPHER_WEP: |
134 | if (k->kv_len < 40 / NBBY) { |
135 | HALDEBUG(ah, HAL_DEBUG_ANY, |
136 | "%s: WEP key length %u too small\n" , |
137 | __func__, k->kv_len); |
138 | return AH_FALSE; |
139 | } |
140 | if (k->kv_len <= 40 / NBBY) |
141 | keyType = AR_KEYTABLE_TYPE_40; |
142 | else if (k->kv_len <= 104 / NBBY) |
143 | keyType = AR_KEYTABLE_TYPE_104; |
144 | else |
145 | keyType = AR_KEYTABLE_TYPE_128; |
146 | break; |
147 | case HAL_CIPHER_CLR: |
148 | keyType = AR_KEYTABLE_TYPE_CLR; |
149 | break; |
150 | default: |
151 | HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cipher %u not supported\n" , |
152 | __func__, k->kv_type); |
153 | return AH_FALSE; |
154 | } |
155 | |
156 | key0 = LE_READ_4(k->kv_val+0) ^ xorMask; |
157 | key1 = (LE_READ_2(k->kv_val+4) ^ xorMask) & 0xffff; |
158 | key2 = LE_READ_4(k->kv_val+6) ^ xorMask; |
159 | key3 = (LE_READ_2(k->kv_val+10) ^ xorMask) & 0xffff; |
160 | key4 = LE_READ_4(k->kv_val+12) ^ xorMask; |
161 | if (k->kv_len <= 104 / NBBY) |
162 | key4 &= 0xff; |
163 | |
164 | |
165 | /* |
166 | * Note: WEP key cache hardware requires that each double-word |
167 | * pair be written in even/odd order (since the destination is |
168 | * a 64-bit register). Don't reorder these writes w/o |
169 | * understanding this! |
170 | */ |
171 | OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); |
172 | OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); |
173 | OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); |
174 | OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); |
175 | OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); |
176 | OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); |
177 | return ar5211SetKeyCacheEntryMac(ah, entry, mac); |
178 | } |
179 | |