1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
26 | * Jerome Glisse |
27 | */ |
28 | #include <linux/kernel.h> |
29 | #include <drm/drmP.h> |
30 | #include "radeon.h" |
31 | #include "r600d.h" |
32 | #include "r600_reg_safe.h" |
33 | |
34 | static int r600_nomm; |
35 | extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size); |
36 | |
37 | |
38 | struct r600_cs_track { |
39 | /* configuration we miror so that we use same code btw kms/ums */ |
40 | u32 group_size; |
41 | u32 nbanks; |
42 | u32 npipes; |
43 | /* value we track */ |
44 | u32 sq_config; |
45 | u32 log_nsamples; |
46 | u32 nsamples; |
47 | u32 cb_color_base_last[8]; |
48 | struct radeon_bo *cb_color_bo[8]; |
49 | u64 cb_color_bo_mc[8]; |
50 | u64 cb_color_bo_offset[8]; |
51 | struct radeon_bo *cb_color_frag_bo[8]; |
52 | u64 cb_color_frag_offset[8]; |
53 | struct radeon_bo *cb_color_tile_bo[8]; |
54 | u64 cb_color_tile_offset[8]; |
55 | u32 cb_color_mask[8]; |
56 | u32 cb_color_info[8]; |
57 | u32 cb_color_view[8]; |
58 | u32 cb_color_size_idx[8]; /* unused */ |
59 | u32 cb_target_mask; |
60 | u32 cb_shader_mask; /* unused */ |
61 | bool is_resolve; |
62 | u32 cb_color_size[8]; |
63 | u32 vgt_strmout_en; |
64 | u32 vgt_strmout_buffer_en; |
65 | struct radeon_bo *vgt_strmout_bo[4]; |
66 | u64 vgt_strmout_bo_mc[4]; /* unused */ |
67 | u32 vgt_strmout_bo_offset[4]; |
68 | u32 vgt_strmout_size[4]; |
69 | u32 db_depth_control; |
70 | u32 db_depth_info; |
71 | u32 db_depth_size_idx; |
72 | u32 db_depth_view; |
73 | u32 db_depth_size; |
74 | u32 db_offset; |
75 | struct radeon_bo *db_bo; |
76 | u64 db_bo_mc; |
77 | bool sx_misc_kill_all_prims; |
78 | bool cb_dirty; |
79 | bool db_dirty; |
80 | bool streamout_dirty; |
81 | struct radeon_bo *htile_bo; |
82 | u64 htile_offset; |
83 | u32 htile_surface; |
84 | }; |
85 | |
86 | #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 } |
87 | #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 } |
88 | #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 } |
89 | #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 } |
90 | #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 } |
91 | #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 } |
92 | #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 } |
93 | #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 } |
94 | |
95 | struct gpu_formats { |
96 | unsigned blockwidth; |
97 | unsigned blockheight; |
98 | unsigned blocksize; |
99 | unsigned valid_color; |
100 | enum radeon_family min_family; |
101 | }; |
102 | |
103 | static const struct gpu_formats color_formats_table[] = { |
104 | /* 8 bit */ |
105 | FMT_8_BIT(V_038004_COLOR_8, 1), |
106 | FMT_8_BIT(V_038004_COLOR_4_4, 1), |
107 | FMT_8_BIT(V_038004_COLOR_3_3_2, 1), |
108 | FMT_8_BIT(V_038004_FMT_1, 0), |
109 | |
110 | /* 16-bit */ |
111 | FMT_16_BIT(V_038004_COLOR_16, 1), |
112 | FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1), |
113 | FMT_16_BIT(V_038004_COLOR_8_8, 1), |
114 | FMT_16_BIT(V_038004_COLOR_5_6_5, 1), |
115 | FMT_16_BIT(V_038004_COLOR_6_5_5, 1), |
116 | FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1), |
117 | FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1), |
118 | FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1), |
119 | |
120 | /* 24-bit */ |
121 | FMT_24_BIT(V_038004_FMT_8_8_8), |
122 | |
123 | /* 32-bit */ |
124 | FMT_32_BIT(V_038004_COLOR_32, 1), |
125 | FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1), |
126 | FMT_32_BIT(V_038004_COLOR_16_16, 1), |
127 | FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1), |
128 | FMT_32_BIT(V_038004_COLOR_8_24, 1), |
129 | FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1), |
130 | FMT_32_BIT(V_038004_COLOR_24_8, 1), |
131 | FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1), |
132 | FMT_32_BIT(V_038004_COLOR_10_11_11, 1), |
133 | FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1), |
134 | FMT_32_BIT(V_038004_COLOR_11_11_10, 1), |
135 | FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1), |
136 | FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1), |
137 | FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1), |
138 | FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1), |
139 | FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0), |
140 | FMT_32_BIT(V_038004_FMT_32_AS_8, 0), |
141 | FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0), |
142 | |
143 | /* 48-bit */ |
144 | FMT_48_BIT(V_038004_FMT_16_16_16), |
145 | FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT), |
146 | |
147 | /* 64-bit */ |
148 | FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1), |
149 | FMT_64_BIT(V_038004_COLOR_32_32, 1), |
150 | FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1), |
151 | FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1), |
152 | FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1), |
153 | |
154 | FMT_96_BIT(V_038004_FMT_32_32_32), |
155 | FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT), |
156 | |
157 | /* 128-bit */ |
158 | FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1), |
159 | FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1), |
160 | |
161 | [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 }, |
162 | [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 }, |
163 | |
164 | /* block compressed formats */ |
165 | [V_038004_FMT_BC1] = { 4, 4, 8, 0 }, |
166 | [V_038004_FMT_BC2] = { 4, 4, 16, 0 }, |
167 | [V_038004_FMT_BC3] = { 4, 4, 16, 0 }, |
168 | [V_038004_FMT_BC4] = { 4, 4, 8, 0 }, |
169 | [V_038004_FMT_BC5] = { 4, 4, 16, 0}, |
170 | [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */ |
171 | [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */ |
172 | |
173 | /* The other Evergreen formats */ |
174 | [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR}, |
175 | }; |
176 | |
177 | bool r600_fmt_is_valid_color(u32 format) |
178 | { |
179 | if (format >= ARRAY_SIZE(color_formats_table)) |
180 | return false; |
181 | |
182 | if (color_formats_table[format].valid_color) |
183 | return true; |
184 | |
185 | return false; |
186 | } |
187 | |
188 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family) |
189 | { |
190 | if (format >= ARRAY_SIZE(color_formats_table)) |
191 | return false; |
192 | |
193 | if (family < color_formats_table[format].min_family) |
194 | return false; |
195 | |
196 | if (color_formats_table[format].blockwidth > 0) |
197 | return true; |
198 | |
199 | return false; |
200 | } |
201 | |
202 | int r600_fmt_get_blocksize(u32 format) |
203 | { |
204 | if (format >= ARRAY_SIZE(color_formats_table)) |
205 | return 0; |
206 | |
207 | return color_formats_table[format].blocksize; |
208 | } |
209 | |
210 | int r600_fmt_get_nblocksx(u32 format, u32 w) |
211 | { |
212 | unsigned bw; |
213 | |
214 | if (format >= ARRAY_SIZE(color_formats_table)) |
215 | return 0; |
216 | |
217 | bw = color_formats_table[format].blockwidth; |
218 | if (bw == 0) |
219 | return 0; |
220 | |
221 | return (w + bw - 1) / bw; |
222 | } |
223 | |
224 | int r600_fmt_get_nblocksy(u32 format, u32 h) |
225 | { |
226 | unsigned bh; |
227 | |
228 | if (format >= ARRAY_SIZE(color_formats_table)) |
229 | return 0; |
230 | |
231 | bh = color_formats_table[format].blockheight; |
232 | if (bh == 0) |
233 | return 0; |
234 | |
235 | return (h + bh - 1) / bh; |
236 | } |
237 | |
238 | struct array_mode_checker { |
239 | int array_mode; |
240 | u32 group_size; |
241 | u32 nbanks; |
242 | u32 npipes; |
243 | u32 nsamples; |
244 | u32 blocksize; |
245 | }; |
246 | |
247 | /* returns alignment in pixels for pitch/height/depth and bytes for base */ |
248 | static int r600_get_array_mode_alignment(struct array_mode_checker *values, |
249 | u32 *pitch_align, |
250 | u32 *height_align, |
251 | u32 *depth_align, |
252 | u64 *base_align) |
253 | { |
254 | u32 tile_width = 8; |
255 | u32 tile_height = 8; |
256 | u32 macro_tile_width = values->nbanks; |
257 | u32 macro_tile_height = values->npipes; |
258 | u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples; |
259 | u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes; |
260 | |
261 | switch (values->array_mode) { |
262 | case ARRAY_LINEAR_GENERAL: |
263 | /* technically tile_width/_height for pitch/height */ |
264 | *pitch_align = 1; /* tile_width */ |
265 | *height_align = 1; /* tile_height */ |
266 | *depth_align = 1; |
267 | *base_align = 1; |
268 | break; |
269 | case ARRAY_LINEAR_ALIGNED: |
270 | *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize)); |
271 | *height_align = 1; |
272 | *depth_align = 1; |
273 | *base_align = values->group_size; |
274 | break; |
275 | case ARRAY_1D_TILED_THIN1: |
276 | *pitch_align = max((u32)tile_width, |
277 | (u32)(values->group_size / |
278 | (tile_height * values->blocksize * values->nsamples))); |
279 | *height_align = tile_height; |
280 | *depth_align = 1; |
281 | *base_align = values->group_size; |
282 | break; |
283 | case ARRAY_2D_TILED_THIN1: |
284 | *pitch_align = max((u32)macro_tile_width * tile_width, |
285 | (u32)((values->group_size * values->nbanks) / |
286 | (values->blocksize * values->nsamples * tile_width))); |
287 | *height_align = macro_tile_height * tile_height; |
288 | *depth_align = 1; |
289 | *base_align = max(macro_tile_bytes, |
290 | (*pitch_align) * values->blocksize * (*height_align) * values->nsamples); |
291 | break; |
292 | default: |
293 | return -EINVAL; |
294 | } |
295 | |
296 | return 0; |
297 | } |
298 | |
299 | static void r600_cs_track_init(struct r600_cs_track *track) |
300 | { |
301 | int i; |
302 | |
303 | /* assume DX9 mode */ |
304 | track->sq_config = DX9_CONSTS; |
305 | for (i = 0; i < 8; i++) { |
306 | track->cb_color_base_last[i] = 0; |
307 | track->cb_color_size[i] = 0; |
308 | track->cb_color_size_idx[i] = 0; |
309 | track->cb_color_info[i] = 0; |
310 | track->cb_color_view[i] = 0xFFFFFFFF; |
311 | track->cb_color_bo[i] = NULL; |
312 | track->cb_color_bo_offset[i] = 0xFFFFFFFF; |
313 | track->cb_color_bo_mc[i] = 0xFFFFFFFF; |
314 | track->cb_color_frag_bo[i] = NULL; |
315 | track->cb_color_frag_offset[i] = 0xFFFFFFFF; |
316 | track->cb_color_tile_bo[i] = NULL; |
317 | track->cb_color_tile_offset[i] = 0xFFFFFFFF; |
318 | track->cb_color_mask[i] = 0xFFFFFFFF; |
319 | } |
320 | track->is_resolve = false; |
321 | track->nsamples = 16; |
322 | track->log_nsamples = 4; |
323 | track->cb_target_mask = 0xFFFFFFFF; |
324 | track->cb_shader_mask = 0xFFFFFFFF; |
325 | track->cb_dirty = true; |
326 | track->db_bo = NULL; |
327 | track->db_bo_mc = 0xFFFFFFFF; |
328 | /* assume the biggest format and that htile is enabled */ |
329 | track->db_depth_info = 7 | (1 << 25); |
330 | track->db_depth_view = 0xFFFFC000; |
331 | track->db_depth_size = 0xFFFFFFFF; |
332 | track->db_depth_size_idx = 0; |
333 | track->db_depth_control = 0xFFFFFFFF; |
334 | track->db_dirty = true; |
335 | track->htile_bo = NULL; |
336 | track->htile_offset = 0xFFFFFFFF; |
337 | track->htile_surface = 0; |
338 | |
339 | for (i = 0; i < 4; i++) { |
340 | track->vgt_strmout_size[i] = 0; |
341 | track->vgt_strmout_bo[i] = NULL; |
342 | track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; |
343 | track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF; |
344 | } |
345 | track->streamout_dirty = true; |
346 | track->sx_misc_kill_all_prims = false; |
347 | } |
348 | |
349 | static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) |
350 | { |
351 | struct r600_cs_track *track = p->track; |
352 | u32 slice_tile_max, size __unused, tmp; |
353 | u32 height, height_align, pitch, pitch_align, depth_align; |
354 | u64 base_offset, base_align; |
355 | struct array_mode_checker array_check; |
356 | volatile u32 *ib = p->ib.ptr; |
357 | unsigned array_mode; |
358 | u32 format; |
359 | /* When resolve is used, the second colorbuffer has always 1 sample. */ |
360 | unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples; |
361 | |
362 | size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i]; |
363 | format = G_0280A0_FORMAT(track->cb_color_info[i]); |
364 | if (!r600_fmt_is_valid_color(format)) { |
365 | dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n" , |
366 | __func__, __LINE__, format, |
367 | i, track->cb_color_info[i]); |
368 | return -EINVAL; |
369 | } |
370 | /* pitch in pixels */ |
371 | pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8; |
372 | slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1; |
373 | slice_tile_max *= 64; |
374 | height = slice_tile_max / pitch; |
375 | if (height > 8192) |
376 | height = 8192; |
377 | array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]); |
378 | |
379 | base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i]; |
380 | array_check.array_mode = array_mode; |
381 | array_check.group_size = track->group_size; |
382 | array_check.nbanks = track->nbanks; |
383 | array_check.npipes = track->npipes; |
384 | array_check.nsamples = nsamples; |
385 | array_check.blocksize = r600_fmt_get_blocksize(format); |
386 | if (r600_get_array_mode_alignment(&array_check, |
387 | &pitch_align, &height_align, &depth_align, &base_align)) { |
388 | dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n" , __func__, |
389 | G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, |
390 | track->cb_color_info[i]); |
391 | return -EINVAL; |
392 | } |
393 | switch (array_mode) { |
394 | case V_0280A0_ARRAY_LINEAR_GENERAL: |
395 | break; |
396 | case V_0280A0_ARRAY_LINEAR_ALIGNED: |
397 | break; |
398 | case V_0280A0_ARRAY_1D_TILED_THIN1: |
399 | /* avoid breaking userspace */ |
400 | if (height > 7) |
401 | height &= ~0x7; |
402 | break; |
403 | case V_0280A0_ARRAY_2D_TILED_THIN1: |
404 | break; |
405 | default: |
406 | dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n" , __func__, |
407 | G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, |
408 | track->cb_color_info[i]); |
409 | return -EINVAL; |
410 | } |
411 | |
412 | if (!IS_ALIGNED(pitch, pitch_align)) { |
413 | dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n" , |
414 | __func__, __LINE__, pitch, pitch_align, array_mode); |
415 | return -EINVAL; |
416 | } |
417 | if (!IS_ALIGNED(height, height_align)) { |
418 | dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n" , |
419 | __func__, __LINE__, height, height_align, array_mode); |
420 | return -EINVAL; |
421 | } |
422 | if (!IS_ALIGNED(base_offset, base_align)) { |
423 | dev_warn(p->dev, "%s offset[%d] 0x%" PRIx64" 0x%" PRIx64", %d not aligned\n" , __func__, i, |
424 | base_offset, base_align, array_mode); |
425 | return -EINVAL; |
426 | } |
427 | |
428 | /* check offset */ |
429 | tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * |
430 | r600_fmt_get_blocksize(format) * nsamples; |
431 | switch (array_mode) { |
432 | default: |
433 | case V_0280A0_ARRAY_LINEAR_GENERAL: |
434 | case V_0280A0_ARRAY_LINEAR_ALIGNED: |
435 | tmp += track->cb_color_view[i] & 0xFF; |
436 | break; |
437 | case V_0280A0_ARRAY_1D_TILED_THIN1: |
438 | case V_0280A0_ARRAY_2D_TILED_THIN1: |
439 | tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp; |
440 | break; |
441 | } |
442 | if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { |
443 | if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) { |
444 | /* the initial DDX does bad things with the CB size occasionally */ |
445 | /* it rounds up height too far for slice tile max but the BO is smaller */ |
446 | /* r600c,g also seem to flush at bad times in some apps resulting in |
447 | * bogus values here. So for linear just allow anything to avoid breaking |
448 | * broken userspace. |
449 | */ |
450 | } else { |
451 | dev_warn(p->dev, "%s offset[%d] %d %" PRIu64" %d %lu too big (%d %d) (%d %d %d)\n" , |
452 | __func__, i, array_mode, |
453 | track->cb_color_bo_offset[i], tmp, |
454 | radeon_bo_size(track->cb_color_bo[i]), |
455 | pitch, height, r600_fmt_get_nblocksx(format, pitch), |
456 | r600_fmt_get_nblocksy(format, height), |
457 | r600_fmt_get_blocksize(format)); |
458 | return -EINVAL; |
459 | } |
460 | } |
461 | /* limit max tile */ |
462 | tmp = (height * pitch) >> 6; |
463 | if (tmp < slice_tile_max) |
464 | slice_tile_max = tmp; |
465 | tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) | |
466 | S_028060_SLICE_TILE_MAX(slice_tile_max - 1); |
467 | ib[track->cb_color_size_idx[i]] = tmp; |
468 | |
469 | /* FMASK/CMASK */ |
470 | switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) { |
471 | case V_0280A0_TILE_DISABLE: |
472 | break; |
473 | case V_0280A0_FRAG_ENABLE: |
474 | if (track->nsamples > 1) { |
475 | uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]); |
476 | /* the tile size is 8x8, but the size is in units of bits. |
477 | * for bytes, do just * 8. */ |
478 | uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1); |
479 | |
480 | if (bytes + track->cb_color_frag_offset[i] > |
481 | radeon_bo_size(track->cb_color_frag_bo[i])) { |
482 | dev_warn(p->dev, "%s FMASK_TILE_MAX too large " |
483 | "(tile_max=%u, bytes=%u, offset=%" PRIu64", bo_size=%lu)\n" , |
484 | __func__, tile_max, bytes, |
485 | track->cb_color_frag_offset[i], |
486 | radeon_bo_size(track->cb_color_frag_bo[i])); |
487 | return -EINVAL; |
488 | } |
489 | } |
490 | /* fall through */ |
491 | case V_0280A0_CLEAR_ENABLE: |
492 | { |
493 | uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]); |
494 | /* One block = 128x128 pixels, one 8x8 tile has 4 bits.. |
495 | * (128*128) / (8*8) / 2 = 128 bytes per block. */ |
496 | uint32_t bytes = (block_max + 1) * 128; |
497 | |
498 | if (bytes + track->cb_color_tile_offset[i] > |
499 | radeon_bo_size(track->cb_color_tile_bo[i])) { |
500 | dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large " |
501 | "(block_max=%u, bytes=%u, offset=%" PRIu64", bo_size=%lu)\n" , |
502 | __func__, block_max, bytes, |
503 | track->cb_color_tile_offset[i], |
504 | radeon_bo_size(track->cb_color_tile_bo[i])); |
505 | return -EINVAL; |
506 | } |
507 | break; |
508 | } |
509 | default: |
510 | dev_warn(p->dev, "%s invalid tile mode\n" , __func__); |
511 | return -EINVAL; |
512 | } |
513 | return 0; |
514 | } |
515 | |
516 | static int r600_cs_track_validate_db(struct radeon_cs_parser *p) |
517 | { |
518 | struct r600_cs_track *track = p->track; |
519 | u32 nviews, bpe, ntiles, size __unused, slice_tile_max, tmp; |
520 | u32 height_align, pitch_align, depth_align; |
521 | u32 pitch = 8192; |
522 | u32 height = 8192; |
523 | u64 base_offset, base_align; |
524 | struct array_mode_checker array_check; |
525 | int array_mode; |
526 | volatile u32 *ib = p->ib.ptr; |
527 | |
528 | |
529 | if (track->db_bo == NULL) { |
530 | dev_warn(p->dev, "z/stencil with no depth buffer\n" ); |
531 | return -EINVAL; |
532 | } |
533 | switch (G_028010_FORMAT(track->db_depth_info)) { |
534 | case V_028010_DEPTH_16: |
535 | bpe = 2; |
536 | break; |
537 | case V_028010_DEPTH_X8_24: |
538 | case V_028010_DEPTH_8_24: |
539 | case V_028010_DEPTH_X8_24_FLOAT: |
540 | case V_028010_DEPTH_8_24_FLOAT: |
541 | case V_028010_DEPTH_32_FLOAT: |
542 | bpe = 4; |
543 | break; |
544 | case V_028010_DEPTH_X24_8_32_FLOAT: |
545 | bpe = 8; |
546 | break; |
547 | default: |
548 | dev_warn(p->dev, "z/stencil with invalid format %d\n" , G_028010_FORMAT(track->db_depth_info)); |
549 | return -EINVAL; |
550 | } |
551 | if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { |
552 | if (!track->db_depth_size_idx) { |
553 | dev_warn(p->dev, "z/stencil buffer size not set\n" ); |
554 | return -EINVAL; |
555 | } |
556 | tmp = radeon_bo_size(track->db_bo) - track->db_offset; |
557 | tmp = (tmp / bpe) >> 6; |
558 | if (!tmp) { |
559 | dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n" , |
560 | track->db_depth_size, bpe, track->db_offset, |
561 | radeon_bo_size(track->db_bo)); |
562 | return -EINVAL; |
563 | } |
564 | ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); |
565 | } else { |
566 | size = radeon_bo_size(track->db_bo); |
567 | /* pitch in pixels */ |
568 | pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8; |
569 | slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; |
570 | slice_tile_max *= 64; |
571 | height = slice_tile_max / pitch; |
572 | if (height > 8192) |
573 | height = 8192; |
574 | base_offset = track->db_bo_mc + track->db_offset; |
575 | array_mode = G_028010_ARRAY_MODE(track->db_depth_info); |
576 | array_check.array_mode = array_mode; |
577 | array_check.group_size = track->group_size; |
578 | array_check.nbanks = track->nbanks; |
579 | array_check.npipes = track->npipes; |
580 | array_check.nsamples = track->nsamples; |
581 | array_check.blocksize = bpe; |
582 | if (r600_get_array_mode_alignment(&array_check, |
583 | &pitch_align, &height_align, &depth_align, &base_align)) { |
584 | dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n" , __func__, |
585 | G_028010_ARRAY_MODE(track->db_depth_info), |
586 | track->db_depth_info); |
587 | return -EINVAL; |
588 | } |
589 | switch (array_mode) { |
590 | case V_028010_ARRAY_1D_TILED_THIN1: |
591 | /* don't break userspace */ |
592 | height &= ~0x7; |
593 | break; |
594 | case V_028010_ARRAY_2D_TILED_THIN1: |
595 | break; |
596 | default: |
597 | dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n" , __func__, |
598 | G_028010_ARRAY_MODE(track->db_depth_info), |
599 | track->db_depth_info); |
600 | return -EINVAL; |
601 | } |
602 | |
603 | if (!IS_ALIGNED(pitch, pitch_align)) { |
604 | dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n" , |
605 | __func__, __LINE__, pitch, pitch_align, array_mode); |
606 | return -EINVAL; |
607 | } |
608 | if (!IS_ALIGNED(height, height_align)) { |
609 | dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n" , |
610 | __func__, __LINE__, height, height_align, array_mode); |
611 | return -EINVAL; |
612 | } |
613 | if (!IS_ALIGNED(base_offset, base_align)) { |
614 | dev_warn(p->dev, "%s offset 0x%" PRIx64", 0x%" PRIx64", %d not aligned\n" , __func__, |
615 | base_offset, base_align, array_mode); |
616 | return -EINVAL; |
617 | } |
618 | |
619 | ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; |
620 | nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; |
621 | tmp = ntiles * bpe * 64 * nviews * track->nsamples; |
622 | if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { |
623 | dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n" , |
624 | array_mode, |
625 | track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, |
626 | radeon_bo_size(track->db_bo)); |
627 | return -EINVAL; |
628 | } |
629 | } |
630 | |
631 | /* hyperz */ |
632 | if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) { |
633 | unsigned long size; |
634 | unsigned nbx, nby; |
635 | |
636 | if (track->htile_bo == NULL) { |
637 | dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n" , |
638 | __func__, __LINE__, track->db_depth_info); |
639 | return -EINVAL; |
640 | } |
641 | if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { |
642 | dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n" , |
643 | __func__, __LINE__, track->db_depth_size); |
644 | return -EINVAL; |
645 | } |
646 | |
647 | nbx = pitch; |
648 | nby = height; |
649 | if (G_028D24_LINEAR(track->htile_surface)) { |
650 | /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */ |
651 | nbx = round_up(nbx, 16 * 8); |
652 | /* nby is npipes htiles aligned == npipes * 8 pixel aligned */ |
653 | nby = round_up(nby, track->npipes * 8); |
654 | } else { |
655 | /* always assume 8x8 htile */ |
656 | /* align is htile align * 8, htile align vary according to |
657 | * number of pipe and tile width and nby |
658 | */ |
659 | switch (track->npipes) { |
660 | case 8: |
661 | /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ |
662 | nbx = round_up(nbx, 64 * 8); |
663 | nby = round_up(nby, 64 * 8); |
664 | break; |
665 | case 4: |
666 | /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ |
667 | nbx = round_up(nbx, 64 * 8); |
668 | nby = round_up(nby, 32 * 8); |
669 | break; |
670 | case 2: |
671 | /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ |
672 | nbx = round_up(nbx, 32 * 8); |
673 | nby = round_up(nby, 32 * 8); |
674 | break; |
675 | case 1: |
676 | /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ |
677 | nbx = round_up(nbx, 32 * 8); |
678 | nby = round_up(nby, 16 * 8); |
679 | break; |
680 | default: |
681 | dev_warn(p->dev, "%s:%d invalid num pipes %d\n" , |
682 | __func__, __LINE__, track->npipes); |
683 | return -EINVAL; |
684 | } |
685 | } |
686 | /* compute number of htile */ |
687 | nbx = nbx >> 3; |
688 | nby = nby >> 3; |
689 | /* size must be aligned on npipes * 2K boundary */ |
690 | size = roundup(nbx * nby * 4, track->npipes * (2 << 10)); |
691 | size += track->htile_offset; |
692 | |
693 | if (size > radeon_bo_size(track->htile_bo)) { |
694 | dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n" , |
695 | __func__, __LINE__, radeon_bo_size(track->htile_bo), |
696 | size, nbx, nby); |
697 | return -EINVAL; |
698 | } |
699 | } |
700 | |
701 | track->db_dirty = false; |
702 | return 0; |
703 | } |
704 | |
705 | static int r600_cs_track_check(struct radeon_cs_parser *p) |
706 | { |
707 | struct r600_cs_track *track = p->track; |
708 | u32 tmp; |
709 | int r, i; |
710 | |
711 | /* on legacy kernel we don't perform advanced check */ |
712 | if (p->rdev == NULL) |
713 | return 0; |
714 | |
715 | /* check streamout */ |
716 | if (track->streamout_dirty && track->vgt_strmout_en) { |
717 | for (i = 0; i < 4; i++) { |
718 | if (track->vgt_strmout_buffer_en & (1 << i)) { |
719 | if (track->vgt_strmout_bo[i]) { |
720 | u64 offset = (u64)track->vgt_strmout_bo_offset[i] + |
721 | (u64)track->vgt_strmout_size[i]; |
722 | if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { |
723 | DRM_ERROR("streamout %d bo too small: 0x%" PRIx64", 0x%lx\n" , |
724 | i, offset, |
725 | radeon_bo_size(track->vgt_strmout_bo[i])); |
726 | return -EINVAL; |
727 | } |
728 | } else { |
729 | dev_warn(p->dev, "No buffer for streamout %d\n" , i); |
730 | return -EINVAL; |
731 | } |
732 | } |
733 | } |
734 | track->streamout_dirty = false; |
735 | } |
736 | |
737 | if (track->sx_misc_kill_all_prims) |
738 | return 0; |
739 | |
740 | /* check that we have a cb for each enabled target, we don't check |
741 | * shader_mask because it seems mesa isn't always setting it :( |
742 | */ |
743 | if (track->cb_dirty) { |
744 | tmp = track->cb_target_mask; |
745 | |
746 | /* We must check both colorbuffers for RESOLVE. */ |
747 | if (track->is_resolve) { |
748 | tmp |= 0xff; |
749 | } |
750 | |
751 | for (i = 0; i < 8; i++) { |
752 | u32 format = G_0280A0_FORMAT(track->cb_color_info[i]); |
753 | |
754 | if (format != V_0280A0_COLOR_INVALID && |
755 | (tmp >> (i * 4)) & 0xF) { |
756 | /* at least one component is enabled */ |
757 | if (track->cb_color_bo[i] == NULL) { |
758 | dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n" , |
759 | __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); |
760 | return -EINVAL; |
761 | } |
762 | /* perform rewrite of CB_COLOR[0-7]_SIZE */ |
763 | r = r600_cs_track_validate_cb(p, i); |
764 | if (r) |
765 | return r; |
766 | } |
767 | } |
768 | track->cb_dirty = false; |
769 | } |
770 | |
771 | /* Check depth buffer */ |
772 | if (track->db_dirty && |
773 | G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID && |
774 | (G_028800_STENCIL_ENABLE(track->db_depth_control) || |
775 | G_028800_Z_ENABLE(track->db_depth_control))) { |
776 | r = r600_cs_track_validate_db(p); |
777 | if (r) |
778 | return r; |
779 | } |
780 | |
781 | return 0; |
782 | } |
783 | |
784 | /** |
785 | * r600_cs_packet_parse_vline() - parse userspace VLINE packet |
786 | * @parser: parser structure holding parsing context. |
787 | * |
788 | * This is an R600-specific function for parsing VLINE packets. |
789 | * Real work is done by r600_cs_common_vline_parse function. |
790 | * Here we just set up ASIC-specific register table and call |
791 | * the common implementation function. |
792 | */ |
793 | static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p) |
794 | { |
795 | static uint32_t vline_start_end[2] = {AVIVO_D1MODE_VLINE_START_END, |
796 | AVIVO_D2MODE_VLINE_START_END}; |
797 | static uint32_t vline_status[2] = {AVIVO_D1MODE_VLINE_STATUS, |
798 | AVIVO_D2MODE_VLINE_STATUS}; |
799 | |
800 | return r600_cs_common_vline_parse(p, vline_start_end, vline_status); |
801 | } |
802 | |
803 | /** |
804 | * r600_cs_common_vline_parse() - common vline parser |
805 | * @parser: parser structure holding parsing context. |
806 | * @vline_start_end: table of vline_start_end registers |
807 | * @vline_status: table of vline_status registers |
808 | * |
809 | * Userspace sends a special sequence for VLINE waits. |
810 | * PACKET0 - VLINE_START_END + value |
811 | * PACKET3 - WAIT_REG_MEM poll vline status reg |
812 | * RELOC (P3) - crtc_id in reloc. |
813 | * |
814 | * This function parses this and relocates the VLINE START END |
815 | * and WAIT_REG_MEM packets to the correct crtc. |
816 | * It also detects a switched off crtc and nulls out the |
817 | * wait in that case. This function is common for all ASICs that |
818 | * are R600 and newer. The parsing algorithm is the same, and only |
819 | * differs in which registers are used. |
820 | * |
821 | * Caller is the ASIC-specific function which passes the parser |
822 | * context and ASIC-specific register table |
823 | */ |
824 | int r600_cs_common_vline_parse(struct radeon_cs_parser *p, |
825 | uint32_t *vline_start_end, |
826 | uint32_t *vline_status) |
827 | { |
828 | struct drm_mode_object *obj; |
829 | struct drm_crtc *crtc; |
830 | struct radeon_crtc *radeon_crtc; |
831 | struct radeon_cs_packet p3reloc, wait_reg_mem; |
832 | int crtc_id; |
833 | int r; |
834 | uint32_t , h_idx, reg, wait_reg_mem_info; |
835 | volatile uint32_t *ib; |
836 | |
837 | ib = p->ib.ptr; |
838 | |
839 | /* parse the WAIT_REG_MEM */ |
840 | r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx); |
841 | if (r) |
842 | return r; |
843 | |
844 | /* check its a WAIT_REG_MEM */ |
845 | if (wait_reg_mem.type != RADEON_PACKET_TYPE3 || |
846 | wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { |
847 | DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n" ); |
848 | return -EINVAL; |
849 | } |
850 | |
851 | wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); |
852 | /* bit 4 is reg (0) or mem (1) */ |
853 | if (wait_reg_mem_info & 0x10) { |
854 | DRM_ERROR("vline WAIT_REG_MEM waiting on MEM instead of REG\n" ); |
855 | return -EINVAL; |
856 | } |
857 | /* bit 8 is me (0) or pfp (1) */ |
858 | if (wait_reg_mem_info & 0x100) { |
859 | DRM_ERROR("vline WAIT_REG_MEM waiting on PFP instead of ME\n" ); |
860 | return -EINVAL; |
861 | } |
862 | /* waiting for value to be equal */ |
863 | if ((wait_reg_mem_info & 0x7) != 0x3) { |
864 | DRM_ERROR("vline WAIT_REG_MEM function not equal\n" ); |
865 | return -EINVAL; |
866 | } |
867 | if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) { |
868 | DRM_ERROR("vline WAIT_REG_MEM bad reg\n" ); |
869 | return -EINVAL; |
870 | } |
871 | |
872 | if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) { |
873 | DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n" ); |
874 | return -EINVAL; |
875 | } |
876 | |
877 | /* jump over the NOP */ |
878 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); |
879 | if (r) |
880 | return r; |
881 | |
882 | h_idx = p->idx - 2; |
883 | p->idx += wait_reg_mem.count + 2; |
884 | p->idx += p3reloc.count + 2; |
885 | |
886 | header = radeon_get_ib_value(p, h_idx); |
887 | crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); |
888 | reg = R600_CP_PACKET0_GET_REG(header); |
889 | |
890 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); |
891 | if (!obj) { |
892 | DRM_ERROR("cannot find crtc %d\n" , crtc_id); |
893 | return -ENOENT; |
894 | } |
895 | crtc = obj_to_crtc(obj); |
896 | radeon_crtc = to_radeon_crtc(crtc); |
897 | crtc_id = radeon_crtc->crtc_id; |
898 | |
899 | if (!crtc->enabled) { |
900 | /* CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */ |
901 | ib[h_idx + 2] = PACKET2(0); |
902 | ib[h_idx + 3] = PACKET2(0); |
903 | ib[h_idx + 4] = PACKET2(0); |
904 | ib[h_idx + 5] = PACKET2(0); |
905 | ib[h_idx + 6] = PACKET2(0); |
906 | ib[h_idx + 7] = PACKET2(0); |
907 | ib[h_idx + 8] = PACKET2(0); |
908 | } else if (reg == vline_start_end[0]) { |
909 | header &= ~R600_CP_PACKET0_REG_MASK; |
910 | header |= vline_start_end[crtc_id] >> 2; |
911 | ib[h_idx] = header; |
912 | ib[h_idx + 4] = vline_status[crtc_id] >> 2; |
913 | } else { |
914 | DRM_ERROR("unknown crtc reloc\n" ); |
915 | return -EINVAL; |
916 | } |
917 | return 0; |
918 | } |
919 | |
920 | static int r600_packet0_check(struct radeon_cs_parser *p, |
921 | struct radeon_cs_packet *pkt, |
922 | unsigned idx, unsigned reg) |
923 | { |
924 | int r; |
925 | |
926 | switch (reg) { |
927 | case AVIVO_D1MODE_VLINE_START_END: |
928 | r = r600_cs_packet_parse_vline(p); |
929 | if (r) { |
930 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n" , |
931 | idx, reg); |
932 | return r; |
933 | } |
934 | break; |
935 | default: |
936 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n" , |
937 | reg, idx); |
938 | return -EINVAL; |
939 | } |
940 | return 0; |
941 | } |
942 | |
943 | static int r600_cs_parse_packet0(struct radeon_cs_parser *p, |
944 | struct radeon_cs_packet *pkt) |
945 | { |
946 | unsigned reg, i; |
947 | unsigned idx; |
948 | int r; |
949 | |
950 | idx = pkt->idx + 1; |
951 | reg = pkt->reg; |
952 | for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { |
953 | r = r600_packet0_check(p, pkt, idx, reg); |
954 | if (r) { |
955 | return r; |
956 | } |
957 | } |
958 | return 0; |
959 | } |
960 | |
961 | /** |
962 | * r600_cs_check_reg() - check if register is authorized or not |
963 | * @parser: parser structure holding parsing context |
964 | * @reg: register we are testing |
965 | * @idx: index into the cs buffer |
966 | * |
967 | * This function will test against r600_reg_safe_bm and return 0 |
968 | * if register is safe. If register is not flag as safe this function |
969 | * will test it against a list of register needind special handling. |
970 | */ |
971 | static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) |
972 | { |
973 | struct r600_cs_track *track = (struct r600_cs_track *)p->track; |
974 | struct radeon_cs_reloc *reloc; |
975 | u32 m, i, tmp, *ib; |
976 | int r; |
977 | |
978 | i = (reg >> 7); |
979 | if (i >= ARRAY_SIZE(r600_reg_safe_bm)) { |
980 | dev_warn(p->dev, "forbidden register 0x%08x at %d\n" , reg, idx); |
981 | return -EINVAL; |
982 | } |
983 | m = 1 << ((reg >> 2) & 31); |
984 | if (!(r600_reg_safe_bm[i] & m)) |
985 | return 0; |
986 | ib = p->ib.ptr; |
987 | switch (reg) { |
988 | /* force following reg to 0 in an attempt to disable out buffer |
989 | * which will need us to better understand how it works to perform |
990 | * security check on it (Jerome) |
991 | */ |
992 | case R_0288A8_SQ_ESGS_RING_ITEMSIZE: |
993 | case R_008C44_SQ_ESGS_RING_SIZE: |
994 | case R_0288B0_SQ_ESTMP_RING_ITEMSIZE: |
995 | case R_008C54_SQ_ESTMP_RING_SIZE: |
996 | case R_0288C0_SQ_FBUF_RING_ITEMSIZE: |
997 | case R_008C74_SQ_FBUF_RING_SIZE: |
998 | case R_0288B4_SQ_GSTMP_RING_ITEMSIZE: |
999 | case R_008C5C_SQ_GSTMP_RING_SIZE: |
1000 | case R_0288AC_SQ_GSVS_RING_ITEMSIZE: |
1001 | case R_008C4C_SQ_GSVS_RING_SIZE: |
1002 | case R_0288BC_SQ_PSTMP_RING_ITEMSIZE: |
1003 | case R_008C6C_SQ_PSTMP_RING_SIZE: |
1004 | case R_0288C4_SQ_REDUC_RING_ITEMSIZE: |
1005 | case R_008C7C_SQ_REDUC_RING_SIZE: |
1006 | case R_0288B8_SQ_VSTMP_RING_ITEMSIZE: |
1007 | case R_008C64_SQ_VSTMP_RING_SIZE: |
1008 | case R_0288C8_SQ_GS_VERT_ITEMSIZE: |
1009 | /* get value to populate the IB don't remove */ |
1010 | /*tmp =radeon_get_ib_value(p, idx); |
1011 | ib[idx] = 0;*/ |
1012 | break; |
1013 | case SQ_ESGS_RING_BASE: |
1014 | case SQ_GSVS_RING_BASE: |
1015 | case SQ_ESTMP_RING_BASE: |
1016 | case SQ_GSTMP_RING_BASE: |
1017 | case SQ_PSTMP_RING_BASE: |
1018 | case SQ_VSTMP_RING_BASE: |
1019 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1020 | if (r) { |
1021 | dev_warn(p->dev, "bad SET_CONTEXT_REG " |
1022 | "0x%04X\n" , reg); |
1023 | return -EINVAL; |
1024 | } |
1025 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1026 | break; |
1027 | case SQ_CONFIG: |
1028 | track->sq_config = radeon_get_ib_value(p, idx); |
1029 | break; |
1030 | case R_028800_DB_DEPTH_CONTROL: |
1031 | track->db_depth_control = radeon_get_ib_value(p, idx); |
1032 | track->db_dirty = true; |
1033 | break; |
1034 | case R_028010_DB_DEPTH_INFO: |
1035 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && |
1036 | radeon_cs_packet_next_is_pkt3_nop(p)) { |
1037 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1038 | if (r) { |
1039 | dev_warn(p->dev, "bad SET_CONTEXT_REG " |
1040 | "0x%04X\n" , reg); |
1041 | return -EINVAL; |
1042 | } |
1043 | track->db_depth_info = radeon_get_ib_value(p, idx); |
1044 | ib[idx] &= C_028010_ARRAY_MODE; |
1045 | track->db_depth_info &= C_028010_ARRAY_MODE; |
1046 | if (reloc->tiling_flags & RADEON_TILING_MACRO) { |
1047 | ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); |
1048 | track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); |
1049 | } else { |
1050 | ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); |
1051 | track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); |
1052 | } |
1053 | } else { |
1054 | track->db_depth_info = radeon_get_ib_value(p, idx); |
1055 | } |
1056 | track->db_dirty = true; |
1057 | break; |
1058 | case R_028004_DB_DEPTH_VIEW: |
1059 | track->db_depth_view = radeon_get_ib_value(p, idx); |
1060 | track->db_dirty = true; |
1061 | break; |
1062 | case R_028000_DB_DEPTH_SIZE: |
1063 | track->db_depth_size = radeon_get_ib_value(p, idx); |
1064 | track->db_depth_size_idx = idx; |
1065 | track->db_dirty = true; |
1066 | break; |
1067 | case R_028AB0_VGT_STRMOUT_EN: |
1068 | track->vgt_strmout_en = radeon_get_ib_value(p, idx); |
1069 | track->streamout_dirty = true; |
1070 | break; |
1071 | case R_028B20_VGT_STRMOUT_BUFFER_EN: |
1072 | track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx); |
1073 | track->streamout_dirty = true; |
1074 | break; |
1075 | case VGT_STRMOUT_BUFFER_BASE_0: |
1076 | case VGT_STRMOUT_BUFFER_BASE_1: |
1077 | case VGT_STRMOUT_BUFFER_BASE_2: |
1078 | case VGT_STRMOUT_BUFFER_BASE_3: |
1079 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1080 | if (r) { |
1081 | dev_warn(p->dev, "bad SET_CONTEXT_REG " |
1082 | "0x%04X\n" , reg); |
1083 | return -EINVAL; |
1084 | } |
1085 | tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; |
1086 | track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; |
1087 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1088 | track->vgt_strmout_bo[tmp] = reloc->robj; |
1089 | track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset; |
1090 | track->streamout_dirty = true; |
1091 | break; |
1092 | case VGT_STRMOUT_BUFFER_SIZE_0: |
1093 | case VGT_STRMOUT_BUFFER_SIZE_1: |
1094 | case VGT_STRMOUT_BUFFER_SIZE_2: |
1095 | case VGT_STRMOUT_BUFFER_SIZE_3: |
1096 | tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16; |
1097 | /* size in register is DWs, convert to bytes */ |
1098 | track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; |
1099 | track->streamout_dirty = true; |
1100 | break; |
1101 | case CP_COHER_BASE: |
1102 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1103 | if (r) { |
1104 | dev_warn(p->dev, "missing reloc for CP_COHER_BASE " |
1105 | "0x%04X\n" , reg); |
1106 | return -EINVAL; |
1107 | } |
1108 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1109 | break; |
1110 | case R_028238_CB_TARGET_MASK: |
1111 | track->cb_target_mask = radeon_get_ib_value(p, idx); |
1112 | track->cb_dirty = true; |
1113 | break; |
1114 | case R_02823C_CB_SHADER_MASK: |
1115 | track->cb_shader_mask = radeon_get_ib_value(p, idx); |
1116 | break; |
1117 | case R_028C04_PA_SC_AA_CONFIG: |
1118 | tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); |
1119 | track->log_nsamples = tmp; |
1120 | track->nsamples = 1 << tmp; |
1121 | track->cb_dirty = true; |
1122 | break; |
1123 | case R_028808_CB_COLOR_CONTROL: |
1124 | tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx)); |
1125 | track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX; |
1126 | track->cb_dirty = true; |
1127 | break; |
1128 | case R_0280A0_CB_COLOR0_INFO: |
1129 | case R_0280A4_CB_COLOR1_INFO: |
1130 | case R_0280A8_CB_COLOR2_INFO: |
1131 | case R_0280AC_CB_COLOR3_INFO: |
1132 | case R_0280B0_CB_COLOR4_INFO: |
1133 | case R_0280B4_CB_COLOR5_INFO: |
1134 | case R_0280B8_CB_COLOR6_INFO: |
1135 | case R_0280BC_CB_COLOR7_INFO: |
1136 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && |
1137 | radeon_cs_packet_next_is_pkt3_nop(p)) { |
1138 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1139 | if (r) { |
1140 | dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n" , reg); |
1141 | return -EINVAL; |
1142 | } |
1143 | tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; |
1144 | track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); |
1145 | if (reloc->tiling_flags & RADEON_TILING_MACRO) { |
1146 | ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); |
1147 | track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); |
1148 | } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { |
1149 | ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); |
1150 | track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); |
1151 | } |
1152 | } else { |
1153 | tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; |
1154 | track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); |
1155 | } |
1156 | track->cb_dirty = true; |
1157 | break; |
1158 | case R_028080_CB_COLOR0_VIEW: |
1159 | case R_028084_CB_COLOR1_VIEW: |
1160 | case R_028088_CB_COLOR2_VIEW: |
1161 | case R_02808C_CB_COLOR3_VIEW: |
1162 | case R_028090_CB_COLOR4_VIEW: |
1163 | case R_028094_CB_COLOR5_VIEW: |
1164 | case R_028098_CB_COLOR6_VIEW: |
1165 | case R_02809C_CB_COLOR7_VIEW: |
1166 | tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4; |
1167 | track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); |
1168 | track->cb_dirty = true; |
1169 | break; |
1170 | case R_028060_CB_COLOR0_SIZE: |
1171 | case R_028064_CB_COLOR1_SIZE: |
1172 | case R_028068_CB_COLOR2_SIZE: |
1173 | case R_02806C_CB_COLOR3_SIZE: |
1174 | case R_028070_CB_COLOR4_SIZE: |
1175 | case R_028074_CB_COLOR5_SIZE: |
1176 | case R_028078_CB_COLOR6_SIZE: |
1177 | case R_02807C_CB_COLOR7_SIZE: |
1178 | tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4; |
1179 | track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); |
1180 | track->cb_color_size_idx[tmp] = idx; |
1181 | track->cb_dirty = true; |
1182 | break; |
1183 | /* This register were added late, there is userspace |
1184 | * which does provide relocation for those but set |
1185 | * 0 offset. In order to avoid breaking old userspace |
1186 | * we detect this and set address to point to last |
1187 | * CB_COLOR0_BASE, note that if userspace doesn't set |
1188 | * CB_COLOR0_BASE before this register we will report |
1189 | * error. Old userspace always set CB_COLOR0_BASE |
1190 | * before any of this. |
1191 | */ |
1192 | case R_0280E0_CB_COLOR0_FRAG: |
1193 | case R_0280E4_CB_COLOR1_FRAG: |
1194 | case R_0280E8_CB_COLOR2_FRAG: |
1195 | case R_0280EC_CB_COLOR3_FRAG: |
1196 | case R_0280F0_CB_COLOR4_FRAG: |
1197 | case R_0280F4_CB_COLOR5_FRAG: |
1198 | case R_0280F8_CB_COLOR6_FRAG: |
1199 | case R_0280FC_CB_COLOR7_FRAG: |
1200 | tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4; |
1201 | if (!radeon_cs_packet_next_is_pkt3_nop(p)) { |
1202 | if (!track->cb_color_base_last[tmp]) { |
1203 | dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n" , reg); |
1204 | return -EINVAL; |
1205 | } |
1206 | track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp]; |
1207 | track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp]; |
1208 | ib[idx] = track->cb_color_base_last[tmp]; |
1209 | } else { |
1210 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1211 | if (r) { |
1212 | dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n" , reg); |
1213 | return -EINVAL; |
1214 | } |
1215 | track->cb_color_frag_bo[tmp] = reloc->robj; |
1216 | track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; |
1217 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1218 | } |
1219 | if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { |
1220 | track->cb_dirty = true; |
1221 | } |
1222 | break; |
1223 | case R_0280C0_CB_COLOR0_TILE: |
1224 | case R_0280C4_CB_COLOR1_TILE: |
1225 | case R_0280C8_CB_COLOR2_TILE: |
1226 | case R_0280CC_CB_COLOR3_TILE: |
1227 | case R_0280D0_CB_COLOR4_TILE: |
1228 | case R_0280D4_CB_COLOR5_TILE: |
1229 | case R_0280D8_CB_COLOR6_TILE: |
1230 | case R_0280DC_CB_COLOR7_TILE: |
1231 | tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4; |
1232 | if (!radeon_cs_packet_next_is_pkt3_nop(p)) { |
1233 | if (!track->cb_color_base_last[tmp]) { |
1234 | dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n" , reg); |
1235 | return -EINVAL; |
1236 | } |
1237 | track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp]; |
1238 | track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp]; |
1239 | ib[idx] = track->cb_color_base_last[tmp]; |
1240 | } else { |
1241 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1242 | if (r) { |
1243 | dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n" , reg); |
1244 | return -EINVAL; |
1245 | } |
1246 | track->cb_color_tile_bo[tmp] = reloc->robj; |
1247 | track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; |
1248 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1249 | } |
1250 | if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { |
1251 | track->cb_dirty = true; |
1252 | } |
1253 | break; |
1254 | case R_028100_CB_COLOR0_MASK: |
1255 | case R_028104_CB_COLOR1_MASK: |
1256 | case R_028108_CB_COLOR2_MASK: |
1257 | case R_02810C_CB_COLOR3_MASK: |
1258 | case R_028110_CB_COLOR4_MASK: |
1259 | case R_028114_CB_COLOR5_MASK: |
1260 | case R_028118_CB_COLOR6_MASK: |
1261 | case R_02811C_CB_COLOR7_MASK: |
1262 | tmp = (reg - R_028100_CB_COLOR0_MASK) / 4; |
1263 | track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx); |
1264 | if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { |
1265 | track->cb_dirty = true; |
1266 | } |
1267 | break; |
1268 | case CB_COLOR0_BASE: |
1269 | case CB_COLOR1_BASE: |
1270 | case CB_COLOR2_BASE: |
1271 | case CB_COLOR3_BASE: |
1272 | case CB_COLOR4_BASE: |
1273 | case CB_COLOR5_BASE: |
1274 | case CB_COLOR6_BASE: |
1275 | case CB_COLOR7_BASE: |
1276 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1277 | if (r) { |
1278 | dev_warn(p->dev, "bad SET_CONTEXT_REG " |
1279 | "0x%04X\n" , reg); |
1280 | return -EINVAL; |
1281 | } |
1282 | tmp = (reg - CB_COLOR0_BASE) / 4; |
1283 | track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; |
1284 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1285 | track->cb_color_base_last[tmp] = ib[idx]; |
1286 | track->cb_color_bo[tmp] = reloc->robj; |
1287 | track->cb_color_bo_mc[tmp] = reloc->gpu_offset; |
1288 | track->cb_dirty = true; |
1289 | break; |
1290 | case DB_DEPTH_BASE: |
1291 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1292 | if (r) { |
1293 | dev_warn(p->dev, "bad SET_CONTEXT_REG " |
1294 | "0x%04X\n" , reg); |
1295 | return -EINVAL; |
1296 | } |
1297 | track->db_offset = radeon_get_ib_value(p, idx) << 8; |
1298 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1299 | track->db_bo = reloc->robj; |
1300 | track->db_bo_mc = reloc->gpu_offset; |
1301 | track->db_dirty = true; |
1302 | break; |
1303 | case DB_HTILE_DATA_BASE: |
1304 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1305 | if (r) { |
1306 | dev_warn(p->dev, "bad SET_CONTEXT_REG " |
1307 | "0x%04X\n" , reg); |
1308 | return -EINVAL; |
1309 | } |
1310 | track->htile_offset = radeon_get_ib_value(p, idx) << 8; |
1311 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1312 | track->htile_bo = reloc->robj; |
1313 | track->db_dirty = true; |
1314 | break; |
1315 | case DB_HTILE_SURFACE: |
1316 | track->htile_surface = radeon_get_ib_value(p, idx); |
1317 | /* force 8x8 htile width and height */ |
1318 | ib[idx] |= 3; |
1319 | track->db_dirty = true; |
1320 | break; |
1321 | case SQ_PGM_START_FS: |
1322 | case SQ_PGM_START_ES: |
1323 | case SQ_PGM_START_VS: |
1324 | case SQ_PGM_START_GS: |
1325 | case SQ_PGM_START_PS: |
1326 | case SQ_ALU_CONST_CACHE_GS_0: |
1327 | case SQ_ALU_CONST_CACHE_GS_1: |
1328 | case SQ_ALU_CONST_CACHE_GS_2: |
1329 | case SQ_ALU_CONST_CACHE_GS_3: |
1330 | case SQ_ALU_CONST_CACHE_GS_4: |
1331 | case SQ_ALU_CONST_CACHE_GS_5: |
1332 | case SQ_ALU_CONST_CACHE_GS_6: |
1333 | case SQ_ALU_CONST_CACHE_GS_7: |
1334 | case SQ_ALU_CONST_CACHE_GS_8: |
1335 | case SQ_ALU_CONST_CACHE_GS_9: |
1336 | case SQ_ALU_CONST_CACHE_GS_10: |
1337 | case SQ_ALU_CONST_CACHE_GS_11: |
1338 | case SQ_ALU_CONST_CACHE_GS_12: |
1339 | case SQ_ALU_CONST_CACHE_GS_13: |
1340 | case SQ_ALU_CONST_CACHE_GS_14: |
1341 | case SQ_ALU_CONST_CACHE_GS_15: |
1342 | case SQ_ALU_CONST_CACHE_PS_0: |
1343 | case SQ_ALU_CONST_CACHE_PS_1: |
1344 | case SQ_ALU_CONST_CACHE_PS_2: |
1345 | case SQ_ALU_CONST_CACHE_PS_3: |
1346 | case SQ_ALU_CONST_CACHE_PS_4: |
1347 | case SQ_ALU_CONST_CACHE_PS_5: |
1348 | case SQ_ALU_CONST_CACHE_PS_6: |
1349 | case SQ_ALU_CONST_CACHE_PS_7: |
1350 | case SQ_ALU_CONST_CACHE_PS_8: |
1351 | case SQ_ALU_CONST_CACHE_PS_9: |
1352 | case SQ_ALU_CONST_CACHE_PS_10: |
1353 | case SQ_ALU_CONST_CACHE_PS_11: |
1354 | case SQ_ALU_CONST_CACHE_PS_12: |
1355 | case SQ_ALU_CONST_CACHE_PS_13: |
1356 | case SQ_ALU_CONST_CACHE_PS_14: |
1357 | case SQ_ALU_CONST_CACHE_PS_15: |
1358 | case SQ_ALU_CONST_CACHE_VS_0: |
1359 | case SQ_ALU_CONST_CACHE_VS_1: |
1360 | case SQ_ALU_CONST_CACHE_VS_2: |
1361 | case SQ_ALU_CONST_CACHE_VS_3: |
1362 | case SQ_ALU_CONST_CACHE_VS_4: |
1363 | case SQ_ALU_CONST_CACHE_VS_5: |
1364 | case SQ_ALU_CONST_CACHE_VS_6: |
1365 | case SQ_ALU_CONST_CACHE_VS_7: |
1366 | case SQ_ALU_CONST_CACHE_VS_8: |
1367 | case SQ_ALU_CONST_CACHE_VS_9: |
1368 | case SQ_ALU_CONST_CACHE_VS_10: |
1369 | case SQ_ALU_CONST_CACHE_VS_11: |
1370 | case SQ_ALU_CONST_CACHE_VS_12: |
1371 | case SQ_ALU_CONST_CACHE_VS_13: |
1372 | case SQ_ALU_CONST_CACHE_VS_14: |
1373 | case SQ_ALU_CONST_CACHE_VS_15: |
1374 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1375 | if (r) { |
1376 | dev_warn(p->dev, "bad SET_CONTEXT_REG " |
1377 | "0x%04X\n" , reg); |
1378 | return -EINVAL; |
1379 | } |
1380 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1381 | break; |
1382 | case SX_MEMORY_EXPORT_BASE: |
1383 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1384 | if (r) { |
1385 | dev_warn(p->dev, "bad SET_CONFIG_REG " |
1386 | "0x%04X\n" , reg); |
1387 | return -EINVAL; |
1388 | } |
1389 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1390 | break; |
1391 | case SX_MISC: |
1392 | track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; |
1393 | break; |
1394 | default: |
1395 | dev_warn(p->dev, "forbidden register 0x%08x at %d\n" , reg, idx); |
1396 | return -EINVAL; |
1397 | } |
1398 | return 0; |
1399 | } |
1400 | |
1401 | unsigned r600_mip_minify(unsigned size, unsigned level) |
1402 | { |
1403 | unsigned val; |
1404 | |
1405 | val = max(1U, size >> level); |
1406 | if (level > 0) |
1407 | val = roundup_pow_of_two(val); |
1408 | return val; |
1409 | } |
1410 | |
1411 | static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel, |
1412 | unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format, |
1413 | unsigned block_align, unsigned height_align, unsigned base_align, |
1414 | unsigned *l0_size, unsigned *mipmap_size) |
1415 | { |
1416 | unsigned offset, i, level; |
1417 | unsigned width, height, depth, size; |
1418 | unsigned blocksize; |
1419 | unsigned nbx, nby; |
1420 | unsigned nlevels = llevel - blevel + 1; |
1421 | |
1422 | *l0_size = -1; |
1423 | blocksize = r600_fmt_get_blocksize(format); |
1424 | |
1425 | w0 = r600_mip_minify(w0, 0); |
1426 | h0 = r600_mip_minify(h0, 0); |
1427 | d0 = r600_mip_minify(d0, 0); |
1428 | for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) { |
1429 | width = r600_mip_minify(w0, i); |
1430 | nbx = r600_fmt_get_nblocksx(format, width); |
1431 | |
1432 | nbx = round_up(nbx, block_align); |
1433 | |
1434 | height = r600_mip_minify(h0, i); |
1435 | nby = r600_fmt_get_nblocksy(format, height); |
1436 | nby = round_up(nby, height_align); |
1437 | |
1438 | depth = r600_mip_minify(d0, i); |
1439 | |
1440 | size = nbx * nby * blocksize * nsamples; |
1441 | if (nfaces) |
1442 | size *= nfaces; |
1443 | else |
1444 | size *= depth; |
1445 | |
1446 | if (i == 0) |
1447 | *l0_size = size; |
1448 | |
1449 | if (i == 0 || i == 1) |
1450 | offset = round_up(offset, base_align); |
1451 | |
1452 | offset += size; |
1453 | } |
1454 | *mipmap_size = offset; |
1455 | if (llevel == 0) |
1456 | *mipmap_size = *l0_size; |
1457 | if (!blevel) |
1458 | *mipmap_size -= *l0_size; |
1459 | } |
1460 | |
1461 | /** |
1462 | * r600_check_texture_resource() - check if register is authorized or not |
1463 | * @p: parser structure holding parsing context |
1464 | * @idx: index into the cs buffer |
1465 | * @texture: texture's bo structure |
1466 | * @mipmap: mipmap's bo structure |
1467 | * |
1468 | * This function will check that the resource has valid field and that |
1469 | * the texture and mipmap bo object are big enough to cover this resource. |
1470 | */ |
1471 | static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, |
1472 | struct radeon_bo *texture, |
1473 | struct radeon_bo *mipmap, |
1474 | u64 base_offset, |
1475 | u64 mip_offset, |
1476 | u32 tiling_flags) |
1477 | { |
1478 | struct r600_cs_track *track = p->track; |
1479 | u32 dim, nfaces, llevel, blevel, w0, h0, d0; |
1480 | u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5; |
1481 | u32 height_align, pitch, pitch_align, depth_align; |
1482 | u32 barray, larray; |
1483 | u64 base_align; |
1484 | struct array_mode_checker array_check; |
1485 | u32 format; |
1486 | bool is_array; |
1487 | |
1488 | /* on legacy kernel we don't perform advanced check */ |
1489 | if (p->rdev == NULL) |
1490 | return 0; |
1491 | |
1492 | /* convert to bytes */ |
1493 | base_offset <<= 8; |
1494 | mip_offset <<= 8; |
1495 | |
1496 | word0 = radeon_get_ib_value(p, idx + 0); |
1497 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1498 | if (tiling_flags & RADEON_TILING_MACRO) |
1499 | word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); |
1500 | else if (tiling_flags & RADEON_TILING_MICRO) |
1501 | word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); |
1502 | } |
1503 | word1 = radeon_get_ib_value(p, idx + 1); |
1504 | word2 = radeon_get_ib_value(p, idx + 2) << 8; |
1505 | word3 = radeon_get_ib_value(p, idx + 3) << 8; |
1506 | word4 = radeon_get_ib_value(p, idx + 4); |
1507 | word5 = radeon_get_ib_value(p, idx + 5); |
1508 | dim = G_038000_DIM(word0); |
1509 | w0 = G_038000_TEX_WIDTH(word0) + 1; |
1510 | pitch = (G_038000_PITCH(word0) + 1) * 8; |
1511 | h0 = G_038004_TEX_HEIGHT(word1) + 1; |
1512 | d0 = G_038004_TEX_DEPTH(word1); |
1513 | format = G_038004_DATA_FORMAT(word1); |
1514 | blevel = G_038010_BASE_LEVEL(word4); |
1515 | llevel = G_038014_LAST_LEVEL(word5); |
1516 | /* pitch in texels */ |
1517 | array_check.array_mode = G_038000_TILE_MODE(word0); |
1518 | array_check.group_size = track->group_size; |
1519 | array_check.nbanks = track->nbanks; |
1520 | array_check.npipes = track->npipes; |
1521 | array_check.nsamples = 1; |
1522 | array_check.blocksize = r600_fmt_get_blocksize(format); |
1523 | nfaces = 1; |
1524 | is_array = false; |
1525 | switch (dim) { |
1526 | case V_038000_SQ_TEX_DIM_1D: |
1527 | case V_038000_SQ_TEX_DIM_2D: |
1528 | case V_038000_SQ_TEX_DIM_3D: |
1529 | break; |
1530 | case V_038000_SQ_TEX_DIM_CUBEMAP: |
1531 | if (p->family >= CHIP_RV770) |
1532 | nfaces = 8; |
1533 | else |
1534 | nfaces = 6; |
1535 | break; |
1536 | case V_038000_SQ_TEX_DIM_1D_ARRAY: |
1537 | case V_038000_SQ_TEX_DIM_2D_ARRAY: |
1538 | is_array = true; |
1539 | break; |
1540 | case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA: |
1541 | is_array = true; |
1542 | /* fall through */ |
1543 | case V_038000_SQ_TEX_DIM_2D_MSAA: |
1544 | array_check.nsamples = 1 << llevel; |
1545 | llevel = 0; |
1546 | break; |
1547 | default: |
1548 | dev_warn(p->dev, "this kernel doesn't support %d texture dim\n" , G_038000_DIM(word0)); |
1549 | return -EINVAL; |
1550 | } |
1551 | if (!r600_fmt_is_valid_texture(format, p->family)) { |
1552 | dev_warn(p->dev, "%s:%d texture invalid format %d\n" , |
1553 | __func__, __LINE__, format); |
1554 | return -EINVAL; |
1555 | } |
1556 | |
1557 | if (r600_get_array_mode_alignment(&array_check, |
1558 | &pitch_align, &height_align, &depth_align, &base_align)) { |
1559 | dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n" , |
1560 | __func__, __LINE__, G_038000_TILE_MODE(word0)); |
1561 | return -EINVAL; |
1562 | } |
1563 | |
1564 | /* XXX check height as well... */ |
1565 | |
1566 | if (!IS_ALIGNED(pitch, pitch_align)) { |
1567 | dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n" , |
1568 | __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0)); |
1569 | return -EINVAL; |
1570 | } |
1571 | if (!IS_ALIGNED(base_offset, base_align)) { |
1572 | dev_warn(p->dev, "%s:%d tex base offset (0x%" PRIx64", 0x%" PRIx64", %d) invalid\n" , |
1573 | __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0)); |
1574 | return -EINVAL; |
1575 | } |
1576 | if (!IS_ALIGNED(mip_offset, base_align)) { |
1577 | dev_warn(p->dev, "%s:%d tex mip offset (0x%" PRIx64", 0x%" PRIx64", %d) invalid\n" , |
1578 | __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0)); |
1579 | return -EINVAL; |
1580 | } |
1581 | |
1582 | if (blevel > llevel) { |
1583 | dev_warn(p->dev, "texture blevel %d > llevel %d\n" , |
1584 | blevel, llevel); |
1585 | } |
1586 | if (is_array) { |
1587 | barray = G_038014_BASE_ARRAY(word5); |
1588 | larray = G_038014_LAST_ARRAY(word5); |
1589 | |
1590 | nfaces = larray - barray + 1; |
1591 | } |
1592 | r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format, |
1593 | pitch_align, height_align, base_align, |
1594 | &l0_size, &mipmap_size); |
1595 | /* using get ib will give us the offset into the texture bo */ |
1596 | if ((l0_size + word2) > radeon_bo_size(texture)) { |
1597 | dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n" , |
1598 | w0, h0, pitch_align, height_align, |
1599 | array_check.array_mode, format, word2, |
1600 | l0_size, radeon_bo_size(texture)); |
1601 | dev_warn(p->dev, "alignments %d %d %d %" PRIu64"\n" , pitch, pitch_align, height_align, base_align); |
1602 | return -EINVAL; |
1603 | } |
1604 | /* using get ib will give us the offset into the mipmap bo */ |
1605 | if ((mipmap_size + word3) > radeon_bo_size(mipmap)) { |
1606 | /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", |
1607 | w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/ |
1608 | } |
1609 | return 0; |
1610 | } |
1611 | |
1612 | static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) |
1613 | { |
1614 | u32 m, i; |
1615 | |
1616 | i = (reg >> 7); |
1617 | if (i >= ARRAY_SIZE(r600_reg_safe_bm)) { |
1618 | dev_warn(p->dev, "forbidden register 0x%08x at %d\n" , reg, idx); |
1619 | return false; |
1620 | } |
1621 | m = 1 << ((reg >> 2) & 31); |
1622 | if (!(r600_reg_safe_bm[i] & m)) |
1623 | return true; |
1624 | dev_warn(p->dev, "forbidden register 0x%08x at %d\n" , reg, idx); |
1625 | return false; |
1626 | } |
1627 | |
1628 | static int r600_packet3_check(struct radeon_cs_parser *p, |
1629 | struct radeon_cs_packet *pkt) |
1630 | { |
1631 | struct radeon_cs_reloc *reloc; |
1632 | struct r600_cs_track *track; |
1633 | volatile u32 *ib; |
1634 | unsigned idx; |
1635 | unsigned i; |
1636 | unsigned start_reg, end_reg, reg; |
1637 | int r; |
1638 | u32 idx_value; |
1639 | |
1640 | track = (struct r600_cs_track *)p->track; |
1641 | ib = p->ib.ptr; |
1642 | idx = pkt->idx + 1; |
1643 | idx_value = radeon_get_ib_value(p, idx); |
1644 | |
1645 | switch (pkt->opcode) { |
1646 | case PACKET3_SET_PREDICATION: |
1647 | { |
1648 | int pred_op; |
1649 | int tmp; |
1650 | uint64_t offset; |
1651 | |
1652 | if (pkt->count != 1) { |
1653 | DRM_ERROR("bad SET PREDICATION\n" ); |
1654 | return -EINVAL; |
1655 | } |
1656 | |
1657 | tmp = radeon_get_ib_value(p, idx + 1); |
1658 | pred_op = (tmp >> 16) & 0x7; |
1659 | |
1660 | /* for the clear predicate operation */ |
1661 | if (pred_op == 0) |
1662 | return 0; |
1663 | |
1664 | if (pred_op > 2) { |
1665 | DRM_ERROR("bad SET PREDICATION operation %d\n" , pred_op); |
1666 | return -EINVAL; |
1667 | } |
1668 | |
1669 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1670 | if (r) { |
1671 | DRM_ERROR("bad SET PREDICATION\n" ); |
1672 | return -EINVAL; |
1673 | } |
1674 | |
1675 | offset = reloc->gpu_offset + |
1676 | (idx_value & 0xfffffff0) + |
1677 | ((u64)(tmp & 0xff) << 32); |
1678 | |
1679 | ib[idx + 0] = offset; |
1680 | ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); |
1681 | } |
1682 | break; |
1683 | |
1684 | case PACKET3_START_3D_CMDBUF: |
1685 | if (p->family >= CHIP_RV770 || pkt->count) { |
1686 | DRM_ERROR("bad START_3D\n" ); |
1687 | return -EINVAL; |
1688 | } |
1689 | break; |
1690 | case PACKET3_CONTEXT_CONTROL: |
1691 | if (pkt->count != 1) { |
1692 | DRM_ERROR("bad CONTEXT_CONTROL\n" ); |
1693 | return -EINVAL; |
1694 | } |
1695 | break; |
1696 | case PACKET3_INDEX_TYPE: |
1697 | case PACKET3_NUM_INSTANCES: |
1698 | if (pkt->count) { |
1699 | DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n" ); |
1700 | return -EINVAL; |
1701 | } |
1702 | break; |
1703 | case PACKET3_DRAW_INDEX: |
1704 | { |
1705 | uint64_t offset; |
1706 | if (pkt->count != 3) { |
1707 | DRM_ERROR("bad DRAW_INDEX\n" ); |
1708 | return -EINVAL; |
1709 | } |
1710 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1711 | if (r) { |
1712 | DRM_ERROR("bad DRAW_INDEX\n" ); |
1713 | return -EINVAL; |
1714 | } |
1715 | |
1716 | offset = reloc->gpu_offset + |
1717 | idx_value + |
1718 | ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); |
1719 | |
1720 | ib[idx+0] = offset; |
1721 | ib[idx+1] = upper_32_bits(offset) & 0xff; |
1722 | |
1723 | r = r600_cs_track_check(p); |
1724 | if (r) { |
1725 | dev_warn(p->dev, "%s:%d invalid cmd stream\n" , __func__, __LINE__); |
1726 | return r; |
1727 | } |
1728 | break; |
1729 | } |
1730 | case PACKET3_DRAW_INDEX_AUTO: |
1731 | if (pkt->count != 1) { |
1732 | DRM_ERROR("bad DRAW_INDEX_AUTO\n" ); |
1733 | return -EINVAL; |
1734 | } |
1735 | r = r600_cs_track_check(p); |
1736 | if (r) { |
1737 | dev_warn(p->dev, "%s:%d invalid cmd stream %d\n" , __func__, __LINE__, idx); |
1738 | return r; |
1739 | } |
1740 | break; |
1741 | case PACKET3_DRAW_INDEX_IMMD_BE: |
1742 | case PACKET3_DRAW_INDEX_IMMD: |
1743 | if (pkt->count < 2) { |
1744 | DRM_ERROR("bad DRAW_INDEX_IMMD\n" ); |
1745 | return -EINVAL; |
1746 | } |
1747 | r = r600_cs_track_check(p); |
1748 | if (r) { |
1749 | dev_warn(p->dev, "%s:%d invalid cmd stream\n" , __func__, __LINE__); |
1750 | return r; |
1751 | } |
1752 | break; |
1753 | case PACKET3_WAIT_REG_MEM: |
1754 | if (pkt->count != 5) { |
1755 | DRM_ERROR("bad WAIT_REG_MEM\n" ); |
1756 | return -EINVAL; |
1757 | } |
1758 | /* bit 4 is reg (0) or mem (1) */ |
1759 | if (idx_value & 0x10) { |
1760 | uint64_t offset; |
1761 | |
1762 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1763 | if (r) { |
1764 | DRM_ERROR("bad WAIT_REG_MEM\n" ); |
1765 | return -EINVAL; |
1766 | } |
1767 | |
1768 | offset = reloc->gpu_offset + |
1769 | (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + |
1770 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
1771 | |
1772 | ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0); |
1773 | ib[idx+2] = upper_32_bits(offset) & 0xff; |
1774 | } else if (idx_value & 0x100) { |
1775 | DRM_ERROR("cannot use PFP on REG wait\n" ); |
1776 | return -EINVAL; |
1777 | } |
1778 | break; |
1779 | case PACKET3_CP_DMA: |
1780 | { |
1781 | u32 command, size; |
1782 | u64 offset, tmp; |
1783 | if (pkt->count != 4) { |
1784 | DRM_ERROR("bad CP DMA\n" ); |
1785 | return -EINVAL; |
1786 | } |
1787 | command = radeon_get_ib_value(p, idx+4); |
1788 | size = command & 0x1fffff; |
1789 | if (command & PACKET3_CP_DMA_CMD_SAS) { |
1790 | /* src address space is register */ |
1791 | DRM_ERROR("CP DMA SAS not supported\n" ); |
1792 | return -EINVAL; |
1793 | } else { |
1794 | if (command & PACKET3_CP_DMA_CMD_SAIC) { |
1795 | DRM_ERROR("CP DMA SAIC only supported for registers\n" ); |
1796 | return -EINVAL; |
1797 | } |
1798 | /* src address space is memory */ |
1799 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1800 | if (r) { |
1801 | DRM_ERROR("bad CP DMA SRC\n" ); |
1802 | return -EINVAL; |
1803 | } |
1804 | |
1805 | tmp = radeon_get_ib_value(p, idx) + |
1806 | ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); |
1807 | |
1808 | offset = reloc->gpu_offset + tmp; |
1809 | |
1810 | if ((tmp + size) > radeon_bo_size(reloc->robj)) { |
1811 | dev_warn(p->dev, "CP DMA src buffer too small (%" PRIu64" %lu)\n" , |
1812 | tmp + size, radeon_bo_size(reloc->robj)); |
1813 | return -EINVAL; |
1814 | } |
1815 | |
1816 | ib[idx] = offset; |
1817 | ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); |
1818 | } |
1819 | if (command & PACKET3_CP_DMA_CMD_DAS) { |
1820 | /* dst address space is register */ |
1821 | DRM_ERROR("CP DMA DAS not supported\n" ); |
1822 | return -EINVAL; |
1823 | } else { |
1824 | /* dst address space is memory */ |
1825 | if (command & PACKET3_CP_DMA_CMD_DAIC) { |
1826 | DRM_ERROR("CP DMA DAIC only supported for registers\n" ); |
1827 | return -EINVAL; |
1828 | } |
1829 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1830 | if (r) { |
1831 | DRM_ERROR("bad CP DMA DST\n" ); |
1832 | return -EINVAL; |
1833 | } |
1834 | |
1835 | tmp = radeon_get_ib_value(p, idx+2) + |
1836 | ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); |
1837 | |
1838 | offset = reloc->gpu_offset + tmp; |
1839 | |
1840 | if ((tmp + size) > radeon_bo_size(reloc->robj)) { |
1841 | dev_warn(p->dev, "CP DMA dst buffer too small (%" PRIu64" %lu)\n" , |
1842 | tmp + size, radeon_bo_size(reloc->robj)); |
1843 | return -EINVAL; |
1844 | } |
1845 | |
1846 | ib[idx+2] = offset; |
1847 | ib[idx+3] = upper_32_bits(offset) & 0xff; |
1848 | } |
1849 | break; |
1850 | } |
1851 | case PACKET3_SURFACE_SYNC: |
1852 | if (pkt->count != 3) { |
1853 | DRM_ERROR("bad SURFACE_SYNC\n" ); |
1854 | return -EINVAL; |
1855 | } |
1856 | /* 0xffffffff/0x0 is flush all cache flag */ |
1857 | if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || |
1858 | radeon_get_ib_value(p, idx + 2) != 0) { |
1859 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1860 | if (r) { |
1861 | DRM_ERROR("bad SURFACE_SYNC\n" ); |
1862 | return -EINVAL; |
1863 | } |
1864 | ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1865 | } |
1866 | break; |
1867 | case PACKET3_EVENT_WRITE: |
1868 | if (pkt->count != 2 && pkt->count != 0) { |
1869 | DRM_ERROR("bad EVENT_WRITE\n" ); |
1870 | return -EINVAL; |
1871 | } |
1872 | if (pkt->count) { |
1873 | uint64_t offset; |
1874 | |
1875 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1876 | if (r) { |
1877 | DRM_ERROR("bad EVENT_WRITE\n" ); |
1878 | return -EINVAL; |
1879 | } |
1880 | offset = reloc->gpu_offset + |
1881 | (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + |
1882 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
1883 | |
1884 | ib[idx+1] = offset & 0xfffffff8; |
1885 | ib[idx+2] = upper_32_bits(offset) & 0xff; |
1886 | } |
1887 | break; |
1888 | case PACKET3_EVENT_WRITE_EOP: |
1889 | { |
1890 | uint64_t offset; |
1891 | |
1892 | if (pkt->count != 4) { |
1893 | DRM_ERROR("bad EVENT_WRITE_EOP\n" ); |
1894 | return -EINVAL; |
1895 | } |
1896 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1897 | if (r) { |
1898 | DRM_ERROR("bad EVENT_WRITE\n" ); |
1899 | return -EINVAL; |
1900 | } |
1901 | |
1902 | offset = reloc->gpu_offset + |
1903 | (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + |
1904 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
1905 | |
1906 | ib[idx+1] = offset & 0xfffffffc; |
1907 | ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); |
1908 | break; |
1909 | } |
1910 | case PACKET3_SET_CONFIG_REG: |
1911 | start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; |
1912 | end_reg = 4 * pkt->count + start_reg - 4; |
1913 | if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) || |
1914 | (start_reg >= PACKET3_SET_CONFIG_REG_END) || |
1915 | (end_reg >= PACKET3_SET_CONFIG_REG_END)) { |
1916 | DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n" ); |
1917 | return -EINVAL; |
1918 | } |
1919 | for (i = 0; i < pkt->count; i++) { |
1920 | reg = start_reg + (4 * i); |
1921 | r = r600_cs_check_reg(p, reg, idx+1+i); |
1922 | if (r) |
1923 | return r; |
1924 | } |
1925 | break; |
1926 | case PACKET3_SET_CONTEXT_REG: |
1927 | start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; |
1928 | end_reg = 4 * pkt->count + start_reg - 4; |
1929 | if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) || |
1930 | (start_reg >= PACKET3_SET_CONTEXT_REG_END) || |
1931 | (end_reg >= PACKET3_SET_CONTEXT_REG_END)) { |
1932 | DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n" ); |
1933 | return -EINVAL; |
1934 | } |
1935 | for (i = 0; i < pkt->count; i++) { |
1936 | reg = start_reg + (4 * i); |
1937 | r = r600_cs_check_reg(p, reg, idx+1+i); |
1938 | if (r) |
1939 | return r; |
1940 | } |
1941 | break; |
1942 | case PACKET3_SET_RESOURCE: |
1943 | if (pkt->count % 7) { |
1944 | DRM_ERROR("bad SET_RESOURCE\n" ); |
1945 | return -EINVAL; |
1946 | } |
1947 | start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; |
1948 | end_reg = 4 * pkt->count + start_reg - 4; |
1949 | if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) || |
1950 | (start_reg >= PACKET3_SET_RESOURCE_END) || |
1951 | (end_reg >= PACKET3_SET_RESOURCE_END)) { |
1952 | DRM_ERROR("bad SET_RESOURCE\n" ); |
1953 | return -EINVAL; |
1954 | } |
1955 | for (i = 0; i < (pkt->count / 7); i++) { |
1956 | struct radeon_bo *texture, *mipmap; |
1957 | u32 size, offset, base_offset, mip_offset; |
1958 | |
1959 | switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { |
1960 | case SQ_TEX_VTX_VALID_TEXTURE: |
1961 | /* tex base */ |
1962 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1963 | if (r) { |
1964 | DRM_ERROR("bad SET_RESOURCE\n" ); |
1965 | return -EINVAL; |
1966 | } |
1967 | base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1968 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1969 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
1970 | ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); |
1971 | else if (reloc->tiling_flags & RADEON_TILING_MICRO) |
1972 | ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); |
1973 | } |
1974 | texture = reloc->robj; |
1975 | /* tex mip base */ |
1976 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1977 | if (r) { |
1978 | DRM_ERROR("bad SET_RESOURCE\n" ); |
1979 | return -EINVAL; |
1980 | } |
1981 | mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1982 | mipmap = reloc->robj; |
1983 | r = r600_check_texture_resource(p, idx+(i*7)+1, |
1984 | texture, mipmap, |
1985 | base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), |
1986 | mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3), |
1987 | reloc->tiling_flags); |
1988 | if (r) |
1989 | return r; |
1990 | ib[idx+1+(i*7)+2] += base_offset; |
1991 | ib[idx+1+(i*7)+3] += mip_offset; |
1992 | break; |
1993 | case SQ_TEX_VTX_VALID_BUFFER: |
1994 | { |
1995 | uint64_t offset64; |
1996 | /* vtx base */ |
1997 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
1998 | if (r) { |
1999 | DRM_ERROR("bad SET_RESOURCE\n" ); |
2000 | return -EINVAL; |
2001 | } |
2002 | offset = radeon_get_ib_value(p, idx+1+(i*7)+0); |
2003 | size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1; |
2004 | if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { |
2005 | /* force size to size of the buffer */ |
2006 | dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n" , |
2007 | size + offset, radeon_bo_size(reloc->robj)); |
2008 | ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset; |
2009 | } |
2010 | |
2011 | offset64 = reloc->gpu_offset + offset; |
2012 | ib[idx+1+(i*8)+0] = offset64; |
2013 | ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | |
2014 | (upper_32_bits(offset64) & 0xff); |
2015 | break; |
2016 | } |
2017 | case SQ_TEX_VTX_INVALID_TEXTURE: |
2018 | case SQ_TEX_VTX_INVALID_BUFFER: |
2019 | default: |
2020 | DRM_ERROR("bad SET_RESOURCE\n" ); |
2021 | return -EINVAL; |
2022 | } |
2023 | } |
2024 | break; |
2025 | case PACKET3_SET_ALU_CONST: |
2026 | if (track->sq_config & DX9_CONSTS) { |
2027 | start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET; |
2028 | end_reg = 4 * pkt->count + start_reg - 4; |
2029 | if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) || |
2030 | (start_reg >= PACKET3_SET_ALU_CONST_END) || |
2031 | (end_reg >= PACKET3_SET_ALU_CONST_END)) { |
2032 | DRM_ERROR("bad SET_ALU_CONST\n" ); |
2033 | return -EINVAL; |
2034 | } |
2035 | } |
2036 | break; |
2037 | case PACKET3_SET_BOOL_CONST: |
2038 | start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET; |
2039 | end_reg = 4 * pkt->count + start_reg - 4; |
2040 | if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) || |
2041 | (start_reg >= PACKET3_SET_BOOL_CONST_END) || |
2042 | (end_reg >= PACKET3_SET_BOOL_CONST_END)) { |
2043 | DRM_ERROR("bad SET_BOOL_CONST\n" ); |
2044 | return -EINVAL; |
2045 | } |
2046 | break; |
2047 | case PACKET3_SET_LOOP_CONST: |
2048 | start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET; |
2049 | end_reg = 4 * pkt->count + start_reg - 4; |
2050 | if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) || |
2051 | (start_reg >= PACKET3_SET_LOOP_CONST_END) || |
2052 | (end_reg >= PACKET3_SET_LOOP_CONST_END)) { |
2053 | DRM_ERROR("bad SET_LOOP_CONST\n" ); |
2054 | return -EINVAL; |
2055 | } |
2056 | break; |
2057 | case PACKET3_SET_CTL_CONST: |
2058 | start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET; |
2059 | end_reg = 4 * pkt->count + start_reg - 4; |
2060 | if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) || |
2061 | (start_reg >= PACKET3_SET_CTL_CONST_END) || |
2062 | (end_reg >= PACKET3_SET_CTL_CONST_END)) { |
2063 | DRM_ERROR("bad SET_CTL_CONST\n" ); |
2064 | return -EINVAL; |
2065 | } |
2066 | break; |
2067 | case PACKET3_SET_SAMPLER: |
2068 | if (pkt->count % 3) { |
2069 | DRM_ERROR("bad SET_SAMPLER\n" ); |
2070 | return -EINVAL; |
2071 | } |
2072 | start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET; |
2073 | end_reg = 4 * pkt->count + start_reg - 4; |
2074 | if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) || |
2075 | (start_reg >= PACKET3_SET_SAMPLER_END) || |
2076 | (end_reg >= PACKET3_SET_SAMPLER_END)) { |
2077 | DRM_ERROR("bad SET_SAMPLER\n" ); |
2078 | return -EINVAL; |
2079 | } |
2080 | break; |
2081 | case PACKET3_STRMOUT_BASE_UPDATE: |
2082 | /* RS780 and RS880 also need this */ |
2083 | if (p->family < CHIP_RS780) { |
2084 | DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n" ); |
2085 | return -EINVAL; |
2086 | } |
2087 | if (pkt->count != 1) { |
2088 | DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n" ); |
2089 | return -EINVAL; |
2090 | } |
2091 | if (idx_value > 3) { |
2092 | DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n" ); |
2093 | return -EINVAL; |
2094 | } |
2095 | { |
2096 | u64 offset; |
2097 | |
2098 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
2099 | if (r) { |
2100 | DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n" ); |
2101 | return -EINVAL; |
2102 | } |
2103 | |
2104 | if (reloc->robj != track->vgt_strmout_bo[idx_value]) { |
2105 | DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n" ); |
2106 | return -EINVAL; |
2107 | } |
2108 | |
2109 | offset = radeon_get_ib_value(p, idx+1) << 8; |
2110 | if (offset != track->vgt_strmout_bo_offset[idx_value]) { |
2111 | DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%" PRIx64", 0x%x\n" , |
2112 | offset, track->vgt_strmout_bo_offset[idx_value]); |
2113 | return -EINVAL; |
2114 | } |
2115 | |
2116 | if ((offset + 4) > radeon_bo_size(reloc->robj)) { |
2117 | DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%" PRIx64", 0x%lx\n" , |
2118 | offset + 4, radeon_bo_size(reloc->robj)); |
2119 | return -EINVAL; |
2120 | } |
2121 | ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
2122 | } |
2123 | break; |
2124 | case PACKET3_SURFACE_BASE_UPDATE: |
2125 | if (p->family >= CHIP_RV770 || p->family == CHIP_R600) { |
2126 | DRM_ERROR("bad SURFACE_BASE_UPDATE\n" ); |
2127 | return -EINVAL; |
2128 | } |
2129 | if (pkt->count) { |
2130 | DRM_ERROR("bad SURFACE_BASE_UPDATE\n" ); |
2131 | return -EINVAL; |
2132 | } |
2133 | break; |
2134 | case PACKET3_STRMOUT_BUFFER_UPDATE: |
2135 | if (pkt->count != 4) { |
2136 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n" ); |
2137 | return -EINVAL; |
2138 | } |
2139 | /* Updating memory at DST_ADDRESS. */ |
2140 | if (idx_value & 0x1) { |
2141 | u64 offset; |
2142 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
2143 | if (r) { |
2144 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n" ); |
2145 | return -EINVAL; |
2146 | } |
2147 | offset = radeon_get_ib_value(p, idx+1); |
2148 | offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; |
2149 | if ((offset + 4) > radeon_bo_size(reloc->robj)) { |
2150 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%" PRIx64", 0x%lx\n" , |
2151 | offset + 4, radeon_bo_size(reloc->robj)); |
2152 | return -EINVAL; |
2153 | } |
2154 | offset += reloc->gpu_offset; |
2155 | ib[idx+1] = offset; |
2156 | ib[idx+2] = upper_32_bits(offset) & 0xff; |
2157 | } |
2158 | /* Reading data from SRC_ADDRESS. */ |
2159 | if (((idx_value >> 1) & 0x3) == 2) { |
2160 | u64 offset; |
2161 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
2162 | if (r) { |
2163 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n" ); |
2164 | return -EINVAL; |
2165 | } |
2166 | offset = radeon_get_ib_value(p, idx+3); |
2167 | offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; |
2168 | if ((offset + 4) > radeon_bo_size(reloc->robj)) { |
2169 | DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%" PRIx64", 0x%lx\n" , |
2170 | offset + 4, radeon_bo_size(reloc->robj)); |
2171 | return -EINVAL; |
2172 | } |
2173 | offset += reloc->gpu_offset; |
2174 | ib[idx+3] = offset; |
2175 | ib[idx+4] = upper_32_bits(offset) & 0xff; |
2176 | } |
2177 | break; |
2178 | case PACKET3_MEM_WRITE: |
2179 | { |
2180 | u64 offset; |
2181 | |
2182 | if (pkt->count != 3) { |
2183 | DRM_ERROR("bad MEM_WRITE (invalid count)\n" ); |
2184 | return -EINVAL; |
2185 | } |
2186 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
2187 | if (r) { |
2188 | DRM_ERROR("bad MEM_WRITE (missing reloc)\n" ); |
2189 | return -EINVAL; |
2190 | } |
2191 | offset = radeon_get_ib_value(p, idx+0); |
2192 | offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; |
2193 | if (offset & 0x7) { |
2194 | DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n" ); |
2195 | return -EINVAL; |
2196 | } |
2197 | if ((offset + 8) > radeon_bo_size(reloc->robj)) { |
2198 | DRM_ERROR("bad MEM_WRITE bo too small: 0x%" PRIx64", 0x%lx\n" , |
2199 | offset + 8, radeon_bo_size(reloc->robj)); |
2200 | return -EINVAL; |
2201 | } |
2202 | offset += reloc->gpu_offset; |
2203 | ib[idx+0] = offset; |
2204 | ib[idx+1] = upper_32_bits(offset) & 0xff; |
2205 | break; |
2206 | } |
2207 | case PACKET3_COPY_DW: |
2208 | if (pkt->count != 4) { |
2209 | DRM_ERROR("bad COPY_DW (invalid count)\n" ); |
2210 | return -EINVAL; |
2211 | } |
2212 | if (idx_value & 0x1) { |
2213 | u64 offset; |
2214 | /* SRC is memory. */ |
2215 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
2216 | if (r) { |
2217 | DRM_ERROR("bad COPY_DW (missing src reloc)\n" ); |
2218 | return -EINVAL; |
2219 | } |
2220 | offset = radeon_get_ib_value(p, idx+1); |
2221 | offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; |
2222 | if ((offset + 4) > radeon_bo_size(reloc->robj)) { |
2223 | DRM_ERROR("bad COPY_DW src bo too small: 0x%" PRIx64", 0x%lx\n" , |
2224 | offset + 4, radeon_bo_size(reloc->robj)); |
2225 | return -EINVAL; |
2226 | } |
2227 | offset += reloc->gpu_offset; |
2228 | ib[idx+1] = offset; |
2229 | ib[idx+2] = upper_32_bits(offset) & 0xff; |
2230 | } else { |
2231 | /* SRC is a reg. */ |
2232 | reg = radeon_get_ib_value(p, idx+1) << 2; |
2233 | if (!r600_is_safe_reg(p, reg, idx+1)) |
2234 | return -EINVAL; |
2235 | } |
2236 | if (idx_value & 0x2) { |
2237 | u64 offset; |
2238 | /* DST is memory. */ |
2239 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
2240 | if (r) { |
2241 | DRM_ERROR("bad COPY_DW (missing dst reloc)\n" ); |
2242 | return -EINVAL; |
2243 | } |
2244 | offset = radeon_get_ib_value(p, idx+3); |
2245 | offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; |
2246 | if ((offset + 4) > radeon_bo_size(reloc->robj)) { |
2247 | DRM_ERROR("bad COPY_DW dst bo too small: 0x%" PRIx64", 0x%lx\n" , |
2248 | offset + 4, radeon_bo_size(reloc->robj)); |
2249 | return -EINVAL; |
2250 | } |
2251 | offset += reloc->gpu_offset; |
2252 | ib[idx+3] = offset; |
2253 | ib[idx+4] = upper_32_bits(offset) & 0xff; |
2254 | } else { |
2255 | /* DST is a reg. */ |
2256 | reg = radeon_get_ib_value(p, idx+3) << 2; |
2257 | if (!r600_is_safe_reg(p, reg, idx+3)) |
2258 | return -EINVAL; |
2259 | } |
2260 | break; |
2261 | case PACKET3_NOP: |
2262 | break; |
2263 | default: |
2264 | DRM_ERROR("Packet3 opcode %x not supported\n" , pkt->opcode); |
2265 | return -EINVAL; |
2266 | } |
2267 | return 0; |
2268 | } |
2269 | |
2270 | int r600_cs_parse(struct radeon_cs_parser *p) |
2271 | { |
2272 | struct radeon_cs_packet pkt; |
2273 | struct r600_cs_track *track; |
2274 | int r; |
2275 | |
2276 | if (p->track == NULL) { |
2277 | /* initialize tracker, we are in kms */ |
2278 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
2279 | if (track == NULL) |
2280 | return -ENOMEM; |
2281 | r600_cs_track_init(track); |
2282 | if (p->rdev->family < CHIP_RV770) { |
2283 | track->npipes = p->rdev->config.r600.tiling_npipes; |
2284 | track->nbanks = p->rdev->config.r600.tiling_nbanks; |
2285 | track->group_size = p->rdev->config.r600.tiling_group_size; |
2286 | } else if (p->rdev->family <= CHIP_RV740) { |
2287 | track->npipes = p->rdev->config.rv770.tiling_npipes; |
2288 | track->nbanks = p->rdev->config.rv770.tiling_nbanks; |
2289 | track->group_size = p->rdev->config.rv770.tiling_group_size; |
2290 | } |
2291 | p->track = track; |
2292 | } |
2293 | do { |
2294 | r = radeon_cs_packet_parse(p, &pkt, p->idx); |
2295 | if (r) { |
2296 | kfree(p->track); |
2297 | p->track = NULL; |
2298 | return r; |
2299 | } |
2300 | p->idx += pkt.count + 2; |
2301 | switch (pkt.type) { |
2302 | case RADEON_PACKET_TYPE0: |
2303 | r = r600_cs_parse_packet0(p, &pkt); |
2304 | break; |
2305 | case RADEON_PACKET_TYPE2: |
2306 | break; |
2307 | case RADEON_PACKET_TYPE3: |
2308 | r = r600_packet3_check(p, &pkt); |
2309 | break; |
2310 | default: |
2311 | DRM_ERROR("Unknown packet type %d !\n" , pkt.type); |
2312 | kfree(p->track); |
2313 | p->track = NULL; |
2314 | return -EINVAL; |
2315 | } |
2316 | if (r) { |
2317 | kfree(p->track); |
2318 | p->track = NULL; |
2319 | return r; |
2320 | } |
2321 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
2322 | #if 0 |
2323 | for (r = 0; r < p->ib.length_dw; r++) { |
2324 | printk(KERN_INFO "%05d 0x%08X\n" , r, p->ib.ptr[r]); |
2325 | mdelay(1); |
2326 | } |
2327 | #endif |
2328 | kfree(p->track); |
2329 | p->track = NULL; |
2330 | return 0; |
2331 | } |
2332 | |
2333 | #ifdef CONFIG_DRM_RADEON_UMS |
2334 | |
2335 | /** |
2336 | * cs_parser_fini() - clean parser states |
2337 | * @parser: parser structure holding parsing context. |
2338 | * @error: error number |
2339 | * |
2340 | * If error is set than unvalidate buffer, otherwise just free memory |
2341 | * used by parsing context. |
2342 | **/ |
2343 | static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error) |
2344 | { |
2345 | unsigned i; |
2346 | |
2347 | kfree(parser->relocs); |
2348 | for (i = 0; i < parser->nchunks; i++) |
2349 | drm_free_large(parser->chunks[i].kdata); |
2350 | kfree(parser->chunks); |
2351 | kfree(parser->chunks_array); |
2352 | } |
2353 | |
2354 | static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p) |
2355 | { |
2356 | if (p->chunk_relocs_idx == -1) { |
2357 | return 0; |
2358 | } |
2359 | p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL); |
2360 | if (p->relocs == NULL) { |
2361 | return -ENOMEM; |
2362 | } |
2363 | return 0; |
2364 | } |
2365 | |
2366 | int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, |
2367 | unsigned family, u32 *ib, int *l) |
2368 | { |
2369 | struct radeon_cs_parser parser; |
2370 | struct radeon_cs_chunk *ib_chunk; |
2371 | struct r600_cs_track *track; |
2372 | int r; |
2373 | |
2374 | /* initialize tracker */ |
2375 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
2376 | if (track == NULL) |
2377 | return -ENOMEM; |
2378 | r600_cs_track_init(track); |
2379 | r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size); |
2380 | /* initialize parser */ |
2381 | memset(&parser, 0, sizeof(struct radeon_cs_parser)); |
2382 | parser.filp = filp; |
2383 | parser.dev = &dev->pdev->dev; |
2384 | parser.rdev = NULL; |
2385 | parser.family = family; |
2386 | parser.track = track; |
2387 | parser.ib.ptr = ib; |
2388 | r = radeon_cs_parser_init(&parser, data); |
2389 | if (r) { |
2390 | DRM_ERROR("Failed to initialize parser !\n" ); |
2391 | r600_cs_parser_fini(&parser, r); |
2392 | return r; |
2393 | } |
2394 | r = r600_cs_parser_relocs_legacy(&parser); |
2395 | if (r) { |
2396 | DRM_ERROR("Failed to parse relocation !\n" ); |
2397 | r600_cs_parser_fini(&parser, r); |
2398 | return r; |
2399 | } |
2400 | /* Copy the packet into the IB, the parser will read from the |
2401 | * input memory (cached) and write to the IB (which can be |
2402 | * uncached). */ |
2403 | ib_chunk = &parser.chunks[parser.chunk_ib_idx]; |
2404 | parser.ib.length_dw = ib_chunk->length_dw; |
2405 | *l = parser.ib.length_dw; |
2406 | if (copy_from_user(ib, ib_chunk->user_ptr, ib_chunk->length_dw * 4)) { |
2407 | r = -EFAULT; |
2408 | r600_cs_parser_fini(&parser, r); |
2409 | return r; |
2410 | } |
2411 | r = r600_cs_parse(&parser); |
2412 | if (r) { |
2413 | DRM_ERROR("Invalid command stream !\n" ); |
2414 | r600_cs_parser_fini(&parser, r); |
2415 | return r; |
2416 | } |
2417 | r600_cs_parser_fini(&parser, r); |
2418 | return r; |
2419 | } |
2420 | |
2421 | void r600_cs_legacy_init(void) |
2422 | { |
2423 | r600_nomm = 1; |
2424 | } |
2425 | |
2426 | #endif |
2427 | |
2428 | /* |
2429 | * DMA |
2430 | */ |
2431 | /** |
2432 | * r600_dma_cs_next_reloc() - parse next reloc |
2433 | * @p: parser structure holding parsing context. |
2434 | * @cs_reloc: reloc informations |
2435 | * |
2436 | * Return the next reloc, do bo validation and compute |
2437 | * GPU offset using the provided start. |
2438 | **/ |
2439 | int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, |
2440 | struct radeon_cs_reloc **cs_reloc) |
2441 | { |
2442 | struct radeon_cs_chunk *relocs_chunk __unused; |
2443 | unsigned idx; |
2444 | |
2445 | *cs_reloc = NULL; |
2446 | if (p->chunk_relocs_idx == -1) { |
2447 | DRM_ERROR("No relocation chunk !\n" ); |
2448 | return -EINVAL; |
2449 | } |
2450 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
2451 | idx = p->dma_reloc_idx; |
2452 | if (idx >= p->nrelocs) { |
2453 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n" , |
2454 | idx, p->nrelocs); |
2455 | return -EINVAL; |
2456 | } |
2457 | *cs_reloc = p->relocs_ptr[idx]; |
2458 | p->dma_reloc_idx++; |
2459 | return 0; |
2460 | } |
2461 | |
2462 | #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28) |
2463 | #define GET_DMA_COUNT(h) ((h) & 0x0000ffff) |
2464 | #define GET_DMA_T(h) (((h) & 0x00800000) >> 23) |
2465 | |
2466 | /** |
2467 | * r600_dma_cs_parse() - parse the DMA IB |
2468 | * @p: parser structure holding parsing context. |
2469 | * |
2470 | * Parses the DMA IB from the CS ioctl and updates |
2471 | * the GPU addresses based on the reloc information and |
2472 | * checks for errors. (R6xx-R7xx) |
2473 | * Returns 0 for success and an error on failure. |
2474 | **/ |
2475 | int r600_dma_cs_parse(struct radeon_cs_parser *p) |
2476 | { |
2477 | struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; |
2478 | struct radeon_cs_reloc *src_reloc, *dst_reloc; |
2479 | u32 , cmd, count, tiled; |
2480 | volatile u32 *ib = p->ib.ptr; |
2481 | u32 idx, idx_value; |
2482 | u64 src_offset, dst_offset; |
2483 | int r; |
2484 | |
2485 | do { |
2486 | if (p->idx >= ib_chunk->length_dw) { |
2487 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n" , |
2488 | p->idx, ib_chunk->length_dw); |
2489 | return -EINVAL; |
2490 | } |
2491 | idx = p->idx; |
2492 | header = radeon_get_ib_value(p, idx); |
2493 | cmd = GET_DMA_CMD(header); |
2494 | count = GET_DMA_COUNT(header); |
2495 | tiled = GET_DMA_T(header); |
2496 | |
2497 | switch (cmd) { |
2498 | case DMA_PACKET_WRITE: |
2499 | r = r600_dma_cs_next_reloc(p, &dst_reloc); |
2500 | if (r) { |
2501 | DRM_ERROR("bad DMA_PACKET_WRITE\n" ); |
2502 | return -EINVAL; |
2503 | } |
2504 | if (tiled) { |
2505 | dst_offset = radeon_get_ib_value(p, idx+1); |
2506 | dst_offset <<= 8; |
2507 | |
2508 | ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); |
2509 | p->idx += count + 5; |
2510 | } else { |
2511 | dst_offset = radeon_get_ib_value(p, idx+1); |
2512 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; |
2513 | |
2514 | ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2515 | ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; |
2516 | p->idx += count + 3; |
2517 | } |
2518 | if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { |
2519 | dev_warn(p->dev, "DMA write buffer too small (%" PRIu64" %lu)\n" , |
2520 | dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); |
2521 | return -EINVAL; |
2522 | } |
2523 | break; |
2524 | case DMA_PACKET_COPY: |
2525 | r = r600_dma_cs_next_reloc(p, &src_reloc); |
2526 | if (r) { |
2527 | DRM_ERROR("bad DMA_PACKET_COPY\n" ); |
2528 | return -EINVAL; |
2529 | } |
2530 | r = r600_dma_cs_next_reloc(p, &dst_reloc); |
2531 | if (r) { |
2532 | DRM_ERROR("bad DMA_PACKET_COPY\n" ); |
2533 | return -EINVAL; |
2534 | } |
2535 | if (tiled) { |
2536 | idx_value = radeon_get_ib_value(p, idx + 2); |
2537 | /* detile bit */ |
2538 | if (idx_value & (1 << 31)) { |
2539 | /* tiled src, linear dst */ |
2540 | src_offset = radeon_get_ib_value(p, idx+1); |
2541 | src_offset <<= 8; |
2542 | ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); |
2543 | |
2544 | dst_offset = radeon_get_ib_value(p, idx+5); |
2545 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; |
2546 | ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2547 | ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; |
2548 | } else { |
2549 | /* linear src, tiled dst */ |
2550 | src_offset = radeon_get_ib_value(p, idx+5); |
2551 | src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; |
2552 | ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc); |
2553 | ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
2554 | |
2555 | dst_offset = radeon_get_ib_value(p, idx+1); |
2556 | dst_offset <<= 8; |
2557 | ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); |
2558 | } |
2559 | p->idx += 7; |
2560 | } else { |
2561 | if (p->family >= CHIP_RV770) { |
2562 | src_offset = radeon_get_ib_value(p, idx+2); |
2563 | src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; |
2564 | dst_offset = radeon_get_ib_value(p, idx+1); |
2565 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; |
2566 | |
2567 | ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2568 | ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); |
2569 | ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; |
2570 | ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
2571 | p->idx += 5; |
2572 | } else { |
2573 | src_offset = radeon_get_ib_value(p, idx+2); |
2574 | src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; |
2575 | dst_offset = radeon_get_ib_value(p, idx+1); |
2576 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16; |
2577 | |
2578 | ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2579 | ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); |
2580 | ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
2581 | ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16; |
2582 | p->idx += 4; |
2583 | } |
2584 | } |
2585 | if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { |
2586 | dev_warn(p->dev, "DMA copy src buffer too small (%" PRIu64" %lu)\n" , |
2587 | src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); |
2588 | return -EINVAL; |
2589 | } |
2590 | if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { |
2591 | dev_warn(p->dev, "DMA write dst buffer too small (%" PRIu64" %lu)\n" , |
2592 | dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); |
2593 | return -EINVAL; |
2594 | } |
2595 | break; |
2596 | case DMA_PACKET_CONSTANT_FILL: |
2597 | if (p->family < CHIP_RV770) { |
2598 | DRM_ERROR("Constant Fill is 7xx only !\n" ); |
2599 | return -EINVAL; |
2600 | } |
2601 | r = r600_dma_cs_next_reloc(p, &dst_reloc); |
2602 | if (r) { |
2603 | DRM_ERROR("bad DMA_PACKET_WRITE\n" ); |
2604 | return -EINVAL; |
2605 | } |
2606 | dst_offset = radeon_get_ib_value(p, idx+1); |
2607 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; |
2608 | if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { |
2609 | dev_warn(p->dev, "DMA constant fill buffer too small (%" PRIu64" %lu)\n" , |
2610 | dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); |
2611 | return -EINVAL; |
2612 | } |
2613 | ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2614 | ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; |
2615 | p->idx += 4; |
2616 | break; |
2617 | case DMA_PACKET_NOP: |
2618 | p->idx += 1; |
2619 | break; |
2620 | default: |
2621 | DRM_ERROR("Unknown packet type %d at %d !\n" , cmd, idx); |
2622 | return -EINVAL; |
2623 | } |
2624 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
2625 | #if 0 |
2626 | for (r = 0; r < p->ib->length_dw; r++) { |
2627 | printk(KERN_INFO "%05d 0x%08X\n" , r, p->ib.ptr[r]); |
2628 | mdelay(1); |
2629 | } |
2630 | #endif |
2631 | return 0; |
2632 | } |
2633 | |