1 | /* $NetBSD: arn9003.c,v 1.9 2016/06/10 13:27:13 ozaki-r Exp $ */ |
2 | /* $OpenBSD: ar9003.c,v 1.25 2012/10/20 09:53:32 stsp Exp $ */ |
3 | |
4 | /*- |
5 | * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> |
6 | * Copyright (c) 2010 Atheros Communications Inc. |
7 | * |
8 | * Permission to use, copy, modify, and/or distribute this software for any |
9 | * purpose with or without fee is hereby granted, provided that the above |
10 | * copyright notice and this permission notice appear in all copies. |
11 | * |
12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
19 | */ |
20 | |
21 | /* |
22 | * Driver for Atheros 802.11a/g/n chipsets. |
23 | * Routines for AR9003 family. |
24 | */ |
25 | |
26 | #include <sys/cdefs.h> |
27 | __KERNEL_RCSID(0, "$NetBSD: arn9003.c,v 1.9 2016/06/10 13:27:13 ozaki-r Exp $" ); |
28 | |
29 | #include <sys/param.h> |
30 | #include <sys/sockio.h> |
31 | #include <sys/mbuf.h> |
32 | #include <sys/kernel.h> |
33 | #include <sys/socket.h> |
34 | #include <sys/systm.h> |
35 | #include <sys/malloc.h> |
36 | #include <sys/queue.h> |
37 | #include <sys/callout.h> |
38 | #include <sys/conf.h> |
39 | #include <sys/device.h> |
40 | |
41 | #include <sys/bus.h> |
42 | #include <sys/endian.h> |
43 | #include <sys/intr.h> |
44 | |
45 | #include <net/bpf.h> |
46 | #include <net/if.h> |
47 | #include <net/if_arp.h> |
48 | #include <net/if_dl.h> |
49 | #include <net/if_ether.h> |
50 | #include <net/if_media.h> |
51 | #include <net/if_types.h> |
52 | |
53 | #include <netinet/in.h> |
54 | #include <netinet/in_systm.h> |
55 | #include <netinet/in_var.h> |
56 | #include <netinet/ip.h> |
57 | |
58 | #include <net80211/ieee80211_var.h> |
59 | #include <net80211/ieee80211_amrr.h> |
60 | #include <net80211/ieee80211_radiotap.h> |
61 | |
62 | #include <dev/ic/athnreg.h> |
63 | #include <dev/ic/athnvar.h> |
64 | #include <dev/ic/arn9003reg.h> |
65 | #include <dev/ic/arn9003.h> |
66 | |
67 | #define Static static |
68 | |
69 | Static void ar9003_calib_iq(struct athn_softc *); |
70 | Static int ar9003_calib_tx_iq(struct athn_softc *); |
71 | Static int ar9003_compute_predistortion(struct athn_softc *, |
72 | const uint32_t *, const uint32_t *); |
73 | Static void ar9003_disable_ofdm_weak_signal(struct athn_softc *); |
74 | Static void ar9003_disable_phy(struct athn_softc *); |
75 | Static int ar9003_dma_alloc(struct athn_softc *); |
76 | Static void ar9003_dma_free(struct athn_softc *); |
77 | Static void ar9003_do_calib(struct athn_softc *); |
78 | Static void ar9003_do_noisefloor_calib(struct athn_softc *); |
79 | Static void ar9003_enable_antenna_diversity(struct athn_softc *); |
80 | Static void ar9003_enable_ofdm_weak_signal(struct athn_softc *); |
81 | Static void ar9003_enable_predistorter(struct athn_softc *, int); |
82 | Static int ar9003_find_rom(struct athn_softc *); |
83 | Static void ar9003_force_txgain(struct athn_softc *, uint32_t); |
84 | Static int ar9003_get_desired_txgain(struct athn_softc *, int, int); |
85 | Static int ar9003_get_iq_corr(struct athn_softc *, int32_t[], int32_t[]); |
86 | Static void ar9003_gpio_config_input(struct athn_softc *, int); |
87 | Static void ar9003_gpio_config_output(struct athn_softc *, int, int); |
88 | Static int ar9003_gpio_read(struct athn_softc *, int); |
89 | Static void ar9003_gpio_write(struct athn_softc *, int, int); |
90 | Static void ar9003_hw_init(struct athn_softc *, struct ieee80211_channel *, |
91 | struct ieee80211_channel *); |
92 | Static void ar9003_init_baseband(struct athn_softc *); |
93 | Static void ar9003_init_chains(struct athn_softc *); |
94 | Static int ar9003_intr(struct athn_softc *); |
95 | Static void ar9003_next_calib(struct athn_softc *); |
96 | Static void ar9003_paprd_enable(struct athn_softc *); |
97 | Static int ar9003_paprd_tx_tone(struct athn_softc *); |
98 | Static void ar9003_paprd_tx_tone_done(struct athn_softc *); |
99 | Static int ar9003_read_eep_data(struct athn_softc *, uint32_t, void *, |
100 | int); |
101 | Static int ar9003_read_eep_word(struct athn_softc *, uint32_t, |
102 | uint16_t *); |
103 | Static int ar9003_read_otp_data(struct athn_softc *, uint32_t, void *, |
104 | int); |
105 | Static int ar9003_read_otp_word(struct athn_softc *, uint32_t, |
106 | uint32_t *); |
107 | Static int ar9003_read_rom(struct athn_softc *); |
108 | Static void ar9003_reset_rx_gain(struct athn_softc *, |
109 | struct ieee80211_channel *); |
110 | Static void ar9003_reset_tx_gain(struct athn_softc *, |
111 | struct ieee80211_channel *); |
112 | Static int ar9003_restore_rom_block(struct athn_softc *, uint8_t, |
113 | uint8_t, const uint8_t *, size_t); |
114 | Static void ar9003_rf_bus_release(struct athn_softc *); |
115 | Static int ar9003_rf_bus_request(struct athn_softc *); |
116 | Static void ar9003_rfsilent_init(struct athn_softc *); |
117 | Static int ar9003_rx_alloc(struct athn_softc *, int, int); |
118 | Static void ar9003_rx_enable(struct athn_softc *); |
119 | Static void ar9003_rx_free(struct athn_softc *, int); |
120 | Static void ar9003_rx_intr(struct athn_softc *, int); |
121 | Static int ar9003_rx_process(struct athn_softc *, int); |
122 | Static void ar9003_rx_radiotap(struct athn_softc *, struct mbuf *, |
123 | struct ar_rx_status *); |
124 | Static void ar9003_set_cck_weak_signal(struct athn_softc *, int); |
125 | Static void ar9003_set_delta_slope(struct athn_softc *, |
126 | struct ieee80211_channel *, struct ieee80211_channel *); |
127 | Static void ar9003_set_firstep_level(struct athn_softc *, int); |
128 | Static void ar9003_set_noise_immunity_level(struct athn_softc *, int); |
129 | Static void ar9003_set_phy(struct athn_softc *, struct ieee80211_channel *, |
130 | struct ieee80211_channel *); |
131 | Static void ar9003_set_rf_mode(struct athn_softc *, |
132 | struct ieee80211_channel *); |
133 | Static void ar9003_set_rxchains(struct athn_softc *); |
134 | Static void ar9003_set_spur_immunity_level(struct athn_softc *, int); |
135 | Static void ar9003_set_training_gain(struct athn_softc *, int); |
136 | Static int ar9003_swba_intr(struct athn_softc *); |
137 | Static int ar9003_tx(struct athn_softc *, struct mbuf *, |
138 | struct ieee80211_node *, int); |
139 | Static int ar9003_tx_alloc(struct athn_softc *); |
140 | Static void ar9003_tx_free(struct athn_softc *); |
141 | Static void ar9003_tx_intr(struct athn_softc *); |
142 | Static int ar9003_tx_process(struct athn_softc *); |
143 | |
144 | #ifdef notused |
145 | Static void ar9003_bb_load_noisefloor(struct athn_softc *); |
146 | Static void ar9003_get_noisefloor(struct athn_softc *, |
147 | struct ieee80211_channel *); |
148 | Static void ar9003_paprd_calib(struct athn_softc *, |
149 | struct ieee80211_channel *); |
150 | Static void ar9003_read_noisefloor(struct athn_softc *, int16_t *, |
151 | int16_t *); |
152 | Static void ar9003_write_noisefloor(struct athn_softc *, int16_t *, |
153 | int16_t *); |
154 | Static void ar9300_noisefloor_calib(struct athn_softc *); |
155 | #endif /* notused */ |
156 | |
157 | /* |
158 | * XXX: See if_iwn.c:MCLGETIalt() for a better solution. |
159 | * XXX: Put this in a header or in athn.c so it can be shared between |
160 | * ar5008.c and ar9003.c? |
161 | */ |
162 | static struct mbuf * |
163 | MCLGETI(struct athn_softc *sc __unused, int how, |
164 | struct ifnet *ifp __unused, u_int size) |
165 | { |
166 | struct mbuf *m; |
167 | |
168 | MGETHDR(m, how, MT_DATA); |
169 | if (m == NULL) |
170 | return NULL; |
171 | |
172 | MEXTMALLOC(m, size, how); |
173 | if ((m->m_flags & M_EXT) == 0) { |
174 | m_freem(m); |
175 | return NULL; |
176 | } |
177 | return m; |
178 | } |
179 | |
180 | PUBLIC int |
181 | ar9003_attach(struct athn_softc *sc) |
182 | { |
183 | struct athn_ops *ops = &sc->sc_ops; |
184 | int error; |
185 | |
186 | /* Set callbacks for AR9003 family. */ |
187 | ops->gpio_read = ar9003_gpio_read; |
188 | ops->gpio_write = ar9003_gpio_write; |
189 | ops->gpio_config_input = ar9003_gpio_config_input; |
190 | ops->gpio_config_output = ar9003_gpio_config_output; |
191 | ops->rfsilent_init = ar9003_rfsilent_init; |
192 | |
193 | ops->dma_alloc = ar9003_dma_alloc; |
194 | ops->dma_free = ar9003_dma_free; |
195 | ops->rx_enable = ar9003_rx_enable; |
196 | ops->intr = ar9003_intr; |
197 | ops->tx = ar9003_tx; |
198 | |
199 | ops->set_rf_mode = ar9003_set_rf_mode; |
200 | ops->rf_bus_request = ar9003_rf_bus_request; |
201 | ops->rf_bus_release = ar9003_rf_bus_release; |
202 | ops->set_phy = ar9003_set_phy; |
203 | ops->set_delta_slope = ar9003_set_delta_slope; |
204 | ops->enable_antenna_diversity = ar9003_enable_antenna_diversity; |
205 | ops->init_baseband = ar9003_init_baseband; |
206 | ops->disable_phy = ar9003_disable_phy; |
207 | ops->set_rxchains = ar9003_set_rxchains; |
208 | ops->noisefloor_calib = ar9003_do_noisefloor_calib; |
209 | ops->do_calib = ar9003_do_calib; |
210 | ops->next_calib = ar9003_next_calib; |
211 | ops->hw_init = ar9003_hw_init; |
212 | |
213 | ops->set_noise_immunity_level = ar9003_set_noise_immunity_level; |
214 | ops->enable_ofdm_weak_signal = ar9003_enable_ofdm_weak_signal; |
215 | ops->disable_ofdm_weak_signal = ar9003_disable_ofdm_weak_signal; |
216 | ops->set_cck_weak_signal = ar9003_set_cck_weak_signal; |
217 | ops->set_firstep_level = ar9003_set_firstep_level; |
218 | ops->set_spur_immunity_level = ar9003_set_spur_immunity_level; |
219 | |
220 | /* Set MAC registers offsets. */ |
221 | sc->sc_obs_off = AR_OBS; |
222 | sc->sc_gpio_input_en_off = AR_GPIO_INPUT_EN_VAL; |
223 | |
224 | if (!(sc->sc_flags & ATHN_FLAG_PCIE)) |
225 | athn_config_nonpcie(sc); |
226 | else |
227 | athn_config_pcie(sc); |
228 | |
229 | /* Determine ROM type and location. */ |
230 | if ((error = ar9003_find_rom(sc)) != 0) { |
231 | aprint_error_dev(sc->sc_dev, "could not find ROM\n" ); |
232 | return error; |
233 | } |
234 | /* Read entire ROM content in memory. */ |
235 | if ((error = ar9003_read_rom(sc)) != 0) { |
236 | aprint_error_dev(sc->sc_dev, "could not read ROM\n" ); |
237 | return error; |
238 | } |
239 | |
240 | /* Determine if it is a non-enterprise AR9003 card. */ |
241 | if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_MPSD) |
242 | sc->sc_flags |= ATHN_FLAG_NON_ENTERPRISE; |
243 | |
244 | ops->setup(sc); |
245 | return 0; |
246 | } |
247 | |
248 | /* |
249 | * Read 16-bit word from EEPROM. |
250 | */ |
251 | Static int |
252 | ar9003_read_eep_word(struct athn_softc *sc, uint32_t addr, uint16_t *val) |
253 | { |
254 | uint32_t reg; |
255 | int ntries; |
256 | |
257 | reg = AR_READ(sc, AR_EEPROM_OFFSET(addr)); |
258 | for (ntries = 0; ntries < 1000; ntries++) { |
259 | reg = AR_READ(sc, AR_EEPROM_STATUS_DATA); |
260 | if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY | |
261 | AR_EEPROM_STATUS_DATA_PROT_ACCESS))) { |
262 | *val = MS(reg, AR_EEPROM_STATUS_DATA_VAL); |
263 | return 0; |
264 | } |
265 | DELAY(10); |
266 | } |
267 | *val = 0xffff; |
268 | return ETIMEDOUT; |
269 | } |
270 | |
271 | /* |
272 | * Read an arbitrary number of bytes at a specified address in EEPROM. |
273 | * NB: The address may not be 16-bit aligned. |
274 | */ |
275 | Static int |
276 | ar9003_read_eep_data(struct athn_softc *sc, uint32_t addr, void *buf, int len) |
277 | { |
278 | uint8_t *dst = buf; |
279 | uint16_t val; |
280 | int error; |
281 | |
282 | if (len > 0 && (addr & 1)) { |
283 | /* Deal with non-aligned reads. */ |
284 | addr >>= 1; |
285 | error = ar9003_read_eep_word(sc, addr, &val); |
286 | if (error != 0) |
287 | return error; |
288 | *dst++ = val & 0xff; |
289 | addr--; |
290 | len--; |
291 | } |
292 | else |
293 | addr >>= 1; |
294 | for (; len >= 2; addr--, len -= 2) { |
295 | error = ar9003_read_eep_word(sc, addr, &val); |
296 | if (error != 0) |
297 | return error; |
298 | *dst++ = val >> 8; |
299 | *dst++ = val & 0xff; |
300 | } |
301 | if (len > 0) { |
302 | error = ar9003_read_eep_word(sc, addr, &val); |
303 | if (error != 0) |
304 | return error; |
305 | *dst++ = val >> 8; |
306 | } |
307 | return 0; |
308 | } |
309 | |
310 | /* |
311 | * Read 32-bit word from OTPROM. |
312 | */ |
313 | Static int |
314 | ar9003_read_otp_word(struct athn_softc *sc, uint32_t addr, uint32_t *val) |
315 | { |
316 | uint32_t reg; |
317 | int ntries; |
318 | |
319 | reg = AR_READ(sc, AR_OTP_BASE(addr)); |
320 | for (ntries = 0; ntries < 1000; ntries++) { |
321 | reg = AR_READ(sc, AR_OTP_STATUS); |
322 | if (MS(reg, AR_OTP_STATUS_TYPE) == AR_OTP_STATUS_VALID) { |
323 | *val = AR_READ(sc, AR_OTP_READ_DATA); |
324 | return 0; |
325 | } |
326 | DELAY(10); |
327 | } |
328 | return ETIMEDOUT; |
329 | } |
330 | |
331 | /* |
332 | * Read an arbitrary number of bytes at a specified address in OTPROM. |
333 | * NB: The address may not be 32-bit aligned. |
334 | */ |
335 | Static int |
336 | ar9003_read_otp_data(struct athn_softc *sc, uint32_t addr, void *buf, int len) |
337 | { |
338 | uint8_t *dst = buf; |
339 | uint32_t val; |
340 | int error; |
341 | |
342 | /* NB: not optimal for non-aligned reads, but correct. */ |
343 | for (; len > 0; addr--, len--) { |
344 | error = ar9003_read_otp_word(sc, addr >> 2, &val); |
345 | if (error != 0) |
346 | return error; |
347 | *dst++ = (val >> ((addr & 3) * 8)) & 0xff; |
348 | } |
349 | return 0; |
350 | } |
351 | |
352 | /* |
353 | * Determine if the chip has an external EEPROM or an OTPROM and its size. |
354 | */ |
355 | Static int |
356 | ar9003_find_rom(struct athn_softc *sc) |
357 | { |
358 | struct athn_ops *ops = &sc->sc_ops; |
359 | uint32_t hdr; |
360 | int error; |
361 | |
362 | /* Try EEPROM. */ |
363 | ops->read_rom_data = ar9003_read_eep_data; |
364 | |
365 | sc->sc_eep_size = AR_SREV_9485(sc) ? 4096 : 1024; |
366 | sc->sc_eep_base = sc->sc_eep_size - 1; |
367 | error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); |
368 | if (error == 0 && hdr != 0 && hdr != 0xffffffff) |
369 | return 0; |
370 | |
371 | sc->sc_eep_size = 512; |
372 | sc->sc_eep_base = sc->sc_eep_size - 1; |
373 | error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); |
374 | if (error == 0 && hdr != 0 && hdr != 0xffffffff) |
375 | return 0; |
376 | |
377 | /* Try OTPROM. */ |
378 | ops->read_rom_data = ar9003_read_otp_data; |
379 | |
380 | sc->sc_eep_size = 1024; |
381 | sc->sc_eep_base = sc->sc_eep_size - 1; |
382 | error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); |
383 | if (error == 0 && hdr != 0 && hdr != 0xffffffff) |
384 | return 0; |
385 | |
386 | sc->sc_eep_size = 512; |
387 | sc->sc_eep_base = sc->sc_eep_size - 1; |
388 | error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); |
389 | if (error == 0 && hdr != 0 && hdr != 0xffffffff) |
390 | return 0; |
391 | |
392 | return EIO; /* Not found. */ |
393 | } |
394 | |
395 | Static int |
396 | ar9003_restore_rom_block(struct athn_softc *sc, uint8_t alg, uint8_t ref, |
397 | const uint8_t *buf, size_t len) |
398 | { |
399 | const uint8_t *def, *ptr, *end; |
400 | uint8_t *eep = sc->sc_eep; |
401 | size_t off, clen; |
402 | |
403 | if (alg == AR_EEP_COMPRESS_BLOCK) { |
404 | /* Block contains chunks that shadow ROM template. */ |
405 | def = sc->sc_ops.get_rom_template(sc, ref); |
406 | if (def == NULL) { |
407 | DPRINTFN(DBG_INIT, sc, "unknown template image %d\n" , |
408 | ref); |
409 | return EINVAL; |
410 | } |
411 | /* Start with template. */ |
412 | memcpy(eep, def, sc->sc_eep_size); |
413 | /* Shadow template with chunks. */ |
414 | off = 0; /* Offset in ROM image. */ |
415 | ptr = buf; /* Offset in block. */ |
416 | end = buf + len; |
417 | /* Process chunks. */ |
418 | while (ptr + 2 <= end) { |
419 | off += *ptr++; /* Gap with previous chunk. */ |
420 | clen = *ptr++; /* Chunk length. */ |
421 | /* Make sure block is large enough. */ |
422 | if (ptr + clen > end) |
423 | return EINVAL; |
424 | /* Make sure chunk fits in ROM image. */ |
425 | if (off + clen > sc->sc_eep_size) |
426 | return EINVAL; |
427 | /* Restore chunk. */ |
428 | DPRINTFN(DBG_INIT, sc, "ROM chunk @%zd/%zd\n" , |
429 | off, clen); |
430 | memcpy(&eep[off], ptr, clen); |
431 | ptr += clen; |
432 | off += clen; |
433 | } |
434 | } |
435 | else if (alg == AR_EEP_COMPRESS_NONE) { |
436 | /* Block contains full ROM image. */ |
437 | if (len != sc->sc_eep_size) { |
438 | DPRINTFN(DBG_INIT, sc, "block length mismatch %zd\n" , |
439 | len); |
440 | return EINVAL; |
441 | } |
442 | memcpy(eep, buf, len); |
443 | } |
444 | return 0; |
445 | } |
446 | |
447 | Static int |
448 | ar9003_read_rom(struct athn_softc *sc) |
449 | { |
450 | struct athn_ops *ops = &sc->sc_ops; |
451 | uint8_t *buf, *ptr, alg, ref; |
452 | uint16_t sum, rsum; |
453 | uint32_t hdr; |
454 | int error, addr; |
455 | size_t len, i, j; |
456 | |
457 | /* Allocate space to store ROM in host memory. */ |
458 | sc->sc_eep = malloc(sc->sc_eep_size, M_DEVBUF, M_NOWAIT); |
459 | if (sc->sc_eep == NULL) |
460 | return ENOMEM; |
461 | |
462 | /* Allocate temporary buffer to store ROM blocks. */ |
463 | buf = malloc(2048, M_DEVBUF, M_NOWAIT); |
464 | if (buf == NULL) |
465 | return ENOMEM; |
466 | |
467 | /* Restore vendor-specified ROM blocks. */ |
468 | addr = sc->sc_eep_base; |
469 | for (i = 0; i < 100; i++) { |
470 | /* Read block header. */ |
471 | error = ops->read_rom_data(sc, addr, &hdr, sizeof(hdr)); |
472 | if (error != 0) |
473 | break; |
474 | if (hdr == 0 || hdr == 0xffffffff) |
475 | break; |
476 | addr -= sizeof(hdr); |
477 | |
478 | /* Extract bits from header. */ |
479 | ptr = (uint8_t *)&hdr; |
480 | alg = (ptr[0] & 0xe0) >> 5; |
481 | ref = (ptr[1] & 0x80) >> 2 | (ptr[0] & 0x1f); |
482 | len = (ptr[1] & 0x7f) << 4 | (ptr[2] & 0xf0) >> 4; |
483 | DPRINTFN(DBG_INIT, sc, |
484 | "ROM block %zd: alg=%d ref=%d len=%zd\n" , |
485 | i, alg, ref, len); |
486 | |
487 | /* Read block data (len <= 0x7ff). */ |
488 | error = ops->read_rom_data(sc, addr, buf, len); |
489 | if (error != 0) |
490 | break; |
491 | addr -= len; |
492 | |
493 | /* Read block checksum. */ |
494 | error = ops->read_rom_data(sc, addr, &sum, sizeof(sum)); |
495 | if (error != 0) |
496 | break; |
497 | addr -= sizeof(sum); |
498 | |
499 | /* Compute block checksum. */ |
500 | rsum = 0; |
501 | for (j = 0; j < len; j++) |
502 | rsum += buf[j]; |
503 | /* Compare to that in ROM. */ |
504 | if (le16toh(sum) != rsum) { |
505 | DPRINTFN(DBG_INIT, sc, |
506 | "bad block checksum 0x%x/0x%x\n" , |
507 | le16toh(sum), rsum); |
508 | continue; /* Skip bad block. */ |
509 | } |
510 | /* Checksum is correct, restore block. */ |
511 | ar9003_restore_rom_block(sc, alg, ref, buf, len); |
512 | } |
513 | #if BYTE_ORDER == BIG_ENDIAN |
514 | /* NB: ROM is always little endian. */ |
515 | if (error == 0) |
516 | ops->swap_rom(sc); |
517 | #endif |
518 | free(buf, M_DEVBUF); |
519 | return error; |
520 | } |
521 | |
522 | /* |
523 | * Access to General Purpose Input/Output ports. |
524 | */ |
525 | Static int |
526 | ar9003_gpio_read(struct athn_softc *sc, int pin) |
527 | { |
528 | |
529 | KASSERT(pin < sc->sc_ngpiopins); |
530 | return ((AR_READ(sc, AR_GPIO_IN) & AR9300_GPIO_IN_VAL) & |
531 | (1 << pin)) != 0; |
532 | } |
533 | |
534 | Static void |
535 | ar9003_gpio_write(struct athn_softc *sc, int pin, int set) |
536 | { |
537 | uint32_t reg; |
538 | |
539 | KASSERT(pin < sc->sc_ngpiopins); |
540 | reg = AR_READ(sc, AR_GPIO_IN_OUT); |
541 | if (set) |
542 | reg |= 1 << pin; |
543 | else |
544 | reg &= ~(1 << pin); |
545 | AR_WRITE(sc, AR_GPIO_IN_OUT, reg); |
546 | AR_WRITE_BARRIER(sc); |
547 | } |
548 | |
549 | Static void |
550 | ar9003_gpio_config_input(struct athn_softc *sc, int pin) |
551 | { |
552 | uint32_t reg; |
553 | |
554 | reg = AR_READ(sc, AR_GPIO_OE_OUT); |
555 | reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2)); |
556 | reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2); |
557 | AR_WRITE(sc, AR_GPIO_OE_OUT, reg); |
558 | AR_WRITE_BARRIER(sc); |
559 | } |
560 | |
561 | Static void |
562 | ar9003_gpio_config_output(struct athn_softc *sc, int pin, int type) |
563 | { |
564 | uint32_t reg; |
565 | int mux, off; |
566 | |
567 | mux = pin / 6; |
568 | off = pin % 6; |
569 | |
570 | reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux)); |
571 | reg &= ~(0x1f << (off * 5)); |
572 | reg |= (type & 0x1f) << (off * 5); |
573 | AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg); |
574 | |
575 | reg = AR_READ(sc, AR_GPIO_OE_OUT); |
576 | reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2)); |
577 | reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2); |
578 | AR_WRITE(sc, AR_GPIO_OE_OUT, reg); |
579 | AR_WRITE_BARRIER(sc); |
580 | } |
581 | |
582 | Static void |
583 | ar9003_rfsilent_init(struct athn_softc *sc) |
584 | { |
585 | uint32_t reg; |
586 | |
587 | /* Configure hardware radio switch. */ |
588 | AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); |
589 | reg = AR_READ(sc, AR_GPIO_INPUT_MUX2); |
590 | reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); |
591 | AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg); |
592 | ar9003_gpio_config_input(sc, sc->sc_rfsilent_pin); |
593 | AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB); |
594 | if (!(sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED)) { |
595 | AR_SETBITS(sc, AR_GPIO_INTR_POL, |
596 | AR_GPIO_INTR_POL_PIN(sc->sc_rfsilent_pin)); |
597 | } |
598 | AR_WRITE_BARRIER(sc); |
599 | } |
600 | |
601 | Static int |
602 | ar9003_dma_alloc(struct athn_softc *sc) |
603 | { |
604 | int error; |
605 | |
606 | error = ar9003_tx_alloc(sc); |
607 | if (error != 0) |
608 | return error; |
609 | |
610 | error = ar9003_rx_alloc(sc, ATHN_QID_LP, AR9003_RX_LP_QDEPTH); |
611 | if (error != 0) |
612 | return error; |
613 | |
614 | error = ar9003_rx_alloc(sc, ATHN_QID_HP, AR9003_RX_HP_QDEPTH); |
615 | if (error != 0) |
616 | return error; |
617 | |
618 | return 0; |
619 | } |
620 | |
621 | Static void |
622 | ar9003_dma_free(struct athn_softc *sc) |
623 | { |
624 | |
625 | ar9003_tx_free(sc); |
626 | ar9003_rx_free(sc, ATHN_QID_LP); |
627 | ar9003_rx_free(sc, ATHN_QID_HP); |
628 | } |
629 | |
630 | Static int |
631 | ar9003_tx_alloc(struct athn_softc *sc) |
632 | { |
633 | struct athn_tx_buf *bf; |
634 | bus_size_t size; |
635 | int error, nsegs, i; |
636 | |
637 | /* |
638 | * Allocate Tx status ring. |
639 | */ |
640 | size = AR9003_NTXSTATUS * sizeof(struct ar_tx_status); |
641 | |
642 | error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, |
643 | BUS_DMA_NOWAIT, &sc->sc_txsmap); |
644 | if (error != 0) |
645 | goto fail; |
646 | |
647 | error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_txsseg, 1, |
648 | // XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); |
649 | &nsegs, BUS_DMA_NOWAIT); |
650 | if (error != 0) |
651 | goto fail; |
652 | |
653 | error = bus_dmamem_map(sc->sc_dmat, &sc->sc_txsseg, 1, size, |
654 | (void **)&sc->sc_txsring, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); |
655 | if (error != 0) |
656 | goto fail; |
657 | |
658 | error = bus_dmamap_load(sc->sc_dmat, sc->sc_txsmap, sc->sc_txsring, |
659 | size, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); |
660 | if (error != 0) |
661 | goto fail; |
662 | |
663 | /* |
664 | * Allocate a pool of Tx descriptors shared between all Tx queues. |
665 | */ |
666 | size = ATHN_NTXBUFS * sizeof(struct ar_tx_desc); |
667 | |
668 | error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, |
669 | BUS_DMA_NOWAIT, &sc->sc_map); |
670 | if (error != 0) |
671 | goto fail; |
672 | |
673 | error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_seg, 1, |
674 | // XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); |
675 | &nsegs, BUS_DMA_NOWAIT); |
676 | if (error != 0) |
677 | goto fail; |
678 | |
679 | error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, 1, size, |
680 | (void **)&sc->sc_descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); |
681 | if (error != 0) |
682 | goto fail; |
683 | |
684 | error = bus_dmamap_load(sc->sc_dmat, sc->sc_map, sc->sc_descs, size, |
685 | NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); |
686 | if (error != 0) |
687 | goto fail; |
688 | |
689 | SIMPLEQ_INIT(&sc->sc_txbufs); |
690 | for (i = 0; i < ATHN_NTXBUFS; i++) { |
691 | bf = &sc->sc_txpool[i]; |
692 | |
693 | error = bus_dmamap_create(sc->sc_dmat, ATHN_TXBUFSZ, |
694 | AR9003_MAX_SCATTER, ATHN_TXBUFSZ, 0, BUS_DMA_NOWAIT, |
695 | &bf->bf_map); |
696 | if (error != 0) { |
697 | aprint_error_dev(sc->sc_dev, |
698 | "could not create Tx buf DMA map\n" ); |
699 | goto fail; |
700 | } |
701 | |
702 | bf->bf_descs = &((struct ar_tx_desc *)sc->sc_descs)[i]; |
703 | bf->bf_daddr = sc->sc_map->dm_segs[0].ds_addr + |
704 | i * sizeof(struct ar_tx_desc); |
705 | |
706 | SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); |
707 | } |
708 | return 0; |
709 | fail: |
710 | ar9003_tx_free(sc); |
711 | return error; |
712 | } |
713 | |
714 | Static void |
715 | ar9003_tx_free(struct athn_softc *sc) |
716 | { |
717 | struct athn_tx_buf *bf; |
718 | int i; |
719 | |
720 | for (i = 0; i < ATHN_NTXBUFS; i++) { |
721 | bf = &sc->sc_txpool[i]; |
722 | |
723 | if (bf->bf_map != NULL) |
724 | bus_dmamap_destroy(sc->sc_dmat, bf->bf_map); |
725 | } |
726 | /* Free Tx descriptors. */ |
727 | if (sc->sc_map != NULL) { |
728 | if (sc->sc_descs != NULL) { |
729 | bus_dmamap_unload(sc->sc_dmat, sc->sc_map); |
730 | bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, |
731 | ATHN_NTXBUFS * sizeof(struct ar_tx_desc)); |
732 | bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); |
733 | } |
734 | bus_dmamap_destroy(sc->sc_dmat, sc->sc_map); |
735 | } |
736 | /* Free Tx status ring. */ |
737 | if (sc->sc_txsmap != NULL) { |
738 | if (sc->sc_txsring != NULL) { |
739 | bus_dmamap_unload(sc->sc_dmat, sc->sc_txsmap); |
740 | bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_txsring, |
741 | AR9003_NTXSTATUS * sizeof(struct ar_tx_status)); |
742 | bus_dmamem_free(sc->sc_dmat, &sc->sc_txsseg, 1); |
743 | } |
744 | bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsmap); |
745 | } |
746 | } |
747 | |
748 | Static int |
749 | ar9003_rx_alloc(struct athn_softc *sc, int qid, int count) |
750 | { |
751 | struct athn_rxq *rxq = &sc->sc_rxq[qid]; |
752 | struct athn_rx_buf *bf; |
753 | struct ar_rx_status *ds; |
754 | int error, i; |
755 | |
756 | rxq->bf = malloc(count * sizeof(*bf), M_DEVBUF, M_NOWAIT | M_ZERO); |
757 | if (rxq->bf == NULL) |
758 | return ENOMEM; |
759 | |
760 | rxq->count = count; |
761 | |
762 | for (i = 0; i < rxq->count; i++) { |
763 | bf = &rxq->bf[i]; |
764 | |
765 | error = bus_dmamap_create(sc->sc_dmat, ATHN_RXBUFSZ, 1, |
766 | ATHN_RXBUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, |
767 | &bf->bf_map); |
768 | if (error != 0) { |
769 | aprint_error_dev(sc->sc_dev, |
770 | "could not create Rx buf DMA map\n" ); |
771 | goto fail; |
772 | } |
773 | /* |
774 | * Assumes MCLGETI returns cache-line-size aligned buffers. |
775 | */ |
776 | bf->bf_m = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ); |
777 | if (bf->bf_m == NULL) { |
778 | aprint_error_dev(sc->sc_dev, |
779 | "could not allocate Rx mbuf\n" ); |
780 | error = ENOBUFS; |
781 | goto fail; |
782 | } |
783 | |
784 | error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, |
785 | mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL, |
786 | BUS_DMA_NOWAIT); |
787 | if (error != 0) { |
788 | aprint_error_dev(sc->sc_dev, |
789 | "could not DMA map Rx buffer\n" ); |
790 | goto fail; |
791 | } |
792 | |
793 | ds = mtod(bf->bf_m, struct ar_rx_status *); |
794 | memset(ds, 0, sizeof(*ds)); |
795 | bf->bf_desc = ds; |
796 | bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; |
797 | |
798 | bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, |
799 | BUS_DMASYNC_PREREAD); |
800 | } |
801 | return 0; |
802 | fail: |
803 | ar9003_rx_free(sc, qid); |
804 | return error; |
805 | } |
806 | |
807 | Static void |
808 | ar9003_rx_free(struct athn_softc *sc, int qid) |
809 | { |
810 | struct athn_rxq *rxq = &sc->sc_rxq[qid]; |
811 | struct athn_rx_buf *bf; |
812 | int i; |
813 | |
814 | if (rxq->bf == NULL) |
815 | return; |
816 | for (i = 0; i < rxq->count; i++) { |
817 | bf = &rxq->bf[i]; |
818 | |
819 | if (bf->bf_map != NULL) |
820 | bus_dmamap_destroy(sc->sc_dmat, bf->bf_map); |
821 | if (bf->bf_m != NULL) |
822 | m_freem(bf->bf_m); |
823 | } |
824 | free(rxq->bf, M_DEVBUF); |
825 | } |
826 | |
827 | PUBLIC void |
828 | ar9003_reset_txsring(struct athn_softc *sc) |
829 | { |
830 | |
831 | sc->sc_txscur = 0; |
832 | memset(sc->sc_txsring, 0, AR9003_NTXSTATUS * sizeof(struct ar_tx_status)); |
833 | AR_WRITE(sc, AR_Q_STATUS_RING_START, |
834 | sc->sc_txsmap->dm_segs[0].ds_addr); |
835 | AR_WRITE(sc, AR_Q_STATUS_RING_END, |
836 | sc->sc_txsmap->dm_segs[0].ds_addr + sc->sc_txsmap->dm_segs[0].ds_len); |
837 | AR_WRITE_BARRIER(sc); |
838 | } |
839 | |
840 | Static void |
841 | ar9003_rx_enable(struct athn_softc *sc) |
842 | { |
843 | struct athn_rxq *rxq; |
844 | struct athn_rx_buf *bf; |
845 | struct ar_rx_status *ds; |
846 | uint32_t reg; |
847 | int qid, i; |
848 | |
849 | reg = AR_READ(sc, AR_RXBP_THRESH); |
850 | reg = RW(reg, AR_RXBP_THRESH_HP, 1); |
851 | reg = RW(reg, AR_RXBP_THRESH_LP, 1); |
852 | AR_WRITE(sc, AR_RXBP_THRESH, reg); |
853 | |
854 | /* Set Rx buffer size. */ |
855 | AR_WRITE(sc, AR_DATABUF_SIZE, ATHN_RXBUFSZ - sizeof(*ds)); |
856 | |
857 | for (qid = 0; qid < 2; qid++) { |
858 | rxq = &sc->sc_rxq[qid]; |
859 | |
860 | /* Setup Rx status descriptors. */ |
861 | SIMPLEQ_INIT(&rxq->head); |
862 | for (i = 0; i < rxq->count; i++) { |
863 | bf = &rxq->bf[i]; |
864 | ds = bf->bf_desc; |
865 | |
866 | memset(ds, 0, sizeof(*ds)); |
867 | if (qid == ATHN_QID_LP) |
868 | AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); |
869 | else |
870 | AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr); |
871 | AR_WRITE_BARRIER(sc); |
872 | SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list); |
873 | } |
874 | } |
875 | /* Enable Rx. */ |
876 | AR_WRITE(sc, AR_CR, 0); |
877 | AR_WRITE_BARRIER(sc); |
878 | } |
879 | |
880 | Static void |
881 | ar9003_rx_radiotap(struct athn_softc *sc, struct mbuf *m, |
882 | struct ar_rx_status *ds) |
883 | { |
884 | struct athn_rx_radiotap_header *tap = &sc->sc_rxtap; |
885 | struct ieee80211com *ic = &sc->sc_ic; |
886 | uint64_t tsf; |
887 | uint32_t tstamp; |
888 | uint8_t rate; |
889 | |
890 | /* Extend the 15-bit timestamp from Rx status to 64-bit TSF. */ |
891 | tstamp = ds->ds_status3; |
892 | tsf = AR_READ(sc, AR_TSF_U32); |
893 | tsf = tsf << 32 | AR_READ(sc, AR_TSF_L32); |
894 | if ((tsf & 0x7fff) < tstamp) |
895 | tsf -= 0x8000; |
896 | tsf = (tsf & ~0x7fff) | tstamp; |
897 | |
898 | tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; |
899 | tap->wr_tsft = htole64(tsf); |
900 | tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); |
901 | tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); |
902 | tap->wr_dbm_antsignal = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED); |
903 | /* XXX noise. */ |
904 | tap->wr_antenna = MS(ds->ds_status4, AR_RXS4_ANTENNA); |
905 | tap->wr_rate = 0; /* In case it can't be found below. */ |
906 | rate = MS(ds->ds_status1, AR_RXS1_RATE); |
907 | if (rate & 0x80) { /* HT. */ |
908 | /* Bit 7 set means HT MCS instead of rate. */ |
909 | tap->wr_rate = rate; |
910 | if (!(ds->ds_status4 & AR_RXS4_GI)) |
911 | tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; |
912 | |
913 | } |
914 | else if (rate & 0x10) { /* CCK. */ |
915 | if (rate & 0x04) |
916 | tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; |
917 | switch (rate & ~0x14) { |
918 | case 0xb: tap->wr_rate = 2; break; |
919 | case 0xa: tap->wr_rate = 4; break; |
920 | case 0x9: tap->wr_rate = 11; break; |
921 | case 0x8: tap->wr_rate = 22; break; |
922 | } |
923 | } |
924 | else { /* OFDM. */ |
925 | switch (rate) { |
926 | case 0xb: tap->wr_rate = 12; break; |
927 | case 0xf: tap->wr_rate = 18; break; |
928 | case 0xa: tap->wr_rate = 24; break; |
929 | case 0xe: tap->wr_rate = 36; break; |
930 | case 0x9: tap->wr_rate = 48; break; |
931 | case 0xd: tap->wr_rate = 72; break; |
932 | case 0x8: tap->wr_rate = 96; break; |
933 | case 0xc: tap->wr_rate = 108; break; |
934 | } |
935 | } |
936 | bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); |
937 | } |
938 | |
939 | Static int |
940 | ar9003_rx_process(struct athn_softc *sc, int qid) |
941 | { |
942 | struct ieee80211com *ic = &sc->sc_ic; |
943 | struct ifnet *ifp = &sc->sc_if; |
944 | struct athn_rxq *rxq = &sc->sc_rxq[qid]; |
945 | struct athn_rx_buf *bf; |
946 | struct ar_rx_status *ds; |
947 | struct ieee80211_frame *wh; |
948 | struct ieee80211_node *ni; |
949 | struct mbuf *m, *m1; |
950 | size_t len; |
951 | u_int32_t rstamp; |
952 | int error, ; |
953 | |
954 | bf = SIMPLEQ_FIRST(&rxq->head); |
955 | if (__predict_false(bf == NULL)) { /* Should not happen. */ |
956 | aprint_error_dev(sc->sc_dev, "Rx queue is empty!\n" ); |
957 | return ENOENT; |
958 | } |
959 | bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, |
960 | BUS_DMASYNC_POSTREAD); |
961 | |
962 | ds = mtod(bf->bf_m, struct ar_rx_status *); |
963 | if (!(ds->ds_status1 & AR_RXS1_DONE)) |
964 | return EBUSY; |
965 | |
966 | /* Check that it is a valid Rx status descriptor. */ |
967 | if ((ds->ds_info & (AR_RXI_DESC_ID_M | AR_RXI_DESC_TX | |
968 | AR_RXI_CTRL_STAT)) != SM(AR_RXI_DESC_ID, AR_VENDOR_ATHEROS)) |
969 | goto skip; |
970 | |
971 | if (!(ds->ds_status11 & AR_RXS11_FRAME_OK)) { |
972 | if (ds->ds_status11 & AR_RXS11_CRC_ERR) |
973 | DPRINTFN(DBG_RX, sc, "CRC error\n" ); |
974 | else if (ds->ds_status11 & AR_RXS11_PHY_ERR) |
975 | DPRINTFN(DBG_RX, sc, "PHY error=0x%x\n" , |
976 | MS(ds->ds_status11, AR_RXS11_PHY_ERR_CODE)); |
977 | else if (ds->ds_status11 & AR_RXS11_DECRYPT_CRC_ERR) |
978 | DPRINTFN(DBG_RX, sc, "Decryption CRC error\n" ); |
979 | else if (ds->ds_status11 & AR_RXS11_MICHAEL_ERR) { |
980 | DPRINTFN(DBG_RX, sc, "Michael MIC failure\n" ); |
981 | /* Report Michael MIC failures to net80211. */ |
982 | |
983 | len = MS(ds->ds_status2, AR_RXS2_DATA_LEN); |
984 | m = bf->bf_m; |
985 | m_set_rcvif(m, ifp); |
986 | m->m_data = (void *)&ds[1]; |
987 | m->m_pkthdr.len = m->m_len = len; |
988 | wh = mtod(m, struct ieee80211_frame *); |
989 | |
990 | ieee80211_notify_michael_failure(ic, wh, |
991 | 0 /* XXX: keyix */); |
992 | } |
993 | ifp->if_ierrors++; |
994 | goto skip; |
995 | } |
996 | |
997 | len = MS(ds->ds_status2, AR_RXS2_DATA_LEN); |
998 | if (__predict_false(len < IEEE80211_MIN_LEN || |
999 | len > ATHN_RXBUFSZ - sizeof(*ds))) { |
1000 | DPRINTFN(DBG_RX, sc, "corrupted descriptor length=%zd\n" , |
1001 | len); |
1002 | ifp->if_ierrors++; |
1003 | goto skip; |
1004 | } |
1005 | |
1006 | /* Allocate a new Rx buffer. */ |
1007 | m1 = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ); |
1008 | if (__predict_false(m1 == NULL)) { |
1009 | ic->ic_stats.is_rx_nobuf++; |
1010 | ifp->if_ierrors++; |
1011 | goto skip; |
1012 | } |
1013 | |
1014 | /* Unmap the old Rx buffer. */ |
1015 | bus_dmamap_unload(sc->sc_dmat, bf->bf_map); |
1016 | |
1017 | /* Map the new Rx buffer. */ |
1018 | error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, mtod(m1, void *), |
1019 | ATHN_RXBUFSZ, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); |
1020 | if (__predict_false(error != 0)) { |
1021 | m_freem(m1); |
1022 | |
1023 | /* Remap the old Rx buffer or panic. */ |
1024 | error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, |
1025 | mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL, |
1026 | BUS_DMA_NOWAIT | BUS_DMA_READ); |
1027 | KASSERT(error != 0); |
1028 | bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; |
1029 | ifp->if_ierrors++; |
1030 | goto skip; |
1031 | } |
1032 | bf->bf_desc = mtod(m1, struct ar_rx_status *); |
1033 | bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; |
1034 | |
1035 | m = bf->bf_m; |
1036 | bf->bf_m = m1; |
1037 | |
1038 | /* Finalize mbuf. */ |
1039 | m_set_rcvif(m, ifp); |
1040 | /* Strip Rx status descriptor from head. */ |
1041 | m->m_data = (void *)&ds[1]; |
1042 | m->m_pkthdr.len = m->m_len = len; |
1043 | |
1044 | /* Grab a reference to the source node. */ |
1045 | wh = mtod(m, struct ieee80211_frame *); |
1046 | ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); |
1047 | |
1048 | /* Remove any HW padding after the 802.11 header. */ |
1049 | if (!(wh->i_fc[0] & IEEE80211_FC0_TYPE_CTL)) { |
1050 | u_int hdrlen = ieee80211_anyhdrsize(wh); |
1051 | if (hdrlen & 3) { |
1052 | ovbcopy(wh, (uint8_t *)wh + 2, hdrlen); |
1053 | m_adj(m, 2); |
1054 | } |
1055 | } |
1056 | if (__predict_false(sc->sc_drvbpf != NULL)) |
1057 | ar9003_rx_radiotap(sc, m, ds); |
1058 | /* Trim 802.11 FCS after radiotap. */ |
1059 | m_adj(m, -IEEE80211_CRC_LEN); |
1060 | |
1061 | /* Send the frame to the 802.11 layer. */ |
1062 | rssi = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED); |
1063 | rstamp = ds->ds_status3; |
1064 | ieee80211_input(ic, m, ni, rssi, rstamp); |
1065 | |
1066 | /* Node is no longer needed. */ |
1067 | ieee80211_free_node(ni); |
1068 | |
1069 | skip: |
1070 | /* Unlink this descriptor from head. */ |
1071 | SIMPLEQ_REMOVE_HEAD(&rxq->head, bf_list); |
1072 | memset(bf->bf_desc, 0, sizeof(*ds)); |
1073 | |
1074 | /* Re-use this descriptor and link it to tail. */ |
1075 | bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, |
1076 | BUS_DMASYNC_PREREAD); |
1077 | |
1078 | if (qid == ATHN_QID_LP) |
1079 | AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); |
1080 | else |
1081 | AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr); |
1082 | AR_WRITE_BARRIER(sc); |
1083 | SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list); |
1084 | |
1085 | /* Re-enable Rx. */ |
1086 | AR_WRITE(sc, AR_CR, 0); |
1087 | AR_WRITE_BARRIER(sc); |
1088 | return 0; |
1089 | } |
1090 | |
1091 | Static void |
1092 | ar9003_rx_intr(struct athn_softc *sc, int qid) |
1093 | { |
1094 | |
1095 | while (ar9003_rx_process(sc, qid) == 0) |
1096 | continue; |
1097 | } |
1098 | |
1099 | Static int |
1100 | ar9003_tx_process(struct athn_softc *sc) |
1101 | { |
1102 | struct ifnet *ifp = &sc->sc_if; |
1103 | struct athn_txq *txq; |
1104 | struct athn_node *an; |
1105 | struct athn_tx_buf *bf; |
1106 | struct ar_tx_status *ds; |
1107 | uint8_t qid, failcnt; |
1108 | |
1109 | ds = &((struct ar_tx_status *)sc->sc_txsring)[sc->sc_txscur]; |
1110 | if (!(ds->ds_status8 & AR_TXS8_DONE)) |
1111 | return EBUSY; |
1112 | |
1113 | sc->sc_txscur = (sc->sc_txscur + 1) % AR9003_NTXSTATUS; |
1114 | |
1115 | /* Check that it is a valid Tx status descriptor. */ |
1116 | if ((ds->ds_info & (AR_TXI_DESC_ID_M | AR_TXI_DESC_TX)) != |
1117 | (SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | AR_TXI_DESC_TX)) { |
1118 | memset(ds, 0, sizeof(*ds)); |
1119 | return 0; |
1120 | } |
1121 | /* Retrieve the queue that was used to send this PDU. */ |
1122 | qid = MS(ds->ds_info, AR_TXI_QCU_NUM); |
1123 | txq = &sc->sc_txq[qid]; |
1124 | |
1125 | bf = SIMPLEQ_FIRST(&txq->head); |
1126 | if (bf == NULL || bf == txq->wait) { |
1127 | memset(ds, 0, sizeof(*ds)); |
1128 | return 0; |
1129 | } |
1130 | SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); |
1131 | ifp->if_opackets++; |
1132 | |
1133 | sc->sc_tx_timer = 0; |
1134 | |
1135 | if (ds->ds_status3 & AR_TXS3_EXCESSIVE_RETRIES) |
1136 | ifp->if_oerrors++; |
1137 | |
1138 | if (ds->ds_status3 & AR_TXS3_UNDERRUN) |
1139 | athn_inc_tx_trigger_level(sc); |
1140 | |
1141 | /* Wakeup PA predistortion state machine. */ |
1142 | if (bf->bf_txflags & ATHN_TXFLAG_PAPRD) |
1143 | ar9003_paprd_tx_tone_done(sc); |
1144 | |
1145 | an = (struct athn_node *)bf->bf_ni; |
1146 | /* |
1147 | * NB: the data fail count contains the number of un-acked tries |
1148 | * for the final series used. We must add the number of tries for |
1149 | * each series that was fully processed. |
1150 | */ |
1151 | failcnt = MS(ds->ds_status3, AR_TXS3_DATA_FAIL_CNT); |
1152 | /* NB: Assume two tries per series. */ |
1153 | failcnt += MS(ds->ds_status8, AR_TXS8_FINAL_IDX) * 2; |
1154 | |
1155 | /* Update rate control statistics. */ |
1156 | an->amn.amn_txcnt++; |
1157 | if (failcnt > 0) |
1158 | an->amn.amn_retrycnt++; |
1159 | |
1160 | DPRINTFN(DBG_TX, sc, "Tx done qid=%d status3=%d fail count=%d\n" , |
1161 | qid, ds->ds_status3, failcnt); |
1162 | |
1163 | /* Reset Tx status descriptor. */ |
1164 | memset(ds, 0, sizeof(*ds)); |
1165 | |
1166 | /* Unmap Tx buffer. */ |
1167 | bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, |
1168 | BUS_DMASYNC_POSTWRITE); |
1169 | bus_dmamap_unload(sc->sc_dmat, bf->bf_map); |
1170 | |
1171 | m_freem(bf->bf_m); |
1172 | bf->bf_m = NULL; |
1173 | ieee80211_free_node(bf->bf_ni); |
1174 | bf->bf_ni = NULL; |
1175 | |
1176 | /* Link Tx buffer back to global free list. */ |
1177 | SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); |
1178 | |
1179 | /* Queue buffers that are waiting if there is new room. */ |
1180 | if (--txq->queued < AR9003_TX_QDEPTH && txq->wait != NULL) { |
1181 | AR_WRITE(sc, AR_QTXDP(qid), txq->wait->bf_daddr); |
1182 | AR_WRITE_BARRIER(sc); |
1183 | txq->wait = SIMPLEQ_NEXT(txq->wait, bf_list); |
1184 | } |
1185 | return 0; |
1186 | } |
1187 | |
1188 | Static void |
1189 | ar9003_tx_intr(struct athn_softc *sc) |
1190 | { |
1191 | struct ifnet *ifp = &sc->sc_if; |
1192 | |
1193 | while (ar9003_tx_process(sc) == 0); |
1194 | |
1195 | if (!SIMPLEQ_EMPTY(&sc->sc_txbufs)) { |
1196 | ifp->if_flags &= ~IFF_OACTIVE; |
1197 | ifp->if_start(ifp); |
1198 | } |
1199 | } |
1200 | |
1201 | #ifndef IEEE80211_STA_ONLY |
1202 | /* |
1203 | * Process Software Beacon Alert interrupts. |
1204 | */ |
1205 | Static int |
1206 | ar9003_swba_intr(struct athn_softc *sc) |
1207 | { |
1208 | struct ieee80211com *ic = &sc->sc_ic; |
1209 | struct ifnet *ifp = &sc->sc_if; |
1210 | struct ieee80211_node *ni = ic->ic_bss; |
1211 | struct athn_tx_buf *bf = sc->sc_bcnbuf; |
1212 | struct ieee80211_frame *wh; |
1213 | struct ieee80211_beacon_offsets bo; |
1214 | struct ar_tx_desc *ds; |
1215 | struct mbuf *m; |
1216 | uint32_t sum; |
1217 | uint8_t ridx, hwrate; |
1218 | int error, totlen; |
1219 | |
1220 | #if notyet |
1221 | if (ic->ic_tim_mcast_pending && |
1222 | IF_IS_EMPTY(&ni->ni_savedq) && |
1223 | SIMPLEQ_EMPTY(&sc->sc_txq[ATHN_QID_CAB].head)) |
1224 | ic->ic_tim_mcast_pending = 0; |
1225 | #endif |
1226 | if (ic->ic_dtim_count == 0) |
1227 | ic->ic_dtim_count = ic->ic_dtim_period - 1; |
1228 | else |
1229 | ic->ic_dtim_count--; |
1230 | |
1231 | /* Make sure previous beacon has been sent. */ |
1232 | if (athn_tx_pending(sc, ATHN_QID_BEACON)) { |
1233 | DPRINTFN(DBG_INTR, sc, "beacon stuck\n" ); |
1234 | return EBUSY; |
1235 | } |
1236 | /* Get new beacon. */ |
1237 | m = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); |
1238 | if (__predict_false(m == NULL)) |
1239 | return ENOBUFS; |
1240 | /* Assign sequence number. */ |
1241 | /* XXX: use non-QoS tid? */ |
1242 | wh = mtod(m, struct ieee80211_frame *); |
1243 | *(uint16_t *)&wh->i_seq[0] = |
1244 | htole16(ic->ic_bss->ni_txseqs[0] << IEEE80211_SEQ_SEQ_SHIFT); |
1245 | ic->ic_bss->ni_txseqs[0]++; |
1246 | |
1247 | /* Unmap and free old beacon if any. */ |
1248 | if (__predict_true(bf->bf_m != NULL)) { |
1249 | bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, |
1250 | bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); |
1251 | bus_dmamap_unload(sc->sc_dmat, bf->bf_map); |
1252 | m_freem(bf->bf_m); |
1253 | bf->bf_m = NULL; |
1254 | } |
1255 | /* DMA map new beacon. */ |
1256 | error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, |
1257 | BUS_DMA_NOWAIT | BUS_DMA_WRITE); |
1258 | if (__predict_false(error != 0)) { |
1259 | m_freem(m); |
1260 | return error; |
1261 | } |
1262 | bf->bf_m = m; |
1263 | |
1264 | /* Setup Tx descriptor (simplified ar9003_tx()). */ |
1265 | ds = bf->bf_descs; |
1266 | memset(ds, 0, sizeof(*ds)); |
1267 | |
1268 | ds->ds_info = |
1269 | SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | |
1270 | SM(AR_TXI_DESC_NDWORDS, 23) | |
1271 | SM(AR_TXI_QCU_NUM, ATHN_QID_BEACON) | |
1272 | AR_TXI_DESC_TX | AR_TXI_CTRL_STAT; |
1273 | |
1274 | totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; |
1275 | ds->ds_ctl11 = SM(AR_TXC11_FRAME_LEN, totlen); |
1276 | ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, AR_MAX_RATE_POWER); |
1277 | ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, AR_FRAME_TYPE_BEACON); |
1278 | ds->ds_ctl12 |= AR_TXC12_NO_ACK; |
1279 | ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, AR_ENCR_TYPE_CLEAR); |
1280 | |
1281 | /* Write number of tries. */ |
1282 | ds->ds_ctl13 = SM(AR_TXC13_XMIT_DATA_TRIES0, 1); |
1283 | |
1284 | /* Write Tx rate. */ |
1285 | ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? |
1286 | ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1; |
1287 | hwrate = athn_rates[ridx].hwrate; |
1288 | ds->ds_ctl14 = SM(AR_TXC14_XMIT_RATE0, hwrate); |
1289 | |
1290 | /* Write Tx chains. */ |
1291 | ds->ds_ctl18 = SM(AR_TXC18_CHAIN_SEL0, sc->sc_txchainmask); |
1292 | |
1293 | ds->ds_segs[0].ds_data = bf->bf_map->dm_segs[0].ds_addr; |
1294 | /* Segment length must be a multiple of 4. */ |
1295 | ds->ds_segs[0].ds_ctl |= SM(AR_TXC_BUF_LEN, |
1296 | (bf->bf_map->dm_segs[0].ds_len + 3) & ~3); |
1297 | /* Compute Tx descriptor checksum. */ |
1298 | sum = ds->ds_info; |
1299 | sum += ds->ds_segs[0].ds_data; |
1300 | sum += ds->ds_segs[0].ds_ctl; |
1301 | sum = (sum >> 16) + (sum & 0xffff); |
1302 | ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum); |
1303 | |
1304 | bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, |
1305 | BUS_DMASYNC_PREWRITE); |
1306 | |
1307 | /* Stop Tx DMA before putting the new beacon on the queue. */ |
1308 | athn_stop_tx_dma(sc, ATHN_QID_BEACON); |
1309 | |
1310 | AR_WRITE(sc, AR_QTXDP(ATHN_QID_BEACON), bf->bf_daddr); |
1311 | |
1312 | for(;;) { |
1313 | if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) |
1314 | break; |
1315 | |
1316 | IF_DEQUEUE(&ni->ni_savedq, m); |
1317 | if (m == NULL) |
1318 | break; |
1319 | if (!IF_IS_EMPTY(&ni->ni_savedq)) { |
1320 | /* more queued frames, set the more data bit */ |
1321 | wh = mtod(m, struct ieee80211_frame *); |
1322 | wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; |
1323 | } |
1324 | |
1325 | if (sc->sc_ops.tx(sc, m, ni, ATHN_TXFLAG_CAB) != 0) { |
1326 | ieee80211_free_node(ni); |
1327 | ifp->if_oerrors++; |
1328 | break; |
1329 | } |
1330 | } |
1331 | |
1332 | /* Kick Tx. */ |
1333 | AR_WRITE(sc, AR_Q_TXE, 1 << ATHN_QID_BEACON); |
1334 | AR_WRITE_BARRIER(sc); |
1335 | return 0; |
1336 | } |
1337 | #endif |
1338 | |
1339 | Static int |
1340 | ar9003_intr(struct athn_softc *sc) |
1341 | { |
1342 | uint32_t intr, sync; |
1343 | |
1344 | /* Get pending interrupts. */ |
1345 | intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE); |
1346 | if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) { |
1347 | intr = AR_READ(sc, AR_INTR_SYNC_CAUSE); |
1348 | if (intr == AR_INTR_SPURIOUS || (intr & sc->sc_isync) == 0) |
1349 | return 0; /* Not for us. */ |
1350 | } |
1351 | |
1352 | if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) && |
1353 | (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) |
1354 | intr = AR_READ(sc, AR_ISR); |
1355 | else |
1356 | intr = 0; |
1357 | sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync; |
1358 | if (intr == 0 && sync == 0) |
1359 | return 0; /* Not for us. */ |
1360 | |
1361 | if (intr != 0) { |
1362 | if (intr & AR_ISR_BCNMISC) { |
1363 | uint32_t intr2 = AR_READ(sc, AR_ISR_S2); |
1364 | #ifdef notyet |
1365 | if (intr2 & AR_ISR_S2_TIM) |
1366 | /* TBD */; |
1367 | if (intr2 & AR_ISR_S2_TSFOOR) |
1368 | /* TBD */; |
1369 | if (intr2 & AR_ISR_S2_BB_WATCHDOG) |
1370 | /* TBD */; |
1371 | #else |
1372 | __USE(intr2); |
1373 | #endif |
1374 | } |
1375 | intr = AR_READ(sc, AR_ISR_RAC); |
1376 | if (intr == AR_INTR_SPURIOUS) |
1377 | return 1; |
1378 | |
1379 | #ifndef IEEE80211_STA_ONLY |
1380 | if (intr & AR_ISR_SWBA) |
1381 | ar9003_swba_intr(sc); |
1382 | #endif |
1383 | if (intr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) |
1384 | ar9003_rx_intr(sc, ATHN_QID_LP); |
1385 | if (intr & (AR_ISR_LP_RXOK | AR_ISR_RXERR)) |
1386 | ar9003_rx_intr(sc, ATHN_QID_LP); |
1387 | if (intr & AR_ISR_HP_RXOK) |
1388 | ar9003_rx_intr(sc, ATHN_QID_HP); |
1389 | |
1390 | if (intr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) |
1391 | ar9003_tx_intr(sc); |
1392 | if (intr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) |
1393 | ar9003_tx_intr(sc); |
1394 | |
1395 | if (intr & AR_ISR_GENTMR) { |
1396 | uint32_t intr5 = AR_READ(sc, AR_ISR_S5_S); |
1397 | #ifdef ATHN_DEBUG |
1398 | DPRINTFN(DBG_INTR, sc, |
1399 | "GENTMR trigger=%d thresh=%d\n" , |
1400 | MS(intr5, AR_ISR_S5_GENTIMER_TRIG), |
1401 | MS(intr5, AR_ISR_S5_GENTIMER_THRESH)); |
1402 | #else |
1403 | __USE(intr5); |
1404 | #endif |
1405 | } |
1406 | } |
1407 | if (sync != 0) { |
1408 | if (sync & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { |
1409 | AR_WRITE(sc, AR_RC, AR_RC_HOSTIF); |
1410 | AR_WRITE(sc, AR_RC, 0); |
1411 | } |
1412 | |
1413 | if ((sc->sc_flags & ATHN_FLAG_RFSILENT) && |
1414 | (sync & AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin))) { |
1415 | pmf_event_inject(sc->sc_dev, PMFE_RADIO_OFF); |
1416 | return 1; |
1417 | } |
1418 | |
1419 | AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync); |
1420 | (void)AR_READ(sc, AR_INTR_SYNC_CAUSE); |
1421 | } |
1422 | return 1; |
1423 | } |
1424 | |
1425 | Static int |
1426 | ar9003_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, |
1427 | int txflags) |
1428 | { |
1429 | struct ieee80211com *ic = &sc->sc_ic; |
1430 | struct ieee80211_key *k = NULL; |
1431 | struct ieee80211_frame *wh; |
1432 | struct athn_series series[4]; |
1433 | struct ar_tx_desc *ds; |
1434 | struct athn_txq *txq; |
1435 | struct athn_tx_buf *bf; |
1436 | struct athn_node *an = (void *)ni; |
1437 | struct mbuf *m1; |
1438 | uint32_t sum; |
1439 | uint16_t qos; |
1440 | uint8_t txpower, type, encrtype, ridx[4]; |
1441 | int i, error, totlen, hasqos, qid; |
1442 | |
1443 | /* Grab a Tx buffer from our global free list. */ |
1444 | bf = SIMPLEQ_FIRST(&sc->sc_txbufs); |
1445 | KASSERT(bf != NULL); |
1446 | |
1447 | /* Map 802.11 frame type to hardware frame type. */ |
1448 | wh = mtod(m, struct ieee80211_frame *); |
1449 | if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == |
1450 | IEEE80211_FC0_TYPE_MGT) { |
1451 | /* NB: Beacons do not use ar9003_tx(). */ |
1452 | if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == |
1453 | IEEE80211_FC0_SUBTYPE_PROBE_RESP) |
1454 | type = AR_FRAME_TYPE_PROBE_RESP; |
1455 | else if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == |
1456 | IEEE80211_FC0_SUBTYPE_ATIM) |
1457 | type = AR_FRAME_TYPE_ATIM; |
1458 | else |
1459 | type = AR_FRAME_TYPE_NORMAL; |
1460 | } |
1461 | else if ((wh->i_fc[0] & |
1462 | (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == |
1463 | (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_PS_POLL)) { |
1464 | type = AR_FRAME_TYPE_PSPOLL; |
1465 | } |
1466 | else |
1467 | type = AR_FRAME_TYPE_NORMAL; |
1468 | |
1469 | if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { |
1470 | k = ieee80211_crypto_encap(ic, ni, m); |
1471 | if (k == NULL) |
1472 | return ENOBUFS; |
1473 | |
1474 | /* packet header may have moved, reset our local pointer */ |
1475 | wh = mtod(m, struct ieee80211_frame *); |
1476 | } |
1477 | |
1478 | /* XXX 2-byte padding for QoS and 4-addr headers. */ |
1479 | |
1480 | /* Select the HW Tx queue to use for this frame. */ |
1481 | if ((hasqos = ieee80211_has_qos(wh))) { |
1482 | #ifdef notyet_edca |
1483 | uint8_t tid; |
1484 | |
1485 | qos = ieee80211_get_qos(wh); |
1486 | tid = qos & IEEE80211_QOS_TID; |
1487 | qid = athn_ac2qid[ieee80211_up_to_ac(ic, tid)]; |
1488 | #else |
1489 | qos = ieee80211_get_qos(wh); |
1490 | qid = ATHN_QID_AC_BE; |
1491 | #endif /* notyet_edca */ |
1492 | } |
1493 | else if (type == AR_FRAME_TYPE_PSPOLL) { |
1494 | qos = 0; |
1495 | qid = ATHN_QID_PSPOLL; |
1496 | } |
1497 | else if (txflags & ATHN_TXFLAG_CAB) { |
1498 | qos = 0; |
1499 | qid = ATHN_QID_CAB; |
1500 | } |
1501 | else { |
1502 | qos = 0; |
1503 | qid = ATHN_QID_AC_BE; |
1504 | } |
1505 | txq = &sc->sc_txq[qid]; |
1506 | |
1507 | /* Select the transmit rates to use for this frame. */ |
1508 | if (IEEE80211_IS_MULTICAST(wh->i_addr1) || |
1509 | (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != |
1510 | IEEE80211_FC0_TYPE_DATA) { |
1511 | /* Use lowest rate for all tries. */ |
1512 | ridx[0] = ridx[1] = ridx[2] = ridx[3] = |
1513 | (ic->ic_curmode == IEEE80211_MODE_11A) ? |
1514 | ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1; |
1515 | } |
1516 | else if (ic->ic_fixed_rate != -1) { |
1517 | /* Use same fixed rate for all tries. */ |
1518 | ridx[0] = ridx[1] = ridx[2] = ridx[3] = |
1519 | sc->sc_fixed_ridx; |
1520 | } |
1521 | else { |
1522 | int txrate = ni->ni_txrate; |
1523 | /* Use fallback table of the node. */ |
1524 | for (i = 0; i < 4; i++) { |
1525 | ridx[i] = an->ridx[txrate]; |
1526 | txrate = an->fallback[txrate]; |
1527 | } |
1528 | } |
1529 | |
1530 | if (__predict_false(sc->sc_drvbpf != NULL)) { |
1531 | struct athn_tx_radiotap_header *tap = &sc->sc_txtap; |
1532 | |
1533 | tap->wt_flags = 0; |
1534 | /* Use initial transmit rate. */ |
1535 | tap->wt_rate = athn_rates[ridx[0]].rate; |
1536 | tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); |
1537 | tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); |
1538 | // XXX tap->wt_hwqueue = qid; |
1539 | if (ridx[0] != ATHN_RIDX_CCK1 && |
1540 | (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) |
1541 | tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; |
1542 | |
1543 | bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); |
1544 | } |
1545 | |
1546 | /* DMA map mbuf. */ |
1547 | error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, |
1548 | BUS_DMA_NOWAIT | BUS_DMA_WRITE); |
1549 | if (__predict_false(error != 0)) { |
1550 | if (error != EFBIG) { |
1551 | aprint_error_dev(sc->sc_dev, |
1552 | "can't map mbuf (error %d)\n" , error); |
1553 | m_freem(m); |
1554 | return error; |
1555 | } |
1556 | /* |
1557 | * DMA mapping requires too many DMA segments; linearize |
1558 | * mbuf in kernel virtual address space and retry. |
1559 | */ |
1560 | MGETHDR(m1, M_DONTWAIT, MT_DATA); |
1561 | if (m1 == NULL) { |
1562 | m_freem(m); |
1563 | return ENOBUFS; |
1564 | } |
1565 | if (m->m_pkthdr.len > (int)MHLEN) { |
1566 | MCLGET(m1, M_DONTWAIT); |
1567 | if (!(m1->m_flags & M_EXT)) { |
1568 | m_freem(m); |
1569 | m_freem(m1); |
1570 | return ENOBUFS; |
1571 | } |
1572 | } |
1573 | m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); |
1574 | m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; |
1575 | m_freem(m); |
1576 | m = m1; |
1577 | |
1578 | error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, |
1579 | BUS_DMA_NOWAIT | BUS_DMA_WRITE); |
1580 | if (error != 0) { |
1581 | aprint_error_dev(sc->sc_dev, |
1582 | "can't map mbuf (error %d)\n" , error); |
1583 | m_freem(m); |
1584 | return error; |
1585 | } |
1586 | } |
1587 | bf->bf_m = m; |
1588 | bf->bf_ni = ni; |
1589 | bf->bf_txflags = txflags; |
1590 | |
1591 | wh = mtod(m, struct ieee80211_frame *); |
1592 | |
1593 | totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; |
1594 | |
1595 | /* Setup Tx descriptor. */ |
1596 | ds = bf->bf_descs; |
1597 | memset(ds, 0, sizeof(*ds)); |
1598 | |
1599 | ds->ds_info = |
1600 | SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | |
1601 | SM(AR_TXI_DESC_NDWORDS, 23) | |
1602 | SM(AR_TXI_QCU_NUM, qid) | |
1603 | AR_TXI_DESC_TX | AR_TXI_CTRL_STAT; |
1604 | |
1605 | ds->ds_ctl11 = AR_TXC11_CLR_DEST_MASK; |
1606 | txpower = AR_MAX_RATE_POWER; /* Get from per-rate registers. */ |
1607 | ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, txpower); |
1608 | |
1609 | ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, type); |
1610 | |
1611 | if (IEEE80211_IS_MULTICAST(wh->i_addr1) || |
1612 | (hasqos && (qos & IEEE80211_QOS_ACKPOLICY_MASK) == |
1613 | IEEE80211_QOS_ACKPOLICY_NOACK)) |
1614 | ds->ds_ctl12 |= AR_TXC12_NO_ACK; |
1615 | |
1616 | #if notyet |
1617 | if (0 && k != NULL) { |
1618 | uintptr_t entry; |
1619 | |
1620 | /* |
1621 | * Map 802.11 cipher to hardware encryption type and |
1622 | * compute MIC+ICV overhead. |
1623 | */ |
1624 | switch (k->k_cipher) { |
1625 | case IEEE80211_CIPHER_WEP40: |
1626 | case IEEE80211_CIPHER_WEP104: |
1627 | encrtype = AR_ENCR_TYPE_WEP; |
1628 | totlen += 4; |
1629 | break; |
1630 | case IEEE80211_CIPHER_TKIP: |
1631 | encrtype = AR_ENCR_TYPE_TKIP; |
1632 | totlen += 12; |
1633 | break; |
1634 | case IEEE80211_CIPHER_CCMP: |
1635 | encrtype = AR_ENCR_TYPE_AES; |
1636 | totlen += 8; |
1637 | break; |
1638 | default: |
1639 | panic("unsupported cipher" ); |
1640 | } |
1641 | /* |
1642 | * NB: The key cache entry index is stored in the key |
1643 | * private field when the key is installed. |
1644 | */ |
1645 | entry = (uintptr_t)k->k_priv; |
1646 | ds->ds_ctl12 |= SM(AR_TXC12_DEST_IDX, entry); |
1647 | ds->ds_ctl11 |= AR_TXC11_DEST_IDX_VALID; |
1648 | } |
1649 | else |
1650 | #endif |
1651 | encrtype = AR_ENCR_TYPE_CLEAR; |
1652 | ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, encrtype); |
1653 | |
1654 | /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ |
1655 | if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { |
1656 | /* NB: Group frames are sent using CCK in 802.11b/g. */ |
1657 | if (totlen > ic->ic_rtsthreshold) { |
1658 | ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE; |
1659 | } |
1660 | else if ((ic->ic_flags & IEEE80211_F_USEPROT) && |
1661 | athn_rates[ridx[0]].phy == IEEE80211_T_OFDM) { |
1662 | if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) |
1663 | ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE; |
1664 | else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) |
1665 | ds->ds_ctl11 |= AR_TXC11_CTS_ENABLE; |
1666 | } |
1667 | } |
1668 | if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) { |
1669 | /* Disable multi-rate retries when protection is used. */ |
1670 | ridx[1] = ridx[2] = ridx[3] = ridx[0]; |
1671 | } |
1672 | /* Setup multi-rate retries. */ |
1673 | for (i = 0; i < 4; i++) { |
1674 | series[i].hwrate = athn_rates[ridx[i]].hwrate; |
1675 | if (athn_rates[ridx[i]].phy == IEEE80211_T_DS && |
1676 | ridx[i] != ATHN_RIDX_CCK1 && |
1677 | (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) |
1678 | series[i].hwrate |= 0x04; |
1679 | series[i].dur = 0; |
1680 | } |
1681 | if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) { |
1682 | /* Compute duration for each series. */ |
1683 | for (i = 0; i < 4; i++) { |
1684 | series[i].dur = athn_txtime(sc, IEEE80211_ACK_LEN, |
1685 | athn_rates[ridx[i]].rspridx, ic->ic_flags); |
1686 | } |
1687 | } |
1688 | /* If this is a PA training frame, select the Tx chain to use. */ |
1689 | if (__predict_false(txflags & ATHN_TXFLAG_PAPRD)) { |
1690 | ds->ds_ctl12 |= SM(AR_TXC12_PAPRD_CHAIN_MASK, |
1691 | 1 << sc->sc_paprd_curchain); |
1692 | } |
1693 | |
1694 | /* Write number of tries for each series. */ |
1695 | ds->ds_ctl13 = |
1696 | SM(AR_TXC13_XMIT_DATA_TRIES0, 2) | |
1697 | SM(AR_TXC13_XMIT_DATA_TRIES1, 2) | |
1698 | SM(AR_TXC13_XMIT_DATA_TRIES2, 2) | |
1699 | SM(AR_TXC13_XMIT_DATA_TRIES3, 4); |
1700 | |
1701 | /* Tell HW to update duration field in 802.11 header. */ |
1702 | if (type != AR_FRAME_TYPE_PSPOLL) |
1703 | ds->ds_ctl13 |= AR_TXC13_DUR_UPDATE_ENA; |
1704 | |
1705 | /* Write Tx rate for each series. */ |
1706 | ds->ds_ctl14 = |
1707 | SM(AR_TXC14_XMIT_RATE0, series[0].hwrate) | |
1708 | SM(AR_TXC14_XMIT_RATE1, series[1].hwrate) | |
1709 | SM(AR_TXC14_XMIT_RATE2, series[2].hwrate) | |
1710 | SM(AR_TXC14_XMIT_RATE3, series[3].hwrate); |
1711 | |
1712 | /* Write duration for each series. */ |
1713 | ds->ds_ctl15 = |
1714 | SM(AR_TXC15_PACKET_DUR0, series[0].dur) | |
1715 | SM(AR_TXC15_PACKET_DUR1, series[1].dur); |
1716 | ds->ds_ctl16 = |
1717 | SM(AR_TXC16_PACKET_DUR2, series[2].dur) | |
1718 | SM(AR_TXC16_PACKET_DUR3, series[3].dur); |
1719 | |
1720 | if ((sc->sc_flags & ATHN_FLAG_3TREDUCE_CHAIN) && |
1721 | ic->ic_curmode == IEEE80211_MODE_11A) { |
1722 | /* |
1723 | * In order to not exceed PCIe power requirements, we only |
1724 | * use two Tx chains for MCS0~15 on 5GHz band on these chips. |
1725 | */ |
1726 | ds->ds_ctl18 = |
1727 | SM(AR_TXC18_CHAIN_SEL0, |
1728 | (ridx[0] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | |
1729 | SM(AR_TXC18_CHAIN_SEL1, |
1730 | (ridx[1] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | |
1731 | SM(AR_TXC18_CHAIN_SEL2, |
1732 | (ridx[2] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | |
1733 | SM(AR_TXC18_CHAIN_SEL3, |
1734 | (ridx[3] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask); |
1735 | } |
1736 | else { |
1737 | /* Use the same Tx chains for all tries. */ |
1738 | ds->ds_ctl18 = |
1739 | SM(AR_TXC18_CHAIN_SEL0, sc->sc_txchainmask) | |
1740 | SM(AR_TXC18_CHAIN_SEL1, sc->sc_txchainmask) | |
1741 | SM(AR_TXC18_CHAIN_SEL2, sc->sc_txchainmask) | |
1742 | SM(AR_TXC18_CHAIN_SEL3, sc->sc_txchainmask); |
1743 | } |
1744 | #ifdef notyet |
1745 | #ifndef IEEE80211_NO_HT |
1746 | /* Use the same short GI setting for all tries. */ |
1747 | if (ic->ic_flags & IEEE80211_F_SHGI) |
1748 | ds->ds_ctl18 |= AR_TXC18_GI0123; |
1749 | /* Use the same channel width for all tries. */ |
1750 | if (ic->ic_flags & IEEE80211_F_CBW40) |
1751 | ds->ds_ctl18 |= AR_TXC18_2040_0123; |
1752 | #endif |
1753 | #endif |
1754 | |
1755 | if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) { |
1756 | uint8_t protridx, hwrate; |
1757 | uint16_t dur = 0; |
1758 | |
1759 | /* Use the same protection mode for all tries. */ |
1760 | if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) { |
1761 | ds->ds_ctl15 |= AR_TXC15_RTSCTS_QUAL01; |
1762 | ds->ds_ctl16 |= AR_TXC16_RTSCTS_QUAL23; |
1763 | } |
1764 | /* Select protection rate (suboptimal but ok). */ |
1765 | protridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? |
1766 | ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK2; |
1767 | if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) { |
1768 | /* Account for CTS duration. */ |
1769 | dur += athn_txtime(sc, IEEE80211_ACK_LEN, |
1770 | athn_rates[protridx].rspridx, ic->ic_flags); |
1771 | } |
1772 | dur += athn_txtime(sc, totlen, ridx[0], ic->ic_flags); |
1773 | if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) { |
1774 | /* Account for ACK duration. */ |
1775 | dur += athn_txtime(sc, IEEE80211_ACK_LEN, |
1776 | athn_rates[ridx[0]].rspridx, ic->ic_flags); |
1777 | } |
1778 | /* Write protection frame duration and rate. */ |
1779 | ds->ds_ctl13 |= SM(AR_TXC13_BURST_DUR, dur); |
1780 | hwrate = athn_rates[protridx].hwrate; |
1781 | if (protridx == ATHN_RIDX_CCK2 && |
1782 | (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) |
1783 | hwrate |= 0x04; |
1784 | ds->ds_ctl18 |= SM(AR_TXC18_RTSCTS_RATE, hwrate); |
1785 | } |
1786 | |
1787 | ds->ds_ctl11 |= SM(AR_TXC11_FRAME_LEN, totlen); |
1788 | ds->ds_ctl19 = AR_TXC19_NOT_SOUNDING; |
1789 | |
1790 | for (i = 0; i < bf->bf_map->dm_nsegs; i++) { |
1791 | ds->ds_segs[i].ds_data = bf->bf_map->dm_segs[i].ds_addr; |
1792 | ds->ds_segs[i].ds_ctl = SM(AR_TXC_BUF_LEN, |
1793 | bf->bf_map->dm_segs[i].ds_len); |
1794 | } |
1795 | /* Compute Tx descriptor checksum. */ |
1796 | sum = ds->ds_info + ds->ds_link; |
1797 | for (i = 0; i < 4; i++) { |
1798 | sum += ds->ds_segs[i].ds_data; |
1799 | sum += ds->ds_segs[i].ds_ctl; |
1800 | } |
1801 | sum = (sum >> 16) + (sum & 0xffff); |
1802 | ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum); |
1803 | |
1804 | bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, |
1805 | BUS_DMASYNC_PREWRITE); |
1806 | |
1807 | DPRINTFN(DBG_TX, sc, |
1808 | "Tx qid=%d nsegs=%d ctl11=0x%x ctl12=0x%x ctl14=0x%x\n" , |
1809 | qid, bf->bf_map->dm_nsegs, ds->ds_ctl11, ds->ds_ctl12, |
1810 | ds->ds_ctl14); |
1811 | |
1812 | SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); |
1813 | SIMPLEQ_INSERT_TAIL(&txq->head, bf, bf_list); |
1814 | |
1815 | /* Queue buffer unless hardware FIFO is already full. */ |
1816 | if (++txq->queued <= AR9003_TX_QDEPTH) { |
1817 | AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr); |
1818 | AR_WRITE_BARRIER(sc); |
1819 | } |
1820 | else if (txq->wait == NULL) |
1821 | txq->wait = bf; |
1822 | return 0; |
1823 | } |
1824 | |
1825 | Static void |
1826 | ar9003_set_rf_mode(struct athn_softc *sc, struct ieee80211_channel *c) |
1827 | { |
1828 | uint32_t reg; |
1829 | |
1830 | reg = IEEE80211_IS_CHAN_2GHZ(c) ? |
1831 | AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; |
1832 | if (IEEE80211_IS_CHAN_5GHZ(c) && |
1833 | (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) { |
1834 | reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE; |
1835 | } |
1836 | AR_WRITE(sc, AR_PHY_MODE, reg); |
1837 | AR_WRITE_BARRIER(sc); |
1838 | } |
1839 | |
1840 | static __inline uint32_t |
1841 | ar9003_synth_delay(struct athn_softc *sc) |
1842 | { |
1843 | uint32_t synth_delay; |
1844 | |
1845 | synth_delay = MS(AR_READ(sc, AR_PHY_RX_DELAY), AR_PHY_RX_DELAY_DELAY); |
1846 | if (sc->sc_ic.ic_curmode == IEEE80211_MODE_11B) |
1847 | synth_delay = (synth_delay * 4) / 22; |
1848 | else |
1849 | synth_delay = synth_delay / 10; /* in 100ns steps */ |
1850 | return synth_delay; |
1851 | } |
1852 | |
1853 | Static int |
1854 | ar9003_rf_bus_request(struct athn_softc *sc) |
1855 | { |
1856 | int ntries; |
1857 | |
1858 | /* Request RF Bus grant. */ |
1859 | AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); |
1860 | for (ntries = 0; ntries < 10000; ntries++) { |
1861 | if (AR_READ(sc, AR_PHY_RFBUS_GRANT) & AR_PHY_RFBUS_GRANT_EN) |
1862 | return 0; |
1863 | DELAY(10); |
1864 | } |
1865 | DPRINTFN(DBG_RF, sc, "could not kill baseband Rx" ); |
1866 | return ETIMEDOUT; |
1867 | } |
1868 | |
1869 | Static void |
1870 | ar9003_rf_bus_release(struct athn_softc *sc) |
1871 | { |
1872 | /* Wait for the synthesizer to settle. */ |
1873 | DELAY(AR_BASE_PHY_ACTIVE_DELAY + ar9003_synth_delay(sc)); |
1874 | |
1875 | /* Release the RF Bus grant. */ |
1876 | AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0); |
1877 | AR_WRITE_BARRIER(sc); |
1878 | } |
1879 | |
1880 | Static void |
1881 | ar9003_set_phy(struct athn_softc *sc, struct ieee80211_channel *c, |
1882 | struct ieee80211_channel *extc) |
1883 | { |
1884 | uint32_t phy; |
1885 | |
1886 | phy = AR_READ(sc, AR_PHY_GEN_CTRL); |
1887 | phy |= AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | |
1888 | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH; |
1889 | #ifndef IEEE80211_NO_HT |
1890 | if (extc != NULL) { |
1891 | phy |= AR_PHY_GC_DYN2040_EN; |
1892 | if (extc > c) /* XXX */ |
1893 | phy |= AR_PHY_GC_DYN2040_PRI_CH; |
1894 | } |
1895 | #endif |
1896 | /* Turn off Green Field detection for now. */ |
1897 | phy &= ~AR_PHY_GC_GF_DETECT_EN; |
1898 | AR_WRITE(sc, AR_PHY_GEN_CTRL, phy); |
1899 | |
1900 | AR_WRITE(sc, AR_2040_MODE, |
1901 | (extc != NULL) ? AR_2040_JOINED_RX_CLEAR : 0); |
1902 | |
1903 | /* Set global transmit timeout. */ |
1904 | AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25)); |
1905 | /* Set carrier sense timeout. */ |
1906 | AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15)); |
1907 | AR_WRITE_BARRIER(sc); |
1908 | } |
1909 | |
1910 | Static void |
1911 | ar9003_set_delta_slope(struct athn_softc *sc, struct ieee80211_channel *c, |
1912 | struct ieee80211_channel *extc) |
1913 | { |
1914 | uint32_t coeff, exp, man, reg; |
1915 | |
1916 | /* Set Delta Slope (exponent and mantissa). */ |
1917 | coeff = (100 << 24) / c->ic_freq; |
1918 | athn_get_delta_slope(coeff, &exp, &man); |
1919 | DPRINTFN(DBG_RF, sc, "delta slope coeff exp=%u man=%u\n" , exp, man); |
1920 | |
1921 | reg = AR_READ(sc, AR_PHY_TIMING3); |
1922 | reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); |
1923 | reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); |
1924 | AR_WRITE(sc, AR_PHY_TIMING3, reg); |
1925 | |
1926 | /* For Short GI, coeff is 9/10 that of normal coeff. */ |
1927 | coeff = (9 * coeff) / 10; |
1928 | athn_get_delta_slope(coeff, &exp, &man); |
1929 | DPRINTFN(DBG_RF, sc, "delta slope coeff exp=%u man=%u\n" , exp, man); |
1930 | |
1931 | reg = AR_READ(sc, AR_PHY_SGI_DELTA); |
1932 | reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp); |
1933 | reg = RW(reg, AR_PHY_SGI_DSC_MAN, man); |
1934 | AR_WRITE(sc, AR_PHY_SGI_DELTA, reg); |
1935 | AR_WRITE_BARRIER(sc); |
1936 | } |
1937 | |
1938 | Static void |
1939 | ar9003_enable_antenna_diversity(struct athn_softc *sc) |
1940 | { |
1941 | AR_SETBITS(sc, AR_PHY_CCK_DETECT, |
1942 | AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); |
1943 | AR_WRITE_BARRIER(sc); |
1944 | } |
1945 | |
1946 | Static void |
1947 | ar9003_init_baseband(struct athn_softc *sc) |
1948 | { |
1949 | uint32_t synth_delay; |
1950 | |
1951 | synth_delay = ar9003_synth_delay(sc); |
1952 | /* Activate the PHY (includes baseband activate and synthesizer on). */ |
1953 | AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); |
1954 | AR_WRITE_BARRIER(sc); |
1955 | DELAY(AR_BASE_PHY_ACTIVE_DELAY + synth_delay); |
1956 | } |
1957 | |
1958 | Static void |
1959 | ar9003_disable_phy(struct athn_softc *sc) |
1960 | { |
1961 | AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); |
1962 | AR_WRITE_BARRIER(sc); |
1963 | } |
1964 | |
1965 | Static void |
1966 | ar9003_init_chains(struct athn_softc *sc) |
1967 | { |
1968 | if (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5) |
1969 | AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); |
1970 | |
1971 | /* Setup chain masks. */ |
1972 | AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask); |
1973 | AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask); |
1974 | |
1975 | if (sc->sc_flags & ATHN_FLAG_3TREDUCE_CHAIN) { |
1976 | /* |
1977 | * All self-generated frames are sent using two Tx chains |
1978 | * on these chips to not exceed PCIe power requirements. |
1979 | */ |
1980 | AR_WRITE(sc, AR_SELFGEN_MASK, 0x3); |
1981 | } |
1982 | else |
1983 | AR_WRITE(sc, AR_SELFGEN_MASK, sc->sc_txchainmask); |
1984 | AR_WRITE_BARRIER(sc); |
1985 | } |
1986 | |
1987 | Static void |
1988 | ar9003_set_rxchains(struct athn_softc *sc) |
1989 | { |
1990 | if (sc->sc_rxchainmask == 0x3 || sc->sc_rxchainmask == 0x5) { |
1991 | AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask); |
1992 | AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask); |
1993 | AR_WRITE_BARRIER(sc); |
1994 | } |
1995 | } |
1996 | |
1997 | #ifdef notused |
1998 | Static void |
1999 | ar9003_read_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext) |
2000 | { |
2001 | /* Sign-extends 9-bit value (assumes upper bits are zeroes). */ |
2002 | #define SIGN_EXT(v) (((v) ^ 0x100) - 0x100) |
2003 | uint32_t reg; |
2004 | int i; |
2005 | |
2006 | for (i = 0; i < sc->sc_nrxchains; i++) { |
2007 | reg = AR_READ(sc, AR_PHY_CCA(i)); |
2008 | nf[i] = MS(reg, AR_PHY_MINCCA_PWR); |
2009 | nf[i] = SIGN_EXT(nf[i]); |
2010 | |
2011 | reg = AR_READ(sc, AR_PHY_EXT_CCA(i)); |
2012 | nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR); |
2013 | nf_ext[i] = SIGN_EXT(nf_ext[i]); |
2014 | } |
2015 | #undef SIGN_EXT |
2016 | } |
2017 | #endif /* notused */ |
2018 | |
2019 | #ifdef notused |
2020 | Static void |
2021 | ar9003_write_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext) |
2022 | { |
2023 | uint32_t reg; |
2024 | int i; |
2025 | |
2026 | for (i = 0; i < sc->sc_nrxchains; i++) { |
2027 | reg = AR_READ(sc, AR_PHY_CCA(i)); |
2028 | reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); |
2029 | AR_WRITE(sc, AR_PHY_CCA(i), reg); |
2030 | |
2031 | reg = AR_READ(sc, AR_PHY_EXT_CCA(i)); |
2032 | reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]); |
2033 | AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg); |
2034 | } |
2035 | AR_WRITE_BARRIER(sc); |
2036 | } |
2037 | #endif /* notused */ |
2038 | |
2039 | #ifdef notused |
2040 | Static void |
2041 | ar9003_get_noisefloor(struct athn_softc *sc, struct ieee80211_channel *c) |
2042 | { |
2043 | int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS]; |
2044 | int16_t cca_min, cca_max; |
2045 | int i; |
2046 | |
2047 | if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { |
2048 | /* Noisefloor calibration not finished. */ |
2049 | return; |
2050 | } |
2051 | /* Noisefloor calibration is finished. */ |
2052 | ar9003_read_noisefloor(sc, nf, nf_ext); |
2053 | |
2054 | if (IEEE80211_IS_CHAN_2GHZ(c)) { |
2055 | cca_min = sc->sc_cca_min_2g; |
2056 | cca_max = sc->sc_cca_max_2g; |
2057 | } |
2058 | else { |
2059 | cca_min = sc->sc_cca_min_5g; |
2060 | cca_max = sc->sc_cca_max_5g; |
2061 | } |
2062 | /* Update noisefloor history. */ |
2063 | for (i = 0; i < sc->sc_nrxchains; i++) { |
2064 | if (nf[i] < cca_min) |
2065 | nf[i] = cca_min; |
2066 | else if (nf[i] > cca_max) |
2067 | nf[i] = cca_max; |
2068 | if (nf_ext[i] < cca_min) |
2069 | nf_ext[i] = cca_min; |
2070 | else if (nf_ext[i] > cca_max) |
2071 | nf_ext[i] = cca_max; |
2072 | |
2073 | sc->sc_nf_hist[sc->sc_nf_hist_cur].nf[i] = nf[i]; |
2074 | sc->sc_nf_hist[sc->sc_nf_hist_cur].nf_ext[i] = nf_ext[i]; |
2075 | } |
2076 | if (++sc->sc_nf_hist_cur >= ATHN_NF_CAL_HIST_MAX) |
2077 | sc->sc_nf_hist_cur = 0; |
2078 | } |
2079 | #endif /* notused */ |
2080 | |
2081 | #ifdef notused |
2082 | Static void |
2083 | ar9003_bb_load_noisefloor(struct athn_softc *sc) |
2084 | { |
2085 | int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS]; |
2086 | int i, ntries; |
2087 | |
2088 | /* Write filtered noisefloor values. */ |
2089 | for (i = 0; i < sc->sc_nrxchains; i++) { |
2090 | nf[i] = sc->sc_nf_priv[i] * 2; |
2091 | nf_ext[i] = sc->sc_nf_ext_priv[i] * 2; |
2092 | } |
2093 | ar9003_write_noisefloor(sc, nf, nf_ext); |
2094 | |
2095 | /* Load filtered noisefloor values into baseband. */ |
2096 | AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); |
2097 | AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); |
2098 | AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); |
2099 | /* Wait for load to complete. */ |
2100 | for (ntries = 0; ntries < 1000; ntries++) { |
2101 | if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)) |
2102 | break; |
2103 | DELAY(10); |
2104 | } |
2105 | if (ntries == 1000) { |
2106 | DPRINTFN(DBG_RF, sc, "failed to load noisefloor values\n" ); |
2107 | return; |
2108 | } |
2109 | |
2110 | /* Restore noisefloor values to initial (max) values. */ |
2111 | for (i = 0; i < AR_MAX_CHAINS; i++) |
2112 | nf[i] = nf_ext[i] = -50 * 2; |
2113 | ar9003_write_noisefloor(sc, nf, nf_ext); |
2114 | } |
2115 | #endif /* notused */ |
2116 | |
2117 | #ifdef notused |
2118 | Static void |
2119 | ar9300_noisefloor_calib(struct athn_softc *sc) |
2120 | { |
2121 | |
2122 | AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); |
2123 | AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); |
2124 | AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); |
2125 | } |
2126 | #endif /* notused */ |
2127 | |
2128 | Static void |
2129 | ar9003_do_noisefloor_calib(struct athn_softc *sc) |
2130 | { |
2131 | |
2132 | AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); |
2133 | } |
2134 | |
2135 | PUBLIC int |
2136 | ar9003_init_calib(struct athn_softc *sc) |
2137 | { |
2138 | uint8_t txchainmask, rxchainmask; |
2139 | uint32_t reg; |
2140 | int ntries; |
2141 | |
2142 | /* Save chains masks. */ |
2143 | txchainmask = sc->sc_txchainmask; |
2144 | rxchainmask = sc->sc_rxchainmask; |
2145 | /* Configure hardware before calibration. */ |
2146 | if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_CHAIN2_DISABLE) |
2147 | txchainmask = rxchainmask = 0x3; |
2148 | else |
2149 | txchainmask = rxchainmask = 0x7; |
2150 | ar9003_init_chains(sc); |
2151 | |
2152 | /* Perform Tx IQ calibration. */ |
2153 | ar9003_calib_tx_iq(sc); |
2154 | /* Disable and re-enable the PHY chips. */ |
2155 | AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); |
2156 | AR_WRITE_BARRIER(sc); |
2157 | DELAY(5); |
2158 | AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); |
2159 | |
2160 | /* Calibrate the AGC. */ |
2161 | AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); |
2162 | /* Poll for offset calibration completion. */ |
2163 | for (ntries = 0; ntries < 10000; ntries++) { |
2164 | reg = AR_READ(sc, AR_PHY_AGC_CONTROL); |
2165 | if (!(reg & AR_PHY_AGC_CONTROL_CAL)) |
2166 | break; |
2167 | DELAY(10); |
2168 | } |
2169 | if (ntries == 10000) |
2170 | return ETIMEDOUT; |
2171 | |
2172 | /* Restore chains masks. */ |
2173 | sc->sc_txchainmask = txchainmask; |
2174 | sc->sc_rxchainmask = rxchainmask; |
2175 | ar9003_init_chains(sc); |
2176 | |
2177 | return 0; |
2178 | } |
2179 | |
2180 | Static void |
2181 | ar9003_do_calib(struct athn_softc *sc) |
2182 | { |
2183 | uint32_t reg; |
2184 | |
2185 | if (sc->sc_cur_calib_mask & ATHN_CAL_IQ) { |
2186 | reg = AR_READ(sc, AR_PHY_TIMING4); |
2187 | reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10); |
2188 | AR_WRITE(sc, AR_PHY_TIMING4, reg); |
2189 | AR_WRITE(sc, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); |
2190 | AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); |
2191 | AR_WRITE_BARRIER(sc); |
2192 | } |
2193 | else if (sc->sc_cur_calib_mask & ATHN_CAL_TEMP) { |
2194 | AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM, |
2195 | AR_PHY_65NM_CH0_THERM_LOCAL); |
2196 | AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM, |
2197 | AR_PHY_65NM_CH0_THERM_START); |
2198 | AR_WRITE_BARRIER(sc); |
2199 | } |
2200 | } |
2201 | |
2202 | Static void |
2203 | ar9003_next_calib(struct athn_softc *sc) |
2204 | { |
2205 | /* Check if we have any calibration in progress. */ |
2206 | if (sc->sc_cur_calib_mask != 0) { |
2207 | if (!(AR_READ(sc, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) { |
2208 | /* Calibration completed for current sample. */ |
2209 | ar9003_calib_iq(sc); |
2210 | } |
2211 | } |
2212 | } |
2213 | |
2214 | Static void |
2215 | ar9003_calib_iq(struct athn_softc *sc) |
2216 | { |
2217 | struct athn_iq_cal *cal; |
2218 | uint32_t reg, i_coff_denom, q_coff_denom; |
2219 | int32_t i_coff, q_coff; |
2220 | int i, iq_corr_neg; |
2221 | |
2222 | for (i = 0; i < AR_MAX_CHAINS; i++) { |
2223 | cal = &sc->sc_calib.iq[i]; |
2224 | |
2225 | /* Read IQ calibration measures (clear on read). */ |
2226 | cal->pwr_meas_i = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_0_B(i)); |
2227 | cal->pwr_meas_q = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_1_B(i)); |
2228 | cal->iq_corr_meas = |
2229 | (int32_t)AR_READ(sc, AR_PHY_IQ_ADC_MEAS_2_B(i)); |
2230 | } |
2231 | |
2232 | for (i = 0; i < sc->sc_nrxchains; i++) { |
2233 | cal = &sc->sc_calib.iq[i]; |
2234 | |
2235 | if (cal->pwr_meas_q == 0) |
2236 | continue; |
2237 | |
2238 | if ((iq_corr_neg = cal->iq_corr_meas) < 0) |
2239 | cal->iq_corr_meas = -cal->iq_corr_meas; |
2240 | |
2241 | i_coff_denom = |
2242 | (cal->pwr_meas_i / 2 + cal->pwr_meas_q / 2) / 256; |
2243 | q_coff_denom = cal->pwr_meas_q / 64; |
2244 | |
2245 | if (i_coff_denom == 0 || q_coff_denom == 0) |
2246 | continue; /* Prevents division by zero. */ |
2247 | |
2248 | i_coff = cal->iq_corr_meas / i_coff_denom; |
2249 | q_coff = (cal->pwr_meas_i / q_coff_denom) - 64; |
2250 | |
2251 | if (i_coff > 63) |
2252 | i_coff = 63; |
2253 | else if (i_coff < -63) |
2254 | i_coff = -63; |
2255 | /* Negate i_coff if iq_corr_meas is positive. */ |
2256 | if (!iq_corr_neg) |
2257 | i_coff = -i_coff; |
2258 | if (q_coff > 63) |
2259 | q_coff = 63; |
2260 | else if (q_coff < -63) |
2261 | q_coff = -63; |
2262 | |
2263 | DPRINTFN(DBG_RF, sc, "IQ calibration for chain %d\n" , i); |
2264 | reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i)); |
2265 | reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, i_coff); |
2266 | reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, q_coff); |
2267 | AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg); |
2268 | } |
2269 | |
2270 | /* Apply new settings. */ |
2271 | AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0), |
2272 | AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE); |
2273 | AR_WRITE_BARRIER(sc); |
2274 | |
2275 | /* IQ calibration done. */ |
2276 | sc->sc_cur_calib_mask &= ~ATHN_CAL_IQ; |
2277 | memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); |
2278 | } |
2279 | |
2280 | #define DELPT 32 |
2281 | Static int |
2282 | ar9003_get_iq_corr(struct athn_softc *sc, int32_t res[6], int32_t coeff[2]) |
2283 | { |
2284 | /* Sign-extends 12-bit value (assumes upper bits are zeroes). */ |
2285 | #define SIGN_EXT(v) (((v) ^ 0x800) - 0x800) |
2286 | #define SCALE (1 << 15) |
2287 | #define SHIFT (1 << 8) |
2288 | struct { |
2289 | int32_t m, p, c; |
2290 | } val[2][2]; |
2291 | int32_t mag[2][2], phs[2][2], cos[2], sin[2]; |
2292 | int32_t div, f1, f2, f3, m, p, c; |
2293 | int32_t txmag, txphs, rxmag, rxphs; |
2294 | int32_t q_coff, i_coff; |
2295 | int i, j; |
2296 | |
2297 | /* Extract our twelve signed 12-bit values from res[] array. */ |
2298 | val[0][0].m = res[0] & 0xfff; |
2299 | val[0][0].p = (res[0] >> 12) & 0xfff; |
2300 | val[0][0].c = ((res[0] >> 24) & 0xff) | (res[1] & 0xf) << 8; |
2301 | |
2302 | val[0][1].m = (res[1] >> 4) & 0xfff; |
2303 | val[0][1].p = res[2] & 0xfff; |
2304 | val[0][1].c = (res[2] >> 12) & 0xfff; |
2305 | |
2306 | val[1][0].m = ((res[2] >> 24) & 0xff) | (res[3] & 0xf) << 8; |
2307 | val[1][0].p = (res[3] >> 4) & 0xfff; |
2308 | val[1][0].c = res[4] & 0xfff; |
2309 | |
2310 | val[1][1].m = (res[4] >> 12) & 0xfff; |
2311 | val[1][1].p = ((res[4] >> 24) & 0xff) | (res[5] & 0xf) << 8; |
2312 | val[1][1].c = (res[5] >> 4) & 0xfff; |
2313 | |
2314 | for (i = 0; i < 2; i++) { |
2315 | int32_t ymin, ymax; |
2316 | for (j = 0; j < 2; j++) { |
2317 | m = SIGN_EXT(val[i][j].m); |
2318 | p = SIGN_EXT(val[i][j].p); |
2319 | c = SIGN_EXT(val[i][j].c); |
2320 | |
2321 | if (p == 0) |
2322 | return 1; /* Prevent division by 0. */ |
2323 | |
2324 | mag[i][j] = (m * SCALE) / p; |
2325 | phs[i][j] = (c * SCALE) / p; |
2326 | } |
2327 | sin[i] = ((mag[i][0] - mag[i][1]) * SHIFT) / DELPT; |
2328 | cos[i] = ((phs[i][0] - phs[i][1]) * SHIFT) / DELPT; |
2329 | /* Find magnitude by approximation. */ |
2330 | ymin = MIN(abs(sin[i]), abs(cos[i])); |
2331 | ymax = MAX(abs(sin[i]), abs(cos[i])); |
2332 | div = ymax - (ymax / 32) + (ymin / 8) + (ymin / 4); |
2333 | if (div == 0) |
2334 | return 1; /* Prevent division by 0. */ |
2335 | /* Normalize sin and cos by magnitude. */ |
2336 | sin[i] = (sin[i] * SCALE) / div; |
2337 | cos[i] = (cos[i] * SCALE) / div; |
2338 | } |
2339 | |
2340 | /* Compute IQ mismatch (solve 4x4 linear equation). */ |
2341 | f1 = cos[0] - cos[1]; |
2342 | f3 = sin[0] - sin[1]; |
2343 | f2 = (f1 * f1 + f3 * f3) / SCALE; |
2344 | if (f2 == 0) |
2345 | return 1; /* Prevent division by 0. */ |
2346 | |
2347 | /* Compute Tx magnitude mismatch. */ |
2348 | txmag = (f1 * ( mag[0][0] - mag[1][0]) + |
2349 | f3 * ( phs[0][0] - phs[1][0])) / f2; |
2350 | /* Compute Tx phase mismatch. */ |
2351 | txphs = (f3 * (-mag[0][0] + mag[1][0]) + |
2352 | f1 * ( phs[0][0] - phs[1][0])) / f2; |
2353 | |
2354 | if (txmag == SCALE) |
2355 | return 1; /* Prevent division by 0. */ |
2356 | |
2357 | /* Compute Rx magnitude mismatch. */ |
2358 | rxmag = mag[0][0] - (cos[0] * txmag + sin[0] * txphs) / SCALE; |
2359 | /* Compute Rx phase mismatch. */ |
2360 | rxphs = phs[0][0] + (sin[0] * txmag - cos[0] * txphs) / SCALE; |
2361 | |
2362 | if (-rxmag == SCALE) |
2363 | return 1; /* Prevent division by 0. */ |
2364 | |
2365 | txmag = (txmag * SCALE) / (SCALE - txmag); |
2366 | txphs = -txphs; |
2367 | |
2368 | q_coff = (txmag * 128) / SCALE; |
2369 | if (q_coff < -63) |
2370 | q_coff = -63; |
2371 | else if (q_coff > 63) |
2372 | q_coff = 63; |
2373 | i_coff = (txphs * 256) / SCALE; |
2374 | if (i_coff < -63) |
2375 | i_coff = -63; |
2376 | else if (i_coff > 63) |
2377 | i_coff = 63; |
2378 | coeff[0] = q_coff * 128 + i_coff; |
2379 | |
2380 | rxmag = (-rxmag * SCALE) / (SCALE + rxmag); |
2381 | rxphs = -rxphs; |
2382 | |
2383 | q_coff = (rxmag * 128) / SCALE; |
2384 | if (q_coff < -63) |
2385 | q_coff = -63; |
2386 | else if (q_coff > 63) |
2387 | q_coff = 63; |
2388 | i_coff = (rxphs * 256) / SCALE; |
2389 | if (i_coff < -63) |
2390 | i_coff = -63; |
2391 | else if (i_coff > 63) |
2392 | i_coff = 63; |
2393 | coeff[1] = q_coff * 128 + i_coff; |
2394 | |
2395 | return 0; |
2396 | #undef SHIFT |
2397 | #undef SCALE |
2398 | #undef SIGN_EXT |
2399 | } |
2400 | |
2401 | Static int |
2402 | ar9003_calib_tx_iq(struct athn_softc *sc) |
2403 | { |
2404 | uint32_t reg; |
2405 | int32_t res[6], coeff[2]; |
2406 | int i, j, ntries; |
2407 | |
2408 | reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1); |
2409 | reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT); |
2410 | AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg); |
2411 | |
2412 | /* Start Tx IQ calibration. */ |
2413 | AR_SETBITS(sc, AR_PHY_TX_IQCAL_START, AR_PHY_TX_IQCAL_START_DO_CAL); |
2414 | /* Wait for completion. */ |
2415 | for (ntries = 0; ntries < 10000; ntries++) { |
2416 | reg = AR_READ(sc, AR_PHY_TX_IQCAL_START); |
2417 | if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL)) |
2418 | break; |
2419 | DELAY(10); |
2420 | } |
2421 | if (ntries == 10000) |
2422 | return ETIMEDOUT; |
2423 | |
2424 | for (i = 0; i < sc->sc_ntxchains; i++) { |
2425 | /* Read Tx IQ calibration status for this chain. */ |
2426 | reg = AR_READ(sc, AR_PHY_TX_IQCAL_STATUS_B(i)); |
2427 | if (reg & AR_PHY_TX_IQCAL_STATUS_FAILED) |
2428 | return EIO; |
2429 | /* |
2430 | * Read Tx IQ calibration results for this chain. |
2431 | * This consists in twelve signed 12-bit values. |
2432 | */ |
2433 | for (j = 0; j < 3; j++) { |
2434 | AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, |
2435 | AR_PHY_CHAN_INFO_TAB_S2_READ); |
2436 | reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j)); |
2437 | res[j * 2 + 0] = reg; |
2438 | |
2439 | AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, |
2440 | AR_PHY_CHAN_INFO_TAB_S2_READ); |
2441 | reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j)); |
2442 | res[j * 2 + 1] = reg & 0xffff; |
2443 | } |
2444 | |
2445 | /* Compute Tx IQ correction. */ |
2446 | if (ar9003_get_iq_corr(sc, res, coeff) != 0) |
2447 | return EIO; |
2448 | |
2449 | /* Write Tx IQ correction coefficients. */ |
2450 | reg = AR_READ(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i)); |
2451 | reg = RW(reg, AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, |
2452 | coeff[0]); |
2453 | AR_WRITE(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i), reg); |
2454 | |
2455 | reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i)); |
2456 | reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF, |
2457 | coeff[1] >> 7); |
2458 | reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF, |
2459 | coeff[1]); |
2460 | AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg); |
2461 | AR_WRITE_BARRIER(sc); |
2462 | } |
2463 | |
2464 | /* Enable Tx IQ correction. */ |
2465 | AR_SETBITS(sc, AR_PHY_TX_IQCAL_CONTROL_3, |
2466 | AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN); |
2467 | AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0), |
2468 | AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN); |
2469 | AR_WRITE_BARRIER(sc); |
2470 | return 0; |
2471 | } |
2472 | #undef DELPT |
2473 | |
2474 | /*- |
2475 | * The power amplifier predistortion state machine works as follows: |
2476 | * 1) Disable digital predistorters for all Tx chains |
2477 | * 2) Repeat steps 3~7 for all Tx chains |
2478 | * 3) Force Tx gain to that of training signal |
2479 | * 4) Send training signal (asynchronous) |
2480 | * 5) Wait for training signal to complete (asynchronous) |
2481 | * 6) Read PA measurements (input power, output power, output phase) |
2482 | * 7) Compute the predistortion function that linearizes PA output |
2483 | * 8) Write predistortion functions to hardware tables for all Tx chains |
2484 | * 9) Enable digital predistorters for all Tx chains |
2485 | */ |
2486 | #ifdef notused |
2487 | Static void |
2488 | ar9003_paprd_calib(struct athn_softc *sc, struct ieee80211_channel *c) |
2489 | { |
2490 | static const int scaling[] = { |
2491 | 261376, 248079, 233759, 220464, |
2492 | 208194, 196949, 185706, 175487 |
2493 | }; |
2494 | struct athn_ops *ops = &sc->sc_ops; |
2495 | uint32_t reg, ht20mask, ht40mask; |
2496 | int i; |
2497 | |
2498 | /* Read PA predistortion masks from ROM. */ |
2499 | ops->get_paprd_masks(sc, c, &ht20mask, &ht40mask); |
2500 | |
2501 | /* AM-to-AM: amplifier's amplitude characteristic. */ |
2502 | reg = AR_READ(sc, AR_PHY_PAPRD_AM2AM); |
2503 | reg = RW(reg, AR_PHY_PAPRD_AM2AM_MASK, ht20mask); |
2504 | AR_WRITE(sc, AR_PHY_PAPRD_AM2AM, reg); |
2505 | |
2506 | /* AM-to-PM: amplifier's phase transfer characteristic. */ |
2507 | reg = AR_READ(sc, AR_PHY_PAPRD_AM2PM); |
2508 | reg = RW(reg, AR_PHY_PAPRD_AM2PM_MASK, ht20mask); |
2509 | AR_WRITE(sc, AR_PHY_PAPRD_AM2PM, reg); |
2510 | |
2511 | reg = AR_READ(sc, AR_PHY_PAPRD_HT40); |
2512 | reg = RW(reg, AR_PHY_PAPRD_HT40_MASK, ht40mask); |
2513 | AR_WRITE(sc, AR_PHY_PAPRD_HT40, reg); |
2514 | |
2515 | for (i = 0; i < AR9003_MAX_CHAINS; i++) { |
2516 | AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(i), |
2517 | AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE); |
2518 | |
2519 | reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(i)); |
2520 | reg = RW(reg, AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT, 181); |
2521 | reg = RW(reg, AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT, 361); |
2522 | reg &= ~AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA; |
2523 | reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA; |
2524 | reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA; |
2525 | AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(i), reg); |
2526 | |
2527 | reg = AR_READ(sc, AR_PHY_PAPRD_CTRL0_B(i)); |
2528 | reg = RW(reg, AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH, 3); |
2529 | AR_WRITE(sc, AR_PHY_PAPRD_CTRL0_B(i), reg); |
2530 | } |
2531 | |
2532 | /* Disable all digital predistorters during calibration. */ |
2533 | for (i = 0; i < AR9003_MAX_CHAINS; i++) { |
2534 | AR_CLRBITS(sc, AR_PHY_PAPRD_CTRL0_B(i), |
2535 | AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE); |
2536 | } |
2537 | AR_WRITE_BARRIER(sc); |
2538 | |
2539 | /* |
2540 | * Configure training signal. |
2541 | */ |
2542 | reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL1); |
2543 | reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING, 28); |
2544 | reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP, 0x30); |
2545 | reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE; |
2546 | reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE; |
2547 | reg |= AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE; |
2548 | reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE; |
2549 | reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE; |
2550 | AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL1, reg); |
2551 | |
2552 | AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL2, 147); |
2553 | |
2554 | reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL3); |
2555 | reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN, 4); |
2556 | reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN, 4); |
2557 | reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES, 7); |
2558 | reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL, 1); |
2559 | if (AR_SREV_9485(sc)) |
2560 | reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -3); |
2561 | else |
2562 | reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -6); |
2563 | reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE, -15); |
2564 | reg |= AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE; |
2565 | AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL3, reg); |
2566 | |
2567 | reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL4); |
2568 | reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA, 0); |
2569 | reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR, 400); |
2570 | reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES, 100); |
2571 | AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL4, reg); |
2572 | |
2573 | for (i = 0; i < __arraycount(scaling); i++) { |
2574 | reg = AR_READ(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i)); |
2575 | reg = RW(reg, AR_PHY_PAPRD_PRE_POST_SCALING, scaling[i]); |
2576 | AR_WRITE(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i), reg); |
2577 | } |
2578 | |
2579 | /* Save Tx gain table. */ |
2580 | for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE; i++) |
2581 | sc->sc_txgain[i] = AR_READ(sc, AR_PHY_TXGAIN_TABLE(i)); |
2582 | |
2583 | /* Set Tx power of training signal (use setting for MCS0). */ |
2584 | sc->sc_trainpow = MS(AR_READ(sc, AR_PHY_PWRTX_RATE5), |
2585 | AR_PHY_PWRTX_RATE5_POWERTXHT20_0) - 4; |
2586 | |
2587 | /* |
2588 | * Start PA predistortion calibration state machine. |
2589 | */ |
2590 | /* Find first available Tx chain. */ |
2591 | sc->sc_paprd_curchain = 0; |
2592 | while (!(sc->sc_txchainmask & (1 << sc->sc_paprd_curchain))) |
2593 | sc->sc_paprd_curchain++; |
2594 | |
2595 | /* Make sure training done bit is clear. */ |
2596 | AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1, |
2597 | AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE); |
2598 | AR_WRITE_BARRIER(sc); |
2599 | |
2600 | /* Transmit training signal. */ |
2601 | ar9003_paprd_tx_tone(sc); |
2602 | } |
2603 | #endif /* notused */ |
2604 | |
2605 | Static int |
2606 | ar9003_get_desired_txgain(struct athn_softc *sc, int chain, int pow) |
2607 | { |
2608 | int32_t scale, atemp, avolt, tempcal, voltcal, temp, volt; |
2609 | int32_t tempcorr, voltcorr; |
2610 | uint32_t reg; |
2611 | int8_t delta; |
2612 | |
2613 | scale = MS(AR_READ(sc, AR_PHY_TPC_12), |
2614 | AR_PHY_TPC_12_DESIRED_SCALE_HT40_5); |
2615 | |
2616 | reg = AR_READ(sc, AR_PHY_TPC_19); |
2617 | atemp = MS(reg, AR_PHY_TPC_19_ALPHA_THERM); |
2618 | avolt = MS(reg, AR_PHY_TPC_19_ALPHA_VOLT); |
2619 | |
2620 | reg = AR_READ(sc, AR_PHY_TPC_18); |
2621 | tempcal = MS(reg, AR_PHY_TPC_18_THERM_CAL); |
2622 | voltcal = MS(reg, AR_PHY_TPC_18_VOLT_CAL); |
2623 | |
2624 | reg = AR_READ(sc, AR_PHY_BB_THERM_ADC_4); |
2625 | temp = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_THERM); |
2626 | volt = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_VOLT); |
2627 | |
2628 | delta = (int8_t)MS(AR_READ(sc, AR_PHY_TPC_11_B(chain)), |
2629 | AR_PHY_TPC_11_OLPC_GAIN_DELTA); |
2630 | |
2631 | /* Compute temperature and voltage correction. */ |
2632 | tempcorr = (atemp * (temp - tempcal) + 128) / 256; |
2633 | voltcorr = (avolt * (volt - voltcal) + 64) / 128; |
2634 | |
2635 | /* Compute desired Tx gain. */ |
2636 | return pow - delta - tempcorr - voltcorr + scale; |
2637 | } |
2638 | |
2639 | Static void |
2640 | ar9003_force_txgain(struct athn_softc *sc, uint32_t txgain) |
2641 | { |
2642 | uint32_t reg; |
2643 | |
2644 | reg = AR_READ(sc, AR_PHY_TX_FORCED_GAIN); |
2645 | reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN, |
2646 | MS(txgain, AR_PHY_TXGAIN_TXBB1DBGAIN)); |
2647 | reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN, |
2648 | MS(txgain, AR_PHY_TXGAIN_TXBB6DBGAIN)); |
2649 | reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXMXRGAIN, |
2650 | MS(txgain, AR_PHY_TXGAIN_TXMXRGAIN)); |
2651 | reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNA, |
2652 | MS(txgain, AR_PHY_TXGAIN_PADRVGNA)); |
2653 | reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNB, |
2654 | MS(txgain, AR_PHY_TXGAIN_PADRVGNB)); |
2655 | reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNC, |
2656 | MS(txgain, AR_PHY_TXGAIN_PADRVGNC)); |
2657 | reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGND, |
2658 | MS(txgain, AR_PHY_TXGAIN_PADRVGND)); |
2659 | reg &= ~AR_PHY_TX_FORCED_GAIN_ENABLE_PAL; |
2660 | reg &= ~AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN; |
2661 | AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, reg); |
2662 | |
2663 | reg = AR_READ(sc, AR_PHY_TPC_1); |
2664 | reg = RW(reg, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0); |
2665 | reg &= ~AR_PHY_TPC_1_FORCE_DAC_GAIN; |
2666 | AR_WRITE(sc, AR_PHY_TPC_1, reg); |
2667 | AR_WRITE_BARRIER(sc); |
2668 | } |
2669 | |
2670 | Static void |
2671 | ar9003_set_training_gain(struct athn_softc *sc, int chain) |
2672 | { |
2673 | size_t i; |
2674 | int gain; |
2675 | |
2676 | /* |
2677 | * Get desired gain for training signal power (take into account |
2678 | * current temperature/voltage). |
2679 | */ |
2680 | gain = ar9003_get_desired_txgain(sc, chain, sc->sc_trainpow); |
2681 | /* Find entry in table. */ |
2682 | for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE - 1; i++) |
2683 | if ((int)MS(sc->sc_txgain[i], AR_PHY_TXGAIN_INDEX) >= gain) |
2684 | break; |
2685 | ar9003_force_txgain(sc, sc->sc_txgain[i]); |
2686 | } |
2687 | |
2688 | Static int |
2689 | ar9003_paprd_tx_tone(struct athn_softc *sc) |
2690 | { |
2691 | #define TONE_LEN 1800 |
2692 | struct ieee80211com *ic = &sc->sc_ic; |
2693 | struct ieee80211_frame *wh; |
2694 | struct ieee80211_node *ni; |
2695 | struct mbuf *m; |
2696 | int error; |
2697 | |
2698 | /* Build a Null (no data) frame of TONE_LEN bytes. */ |
2699 | m = MCLGETI(NULL, M_DONTWAIT, NULL, TONE_LEN); |
2700 | if (m == NULL) |
2701 | return ENOBUFS; |
2702 | memset(mtod(m, void *), 0, TONE_LEN); |
2703 | wh = mtod(m, struct ieee80211_frame *); |
2704 | wh->i_fc[0] = IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_NODATA; |
2705 | wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; |
2706 | *(uint16_t *)wh->i_dur = htole16(10); /* XXX */ |
2707 | IEEE80211_ADDR_COPY(wh->i_addr1, ic->ic_myaddr); |
2708 | IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); |
2709 | IEEE80211_ADDR_COPY(wh->i_addr3, ic->ic_myaddr); |
2710 | m->m_pkthdr.len = m->m_len = TONE_LEN; |
2711 | |
2712 | /* Set gain of training signal. */ |
2713 | ar9003_set_training_gain(sc, sc->sc_paprd_curchain); |
2714 | |
2715 | /* Transmit training signal. */ |
2716 | ni = ieee80211_ref_node(ic->ic_bss); |
2717 | if ((error = ar9003_tx(sc, m, ni, ATHN_TXFLAG_PAPRD)) != 0) |
2718 | ieee80211_free_node(ni); |
2719 | return error; |
2720 | #undef TONE_LEN |
2721 | } |
2722 | |
2723 | static __inline int |
2724 | get_scale(int val) |
2725 | { |
2726 | int log = 0; |
2727 | |
2728 | /* Find the log base 2 (position of highest bit set). */ |
2729 | while (val >>= 1) |
2730 | log++; |
2731 | |
2732 | return (log > 10) ? log - 10 : 0; |
2733 | } |
2734 | |
2735 | /* |
2736 | * Compute predistortion function to linearize power amplifier output based |
2737 | * on feedback from training signal. |
2738 | */ |
2739 | Static int |
2740 | ar9003_compute_predistortion(struct athn_softc *sc, const uint32_t *lo, |
2741 | const uint32_t *hi) |
2742 | { |
2743 | #define NBINS 23 |
2744 | int chain = sc->sc_paprd_curchain; |
2745 | int x[NBINS + 1], y[NBINS + 1], t[NBINS + 1]; |
2746 | int b1[NBINS + 1], b2[NBINS + 1], xtilde[NBINS + 1]; |
2747 | int nsamples, txsum, rxsum, rosum, maxidx; |
2748 | int order, order5x, order5xrem, order3x, order3xrem, y5, y3; |
2749 | int icept, G, I, L, M, angle, xnonlin, y2, y4, sumy2, sumy4; |
2750 | int alpha, beta, scale, Qalpha, Qbeta, Qscale, Qx, Qb1, Qb2; |
2751 | int tavg, ttilde, maxb1abs, maxb2abs, maxxtildeabs, in; |
2752 | int tmp, i; |
2753 | |
2754 | /* Set values at origin. */ |
2755 | x[0] = y[0] = t[0] = 0; |
2756 | |
2757 | #define SCALE 32 |
2758 | maxidx = 0; |
2759 | for (i = 0; i < NBINS; i++) { |
2760 | nsamples = lo[i] & 0xffff; |
2761 | /* Skip bins that contain 16 or less samples. */ |
2762 | if (nsamples <= 16) { |
2763 | x[i + 1] = y[i + 1] = t[i + 1] = 0; |
2764 | continue; |
2765 | } |
2766 | txsum = (hi[i] & 0x7ff) << 16 | lo[i] >> 16; |
2767 | rxsum = (lo[i + NBINS] & 0xffff) << 5 | |
2768 | ((hi[i] >> 11) & 0x1f); |
2769 | rosum = (hi[i + NBINS] & 0x7ff) << 16 | hi[i + NBINS] >> 16; |
2770 | /* Sign-extend 27-bit value. */ |
2771 | rosum = (rosum ^ 0x4000000) - 0x4000000; |
2772 | |
2773 | txsum *= SCALE; |
2774 | rxsum *= SCALE; |
2775 | rosum *= SCALE; |
2776 | |
2777 | x[i + 1] = ((txsum + nsamples) / nsamples + SCALE) / SCALE; |
2778 | y[i + 1] = ((rxsum + nsamples) / nsamples + SCALE) / SCALE + |
2779 | SCALE * maxidx + SCALE / 2; |
2780 | t[i + 1] = (rosum + nsamples) / nsamples; |
2781 | maxidx++; |
2782 | } |
2783 | #undef SCALE |
2784 | |
2785 | #define SCALE_LOG 8 |
2786 | #define SCALE (1 << SCALE_LOG) |
2787 | if (x[6] == x[3]) |
2788 | return 1; /* Prevent division by 0. */ |
2789 | G = ((y[6] - y[3]) * SCALE + (x[6] - x[3])) / (x[6] - x[3]); |
2790 | if (G == 0) |
2791 | return 1; /* Prevent division by 0. */ |
2792 | |
2793 | sc->sc_gain1[chain] = G; /* Save low signal gain. */ |
2794 | |
2795 | /* Find interception point. */ |
2796 | icept = (G * (x[0] - x[3]) + SCALE) / SCALE + y[3]; |
2797 | for (i = 0; i <= 3; i++) { |
2798 | y[i] = i * 32; |
2799 | x[i] = (y[i] * SCALE + G) / G; |
2800 | } |
2801 | for (i = 4; i <= maxidx; i++) |
2802 | y[i] -= icept; |
2803 | |
2804 | xnonlin = x[maxidx] - (y[maxidx] * SCALE + G) / G; |
2805 | order = (xnonlin + y[maxidx]) / y[maxidx]; |
2806 | if (order == 0) |
2807 | M = 10; |
2808 | else if (order == 1) |
2809 | M = 9; |
2810 | else |
2811 | M = 8; |
2812 | |
2813 | I = (maxidx >= 16) ? 7 : maxidx / 2; |
2814 | L = maxidx - I; |
2815 | |
2816 | sumy2 = sumy4 = y2 = y4 = 0; |
2817 | for (i = 0; i <= L; i++) { |
2818 | if (y[i + I] == 0) |
2819 | return 1; /* Prevent division by 0. */ |
2820 | |
2821 | xnonlin = x[i + I] - ((y[i + I] * SCALE) + G) / G; |
2822 | xtilde[i] = ((xnonlin << M) + y[i + I]) / y[i + I]; |
2823 | xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I]; |
2824 | xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I]; |
2825 | |
2826 | y2 = (y[i + I] * y[i + I] + SCALE * SCALE) / (SCALE * SCALE); |
2827 | |
2828 | sumy2 += y2; |
2829 | sumy4 += y2 * y2; |
2830 | |
2831 | b1[i] = y2 * (L + 1); |
2832 | b2[i] = y2; |
2833 | } |
2834 | for (i = 0; i <= L; i++) { |
2835 | b1[i] -= sumy2; |
2836 | b2[i] = sumy4 - sumy2 * b2[i]; |
2837 | } |
2838 | |
2839 | maxxtildeabs = maxb1abs = maxb2abs = 0; |
2840 | for (i = 0; i <= L; i++) { |
2841 | tmp = abs(xtilde[i]); |
2842 | if (tmp > maxxtildeabs) |
2843 | maxxtildeabs = tmp; |
2844 | |
2845 | tmp = abs(b1[i]); |
2846 | if (tmp > maxb1abs) |
2847 | maxb1abs = tmp; |
2848 | |
2849 | tmp = abs(b2[i]); |
2850 | if (tmp > maxb2abs) |
2851 | maxb2abs = tmp; |
2852 | } |
2853 | Qx = get_scale(maxxtildeabs); |
2854 | Qb1 = get_scale(maxb1abs); |
2855 | Qb2 = get_scale(maxb2abs); |
2856 | for (i = 0; i <= L; i++) { |
2857 | xtilde[i] /= 1 << Qx; |
2858 | b1[i] /= 1 << Qb1; |
2859 | b2[i] /= 1 << Qb2; |
2860 | } |
2861 | |
2862 | alpha = beta = 0; |
2863 | for (i = 0; i <= L; i++) { |
2864 | alpha += b1[i] * xtilde[i]; |
2865 | beta += b2[i] * xtilde[i]; |
2866 | } |
2867 | |
2868 | scale = ((y4 / SCALE_LOG) * (L + 1) - |
2869 | (y2 / SCALE_LOG) * sumy2) * SCALE_LOG; |
2870 | |
2871 | Qscale = get_scale(abs(scale)); |
2872 | scale /= 1 << Qscale; |
2873 | Qalpha = get_scale(abs(alpha)); |
2874 | alpha /= 1 << Qalpha; |
2875 | Qbeta = get_scale(abs(beta)); |
2876 | beta /= 1 << Qbeta; |
2877 | |
2878 | order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale; |
2879 | order5x = 1 << (order / 5); |
2880 | order5xrem = 1 << (order % 5); |
2881 | |
2882 | order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale; |
2883 | order3x = 1 << (order / 3); |
2884 | order3xrem = 1 << (order % 3); |
2885 | |
2886 | for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { |
2887 | tmp = i * 32; |
2888 | |
2889 | /* Fifth order. */ |
2890 | y5 = ((beta * tmp) / 64) / order5x; |
2891 | y5 = (y5 * tmp) / order5x; |
2892 | y5 = (y5 * tmp) / order5x; |
2893 | y5 = (y5 * tmp) / order5x; |
2894 | y5 = (y5 * tmp) / order5x; |
2895 | y5 = y5 / order5xrem; |
2896 | |
2897 | /* Third oder. */ |
2898 | y3 = (alpha * tmp) / order3x; |
2899 | y3 = (y3 * tmp) / order3x; |
2900 | y3 = (y3 * tmp) / order3x; |
2901 | y3 = y3 / order3xrem; |
2902 | |
2903 | in = y5 + y3 + (SCALE * tmp) / G; |
2904 | if (i >= 2 && in < sc->sc_pa_in[chain][i - 1]) { |
2905 | in = sc->sc_pa_in[chain][i - 1] + |
2906 | (sc->sc_pa_in[chain][i - 1] - |
2907 | sc->sc_pa_in[chain][i - 2]); |
2908 | } |
2909 | if (in > 1400) |
2910 | in = 1400; |
2911 | sc->sc_pa_in[chain][i] = in; |
2912 | } |
2913 | |
2914 | /* Compute average theta of first 5 bins (linear region). */ |
2915 | tavg = 0; |
2916 | for (i = 1; i <= 5; i++) |
2917 | tavg += t[i]; |
2918 | tavg /= 5; |
2919 | for (i = 1; i <= 5; i++) |
2920 | t[i] = 0; |
2921 | for (i = 6; i <= maxidx; i++) |
2922 | t[i] -= tavg; |
2923 | |
2924 | alpha = beta = 0; |
2925 | for (i = 0; i <= L; i++) { |
2926 | ttilde = ((t[i + I] << M) + y[i + I]) / y[i + I]; |
2927 | ttilde = ((ttilde << M) + y[i + I]) / y[i + I]; |
2928 | ttilde = ((ttilde << M) + y[i + I]) / y[i + I]; |
2929 | |
2930 | alpha += b2[i] * ttilde; |
2931 | beta += b1[i] * ttilde; |
2932 | } |
2933 | |
2934 | Qalpha = get_scale(abs(alpha)); |
2935 | alpha /= 1 << Qalpha; |
2936 | Qbeta = get_scale(abs(beta)); |
2937 | beta /= 1 << Qbeta; |
2938 | |
2939 | order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale + 5; |
2940 | order5x = 1 << (order / 5); |
2941 | order5xrem = 1 << (order % 5); |
2942 | |
2943 | order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale + 5; |
2944 | order3x = 1 << (order / 3); |
2945 | order3xrem = 1 << (order % 3); |
2946 | |
2947 | for (i = 0; i <= 4; i++) |
2948 | sc->sc_angle[chain][i] = 0; /* Linear at that range. */ |
2949 | for (i = 5; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { |
2950 | tmp = i * 32; |
2951 | |
2952 | /* Fifth order. */ |
2953 | if (beta > 0) |
2954 | y5 = (((beta * tmp - 64) / 64) - order5x) / order5x; |
2955 | else |
2956 | y5 = (((beta * tmp - 64) / 64) + order5x) / order5x; |
2957 | y5 = (y5 * tmp) / order5x; |
2958 | y5 = (y5 * tmp) / order5x; |
2959 | y5 = (y5 * tmp) / order5x; |
2960 | y5 = (y5 * tmp) / order5x; |
2961 | y5 = y5 / order5xrem; |
2962 | |
2963 | /* Third oder. */ |
2964 | if (beta > 0) /* XXX alpha? */ |
2965 | y3 = (alpha * tmp - order3x) / order3x; |
2966 | else |
2967 | y3 = (alpha * tmp + order3x) / order3x; |
2968 | y3 = (y3 * tmp) / order3x; |
2969 | y3 = (y3 * tmp) / order3x; |
2970 | y3 = y3 / order3xrem; |
2971 | |
2972 | angle = y5 + y3; |
2973 | if (angle < -150) |
2974 | angle = -150; |
2975 | else if (angle > 150) |
2976 | angle = 150; |
2977 | sc->sc_angle[chain][i] = angle; |
2978 | } |
2979 | /* Angle for entry 4 is derived from angle for entry 5. */ |
2980 | sc->sc_angle[chain][4] = (sc->sc_angle[chain][5] + 2) / 2; |
2981 | |
2982 | return 0; |
2983 | #undef SCALE |
2984 | #undef SCALE_LOG |
2985 | #undef NBINS |
2986 | } |
2987 | |
2988 | Static void |
2989 | ar9003_enable_predistorter(struct athn_softc *sc, int chain) |
2990 | { |
2991 | uint32_t reg; |
2992 | int i; |
2993 | |
2994 | /* Write digital predistorter lookup table. */ |
2995 | for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { |
2996 | AR_WRITE(sc, AR_PHY_PAPRD_MEM_TAB_B(chain, i), |
2997 | SM(AR_PHY_PAPRD_PA_IN, sc->sc_pa_in[chain][i]) | |
2998 | SM(AR_PHY_PAPRD_ANGLE, sc->sc_angle[chain][i])); |
2999 | } |
3000 | |
3001 | reg = AR_READ(sc, AR_PHY_PA_GAIN123_B(chain)); |
3002 | reg = RW(reg, AR_PHY_PA_GAIN123_PA_GAIN1, sc->sc_gain1[chain]); |
3003 | AR_WRITE(sc, AR_PHY_PA_GAIN123_B(chain), reg); |
3004 | |
3005 | /* Indicate Tx power used for calibration (training signal). */ |
3006 | reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(chain)); |
3007 | reg = RW(reg, AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL, sc->sc_trainpow); |
3008 | AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(chain), reg); |
3009 | |
3010 | /* Enable digital predistorter for this chain. */ |
3011 | AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(chain), |
3012 | AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE); |
3013 | AR_WRITE_BARRIER(sc); |
3014 | } |
3015 | |
3016 | Static void |
3017 | ar9003_paprd_enable(struct athn_softc *sc) |
3018 | { |
3019 | int i; |
3020 | |
3021 | /* Enable digital predistorters for all Tx chains. */ |
3022 | for (i = 0; i < AR9003_MAX_CHAINS; i++) |
3023 | if (sc->sc_txchainmask & (1 << i)) |
3024 | ar9003_enable_predistorter(sc, i); |
3025 | } |
3026 | |
3027 | /* |
3028 | * This function is called when our training signal has been sent. |
3029 | */ |
3030 | Static void |
3031 | ar9003_paprd_tx_tone_done(struct athn_softc *sc) |
3032 | { |
3033 | uint32_t lo[48], hi[48]; |
3034 | size_t i; |
3035 | |
3036 | /* Make sure training is complete. */ |
3037 | if (!(AR_READ(sc, AR_PHY_PAPRD_TRAINER_STAT1) & |
3038 | AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE)) |
3039 | return; |
3040 | |
3041 | /* Read feedback from training signal. */ |
3042 | AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ); |
3043 | for (i = 0; i < __arraycount(lo); i++) |
3044 | lo[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i)); |
3045 | AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ); |
3046 | for (i = 0; i < __arraycount(hi); i++) |
3047 | hi[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i)); |
3048 | |
3049 | AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1, |
3050 | AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE); |
3051 | |
3052 | /* Compute predistortion function based on this feedback. */ |
3053 | if (ar9003_compute_predistortion(sc, lo, hi) != 0) |
3054 | return; |
3055 | |
3056 | /* Get next available Tx chain. */ |
3057 | while (++sc->sc_paprd_curchain < AR9003_MAX_CHAINS) |
3058 | if (sc->sc_txchainmask & (1 << sc->sc_paprd_curchain)) |
3059 | break; |
3060 | if (sc->sc_paprd_curchain == AR9003_MAX_CHAINS) { |
3061 | /* All Tx chains measured; enable digital predistortion. */ |
3062 | ar9003_paprd_enable(sc); |
3063 | } |
3064 | else /* Measure next Tx chain. */ |
3065 | ar9003_paprd_tx_tone(sc); |
3066 | } |
3067 | |
3068 | PUBLIC void |
3069 | ar9003_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT]) |
3070 | { |
3071 | |
3072 | /* Make sure forced gain is disabled. */ |
3073 | AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, 0); |
3074 | |
3075 | AR_WRITE(sc, AR_PHY_PWRTX_RATE1, |
3076 | (power[ATHN_POWER_OFDM18 ] & 0x3f) << 24 | |
3077 | (power[ATHN_POWER_OFDM12 ] & 0x3f) << 16 | |
3078 | (power[ATHN_POWER_OFDM9 ] & 0x3f) << 8 | |
3079 | (power[ATHN_POWER_OFDM6 ] & 0x3f)); |
3080 | AR_WRITE(sc, AR_PHY_PWRTX_RATE2, |
3081 | (power[ATHN_POWER_OFDM54 ] & 0x3f) << 24 | |
3082 | (power[ATHN_POWER_OFDM48 ] & 0x3f) << 16 | |
3083 | (power[ATHN_POWER_OFDM36 ] & 0x3f) << 8 | |
3084 | (power[ATHN_POWER_OFDM24 ] & 0x3f)); |
3085 | AR_WRITE(sc, AR_PHY_PWRTX_RATE3, |
3086 | (power[ATHN_POWER_CCK2_SP ] & 0x3f) << 24 | |
3087 | (power[ATHN_POWER_CCK2_LP ] & 0x3f) << 16 | |
3088 | /* NB: No eXtended Range for AR9003. */ |
3089 | (power[ATHN_POWER_CCK1_LP ] & 0x3f)); |
3090 | AR_WRITE(sc, AR_PHY_PWRTX_RATE4, |
3091 | (power[ATHN_POWER_CCK11_SP] & 0x3f) << 24 | |
3092 | (power[ATHN_POWER_CCK11_LP] & 0x3f) << 16 | |
3093 | (power[ATHN_POWER_CCK55_SP] & 0x3f) << 8 | |
3094 | (power[ATHN_POWER_CCK55_LP] & 0x3f)); |
3095 | /* |
3096 | * NB: AR_PHY_PWRTX_RATE5 needs to be written even if HT is disabled |
3097 | * because it is read by PA predistortion functions. |
3098 | */ |
3099 | AR_WRITE(sc, AR_PHY_PWRTX_RATE5, |
3100 | (power[ATHN_POWER_HT20( 5)] & 0x3f) << 24 | |
3101 | (power[ATHN_POWER_HT20( 4)] & 0x3f) << 16 | |
3102 | (power[ATHN_POWER_HT20( 1)] & 0x3f) << 8 | |
3103 | (power[ATHN_POWER_HT20( 0)] & 0x3f)); |
3104 | #ifndef IEEE80211_NO_HT |
3105 | AR_WRITE(sc, AR_PHY_PWRTX_RATE6, |
3106 | (power[ATHN_POWER_HT20(13)] & 0x3f) << 24 | |
3107 | (power[ATHN_POWER_HT20(12)] & 0x3f) << 16 | |
3108 | (power[ATHN_POWER_HT20( 7)] & 0x3f) << 8 | |
3109 | (power[ATHN_POWER_HT20( 6)] & 0x3f)); |
3110 | AR_WRITE(sc, AR_PHY_PWRTX_RATE7, |
3111 | (power[ATHN_POWER_HT40( 5)] & 0x3f) << 24 | |
3112 | (power[ATHN_POWER_HT40( 4)] & 0x3f) << 16 | |
3113 | (power[ATHN_POWER_HT40( 1)] & 0x3f) << 8 | |
3114 | (power[ATHN_POWER_HT40( 0)] & 0x3f)); |
3115 | AR_WRITE(sc, AR_PHY_PWRTX_RATE8, |
3116 | (power[ATHN_POWER_HT40(13)] & 0x3f) << 24 | |
3117 | (power[ATHN_POWER_HT40(12)] & 0x3f) << 16 | |
3118 | (power[ATHN_POWER_HT40( 7)] & 0x3f) << 8 | |
3119 | (power[ATHN_POWER_HT40( 6)] & 0x3f)); |
3120 | AR_WRITE(sc, AR_PHY_PWRTX_RATE10, |
3121 | (power[ATHN_POWER_HT20(21)] & 0x3f) << 24 | |
3122 | (power[ATHN_POWER_HT20(20)] & 0x3f) << 16 | |
3123 | (power[ATHN_POWER_HT20(15)] & 0x3f) << 8 | |
3124 | (power[ATHN_POWER_HT20(14)] & 0x3f)); |
3125 | AR_WRITE(sc, AR_PHY_PWRTX_RATE11, |
3126 | (power[ATHN_POWER_HT40(23)] & 0x3f) << 24 | |
3127 | (power[ATHN_POWER_HT40(22)] & 0x3f) << 16 | |
3128 | (power[ATHN_POWER_HT20(23)] & 0x3f) << 8 | |
3129 | (power[ATHN_POWER_HT20(22)] & 0x3f)); |
3130 | AR_WRITE(sc, AR_PHY_PWRTX_RATE12, |
3131 | (power[ATHN_POWER_HT40(21)] & 0x3f) << 24 | |
3132 | (power[ATHN_POWER_HT40(20)] & 0x3f) << 16 | |
3133 | (power[ATHN_POWER_HT40(15)] & 0x3f) << 8 | |
3134 | (power[ATHN_POWER_HT40(14)] & 0x3f)); |
3135 | #endif |
3136 | AR_WRITE_BARRIER(sc); |
3137 | } |
3138 | |
3139 | Static void |
3140 | ar9003_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c) |
3141 | { |
3142 | #define X(x) ((uint32_t)(x) << 2) |
3143 | const struct athn_gain *prog = sc->sc_rx_gain; |
3144 | const uint32_t *pvals; |
3145 | int i; |
3146 | |
3147 | if (IEEE80211_IS_CHAN_2GHZ(c)) |
3148 | pvals = prog->vals_2g; |
3149 | else |
3150 | pvals = prog->vals_5g; |
3151 | for (i = 0; i < prog->nregs; i++) |
3152 | AR_WRITE(sc, X(prog->regs[i]), pvals[i]); |
3153 | AR_WRITE_BARRIER(sc); |
3154 | #undef X |
3155 | } |
3156 | |
3157 | Static void |
3158 | ar9003_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c) |
3159 | { |
3160 | #define X(x) ((uint32_t)(x) << 2) |
3161 | const struct athn_gain *prog = sc->sc_tx_gain; |
3162 | const uint32_t *pvals; |
3163 | int i; |
3164 | |
3165 | if (IEEE80211_IS_CHAN_2GHZ(c)) |
3166 | pvals = prog->vals_2g; |
3167 | else |
3168 | pvals = prog->vals_5g; |
3169 | for (i = 0; i < prog->nregs; i++) |
3170 | AR_WRITE(sc, X(prog->regs[i]), pvals[i]); |
3171 | AR_WRITE_BARRIER(sc); |
3172 | #undef X |
3173 | } |
3174 | |
3175 | Static void |
3176 | ar9003_hw_init(struct athn_softc *sc, struct ieee80211_channel *c, |
3177 | struct ieee80211_channel *extc) |
3178 | { |
3179 | #define X(x) ((uint32_t)(x) << 2) |
3180 | struct athn_ops *ops = &sc->sc_ops; |
3181 | const struct athn_ini *ini = sc->sc_ini; |
3182 | const uint32_t *pvals; |
3183 | uint32_t reg; |
3184 | int i; |
3185 | |
3186 | /* |
3187 | * The common init values include the pre and core phases for the |
3188 | * SoC, MAC, BB and Radio subsystems. |
3189 | */ |
3190 | DPRINTFN(DBG_INIT, sc, "writing pre and core init vals\n" ); |
3191 | for (i = 0; i < ini->ncmregs; i++) { |
3192 | AR_WRITE(sc, X(ini->cmregs[i]), ini->cmvals[i]); |
3193 | if (AR_IS_ANALOG_REG(X(ini->cmregs[i]))) |
3194 | DELAY(100); |
3195 | if ((i & 0x1f) == 0) |
3196 | DELAY(1); |
3197 | } |
3198 | |
3199 | /* |
3200 | * The modal init values include the post phase for the SoC, MAC, |
3201 | * BB and Radio subsystems. |
3202 | */ |
3203 | #ifndef IEEE80211_NO_HT |
3204 | if (extc != NULL) { |
3205 | if (IEEE80211_IS_CHAN_2GHZ(c)) |
3206 | pvals = ini->vals_2g40; |
3207 | else |
3208 | pvals = ini->vals_5g40; |
3209 | } |
3210 | else |
3211 | #endif |
3212 | { |
3213 | if (IEEE80211_IS_CHAN_2GHZ(c)) |
3214 | pvals = ini->vals_2g20; |
3215 | else |
3216 | pvals = ini->vals_5g20; |
3217 | } |
3218 | DPRINTFN(DBG_INIT, sc, "writing post init vals\n" ); |
3219 | for (i = 0; i < ini->nregs; i++) { |
3220 | AR_WRITE(sc, X(ini->regs[i]), pvals[i]); |
3221 | if (AR_IS_ANALOG_REG(X(ini->regs[i]))) |
3222 | DELAY(100); |
3223 | if ((i & 0x1f) == 0) |
3224 | DELAY(1); |
3225 | } |
3226 | |
3227 | if (sc->sc_rx_gain != NULL) |
3228 | ar9003_reset_rx_gain(sc, c); |
3229 | if (sc->sc_tx_gain != NULL) |
3230 | ar9003_reset_tx_gain(sc, c); |
3231 | |
3232 | if (IEEE80211_IS_CHAN_5GHZ(c) && |
3233 | (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) { |
3234 | /* Update modal values for fast PLL clock. */ |
3235 | #ifndef IEEE80211_NO_HT |
3236 | if (extc != NULL) |
3237 | pvals = ini->fastvals_5g40; |
3238 | else |
3239 | #endif |
3240 | pvals = ini->fastvals_5g20; |
3241 | DPRINTFN(DBG_INIT, sc, "writing fast pll clock init vals\n" ); |
3242 | for (i = 0; i < ini->nfastregs; i++) { |
3243 | AR_WRITE(sc, X(ini->fastregs[i]), pvals[i]); |
3244 | if (AR_IS_ANALOG_REG(X(ini->fastregs[i]))) |
3245 | DELAY(100); |
3246 | if ((i & 0x1f) == 0) |
3247 | DELAY(1); |
3248 | } |
3249 | } |
3250 | |
3251 | /* |
3252 | * Set the RX_ABORT and RX_DIS bits to prevent frames with corrupted |
3253 | * descriptor status. |
3254 | */ |
3255 | AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); |
3256 | |
3257 | reg = AR_READ(sc, AR_PCU_MISC_MODE2); |
3258 | reg &= ~AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE; |
3259 | reg |= AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX; |
3260 | reg |= AR_PCU_MISC_MODE2_ENABLE_AGGWEP; |
3261 | AR_WRITE(sc, AR_PCU_MISC_MODE2, reg); |
3262 | AR_WRITE_BARRIER(sc); |
3263 | |
3264 | ar9003_set_phy(sc, c, extc); |
3265 | ar9003_init_chains(sc); |
3266 | |
3267 | ops->set_txpower(sc, c, extc); |
3268 | #undef X |
3269 | } |
3270 | |
3271 | PUBLIC void |
3272 | ar9003_get_lg_tpow(struct athn_softc *sc, struct ieee80211_channel *c, |
3273 | uint8_t ctl, const uint8_t *fbins, |
3274 | const struct ar_cal_target_power_leg *tgt, int nchans, uint8_t tpow[4]) |
3275 | { |
3276 | uint8_t fbin; |
3277 | int i, delta, lo, hi; |
3278 | |
3279 | lo = hi = -1; |
3280 | fbin = athn_chan2fbin(c); |
3281 | for (i = 0; i < nchans; i++) { |
3282 | delta = fbin - fbins[i]; |
3283 | /* Find the largest sample that is <= our frequency. */ |
3284 | if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo])) |
3285 | lo = i; |
3286 | /* Find the smallest sample that is >= our frequency. */ |
3287 | if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi])) |
3288 | hi = i; |
3289 | } |
3290 | if (lo == -1) |
3291 | lo = hi; |
3292 | else if (hi == -1) |
3293 | hi = lo; |
3294 | /* Interpolate values. */ |
3295 | for (i = 0; i < 4; i++) { |
3296 | tpow[i] = athn_interpolate(fbin, |
3297 | fbins[lo], tgt[lo].tPow2x[i], |
3298 | fbins[hi], tgt[hi].tPow2x[i]); |
3299 | } |
3300 | /* XXX Apply conformance test limit. */ |
3301 | } |
3302 | |
3303 | PUBLIC void |
3304 | ar9003_get_ht_tpow(struct athn_softc *sc, struct ieee80211_channel *c, |
3305 | uint8_t ctl, const uint8_t *fbins, |
3306 | const struct ar_cal_target_power_ht *tgt, int nchans, uint8_t tpow[14]) |
3307 | { |
3308 | uint8_t fbin; |
3309 | int i, delta, lo, hi; |
3310 | |
3311 | lo = hi = -1; |
3312 | fbin = athn_chan2fbin(c); |
3313 | for (i = 0; i < nchans; i++) { |
3314 | delta = fbin - fbins[i]; |
3315 | /* Find the largest sample that is <= our frequency. */ |
3316 | if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo])) |
3317 | lo = i; |
3318 | /* Find the smallest sample that is >= our frequency. */ |
3319 | if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi])) |
3320 | hi = i; |
3321 | } |
3322 | if (lo == -1) |
3323 | lo = hi; |
3324 | else if (hi == -1) |
3325 | hi = lo; |
3326 | /* Interpolate values. */ |
3327 | for (i = 0; i < 14; i++) { |
3328 | tpow[i] = athn_interpolate(fbin, |
3329 | fbins[lo], tgt[lo].tPow2x[i], |
3330 | fbins[hi], tgt[hi].tPow2x[i]); |
3331 | } |
3332 | /* XXX Apply conformance test limit. */ |
3333 | } |
3334 | |
3335 | /* |
3336 | * Adaptive noise immunity. |
3337 | */ |
3338 | Static void |
3339 | ar9003_set_noise_immunity_level(struct athn_softc *sc, int level) |
3340 | { |
3341 | int high = level == 4; |
3342 | uint32_t reg; |
3343 | |
3344 | reg = AR_READ(sc, AR_PHY_DESIRED_SZ); |
3345 | reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55); |
3346 | AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); |
3347 | |
3348 | reg = AR_READ(sc, AR_PHY_AGC); |
3349 | reg = RW(reg, AR_PHY_AGC_COARSE_LOW, high ? -70 : -64); |
3350 | reg = RW(reg, AR_PHY_AGC_COARSE_HIGH, high ? -12 : -14); |
3351 | AR_WRITE(sc, AR_PHY_AGC, reg); |
3352 | |
3353 | reg = AR_READ(sc, AR_PHY_FIND_SIG); |
3354 | reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78); |
3355 | AR_WRITE(sc, AR_PHY_FIND_SIG, reg); |
3356 | AR_WRITE_BARRIER(sc); |
3357 | } |
3358 | |
3359 | Static void |
3360 | ar9003_enable_ofdm_weak_signal(struct athn_softc *sc) |
3361 | { |
3362 | uint32_t reg; |
3363 | |
3364 | reg = AR_READ(sc, AR_PHY_SFCORR_LOW); |
3365 | reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50); |
3366 | reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40); |
3367 | reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48); |
3368 | AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg); |
3369 | |
3370 | reg = AR_READ(sc, AR_PHY_SFCORR); |
3371 | reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77); |
3372 | reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64); |
3373 | reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16); |
3374 | AR_WRITE(sc, AR_PHY_SFCORR, reg); |
3375 | |
3376 | reg = AR_READ(sc, AR_PHY_SFCORR_EXT); |
3377 | reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50); |
3378 | reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40); |
3379 | reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77); |
3380 | reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64); |
3381 | AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); |
3382 | |
3383 | AR_SETBITS(sc, AR_PHY_SFCORR_LOW, |
3384 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); |
3385 | AR_WRITE_BARRIER(sc); |
3386 | } |
3387 | |
3388 | Static void |
3389 | ar9003_disable_ofdm_weak_signal(struct athn_softc *sc) |
3390 | { |
3391 | uint32_t reg; |
3392 | |
3393 | reg = AR_READ(sc, AR_PHY_SFCORR_LOW); |
3394 | reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127); |
3395 | reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127); |
3396 | reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63); |
3397 | AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg); |
3398 | |
3399 | reg = AR_READ(sc, AR_PHY_SFCORR); |
3400 | reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127); |
3401 | reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127); |
3402 | reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31); |
3403 | AR_WRITE(sc, AR_PHY_SFCORR, reg); |
3404 | |
3405 | reg = AR_READ(sc, AR_PHY_SFCORR_EXT); |
3406 | reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127); |
3407 | reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127); |
3408 | reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127); |
3409 | reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127); |
3410 | AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); |
3411 | |
3412 | AR_CLRBITS(sc, AR_PHY_SFCORR_LOW, |
3413 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); |
3414 | AR_WRITE_BARRIER(sc); |
3415 | } |
3416 | |
3417 | Static void |
3418 | ar9003_set_cck_weak_signal(struct athn_softc *sc, int high) |
3419 | { |
3420 | uint32_t reg; |
3421 | |
3422 | reg = AR_READ(sc, AR_PHY_CCK_DETECT); |
3423 | reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8); |
3424 | AR_WRITE(sc, AR_PHY_CCK_DETECT, reg); |
3425 | AR_WRITE_BARRIER(sc); |
3426 | } |
3427 | |
3428 | Static void |
3429 | ar9003_set_firstep_level(struct athn_softc *sc, int level) |
3430 | { |
3431 | uint32_t reg; |
3432 | |
3433 | reg = AR_READ(sc, AR_PHY_FIND_SIG); |
3434 | reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4); |
3435 | AR_WRITE(sc, AR_PHY_FIND_SIG, reg); |
3436 | AR_WRITE_BARRIER(sc); |
3437 | } |
3438 | |
3439 | Static void |
3440 | ar9003_set_spur_immunity_level(struct athn_softc *sc, int level) |
3441 | { |
3442 | uint32_t reg; |
3443 | |
3444 | reg = AR_READ(sc, AR_PHY_TIMING5); |
3445 | reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2); |
3446 | AR_WRITE(sc, AR_PHY_TIMING5, reg); |
3447 | AR_WRITE_BARRIER(sc); |
3448 | } |
3449 | |