1/* $NetBSD: nouveau_subdev_fb_ramnv40.c,v 1.1.1.1 2014/08/06 12:36:30 riastradh Exp $ */
2
3/*
4 * Copyright 2013 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26
27#include <sys/cdefs.h>
28__KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_fb_ramnv40.c,v 1.1.1.1 2014/08/06 12:36:30 riastradh Exp $");
29
30#include <subdev/bios.h>
31#include <subdev/bios/bit.h>
32#include <subdev/bios/pll.h>
33#include <subdev/bios/init.h>
34#include <subdev/clock.h>
35#include <subdev/clock/pll.h>
36#include <subdev/timer.h>
37
38#include <engine/fifo.h>
39
40#include "nv40.h"
41
42int
43nv40_ram_calc(struct nouveau_fb *pfb, u32 freq)
44{
45 struct nouveau_bios *bios = nouveau_bios(pfb);
46 struct nv40_ram *ram = (void *)pfb->ram;
47 struct nvbios_pll pll;
48 int N1, M1, N2, M2;
49 int log2P, ret;
50
51 ret = nvbios_pll_parse(bios, 0x04, &pll);
52 if (ret) {
53 nv_error(pfb, "mclk pll data not found\n");
54 return ret;
55 }
56
57 ret = nv04_pll_calc(nv_subdev(pfb), &pll, freq,
58 &N1, &M1, &N2, &M2, &log2P);
59 if (ret < 0)
60 return ret;
61
62 ram->ctrl = 0x80000000 | (log2P << 16);
63 ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20;
64 if (N2 == M2) {
65 ram->ctrl |= 0x00000100;
66 ram->coef = (N1 << 8) | M1;
67 } else {
68 ram->ctrl |= 0x40000000;
69 ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
70 }
71
72 return 0;
73}
74
75int
76nv40_ram_prog(struct nouveau_fb *pfb)
77{
78 struct nouveau_bios *bios = nouveau_bios(pfb);
79 struct nv40_ram *ram = (void *)pfb->ram;
80 struct bit_entry M;
81 u32 crtc_mask = 0;
82 u8 sr1[2];
83 int i;
84
85 /* determine which CRTCs are active, fetch VGA_SR1 for each */
86 for (i = 0; i < 2; i++) {
87 u32 vbl = nv_rd32(pfb, 0x600808 + (i * 0x2000));
88 u32 cnt = 0;
89 do {
90 if (vbl != nv_rd32(pfb, 0x600808 + (i * 0x2000))) {
91 nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);
92 sr1[i] = nv_rd08(pfb, 0x0c03c5 + (i * 0x2000));
93 if (!(sr1[i] & 0x20))
94 crtc_mask |= (1 << i);
95 break;
96 }
97 udelay(1);
98 } while (cnt++ < 32);
99 }
100
101 /* wait for vblank start on active crtcs, disable memory access */
102 for (i = 0; i < 2; i++) {
103 if (!(crtc_mask & (1 << i)))
104 continue;
105 nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000);
106 nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
107 nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);
108 nv_wr08(pfb, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
109 }
110
111 /* prepare ram for reclocking */
112 nv_wr32(pfb, 0x1002d4, 0x00000001); /* precharge */
113 nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */
114 nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */
115 nv_mask(pfb, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
116 nv_wr32(pfb, 0x1002dc, 0x00000001); /* enable self-refresh */
117
118 /* change the PLL of each memory partition */
119 nv_mask(pfb, 0x00c040, 0x0000c000, 0x00000000);
120 switch (nv_device(pfb)->chipset) {
121 case 0x40:
122 case 0x45:
123 case 0x41:
124 case 0x42:
125 case 0x47:
126 nv_mask(pfb, 0x004044, 0xc0771100, ram->ctrl);
127 nv_mask(pfb, 0x00402c, 0xc0771100, ram->ctrl);
128 nv_wr32(pfb, 0x004048, ram->coef);
129 nv_wr32(pfb, 0x004030, ram->coef);
130 case 0x43:
131 case 0x49:
132 case 0x4b:
133 nv_mask(pfb, 0x004038, 0xc0771100, ram->ctrl);
134 nv_wr32(pfb, 0x00403c, ram->coef);
135 default:
136 nv_mask(pfb, 0x004020, 0xc0771100, ram->ctrl);
137 nv_wr32(pfb, 0x004024, ram->coef);
138 break;
139 }
140 udelay(100);
141 nv_mask(pfb, 0x00c040, 0x0000c000, 0x0000c000);
142
143 /* re-enable normal operation of memory controller */
144 nv_wr32(pfb, 0x1002dc, 0x00000000);
145 nv_mask(pfb, 0x100210, 0x80000000, 0x80000000);
146 udelay(100);
147
148 /* execute memory reset script from vbios */
149 if (!bit_entry(bios, 'M', &M)) {
150 struct nvbios_init init = {
151 .subdev = nv_subdev(pfb),
152 .bios = bios,
153 .offset = nv_ro16(bios, M.offset + 0x00),
154 .execute = 1,
155 };
156
157 nvbios_exec(&init);
158 }
159
160 /* make sure we're in vblank (hopefully the same one as before), and
161 * then re-enable crtc memory access
162 */
163 for (i = 0; i < 2; i++) {
164 if (!(crtc_mask & (1 << i)))
165 continue;
166 nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
167 nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);
168 nv_wr08(pfb, 0x0c03c5 + (i * 0x2000), sr1[i]);
169 }
170
171 return 0;
172}
173
174void
175nv40_ram_tidy(struct nouveau_fb *pfb)
176{
177}
178
179static int
180nv40_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
181 struct nouveau_oclass *oclass, void *data, u32 size,
182 struct nouveau_object **pobject)
183{
184 struct nouveau_fb *pfb = nouveau_fb(parent);
185 struct nv40_ram *ram;
186 u32 pbus1218 = nv_rd32(pfb, 0x001218);
187 int ret;
188
189 ret = nouveau_ram_create(parent, engine, oclass, &ram);
190 *pobject = nv_object(ram);
191 if (ret)
192 return ret;
193
194 switch (pbus1218 & 0x00000300) {
195 case 0x00000000: ram->base.type = NV_MEM_TYPE_SDRAM; break;
196 case 0x00000100: ram->base.type = NV_MEM_TYPE_DDR1; break;
197 case 0x00000200: ram->base.type = NV_MEM_TYPE_GDDR3; break;
198 case 0x00000300: ram->base.type = NV_MEM_TYPE_DDR2; break;
199 }
200
201 ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000;
202 ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
203 ram->base.tags = nv_rd32(pfb, 0x100320);
204 ram->base.calc = nv40_ram_calc;
205 ram->base.prog = nv40_ram_prog;
206 ram->base.tidy = nv40_ram_tidy;
207 return 0;
208}
209
210
211struct nouveau_oclass
212nv40_ram_oclass = {
213 .handle = 0,
214 .ofuncs = &(struct nouveau_ofuncs) {
215 .ctor = nv40_ram_create,
216 .dtor = _nouveau_ram_dtor,
217 .init = _nouveau_ram_init,
218 .fini = _nouveau_ram_fini,
219 }
220};
221