1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <drm/drmP.h>
28#include "radeon.h"
29#include "radeon_asic.h"
30#include <drm/radeon_drm.h>
31#include "nid.h"
32#include "atom.h"
33#include "ni_reg.h"
34#include "cayman_blit_shaders.h"
35#include "radeon_ucode.h"
36#include "clearstate_cayman.h"
37
38static const u32 tn_rlc_save_restore_register_list[] =
39{
40 0x98fc,
41 0x98f0,
42 0x9834,
43 0x9838,
44 0x9870,
45 0x9874,
46 0x8a14,
47 0x8b24,
48 0x8bcc,
49 0x8b10,
50 0x8c30,
51 0x8d00,
52 0x8d04,
53 0x8c00,
54 0x8c04,
55 0x8c10,
56 0x8c14,
57 0x8d8c,
58 0x8cf0,
59 0x8e38,
60 0x9508,
61 0x9688,
62 0x9608,
63 0x960c,
64 0x9610,
65 0x9614,
66 0x88c4,
67 0x8978,
68 0x88d4,
69 0x900c,
70 0x9100,
71 0x913c,
72 0x90e8,
73 0x9354,
74 0xa008,
75 0x98f8,
76 0x9148,
77 0x914c,
78 0x3f94,
79 0x98f4,
80 0x9b7c,
81 0x3f8c,
82 0x8950,
83 0x8954,
84 0x8a18,
85 0x8b28,
86 0x9144,
87 0x3f90,
88 0x915c,
89 0x9160,
90 0x9178,
91 0x917c,
92 0x9180,
93 0x918c,
94 0x9190,
95 0x9194,
96 0x9198,
97 0x919c,
98 0x91a8,
99 0x91ac,
100 0x91b0,
101 0x91b4,
102 0x91b8,
103 0x91c4,
104 0x91c8,
105 0x91cc,
106 0x91d0,
107 0x91d4,
108 0x91e0,
109 0x91e4,
110 0x91ec,
111 0x91f0,
112 0x91f4,
113 0x9200,
114 0x9204,
115 0x929c,
116 0x8030,
117 0x9150,
118 0x9a60,
119 0x920c,
120 0x9210,
121 0x9228,
122 0x922c,
123 0x9244,
124 0x9248,
125 0x91e8,
126 0x9294,
127 0x9208,
128 0x9224,
129 0x9240,
130 0x9220,
131 0x923c,
132 0x9258,
133 0x9744,
134 0xa200,
135 0xa204,
136 0xa208,
137 0xa20c,
138 0x8d58,
139 0x9030,
140 0x9034,
141 0x9038,
142 0x903c,
143 0x9040,
144 0x9654,
145 0x897c,
146 0xa210,
147 0xa214,
148 0x9868,
149 0xa02c,
150 0x9664,
151 0x9698,
152 0x949c,
153 0x8e10,
154 0x8e18,
155 0x8c50,
156 0x8c58,
157 0x8c60,
158 0x8c68,
159 0x89b4,
160 0x9830,
161 0x802c,
162};
163
164extern bool evergreen_is_display_hung(struct radeon_device *rdev);
165extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
166extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
167extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
168extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
169extern void evergreen_mc_program(struct radeon_device *rdev);
170extern void evergreen_irq_suspend(struct radeon_device *rdev);
171extern int evergreen_mc_init(struct radeon_device *rdev);
172extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
173extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
174extern void evergreen_program_aspm(struct radeon_device *rdev);
175extern void sumo_rlc_fini(struct radeon_device *rdev);
176extern int sumo_rlc_init(struct radeon_device *rdev);
177extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev);
178
179/* Firmware Names */
180MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
181MODULE_FIRMWARE("radeon/BARTS_me.bin");
182MODULE_FIRMWARE("radeon/BARTS_mc.bin");
183MODULE_FIRMWARE("radeon/BARTS_smc.bin");
184MODULE_FIRMWARE("radeon/BTC_rlc.bin");
185MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
186MODULE_FIRMWARE("radeon/TURKS_me.bin");
187MODULE_FIRMWARE("radeon/TURKS_mc.bin");
188MODULE_FIRMWARE("radeon/TURKS_smc.bin");
189MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
190MODULE_FIRMWARE("radeon/CAICOS_me.bin");
191MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
192MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
193MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
194MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
195MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
196MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
197MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
198MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
199MODULE_FIRMWARE("radeon/ARUBA_me.bin");
200MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
201
202
203static const u32 cayman_golden_registers2[] =
204{
205 0x3e5c, 0xffffffff, 0x00000000,
206 0x3e48, 0xffffffff, 0x00000000,
207 0x3e4c, 0xffffffff, 0x00000000,
208 0x3e64, 0xffffffff, 0x00000000,
209 0x3e50, 0xffffffff, 0x00000000,
210 0x3e60, 0xffffffff, 0x00000000
211};
212
213static const u32 cayman_golden_registers[] =
214{
215 0x5eb4, 0xffffffff, 0x00000002,
216 0x5e78, 0x8f311ff1, 0x001000f0,
217 0x3f90, 0xffff0000, 0xff000000,
218 0x9148, 0xffff0000, 0xff000000,
219 0x3f94, 0xffff0000, 0xff000000,
220 0x914c, 0xffff0000, 0xff000000,
221 0xc78, 0x00000080, 0x00000080,
222 0xbd4, 0x70073777, 0x00011003,
223 0xd02c, 0xbfffff1f, 0x08421000,
224 0xd0b8, 0x73773777, 0x02011003,
225 0x5bc0, 0x00200000, 0x50100000,
226 0x98f8, 0x33773777, 0x02011003,
227 0x98fc, 0xffffffff, 0x76541032,
228 0x7030, 0x31000311, 0x00000011,
229 0x2f48, 0x33773777, 0x42010001,
230 0x6b28, 0x00000010, 0x00000012,
231 0x7728, 0x00000010, 0x00000012,
232 0x10328, 0x00000010, 0x00000012,
233 0x10f28, 0x00000010, 0x00000012,
234 0x11b28, 0x00000010, 0x00000012,
235 0x12728, 0x00000010, 0x00000012,
236 0x240c, 0x000007ff, 0x00000000,
237 0x8a14, 0xf000001f, 0x00000007,
238 0x8b24, 0x3fff3fff, 0x00ff0fff,
239 0x8b10, 0x0000ff0f, 0x00000000,
240 0x28a4c, 0x07ffffff, 0x06000000,
241 0x10c, 0x00000001, 0x00010003,
242 0xa02c, 0xffffffff, 0x0000009b,
243 0x913c, 0x0000010f, 0x01000100,
244 0x8c04, 0xf8ff00ff, 0x40600060,
245 0x28350, 0x00000f01, 0x00000000,
246 0x9508, 0x3700001f, 0x00000002,
247 0x960c, 0xffffffff, 0x54763210,
248 0x88c4, 0x001f3ae3, 0x00000082,
249 0x88d0, 0xffffffff, 0x0f40df40,
250 0x88d4, 0x0000001f, 0x00000010,
251 0x8974, 0xffffffff, 0x00000000
252};
253
254static const u32 dvst_golden_registers2[] =
255{
256 0x8f8, 0xffffffff, 0,
257 0x8fc, 0x00380000, 0,
258 0x8f8, 0xffffffff, 1,
259 0x8fc, 0x0e000000, 0
260};
261
262static const u32 dvst_golden_registers[] =
263{
264 0x690, 0x3fff3fff, 0x20c00033,
265 0x918c, 0x0fff0fff, 0x00010006,
266 0x91a8, 0x0fff0fff, 0x00010006,
267 0x9150, 0xffffdfff, 0x6e944040,
268 0x917c, 0x0fff0fff, 0x00030002,
269 0x9198, 0x0fff0fff, 0x00030002,
270 0x915c, 0x0fff0fff, 0x00010000,
271 0x3f90, 0xffff0001, 0xff000000,
272 0x9178, 0x0fff0fff, 0x00070000,
273 0x9194, 0x0fff0fff, 0x00070000,
274 0x9148, 0xffff0001, 0xff000000,
275 0x9190, 0x0fff0fff, 0x00090008,
276 0x91ac, 0x0fff0fff, 0x00090008,
277 0x3f94, 0xffff0000, 0xff000000,
278 0x914c, 0xffff0000, 0xff000000,
279 0x929c, 0x00000fff, 0x00000001,
280 0x55e4, 0xff607fff, 0xfc000100,
281 0x8a18, 0xff000fff, 0x00000100,
282 0x8b28, 0xff000fff, 0x00000100,
283 0x9144, 0xfffc0fff, 0x00000100,
284 0x6ed8, 0x00010101, 0x00010000,
285 0x9830, 0xffffffff, 0x00000000,
286 0x9834, 0xf00fffff, 0x00000400,
287 0x9838, 0xfffffffe, 0x00000000,
288 0xd0c0, 0xff000fff, 0x00000100,
289 0xd02c, 0xbfffff1f, 0x08421000,
290 0xd0b8, 0x73773777, 0x12010001,
291 0x5bb0, 0x000000f0, 0x00000070,
292 0x98f8, 0x73773777, 0x12010001,
293 0x98fc, 0xffffffff, 0x00000010,
294 0x9b7c, 0x00ff0000, 0x00fc0000,
295 0x8030, 0x00001f0f, 0x0000100a,
296 0x2f48, 0x73773777, 0x12010001,
297 0x2408, 0x00030000, 0x000c007f,
298 0x8a14, 0xf000003f, 0x00000007,
299 0x8b24, 0x3fff3fff, 0x00ff0fff,
300 0x8b10, 0x0000ff0f, 0x00000000,
301 0x28a4c, 0x07ffffff, 0x06000000,
302 0x4d8, 0x00000fff, 0x00000100,
303 0xa008, 0xffffffff, 0x00010000,
304 0x913c, 0xffff03ff, 0x01000100,
305 0x8c00, 0x000000ff, 0x00000003,
306 0x8c04, 0xf8ff00ff, 0x40600060,
307 0x8cf0, 0x1fff1fff, 0x08e00410,
308 0x28350, 0x00000f01, 0x00000000,
309 0x9508, 0xf700071f, 0x00000002,
310 0x960c, 0xffffffff, 0x54763210,
311 0x20ef8, 0x01ff01ff, 0x00000002,
312 0x20e98, 0xfffffbff, 0x00200000,
313 0x2015c, 0xffffffff, 0x00000f40,
314 0x88c4, 0x001f3ae3, 0x00000082,
315 0x8978, 0x3fffffff, 0x04050140,
316 0x88d4, 0x0000001f, 0x00000010,
317 0x8974, 0xffffffff, 0x00000000
318};
319
320static const u32 scrapper_golden_registers[] =
321{
322 0x690, 0x3fff3fff, 0x20c00033,
323 0x918c, 0x0fff0fff, 0x00010006,
324 0x918c, 0x0fff0fff, 0x00010006,
325 0x91a8, 0x0fff0fff, 0x00010006,
326 0x91a8, 0x0fff0fff, 0x00010006,
327 0x9150, 0xffffdfff, 0x6e944040,
328 0x9150, 0xffffdfff, 0x6e944040,
329 0x917c, 0x0fff0fff, 0x00030002,
330 0x917c, 0x0fff0fff, 0x00030002,
331 0x9198, 0x0fff0fff, 0x00030002,
332 0x9198, 0x0fff0fff, 0x00030002,
333 0x915c, 0x0fff0fff, 0x00010000,
334 0x915c, 0x0fff0fff, 0x00010000,
335 0x3f90, 0xffff0001, 0xff000000,
336 0x3f90, 0xffff0001, 0xff000000,
337 0x9178, 0x0fff0fff, 0x00070000,
338 0x9178, 0x0fff0fff, 0x00070000,
339 0x9194, 0x0fff0fff, 0x00070000,
340 0x9194, 0x0fff0fff, 0x00070000,
341 0x9148, 0xffff0001, 0xff000000,
342 0x9148, 0xffff0001, 0xff000000,
343 0x9190, 0x0fff0fff, 0x00090008,
344 0x9190, 0x0fff0fff, 0x00090008,
345 0x91ac, 0x0fff0fff, 0x00090008,
346 0x91ac, 0x0fff0fff, 0x00090008,
347 0x3f94, 0xffff0000, 0xff000000,
348 0x3f94, 0xffff0000, 0xff000000,
349 0x914c, 0xffff0000, 0xff000000,
350 0x914c, 0xffff0000, 0xff000000,
351 0x929c, 0x00000fff, 0x00000001,
352 0x929c, 0x00000fff, 0x00000001,
353 0x55e4, 0xff607fff, 0xfc000100,
354 0x8a18, 0xff000fff, 0x00000100,
355 0x8a18, 0xff000fff, 0x00000100,
356 0x8b28, 0xff000fff, 0x00000100,
357 0x8b28, 0xff000fff, 0x00000100,
358 0x9144, 0xfffc0fff, 0x00000100,
359 0x9144, 0xfffc0fff, 0x00000100,
360 0x6ed8, 0x00010101, 0x00010000,
361 0x9830, 0xffffffff, 0x00000000,
362 0x9830, 0xffffffff, 0x00000000,
363 0x9834, 0xf00fffff, 0x00000400,
364 0x9834, 0xf00fffff, 0x00000400,
365 0x9838, 0xfffffffe, 0x00000000,
366 0x9838, 0xfffffffe, 0x00000000,
367 0xd0c0, 0xff000fff, 0x00000100,
368 0xd02c, 0xbfffff1f, 0x08421000,
369 0xd02c, 0xbfffff1f, 0x08421000,
370 0xd0b8, 0x73773777, 0x12010001,
371 0xd0b8, 0x73773777, 0x12010001,
372 0x5bb0, 0x000000f0, 0x00000070,
373 0x98f8, 0x73773777, 0x12010001,
374 0x98f8, 0x73773777, 0x12010001,
375 0x98fc, 0xffffffff, 0x00000010,
376 0x98fc, 0xffffffff, 0x00000010,
377 0x9b7c, 0x00ff0000, 0x00fc0000,
378 0x9b7c, 0x00ff0000, 0x00fc0000,
379 0x8030, 0x00001f0f, 0x0000100a,
380 0x8030, 0x00001f0f, 0x0000100a,
381 0x2f48, 0x73773777, 0x12010001,
382 0x2f48, 0x73773777, 0x12010001,
383 0x2408, 0x00030000, 0x000c007f,
384 0x8a14, 0xf000003f, 0x00000007,
385 0x8a14, 0xf000003f, 0x00000007,
386 0x8b24, 0x3fff3fff, 0x00ff0fff,
387 0x8b24, 0x3fff3fff, 0x00ff0fff,
388 0x8b10, 0x0000ff0f, 0x00000000,
389 0x8b10, 0x0000ff0f, 0x00000000,
390 0x28a4c, 0x07ffffff, 0x06000000,
391 0x28a4c, 0x07ffffff, 0x06000000,
392 0x4d8, 0x00000fff, 0x00000100,
393 0x4d8, 0x00000fff, 0x00000100,
394 0xa008, 0xffffffff, 0x00010000,
395 0xa008, 0xffffffff, 0x00010000,
396 0x913c, 0xffff03ff, 0x01000100,
397 0x913c, 0xffff03ff, 0x01000100,
398 0x90e8, 0x001fffff, 0x010400c0,
399 0x8c00, 0x000000ff, 0x00000003,
400 0x8c00, 0x000000ff, 0x00000003,
401 0x8c04, 0xf8ff00ff, 0x40600060,
402 0x8c04, 0xf8ff00ff, 0x40600060,
403 0x8c30, 0x0000000f, 0x00040005,
404 0x8cf0, 0x1fff1fff, 0x08e00410,
405 0x8cf0, 0x1fff1fff, 0x08e00410,
406 0x900c, 0x00ffffff, 0x0017071f,
407 0x28350, 0x00000f01, 0x00000000,
408 0x28350, 0x00000f01, 0x00000000,
409 0x9508, 0xf700071f, 0x00000002,
410 0x9508, 0xf700071f, 0x00000002,
411 0x9688, 0x00300000, 0x0017000f,
412 0x960c, 0xffffffff, 0x54763210,
413 0x960c, 0xffffffff, 0x54763210,
414 0x20ef8, 0x01ff01ff, 0x00000002,
415 0x20e98, 0xfffffbff, 0x00200000,
416 0x2015c, 0xffffffff, 0x00000f40,
417 0x88c4, 0x001f3ae3, 0x00000082,
418 0x88c4, 0x001f3ae3, 0x00000082,
419 0x8978, 0x3fffffff, 0x04050140,
420 0x8978, 0x3fffffff, 0x04050140,
421 0x88d4, 0x0000001f, 0x00000010,
422 0x88d4, 0x0000001f, 0x00000010,
423 0x8974, 0xffffffff, 0x00000000,
424 0x8974, 0xffffffff, 0x00000000
425};
426
427static void ni_init_golden_registers(struct radeon_device *rdev)
428{
429 switch (rdev->family) {
430 case CHIP_CAYMAN:
431 radeon_program_register_sequence(rdev,
432 cayman_golden_registers,
433 (const u32)ARRAY_SIZE(cayman_golden_registers));
434 radeon_program_register_sequence(rdev,
435 cayman_golden_registers2,
436 (const u32)ARRAY_SIZE(cayman_golden_registers2));
437 break;
438 case CHIP_ARUBA:
439 if ((rdev->pdev->device == 0x9900) ||
440 (rdev->pdev->device == 0x9901) ||
441 (rdev->pdev->device == 0x9903) ||
442 (rdev->pdev->device == 0x9904) ||
443 (rdev->pdev->device == 0x9905) ||
444 (rdev->pdev->device == 0x9906) ||
445 (rdev->pdev->device == 0x9907) ||
446 (rdev->pdev->device == 0x9908) ||
447 (rdev->pdev->device == 0x9909) ||
448 (rdev->pdev->device == 0x990A) ||
449 (rdev->pdev->device == 0x990B) ||
450 (rdev->pdev->device == 0x990C) ||
451 (rdev->pdev->device == 0x990D) ||
452 (rdev->pdev->device == 0x990E) ||
453 (rdev->pdev->device == 0x990F) ||
454 (rdev->pdev->device == 0x9910) ||
455 (rdev->pdev->device == 0x9913) ||
456 (rdev->pdev->device == 0x9917) ||
457 (rdev->pdev->device == 0x9918)) {
458 radeon_program_register_sequence(rdev,
459 dvst_golden_registers,
460 (const u32)ARRAY_SIZE(dvst_golden_registers));
461 radeon_program_register_sequence(rdev,
462 dvst_golden_registers2,
463 (const u32)ARRAY_SIZE(dvst_golden_registers2));
464 } else {
465 radeon_program_register_sequence(rdev,
466 scrapper_golden_registers,
467 (const u32)ARRAY_SIZE(scrapper_golden_registers));
468 radeon_program_register_sequence(rdev,
469 dvst_golden_registers2,
470 (const u32)ARRAY_SIZE(dvst_golden_registers2));
471 }
472 break;
473 default:
474 break;
475 }
476}
477
478#define BTC_IO_MC_REGS_SIZE 29
479
480static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
481 {0x00000077, 0xff010100},
482 {0x00000078, 0x00000000},
483 {0x00000079, 0x00001434},
484 {0x0000007a, 0xcc08ec08},
485 {0x0000007b, 0x00040000},
486 {0x0000007c, 0x000080c0},
487 {0x0000007d, 0x09000000},
488 {0x0000007e, 0x00210404},
489 {0x00000081, 0x08a8e800},
490 {0x00000082, 0x00030444},
491 {0x00000083, 0x00000000},
492 {0x00000085, 0x00000001},
493 {0x00000086, 0x00000002},
494 {0x00000087, 0x48490000},
495 {0x00000088, 0x20244647},
496 {0x00000089, 0x00000005},
497 {0x0000008b, 0x66030000},
498 {0x0000008c, 0x00006603},
499 {0x0000008d, 0x00000100},
500 {0x0000008f, 0x00001c0a},
501 {0x00000090, 0xff000001},
502 {0x00000094, 0x00101101},
503 {0x00000095, 0x00000fff},
504 {0x00000096, 0x00116fff},
505 {0x00000097, 0x60010000},
506 {0x00000098, 0x10010000},
507 {0x00000099, 0x00006000},
508 {0x0000009a, 0x00001000},
509 {0x0000009f, 0x00946a00}
510};
511
512static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
513 {0x00000077, 0xff010100},
514 {0x00000078, 0x00000000},
515 {0x00000079, 0x00001434},
516 {0x0000007a, 0xcc08ec08},
517 {0x0000007b, 0x00040000},
518 {0x0000007c, 0x000080c0},
519 {0x0000007d, 0x09000000},
520 {0x0000007e, 0x00210404},
521 {0x00000081, 0x08a8e800},
522 {0x00000082, 0x00030444},
523 {0x00000083, 0x00000000},
524 {0x00000085, 0x00000001},
525 {0x00000086, 0x00000002},
526 {0x00000087, 0x48490000},
527 {0x00000088, 0x20244647},
528 {0x00000089, 0x00000005},
529 {0x0000008b, 0x66030000},
530 {0x0000008c, 0x00006603},
531 {0x0000008d, 0x00000100},
532 {0x0000008f, 0x00001c0a},
533 {0x00000090, 0xff000001},
534 {0x00000094, 0x00101101},
535 {0x00000095, 0x00000fff},
536 {0x00000096, 0x00116fff},
537 {0x00000097, 0x60010000},
538 {0x00000098, 0x10010000},
539 {0x00000099, 0x00006000},
540 {0x0000009a, 0x00001000},
541 {0x0000009f, 0x00936a00}
542};
543
544static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
545 {0x00000077, 0xff010100},
546 {0x00000078, 0x00000000},
547 {0x00000079, 0x00001434},
548 {0x0000007a, 0xcc08ec08},
549 {0x0000007b, 0x00040000},
550 {0x0000007c, 0x000080c0},
551 {0x0000007d, 0x09000000},
552 {0x0000007e, 0x00210404},
553 {0x00000081, 0x08a8e800},
554 {0x00000082, 0x00030444},
555 {0x00000083, 0x00000000},
556 {0x00000085, 0x00000001},
557 {0x00000086, 0x00000002},
558 {0x00000087, 0x48490000},
559 {0x00000088, 0x20244647},
560 {0x00000089, 0x00000005},
561 {0x0000008b, 0x66030000},
562 {0x0000008c, 0x00006603},
563 {0x0000008d, 0x00000100},
564 {0x0000008f, 0x00001c0a},
565 {0x00000090, 0xff000001},
566 {0x00000094, 0x00101101},
567 {0x00000095, 0x00000fff},
568 {0x00000096, 0x00116fff},
569 {0x00000097, 0x60010000},
570 {0x00000098, 0x10010000},
571 {0x00000099, 0x00006000},
572 {0x0000009a, 0x00001000},
573 {0x0000009f, 0x00916a00}
574};
575
576static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
577 {0x00000077, 0xff010100},
578 {0x00000078, 0x00000000},
579 {0x00000079, 0x00001434},
580 {0x0000007a, 0xcc08ec08},
581 {0x0000007b, 0x00040000},
582 {0x0000007c, 0x000080c0},
583 {0x0000007d, 0x09000000},
584 {0x0000007e, 0x00210404},
585 {0x00000081, 0x08a8e800},
586 {0x00000082, 0x00030444},
587 {0x00000083, 0x00000000},
588 {0x00000085, 0x00000001},
589 {0x00000086, 0x00000002},
590 {0x00000087, 0x48490000},
591 {0x00000088, 0x20244647},
592 {0x00000089, 0x00000005},
593 {0x0000008b, 0x66030000},
594 {0x0000008c, 0x00006603},
595 {0x0000008d, 0x00000100},
596 {0x0000008f, 0x00001c0a},
597 {0x00000090, 0xff000001},
598 {0x00000094, 0x00101101},
599 {0x00000095, 0x00000fff},
600 {0x00000096, 0x00116fff},
601 {0x00000097, 0x60010000},
602 {0x00000098, 0x10010000},
603 {0x00000099, 0x00006000},
604 {0x0000009a, 0x00001000},
605 {0x0000009f, 0x00976b00}
606};
607
608int ni_mc_load_microcode(struct radeon_device *rdev)
609{
610 const __be32 *fw_data;
611 u32 mem_type, running, blackout = 0;
612 const u32 *io_mc_regs;
613 int i, ucode_size, regs_size;
614
615 if (!rdev->mc_fw)
616 return -EINVAL;
617
618 switch (rdev->family) {
619 case CHIP_BARTS:
620 io_mc_regs = &barts_io_mc_regs[0][0];
621 ucode_size = BTC_MC_UCODE_SIZE;
622 regs_size = BTC_IO_MC_REGS_SIZE;
623 break;
624 case CHIP_TURKS:
625 io_mc_regs = &turks_io_mc_regs[0][0];
626 ucode_size = BTC_MC_UCODE_SIZE;
627 regs_size = BTC_IO_MC_REGS_SIZE;
628 break;
629 case CHIP_CAICOS:
630 default:
631 io_mc_regs = &caicos_io_mc_regs[0][0];
632 ucode_size = BTC_MC_UCODE_SIZE;
633 regs_size = BTC_IO_MC_REGS_SIZE;
634 break;
635 case CHIP_CAYMAN:
636 io_mc_regs = &cayman_io_mc_regs[0][0];
637 ucode_size = CAYMAN_MC_UCODE_SIZE;
638 regs_size = BTC_IO_MC_REGS_SIZE;
639 break;
640 }
641
642 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
643 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
644
645 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
646 if (running) {
647 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
648 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
649 }
650
651 /* reset the engine and set to writable */
652 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
653 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
654
655 /* load mc io regs */
656 for (i = 0; i < regs_size; i++) {
657 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
658 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
659 }
660 /* load the MC ucode */
661 fw_data = (const __be32 *)rdev->mc_fw->data;
662 for (i = 0; i < ucode_size; i++)
663 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
664
665 /* put the engine back into the active state */
666 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
667 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
668 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
669
670 /* wait for training to complete */
671 for (i = 0; i < rdev->usec_timeout; i++) {
672 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
673 break;
674 udelay(1);
675 }
676
677 if (running)
678 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
679 }
680
681 return 0;
682}
683
684int ni_init_microcode(struct radeon_device *rdev)
685{
686 const char *chip_name;
687 const char *rlc_chip_name;
688 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
689 size_t smc_req_size = 0;
690 char fw_name[30];
691 int err;
692
693 DRM_DEBUG("\n");
694
695 switch (rdev->family) {
696 case CHIP_BARTS:
697 chip_name = "BARTS";
698 rlc_chip_name = "BTC";
699 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
700 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
701 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
702 mc_req_size = BTC_MC_UCODE_SIZE * 4;
703#ifdef __NetBSD__ /* XXX ALIGN means something else. */
704 smc_req_size = round_up(BARTS_SMC_UCODE_SIZE, 4);
705#else
706 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4);
707#endif
708 break;
709 case CHIP_TURKS:
710 chip_name = "TURKS";
711 rlc_chip_name = "BTC";
712 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
713 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
714 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
715 mc_req_size = BTC_MC_UCODE_SIZE * 4;
716#ifdef __NetBSD__ /* XXX ALIGN means something else. */
717 smc_req_size = round_up(TURKS_SMC_UCODE_SIZE, 4);
718#else
719 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4);
720#endif
721 break;
722 case CHIP_CAICOS:
723 chip_name = "CAICOS";
724 rlc_chip_name = "BTC";
725 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
726 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
727 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
728 mc_req_size = BTC_MC_UCODE_SIZE * 4;
729#ifdef __NetBSD__ /* XXX ALIGN means something else. */
730 smc_req_size = round_up(CAICOS_SMC_UCODE_SIZE, 4);
731#else
732 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4);
733#endif
734 break;
735 case CHIP_CAYMAN:
736 chip_name = "CAYMAN";
737 rlc_chip_name = "CAYMAN";
738 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
739 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
740 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
741 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
742#ifdef __NetBSD__ /* XXX ALIGN means something else. */
743 smc_req_size = round_up(CAYMAN_SMC_UCODE_SIZE, 4);
744#else
745 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4);
746#endif
747 break;
748 case CHIP_ARUBA:
749 chip_name = "ARUBA";
750 rlc_chip_name = "ARUBA";
751 /* pfp/me same size as CAYMAN */
752 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
753 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
754 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
755 mc_req_size = 0;
756 break;
757 default: BUG();
758 }
759
760 DRM_INFO("Loading %s Microcode\n", chip_name);
761
762 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
763 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
764 if (err)
765 goto out;
766 if (rdev->pfp_fw->size != pfp_req_size) {
767 printk(KERN_ERR
768 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
769 rdev->pfp_fw->size, fw_name);
770 err = -EINVAL;
771 goto out;
772 }
773
774 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
775 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
776 if (err)
777 goto out;
778 if (rdev->me_fw->size != me_req_size) {
779 printk(KERN_ERR
780 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
781 rdev->me_fw->size, fw_name);
782 err = -EINVAL;
783 }
784
785 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
786 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
787 if (err)
788 goto out;
789 if (rdev->rlc_fw->size != rlc_req_size) {
790 printk(KERN_ERR
791 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
792 rdev->rlc_fw->size, fw_name);
793 err = -EINVAL;
794 }
795
796 /* no MC ucode on TN */
797 if (!(rdev->flags & RADEON_IS_IGP)) {
798 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
799 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
800 if (err)
801 goto out;
802 if (rdev->mc_fw->size != mc_req_size) {
803 printk(KERN_ERR
804 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
805 rdev->mc_fw->size, fw_name);
806 err = -EINVAL;
807 }
808 }
809
810 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) {
811 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
812 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
813 if (err) {
814 printk(KERN_ERR
815 "smc: error loading firmware \"%s\"\n",
816 fw_name);
817 release_firmware(rdev->smc_fw);
818 rdev->smc_fw = NULL;
819 err = 0;
820 } else if (rdev->smc_fw->size != smc_req_size) {
821 printk(KERN_ERR
822 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
823 rdev->mc_fw->size, fw_name);
824 err = -EINVAL;
825 }
826 }
827
828out:
829 if (err) {
830 if (err != -EINVAL)
831 printk(KERN_ERR
832 "ni_cp: Failed to load firmware \"%s\"\n",
833 fw_name);
834 release_firmware(rdev->pfp_fw);
835 rdev->pfp_fw = NULL;
836 release_firmware(rdev->me_fw);
837 rdev->me_fw = NULL;
838 release_firmware(rdev->rlc_fw);
839 rdev->rlc_fw = NULL;
840 release_firmware(rdev->mc_fw);
841 rdev->mc_fw = NULL;
842 }
843 return err;
844}
845
846int tn_get_temp(struct radeon_device *rdev)
847{
848 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
849 int actual_temp = (temp / 8) - 49;
850
851 return actual_temp * 1000;
852}
853
854/*
855 * Core functions
856 */
857static void cayman_gpu_init(struct radeon_device *rdev)
858{
859 u32 gb_addr_config = 0;
860 u32 mc_shared_chmap __unused, mc_arb_ramcfg;
861 u32 cgts_tcc_disable;
862 u32 sx_debug_1;
863 u32 smx_dc_ctl0;
864 u32 cgts_sm_ctrl_reg;
865 u32 hdp_host_path_cntl;
866 u32 tmp;
867 u32 disabled_rb_mask;
868 int i, j;
869
870 switch (rdev->family) {
871 case CHIP_CAYMAN:
872 rdev->config.cayman.max_shader_engines = 2;
873 rdev->config.cayman.max_pipes_per_simd = 4;
874 rdev->config.cayman.max_tile_pipes = 8;
875 rdev->config.cayman.max_simds_per_se = 12;
876 rdev->config.cayman.max_backends_per_se = 4;
877 rdev->config.cayman.max_texture_channel_caches = 8;
878 rdev->config.cayman.max_gprs = 256;
879 rdev->config.cayman.max_threads = 256;
880 rdev->config.cayman.max_gs_threads = 32;
881 rdev->config.cayman.max_stack_entries = 512;
882 rdev->config.cayman.sx_num_of_sets = 8;
883 rdev->config.cayman.sx_max_export_size = 256;
884 rdev->config.cayman.sx_max_export_pos_size = 64;
885 rdev->config.cayman.sx_max_export_smx_size = 192;
886 rdev->config.cayman.max_hw_contexts = 8;
887 rdev->config.cayman.sq_num_cf_insts = 2;
888
889 rdev->config.cayman.sc_prim_fifo_size = 0x100;
890 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
891 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
892 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
893 break;
894 case CHIP_ARUBA:
895 default:
896 rdev->config.cayman.max_shader_engines = 1;
897 rdev->config.cayman.max_pipes_per_simd = 4;
898 rdev->config.cayman.max_tile_pipes = 2;
899 if ((rdev->pdev->device == 0x9900) ||
900 (rdev->pdev->device == 0x9901) ||
901 (rdev->pdev->device == 0x9905) ||
902 (rdev->pdev->device == 0x9906) ||
903 (rdev->pdev->device == 0x9907) ||
904 (rdev->pdev->device == 0x9908) ||
905 (rdev->pdev->device == 0x9909) ||
906 (rdev->pdev->device == 0x990B) ||
907 (rdev->pdev->device == 0x990C) ||
908 (rdev->pdev->device == 0x990F) ||
909 (rdev->pdev->device == 0x9910) ||
910 (rdev->pdev->device == 0x9917) ||
911 (rdev->pdev->device == 0x9999) ||
912 (rdev->pdev->device == 0x999C)) {
913 rdev->config.cayman.max_simds_per_se = 6;
914 rdev->config.cayman.max_backends_per_se = 2;
915 rdev->config.cayman.max_hw_contexts = 8;
916 rdev->config.cayman.sx_max_export_size = 256;
917 rdev->config.cayman.sx_max_export_pos_size = 64;
918 rdev->config.cayman.sx_max_export_smx_size = 192;
919 } else if ((rdev->pdev->device == 0x9903) ||
920 (rdev->pdev->device == 0x9904) ||
921 (rdev->pdev->device == 0x990A) ||
922 (rdev->pdev->device == 0x990D) ||
923 (rdev->pdev->device == 0x990E) ||
924 (rdev->pdev->device == 0x9913) ||
925 (rdev->pdev->device == 0x9918) ||
926 (rdev->pdev->device == 0x999D)) {
927 rdev->config.cayman.max_simds_per_se = 4;
928 rdev->config.cayman.max_backends_per_se = 2;
929 rdev->config.cayman.max_hw_contexts = 8;
930 rdev->config.cayman.sx_max_export_size = 256;
931 rdev->config.cayman.sx_max_export_pos_size = 64;
932 rdev->config.cayman.sx_max_export_smx_size = 192;
933 } else if ((rdev->pdev->device == 0x9919) ||
934 (rdev->pdev->device == 0x9990) ||
935 (rdev->pdev->device == 0x9991) ||
936 (rdev->pdev->device == 0x9994) ||
937 (rdev->pdev->device == 0x9995) ||
938 (rdev->pdev->device == 0x9996) ||
939 (rdev->pdev->device == 0x999A) ||
940 (rdev->pdev->device == 0x99A0)) {
941 rdev->config.cayman.max_simds_per_se = 3;
942 rdev->config.cayman.max_backends_per_se = 1;
943 rdev->config.cayman.max_hw_contexts = 4;
944 rdev->config.cayman.sx_max_export_size = 128;
945 rdev->config.cayman.sx_max_export_pos_size = 32;
946 rdev->config.cayman.sx_max_export_smx_size = 96;
947 } else {
948 rdev->config.cayman.max_simds_per_se = 2;
949 rdev->config.cayman.max_backends_per_se = 1;
950 rdev->config.cayman.max_hw_contexts = 4;
951 rdev->config.cayman.sx_max_export_size = 128;
952 rdev->config.cayman.sx_max_export_pos_size = 32;
953 rdev->config.cayman.sx_max_export_smx_size = 96;
954 }
955 rdev->config.cayman.max_texture_channel_caches = 2;
956 rdev->config.cayman.max_gprs = 256;
957 rdev->config.cayman.max_threads = 256;
958 rdev->config.cayman.max_gs_threads = 32;
959 rdev->config.cayman.max_stack_entries = 512;
960 rdev->config.cayman.sx_num_of_sets = 8;
961 rdev->config.cayman.sq_num_cf_insts = 2;
962
963 rdev->config.cayman.sc_prim_fifo_size = 0x40;
964 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
965 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
966 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
967 break;
968 }
969
970 /* Initialize HDP */
971 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
972 WREG32((0x2c14 + j), 0x00000000);
973 WREG32((0x2c18 + j), 0x00000000);
974 WREG32((0x2c1c + j), 0x00000000);
975 WREG32((0x2c20 + j), 0x00000000);
976 WREG32((0x2c24 + j), 0x00000000);
977 }
978
979 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
980
981 evergreen_fix_pci_max_read_req_size(rdev);
982
983 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
984 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
985
986 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
987 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
988 if (rdev->config.cayman.mem_row_size_in_kb > 4)
989 rdev->config.cayman.mem_row_size_in_kb = 4;
990 /* XXX use MC settings? */
991 rdev->config.cayman.shader_engine_tile_size = 32;
992 rdev->config.cayman.num_gpus = 1;
993 rdev->config.cayman.multi_gpu_tile_size = 64;
994
995 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
996 rdev->config.cayman.num_tile_pipes = (1 << tmp);
997 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
998 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
999 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
1000 rdev->config.cayman.num_shader_engines = tmp + 1;
1001 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
1002 rdev->config.cayman.num_gpus = tmp + 1;
1003 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
1004 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
1005 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
1006 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
1007
1008
1009 /* setup tiling info dword. gb_addr_config is not adequate since it does
1010 * not have bank info, so create a custom tiling dword.
1011 * bits 3:0 num_pipes
1012 * bits 7:4 num_banks
1013 * bits 11:8 group_size
1014 * bits 15:12 row_size
1015 */
1016 rdev->config.cayman.tile_config = 0;
1017 switch (rdev->config.cayman.num_tile_pipes) {
1018 case 1:
1019 default:
1020 rdev->config.cayman.tile_config |= (0 << 0);
1021 break;
1022 case 2:
1023 rdev->config.cayman.tile_config |= (1 << 0);
1024 break;
1025 case 4:
1026 rdev->config.cayman.tile_config |= (2 << 0);
1027 break;
1028 case 8:
1029 rdev->config.cayman.tile_config |= (3 << 0);
1030 break;
1031 }
1032
1033 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1034 if (rdev->flags & RADEON_IS_IGP)
1035 rdev->config.cayman.tile_config |= 1 << 4;
1036 else {
1037 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1038 case 0: /* four banks */
1039 rdev->config.cayman.tile_config |= 0 << 4;
1040 break;
1041 case 1: /* eight banks */
1042 rdev->config.cayman.tile_config |= 1 << 4;
1043 break;
1044 case 2: /* sixteen banks */
1045 default:
1046 rdev->config.cayman.tile_config |= 2 << 4;
1047 break;
1048 }
1049 }
1050 rdev->config.cayman.tile_config |=
1051 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1052 rdev->config.cayman.tile_config |=
1053 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1054
1055 tmp = 0;
1056 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
1057 u32 rb_disable_bitmap;
1058
1059 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1060 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1061 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1062 tmp <<= 4;
1063 tmp |= rb_disable_bitmap;
1064 }
1065 /* enabled rb are just the one not disabled :) */
1066 disabled_rb_mask = tmp;
1067 tmp = 0;
1068 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1069 tmp |= (1 << i);
1070 /* if all the backends are disabled, fix it up here */
1071 if ((disabled_rb_mask & tmp) == tmp) {
1072 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1073 disabled_rb_mask &= ~(1 << i);
1074 }
1075
1076 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1077 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1078
1079 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1080 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1081 if (ASIC_IS_DCE6(rdev))
1082 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1083 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1084 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1085 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1086 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1087 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1088 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1089
1090 if ((rdev->config.cayman.max_backends_per_se == 1) &&
1091 (rdev->flags & RADEON_IS_IGP)) {
1092 if ((disabled_rb_mask & 3) == 1) {
1093 /* RB0 disabled, RB1 enabled */
1094 tmp = 0x11111111;
1095 } else {
1096 /* RB1 disabled, RB0 enabled */
1097 tmp = 0x00000000;
1098 }
1099 } else {
1100 tmp = gb_addr_config & NUM_PIPES_MASK;
1101 tmp = r6xx_remap_render_backend(rdev, tmp,
1102 rdev->config.cayman.max_backends_per_se *
1103 rdev->config.cayman.max_shader_engines,
1104 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
1105 }
1106 WREG32(GB_BACKEND_MAP, tmp);
1107
1108 cgts_tcc_disable = 0xffff0000;
1109 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
1110 cgts_tcc_disable &= ~(1 << (16 + i));
1111 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1112 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
1113 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
1114 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1115
1116 /* reprogram the shader complex */
1117 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
1118 for (i = 0; i < 16; i++)
1119 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
1120 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
1121
1122 /* set HW defaults for 3D engine */
1123 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1124
1125 sx_debug_1 = RREG32(SX_DEBUG_1);
1126 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1127 WREG32(SX_DEBUG_1, sx_debug_1);
1128
1129 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1130 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1131 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
1132 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1133
1134 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
1135
1136 /* need to be explicitly zero-ed */
1137 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
1138 WREG32(SQ_LSTMP_RING_BASE, 0);
1139 WREG32(SQ_HSTMP_RING_BASE, 0);
1140 WREG32(SQ_ESTMP_RING_BASE, 0);
1141 WREG32(SQ_GSTMP_RING_BASE, 0);
1142 WREG32(SQ_VSTMP_RING_BASE, 0);
1143 WREG32(SQ_PSTMP_RING_BASE, 0);
1144
1145 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
1146
1147 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
1148 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
1149 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
1150
1151 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
1152 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
1153 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
1154
1155
1156 WREG32(VGT_NUM_INSTANCES, 1);
1157
1158 WREG32(CP_PERFMON_CNTL, 0);
1159
1160 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
1161 FETCH_FIFO_HIWATER(0x4) |
1162 DONE_FIFO_HIWATER(0xe0) |
1163 ALU_UPDATE_FIFO_HIWATER(0x8)));
1164
1165 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
1166 WREG32(SQ_CONFIG, (VC_ENABLE |
1167 EXPORT_SRC_C |
1168 GFX_PRIO(0) |
1169 CS1_PRIO(0) |
1170 CS2_PRIO(1)));
1171 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
1172
1173 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1174 FORCE_EOV_MAX_REZ_CNT(255)));
1175
1176 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1177 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1178
1179 WREG32(VGT_GS_VERTEX_REUSE, 16);
1180 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1181
1182 WREG32(CB_PERF_CTR0_SEL_0, 0);
1183 WREG32(CB_PERF_CTR0_SEL_1, 0);
1184 WREG32(CB_PERF_CTR1_SEL_0, 0);
1185 WREG32(CB_PERF_CTR1_SEL_1, 0);
1186 WREG32(CB_PERF_CTR2_SEL_0, 0);
1187 WREG32(CB_PERF_CTR2_SEL_1, 0);
1188 WREG32(CB_PERF_CTR3_SEL_0, 0);
1189 WREG32(CB_PERF_CTR3_SEL_1, 0);
1190
1191 tmp = RREG32(HDP_MISC_CNTL);
1192 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1193 WREG32(HDP_MISC_CNTL, tmp);
1194
1195 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1196 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1197
1198 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1199
1200 udelay(50);
1201
1202 /* set clockgating golden values on TN */
1203 if (rdev->family == CHIP_ARUBA) {
1204 tmp = RREG32_CG(CG_CGTT_LOCAL_0);
1205 tmp &= ~0x00380000;
1206 WREG32_CG(CG_CGTT_LOCAL_0, tmp);
1207 tmp = RREG32_CG(CG_CGTT_LOCAL_1);
1208 tmp &= ~0x0e000000;
1209 WREG32_CG(CG_CGTT_LOCAL_1, tmp);
1210 }
1211}
1212
1213/*
1214 * GART
1215 */
1216void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1217{
1218 /* flush hdp cache */
1219 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1220
1221 /* bits 0-7 are the VM contexts0-7 */
1222 WREG32(VM_INVALIDATE_REQUEST, 1);
1223}
1224
1225static int cayman_pcie_gart_enable(struct radeon_device *rdev)
1226{
1227 int i, r;
1228
1229 if (rdev->gart.robj == NULL) {
1230 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1231 return -EINVAL;
1232 }
1233 r = radeon_gart_table_vram_pin(rdev);
1234 if (r)
1235 return r;
1236 radeon_gart_restore(rdev);
1237 /* Setup TLB control */
1238 WREG32(MC_VM_MX_L1_TLB_CNTL,
1239 (0xA << 7) |
1240 ENABLE_L1_TLB |
1241 ENABLE_L1_FRAGMENT_PROCESSING |
1242 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1243 ENABLE_ADVANCED_DRIVER_MODEL |
1244 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1245 /* Setup L2 cache */
1246 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1247 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1248 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1249 EFFECTIVE_L2_QUEUE_SIZE(7) |
1250 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1251 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1252 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1253 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1254 /* setup context0 */
1255 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1256 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1257 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1258 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1259 (u32)(rdev->dummy_page.addr >> 12));
1260 WREG32(VM_CONTEXT0_CNTL2, 0);
1261 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1262 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1263
1264 WREG32(0x15D4, 0);
1265 WREG32(0x15D8, 0);
1266 WREG32(0x15DC, 0);
1267
1268 /* empty context1-7 */
1269 /* Assign the pt base to something valid for now; the pts used for
1270 * the VMs are determined by the application and setup and assigned
1271 * on the fly in the vm part of radeon_gart.c
1272 */
1273 for (i = 1; i < 8; i++) {
1274 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1275 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
1276 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1277 rdev->gart.table_addr >> 12);
1278 }
1279
1280 /* enable context1-7 */
1281 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1282 (u32)(rdev->dummy_page.addr >> 12));
1283 WREG32(VM_CONTEXT1_CNTL2, 4);
1284 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
1285 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1286 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1287 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1288 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1289 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
1290 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
1291 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
1292 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
1293 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
1294 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
1295 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1296 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
1297
1298 cayman_pcie_gart_tlb_flush(rdev);
1299 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1300 (unsigned)(rdev->mc.gtt_size >> 20),
1301 (unsigned long long)rdev->gart.table_addr);
1302 rdev->gart.ready = true;
1303 return 0;
1304}
1305
1306static void cayman_pcie_gart_disable(struct radeon_device *rdev)
1307{
1308 /* Disable all tables */
1309 WREG32(VM_CONTEXT0_CNTL, 0);
1310 WREG32(VM_CONTEXT1_CNTL, 0);
1311 /* Setup TLB control */
1312 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1313 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1314 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1315 /* Setup L2 cache */
1316 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1317 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1318 EFFECTIVE_L2_QUEUE_SIZE(7) |
1319 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1320 WREG32(VM_L2_CNTL2, 0);
1321 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1322 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1323 radeon_gart_table_vram_unpin(rdev);
1324}
1325
1326static void cayman_pcie_gart_fini(struct radeon_device *rdev)
1327{
1328 cayman_pcie_gart_disable(rdev);
1329 radeon_gart_table_vram_free(rdev);
1330 radeon_gart_fini(rdev);
1331}
1332
1333void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1334 int ring, u32 cp_int_cntl)
1335{
1336 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
1337
1338 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
1339 WREG32(CP_INT_CNTL, cp_int_cntl);
1340}
1341
1342/*
1343 * CP.
1344 */
1345void cayman_fence_ring_emit(struct radeon_device *rdev,
1346 struct radeon_fence *fence)
1347{
1348 struct radeon_ring *ring = &rdev->ring[fence->ring];
1349 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1350 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1351 PACKET3_SH_ACTION_ENA;
1352
1353 /* flush read cache over gart for this vmid */
1354 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1355 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1356 radeon_ring_write(ring, 0xFFFFFFFF);
1357 radeon_ring_write(ring, 0);
1358 radeon_ring_write(ring, 10); /* poll interval */
1359 /* EVENT_WRITE_EOP - flush caches, send int */
1360 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1361 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1362 radeon_ring_write(ring, addr & 0xffffffff);
1363 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1364 radeon_ring_write(ring, fence->seq);
1365 radeon_ring_write(ring, 0);
1366}
1367
1368void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1369{
1370 struct radeon_ring *ring = &rdev->ring[ib->ring];
1371 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1372 PACKET3_SH_ACTION_ENA;
1373
1374 /* set to DX10/11 mode */
1375 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1376 radeon_ring_write(ring, 1);
1377
1378 if (ring->rptr_save_reg) {
1379 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1380 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1381 radeon_ring_write(ring, ((ring->rptr_save_reg -
1382 PACKET3_SET_CONFIG_REG_START) >> 2));
1383 radeon_ring_write(ring, next_rptr);
1384 }
1385
1386 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1387 radeon_ring_write(ring,
1388#ifdef __BIG_ENDIAN
1389 (2 << 0) |
1390#endif
1391 (ib->gpu_addr & 0xFFFFFFFC));
1392 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1393 radeon_ring_write(ring, ib->length_dw |
1394 (ib->vm ? (ib->vm->id << 24) : 0));
1395
1396 /* flush read cache over gart for this vmid */
1397 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1398 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1399 radeon_ring_write(ring, 0xFFFFFFFF);
1400 radeon_ring_write(ring, 0);
1401 radeon_ring_write(ring, ((ib->vm ? ib->vm->id : 0) << 24) | 10); /* poll interval */
1402}
1403
1404static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1405{
1406 if (enable)
1407 WREG32(CP_ME_CNTL, 0);
1408 else {
1409 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1410 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1411 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1412 WREG32(SCRATCH_UMSK, 0);
1413 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1414 }
1415}
1416
1417u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
1418 struct radeon_ring *ring)
1419{
1420 u32 rptr;
1421
1422 if (rdev->wb.enabled)
1423 rptr = rdev->wb.wb[ring->rptr_offs/4];
1424 else {
1425 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1426 rptr = RREG32(CP_RB0_RPTR);
1427 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1428 rptr = RREG32(CP_RB1_RPTR);
1429 else
1430 rptr = RREG32(CP_RB2_RPTR);
1431 }
1432
1433 return rptr;
1434}
1435
1436u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
1437 struct radeon_ring *ring)
1438{
1439 u32 wptr;
1440
1441 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1442 wptr = RREG32(CP_RB0_WPTR);
1443 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1444 wptr = RREG32(CP_RB1_WPTR);
1445 else
1446 wptr = RREG32(CP_RB2_WPTR);
1447
1448 return wptr;
1449}
1450
1451void cayman_gfx_set_wptr(struct radeon_device *rdev,
1452 struct radeon_ring *ring)
1453{
1454 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
1455 WREG32(CP_RB0_WPTR, ring->wptr);
1456 (void)RREG32(CP_RB0_WPTR);
1457 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) {
1458 WREG32(CP_RB1_WPTR, ring->wptr);
1459 (void)RREG32(CP_RB1_WPTR);
1460 } else {
1461 WREG32(CP_RB2_WPTR, ring->wptr);
1462 (void)RREG32(CP_RB2_WPTR);
1463 }
1464}
1465
1466static int cayman_cp_load_microcode(struct radeon_device *rdev)
1467{
1468 const __be32 *fw_data;
1469 int i;
1470
1471 if (!rdev->me_fw || !rdev->pfp_fw)
1472 return -EINVAL;
1473
1474 cayman_cp_enable(rdev, false);
1475
1476 fw_data = (const __be32 *)rdev->pfp_fw->data;
1477 WREG32(CP_PFP_UCODE_ADDR, 0);
1478 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1479 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1480 WREG32(CP_PFP_UCODE_ADDR, 0);
1481
1482 fw_data = (const __be32 *)rdev->me_fw->data;
1483 WREG32(CP_ME_RAM_WADDR, 0);
1484 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1485 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1486
1487 WREG32(CP_PFP_UCODE_ADDR, 0);
1488 WREG32(CP_ME_RAM_WADDR, 0);
1489 WREG32(CP_ME_RAM_RADDR, 0);
1490 return 0;
1491}
1492
1493static int cayman_cp_start(struct radeon_device *rdev)
1494{
1495 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1496 int r, i;
1497
1498 r = radeon_ring_lock(rdev, ring, 7);
1499 if (r) {
1500 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1501 return r;
1502 }
1503 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1504 radeon_ring_write(ring, 0x1);
1505 radeon_ring_write(ring, 0x0);
1506 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1507 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1508 radeon_ring_write(ring, 0);
1509 radeon_ring_write(ring, 0);
1510 radeon_ring_unlock_commit(rdev, ring);
1511
1512 cayman_cp_enable(rdev, true);
1513
1514 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1515 if (r) {
1516 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1517 return r;
1518 }
1519
1520 /* setup clear context state */
1521 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1522 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1523
1524 for (i = 0; i < cayman_default_size; i++)
1525 radeon_ring_write(ring, cayman_default_state[i]);
1526
1527 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1528 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1529
1530 /* set clear context state */
1531 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1532 radeon_ring_write(ring, 0);
1533
1534 /* SQ_VTX_BASE_VTX_LOC */
1535 radeon_ring_write(ring, 0xc0026f00);
1536 radeon_ring_write(ring, 0x00000000);
1537 radeon_ring_write(ring, 0x00000000);
1538 radeon_ring_write(ring, 0x00000000);
1539
1540 /* Clear consts */
1541 radeon_ring_write(ring, 0xc0036f00);
1542 radeon_ring_write(ring, 0x00000bc4);
1543 radeon_ring_write(ring, 0xffffffff);
1544 radeon_ring_write(ring, 0xffffffff);
1545 radeon_ring_write(ring, 0xffffffff);
1546
1547 radeon_ring_write(ring, 0xc0026900);
1548 radeon_ring_write(ring, 0x00000316);
1549 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1550 radeon_ring_write(ring, 0x00000010); /* */
1551
1552 radeon_ring_unlock_commit(rdev, ring);
1553
1554 /* XXX init other rings */
1555
1556 return 0;
1557}
1558
1559static void cayman_cp_fini(struct radeon_device *rdev)
1560{
1561 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1562 cayman_cp_enable(rdev, false);
1563 radeon_ring_fini(rdev, ring);
1564 radeon_scratch_free(rdev, ring->rptr_save_reg);
1565}
1566
1567static int cayman_cp_resume(struct radeon_device *rdev)
1568{
1569 static const int ridx[] = {
1570 RADEON_RING_TYPE_GFX_INDEX,
1571 CAYMAN_RING_TYPE_CP1_INDEX,
1572 CAYMAN_RING_TYPE_CP2_INDEX
1573 };
1574 static const unsigned cp_rb_cntl[] = {
1575 CP_RB0_CNTL,
1576 CP_RB1_CNTL,
1577 CP_RB2_CNTL,
1578 };
1579 static const unsigned cp_rb_rptr_addr[] = {
1580 CP_RB0_RPTR_ADDR,
1581 CP_RB1_RPTR_ADDR,
1582 CP_RB2_RPTR_ADDR
1583 };
1584 static const unsigned cp_rb_rptr_addr_hi[] = {
1585 CP_RB0_RPTR_ADDR_HI,
1586 CP_RB1_RPTR_ADDR_HI,
1587 CP_RB2_RPTR_ADDR_HI
1588 };
1589 static const unsigned cp_rb_base[] = {
1590 CP_RB0_BASE,
1591 CP_RB1_BASE,
1592 CP_RB2_BASE
1593 };
1594 static const unsigned cp_rb_rptr[] = {
1595 CP_RB0_RPTR,
1596 CP_RB1_RPTR,
1597 CP_RB2_RPTR
1598 };
1599 static const unsigned cp_rb_wptr[] = {
1600 CP_RB0_WPTR,
1601 CP_RB1_WPTR,
1602 CP_RB2_WPTR
1603 };
1604 struct radeon_ring *ring;
1605 int i, r;
1606
1607 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1608 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1609 SOFT_RESET_PA |
1610 SOFT_RESET_SH |
1611 SOFT_RESET_VGT |
1612 SOFT_RESET_SPI |
1613 SOFT_RESET_SX));
1614 RREG32(GRBM_SOFT_RESET);
1615 mdelay(15);
1616 WREG32(GRBM_SOFT_RESET, 0);
1617 RREG32(GRBM_SOFT_RESET);
1618
1619 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1620 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1621
1622 /* Set the write pointer delay */
1623 WREG32(CP_RB_WPTR_DELAY, 0);
1624
1625 WREG32(CP_DEBUG, (1 << 27));
1626
1627 /* set the wb address whether it's enabled or not */
1628 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1629 WREG32(SCRATCH_UMSK, 0xff);
1630
1631 for (i = 0; i < 3; ++i) {
1632 uint32_t rb_cntl;
1633 uint64_t addr;
1634
1635 /* Set ring buffer size */
1636 ring = &rdev->ring[ridx[i]];
1637 rb_cntl = order_base_2(ring->ring_size / 8);
1638 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
1639#ifdef __BIG_ENDIAN
1640 rb_cntl |= BUF_SWAP_32BIT;
1641#endif
1642 WREG32(cp_rb_cntl[i], rb_cntl);
1643
1644 /* set the wb address whether it's enabled or not */
1645 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1646 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1647 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1648 }
1649
1650 /* set the rb base addr, this causes an internal reset of ALL rings */
1651 for (i = 0; i < 3; ++i) {
1652 ring = &rdev->ring[ridx[i]];
1653 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1654 }
1655
1656 for (i = 0; i < 3; ++i) {
1657 /* Initialize the ring buffer's read and write pointers */
1658 ring = &rdev->ring[ridx[i]];
1659 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1660
1661 ring->wptr = 0;
1662 WREG32(cp_rb_rptr[i], 0);
1663 WREG32(cp_rb_wptr[i], ring->wptr);
1664
1665 mdelay(1);
1666 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1667 }
1668
1669 /* start the rings */
1670 cayman_cp_start(rdev);
1671 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1672 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1673 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1674 /* this only test cp0 */
1675 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1676 if (r) {
1677 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1678 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1679 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1680 return r;
1681 }
1682
1683 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1684 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1685
1686 return 0;
1687}
1688
1689u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
1690{
1691 u32 reset_mask = 0;
1692 u32 tmp;
1693
1694 /* GRBM_STATUS */
1695 tmp = RREG32(GRBM_STATUS);
1696 if (tmp & (PA_BUSY | SC_BUSY |
1697 SH_BUSY | SX_BUSY |
1698 TA_BUSY | VGT_BUSY |
1699 DB_BUSY | CB_BUSY |
1700 GDS_BUSY | SPI_BUSY |
1701 IA_BUSY | IA_BUSY_NO_DMA))
1702 reset_mask |= RADEON_RESET_GFX;
1703
1704 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1705 CP_BUSY | CP_COHERENCY_BUSY))
1706 reset_mask |= RADEON_RESET_CP;
1707
1708 if (tmp & GRBM_EE_BUSY)
1709 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1710
1711 /* DMA_STATUS_REG 0 */
1712 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1713 if (!(tmp & DMA_IDLE))
1714 reset_mask |= RADEON_RESET_DMA;
1715
1716 /* DMA_STATUS_REG 1 */
1717 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1718 if (!(tmp & DMA_IDLE))
1719 reset_mask |= RADEON_RESET_DMA1;
1720
1721 /* SRBM_STATUS2 */
1722 tmp = RREG32(SRBM_STATUS2);
1723 if (tmp & DMA_BUSY)
1724 reset_mask |= RADEON_RESET_DMA;
1725
1726 if (tmp & DMA1_BUSY)
1727 reset_mask |= RADEON_RESET_DMA1;
1728
1729 /* SRBM_STATUS */
1730 tmp = RREG32(SRBM_STATUS);
1731 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1732 reset_mask |= RADEON_RESET_RLC;
1733
1734 if (tmp & IH_BUSY)
1735 reset_mask |= RADEON_RESET_IH;
1736
1737 if (tmp & SEM_BUSY)
1738 reset_mask |= RADEON_RESET_SEM;
1739
1740 if (tmp & GRBM_RQ_PENDING)
1741 reset_mask |= RADEON_RESET_GRBM;
1742
1743 if (tmp & VMC_BUSY)
1744 reset_mask |= RADEON_RESET_VMC;
1745
1746 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1747 MCC_BUSY | MCD_BUSY))
1748 reset_mask |= RADEON_RESET_MC;
1749
1750 if (evergreen_is_display_hung(rdev))
1751 reset_mask |= RADEON_RESET_DISPLAY;
1752
1753 /* VM_L2_STATUS */
1754 tmp = RREG32(VM_L2_STATUS);
1755 if (tmp & L2_BUSY)
1756 reset_mask |= RADEON_RESET_VMC;
1757
1758 /* Skip MC reset as it's mostly likely not hung, just busy */
1759 if (reset_mask & RADEON_RESET_MC) {
1760 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1761 reset_mask &= ~RADEON_RESET_MC;
1762 }
1763
1764 return reset_mask;
1765}
1766
1767static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1768{
1769 struct evergreen_mc_save save;
1770 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1771 u32 tmp;
1772
1773 if (reset_mask == 0)
1774 return;
1775
1776 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1777
1778 evergreen_print_gpu_status_regs(rdev);
1779 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1780 RREG32(0x14F8));
1781 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1782 RREG32(0x14D8));
1783 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1784 RREG32(0x14FC));
1785 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1786 RREG32(0x14DC));
1787
1788 /* Disable CP parsing/prefetching */
1789 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1790
1791 if (reset_mask & RADEON_RESET_DMA) {
1792 /* dma0 */
1793 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1794 tmp &= ~DMA_RB_ENABLE;
1795 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1796 }
1797
1798 if (reset_mask & RADEON_RESET_DMA1) {
1799 /* dma1 */
1800 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1801 tmp &= ~DMA_RB_ENABLE;
1802 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1803 }
1804
1805 udelay(50);
1806
1807 evergreen_mc_stop(rdev, &save);
1808 if (evergreen_mc_wait_for_idle(rdev)) {
1809 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1810 }
1811
1812 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1813 grbm_soft_reset = SOFT_RESET_CB |
1814 SOFT_RESET_DB |
1815 SOFT_RESET_GDS |
1816 SOFT_RESET_PA |
1817 SOFT_RESET_SC |
1818 SOFT_RESET_SPI |
1819 SOFT_RESET_SH |
1820 SOFT_RESET_SX |
1821 SOFT_RESET_TC |
1822 SOFT_RESET_TA |
1823 SOFT_RESET_VGT |
1824 SOFT_RESET_IA;
1825 }
1826
1827 if (reset_mask & RADEON_RESET_CP) {
1828 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1829
1830 srbm_soft_reset |= SOFT_RESET_GRBM;
1831 }
1832
1833 if (reset_mask & RADEON_RESET_DMA)
1834 srbm_soft_reset |= SOFT_RESET_DMA;
1835
1836 if (reset_mask & RADEON_RESET_DMA1)
1837 srbm_soft_reset |= SOFT_RESET_DMA1;
1838
1839 if (reset_mask & RADEON_RESET_DISPLAY)
1840 srbm_soft_reset |= SOFT_RESET_DC;
1841
1842 if (reset_mask & RADEON_RESET_RLC)
1843 srbm_soft_reset |= SOFT_RESET_RLC;
1844
1845 if (reset_mask & RADEON_RESET_SEM)
1846 srbm_soft_reset |= SOFT_RESET_SEM;
1847
1848 if (reset_mask & RADEON_RESET_IH)
1849 srbm_soft_reset |= SOFT_RESET_IH;
1850
1851 if (reset_mask & RADEON_RESET_GRBM)
1852 srbm_soft_reset |= SOFT_RESET_GRBM;
1853
1854 if (reset_mask & RADEON_RESET_VMC)
1855 srbm_soft_reset |= SOFT_RESET_VMC;
1856
1857 if (!(rdev->flags & RADEON_IS_IGP)) {
1858 if (reset_mask & RADEON_RESET_MC)
1859 srbm_soft_reset |= SOFT_RESET_MC;
1860 }
1861
1862 if (grbm_soft_reset) {
1863 tmp = RREG32(GRBM_SOFT_RESET);
1864 tmp |= grbm_soft_reset;
1865 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1866 WREG32(GRBM_SOFT_RESET, tmp);
1867 tmp = RREG32(GRBM_SOFT_RESET);
1868
1869 udelay(50);
1870
1871 tmp &= ~grbm_soft_reset;
1872 WREG32(GRBM_SOFT_RESET, tmp);
1873 tmp = RREG32(GRBM_SOFT_RESET);
1874 }
1875
1876 if (srbm_soft_reset) {
1877 tmp = RREG32(SRBM_SOFT_RESET);
1878 tmp |= srbm_soft_reset;
1879 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1880 WREG32(SRBM_SOFT_RESET, tmp);
1881 tmp = RREG32(SRBM_SOFT_RESET);
1882
1883 udelay(50);
1884
1885 tmp &= ~srbm_soft_reset;
1886 WREG32(SRBM_SOFT_RESET, tmp);
1887 tmp = RREG32(SRBM_SOFT_RESET);
1888 }
1889
1890 /* Wait a little for things to settle down */
1891 udelay(50);
1892
1893 evergreen_mc_resume(rdev, &save);
1894 udelay(50);
1895
1896 evergreen_print_gpu_status_regs(rdev);
1897}
1898
1899int cayman_asic_reset(struct radeon_device *rdev)
1900{
1901 u32 reset_mask;
1902
1903 reset_mask = cayman_gpu_check_soft_reset(rdev);
1904
1905 if (reset_mask)
1906 r600_set_bios_scratch_engine_hung(rdev, true);
1907
1908 cayman_gpu_soft_reset(rdev, reset_mask);
1909
1910 reset_mask = cayman_gpu_check_soft_reset(rdev);
1911
1912 if (reset_mask)
1913 evergreen_gpu_pci_config_reset(rdev);
1914
1915 r600_set_bios_scratch_engine_hung(rdev, false);
1916
1917 return 0;
1918}
1919
1920/**
1921 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1922 *
1923 * @rdev: radeon_device pointer
1924 * @ring: radeon_ring structure holding ring information
1925 *
1926 * Check if the GFX engine is locked up.
1927 * Returns true if the engine appears to be locked up, false if not.
1928 */
1929bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1930{
1931 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1932
1933 if (!(reset_mask & (RADEON_RESET_GFX |
1934 RADEON_RESET_COMPUTE |
1935 RADEON_RESET_CP))) {
1936 radeon_ring_lockup_update(rdev, ring);
1937 return false;
1938 }
1939 return radeon_ring_test_lockup(rdev, ring);
1940}
1941
1942static int cayman_startup(struct radeon_device *rdev)
1943{
1944 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1945 int r;
1946
1947 /* enable pcie gen2 link */
1948 evergreen_pcie_gen2_enable(rdev);
1949 /* enable aspm */
1950 evergreen_program_aspm(rdev);
1951
1952 /* scratch needs to be initialized before MC */
1953 r = r600_vram_scratch_init(rdev);
1954 if (r)
1955 return r;
1956
1957 evergreen_mc_program(rdev);
1958
1959 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
1960 r = ni_mc_load_microcode(rdev);
1961 if (r) {
1962 DRM_ERROR("Failed to load MC firmware!\n");
1963 return r;
1964 }
1965 }
1966
1967 r = cayman_pcie_gart_enable(rdev);
1968 if (r)
1969 return r;
1970 cayman_gpu_init(rdev);
1971
1972 /* allocate rlc buffers */
1973 if (rdev->flags & RADEON_IS_IGP) {
1974 rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
1975 rdev->rlc.reg_list_size =
1976 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);
1977 rdev->rlc.cs_data = cayman_cs_data;
1978 r = sumo_rlc_init(rdev);
1979 if (r) {
1980 DRM_ERROR("Failed to init rlc BOs!\n");
1981 return r;
1982 }
1983 }
1984
1985 /* allocate wb buffer */
1986 r = radeon_wb_init(rdev);
1987 if (r)
1988 return r;
1989
1990 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1991 if (r) {
1992 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1993 return r;
1994 }
1995
1996 r = uvd_v2_2_resume(rdev);
1997 if (!r) {
1998 r = radeon_fence_driver_start_ring(rdev,
1999 R600_RING_TYPE_UVD_INDEX);
2000 if (r)
2001 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
2002 }
2003 if (r)
2004 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
2005
2006 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
2007 if (r) {
2008 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2009 return r;
2010 }
2011
2012 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
2013 if (r) {
2014 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2015 return r;
2016 }
2017
2018 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2019 if (r) {
2020 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2021 return r;
2022 }
2023
2024 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
2025 if (r) {
2026 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2027 return r;
2028 }
2029
2030 /* Enable IRQ */
2031 if (!rdev->irq.installed) {
2032 r = radeon_irq_kms_init(rdev);
2033 if (r)
2034 return r;
2035 }
2036
2037 r = r600_irq_init(rdev);
2038 if (r) {
2039 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2040 radeon_irq_kms_fini(rdev);
2041 return r;
2042 }
2043 evergreen_irq_set(rdev);
2044
2045 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2046 RADEON_CP_PACKET2);
2047 if (r)
2048 return r;
2049
2050 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2051 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2052 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2053 if (r)
2054 return r;
2055
2056 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2057 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
2058 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2059 if (r)
2060 return r;
2061
2062 r = cayman_cp_load_microcode(rdev);
2063 if (r)
2064 return r;
2065 r = cayman_cp_resume(rdev);
2066 if (r)
2067 return r;
2068
2069 r = cayman_dma_resume(rdev);
2070 if (r)
2071 return r;
2072
2073 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2074 if (ring->ring_size) {
2075 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
2076 RADEON_CP_PACKET2);
2077 if (!r)
2078 r = uvd_v1_0_init(rdev);
2079 if (r)
2080 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
2081 }
2082
2083 r = radeon_ib_pool_init(rdev);
2084 if (r) {
2085 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2086 return r;
2087 }
2088
2089 r = radeon_vm_manager_init(rdev);
2090 if (r) {
2091 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
2092 return r;
2093 }
2094
2095 if (ASIC_IS_DCE6(rdev)) {
2096 r = dce6_audio_init(rdev);
2097 if (r)
2098 return r;
2099 } else {
2100 r = r600_audio_init(rdev);
2101 if (r)
2102 return r;
2103 }
2104
2105 return 0;
2106}
2107
2108int cayman_resume(struct radeon_device *rdev)
2109{
2110 int r;
2111
2112 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2113 * posting will perform necessary task to bring back GPU into good
2114 * shape.
2115 */
2116 /* post card */
2117 atom_asic_init(rdev->mode_info.atom_context);
2118
2119 /* init golden registers */
2120 ni_init_golden_registers(rdev);
2121
2122 if (rdev->pm.pm_method == PM_METHOD_DPM)
2123 radeon_pm_resume(rdev);
2124
2125 rdev->accel_working = true;
2126 r = cayman_startup(rdev);
2127 if (r) {
2128 DRM_ERROR("cayman startup failed on resume\n");
2129 rdev->accel_working = false;
2130 return r;
2131 }
2132 return r;
2133}
2134
2135int cayman_suspend(struct radeon_device *rdev)
2136{
2137 radeon_pm_suspend(rdev);
2138 if (ASIC_IS_DCE6(rdev))
2139 dce6_audio_fini(rdev);
2140 else
2141 r600_audio_fini(rdev);
2142 radeon_vm_manager_fini(rdev);
2143 cayman_cp_enable(rdev, false);
2144 cayman_dma_stop(rdev);
2145 uvd_v1_0_fini(rdev);
2146 radeon_uvd_suspend(rdev);
2147 evergreen_irq_suspend(rdev);
2148 radeon_wb_disable(rdev);
2149 cayman_pcie_gart_disable(rdev);
2150 return 0;
2151}
2152
2153/* Plan is to move initialization in that function and use
2154 * helper function so that radeon_device_init pretty much
2155 * do nothing more than calling asic specific function. This
2156 * should also allow to remove a bunch of callback function
2157 * like vram_info.
2158 */
2159int cayman_init(struct radeon_device *rdev)
2160{
2161 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2162 int r;
2163
2164 /* Read BIOS */
2165 if (!radeon_get_bios(rdev)) {
2166 if (ASIC_IS_AVIVO(rdev))
2167 return -EINVAL;
2168 }
2169 /* Must be an ATOMBIOS */
2170 if (!rdev->is_atom_bios) {
2171 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
2172 return -EINVAL;
2173 }
2174 r = radeon_atombios_init(rdev);
2175 if (r)
2176 return r;
2177
2178 /* Post card if necessary */
2179 if (!radeon_card_posted(rdev)) {
2180 if (!rdev->bios) {
2181 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2182 return -EINVAL;
2183 }
2184 DRM_INFO("GPU not posted. posting now...\n");
2185 atom_asic_init(rdev->mode_info.atom_context);
2186 }
2187 /* init golden registers */
2188 ni_init_golden_registers(rdev);
2189 /* Initialize scratch registers */
2190 r600_scratch_init(rdev);
2191 /* Initialize surface registers */
2192 radeon_surface_init(rdev);
2193 /* Initialize clocks */
2194 radeon_get_clock_info(rdev->ddev);
2195 /* Fence driver */
2196 r = radeon_fence_driver_init(rdev);
2197 if (r)
2198 return r;
2199 /* initialize memory controller */
2200 r = evergreen_mc_init(rdev);
2201 if (r)
2202 return r;
2203 /* Memory manager */
2204 r = radeon_bo_init(rdev);
2205 if (r)
2206 return r;
2207
2208 if (rdev->flags & RADEON_IS_IGP) {
2209 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2210 r = ni_init_microcode(rdev);
2211 if (r) {
2212 DRM_ERROR("Failed to load firmware!\n");
2213 return r;
2214 }
2215 }
2216 } else {
2217 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2218 r = ni_init_microcode(rdev);
2219 if (r) {
2220 DRM_ERROR("Failed to load firmware!\n");
2221 return r;
2222 }
2223 }
2224 }
2225
2226 /* Initialize power management */
2227 radeon_pm_init(rdev);
2228
2229 ring->ring_obj = NULL;
2230 r600_ring_init(rdev, ring, 1024 * 1024);
2231
2232 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2233 ring->ring_obj = NULL;
2234 r600_ring_init(rdev, ring, 64 * 1024);
2235
2236 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2237 ring->ring_obj = NULL;
2238 r600_ring_init(rdev, ring, 64 * 1024);
2239
2240 r = radeon_uvd_init(rdev);
2241 if (!r) {
2242 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2243 ring->ring_obj = NULL;
2244 r600_ring_init(rdev, ring, 4096);
2245 }
2246
2247 rdev->ih.ring_obj = NULL;
2248 r600_ih_ring_init(rdev, 64 * 1024);
2249
2250 r = r600_pcie_gart_init(rdev);
2251 if (r)
2252 return r;
2253
2254 rdev->accel_working = true;
2255 r = cayman_startup(rdev);
2256 if (r) {
2257 dev_err(rdev->dev, "disabling GPU acceleration\n");
2258 cayman_cp_fini(rdev);
2259 cayman_dma_fini(rdev);
2260 r600_irq_fini(rdev);
2261 if (rdev->flags & RADEON_IS_IGP)
2262 sumo_rlc_fini(rdev);
2263 radeon_wb_fini(rdev);
2264 radeon_ib_pool_fini(rdev);
2265 radeon_vm_manager_fini(rdev);
2266 radeon_irq_kms_fini(rdev);
2267 cayman_pcie_gart_fini(rdev);
2268 rdev->accel_working = false;
2269 }
2270
2271 /* Don't start up if the MC ucode is missing.
2272 * The default clocks and voltages before the MC ucode
2273 * is loaded are not suffient for advanced operations.
2274 *
2275 * We can skip this check for TN, because there is no MC
2276 * ucode.
2277 */
2278 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
2279 DRM_ERROR("radeon: MC ucode required for NI+.\n");
2280 return -EINVAL;
2281 }
2282
2283 return 0;
2284}
2285
2286void cayman_fini(struct radeon_device *rdev)
2287{
2288 radeon_pm_fini(rdev);
2289 cayman_cp_fini(rdev);
2290 cayman_dma_fini(rdev);
2291 r600_irq_fini(rdev);
2292 if (rdev->flags & RADEON_IS_IGP)
2293 sumo_rlc_fini(rdev);
2294 radeon_wb_fini(rdev);
2295 radeon_vm_manager_fini(rdev);
2296 radeon_ib_pool_fini(rdev);
2297 radeon_irq_kms_fini(rdev);
2298 uvd_v1_0_fini(rdev);
2299 radeon_uvd_fini(rdev);
2300 cayman_pcie_gart_fini(rdev);
2301 r600_vram_scratch_fini(rdev);
2302 radeon_gem_fini(rdev);
2303 radeon_fence_driver_fini(rdev);
2304 radeon_bo_fini(rdev);
2305 radeon_atombios_fini(rdev);
2306 kfree(rdev->bios);
2307 rdev->bios = NULL;
2308}
2309
2310/*
2311 * vm
2312 */
2313int cayman_vm_init(struct radeon_device *rdev)
2314{
2315 /* number of VMs */
2316 rdev->vm_manager.nvm = 8;
2317 /* base offset of vram pages */
2318 if (rdev->flags & RADEON_IS_IGP) {
2319 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
2320 tmp <<= 22;
2321 rdev->vm_manager.vram_base_offset = tmp;
2322 } else
2323 rdev->vm_manager.vram_base_offset = 0;
2324 return 0;
2325}
2326
2327void cayman_vm_fini(struct radeon_device *rdev)
2328{
2329}
2330
2331/**
2332 * cayman_vm_decode_fault - print human readable fault info
2333 *
2334 * @rdev: radeon_device pointer
2335 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
2336 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
2337 *
2338 * Print human readable fault information (cayman/TN).
2339 */
2340void cayman_vm_decode_fault(struct radeon_device *rdev,
2341 u32 status, u32 addr)
2342{
2343 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
2344 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
2345 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
2346 const char *block;
2347
2348 switch (mc_id) {
2349 case 32:
2350 case 16:
2351 case 96:
2352 case 80:
2353 case 160:
2354 case 144:
2355 case 224:
2356 case 208:
2357 block = "CB";
2358 break;
2359 case 33:
2360 case 17:
2361 case 97:
2362 case 81:
2363 case 161:
2364 case 145:
2365 case 225:
2366 case 209:
2367 block = "CB_FMASK";
2368 break;
2369 case 34:
2370 case 18:
2371 case 98:
2372 case 82:
2373 case 162:
2374 case 146:
2375 case 226:
2376 case 210:
2377 block = "CB_CMASK";
2378 break;
2379 case 35:
2380 case 19:
2381 case 99:
2382 case 83:
2383 case 163:
2384 case 147:
2385 case 227:
2386 case 211:
2387 block = "CB_IMMED";
2388 break;
2389 case 36:
2390 case 20:
2391 case 100:
2392 case 84:
2393 case 164:
2394 case 148:
2395 case 228:
2396 case 212:
2397 block = "DB";
2398 break;
2399 case 37:
2400 case 21:
2401 case 101:
2402 case 85:
2403 case 165:
2404 case 149:
2405 case 229:
2406 case 213:
2407 block = "DB_HTILE";
2408 break;
2409 case 38:
2410 case 22:
2411 case 102:
2412 case 86:
2413 case 166:
2414 case 150:
2415 case 230:
2416 case 214:
2417 block = "SX";
2418 break;
2419 case 39:
2420 case 23:
2421 case 103:
2422 case 87:
2423 case 167:
2424 case 151:
2425 case 231:
2426 case 215:
2427 block = "DB_STEN";
2428 break;
2429 case 40:
2430 case 24:
2431 case 104:
2432 case 88:
2433 case 232:
2434 case 216:
2435 case 168:
2436 case 152:
2437 block = "TC_TFETCH";
2438 break;
2439 case 41:
2440 case 25:
2441 case 105:
2442 case 89:
2443 case 233:
2444 case 217:
2445 case 169:
2446 case 153:
2447 block = "TC_VFETCH";
2448 break;
2449 case 42:
2450 case 26:
2451 case 106:
2452 case 90:
2453 case 234:
2454 case 218:
2455 case 170:
2456 case 154:
2457 block = "VC";
2458 break;
2459 case 112:
2460 block = "CP";
2461 break;
2462 case 113:
2463 case 114:
2464 block = "SH";
2465 break;
2466 case 115:
2467 block = "VGT";
2468 break;
2469 case 178:
2470 block = "IH";
2471 break;
2472 case 51:
2473 block = "RLC";
2474 break;
2475 case 55:
2476 block = "DMA";
2477 break;
2478 case 56:
2479 block = "HDP";
2480 break;
2481 default:
2482 block = "unknown";
2483 break;
2484 }
2485
2486 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
2487 protections, vmid, addr,
2488 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
2489 block, mc_id);
2490}
2491
2492/**
2493 * cayman_vm_flush - vm flush using the CP
2494 *
2495 * @rdev: radeon_device pointer
2496 *
2497 * Update the page table base and flush the VM TLB
2498 * using the CP (cayman-si).
2499 */
2500void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2501{
2502 struct radeon_ring *ring = &rdev->ring[ridx];
2503
2504 if (vm == NULL)
2505 return;
2506
2507 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
2508 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2509
2510 /* flush hdp cache */
2511 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2512 radeon_ring_write(ring, 0x1);
2513
2514 /* bits 0-7 are the VM contexts0-7 */
2515 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
2516 radeon_ring_write(ring, 1 << vm->id);
2517
2518 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2519 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2520 radeon_ring_write(ring, 0x0);
2521}
2522