1 | /* $NetBSD: ustirreg.h,v 1.4 2008/04/28 20:24:01 martin Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 2001 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by David Sainty <David.Sainty@dtsp.co.nz> |
9 | * |
10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions |
12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. |
15 | * 2. Redistributions in binary form must reproduce the above copyright |
16 | * notice, this list of conditions and the following disclaimer in the |
17 | * documentation and/or other materials provided with the distribution. |
18 | * |
19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
29 | * POSSIBILITY OF SUCH DAMAGE. |
30 | */ |
31 | |
32 | /* |
33 | * Registers definitions for SigmaTel STIr4200 USB/IrDA Bridge |
34 | * Controller. Documentation available at: |
35 | * http://www.sigmatel.com/technical_docs.htm |
36 | * http://extranet.sigmatel.com/library/infrared/stir4200/stir4200-ds-1-0.pdf |
37 | */ |
38 | |
39 | /* Notes: |
40 | * |
41 | * The data sheet states that the TX and RX frames are prepended with |
42 | * BOF characters. This appears to be incorrect, the standard 0xff |
43 | * characters behave as expected. |
44 | * |
45 | * There does not appear to be any way to get asynchronous |
46 | * notifications from this device that data is waiting. You simply do |
47 | * have to poll continuously looking for a non-zero-length result. |
48 | * |
49 | * The SigmaTel drivers provided with the device for other operating |
50 | * systems poll at full USB speed (1000 per second), which has a |
51 | * significant impact on the system. |
52 | */ |
53 | |
54 | /* |
55 | * The SigmaTel device is controlled via an array of registers, with |
56 | * generic register read/write commands. This is a completely |
57 | * different approach to that defined in the USB IrDA standard. |
58 | */ |
59 | #define STIR_REG_MODE 1 |
60 | #define STIR_REG_BRATE 2 |
61 | #define STIR_REG_CONTROL 3 |
62 | #define STIR_REG_SENSITIVITY 4 |
63 | #define STIR_REG_STATUS 5 |
64 | #define STIR_REG_FFCNT_LSB 6 |
65 | #define STIR_REG_FFCNT_MSB 7 |
66 | #define STIR_REG_DPLL 8 |
67 | #define STIR_REG_IRDIG 9 |
68 | |
69 | /* Register numbers range from zero to STIR_MAX_REG */ |
70 | #define STIR_MAX_REG 15 |
71 | |
72 | |
73 | /* |
74 | * Mode register bits |
75 | * |
76 | * The MIR bit was documented in earlier revisions of the data sheet, |
77 | * but in the current published version (version 1.0, March 2002) the |
78 | * MIR bit is documented as "reserved". Possibly the device has a |
79 | * design flaw affecting the MIR data rates. |
80 | */ |
81 | #define STIR_RMODE_FIR 0x80 |
82 | #define STIR_RMODE_MIR 0x40 |
83 | #define STIR_RMODE_SIR 0x20 |
84 | #define STIR_RMODE_ASK 0x10 |
85 | |
86 | /* |
87 | * FASTRXEN can be set to enable simultaneous reads and writes. It |
88 | * isn't clear that this is useful, the RX and TX data is mixed into |
89 | * the FIFO and the chip appears to get into a funny state. In the |
90 | * absence of good documentation about this bit, leave it disabled! |
91 | */ |
92 | #define STIR_RMODE_FASTRXEN 0x08 |
93 | |
94 | #define STIR_RMODE_FFRSTEN 0x04 |
95 | |
96 | /* FFSPRST must be set to enable the FIFO */ |
97 | #define STIR_RMODE_FFSPRST 0x02 |
98 | |
99 | /* |
100 | * High bit baud rate generator value, used in conjunction with the |
101 | * BRATE register. |
102 | */ |
103 | #define STIR_RMODE_PDCLK8 0x01 |
104 | |
105 | |
106 | /* Status register bits */ |
107 | #define STIR_RSTATUS_EOFRAME 0x80 |
108 | #define STIR_RSTATUS_FFUNDER 0x40 |
109 | #define STIR_RSTATUS_FFOVER 0x20 |
110 | |
111 | /* Set in write direction, cleared in read direction */ |
112 | #define STIR_RSTATUS_FFDIR 0x10 |
113 | |
114 | /* |
115 | * FFCLR is write-only, and the only writable bit in the STATUS |
116 | * register. |
117 | */ |
118 | #define STIR_RSTATUS_FFCLR 0x08 |
119 | |
120 | #define STIR_RSTATUS_FFEMPTY 0x04 |
121 | #define STIR_RSTATUS_FFRXERR 0x02 |
122 | #define STIR_RSTATUS_FFTXERR 0x01 |
123 | |
124 | |
125 | /* Extract data from portions of registers */ |
126 | #define STIR_GET_SENSITIVITY_CHIPREVISION(x) ((x) & 7) |
127 | |
128 | /* |
129 | * According to the documentation, FFCNT may be off by as much as 3 |
130 | * bytes. |
131 | */ |
132 | #define STIR_FFCNT_MARGIN 3 |
133 | |
134 | /* |
135 | * The FIFO size for the device is a fixed 4k bytes |
136 | */ |
137 | #define STIR_FIFO_SIZE 0x1000 |
138 | |
139 | /* |
140 | * Vendor specific device requests |
141 | */ |
142 | #define STIR_CMD_WRITEMULTIREG 0x00 |
143 | #define STIR_CMD_READMULTIREG 0x01 |
144 | #define STIR_CMD_READROM 0x02 |
145 | #define STIR_CMD_WRITESINGLEREG 0x03 |
146 | |
147 | /* |
148 | * The MSB is the MODE register setting, the LSB is the BRATE register |
149 | * setting. |
150 | * |
151 | * The MIR rates (576000 and 1152000) were documented in earlier |
152 | * revisions of the data sheet, but in the current published version |
153 | * these data rates have disappeared. Possibly the device has a |
154 | * design flaw affecting the MIR data rates. |
155 | */ |
156 | #define STIR_BRMODE_4000000 0x8002 |
157 | #define STIR_BRMODE_1152000 0x4001 |
158 | #define STIR_BRMODE_576000 0x4003 |
159 | #define STIR_BRMODE_115200 0x2009 |
160 | #define STIR_BRMODE_57600 0x2013 |
161 | #define STIR_BRMODE_38400 0x201d |
162 | #define STIR_BRMODE_19200 0x203b |
163 | #define STIR_BRMODE_9600 0x2077 |
164 | #define STIR_BRMODE_2400 0x21df |
165 | |
166 | /* |
167 | * Extract values from STIR_BRMODE values. |
168 | */ |
169 | #define STIR_BRMODE_MODEREG(x) ((x) >> 8) |
170 | #define STIR_BRMODE_BRATEREG(x) ((x) & 0xff) |
171 | |
172 | /* |
173 | * Each transmit frame starts with the sequence: |
174 | * |
175 | * 0x55 0xaa LSB(Length) MSB(Length) |
176 | */ |
177 | #define 4 |
178 | #define 0x55 |
179 | #define 0xaa |
180 | |