1 | /* $NetBSD: aic6360reg.h,v 1.3 2005/12/11 12:21:25 christos Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1994, 1995, 1996 Charles M. Hannum. All rights reserved. |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
9 | * 1. Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * 2. Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
14 | * 3. All advertising materials mentioning features or use of this software |
15 | * must display the following acknowledgement: |
16 | * This product includes software developed by Charles M. Hannum. |
17 | * 4. The name of the author may not be used to endorse or promote products |
18 | * derived from this software without specific prior written permission. |
19 | * |
20 | * Copyright (c) 1994 Jarle Greipsland |
21 | * All rights reserved. |
22 | * |
23 | * Redistribution and use in source and binary forms, with or without |
24 | * modification, are permitted provided that the following conditions |
25 | * are met: |
26 | * 1. Redistributions of source code must retain the above copyright |
27 | * notice, this list of conditions and the following disclaimer. |
28 | * 2. Redistributions in binary form must reproduce the above copyright |
29 | * notice, this list of conditions and the following disclaimer in the |
30 | * documentation and/or other materials provided with the distribution. |
31 | * 3. The name of the author may not be used to endorse or promote products |
32 | * derived from this software without specific prior written permission. |
33 | * |
34 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
35 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
36 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
37 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, |
38 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
39 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
40 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
41 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
42 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
43 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
44 | * POSSIBILITY OF SUCH DAMAGE. |
45 | */ |
46 | |
47 | /* |
48 | * Acknowledgements: Many of the algorithms used in this driver are |
49 | * inspired by the work of Julian Elischer (julian@tfs.com) and |
50 | * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! |
51 | */ |
52 | |
53 | /* Definitions, most of them have turned out to be unnecessary, but here they |
54 | * are anyway. |
55 | */ |
56 | |
57 | /* AIC6360 definitions */ |
58 | #define SCSISEQ 0x00 /* SCSI sequence control */ |
59 | #define SXFRCTL0 0x01 /* SCSI transfer control 0 */ |
60 | #define SXFRCTL1 0x02 /* SCSI transfer control 1 */ |
61 | #define SCSISIG 0x03 /* SCSI signal in/out */ |
62 | #define SCSIRATE 0x04 /* SCSI rate control */ |
63 | #define SCSIID 0x05 /* SCSI ID */ |
64 | #define SELID 0x05 /* Selection/Reselection ID */ |
65 | #define SCSIDAT 0x06 /* SCSI Latched Data */ |
66 | #define SCSIBUS 0x07 /* SCSI Data Bus*/ |
67 | #define STCNT0 0x08 /* SCSI transfer count */ |
68 | #define STCNT1 0x09 |
69 | #define STCNT2 0x0a |
70 | #define CLRSINT0 0x0b /* Clear SCSI interrupts 0 */ |
71 | #define SSTAT0 0x0b /* SCSI interrupt status 0 */ |
72 | #define CLRSINT1 0x0c /* Clear SCSI interrupts 1 */ |
73 | #define SSTAT1 0x0c /* SCSI status 1 */ |
74 | #define SSTAT2 0x0d /* SCSI status 2 */ |
75 | #define SCSITEST 0x0e /* SCSI test control */ |
76 | #define SSTAT3 0x0e /* SCSI status 3 */ |
77 | #define CLRSERR 0x0f /* Clear SCSI errors */ |
78 | #define SSTAT4 0x0f /* SCSI status 4 */ |
79 | #define SIMODE0 0x10 /* SCSI interrupt mode 0 */ |
80 | #define SIMODE1 0x11 /* SCSI interrupt mode 1 */ |
81 | #define DMACNTRL0 0x12 /* DMA control 0 */ |
82 | #define DMACNTRL1 0x13 /* DMA control 1 */ |
83 | #define DMASTAT 0x14 /* DMA status */ |
84 | #define FIFOSTAT 0x15 /* FIFO status */ |
85 | #define DMADATA 0x16 /* DMA data */ |
86 | #define DMADATAL 0x16 /* DMA data low byte */ |
87 | #define DMADATAH 0x17 /* DMA data high byte */ |
88 | #define BRSTCNTRL 0x18 /* Burst Control */ |
89 | #define DMADATALONG 0x18 |
90 | #define PORTA 0x1a /* Port A */ |
91 | #define PORTB 0x1b /* Port B */ |
92 | #define REV 0x1c /* Revision (001 for 6360) */ |
93 | #define STACK 0x1d /* Stack */ |
94 | #define TEST 0x1e /* Test register */ |
95 | #define ID 0x1f /* ID register */ |
96 | |
97 | #define IDSTRING "(C)1991ADAPTECAIC6360 " |
98 | |
99 | /* What all the bits do */ |
100 | |
101 | /* SCSISEQ */ |
102 | #define TEMODEO 0x80 |
103 | #define ENSELO 0x40 |
104 | #define ENSELI 0x20 |
105 | #define ENRESELI 0x10 |
106 | #define ENAUTOATNO 0x08 |
107 | #define ENAUTOATNI 0x04 |
108 | #define ENAUTOATNP 0x02 |
109 | #define SCSIRSTO 0x01 |
110 | |
111 | /* SXFRCTL0 */ |
112 | #define SCSIEN 0x80 |
113 | #define DMAEN 0x40 |
114 | #define CHEN 0x20 |
115 | #define CLRSTCNT 0x10 |
116 | #define SPIOEN 0x08 |
117 | #define CLRCH 0x02 |
118 | |
119 | /* SXFRCTL1 */ |
120 | #define BITBUCKET 0x80 |
121 | #define SWRAPEN 0x40 |
122 | #define ENSPCHK 0x20 |
123 | #define STIMESEL1 0x10 |
124 | #define STIMESEL0 0x08 |
125 | #define STIMO_256ms 0x00 |
126 | #define STIMO_128ms 0x08 |
127 | #define STIMO_64ms 0x10 |
128 | #define STIMO_32ms 0x18 |
129 | #define ENSTIMER 0x04 |
130 | #define BYTEALIGN 0x02 |
131 | |
132 | /* SCSISIG (in) */ |
133 | #define CDI 0x80 |
134 | #define IOI 0x40 |
135 | #define MSGI 0x20 |
136 | #define ATNI 0x10 |
137 | #define SELI 0x08 |
138 | #define BSYI 0x04 |
139 | #define REQI 0x02 |
140 | #define ACKI 0x01 |
141 | |
142 | /* Important! The 3 most significant bits of this register, in initiator mode, |
143 | * represents the "expected" SCSI bus phase and can be used to trigger phase |
144 | * mismatch and phase change interrupts. But more important: If there is a |
145 | * phase mismatch the chip will not transfer any data! This is actually a nice |
146 | * feature as it gives us a bit more control over what is happening when we are |
147 | * bursting data (in) through the FIFOs and the phase suddenly changes from |
148 | * DATA IN to STATUS or MESSAGE IN. The transfer will stop and wait for the |
149 | * proper phase to be set in this register instead of dumping the bits into the |
150 | * FIFOs. |
151 | */ |
152 | /* SCSISIG (out) */ |
153 | #define CDO 0x80 |
154 | #define IOO 0x40 |
155 | #define MSGO 0x20 |
156 | #define ATNO 0x10 |
157 | #define SELO 0x08 |
158 | #define BSYO 0x04 |
159 | #define REQO 0x02 |
160 | #define ACKO 0x01 |
161 | |
162 | /* Information transfer phases */ |
163 | #define PH_DATAOUT (0) |
164 | #define PH_DATAIN (IOI) |
165 | #define PH_CMD (CDI) |
166 | #define PH_STAT (CDI | IOI) |
167 | #define PH_MSGOUT (MSGI | CDI) |
168 | #define PH_MSGIN (MSGI | CDI | IOI) |
169 | |
170 | #define PH_MASK (MSGI | CDI | IOI) |
171 | |
172 | #define PH_INVALID 0xff |
173 | |
174 | /* SCSIRATE */ |
175 | #define SXFR2 0x40 |
176 | #define SXFR1 0x20 |
177 | #define SXFR0 0x10 |
178 | #define SOFS3 0x08 |
179 | #define SOFS2 0x04 |
180 | #define SOFS1 0x02 |
181 | #define SOFS0 0x01 |
182 | |
183 | /* SCSI ID */ |
184 | #define OID2 0x40 |
185 | #define OID1 0x20 |
186 | #define OID0 0x10 |
187 | #define OID_S 4 /* shift value */ |
188 | #define TID2 0x04 |
189 | #define TID1 0x02 |
190 | #define TID0 0x01 |
191 | #define SCSI_ID_MASK 0x7 |
192 | |
193 | /* SCSI selection/reselection ID (both target *and* initiator) */ |
194 | #define SELID7 0x80 |
195 | #define SELID6 0x40 |
196 | #define SELID5 0x20 |
197 | #define SELID4 0x10 |
198 | #define SELID3 0x08 |
199 | #define SELID2 0x04 |
200 | #define SELID1 0x02 |
201 | #define SELID0 0x01 |
202 | |
203 | /* CLRSINT0 Clears what? (interrupt and/or status bit) */ |
204 | #define SETSDONE 0x80 |
205 | #define CLRSELDO 0x40 /* I */ |
206 | #define CLRSELDI 0x20 /* I+ */ |
207 | #define CLRSELINGO 0x10 /* I */ |
208 | #define CLRSWRAP 0x08 /* I+S */ |
209 | #define CLRSDONE 0x04 /* I+S */ |
210 | #define CLRSPIORDY 0x02 /* I */ |
211 | #define CLRDMADONE 0x01 /* I */ |
212 | |
213 | /* SSTAT0 Howto clear */ |
214 | #define TARGET 0x80 |
215 | #define SELDO 0x40 /* Selfclearing */ |
216 | #define SELDI 0x20 /* Selfclearing when CLRSELDI is set */ |
217 | #define SELINGO 0x10 /* Selfclearing */ |
218 | #define SWRAP 0x08 /* CLRSWAP */ |
219 | #define SDONE 0x04 /* Not used in initiator mode */ |
220 | #define SPIORDY 0x02 /* Selfclearing (op on SCSIDAT) */ |
221 | #define DMADONE 0x01 /* Selfclearing (all FIFOs empty & T/C */ |
222 | |
223 | /* CLRSINT1 Clears what? */ |
224 | #define CLRSELTIMO 0x80 /* I+S */ |
225 | #define CLRATNO 0x40 |
226 | #define CLRSCSIRSTI 0x20 /* I+S */ |
227 | #define CLRBUSFREE 0x08 /* I+S */ |
228 | #define CLRSCSIPERR 0x04 /* I+S */ |
229 | #define CLRPHASECHG 0x02 /* I+S */ |
230 | #define CLRREQINIT 0x01 /* I+S */ |
231 | |
232 | /* SSTAT1 How to clear? When set?*/ |
233 | #define SELTO 0x80 /* C select out timeout */ |
234 | #define ATNTARG 0x40 /* Not used in initiator mode */ |
235 | #define SCSIRSTI 0x20 /* C RST asserted */ |
236 | #define PHASEMIS 0x10 /* Selfclearing */ |
237 | #define BUSFREE 0x08 /* C bus free condition */ |
238 | #define SCSIPERR 0x04 /* C parity error on inbound data */ |
239 | #define PHASECHG 0x02 /* C phase in SCSISIG doesn't match */ |
240 | #define REQINIT 0x01 /* C or ACK asserting edge of REQ */ |
241 | |
242 | /* SSTAT2 */ |
243 | #define SOFFSET 0x20 |
244 | #define SEMPTY 0x10 |
245 | #define SFULL 0x08 |
246 | #define SFCNT2 0x04 |
247 | #define SFCNT1 0x02 |
248 | #define SFCNT0 0x01 |
249 | |
250 | /* SCSITEST */ |
251 | #define SCTESTU 0x08 |
252 | #define SCTESTD 0x04 |
253 | #define STCTEST 0x01 |
254 | |
255 | /* SSTAT3 */ |
256 | #define SCSICNT3 0x80 |
257 | #define SCSICNT2 0x40 |
258 | #define SCSICNT1 0x20 |
259 | #define SCSICNT0 0x10 |
260 | #define OFFCNT3 0x08 |
261 | #define OFFCNT2 0x04 |
262 | #define OFFCNT1 0x02 |
263 | #define OFFCNT0 0x01 |
264 | |
265 | /* CLRSERR */ |
266 | #define CLRSYNCERR 0x04 |
267 | #define CLRFWERR 0x02 |
268 | #define CLRFRERR 0x01 |
269 | |
270 | /* SSTAT4 */ |
271 | #define SYNCERR 0x04 |
272 | #define FWERR 0x02 |
273 | #define FRERR 0x01 |
274 | |
275 | /* SIMODE0 */ |
276 | #define ENSELDO 0x40 |
277 | #define ENSELDI 0x20 |
278 | #define ENSELINGO 0x10 |
279 | #define ENSWRAP 0x08 |
280 | #define ENSDONE 0x04 |
281 | #define ENSPIORDY 0x02 |
282 | #define ENDMADONE 0x01 |
283 | |
284 | /* SIMODE1 */ |
285 | #define ENSELTIMO 0x80 |
286 | #define ENATNTARG 0x40 |
287 | #define ENSCSIRST 0x20 |
288 | #define ENPHASEMIS 0x10 |
289 | #define ENBUSFREE 0x08 |
290 | #define ENSCSIPERR 0x04 |
291 | #define ENPHASECHG 0x02 |
292 | #define ENREQINIT 0x01 |
293 | |
294 | /* DMACNTRL0 */ |
295 | #define ENDMA 0x80 |
296 | #define B8MODE 0x40 |
297 | #define DMA 0x20 |
298 | #define DWORDPIO 0x10 |
299 | #define WRITE 0x08 |
300 | #define INTEN 0x04 |
301 | #define RSTFIFO 0x02 |
302 | #define SWINT 0x01 |
303 | |
304 | /* DMACNTRL1 */ |
305 | #define PWRDWN 0x80 |
306 | #define ENSTK32 0x40 |
307 | #define STK4 0x10 |
308 | #define STK3 0x08 |
309 | #define STK2 0x04 |
310 | #define STK1 0x02 |
311 | #define STK0 0x01 |
312 | |
313 | /* DMASTAT */ |
314 | #define ATDONE 0x80 |
315 | #define WORDRDY 0x40 |
316 | #define INTSTAT 0x20 |
317 | #define DFIFOFULL 0x10 |
318 | #define DFIFOEMP 0x08 |
319 | #define DFIFOHF 0x04 |
320 | #define DWORDRDY 0x02 |
321 | |
322 | /* BRSTCNTRL */ |
323 | #define BON3 0x80 |
324 | #define BON2 0x40 |
325 | #define BON1 0x20 |
326 | #define BON0 0x10 |
327 | #define BOFF3 0x08 |
328 | #define BOFF2 0x04 |
329 | #define BOFF1 0x02 |
330 | #define BOFF0 0x01 |
331 | |
332 | /* TEST */ |
333 | #define BOFFTMR 0x40 |
334 | #define BONTMR 0x20 |
335 | #define STCNTH 0x10 |
336 | #define STCNTM 0x08 |
337 | #define STCNTL 0x04 |
338 | #define SCSIBLK 0x02 |
339 | #define DMABLK 0x01 |
340 | |