1 | /* |
2 | * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting |
3 | * Copyright (c) 2002-2008 Atheros Communications, Inc. |
4 | * |
5 | * Permission to use, copy, modify, and/or distribute this software for any |
6 | * purpose with or without fee is hereby granted, provided that the above |
7 | * copyright notice and this permission notice appear in all copies. |
8 | * |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
16 | * |
17 | * $Id: ah_eeprom.h,v 1.1.1.1 2008/12/11 04:46:23 alc Exp $ |
18 | */ |
19 | #ifndef _ATH_AH_EEPROM_H_ |
20 | #define _ATH_AH_EEPROM_H_ |
21 | |
22 | #define AR_EEPROM_VER1 0x1000 /* Version 1.0; 5210 only */ |
23 | /* |
24 | * Version 3 EEPROMs are all 16K. |
25 | * 3.1 adds turbo limit, antenna gain, 16 CTL's, 11g info, |
26 | * and 2.4Ghz ob/db for B & G |
27 | * 3.2 has more accurate pcdac intercepts and analog chip |
28 | * calibration. |
29 | * 3.3 adds ctl in-band limit, 32 ctl's, and frequency |
30 | * expansion |
31 | * 3.4 adds xr power, gainI, and 2.4 turbo params |
32 | */ |
33 | #define AR_EEPROM_VER3 0x3000 /* Version 3.0; start of 16k EEPROM */ |
34 | #define AR_EEPROM_VER3_1 0x3001 /* Version 3.1 */ |
35 | #define AR_EEPROM_VER3_2 0x3002 /* Version 3.2 */ |
36 | #define AR_EEPROM_VER3_3 0x3003 /* Version 3.3 */ |
37 | #define AR_EEPROM_VER3_4 0x3004 /* Version 3.4 */ |
38 | #define AR_EEPROM_VER4 0x4000 /* Version 4.x */ |
39 | #define AR_EEPROM_VER4_0 0x4000 /* Version 4.0 */ |
40 | #define AR_EEPROM_VER4_1 0x4001 /* Version 4.0 */ |
41 | #define AR_EEPROM_VER4_2 0x4002 /* Version 4.0 */ |
42 | #define AR_EEPROM_VER4_3 0x4003 /* Version 4.0 */ |
43 | #define AR_EEPROM_VER4_6 0x4006 /* Version 4.0 */ |
44 | #define AR_EEPROM_VER4_7 0x3007 /* Version 4.7 */ |
45 | #define AR_EEPROM_VER4_9 0x4009 /* EEPROM EAR futureproofing */ |
46 | #define AR_EEPROM_VER5 0x5000 /* Version 5.x */ |
47 | #define AR_EEPROM_VER5_0 0x5000 /* Adds new 2413 cal powers and added params */ |
48 | #define AR_EEPROM_VER5_1 0x5001 /* Adds capability values */ |
49 | #define AR_EEPROM_VER5_3 0x5003 /* Adds spur mitigation table */ |
50 | #define AR_EEPROM_VER5_4 0x5004 |
51 | /* |
52 | * Version 14 EEPROMs came in with AR5416. |
53 | * 14.2 adds txFrameToPaOn, txFrameToDataStart, ht40PowerInc |
54 | * 14.3 adds bswAtten, bswMargin, swSettle, and base OpFlags for HT20/40 |
55 | */ |
56 | #define AR_EEPROM_VER14 0xE000 /* Version 14.x */ |
57 | #define AR_EEPROM_VER14_1 0xE001 /* Adds 11n support */ |
58 | #define AR_EEPROM_VER14_2 0xE002 |
59 | #define AR_EEPROM_VER14_3 0xE003 |
60 | #define AR_EEPROM_VER14_7 0xE007 |
61 | #define AR_EEPROM_VER14_9 0xE009 |
62 | #define AR_EEPROM_VER14_16 0xE010 |
63 | #define AR_EEPROM_VER14_17 0xE011 |
64 | #define AR_EEPROM_VER14_19 0xE013 |
65 | |
66 | enum { |
67 | AR_EEP_RFKILL, /* use ath_hal_eepromGetFlag */ |
68 | AR_EEP_AMODE, /* use ath_hal_eepromGetFlag */ |
69 | AR_EEP_BMODE, /* use ath_hal_eepromGetFlag */ |
70 | AR_EEP_GMODE, /* use ath_hal_eepromGetFlag */ |
71 | AR_EEP_TURBO5DISABLE, /* use ath_hal_eepromGetFlag */ |
72 | AR_EEP_TURBO2DISABLE, /* use ath_hal_eepromGetFlag */ |
73 | AR_EEP_ISTALON, /* use ath_hal_eepromGetFlag */ |
74 | AR_EEP_32KHZCRYSTAL, /* use ath_hal_eepromGetFlag */ |
75 | AR_EEP_MACADDR, /* uint8_t* */ |
76 | AR_EEP_COMPRESS, /* use ath_hal_eepromGetFlag */ |
77 | AR_EEP_FASTFRAME, /* use ath_hal_eepromGetFlag */ |
78 | AR_EEP_AES, /* use ath_hal_eepromGetFlag */ |
79 | AR_EEP_BURST, /* use ath_hal_eepromGetFlag */ |
80 | AR_EEP_MAXQCU, /* uint16_t* */ |
81 | AR_EEP_KCENTRIES, /* uint16_t* */ |
82 | AR_EEP_NFTHRESH_5, /* int16_t* */ |
83 | AR_EEP_NFTHRESH_2, /* int16_t* */ |
84 | AR_EEP_REGDMN_0, /* uint16_t* */ |
85 | AR_EEP_REGDMN_1, /* uint16_t* */ |
86 | AR_EEP_OPCAP, /* uint16_t* */ |
87 | AR_EEP_OPMODE, /* uint16_t* */ |
88 | AR_EEP_RFSILENT, /* uint16_t* */ |
89 | AR_EEP_OB_5, /* uint8_t* */ |
90 | AR_EEP_DB_5, /* uint8_t* */ |
91 | AR_EEP_OB_2, /* uint8_t* */ |
92 | AR_EEP_DB_2, /* uint8_t* */ |
93 | AR_EEP_TXMASK, /* uint8_t* */ |
94 | AR_EEP_RXMASK, /* uint8_t* */ |
95 | AR_EEP_RXGAIN_TYPE, /* uint8_t* */ |
96 | AR_EEP_TXGAIN_TYPE, /* uint8_t* */ |
97 | AR_EEP_OL_PWRCTRL, /* use ath_hal_eepromGetFlag */ |
98 | AR_EEP_FSTCLK_5G, /* use ath_hal_eepromGetFlag */ |
99 | AR_EEP_ANTGAINMAX_5, /* int8_t* */ |
100 | AR_EEP_ANTGAINMAX_2, /* int8_t* */ |
101 | AR_EEP_WRITEPROTECT, /* use ath_hal_eepromGetFlag */ |
102 | }; |
103 | |
104 | typedef struct { |
105 | uint16_t rdEdge; |
106 | uint16_t twice_rdEdgePower; |
107 | HAL_BOOL flag; |
108 | } RD_EDGES_POWER; |
109 | |
110 | /* XXX should probably be version-dependent */ |
111 | #define SD_NO_CTL 0xf0 |
112 | #define NO_CTL 0xff |
113 | #define CTL_MODE_M 0x0f |
114 | #define CTL_11A 0 |
115 | #define CTL_11B 1 |
116 | #define CTL_11G 2 |
117 | #define CTL_TURBO 3 |
118 | #define CTL_108G 4 |
119 | #define CTL_2GHT20 5 |
120 | #define CTL_5GHT20 6 |
121 | #define CTL_2GHT40 7 |
122 | #define CTL_5GHT40 8 |
123 | |
124 | #define AR_NO_SPUR 0x8000 |
125 | |
126 | /* XXX exposed to chip code */ |
127 | #define MAX_RATE_POWER 63 |
128 | |
129 | HAL_STATUS ath_hal_v1EepromAttach(struct ath_hal *ah); |
130 | HAL_STATUS ath_hal_legacyEepromAttach(struct ath_hal *ah); |
131 | HAL_STATUS ath_hal_v14EepromAttach(struct ath_hal *ah); |
132 | HAL_STATUS ath_hal_v4kEepromAttach(struct ath_hal *ah); |
133 | #endif /* _ATH_AH_EEPROM_H_ */ |
134 | |