1 | /* $NetBSD: cxdtv.c,v 1.14 2014/03/29 19:28:24 christos Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 2008, 2011 Jonathan A. Kollasch |
5 | * All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
18 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
19 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR |
20 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
21 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
22 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
23 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
25 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
26 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
28 | |
29 | #include <sys/cdefs.h> |
30 | __KERNEL_RCSID(0, "$NetBSD: cxdtv.c,v 1.14 2014/03/29 19:28:24 christos Exp $" ); |
31 | |
32 | #include <sys/param.h> |
33 | #include <sys/kernel.h> |
34 | #include <sys/device.h> |
35 | #include <sys/kmem.h> |
36 | #include <sys/mutex.h> |
37 | #include <sys/proc.h> |
38 | #include <sys/module.h> |
39 | #include <sys/bus.h> |
40 | |
41 | #include <dev/pci/pcivar.h> |
42 | #include <dev/pci/pcireg.h> |
43 | #include <dev/pci/pcidevs.h> |
44 | #include <dev/i2c/i2cvar.h> |
45 | #include <dev/i2c/i2c_bitbang.h> |
46 | |
47 | #include <dev/i2c/tvpllvar.h> |
48 | #include <dev/i2c/tvpll_tuners.h> |
49 | |
50 | #include <dev/i2c/nxt2kvar.h> |
51 | #include <dev/i2c/lg3303var.h> |
52 | |
53 | #include <dev/dtv/dtvif.h> |
54 | |
55 | #include <dev/pci/cxdtvreg.h> |
56 | #include <dev/pci/cxdtvvar.h> |
57 | #include <dev/pci/cxdtv_boards.h> |
58 | |
59 | #define CXDTV_MMBASE 0x10 |
60 | |
61 | #define CXDTV_SRAM_CH_MPEG 0 |
62 | #define CXDTV_TS_PKTSIZE (188 * 8) |
63 | |
64 | static int cxdtv_match(device_t, cfdata_t, void *); |
65 | static void cxdtv_attach(device_t, device_t, void *); |
66 | static int cxdtv_detach(device_t, int); |
67 | static int cxdtv_rescan(device_t, const char *, const int *); |
68 | static void cxdtv_childdet(device_t, device_t); |
69 | static int cxdtv_intr(void *); |
70 | |
71 | static bool cxdtv_resume(device_t, const pmf_qual_t *); |
72 | |
73 | static int cxdtv_iic_acquire_bus(void *, int); |
74 | static void cxdtv_iic_release_bus(void *, int); |
75 | static int cxdtv_iic_send_start(void *, int); |
76 | static int cxdtv_iic_send_stop(void *, int); |
77 | static int cxdtv_iic_initiate_xfer(void *, i2c_addr_t, int); |
78 | static int cxdtv_iic_read_byte(void *, uint8_t *, int); |
79 | static int cxdtv_iic_write_byte(void *, uint8_t, int); |
80 | |
81 | static void cxdtv_i2cbb_set_bits(void *, uint32_t); |
82 | static void cxdtv_i2cbb_set_dir(void *, uint32_t); |
83 | static uint32_t cxdtv_i2cbb_read_bits(void *); |
84 | |
85 | static int cxdtv_sram_ch_setup(struct cxdtv_softc *, |
86 | struct cxdtv_sram_ch *, uint32_t); |
87 | static int cxdtv_allocmem(struct cxdtv_softc *, size_t, size_t, |
88 | struct cxdtv_dma *); |
89 | static int cxdtv_freemem(struct cxdtv_softc *, struct cxdtv_dma *); |
90 | static int cxdtv_risc_buffer(struct cxdtv_softc *, uint32_t, uint32_t); |
91 | static int cxdtv_risc_field(struct cxdtv_softc *, uint32_t *, uint32_t); |
92 | |
93 | static int cxdtv_mpeg_attach(struct cxdtv_softc *); |
94 | static int cxdtv_mpeg_detach(struct cxdtv_softc *, int flags); |
95 | static int cxdtv_mpeg_intr(struct cxdtv_softc *); |
96 | static int cxdtv_mpeg_reset(struct cxdtv_softc *); |
97 | |
98 | static int cxdtv_mpeg_trigger(struct cxdtv_softc *, void *); |
99 | static int cxdtv_mpeg_halt(struct cxdtv_softc *); |
100 | static void * cxdtv_mpeg_malloc(struct cxdtv_softc *, size_t); |
101 | static void cxdtv_mpeg_free(struct cxdtv_softc *, void *); |
102 | |
103 | static void cxdtv_card_init_hd5500(struct cxdtv_softc *); |
104 | static void cxdtv_card_init_hdtvwonder(struct cxdtv_softc *); |
105 | |
106 | /* MPEG TS Port */ |
107 | static void cxdtv_dtv_get_devinfo(void *, struct dvb_frontend_info *); |
108 | static int cxdtv_dtv_open(void *, int); |
109 | static void cxdtv_dtv_close(void *); |
110 | static int cxdtv_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); |
111 | static fe_status_t cxdtv_dtv_get_status(void *); |
112 | static uint16_t cxdtv_dtv_get_signal_strength(void *); |
113 | static uint16_t cxdtv_dtv_get_snr(void *); |
114 | static int cxdtv_dtv_start_transfer(void *, |
115 | void (*)(void *, const struct dtv_payload *), void *); |
116 | static int cxdtv_dtv_stop_transfer(void *); |
117 | |
118 | static const struct dtv_hw_if cxdtv_dtv_if = { |
119 | .get_devinfo = cxdtv_dtv_get_devinfo, |
120 | .open = cxdtv_dtv_open, |
121 | .close = cxdtv_dtv_close, |
122 | .set_tuner = cxdtv_dtv_set_tuner, |
123 | .get_status = cxdtv_dtv_get_status, |
124 | .get_signal_strength = cxdtv_dtv_get_signal_strength, |
125 | .get_snr = cxdtv_dtv_get_snr, |
126 | .start_transfer = cxdtv_dtv_start_transfer, |
127 | .stop_transfer = cxdtv_dtv_stop_transfer, |
128 | }; |
129 | |
130 | const struct i2c_bitbang_ops cxdtv_i2cbb_ops = { |
131 | cxdtv_i2cbb_set_bits, |
132 | cxdtv_i2cbb_set_dir, |
133 | cxdtv_i2cbb_read_bits, |
134 | { CXDTV_I2C_C_DATACONTROL_SDA, CXDTV_I2C_C_DATACONTROL_SCL, 0, 0 } |
135 | }; |
136 | |
137 | /* Maybe make this dynamically allocated. */ |
138 | static struct cxdtv_sram_ch cxdtv_sram_chs[] = { |
139 | [CXDTV_SRAM_CH_MPEG] = { |
140 | .csc_cmds = 0x180200, /* CMDS for ch. 28 */ |
141 | .csc_iq = 0x180340, /* after last CMDS */ |
142 | .csc_iqsz = 0x40, /* 16 dwords */ |
143 | .csc_cdt = 0x180380, /* after iq */ |
144 | .csc_cdtsz = 0x40, /* cluster discriptor space */ |
145 | .csc_fifo = 0x180400, /* after cdt */ |
146 | .csc_fifosz = 0x001C00, /* let's just align this up */ |
147 | .csc_risc = 0x182000, /* after fifo */ |
148 | .csc_riscsz = 0x6000, /* room for dma programs */ |
149 | .csc_ptr1 = CXDTV_DMA28_PTR1, |
150 | .csc_ptr2 = CXDTV_DMA28_PTR2, |
151 | .csc_cnt1 = CXDTV_DMA28_CNT1, |
152 | .csc_cnt2 = CXDTV_DMA28_CNT2, |
153 | }, |
154 | }; |
155 | |
156 | CFATTACH_DECL2_NEW(cxdtv, sizeof(struct cxdtv_softc), |
157 | cxdtv_match, cxdtv_attach, cxdtv_detach, NULL, |
158 | cxdtv_rescan, cxdtv_childdet); |
159 | |
160 | static int |
161 | cxdtv_match(device_t parent, cfdata_t match, void *aux) |
162 | { |
163 | const struct pci_attach_args *pa; |
164 | pcireg_t reg; |
165 | |
166 | pa = aux; |
167 | |
168 | if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) |
169 | return 0; |
170 | |
171 | if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CONEXANT_CX2388XMPEG) |
172 | return 0; |
173 | |
174 | reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); |
175 | if (cxdtv_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg)) == NULL) |
176 | return 0; |
177 | |
178 | return 1; |
179 | } |
180 | |
181 | static void |
182 | cxdtv_attach(device_t parent, device_t self, void *aux) |
183 | { |
184 | struct cxdtv_softc *sc; |
185 | const struct pci_attach_args *pa = aux; |
186 | pci_intr_handle_t ih; |
187 | pcireg_t reg; |
188 | const char *intrstr; |
189 | struct i2cbus_attach_args iba; |
190 | char intrbuf[PCI_INTRSTR_LEN]; |
191 | |
192 | sc = device_private(self); |
193 | |
194 | sc->sc_dev = self; |
195 | sc->sc_pc = pa->pa_pc; |
196 | |
197 | reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); |
198 | |
199 | sc->sc_vendor = PCI_VENDOR(reg); |
200 | sc->sc_product = PCI_PRODUCT(reg); |
201 | |
202 | sc->sc_board = cxdtv_board_lookup(sc->sc_vendor, sc->sc_product); |
203 | KASSERT(sc->sc_board != NULL); |
204 | |
205 | pci_aprint_devinfo(pa, NULL); |
206 | |
207 | if (pci_mapreg_map(pa, CXDTV_MMBASE, PCI_MAPREG_TYPE_MEM, 0, |
208 | &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { |
209 | aprint_error_dev(self, "couldn't map memory space\n" ); |
210 | return; |
211 | } |
212 | |
213 | sc->sc_dmat = pa->pa_dmat; |
214 | |
215 | if (pci_intr_map(pa, &ih)) { |
216 | aprint_error_dev(self, "couldn't map interrupt\n" ); |
217 | return; |
218 | } |
219 | intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); |
220 | sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_VM, cxdtv_intr, sc); |
221 | if (sc->sc_ih == NULL) { |
222 | aprint_error_dev(self, "couldn't establish interrupt" ); |
223 | if (intrstr != NULL) |
224 | aprint_error(" at %s" , intrstr); |
225 | aprint_error("\n" ); |
226 | return; |
227 | } |
228 | aprint_normal_dev(self, "interrupting at %s\n" , intrstr); |
229 | |
230 | /* set master */ |
231 | reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); |
232 | reg |= PCI_COMMAND_MASTER_ENABLE; |
233 | pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); |
234 | |
235 | mutex_init(&sc->sc_i2c_buslock, MUTEX_DRIVER, IPL_NONE); |
236 | sc->sc_i2c.ic_cookie = sc; |
237 | sc->sc_i2c.ic_exec = NULL; |
238 | sc->sc_i2c.ic_acquire_bus = cxdtv_iic_acquire_bus; |
239 | sc->sc_i2c.ic_release_bus = cxdtv_iic_release_bus; |
240 | sc->sc_i2c.ic_send_start = cxdtv_iic_send_start; |
241 | sc->sc_i2c.ic_send_stop = cxdtv_iic_send_stop; |
242 | sc->sc_i2c.ic_initiate_xfer = cxdtv_iic_initiate_xfer; |
243 | sc->sc_i2c.ic_read_byte = cxdtv_iic_read_byte; |
244 | sc->sc_i2c.ic_write_byte = cxdtv_iic_write_byte; |
245 | |
246 | #if notyet |
247 | /* enable i2c compatible software mode */ |
248 | val = bus_space_read_4(sc->sc_memt, sc->sc_memh, |
249 | CXDTV_I2C_C_DATACONTROL); |
250 | val = CXDTV_I2C_C_DATACONTROL_SCL | CXDTV_I2C_C_DATACONTROL_SDA; |
251 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
252 | CXDTV_I2C_C_DATACONTROL, val); |
253 | #endif |
254 | |
255 | cxdtv_mpeg_attach(sc); |
256 | |
257 | /* attach other devices to iic(4) */ |
258 | memset(&iba, 0, sizeof(iba)); |
259 | iba.iba_tag = &sc->sc_i2c; |
260 | config_found_ia(self, "i2cbus" , &iba, iicbus_print); |
261 | |
262 | if (!pmf_device_register(self, NULL, cxdtv_resume)) |
263 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
264 | |
265 | return; |
266 | } |
267 | |
268 | static int |
269 | cxdtv_detach(device_t self, int flags) |
270 | { |
271 | struct cxdtv_softc *sc = device_private(self); |
272 | int error; |
273 | |
274 | error = cxdtv_mpeg_detach(sc, flags); |
275 | if (error) |
276 | return error; |
277 | |
278 | if (sc->sc_ih) |
279 | pci_intr_disestablish(sc->sc_pc, sc->sc_ih); |
280 | |
281 | if (sc->sc_mems) |
282 | bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); |
283 | |
284 | mutex_destroy(&sc->sc_i2c_buslock); |
285 | |
286 | return 0; |
287 | } |
288 | |
289 | static int |
290 | cxdtv_rescan(device_t self, const char *ifattr, const int *locs) |
291 | { |
292 | struct cxdtv_softc *sc = device_private(self); |
293 | struct dtv_attach_args daa; |
294 | |
295 | daa.hw = &cxdtv_dtv_if; |
296 | daa.priv = sc; |
297 | |
298 | if (ifattr_match(ifattr, "dtvbus" ) && sc->sc_dtvdev == NULL) |
299 | sc->sc_dtvdev = config_found_ia(sc->sc_dev, "dtvbus" , |
300 | &daa, dtv_print); |
301 | |
302 | return 0; |
303 | } |
304 | |
305 | static void |
306 | cxdtv_childdet(device_t self, device_t child) |
307 | { |
308 | struct cxdtv_softc *sc = device_private(self); |
309 | |
310 | if (child == sc->sc_dtvdev) |
311 | sc->sc_dtvdev = NULL; |
312 | } |
313 | |
314 | static bool |
315 | cxdtv_resume(device_t dv, const pmf_qual_t *qual) |
316 | { |
317 | /* XXX revisit */ |
318 | |
319 | aprint_debug_dev(dv, "%s\n" , __func__); |
320 | |
321 | return true; |
322 | } |
323 | |
324 | static int |
325 | cxdtv_intr(void *intarg) |
326 | { |
327 | struct cxdtv_softc *sc = intarg; |
328 | uint32_t val; |
329 | |
330 | val = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MSTAT); |
331 | if (val == 0) { |
332 | return 0; /* not ours */ |
333 | } |
334 | |
335 | if (val & CXT_PI_TS_INT) { |
336 | cxdtv_mpeg_intr(sc); |
337 | } |
338 | |
339 | if (val & ~CXT_PI_TS_INT) { |
340 | device_printf(sc->sc_dev, "%s, %08x\n" , __func__, val); |
341 | } |
342 | |
343 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, val); |
344 | |
345 | return 1; |
346 | } |
347 | |
348 | /* I2C interface */ |
349 | |
350 | static void |
351 | cxdtv_i2cbb_set_bits(void *cookie, uint32_t bits) |
352 | { |
353 | struct cxdtv_softc *sc = cookie; |
354 | |
355 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
356 | CXDTV_I2C_C_DATACONTROL, bits); |
357 | (void)bus_space_read_4(sc->sc_memt, sc->sc_memh, |
358 | CXDTV_I2C_C_DATACONTROL); |
359 | |
360 | return; |
361 | } |
362 | |
363 | static void |
364 | cxdtv_i2cbb_set_dir(void *cookie, uint32_t bits) |
365 | { |
366 | return; |
367 | } |
368 | |
369 | static uint32_t |
370 | cxdtv_i2cbb_read_bits(void *cookie) |
371 | { |
372 | struct cxdtv_softc *sc = cookie; |
373 | uint32_t value; |
374 | |
375 | value = bus_space_read_4(sc->sc_memt, sc->sc_memh, |
376 | CXDTV_I2C_C_DATACONTROL); |
377 | |
378 | return value; |
379 | } |
380 | |
381 | static int |
382 | cxdtv_iic_acquire_bus(void *cookie, int flags) |
383 | { |
384 | struct cxdtv_softc *sc = cookie; |
385 | |
386 | mutex_enter(&sc->sc_i2c_buslock); |
387 | |
388 | return 0; |
389 | } |
390 | |
391 | static void |
392 | cxdtv_iic_release_bus(void *cookie, int flags) |
393 | { |
394 | struct cxdtv_softc *sc = cookie; |
395 | |
396 | mutex_exit(&sc->sc_i2c_buslock); |
397 | |
398 | return; |
399 | } |
400 | |
401 | static int |
402 | cxdtv_iic_send_start(void *cookie, int flags) |
403 | { |
404 | return i2c_bitbang_send_start(cookie, flags, &cxdtv_i2cbb_ops); |
405 | } |
406 | |
407 | static int |
408 | cxdtv_iic_send_stop(void *cookie, int flags) |
409 | { |
410 | return i2c_bitbang_send_stop(cookie, flags, &cxdtv_i2cbb_ops); |
411 | } |
412 | |
413 | static int |
414 | cxdtv_iic_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) |
415 | { |
416 | return i2c_bitbang_initiate_xfer(cookie, addr, flags, &cxdtv_i2cbb_ops); |
417 | } |
418 | |
419 | static int |
420 | cxdtv_iic_read_byte(void *cookie, uint8_t *data, int flags) |
421 | { |
422 | return i2c_bitbang_read_byte(cookie, data, flags, &cxdtv_i2cbb_ops); |
423 | } |
424 | |
425 | static int |
426 | cxdtv_iic_write_byte(void *cookie, uint8_t data, int flags) |
427 | { |
428 | return i2c_bitbang_write_byte(cookie, data, flags, &cxdtv_i2cbb_ops); |
429 | } |
430 | |
431 | int |
432 | cxdtv_mpeg_attach(struct cxdtv_softc *sc) |
433 | { |
434 | struct cxdtv_sram_ch *ch; |
435 | |
436 | CX_DPRINTF(("cxdtv_mpeg_attach\n" )); |
437 | |
438 | ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; |
439 | |
440 | sc->sc_riscbufsz = ch->csc_riscsz; |
441 | sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); |
442 | |
443 | if ( sc->sc_riscbuf == NULL ) |
444 | panic("riscbuf null" ); |
445 | |
446 | aprint_debug_dev(sc->sc_dev, "attaching frontend...\n" ); |
447 | |
448 | switch(sc->sc_vendor) { |
449 | case PCI_VENDOR_ATI: |
450 | cxdtv_card_init_hdtvwonder(sc); |
451 | break; |
452 | case PCI_VENDOR_PCHDTV: |
453 | if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { |
454 | cxdtv_card_init_hd5500(sc); |
455 | } |
456 | break; |
457 | } |
458 | |
459 | KASSERT(sc->sc_tuner == NULL); |
460 | KASSERT(sc->sc_demod == NULL); |
461 | |
462 | switch(sc->sc_board->cb_demod) { |
463 | case CXDTV_DEMOD_NXT2004: |
464 | sc->sc_demod = nxt2k_open(sc->sc_dev, &sc->sc_i2c, 0x0a, 0); |
465 | break; |
466 | case CXDTV_DEMOD_LG3303: |
467 | sc->sc_demod = lg3303_open(sc->sc_dev, &sc->sc_i2c, 0x59, |
468 | LG3303_CFG_SERIAL_INPUT); |
469 | break; |
470 | default: |
471 | break; |
472 | } |
473 | |
474 | switch(sc->sc_board->cb_tuner) { |
475 | case CXDTV_TUNER_PLL: |
476 | if (sc->sc_vendor == PCI_VENDOR_ATI) |
477 | sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tuv1236d_pll); |
478 | if (sc->sc_vendor == PCI_VENDOR_PCHDTV) |
479 | sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tdvs_h06xf_pll); |
480 | break; |
481 | default: |
482 | break; |
483 | } |
484 | |
485 | KASSERT(sc->sc_tuner != NULL); |
486 | KASSERT(sc->sc_demod != NULL); |
487 | |
488 | cxdtv_rescan(sc->sc_dev, NULL, NULL); |
489 | |
490 | return (sc->sc_dtvdev != NULL); |
491 | } |
492 | |
493 | int |
494 | cxdtv_mpeg_detach(struct cxdtv_softc *sc, int flags) |
495 | { |
496 | int error = 0; |
497 | |
498 | if (sc->sc_dtvdev) { |
499 | error = config_detach(sc->sc_dtvdev, flags); |
500 | if (error) |
501 | return error; |
502 | } |
503 | |
504 | if (sc->sc_demod) { |
505 | switch (sc->sc_board->cb_demod) { |
506 | case CXDTV_DEMOD_NXT2004: |
507 | nxt2k_close(sc->sc_demod); |
508 | break; |
509 | case CXDTV_DEMOD_LG3303: |
510 | lg3303_close(sc->sc_demod); |
511 | break; |
512 | default: |
513 | break; |
514 | } |
515 | sc->sc_demod = NULL; |
516 | } |
517 | if (sc->sc_tuner) { |
518 | switch (sc->sc_board->cb_tuner) { |
519 | case CXDTV_TUNER_PLL: |
520 | tvpll_close(sc->sc_tuner); |
521 | break; |
522 | default: |
523 | break; |
524 | } |
525 | sc->sc_tuner = NULL; |
526 | } |
527 | |
528 | if (sc->sc_riscbuf) { |
529 | kmem_free(sc->sc_riscbuf, sc->sc_riscbufsz); |
530 | sc->sc_riscbuf = NULL; |
531 | sc->sc_riscbufsz = 0; |
532 | } |
533 | |
534 | return error; |
535 | } |
536 | |
537 | static void |
538 | cxdtv_dtv_get_devinfo(void *priv, struct dvb_frontend_info *info) |
539 | { |
540 | memset(info, 0, sizeof(*info)); |
541 | strlcpy(info->name, "CX23880" , sizeof(info->name)); |
542 | info->type = FE_ATSC; |
543 | info->frequency_min = 54000000; |
544 | info->frequency_max = 858000000; |
545 | info->frequency_stepsize = 62500; |
546 | info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; |
547 | } |
548 | |
549 | static int |
550 | cxdtv_dtv_open(void *priv, int flags) |
551 | { |
552 | struct cxdtv_softc *sc = priv; |
553 | |
554 | KASSERT(sc->sc_tsbuf == NULL); |
555 | |
556 | cxdtv_mpeg_reset(sc); |
557 | |
558 | /* allocate two alternating DMA areas for MPEG TS packets */ |
559 | sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); |
560 | |
561 | if (sc->sc_tsbuf == NULL) |
562 | return ENOMEM; |
563 | |
564 | return 0; |
565 | } |
566 | |
567 | static void |
568 | cxdtv_dtv_close(void *priv) |
569 | { |
570 | struct cxdtv_softc *sc = priv; |
571 | |
572 | cxdtv_dtv_stop_transfer(sc); |
573 | |
574 | if (sc->sc_tsbuf != NULL) { |
575 | cxdtv_mpeg_free(sc, sc->sc_tsbuf); |
576 | sc->sc_tsbuf = NULL; |
577 | } |
578 | } |
579 | |
580 | static int |
581 | cxdtv_dtv_set_tuner(void *priv, const struct dvb_frontend_parameters *params) |
582 | { |
583 | struct cxdtv_softc *sc = priv; |
584 | int error = -1; |
585 | |
586 | switch(sc->sc_board->cb_tuner) { |
587 | case CXDTV_TUNER_PLL: |
588 | error = tvpll_tune_dtv(sc->sc_tuner, params); |
589 | } |
590 | if (error) |
591 | goto bad; |
592 | |
593 | switch(sc->sc_board->cb_demod) { |
594 | case CXDTV_DEMOD_NXT2004: |
595 | error = nxt2k_set_modulation(sc->sc_demod, params->u.vsb.modulation); |
596 | break; |
597 | case CXDTV_DEMOD_LG3303: |
598 | error = lg3303_set_modulation(sc->sc_demod, params->u.vsb.modulation); |
599 | break; |
600 | default: |
601 | break; |
602 | } |
603 | |
604 | bad: |
605 | return error; |
606 | } |
607 | |
608 | static fe_status_t |
609 | cxdtv_dtv_get_status(void *priv) |
610 | { |
611 | struct cxdtv_softc *sc = priv; |
612 | |
613 | switch(sc->sc_board->cb_demod) { |
614 | case CXDTV_DEMOD_NXT2004: |
615 | return nxt2k_get_dtv_status(sc->sc_demod); |
616 | case CXDTV_DEMOD_LG3303: |
617 | return lg3303_get_dtv_status(sc->sc_demod); |
618 | default: |
619 | return 0; |
620 | } |
621 | } |
622 | |
623 | static uint16_t |
624 | cxdtv_dtv_get_signal_strength(void *priv) |
625 | { |
626 | struct cxdtv_softc *sc = priv; |
627 | |
628 | switch(sc->sc_board->cb_demod) { |
629 | case CXDTV_DEMOD_NXT2004: |
630 | return 0; /* TODO */ |
631 | case CXDTV_DEMOD_LG3303: |
632 | return lg3303_get_signal_strength(sc->sc_demod); |
633 | } |
634 | |
635 | return 0; |
636 | } |
637 | |
638 | static uint16_t |
639 | cxdtv_dtv_get_snr(void *priv) |
640 | { |
641 | struct cxdtv_softc *sc = priv; |
642 | |
643 | switch(sc->sc_board->cb_demod) { |
644 | case CXDTV_DEMOD_NXT2004: |
645 | return 0; /* TODO */ |
646 | case CXDTV_DEMOD_LG3303: |
647 | return lg3303_get_snr(sc->sc_demod); |
648 | } |
649 | |
650 | return 0; |
651 | } |
652 | |
653 | static int |
654 | cxdtv_dtv_start_transfer(void *priv, |
655 | void (*cb)(void *, const struct dtv_payload *), void *arg) |
656 | { |
657 | struct cxdtv_softc *sc = priv; |
658 | |
659 | sc->sc_dtvsubmitcb = cb; |
660 | sc->sc_dtvsubmitarg = arg; |
661 | |
662 | /* allocate two alternating DMA areas for MPEG TS packets */ |
663 | sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); |
664 | |
665 | cxdtv_mpeg_trigger(sc, sc->sc_tsbuf); |
666 | |
667 | return 0; |
668 | } |
669 | |
670 | static int |
671 | cxdtv_dtv_stop_transfer(void *priv) |
672 | { |
673 | struct cxdtv_softc *sc = priv; |
674 | |
675 | cxdtv_mpeg_halt(sc); |
676 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); |
677 | |
678 | sc->sc_dtvsubmitcb = NULL; |
679 | sc->sc_dtvsubmitarg = NULL; |
680 | |
681 | return 0; |
682 | } |
683 | |
684 | int |
685 | cxdtv_mpeg_reset(struct cxdtv_softc *sc) |
686 | { |
687 | uint32_t v; |
688 | |
689 | CX_DPRINTF(("cxdtv_mpeg_reset\n" )); |
690 | |
691 | v = (uint32_t)-1; |
692 | |
693 | /* shutdown */ |
694 | /* hold RISC in reset */ |
695 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 0); |
696 | /* disable FIFO and RISC */ |
697 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 0); |
698 | /* mask off all interrupts */ |
699 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); |
700 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 0); |
701 | |
702 | /* clear interrupts */ |
703 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, v); |
704 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, v); |
705 | |
706 | memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); |
707 | |
708 | /* XXX magic */ |
709 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_STHRSH, 0x0707); |
710 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_DTHRSH, 0x0707); |
711 | |
712 | /* reset external components*/ |
713 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 0); |
714 | kpause("cxdtvrst" , false, MAX(1, mstohz(1)), NULL); |
715 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 1); |
716 | |
717 | /* let error interrupts happen */ |
718 | v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); |
719 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, |
720 | v | 0x00fc00); /* XXX magic */ |
721 | |
722 | return 0; |
723 | } |
724 | |
725 | static int |
726 | cxdtv_risc_buffer(struct cxdtv_softc *sc, uint32_t bpl, uint32_t lines) |
727 | { |
728 | uint32_t *rm; |
729 | uint32_t size; |
730 | |
731 | CX_DPRINTF(("cxdtv_risc_buffer: bpl=0x%x\n" , bpl)); |
732 | |
733 | size = 1 + (bpl * lines) / PAGE_SIZE + lines; |
734 | size += 2; |
735 | |
736 | device_printf(sc->sc_dev, "%s: est. inst. %d\n" , __func__, size); |
737 | |
738 | size *= 8; |
739 | device_printf(sc->sc_dev, "%s: est. qword %d\n" , __func__, size); |
740 | |
741 | if (sc->sc_riscbuf == NULL) { |
742 | device_printf(sc->sc_dev, "not enough memory for RISC\n" ); |
743 | return ENOMEM; |
744 | } |
745 | |
746 | rm = (uint32_t *)sc->sc_riscbuf; |
747 | cxdtv_risc_field(sc, rm, bpl); |
748 | |
749 | return 0; |
750 | } |
751 | |
752 | static int |
753 | cxdtv_risc_field(struct cxdtv_softc *sc, uint32_t *rm, uint32_t bpl) |
754 | { |
755 | struct cxdtv_dma *p; |
756 | |
757 | CX_DPRINTF(("cxdtv_risc_field: bpl=0x%x\n" , bpl)); |
758 | |
759 | for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) |
760 | continue; |
761 | if (p == NULL) { |
762 | device_printf(sc->sc_dev, "cxdtv_risc_field: bad addr %p\n" , |
763 | sc->sc_tsbuf); |
764 | return ENOENT; |
765 | } |
766 | |
767 | memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); |
768 | |
769 | rm = sc->sc_riscbuf; |
770 | |
771 | /* htole32 will be done when program is copied to chip SRAM */ |
772 | |
773 | /* XXX */ |
774 | *(rm++) = (CX_RISC_SYNC|0); |
775 | |
776 | *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); |
777 | *(rm++) = (DMAADDR(p) + 0 * bpl); |
778 | |
779 | *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); |
780 | *(rm++) = (DMAADDR(p) + 1 * bpl); |
781 | |
782 | *(rm++) = (CX_RISC_JUMP|1); |
783 | *(rm++) = (cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG].csc_risc + 4); |
784 | |
785 | return 0; |
786 | } |
787 | |
788 | static int |
789 | cxdtv_sram_ch_setup(struct cxdtv_softc *sc, struct cxdtv_sram_ch *csc, |
790 | uint32_t bpl) |
791 | { |
792 | unsigned int i, lines; |
793 | uint32_t cdt; |
794 | |
795 | CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n" , bpl)); |
796 | |
797 | /* XXX why round? */ |
798 | bpl = (bpl + 7) & ~7; |
799 | CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n" , bpl)); |
800 | cdt = csc->csc_cdt; |
801 | lines = csc->csc_fifosz / bpl; |
802 | device_printf(sc->sc_dev, "%s %d lines\n" , __func__, lines); |
803 | |
804 | /* fill in CDT */ |
805 | for (i = 0; i < lines; i++) { |
806 | CX_DPRINTF(("CDT ent %08x, %08x\n" , cdt + (16 * i), |
807 | csc->csc_fifo + (bpl * i))); |
808 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
809 | cdt + (16 * i), |
810 | csc->csc_fifo + (bpl * i)); |
811 | } |
812 | |
813 | /* copy DMA program */ |
814 | |
815 | /* converts program to little endian as it goes into SRAM */ |
816 | bus_space_write_region_4(sc->sc_memt, sc->sc_memh, |
817 | csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); |
818 | |
819 | /* fill in CMDS */ |
820 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
821 | csc->csc_cmds + CX_CMDS_O_IRPC, csc->csc_risc); |
822 | |
823 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
824 | csc->csc_cmds + CX_CMDS_O_CDTB, csc->csc_cdt); |
825 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
826 | csc->csc_cmds + CX_CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ |
827 | |
828 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
829 | csc->csc_cmds + CX_CMDS_O_IQB, csc->csc_iq); |
830 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
831 | csc->csc_cmds + CX_CMDS_O_IQS, |
832 | CX_CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); |
833 | |
834 | /* zero rest of CMDS */ |
835 | bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x14, 0, 0x2c/4); |
836 | |
837 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
838 | csc->csc_cnt1, (bpl >> 3) - 1); |
839 | |
840 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
841 | csc->csc_ptr2, cdt); |
842 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
843 | csc->csc_cnt2, (lines * 16) >> 3); |
844 | |
845 | return 0; |
846 | } |
847 | |
848 | int |
849 | cxdtv_mpeg_trigger(struct cxdtv_softc *sc, void *buf) |
850 | { |
851 | struct cxdtv_dma *p; |
852 | struct cxdtv_sram_ch *ch; |
853 | uint32_t v; |
854 | |
855 | ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; |
856 | |
857 | for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) |
858 | continue; |
859 | if (p == NULL) { |
860 | device_printf(sc->sc_dev, "cxdtv_mpeg_trigger: bad addr %p\n" , |
861 | buf); |
862 | return ENOENT; |
863 | } |
864 | |
865 | CX_DPRINTF(("cxdtv_mpeg_trigger: buf=%p\n" , buf)); |
866 | |
867 | cxdtv_risc_buffer(sc, CXDTV_TS_PKTSIZE, 1); |
868 | cxdtv_sram_ch_setup(sc, ch, CXDTV_TS_PKTSIZE); |
869 | |
870 | /* software reset */ |
871 | |
872 | switch(sc->sc_vendor) { |
873 | case PCI_VENDOR_ATI: |
874 | /* both ATI boards with DTV are the same */ |
875 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
876 | CXDTV_TS_GEN_CONTROL, IPB_SW_RST); |
877 | delay(100); |
878 | /* parallel MPEG port */ |
879 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
880 | CXDTV_PINMUX_IO, MPEG_PAR_EN); |
881 | break; |
882 | case PCI_VENDOR_PCHDTV: |
883 | if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { |
884 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
885 | CXDTV_TS_GEN_CONTROL, IPB_SW_RST|IPB_SMODE); |
886 | delay(100); |
887 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
888 | CXDTV_PINMUX_IO, 0x00); /* serial MPEG port */ |
889 | /* byte-width start-of-packet */ |
890 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
891 | CXDTV_HW_SOP_CONTROL, |
892 | 0x47 << 16 | 188 << 4 | 1); |
893 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
894 | CXDTV_TS_SOP_STATUS, IPB_SOP_BYTEWIDE); |
895 | /* serial MPEG port on HD5500 */ |
896 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
897 | CXDTV_TS_GEN_CONTROL, IPB_SMODE); |
898 | } |
899 | break; |
900 | default: |
901 | break; |
902 | } |
903 | |
904 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_LNGTH, |
905 | CXDTV_TS_PKTSIZE); |
906 | |
907 | /* Configure for standard MPEG TS, 1 good packet to sync */ |
908 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_HW_SOP_CONTROL, |
909 | 0x47 << 16 | 188 << 4 | 1); |
910 | |
911 | /* zero counter */ |
912 | bus_space_write_4(sc->sc_memt, sc->sc_memh, |
913 | CXDTV_TS_GP_CNT_CNTRL, 0x03); |
914 | |
915 | /* enable bad packet interrupt */ |
916 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_BD_PKT_STATUS, |
917 | 0x1000); |
918 | |
919 | /* enable overflow counter */ |
920 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_FIFO_OVFL_STAT, |
921 | 0x1000); |
922 | |
923 | /* unmask TS interrupt */ |
924 | v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); |
925 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, |
926 | v | CXT_PI_TS_INT); |
927 | |
928 | /* unmask all TS interrupts */ |
929 | v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); |
930 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, |
931 | v | 0x1f1011); |
932 | |
933 | /* enable RISC DMA engine */ |
934 | v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2); |
935 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, |
936 | v | CXDTV_DEV_CNTRL2_RUN_RISC); |
937 | |
938 | v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); |
939 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, |
940 | v | CXDTV_TS_RISC_EN | CXDTV_TS_FIFO_EN); |
941 | |
942 | return 0; |
943 | } |
944 | |
945 | int |
946 | cxdtv_mpeg_halt(struct cxdtv_softc *sc) |
947 | { |
948 | uint32_t v; |
949 | |
950 | CX_DPRINTF(("cxdtv_mpeg_halt\n" )); |
951 | |
952 | v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); |
953 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, |
954 | v & ~(CXDTV_TS_RISC_EN|CXDTV_TS_FIFO_EN)); |
955 | |
956 | v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); |
957 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, |
958 | v & ~CXT_PI_TS_INT); |
959 | |
960 | v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); |
961 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, |
962 | v & ~0x1f1011); |
963 | |
964 | return 0; |
965 | } |
966 | |
967 | int |
968 | cxdtv_mpeg_intr(struct cxdtv_softc *sc) |
969 | { |
970 | struct dtv_payload payload; |
971 | uint32_t s, m; |
972 | |
973 | s = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT); |
974 | m = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); |
975 | if ((s & m) == 0) |
976 | return 0; |
977 | |
978 | if ( (s & ~CXDTV_TS_RISCI) != 0 ) |
979 | device_printf(sc->sc_dev, "unexpected TS IS %08x\n" , s); |
980 | |
981 | if (sc->sc_dtvsubmitcb == NULL) |
982 | goto done; |
983 | |
984 | if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { |
985 | bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, |
986 | 0, CXDTV_TS_PKTSIZE, |
987 | BUS_DMASYNC_POSTREAD); |
988 | payload.data = KERNADDR(sc->sc_dma); |
989 | payload.size = CXDTV_TS_PKTSIZE; |
990 | sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); |
991 | } |
992 | |
993 | if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { |
994 | bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, |
995 | CXDTV_TS_PKTSIZE, CXDTV_TS_PKTSIZE, |
996 | BUS_DMASYNC_POSTREAD); |
997 | payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CXDTV_TS_PKTSIZE; |
998 | payload.size = CXDTV_TS_PKTSIZE; |
999 | sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); |
1000 | } |
1001 | |
1002 | done: |
1003 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, s); |
1004 | |
1005 | return 1; |
1006 | } |
1007 | |
1008 | static int |
1009 | cxdtv_allocmem(struct cxdtv_softc *sc, size_t size, size_t align, |
1010 | struct cxdtv_dma *p) |
1011 | { |
1012 | int err; |
1013 | |
1014 | p->size = size; |
1015 | err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, |
1016 | p->segs, __arraycount(p->segs), |
1017 | &p->nsegs, BUS_DMA_NOWAIT); |
1018 | if (err) |
1019 | return err; |
1020 | err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, |
1021 | &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); |
1022 | if (err) |
1023 | goto free; |
1024 | err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, |
1025 | BUS_DMA_NOWAIT, &p->map); |
1026 | if (err) |
1027 | goto unmap; |
1028 | err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, |
1029 | BUS_DMA_NOWAIT); |
1030 | if (err) |
1031 | goto destroy; |
1032 | |
1033 | return 0; |
1034 | |
1035 | destroy: |
1036 | bus_dmamap_destroy(sc->sc_dmat, p->map); |
1037 | unmap: |
1038 | bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); |
1039 | free: |
1040 | bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); |
1041 | |
1042 | return err; |
1043 | } |
1044 | |
1045 | static int |
1046 | cxdtv_freemem(struct cxdtv_softc *sc, struct cxdtv_dma *p) |
1047 | { |
1048 | |
1049 | bus_dmamap_unload(sc->sc_dmat, p->map); |
1050 | bus_dmamap_destroy(sc->sc_dmat, p->map); |
1051 | bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); |
1052 | bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); |
1053 | |
1054 | return 0; |
1055 | } |
1056 | |
1057 | void * |
1058 | cxdtv_mpeg_malloc(struct cxdtv_softc *sc, size_t size) |
1059 | { |
1060 | struct cxdtv_dma *p; |
1061 | int err; |
1062 | |
1063 | p = kmem_alloc(sizeof(*p), KM_SLEEP); |
1064 | if (p == NULL) { |
1065 | return NULL; |
1066 | } |
1067 | |
1068 | err = cxdtv_allocmem(sc, size, 16, p); |
1069 | if (err) { |
1070 | kmem_free(p, sizeof(*p)); |
1071 | device_printf(sc->sc_dev, "not enough memory\n" ); |
1072 | return NULL; |
1073 | } |
1074 | |
1075 | p->next = sc->sc_dma; |
1076 | sc->sc_dma = p; |
1077 | |
1078 | return KERNADDR(p); |
1079 | } |
1080 | |
1081 | static void |
1082 | cxdtv_mpeg_free(struct cxdtv_softc *sc, void *addr) |
1083 | { |
1084 | struct cxdtv_dma *p; |
1085 | struct cxdtv_dma **pp; |
1086 | |
1087 | for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) { |
1088 | if (KERNADDR(p) == addr) { |
1089 | cxdtv_freemem(sc, p); |
1090 | *pp = p->next; |
1091 | kmem_free(p, sizeof(*p)); |
1092 | return; |
1093 | } |
1094 | } |
1095 | |
1096 | device_printf(sc->sc_dev, "%p is already free\n" , addr); |
1097 | |
1098 | return; |
1099 | } |
1100 | |
1101 | |
1102 | /* ATI HDTV Wonder */ |
1103 | static void |
1104 | cxdtv_card_init_hdtvwonder(struct cxdtv_softc *sc) |
1105 | { |
1106 | int i, x; |
1107 | i2c_addr_t na; |
1108 | uint8_t nb[5][2] = { |
1109 | {0x10, 0x12}, {0x13, 0x04}, {0x16, 0x00}, |
1110 | {0x14, 0x04}, {0x17, 0x00} |
1111 | }; |
1112 | |
1113 | /* prepare TUV1236D/TU1236F NIM */ |
1114 | |
1115 | na = 0x0a; /* Nxt2004 address */ |
1116 | x = 0; |
1117 | |
1118 | iic_acquire_bus(&sc->sc_i2c, I2C_F_POLL); |
1119 | |
1120 | for(i = 0; i < 5; i++) |
1121 | x |= iic_exec(&sc->sc_i2c, I2C_OP_WRITE_WITH_STOP, na, |
1122 | nb[i], 2, NULL, 0, I2C_F_POLL); |
1123 | |
1124 | iic_release_bus(&sc->sc_i2c, I2C_F_POLL); |
1125 | |
1126 | if (x) |
1127 | aprint_error_dev(sc->sc_dev, "HDTV Wonder tuner init failed" ); |
1128 | } |
1129 | |
1130 | /* pcHDTV HD5500 */ |
1131 | #define cxdtv_write_field(_mask, _shift, _value) \ |
1132 | (((_value) & (_mask)) << (_shift)) |
1133 | |
1134 | static void |
1135 | cxdtv_write_gpio(struct cxdtv_softc *sc, uint32_t mask, uint32_t value) |
1136 | { |
1137 | uint32_t v = 0; |
1138 | v |= cxdtv_write_field(0xff, 16, mask); |
1139 | v |= cxdtv_write_field(0xff, 8, mask); |
1140 | v |= cxdtv_write_field(0xff, 0, (mask & value)); |
1141 | bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_GP0_IO, v); |
1142 | } |
1143 | |
1144 | static void |
1145 | cxdtv_card_init_hd5500(struct cxdtv_softc *sc) |
1146 | { |
1147 | /* hardware (demod) reset */ |
1148 | cxdtv_write_gpio(sc, 1, 0); |
1149 | delay(100000); |
1150 | cxdtv_write_gpio(sc, 1, 1); |
1151 | delay(200000); |
1152 | } |
1153 | |
1154 | MODULE(MODULE_CLASS_DRIVER, cxdtv, "tvpll,nxt2k,lg3303,pci" ); |
1155 | |
1156 | #ifdef _MODULE |
1157 | #include "ioconf.c" |
1158 | #endif |
1159 | |
1160 | static int |
1161 | cxdtv_modcmd(modcmd_t cmd, void *opaque) |
1162 | { |
1163 | switch (cmd) { |
1164 | case MODULE_CMD_INIT: |
1165 | #ifdef _MODULE |
1166 | return config_init_component(cfdriver_ioconf_cxdtv, |
1167 | cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); |
1168 | #else |
1169 | return 0; |
1170 | #endif |
1171 | case MODULE_CMD_FINI: |
1172 | #ifdef _MODULE |
1173 | return config_fini_component(cfdriver_ioconf_cxdtv, |
1174 | cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); |
1175 | #else |
1176 | return 0; |
1177 | #endif |
1178 | default: |
1179 | return ENOTTY; |
1180 | } |
1181 | } |
1182 | |