1 | /* $NetBSD: plx9060reg.h,v 1.1 2000/05/17 17:47:00 thorpej Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 2000 Zembu Labs, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * Author: Jason R. Thorpe <thorpej@zembu.com> |
8 | * |
9 | * Redistribution and use in source and binary forms, with or without |
10 | * modification, are permitted provided that the following conditions |
11 | * are met: |
12 | * 1. Redistributions of source code must retain the above copyright |
13 | * notice, this list of conditions and the following disclaimer. |
14 | * 2. Redistributions in binary form must reproduce the above copyright |
15 | * notice, this list of conditions and the following disclaimer in the |
16 | * documentation and/or other materials provided with the distribution. |
17 | * 3. All advertising materials mentioning features or use of this software |
18 | * must display the following acknowledgement: |
19 | * This product includes software developed by Zembu Labs, Inc. |
20 | * 4. Neither the name of Zembu Labs nor the names of its employees may |
21 | * be used to endorse or promote products derived from this software |
22 | * without specific prior written permission. |
23 | * |
24 | * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS |
25 | * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- |
26 | * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- |
27 | * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, |
28 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
29 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
30 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
31 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
33 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
34 | */ |
35 | |
36 | /* |
37 | * Register description for the PLX 9060-family of PCI bus |
38 | * controllers. |
39 | * |
40 | * In order for this file to be really useful to you, you'll want to |
41 | * have the PLX 9060 datasheet in front of you. |
42 | */ |
43 | |
44 | #ifndef _DEV_PCI_PLX9060REG_H_ |
45 | #define _DEV_PCI_PLX9060REG_H_ |
46 | |
47 | /* |
48 | * PLX 9060 PCI configuration space registers. |
49 | */ |
50 | |
51 | #define PLX_PCI_RUNTIME_MEMADDR 0x10 /* memory mapped 9060 */ |
52 | #define PLX_PCI_RUNTIME_IOADDR 0x14 /* i/o mapped 9060 */ |
53 | #define PLX_PCI_LOCAL_ADDR0 0x18 /* PCI address of 9060 local bus */ |
54 | |
55 | /* |
56 | * PLX 9060 Runtime registers, in PCI space. |
57 | */ |
58 | |
59 | /* Local Address Space 0 Range Register */ |
60 | #define PLX_LAS0RR 0x00 |
61 | #define LASRR_IO 0x00000001 |
62 | #define LASRR_MEM_1M 0x00000002 |
63 | #define LASRR_MEM_64BIT 0x00000004 |
64 | #define LASRR_MEM_PREFETCH 0x00000008 |
65 | #define LASRR_MEM_MASK 0xfffffff0 |
66 | #define LASRR_IO_MASK 0xfffffffc |
67 | |
68 | |
69 | /* Local Address Space 0 Local Base Address (remap) Register */ |
70 | #define PLX_LAS0BA 0x04 |
71 | #define LASBA_ENABLE 0x00000001 |
72 | #define LASBA_MEM_MASK 0xfffffff0 |
73 | #define LASBA_IO_MASK 0xfffffffc |
74 | |
75 | |
76 | /* Local Arbitration Register */ |
77 | #define PLX_LAR 0x08 |
78 | #define LAR_LATTMR 0x000000ff |
79 | #define LAR_PAUSETMR 0x0000ff00 |
80 | #define LAR_LATTMR_EN 0x00010000 |
81 | #define LAR_BREQ_EN 0x00040000 |
82 | #define LAR_DSGIVEUP 0x00200000 |
83 | #define LAR_DSLOCK_EN 0x00400000 |
84 | #define LAR_PCI21_MODE 0x01000000 |
85 | |
86 | |
87 | /* Big/Little Endian Register */ |
88 | #define PLX_ENDIAN 0x0c |
89 | #define ENDIAN_CRBE 0x00000001 |
90 | #define ENDIAN_DMBE 0x00000002 |
91 | #define ENDIAN_DSAS0BE 0x00000004 |
92 | #define ENDIAN_DSAERBE 0x00000008 |
93 | #define ENDIAN_BEBL 0x00000010 |
94 | |
95 | |
96 | /* Expansion ROM Range Register */ |
97 | #define PLX_EROMRR 0x10 |
98 | #define EROMRR_MASK 0xffffffc0 |
99 | |
100 | |
101 | /* Expansion ROM Base Address (remap) Register */ |
102 | #define PLX_EROMBA 0x14 |
103 | #define EROMBA_BREQ_DC 0x0000000f |
104 | #define EROMBA_BREQ_EN 0x00000010 |
105 | #define EROMBA_MASK 0xffffffc0 |
106 | |
107 | |
108 | /* Local Bus Region Descriptor for PCI to Local Access Register */ |
109 | #define PLX_LBRD 0x18 |
110 | |
111 | |
112 | /* Local Range for Direct Master to PCI */ |
113 | #define PLX_DMRR 0x1c |
114 | |
115 | |
116 | /* Local Bus Base Address for Direct Master to PCI Memory */ |
117 | #define PLX_DMLBAM 0x20 |
118 | |
119 | |
120 | /* Local Bus Base Address for Direct Master to PCI IO/Config */ |
121 | #define PLX_DMLBAI 0x24 |
122 | |
123 | |
124 | /* PCI Base Address (remap) for Direct Master to PCI Memory */ |
125 | #define PLX_DMBPAM 0x28 |
126 | |
127 | |
128 | /* PCI Base Address (remap) for Direct Master to PCI IO/Config */ |
129 | #define PLX_DMPBAI 0x2c |
130 | |
131 | |
132 | #define PLX_MAILBOX0 0x40 /* Mailbox register 0 */ |
133 | #define PLX_MAILBOX1 0x44 /* Mailbox register 1 */ |
134 | #define PLX_MAILBOX2 0x48 /* Mailbox register 2 */ |
135 | #define PLX_MAILBOX3 0x4c /* Mailbox register 3 */ |
136 | #define PLX_MAILBOX4 0x50 /* Mailbox register 4 (not 9060ES) */ |
137 | #define PLX_MAILBOX5 0x54 /* Mailbox register 5 (not 9060ES) */ |
138 | #define PLX_MAILBOX6 0x58 /* Mailbox register 6 (not 9060ES) */ |
139 | #define PLX_MAILBOX7 0x5c /* Mailbox register 7 (not 9060ES) */ |
140 | |
141 | |
142 | #define PLX_PCI_LOCAL_DOORBELL 0x60 /* PCI -> local doorbell */ |
143 | #define PLX_LOCAL_PCI_DOORBELL 0x64 /* local -> PCI doorbell */ |
144 | |
145 | |
146 | /* Interrupt Control/Status */ |
147 | #define PLX_INTCSR 0x68 |
148 | #define INTCSR_LSERR_TAMA 0x00000001 |
149 | #define INTCSR_LSERR_PA 0x00000002 |
150 | #define INTCSR_SERR 0x00000004 |
151 | #define INTCSR_PCI_EN 0x00000100 |
152 | #define INTCSR_PCIDB_EN 0x00000200 |
153 | #define INTCSR_PCIAB_EN 0x00000400 |
154 | #define INTCSR_PCILOC_EN 0x00000800 |
155 | #define INTCSR_RETRYAB_EN 0x00001000 |
156 | #define INTCSR_PCIDB_INT 0x00002000 |
157 | #define INTCSR_PCIAB_INT 0x00004000 |
158 | #define INTCSR_PCILOC_INT 0x00008000 |
159 | #define INTCSR_LOCOE_EN 0x00010000 |
160 | #define INTCSR_LOCDB_EN 0x00020000 |
161 | #define INTCSR_LOCDB_INT 0x00100000 |
162 | #define INTCSR_BIST_INT 0x00800000 |
163 | #define INTCSR_DMAB_INT 0x01000000 |
164 | #define INTCSR_RETRYAB_INT 0x08000000 |
165 | |
166 | |
167 | /* EEPROM Control, PCI Command Codes, User I/O Control, Init Control */ |
168 | #define PLX_CONTROL 0x6c |
169 | #define CONTROL_PCIMRC 0x00000f00 |
170 | #define CONTROL_PCIMRC_SHIFT 8 |
171 | #define CONTROL_PCIMWC 0x0000f000 |
172 | #define CONTORL_PCIMWC_SHIFT 12 |
173 | #define CONTROL_GPO 0x00010000 |
174 | #define CONTROL_GPI 0x00020000 |
175 | #define CONTROL_EESK 0x01000000 |
176 | #define CONTROL_EECS 0x02000000 |
177 | #define CONTROL_EEDO 0x04000000 /* PLX -> EEPROM */ |
178 | #define CONTROL_EEDI 0x08000000 /* EEPROM -> PLX */ |
179 | #define CONTROL_EEPRESENT 0x10000000 |
180 | #define CONTROL_RELOADCFG 0x20000000 |
181 | #define CONTROL_SWR 0x40000000 |
182 | #define CONTROL_LOCALINIT 0x80000000 |
183 | |
184 | /* EEPROM opcodes */ |
185 | #define PLX_EEPROM_OPC_READ(x) (0x0080 | ((x) & 0x3f)) |
186 | #define PLX_EEPROM_OPC_WRITE(x) (0x0040 | ((x) & 0x3f)) |
187 | #define PLX_EEPROM_OPC_WREN 0x0030 |
188 | #define PLX_EEPROM_OPC_WRPR 0x0000 |
189 | #define PLX_EEPROM_COMMAND(y) (((y) & 0xff) | 0x100) |
190 | |
191 | |
192 | /* PCI Configuration ID */ |
193 | #define PLX_IDREG 0x70 |
194 | |
195 | #endif /* _DEV_PCI_PLX9060REG_H_ */ |
196 | |