1/* $NetBSD: nouveau_subdev_vm_nv41.c,v 1.1.1.1 2014/08/06 12:36:32 riastradh Exp $ */
2
3/*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26
27#include <sys/cdefs.h>
28__KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_vm_nv41.c,v 1.1.1.1 2014/08/06 12:36:32 riastradh Exp $");
29
30#include <core/gpuobj.h>
31#include <core/option.h>
32
33#include <subdev/timer.h>
34#include <subdev/vm.h>
35
36#include "nv04.h"
37
38#define NV41_GART_SIZE (512 * 1024 * 1024)
39#define NV41_GART_PAGE ( 4 * 1024)
40
41/*******************************************************************************
42 * VM map/unmap callbacks
43 ******************************************************************************/
44
45static void
46nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
47 struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
48{
49 pte = pte * 4;
50 while (cnt) {
51 u32 page = PAGE_SIZE / NV41_GART_PAGE;
52 u64 phys = (u64)*list++;
53 while (cnt && page--) {
54 nv_wo32(pgt, pte, (phys >> 7) | 1);
55 phys += NV41_GART_PAGE;
56 pte += 4;
57 cnt -= 1;
58 }
59 }
60}
61
62static void
63nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
64{
65 pte = pte * 4;
66 while (cnt--) {
67 nv_wo32(pgt, pte, 0x00000000);
68 pte += 4;
69 }
70}
71
72static void
73nv41_vm_flush(struct nouveau_vm *vm)
74{
75 struct nv04_vmmgr_priv *priv = (void *)vm->vmm;
76
77 mutex_lock(&nv_subdev(priv)->mutex);
78 nv_wr32(priv, 0x100810, 0x00000022);
79 if (!nv_wait(priv, 0x100810, 0x00000020, 0x00000020)) {
80 nv_warn(priv, "flush timeout, 0x%08x\n",
81 nv_rd32(priv, 0x100810));
82 }
83 nv_wr32(priv, 0x100810, 0x00000000);
84 mutex_unlock(&nv_subdev(priv)->mutex);
85}
86
87/*******************************************************************************
88 * VMMGR subdev
89 ******************************************************************************/
90
91static int
92nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
93 struct nouveau_oclass *oclass, void *data, u32 size,
94 struct nouveau_object **pobject)
95{
96 struct nouveau_device *device = nv_device(parent);
97 struct nv04_vmmgr_priv *priv;
98 int ret;
99
100 if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
101 !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) {
102 return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass,
103 data, size, pobject);
104 }
105
106 ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART",
107 "pciegart", &priv);
108 *pobject = nv_object(priv);
109 if (ret)
110 return ret;
111
112 priv->base.create = nv04_vm_create;
113 priv->base.limit = NV41_GART_SIZE;
114 priv->base.dma_bits = 39;
115 priv->base.pgt_bits = 32 - 12;
116 priv->base.spg_shift = 12;
117 priv->base.lpg_shift = 12;
118 priv->base.map_sg = nv41_vm_map_sg;
119 priv->base.unmap = nv41_vm_unmap;
120 priv->base.flush = nv41_vm_flush;
121
122 ret = nouveau_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096,
123 &priv->vm);
124 if (ret)
125 return ret;
126
127 ret = nouveau_gpuobj_new(nv_object(priv), NULL,
128 (NV41_GART_SIZE / NV41_GART_PAGE) * 4,
129 16, NVOBJ_FLAG_ZERO_ALLOC,
130 &priv->vm->pgt[0].obj[0]);
131 priv->vm->pgt[0].refcount[0] = 1;
132 if (ret)
133 return ret;
134
135 return 0;
136}
137
138static int
139nv41_vmmgr_init(struct nouveau_object *object)
140{
141 struct nv04_vmmgr_priv *priv = (void *)object;
142 struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0];
143 int ret;
144
145 ret = nouveau_vmmgr_init(&priv->base);
146 if (ret)
147 return ret;
148
149 nv_wr32(priv, 0x100800, dma->addr | 0x00000002);
150 nv_mask(priv, 0x10008c, 0x00000100, 0x00000100);
151 nv_wr32(priv, 0x100820, 0x00000000);
152 return 0;
153}
154
155struct nouveau_oclass
156nv41_vmmgr_oclass = {
157 .handle = NV_SUBDEV(VM, 0x41),
158 .ofuncs = &(struct nouveau_ofuncs) {
159 .ctor = nv41_vmmgr_ctor,
160 .dtor = nv04_vmmgr_dtor,
161 .init = nv41_vmmgr_init,
162 .fini = _nouveau_vmmgr_fini,
163 },
164};
165