1/* $NetBSD: nouveau_dispnv04_dfp.c,v 1.1.1.1 2014/08/06 12:36:32 riastradh Exp $ */
2
3/*
4 * Copyright 2003 NVIDIA, Corporation
5 * Copyright 2006 Dave Airlie
6 * Copyright 2007 Maarten Maathuis
7 * Copyright 2007-2009 Stuart Bennett
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: nouveau_dispnv04_dfp.c,v 1.1.1.1 2014/08/06 12:36:32 riastradh Exp $");
31
32#include <drm/drmP.h>
33#include <drm/drm_crtc_helper.h>
34
35#include "nouveau_drm.h"
36#include "nouveau_reg.h"
37#include "nouveau_encoder.h"
38#include "nouveau_connector.h"
39#include "nouveau_crtc.h"
40#include "hw.h"
41#include "nvreg.h"
42
43#include <drm/i2c/sil164.h>
44
45#include <subdev/i2c.h>
46
47#define FP_TG_CONTROL_ON (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | \
48 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | \
49 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
50#define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE | \
51 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE | \
52 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE)
53
54static inline bool is_fpc_off(uint32_t fpc)
55{
56 return ((fpc & (FP_TG_CONTROL_ON | FP_TG_CONTROL_OFF)) ==
57 FP_TG_CONTROL_OFF);
58}
59
60int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent)
61{
62 /* special case of nv_read_tmds to find crtc associated with an output.
63 * this does not give a correct answer for off-chip dvi, but there's no
64 * use for such an answer anyway
65 */
66 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
67
68 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL,
69 NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4);
70 return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac;
71}
72
73void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
74 int head, bool dl)
75{
76 /* The BIOS scripts don't do this for us, sadly
77 * Luckily we do know the values ;-)
78 *
79 * head < 0 indicates we wish to force a setting with the overrideval
80 * (for VT restore etc.)
81 */
82
83 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
84 uint8_t tmds04 = 0x80;
85
86 if (head != ramdac)
87 tmds04 = 0x88;
88
89 if (dcbent->type == DCB_OUTPUT_LVDS)
90 tmds04 |= 0x01;
91
92 nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04);
93
94 if (dl) /* dual link */
95 nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
96}
97
98void nv04_dfp_disable(struct drm_device *dev, int head)
99{
100 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
101
102 if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) &
103 FP_TG_CONTROL_ON) {
104 /* digital remnants must be cleaned before new crtc
105 * values programmed. delay is time for the vga stuff
106 * to realise it's in control again
107 */
108 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
109 FP_TG_CONTROL_OFF);
110 msleep(50);
111 }
112 /* don't inadvertently turn it on when state written later */
113 crtcstate[head].fp_control = FP_TG_CONTROL_OFF;
114 crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &=
115 ~NV_CIO_CRE_LCD_ROUTE_MASK;
116}
117
118void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
119{
120 struct drm_device *dev = encoder->dev;
121 struct drm_crtc *crtc;
122 struct nouveau_crtc *nv_crtc;
123 uint32_t *fpc;
124
125 if (mode == DRM_MODE_DPMS_ON) {
126 nv_crtc = nouveau_crtc(encoder->crtc);
127 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
128
129 if (is_fpc_off(*fpc)) {
130 /* using saved value is ok, as (is_digital && dpms_on &&
131 * fp_control==OFF) is (at present) *only* true when
132 * fpc's most recent change was by below "off" code
133 */
134 *fpc = nv_crtc->dpms_saved_fp_control;
135 }
136
137 nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index;
138 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc);
139 } else {
140 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
141 nv_crtc = nouveau_crtc(crtc);
142 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
143
144 nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index);
145 if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) {
146 nv_crtc->dpms_saved_fp_control = *fpc;
147 /* cut the FP output */
148 *fpc &= ~FP_TG_CONTROL_ON;
149 *fpc |= FP_TG_CONTROL_OFF;
150 NVWriteRAMDAC(dev, nv_crtc->index,
151 NV_PRAMDAC_FP_TG_CONTROL, *fpc);
152 }
153 }
154 }
155}
156
157static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder)
158{
159 struct drm_device *dev = encoder->dev;
160 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
161 struct drm_encoder *slave;
162
163 if (dcb->type != DCB_OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP)
164 return NULL;
165
166 /* Some BIOSes (e.g. the one in a Quadro FX1000) report several
167 * TMDS transmitters at the same I2C address, in the same I2C
168 * bus. This can still work because in that case one of them is
169 * always hard-wired to a reasonable configuration using straps,
170 * and the other one needs to be programmed.
171 *
172 * I don't think there's a way to know which is which, even the
173 * blob programs the one exposed via I2C for *both* heads, so
174 * let's do the same.
175 */
176 list_for_each_entry(slave, &dev->mode_config.encoder_list, head) {
177 struct dcb_output *slave_dcb = nouveau_encoder(slave)->dcb;
178
179 if (slave_dcb->type == DCB_OUTPUT_TMDS && get_slave_funcs(slave) &&
180 slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr)
181 return slave;
182 }
183
184 return NULL;
185}
186
187static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder,
188 const struct drm_display_mode *mode,
189 struct drm_display_mode *adjusted_mode)
190{
191 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
192 struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder);
193
194 if (!nv_connector->native_mode ||
195 nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
196 mode->hdisplay > nv_connector->native_mode->hdisplay ||
197 mode->vdisplay > nv_connector->native_mode->vdisplay) {
198 nv_encoder->mode = *adjusted_mode;
199
200 } else {
201 nv_encoder->mode = *nv_connector->native_mode;
202 adjusted_mode->clock = nv_connector->native_mode->clock;
203 }
204
205 return true;
206}
207
208static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
209 struct nouveau_encoder *nv_encoder, int head)
210{
211 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
212 uint32_t bits1618 = nv_encoder->dcb->or & DCB_OUTPUT_A ? 0x10000 : 0x40000;
213
214 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP)
215 return;
216
217 /* SEL_CLK is only used on the primary ramdac
218 * It toggles spread spectrum PLL output and sets the bindings of PLLs
219 * to heads on digital outputs
220 */
221 if (head)
222 state->sel_clk |= bits1618;
223 else
224 state->sel_clk &= ~bits1618;
225
226 /* nv30:
227 * bit 0 NVClk spread spectrum on/off
228 * bit 2 MemClk spread spectrum on/off
229 * bit 4 PixClk1 spread spectrum on/off toggle
230 * bit 6 PixClk2 spread spectrum on/off toggle
231 *
232 * nv40 (observations from bios behaviour and mmio traces):
233 * bits 4&6 as for nv30
234 * bits 5&7 head dependent as for bits 4&6, but do not appear with 4&6;
235 * maybe a different spread mode
236 * bits 8&10 seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
237 * The logic behind turning spread spectrum on/off in the first place,
238 * and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
239 * entry has the necessary info)
240 */
241 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) {
242 int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;
243
244 state->sel_clk &= ~0xf0;
245 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
246 }
247}
248
249static void nv04_dfp_prepare(struct drm_encoder *encoder)
250{
251 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
252 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
253 struct drm_device *dev = encoder->dev;
254 int head = nouveau_crtc(encoder->crtc)->index;
255 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
256 uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
257 uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX];
258
259 helper->dpms(encoder, DRM_MODE_DPMS_OFF);
260
261 nv04_dfp_prepare_sel_clk(dev, nv_encoder, head);
262
263 *cr_lcd = (*cr_lcd & ~NV_CIO_CRE_LCD_ROUTE_MASK) | 0x3;
264
265 if (nv_two_heads(dev)) {
266 if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)
267 *cr_lcd |= head ? 0x0 : 0x8;
268 else {
269 *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
270 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
271 *cr_lcd |= 0x30;
272 if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
273 /* avoid being connected to both crtcs */
274 *cr_lcd_oth &= ~0x30;
275 NVWriteVgaCrtc(dev, head ^ 1,
276 NV_CIO_CRE_LCD__INDEX,
277 *cr_lcd_oth);
278 }
279 }
280 }
281}
282
283
284static void nv04_dfp_mode_set(struct drm_encoder *encoder,
285 struct drm_display_mode *mode,
286 struct drm_display_mode *adjusted_mode)
287{
288 struct drm_device *dev = encoder->dev;
289 struct nouveau_device *device = nouveau_dev(dev);
290 struct nouveau_drm *drm = nouveau_drm(dev);
291 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
292 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
293 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
294 struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc);
295 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
296 struct drm_display_mode *output_mode = &nv_encoder->mode;
297 struct drm_connector *connector = &nv_connector->base;
298 uint32_t mode_ratio, panel_ratio;
299
300 NV_DEBUG(drm, "Output mode on CRTC %d:\n", nv_crtc->index);
301 drm_mode_debug_printmodeline(output_mode);
302
303 /* Initialize the FP registers in this CRTC. */
304 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
305 regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
306 if (!nv_gf4_disp_arch(dev) ||
307 (output_mode->hsync_start - output_mode->hdisplay) >=
308 drm->vbios.digital_min_front_porch)
309 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
310 else
311 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1;
312 regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
313 regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
314 regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
315 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;
316
317 regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
318 regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
319 regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;
320 regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;
321 regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
322 regp->fp_vert_regs[FP_VALID_START] = 0;
323 regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;
324
325 /* bit26: a bit seen on some g7x, no as yet discernable purpose */
326 regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
327 (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG));
328 /* Deal with vsync/hsync polarity */
329 /* LVDS screens do set this, but modes with +ve syncs are very rare */
330 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
331 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
332 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
333 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
334 /* panel scaling first, as native would get set otherwise */
335 if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
336 nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER) /* panel handles it */
337 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER;
338 else if (adjusted_mode->hdisplay == output_mode->hdisplay &&
339 adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */
340 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
341 else /* gpu needs to scale */
342 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
343 if (nv_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
344 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
345 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
346 output_mode->clock > 165000)
347 regp->fp_control |= (2 << 24);
348 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
349 bool duallink = false, dummy;
350 if (nv_connector->edid &&
351 nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
352 duallink = (((u8 *)nv_connector->edid)[121] == 2);
353 } else {
354 nouveau_bios_parse_lvds_table(dev, output_mode->clock,
355 &duallink, &dummy);
356 }
357
358 if (duallink)
359 regp->fp_control |= (8 << 28);
360 } else
361 if (output_mode->clock > 165000)
362 regp->fp_control |= (8 << 28);
363
364 regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
365 NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
366 NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
367 NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
368 NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
369 NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
370 NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
371
372 /* We want automatic scaling */
373 regp->fp_debug_1 = 0;
374 /* This can override HTOTAL and VTOTAL */
375 regp->fp_debug_2 = 0;
376
377 /* Use 20.12 fixed point format to avoid floats */
378 mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay;
379 panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay;
380 /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
381 * get treated the same as SCALE_FULLSCREEN */
382 if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT &&
383 mode_ratio != panel_ratio) {
384 uint32_t diff, scale;
385 bool divide_by_2 = nv_gf4_disp_arch(dev);
386
387 if (mode_ratio < panel_ratio) {
388 /* vertical needs to expand to glass size (automatic)
389 * horizontal needs to be scaled at vertical scale factor
390 * to maintain aspect */
391
392 scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay;
393 regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE |
394 XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE);
395
396 /* restrict area of screen used, horizontally */
397 diff = output_mode->hdisplay -
398 output_mode->vdisplay * mode_ratio / (1 << 12);
399 regp->fp_horiz_regs[FP_VALID_START] += diff / 2;
400 regp->fp_horiz_regs[FP_VALID_END] -= diff / 2;
401 }
402
403 if (mode_ratio > panel_ratio) {
404 /* horizontal needs to expand to glass size (automatic)
405 * vertical needs to be scaled at horizontal scale factor
406 * to maintain aspect */
407
408 scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay;
409 regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE |
410 XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE);
411
412 /* restrict area of screen used, vertically */
413 diff = output_mode->vdisplay -
414 (1 << 12) * output_mode->hdisplay / mode_ratio;
415 regp->fp_vert_regs[FP_VALID_START] += diff / 2;
416 regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
417 }
418 }
419
420 /* Output property. */
421 if ((nv_connector->dithering_mode == DITHERING_MODE_ON) ||
422 (nv_connector->dithering_mode == DITHERING_MODE_AUTO &&
423 encoder->crtc->primary->fb->depth > connector->display_info.bpc * 3)) {
424 if (nv_device(drm->device)->chipset == 0x11)
425 regp->dither = savep->dither | 0x00010000;
426 else {
427 int i;
428 regp->dither = savep->dither | 0x00000001;
429 for (i = 0; i < 3; i++) {
430 regp->dither_regs[i] = 0xe4e4e4e4;
431 regp->dither_regs[i + 3] = 0x44444444;
432 }
433 }
434 } else {
435 if (nv_device(drm->device)->chipset != 0x11) {
436 /* reset them */
437 int i;
438 for (i = 0; i < 3; i++) {
439 regp->dither_regs[i] = savep->dither_regs[i];
440 regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
441 }
442 }
443 regp->dither = savep->dither;
444 }
445
446 regp->fp_margin_color = 0;
447}
448
449static void nv04_dfp_commit(struct drm_encoder *encoder)
450{
451 struct drm_device *dev = encoder->dev;
452 struct nouveau_drm *drm = nouveau_drm(dev);
453 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
454 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
455 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
456 struct dcb_output *dcbe = nv_encoder->dcb;
457 int head = nouveau_crtc(encoder->crtc)->index;
458 struct drm_encoder *slave_encoder;
459
460 if (dcbe->type == DCB_OUTPUT_TMDS)
461 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
462 else if (dcbe->type == DCB_OUTPUT_LVDS)
463 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
464
465 /* update fp_control state for any changes made by scripts,
466 * so correct value is written at DPMS on */
467 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
468 NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
469
470 /* This could use refinement for flatpanels, but it should work this way */
471 if (nv_device(drm->device)->chipset < 0x44)
472 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
473 else
474 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
475
476 /* Init external transmitters */
477 slave_encoder = get_tmds_slave(encoder);
478 if (slave_encoder)
479 get_slave_funcs(slave_encoder)->mode_set(
480 slave_encoder, &nv_encoder->mode, &nv_encoder->mode);
481
482 helper->dpms(encoder, DRM_MODE_DPMS_ON);
483
484 NV_DEBUG(drm, "Output %s is running on CRTC %d using output %c\n",
485 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
486 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
487}
488
489static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
490{
491#ifdef __powerpc__
492 struct drm_device *dev = encoder->dev;
493 struct nouveau_device *device = nouveau_dev(dev);
494
495 /* BIOS scripts usually take care of the backlight, thanks
496 * Apple for your consistency.
497 */
498 if (dev->pdev->device == 0x0174 || dev->pdev->device == 0x0179 ||
499 dev->pdev->device == 0x0189 || dev->pdev->device == 0x0329) {
500 if (mode == DRM_MODE_DPMS_ON) {
501 nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31);
502 nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 1);
503 } else {
504 nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
505 nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 0);
506 }
507 }
508#endif
509}
510
511static inline bool is_powersaving_dpms(int mode)
512{
513 return mode != DRM_MODE_DPMS_ON && mode != NV_DPMS_CLEARED;
514}
515
516static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
517{
518 struct drm_device *dev = encoder->dev;
519 struct drm_crtc *crtc = encoder->crtc;
520 struct nouveau_drm *drm = nouveau_drm(dev);
521 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
522 bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms);
523
524 if (nv_encoder->last_dpms == mode)
525 return;
526 nv_encoder->last_dpms = mode;
527
528 NV_DEBUG(drm, "Setting dpms mode %d on lvds encoder (output %d)\n",
529 mode, nv_encoder->dcb->index);
530
531 if (was_powersaving && is_powersaving_dpms(mode))
532 return;
533
534 if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
535 /* when removing an output, crtc may not be set, but PANEL_OFF
536 * must still be run
537 */
538 int head = crtc ? nouveau_crtc(crtc)->index :
539 nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
540
541 if (mode == DRM_MODE_DPMS_ON) {
542 call_lvds_script(dev, nv_encoder->dcb, head,
543 LVDS_PANEL_ON, nv_encoder->mode.clock);
544 } else
545 /* pxclk of 0 is fine for PANEL_OFF, and for a
546 * disconnected LVDS encoder there is no native_mode
547 */
548 call_lvds_script(dev, nv_encoder->dcb, head,
549 LVDS_PANEL_OFF, 0);
550 }
551
552 nv04_dfp_update_backlight(encoder, mode);
553 nv04_dfp_update_fp_control(encoder, mode);
554
555 if (mode == DRM_MODE_DPMS_ON)
556 nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index);
557 else {
558 nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
559 nv04_display(dev)->mode_reg.sel_clk &= ~0xf0;
560 }
561 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
562}
563
564static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
565{
566 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
567 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
568
569 if (nv_encoder->last_dpms == mode)
570 return;
571 nv_encoder->last_dpms = mode;
572
573 NV_DEBUG(drm, "Setting dpms mode %d on tmds encoder (output %d)\n",
574 mode, nv_encoder->dcb->index);
575
576 nv04_dfp_update_backlight(encoder, mode);
577 nv04_dfp_update_fp_control(encoder, mode);
578}
579
580static void nv04_dfp_save(struct drm_encoder *encoder)
581{
582 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
583 struct drm_device *dev = encoder->dev;
584
585 if (nv_two_heads(dev))
586 nv_encoder->restore.head =
587 nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
588}
589
590static void nv04_dfp_restore(struct drm_encoder *encoder)
591{
592 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
593 struct drm_device *dev = encoder->dev;
594 int head = nv_encoder->restore.head;
595
596 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
597 struct nouveau_connector *connector =
598 nouveau_encoder_connector_get(nv_encoder);
599
600 if (connector && connector->native_mode)
601 call_lvds_script(dev, nv_encoder->dcb, head,
602 LVDS_PANEL_ON,
603 connector->native_mode->clock);
604
605 } else if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) {
606 int clock = nouveau_hw_pllvals_to_clk
607 (&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals);
608
609 run_tmds_table(dev, nv_encoder->dcb, head, clock);
610 }
611
612 nv_encoder->last_dpms = NV_DPMS_CLEARED;
613}
614
615static void nv04_dfp_destroy(struct drm_encoder *encoder)
616{
617 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
618
619 if (get_slave_funcs(encoder))
620 get_slave_funcs(encoder)->destroy(encoder);
621
622 drm_encoder_cleanup(encoder);
623 kfree(nv_encoder);
624}
625
626static void nv04_tmds_slave_init(struct drm_encoder *encoder)
627{
628 struct drm_device *dev = encoder->dev;
629 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
630 struct nouveau_drm *drm = nouveau_drm(dev);
631 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
632 struct nouveau_i2c_port *port = i2c->find(i2c, 2);
633 struct nouveau_i2c_board_info info[] = {
634 {
635 {
636 .type = "sil164",
637 .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38),
638 .platform_data = &(struct sil164_encoder_params) {
639 SIL164_INPUT_EDGE_RISING
640 }
641 }, 0
642 },
643 { }
644 };
645 int type;
646
647 if (!nv_gf4_disp_arch(dev) || !port ||
648 get_tmds_slave(encoder))
649 return;
650
651 type = i2c->identify(i2c, 2, "TMDS transmitter", info, NULL, NULL);
652 if (type < 0)
653 return;
654
655 drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
656 &port->adapter, &info[type].dev);
657}
658
659static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
660 .dpms = nv04_lvds_dpms,
661 .save = nv04_dfp_save,
662 .restore = nv04_dfp_restore,
663 .mode_fixup = nv04_dfp_mode_fixup,
664 .prepare = nv04_dfp_prepare,
665 .commit = nv04_dfp_commit,
666 .mode_set = nv04_dfp_mode_set,
667 .detect = NULL,
668};
669
670static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs = {
671 .dpms = nv04_tmds_dpms,
672 .save = nv04_dfp_save,
673 .restore = nv04_dfp_restore,
674 .mode_fixup = nv04_dfp_mode_fixup,
675 .prepare = nv04_dfp_prepare,
676 .commit = nv04_dfp_commit,
677 .mode_set = nv04_dfp_mode_set,
678 .detect = NULL,
679};
680
681static const struct drm_encoder_funcs nv04_dfp_funcs = {
682 .destroy = nv04_dfp_destroy,
683};
684
685int
686nv04_dfp_create(struct drm_connector *connector, struct dcb_output *entry)
687{
688 const struct drm_encoder_helper_funcs *helper;
689 struct nouveau_encoder *nv_encoder = NULL;
690 struct drm_encoder *encoder;
691 int type;
692
693 switch (entry->type) {
694 case DCB_OUTPUT_TMDS:
695 type = DRM_MODE_ENCODER_TMDS;
696 helper = &nv04_tmds_helper_funcs;
697 break;
698 case DCB_OUTPUT_LVDS:
699 type = DRM_MODE_ENCODER_LVDS;
700 helper = &nv04_lvds_helper_funcs;
701 break;
702 default:
703 return -EINVAL;
704 }
705
706 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
707 if (!nv_encoder)
708 return -ENOMEM;
709
710 encoder = to_drm_encoder(nv_encoder);
711
712 nv_encoder->dcb = entry;
713 nv_encoder->or = ffs(entry->or) - 1;
714
715 drm_encoder_init(connector->dev, encoder, &nv04_dfp_funcs, type);
716 drm_encoder_helper_add(encoder, helper);
717
718 encoder->possible_crtcs = entry->heads;
719 encoder->possible_clones = 0;
720
721 if (entry->type == DCB_OUTPUT_TMDS &&
722 entry->location != DCB_LOC_ON_CHIP)
723 nv04_tmds_slave_init(encoder);
724
725 drm_mode_connector_attach_encoder(connector, encoder);
726 return 0;
727}
728