1 | /* $NetBSD: ohci_pci.c,v 1.55 2016/04/23 10:15:31 skrll Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1998 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Lennart Augustsson (lennart@augustsson.net) at |
9 | * Carlstedt Research & Technology. |
10 | * |
11 | * Redistribution and use in source and binary forms, with or without |
12 | * modification, are permitted provided that the following conditions |
13 | * are met: |
14 | * 1. Redistributions of source code must retain the above copyright |
15 | * notice, this list of conditions and the following disclaimer. |
16 | * 2. Redistributions in binary form must reproduce the above copyright |
17 | * notice, this list of conditions and the following disclaimer in the |
18 | * documentation and/or other materials provided with the distribution. |
19 | * |
20 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
21 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
22 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
23 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
24 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
30 | * POSSIBILITY OF SUCH DAMAGE. |
31 | */ |
32 | |
33 | #include <sys/cdefs.h> |
34 | __KERNEL_RCSID(0, "$NetBSD: ohci_pci.c,v 1.55 2016/04/23 10:15:31 skrll Exp $" ); |
35 | |
36 | #include "ehci.h" |
37 | |
38 | #include <sys/param.h> |
39 | #include <sys/systm.h> |
40 | #include <sys/kernel.h> |
41 | #include <sys/device.h> |
42 | #include <sys/proc.h> |
43 | #include <sys/queue.h> |
44 | |
45 | #include <sys/bus.h> |
46 | |
47 | #include <dev/pci/pcivar.h> |
48 | #include <dev/pci/pcidevs.h> |
49 | #include <dev/pci/usb_pci.h> |
50 | |
51 | #include <dev/usb/usb.h> |
52 | #include <dev/usb/usbdi.h> |
53 | #include <dev/usb/usbdivar.h> |
54 | #include <dev/usb/usb_mem.h> |
55 | |
56 | #include <dev/usb/ohcireg.h> |
57 | #include <dev/usb/ohcivar.h> |
58 | |
59 | struct ohci_pci_softc { |
60 | ohci_softc_t sc; |
61 | #if NEHCI > 0 |
62 | struct usb_pci sc_pci; |
63 | #endif |
64 | pci_chipset_tag_t sc_pc; |
65 | pcitag_t sc_tag; |
66 | void *sc_ih; /* interrupt vectoring */ |
67 | }; |
68 | |
69 | static int |
70 | ohci_pci_match(device_t parent, cfdata_t match, void *aux) |
71 | { |
72 | struct pci_attach_args *pa = (struct pci_attach_args *) aux; |
73 | |
74 | if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && |
75 | PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && |
76 | PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_OHCI) |
77 | return 1; |
78 | |
79 | return 0; |
80 | } |
81 | |
82 | static void |
83 | ohci_pci_attach(device_t parent, device_t self, void *aux) |
84 | { |
85 | struct ohci_pci_softc *sc = device_private(self); |
86 | struct pci_attach_args *pa = (struct pci_attach_args *)aux; |
87 | pci_chipset_tag_t pc = pa->pa_pc; |
88 | pcitag_t tag = pa->pa_tag; |
89 | char const *intrstr; |
90 | pci_intr_handle_t ih; |
91 | pcireg_t csr; |
92 | char intrbuf[PCI_INTRSTR_LEN]; |
93 | |
94 | sc->sc.sc_dev = self; |
95 | sc->sc.sc_bus.ub_hcpriv = sc; |
96 | |
97 | if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && |
98 | PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_USB) { |
99 | sc->sc.sc_flags = OHCIF_SUPERIO; |
100 | } |
101 | |
102 | pci_aprint_devinfo(pa, "USB Controller" ); |
103 | |
104 | /* check if memory space access is enabled */ |
105 | csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); |
106 | #ifdef DEBUG |
107 | printf("csr: %08x\n" , csr); |
108 | #endif |
109 | if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { |
110 | aprint_error_dev(self, "memory access is disabled\n" ); |
111 | return; |
112 | } |
113 | |
114 | /* Map I/O registers */ |
115 | if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, |
116 | &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { |
117 | sc->sc.sc_size = 0; |
118 | aprint_error_dev(self, "can't map mem space\n" ); |
119 | return; |
120 | } |
121 | |
122 | /* Disable interrupts, so we don't get any spurious ones. */ |
123 | bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE, |
124 | OHCI_ALL_INTRS); |
125 | |
126 | sc->sc_pc = pc; |
127 | sc->sc_tag = tag; |
128 | sc->sc.sc_bus.ub_dmatag = pa->pa_dmat; |
129 | |
130 | /* Enable the device. */ |
131 | pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, |
132 | csr | PCI_COMMAND_MASTER_ENABLE); |
133 | |
134 | /* Map and establish the interrupt. */ |
135 | if (pci_intr_map(pa, &ih)) { |
136 | aprint_error_dev(self, "couldn't map interrupt\n" ); |
137 | goto fail; |
138 | } |
139 | |
140 | /* |
141 | * Allocate IRQ |
142 | */ |
143 | intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); |
144 | sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ohci_intr, sc); |
145 | if (sc->sc_ih == NULL) { |
146 | aprint_error_dev(self, "couldn't establish interrupt" ); |
147 | if (intrstr != NULL) |
148 | aprint_error(" at %s" , intrstr); |
149 | aprint_error("\n" ); |
150 | goto fail; |
151 | } |
152 | aprint_normal_dev(self, "interrupting at %s\n" , intrstr); |
153 | |
154 | /* Figure out vendor for root hub descriptor. */ |
155 | sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); |
156 | pci_findvendor(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), |
157 | sc->sc.sc_id_vendor); |
158 | int err = ohci_init(&sc->sc); |
159 | if (err) { |
160 | aprint_error_dev(self, "init failed, error=%d\n" , err); |
161 | goto fail; |
162 | } |
163 | |
164 | #if NEHCI > 0 |
165 | usb_pci_add(&sc->sc_pci, pa, self); |
166 | #endif |
167 | |
168 | if (!pmf_device_register1(self, ohci_suspend, ohci_resume, |
169 | ohci_shutdown)) |
170 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
171 | |
172 | /* Attach usb device. */ |
173 | sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); |
174 | return; |
175 | |
176 | fail: |
177 | if (sc->sc_ih) { |
178 | pci_intr_disestablish(sc->sc_pc, sc->sc_ih); |
179 | sc->sc_ih = NULL; |
180 | } |
181 | if (sc->sc.sc_size) { |
182 | bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); |
183 | sc->sc.sc_size = 0; |
184 | } |
185 | return; |
186 | } |
187 | |
188 | static int |
189 | ohci_pci_detach(device_t self, int flags) |
190 | { |
191 | struct ohci_pci_softc *sc = device_private(self); |
192 | int rv; |
193 | |
194 | rv = ohci_detach(&sc->sc, flags); |
195 | if (rv) |
196 | return rv; |
197 | |
198 | pmf_device_deregister(self); |
199 | |
200 | ohci_shutdown(self, flags); |
201 | |
202 | if (sc->sc.sc_size) { |
203 | /* Disable interrupts, so we don't get any spurious ones. */ |
204 | bus_space_write_4(sc->sc.iot, sc->sc.ioh, |
205 | OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); |
206 | } |
207 | |
208 | if (sc->sc_ih != NULL) { |
209 | pci_intr_disestablish(sc->sc_pc, sc->sc_ih); |
210 | sc->sc_ih = NULL; |
211 | } |
212 | if (sc->sc.sc_size) { |
213 | bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); |
214 | sc->sc.sc_size = 0; |
215 | } |
216 | #if NEHCI > 0 |
217 | usb_pci_rem(&sc->sc_pci); |
218 | #endif |
219 | return 0; |
220 | } |
221 | |
222 | CFATTACH_DECL3_NEW(ohci_pci, sizeof(struct ohci_pci_softc), |
223 | ohci_pci_match, ohci_pci_attach, ohci_pci_detach, ohci_activate, NULL, |
224 | ohci_childdet, DVF_DETACH_SHUTDOWN); |
225 | |