1 | /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- |
2 | * |
3 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. |
5 | * All rights reserved. |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a |
8 | * copy of this software and associated documentation files (the "Software"), |
9 | * to deal in the Software without restriction, including without limitation |
10 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
11 | * and/or sell copies of the Software, and to permit persons to whom the |
12 | * Software is furnished to do so, subject to the following conditions: |
13 | * |
14 | * The above copyright notice and this permission notice (including the next |
15 | * paragraph) shall be included in all copies or substantial portions of the |
16 | * Software. |
17 | * |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
21 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
24 | * DEALINGS IN THE SOFTWARE. |
25 | * |
26 | * Authors: |
27 | * Kevin E. Martin <martin@valinux.com> |
28 | * Gareth Hughes <gareth@valinux.com> |
29 | */ |
30 | |
31 | #ifndef __RADEON_DRV_H__ |
32 | #define __RADEON_DRV_H__ |
33 | |
34 | #include <linux/firmware.h> |
35 | #include <linux/platform_device.h> |
36 | |
37 | #include "radeon_family.h" |
38 | |
39 | /* General customization: |
40 | */ |
41 | |
42 | #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." |
43 | |
44 | #define DRIVER_NAME "radeon" |
45 | #define DRIVER_DESC "ATI Radeon" |
46 | #define DRIVER_DATE "20080528" |
47 | |
48 | /* Interface history: |
49 | * |
50 | * 1.1 - ?? |
51 | * 1.2 - Add vertex2 ioctl (keith) |
52 | * - Add stencil capability to clear ioctl (gareth, keith) |
53 | * - Increase MAX_TEXTURE_LEVELS (brian) |
54 | * 1.3 - Add cmdbuf ioctl (keith) |
55 | * - Add support for new radeon packets (keith) |
56 | * - Add getparam ioctl (keith) |
57 | * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). |
58 | * 1.4 - Add scratch registers to get_param ioctl. |
59 | * 1.5 - Add r200 packets to cmdbuf ioctl |
60 | * - Add r200 function to init ioctl |
61 | * - Add 'scalar2' instruction to cmdbuf |
62 | * 1.6 - Add static GART memory manager |
63 | * Add irq handler (won't be turned on unless X server knows to) |
64 | * Add irq ioctls and irq_active getparam. |
65 | * Add wait command for cmdbuf ioctl |
66 | * Add GART offset query for getparam |
67 | * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] |
68 | * and R200_PP_CUBIC_OFFSET_F1_[0..5]. |
69 | * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and |
70 | * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) |
71 | * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) |
72 | * Add 'GET' queries for starting additional clients on different VT's. |
73 | * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. |
74 | * Add texture rectangle support for r100. |
75 | * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which |
76 | * clients use to tell the DRM where they think the framebuffer is |
77 | * located in the card's address space |
78 | * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color |
79 | * and GL_EXT_blend_[func|equation]_separate on r200 |
80 | * 1.12- Add R300 CP microcode support - this just loads the CP on r300 |
81 | * (No 3D support yet - just microcode loading). |
82 | * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters |
83 | * - Add hyperz support, add hyperz flags to clear ioctl. |
84 | * 1.14- Add support for color tiling |
85 | * - Add R100/R200 surface allocation/free support |
86 | * 1.15- Add support for texture micro tiling |
87 | * - Add support for r100 cube maps |
88 | * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear |
89 | * texture filtering on r200 |
90 | * 1.17- Add initial support for R300 (3D). |
91 | * 1.18- Add support for GL_ATI_fragment_shader, new packets |
92 | * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces |
93 | * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR |
94 | * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) |
95 | * 1.19- Add support for gart table in FB memory and PCIE r300 |
96 | * 1.20- Add support for r300 texrect |
97 | * 1.21- Add support for card type getparam |
98 | * 1.22- Add support for texture cache flushes (R300_TX_CNTL) |
99 | * 1.23- Add new radeon memory map work from benh |
100 | * 1.24- Add general-purpose packet for manipulating scratch registers (r300) |
101 | * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, |
102 | * new packet type) |
103 | * 1.26- Add support for variable size PCI(E) gart aperture |
104 | * 1.27- Add support for IGP GART |
105 | * 1.28- Add support for VBL on CRTC2 |
106 | * 1.29- R500 3D cmd buffer support |
107 | * 1.30- Add support for occlusion queries |
108 | * 1.31- Add support for num Z pipes from GET_PARAM |
109 | * 1.32- fixes for rv740 setup |
110 | * 1.33- Add r6xx/r7xx const buffer support |
111 | * 1.34- fix evergreen/cayman GS register |
112 | */ |
113 | #define DRIVER_MAJOR 1 |
114 | #define DRIVER_MINOR 34 |
115 | #define DRIVER_PATCHLEVEL 0 |
116 | |
117 | long radeon_drm_ioctl(struct file *filp, |
118 | unsigned int cmd, unsigned long arg); |
119 | |
120 | /* The rest of the file is DEPRECATED! */ |
121 | #ifdef CONFIG_DRM_RADEON_UMS |
122 | |
123 | enum radeon_cp_microcode_version { |
124 | UCODE_R100, |
125 | UCODE_R200, |
126 | UCODE_R300, |
127 | }; |
128 | |
129 | typedef struct drm_radeon_freelist { |
130 | unsigned int age; |
131 | struct drm_buf *buf; |
132 | struct drm_radeon_freelist *next; |
133 | struct drm_radeon_freelist *prev; |
134 | } drm_radeon_freelist_t; |
135 | |
136 | typedef struct drm_radeon_ring_buffer { |
137 | u32 *start; |
138 | u32 *end; |
139 | int size; |
140 | int size_l2qw; |
141 | |
142 | int rptr_update; /* Double Words */ |
143 | int rptr_update_l2qw; /* log2 Quad Words */ |
144 | |
145 | int fetch_size; /* Double Words */ |
146 | int fetch_size_l2ow; /* log2 Oct Words */ |
147 | |
148 | u32 tail; |
149 | u32 tail_mask; |
150 | int space; |
151 | |
152 | int high_mark; |
153 | } drm_radeon_ring_buffer_t; |
154 | |
155 | typedef struct drm_radeon_depth_clear_t { |
156 | u32 rb3d_cntl; |
157 | u32 rb3d_zstencilcntl; |
158 | u32 se_cntl; |
159 | } drm_radeon_depth_clear_t; |
160 | |
161 | struct drm_radeon_driver_file_fields { |
162 | int64_t radeon_fb_delta; |
163 | }; |
164 | |
165 | struct mem_block { |
166 | struct mem_block *next; |
167 | struct mem_block *prev; |
168 | int start; |
169 | int size; |
170 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
171 | }; |
172 | |
173 | struct radeon_surface { |
174 | int refcount; |
175 | u32 lower; |
176 | u32 upper; |
177 | u32 flags; |
178 | }; |
179 | |
180 | struct radeon_virt_surface { |
181 | int surface_index; |
182 | u32 lower; |
183 | u32 upper; |
184 | u32 flags; |
185 | struct drm_file *file_priv; |
186 | #define PCIGART_FILE_PRIV ((void *) -1L) |
187 | }; |
188 | |
189 | #define RADEON_FLUSH_EMITED (1 << 0) |
190 | #define RADEON_PURGE_EMITED (1 << 1) |
191 | |
192 | struct drm_radeon_master_private { |
193 | drm_local_map_t *sarea; |
194 | drm_radeon_sarea_t *sarea_priv; |
195 | }; |
196 | |
197 | typedef struct drm_radeon_private { |
198 | drm_radeon_ring_buffer_t ring; |
199 | |
200 | u32 fb_location; |
201 | u32 fb_size; |
202 | int new_memmap; |
203 | |
204 | int gart_size; |
205 | u32 gart_vm_start; |
206 | unsigned long gart_buffers_offset; |
207 | |
208 | int cp_mode; |
209 | int cp_running; |
210 | |
211 | drm_radeon_freelist_t *head; |
212 | drm_radeon_freelist_t *tail; |
213 | int last_buf; |
214 | int writeback_works; |
215 | |
216 | int usec_timeout; |
217 | |
218 | int microcode_version; |
219 | |
220 | struct { |
221 | u32 boxes; |
222 | int freelist_timeouts; |
223 | int freelist_loops; |
224 | int requested_bufs; |
225 | int last_frame_reads; |
226 | int last_clear_reads; |
227 | int clears; |
228 | int texture_uploads; |
229 | } stats; |
230 | |
231 | int do_boxes; |
232 | int page_flipping; |
233 | |
234 | u32 color_fmt; |
235 | unsigned int front_offset; |
236 | unsigned int front_pitch; |
237 | unsigned int back_offset; |
238 | unsigned int back_pitch; |
239 | |
240 | u32 depth_fmt; |
241 | unsigned int depth_offset; |
242 | unsigned int depth_pitch; |
243 | |
244 | u32 front_pitch_offset; |
245 | u32 back_pitch_offset; |
246 | u32 depth_pitch_offset; |
247 | |
248 | drm_radeon_depth_clear_t depth_clear; |
249 | |
250 | unsigned long ring_offset; |
251 | unsigned long ring_rptr_offset; |
252 | unsigned long buffers_offset; |
253 | unsigned long gart_textures_offset; |
254 | |
255 | drm_local_map_t *sarea; |
256 | drm_local_map_t *cp_ring; |
257 | drm_local_map_t *ring_rptr; |
258 | drm_local_map_t *gart_textures; |
259 | |
260 | struct mem_block *gart_heap; |
261 | struct mem_block *fb_heap; |
262 | |
263 | /* SW interrupt */ |
264 | wait_queue_head_t swi_queue; |
265 | atomic_t swi_emitted; |
266 | int vblank_crtc; |
267 | uint32_t irq_enable_reg; |
268 | uint32_t r500_disp_irq_reg; |
269 | |
270 | struct radeon_surface surfaces[RADEON_MAX_SURFACES]; |
271 | struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; |
272 | |
273 | unsigned long pcigart_offset; |
274 | unsigned int pcigart_offset_set; |
275 | struct drm_ati_pcigart_info gart_info; |
276 | |
277 | u32 scratch_ages[5]; |
278 | |
279 | int have_z_offset; |
280 | |
281 | /* starting from here on, data is preserved across an open */ |
282 | uint32_t flags; /* see radeon_chip_flags */ |
283 | resource_size_t fb_aper_offset; |
284 | |
285 | int num_gb_pipes; |
286 | int num_z_pipes; |
287 | int track_flush; |
288 | drm_local_map_t *mmio; |
289 | |
290 | /* r6xx/r7xx pipe/shader config */ |
291 | int r600_max_pipes; |
292 | int r600_max_tile_pipes; |
293 | int r600_max_simds; |
294 | int r600_max_backends; |
295 | int r600_max_gprs; |
296 | int r600_max_threads; |
297 | int r600_max_stack_entries; |
298 | int r600_max_hw_contexts; |
299 | int r600_max_gs_threads; |
300 | int r600_sx_max_export_size; |
301 | int r600_sx_max_export_pos_size; |
302 | int r600_sx_max_export_smx_size; |
303 | int r600_sq_num_cf_insts; |
304 | int r700_sx_num_of_sets; |
305 | int r700_sc_prim_fifo_size; |
306 | int r700_sc_hiz_tile_fifo_size; |
307 | int r700_sc_earlyz_tile_fifo_fize; |
308 | int r600_group_size; |
309 | int r600_npipes; |
310 | int r600_nbanks; |
311 | |
312 | struct mutex cs_mutex; |
313 | u32 cs_id_scnt; |
314 | u32 cs_id_wcnt; |
315 | /* r6xx/r7xx drm blit vertex buffer */ |
316 | struct drm_buf *blit_vb; |
317 | |
318 | /* firmware */ |
319 | const struct firmware *me_fw, *pfp_fw; |
320 | } drm_radeon_private_t; |
321 | |
322 | typedef struct drm_radeon_buf_priv { |
323 | u32 age; |
324 | } drm_radeon_buf_priv_t; |
325 | |
326 | struct drm_buffer; |
327 | |
328 | typedef struct drm_radeon_kcmd_buffer { |
329 | int bufsz; |
330 | struct drm_buffer *buffer; |
331 | int nbox; |
332 | struct drm_clip_rect __user *boxes; |
333 | } drm_radeon_kcmd_buffer_t; |
334 | |
335 | extern int radeon_no_wb; |
336 | extern struct drm_ioctl_desc radeon_ioctls[]; |
337 | extern int radeon_max_ioctl; |
338 | |
339 | extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv); |
340 | extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val); |
341 | |
342 | #define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv) |
343 | #define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val) |
344 | |
345 | /* Check whether the given hardware address is inside the framebuffer or the |
346 | * GART area. |
347 | */ |
348 | static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, |
349 | u64 off) |
350 | { |
351 | u32 fb_start = dev_priv->fb_location; |
352 | u32 fb_end = fb_start + dev_priv->fb_size - 1; |
353 | u32 gart_start = dev_priv->gart_vm_start; |
354 | u32 gart_end = gart_start + dev_priv->gart_size - 1; |
355 | |
356 | return ((off >= fb_start && off <= fb_end) || |
357 | (off >= gart_start && off <= gart_end)); |
358 | } |
359 | |
360 | /* radeon_state.c */ |
361 | extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf); |
362 | |
363 | /* radeon_cp.c */ |
364 | extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); |
365 | extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); |
366 | extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); |
367 | extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); |
368 | extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); |
369 | extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); |
370 | extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); |
371 | extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); |
372 | extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); |
373 | extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); |
374 | extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc); |
375 | extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base); |
376 | |
377 | extern void radeon_freelist_reset(struct drm_device * dev); |
378 | extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); |
379 | |
380 | extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); |
381 | |
382 | extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); |
383 | |
384 | extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); |
385 | extern int radeon_presetup(struct drm_device *dev); |
386 | extern int radeon_driver_postcleanup(struct drm_device *dev); |
387 | |
388 | extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); |
389 | extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); |
390 | extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); |
391 | extern void radeon_mem_takedown(struct mem_block **heap); |
392 | extern void radeon_mem_release(struct drm_file *file_priv, |
393 | struct mem_block *heap); |
394 | |
395 | extern void radeon_enable_bm(struct drm_radeon_private *dev_priv); |
396 | extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off); |
397 | extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val); |
398 | |
399 | /* radeon_irq.c */ |
400 | extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); |
401 | extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); |
402 | extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); |
403 | |
404 | extern void radeon_do_release(struct drm_device * dev); |
405 | extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); |
406 | extern int radeon_enable_vblank(struct drm_device *dev, int crtc); |
407 | extern void radeon_disable_vblank(struct drm_device *dev, int crtc); |
408 | extern irqreturn_t radeon_driver_irq_handler(int irq, void *arg); |
409 | extern void radeon_driver_irq_preinstall(struct drm_device * dev); |
410 | extern int radeon_driver_irq_postinstall(struct drm_device *dev); |
411 | extern void radeon_driver_irq_uninstall(struct drm_device * dev); |
412 | extern void radeon_enable_interrupt(struct drm_device *dev); |
413 | extern int radeon_vblank_crtc_get(struct drm_device *dev); |
414 | extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); |
415 | |
416 | extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); |
417 | extern int radeon_driver_unload(struct drm_device *dev); |
418 | extern int radeon_driver_firstopen(struct drm_device *dev); |
419 | extern void radeon_driver_preclose(struct drm_device *dev, |
420 | struct drm_file *file_priv); |
421 | extern void radeon_driver_postclose(struct drm_device *dev, |
422 | struct drm_file *file_priv); |
423 | extern void radeon_driver_lastclose(struct drm_device * dev); |
424 | extern int radeon_driver_open(struct drm_device *dev, |
425 | struct drm_file *file_priv); |
426 | extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, |
427 | unsigned long arg); |
428 | |
429 | extern int radeon_master_create(struct drm_device *dev, struct drm_master *master); |
430 | extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master); |
431 | extern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master); |
432 | /* r300_cmdbuf.c */ |
433 | extern void r300_init_reg_flags(struct drm_device *dev); |
434 | |
435 | extern int r300_do_cp_cmdbuf(struct drm_device *dev, |
436 | struct drm_file *file_priv, |
437 | drm_radeon_kcmd_buffer_t *cmdbuf); |
438 | |
439 | /* r600_cp.c */ |
440 | extern int r600_do_engine_reset(struct drm_device *dev); |
441 | extern int r600_do_cleanup_cp(struct drm_device *dev); |
442 | extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, |
443 | struct drm_file *file_priv); |
444 | extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv); |
445 | extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv); |
446 | extern void r600_do_cp_start(drm_radeon_private_t *dev_priv); |
447 | extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv); |
448 | extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv); |
449 | extern int r600_cp_dispatch_indirect(struct drm_device *dev, |
450 | struct drm_buf *buf, int start, int end); |
451 | extern int r600_page_table_init(struct drm_device *dev); |
452 | extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); |
453 | extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv); |
454 | extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv); |
455 | extern int r600_cp_dispatch_texture(struct drm_device *dev, |
456 | struct drm_file *file_priv, |
457 | drm_radeon_texture_t *tex, |
458 | drm_radeon_tex_image_t *image); |
459 | /* r600_blit.c */ |
460 | extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv); |
461 | extern void r600_done_blit_copy(struct drm_device *dev); |
462 | extern void r600_blit_copy(struct drm_device *dev, |
463 | uint64_t src_gpu_addr, uint64_t dst_gpu_addr, |
464 | int size_bytes); |
465 | extern void r600_blit_swap(struct drm_device *dev, |
466 | uint64_t src_gpu_addr, uint64_t dst_gpu_addr, |
467 | int sx, int sy, int dx, int dy, |
468 | int w, int h, int src_pitch, int dst_pitch, int cpp); |
469 | |
470 | /* Flags for stats.boxes |
471 | */ |
472 | #define RADEON_BOX_DMA_IDLE 0x1 |
473 | #define RADEON_BOX_RING_FULL 0x2 |
474 | #define RADEON_BOX_FLIP 0x4 |
475 | #define RADEON_BOX_WAIT_IDLE 0x8 |
476 | #define RADEON_BOX_TEXTURE_LOAD 0x10 |
477 | |
478 | /* Register definitions, register access macros and drmAddMap constants |
479 | * for Radeon kernel driver. |
480 | */ |
481 | #define RADEON_MM_INDEX 0x0000 |
482 | #define RADEON_MM_DATA 0x0004 |
483 | |
484 | #define RADEON_AGP_COMMAND 0x0f60 |
485 | #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ |
486 | # define RADEON_AGP_ENABLE (1<<8) |
487 | #define RADEON_AUX_SCISSOR_CNTL 0x26f0 |
488 | # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) |
489 | # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) |
490 | # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) |
491 | # define RADEON_SCISSOR_0_ENABLE (1 << 28) |
492 | # define RADEON_SCISSOR_1_ENABLE (1 << 29) |
493 | # define RADEON_SCISSOR_2_ENABLE (1 << 30) |
494 | |
495 | /* |
496 | * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) |
497 | * don't have an explicit bus mastering disable bit. It's handled |
498 | * by the PCI D-states. PMI_BM_DIS disables D-state bus master |
499 | * handling, not bus mastering itself. |
500 | */ |
501 | #define RADEON_BUS_CNTL 0x0030 |
502 | /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ |
503 | # define RADEON_BUS_MASTER_DIS (1 << 6) |
504 | /* rs600/rs690/rs740 */ |
505 | # define RS600_BUS_MASTER_DIS (1 << 14) |
506 | # define RS600_MSI_REARM (1 << 20) |
507 | /* see RS400_MSI_REARM in AIC_CNTL for rs480 */ |
508 | |
509 | #define RADEON_BUS_CNTL1 0x0034 |
510 | # define RADEON_PMI_BM_DIS (1 << 2) |
511 | # define RADEON_PMI_INT_DIS (1 << 3) |
512 | |
513 | #define RV370_BUS_CNTL 0x004c |
514 | # define RV370_PMI_BM_DIS (1 << 5) |
515 | # define RV370_PMI_INT_DIS (1 << 6) |
516 | |
517 | #define RADEON_MSI_REARM_EN 0x0160 |
518 | /* rv370/rv380, rv410, r423/r430/r480, r5xx */ |
519 | # define RV370_MSI_REARM_EN (1 << 0) |
520 | |
521 | #define RADEON_CLOCK_CNTL_DATA 0x000c |
522 | # define RADEON_PLL_WR_EN (1 << 7) |
523 | #define RADEON_CLOCK_CNTL_INDEX 0x0008 |
524 | #define RADEON_CONFIG_APER_SIZE 0x0108 |
525 | #define RADEON_CONFIG_MEMSIZE 0x00f8 |
526 | #define RADEON_CRTC_OFFSET 0x0224 |
527 | #define RADEON_CRTC_OFFSET_CNTL 0x0228 |
528 | # define RADEON_CRTC_TILE_EN (1 << 15) |
529 | # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) |
530 | #define RADEON_CRTC2_OFFSET 0x0324 |
531 | #define RADEON_CRTC2_OFFSET_CNTL 0x0328 |
532 | |
533 | #define RADEON_PCIE_INDEX 0x0030 |
534 | #define RADEON_PCIE_DATA 0x0034 |
535 | #define RADEON_PCIE_TX_GART_CNTL 0x10 |
536 | # define RADEON_PCIE_TX_GART_EN (1 << 0) |
537 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) |
538 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) |
539 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) |
540 | # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) |
541 | # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) |
542 | # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) |
543 | # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) |
544 | #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 |
545 | #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 |
546 | #define RADEON_PCIE_TX_GART_BASE 0x13 |
547 | #define RADEON_PCIE_TX_GART_START_LO 0x14 |
548 | #define RADEON_PCIE_TX_GART_START_HI 0x15 |
549 | #define RADEON_PCIE_TX_GART_END_LO 0x16 |
550 | #define RADEON_PCIE_TX_GART_END_HI 0x17 |
551 | |
552 | #define RS480_NB_MC_INDEX 0x168 |
553 | # define RS480_NB_MC_IND_WR_EN (1 << 8) |
554 | #define RS480_NB_MC_DATA 0x16c |
555 | |
556 | #define RS690_MC_INDEX 0x78 |
557 | # define RS690_MC_INDEX_MASK 0x1ff |
558 | # define RS690_MC_INDEX_WR_EN (1 << 9) |
559 | # define RS690_MC_INDEX_WR_ACK 0x7f |
560 | #define RS690_MC_DATA 0x7c |
561 | |
562 | /* MC indirect registers */ |
563 | #define RS480_MC_MISC_CNTL 0x18 |
564 | # define RS480_DISABLE_GTW (1 << 1) |
565 | /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ |
566 | # define RS480_GART_INDEX_REG_EN (1 << 12) |
567 | # define RS690_BLOCK_GFX_D3_EN (1 << 14) |
568 | #define RS480_K8_FB_LOCATION 0x1e |
569 | #define RS480_GART_FEATURE_ID 0x2b |
570 | # define RS480_HANG_EN (1 << 11) |
571 | # define RS480_TLB_ENABLE (1 << 18) |
572 | # define RS480_P2P_ENABLE (1 << 19) |
573 | # define RS480_GTW_LAC_EN (1 << 25) |
574 | # define RS480_2LEVEL_GART (0 << 30) |
575 | # define RS480_1LEVEL_GART (1 << 30) |
576 | # define RS480_PDC_EN (1 << 31) |
577 | #define RS480_GART_BASE 0x2c |
578 | #define RS480_GART_CACHE_CNTRL 0x2e |
579 | # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ |
580 | #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 |
581 | # define RS480_GART_EN (1 << 0) |
582 | # define RS480_VA_SIZE_32MB (0 << 1) |
583 | # define RS480_VA_SIZE_64MB (1 << 1) |
584 | # define RS480_VA_SIZE_128MB (2 << 1) |
585 | # define RS480_VA_SIZE_256MB (3 << 1) |
586 | # define RS480_VA_SIZE_512MB (4 << 1) |
587 | # define RS480_VA_SIZE_1GB (5 << 1) |
588 | # define RS480_VA_SIZE_2GB (6 << 1) |
589 | #define RS480_AGP_MODE_CNTL 0x39 |
590 | # define RS480_POST_GART_Q_SIZE (1 << 18) |
591 | # define RS480_NONGART_SNOOP (1 << 19) |
592 | # define RS480_AGP_RD_BUF_SIZE (1 << 20) |
593 | # define RS480_REQ_TYPE_SNOOP_SHIFT 22 |
594 | # define RS480_REQ_TYPE_SNOOP_MASK 0x3 |
595 | # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) |
596 | #define RS480_MC_MISC_UMA_CNTL 0x5f |
597 | #define RS480_MC_MCLK_CNTL 0x7a |
598 | #define RS480_MC_UMA_DUALCH_CNTL 0x86 |
599 | |
600 | #define RS690_MC_FB_LOCATION 0x100 |
601 | #define RS690_MC_AGP_LOCATION 0x101 |
602 | #define RS690_MC_AGP_BASE 0x102 |
603 | #define RS690_MC_AGP_BASE_2 0x103 |
604 | |
605 | #define RS600_MC_INDEX 0x70 |
606 | # define RS600_MC_ADDR_MASK 0xffff |
607 | # define RS600_MC_IND_SEQ_RBS_0 (1 << 16) |
608 | # define RS600_MC_IND_SEQ_RBS_1 (1 << 17) |
609 | # define RS600_MC_IND_SEQ_RBS_2 (1 << 18) |
610 | # define RS600_MC_IND_SEQ_RBS_3 (1 << 19) |
611 | # define RS600_MC_IND_AIC_RBS (1 << 20) |
612 | # define RS600_MC_IND_CITF_ARB0 (1 << 21) |
613 | # define RS600_MC_IND_CITF_ARB1 (1 << 22) |
614 | # define RS600_MC_IND_WR_EN (1 << 23) |
615 | #define RS600_MC_DATA 0x74 |
616 | |
617 | #define RS600_MC_STATUS 0x0 |
618 | # define RS600_MC_IDLE (1 << 1) |
619 | #define RS600_MC_FB_LOCATION 0x4 |
620 | #define RS600_MC_AGP_LOCATION 0x5 |
621 | #define RS600_AGP_BASE 0x6 |
622 | #define RS600_AGP_BASE_2 0x7 |
623 | #define RS600_MC_CNTL1 0x9 |
624 | # define RS600_ENABLE_PAGE_TABLES (1 << 26) |
625 | #define RS600_MC_PT0_CNTL 0x100 |
626 | # define RS600_ENABLE_PT (1 << 0) |
627 | # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) |
628 | # define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) |
629 | # define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) |
630 | # define RS600_INVALIDATE_L2_CACHE (1 << 29) |
631 | #define RS600_MC_PT0_CONTEXT0_CNTL 0x102 |
632 | # define RS600_ENABLE_PAGE_TABLE (1 << 0) |
633 | # define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) |
634 | #define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 |
635 | #define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 |
636 | #define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c |
637 | #define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c |
638 | #define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c |
639 | #define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c |
640 | #define RS600_MC_PT0_CLIENT0_CNTL 0x16c |
641 | # define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) |
642 | # define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) |
643 | # define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) |
644 | # define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) |
645 | # define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) |
646 | # define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) |
647 | # define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) |
648 | # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) |
649 | # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) |
650 | # define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) |
651 | # define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) |
652 | # define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) |
653 | # define RS600_INVALIDATE_L1_TLB (1 << 20) |
654 | |
655 | #define R520_MC_IND_INDEX 0x70 |
656 | #define R520_MC_IND_WR_EN (1 << 24) |
657 | #define R520_MC_IND_DATA 0x74 |
658 | |
659 | #define RV515_MC_FB_LOCATION 0x01 |
660 | #define RV515_MC_AGP_LOCATION 0x02 |
661 | #define RV515_MC_AGP_BASE 0x03 |
662 | #define RV515_MC_AGP_BASE_2 0x04 |
663 | |
664 | #define R520_MC_FB_LOCATION 0x04 |
665 | #define R520_MC_AGP_LOCATION 0x05 |
666 | #define R520_MC_AGP_BASE 0x06 |
667 | #define R520_MC_AGP_BASE_2 0x07 |
668 | |
669 | #define RADEON_MPP_TB_CONFIG 0x01c0 |
670 | #define RADEON_MEM_CNTL 0x0140 |
671 | #define RADEON_MEM_SDRAM_MODE_REG 0x0158 |
672 | #define RADEON_AGP_BASE_2 0x015c /* r200+ only */ |
673 | #define RS480_AGP_BASE_2 0x0164 |
674 | #define RADEON_AGP_BASE 0x0170 |
675 | |
676 | /* pipe config regs */ |
677 | #define R400_GB_PIPE_SELECT 0x402c |
678 | #define RV530_GB_PIPE_SELECT2 0x4124 |
679 | #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ |
680 | #define R300_GB_TILE_CONFIG 0x4018 |
681 | # define R300_ENABLE_TILING (1 << 0) |
682 | # define R300_PIPE_COUNT_RV350 (0 << 1) |
683 | # define R300_PIPE_COUNT_R300 (3 << 1) |
684 | # define R300_PIPE_COUNT_R420_3P (6 << 1) |
685 | # define R300_PIPE_COUNT_R420 (7 << 1) |
686 | # define R300_TILE_SIZE_8 (0 << 4) |
687 | # define R300_TILE_SIZE_16 (1 << 4) |
688 | # define R300_TILE_SIZE_32 (2 << 4) |
689 | # define R300_SUBPIXEL_1_12 (0 << 16) |
690 | # define R300_SUBPIXEL_1_16 (1 << 16) |
691 | #define R300_DST_PIPE_CONFIG 0x170c |
692 | # define R300_PIPE_AUTO_CONFIG (1 << 31) |
693 | #define R300_RB2D_DSTCACHE_MODE 0x3428 |
694 | # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) |
695 | # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) |
696 | |
697 | #define RADEON_RB3D_COLOROFFSET 0x1c40 |
698 | #define RADEON_RB3D_COLORPITCH 0x1c48 |
699 | |
700 | #define RADEON_SRC_X_Y 0x1590 |
701 | |
702 | #define RADEON_DP_GUI_MASTER_CNTL 0x146c |
703 | # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) |
704 | # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) |
705 | # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) |
706 | # define RADEON_GMC_BRUSH_NONE (15 << 4) |
707 | # define RADEON_GMC_DST_16BPP (4 << 8) |
708 | # define RADEON_GMC_DST_24BPP (5 << 8) |
709 | # define RADEON_GMC_DST_32BPP (6 << 8) |
710 | # define RADEON_GMC_DST_DATATYPE_SHIFT 8 |
711 | # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) |
712 | # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) |
713 | # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) |
714 | # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
715 | # define RADEON_GMC_WR_MSK_DIS (1 << 30) |
716 | # define RADEON_ROP3_S 0x00cc0000 |
717 | # define RADEON_ROP3_P 0x00f00000 |
718 | #define RADEON_DP_WRITE_MASK 0x16cc |
719 | #define RADEON_SRC_PITCH_OFFSET 0x1428 |
720 | #define RADEON_DST_PITCH_OFFSET 0x142c |
721 | #define RADEON_DST_PITCH_OFFSET_C 0x1c80 |
722 | # define RADEON_DST_TILE_LINEAR (0 << 30) |
723 | # define RADEON_DST_TILE_MACRO (1 << 30) |
724 | # define RADEON_DST_TILE_MICRO (2 << 30) |
725 | # define RADEON_DST_TILE_BOTH (3 << 30) |
726 | |
727 | #define RADEON_SCRATCH_REG0 0x15e0 |
728 | #define RADEON_SCRATCH_REG1 0x15e4 |
729 | #define RADEON_SCRATCH_REG2 0x15e8 |
730 | #define RADEON_SCRATCH_REG3 0x15ec |
731 | #define RADEON_SCRATCH_REG4 0x15f0 |
732 | #define RADEON_SCRATCH_REG5 0x15f4 |
733 | #define RADEON_SCRATCH_UMSK 0x0770 |
734 | #define RADEON_SCRATCH_ADDR 0x0774 |
735 | |
736 | #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) |
737 | |
738 | extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); |
739 | |
740 | #define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x) |
741 | |
742 | #define R600_SCRATCH_REG0 0x8500 |
743 | #define R600_SCRATCH_REG1 0x8504 |
744 | #define R600_SCRATCH_REG2 0x8508 |
745 | #define R600_SCRATCH_REG3 0x850c |
746 | #define R600_SCRATCH_REG4 0x8510 |
747 | #define R600_SCRATCH_REG5 0x8514 |
748 | #define R600_SCRATCH_REG6 0x8518 |
749 | #define R600_SCRATCH_REG7 0x851c |
750 | #define R600_SCRATCH_UMSK 0x8540 |
751 | #define R600_SCRATCH_ADDR 0x8544 |
752 | |
753 | #define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x)) |
754 | |
755 | #define RADEON_GEN_INT_CNTL 0x0040 |
756 | # define RADEON_CRTC_VBLANK_MASK (1 << 0) |
757 | # define RADEON_CRTC2_VBLANK_MASK (1 << 9) |
758 | # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) |
759 | # define RADEON_SW_INT_ENABLE (1 << 25) |
760 | |
761 | #define RADEON_GEN_INT_STATUS 0x0044 |
762 | # define RADEON_CRTC_VBLANK_STAT (1 << 0) |
763 | # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) |
764 | # define RADEON_CRTC2_VBLANK_STAT (1 << 9) |
765 | # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) |
766 | # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) |
767 | # define RADEON_SW_INT_TEST (1 << 25) |
768 | # define RADEON_SW_INT_TEST_ACK (1 << 25) |
769 | # define RADEON_SW_INT_FIRE (1 << 26) |
770 | # define R500_DISPLAY_INT_STATUS (1 << 0) |
771 | |
772 | #define RADEON_HOST_PATH_CNTL 0x0130 |
773 | # define RADEON_HDP_SOFT_RESET (1 << 26) |
774 | # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) |
775 | # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) |
776 | |
777 | #define RADEON_ISYNC_CNTL 0x1724 |
778 | # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) |
779 | # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) |
780 | # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) |
781 | # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) |
782 | # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) |
783 | # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) |
784 | |
785 | #define RADEON_RBBM_GUICNTL 0x172c |
786 | # define RADEON_HOST_DATA_SWAP_NONE (0 << 0) |
787 | # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) |
788 | # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) |
789 | # define RADEON_HOST_DATA_SWAP_HDW (3 << 0) |
790 | |
791 | #define RADEON_MC_AGP_LOCATION 0x014c |
792 | #define RADEON_MC_FB_LOCATION 0x0148 |
793 | #define RADEON_MCLK_CNTL 0x0012 |
794 | # define RADEON_FORCEON_MCLKA (1 << 16) |
795 | # define RADEON_FORCEON_MCLKB (1 << 17) |
796 | # define RADEON_FORCEON_YCLKA (1 << 18) |
797 | # define RADEON_FORCEON_YCLKB (1 << 19) |
798 | # define RADEON_FORCEON_MC (1 << 20) |
799 | # define RADEON_FORCEON_AIC (1 << 21) |
800 | |
801 | #define RADEON_PP_BORDER_COLOR_0 0x1d40 |
802 | #define RADEON_PP_BORDER_COLOR_1 0x1d44 |
803 | #define RADEON_PP_BORDER_COLOR_2 0x1d48 |
804 | #define RADEON_PP_CNTL 0x1c38 |
805 | # define RADEON_SCISSOR_ENABLE (1 << 1) |
806 | #define RADEON_PP_LUM_MATRIX 0x1d00 |
807 | #define RADEON_PP_MISC 0x1c14 |
808 | #define RADEON_PP_ROT_MATRIX_0 0x1d58 |
809 | #define RADEON_PP_TXFILTER_0 0x1c54 |
810 | #define RADEON_PP_TXOFFSET_0 0x1c5c |
811 | #define RADEON_PP_TXFILTER_1 0x1c6c |
812 | #define RADEON_PP_TXFILTER_2 0x1c84 |
813 | |
814 | #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ |
815 | #define R300_DSTCACHE_CTLSTAT 0x1714 |
816 | # define R300_RB2D_DC_FLUSH (3 << 0) |
817 | # define R300_RB2D_DC_FREE (3 << 2) |
818 | # define R300_RB2D_DC_FLUSH_ALL 0xf |
819 | # define R300_RB2D_DC_BUSY (1 << 31) |
820 | #define RADEON_RB3D_CNTL 0x1c3c |
821 | # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) |
822 | # define RADEON_PLANE_MASK_ENABLE (1 << 1) |
823 | # define RADEON_DITHER_ENABLE (1 << 2) |
824 | # define RADEON_ROUND_ENABLE (1 << 3) |
825 | # define RADEON_SCALE_DITHER_ENABLE (1 << 4) |
826 | # define RADEON_DITHER_INIT (1 << 5) |
827 | # define RADEON_ROP_ENABLE (1 << 6) |
828 | # define RADEON_STENCIL_ENABLE (1 << 7) |
829 | # define RADEON_Z_ENABLE (1 << 8) |
830 | # define RADEON_ZBLOCK16 (1 << 15) |
831 | #define RADEON_RB3D_DEPTHOFFSET 0x1c24 |
832 | #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 |
833 | #define RADEON_RB3D_DEPTHPITCH 0x1c28 |
834 | #define RADEON_RB3D_PLANEMASK 0x1d84 |
835 | #define RADEON_RB3D_STENCILREFMASK 0x1d7c |
836 | #define RADEON_RB3D_ZCACHE_MODE 0x3250 |
837 | #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 |
838 | # define RADEON_RB3D_ZC_FLUSH (1 << 0) |
839 | # define RADEON_RB3D_ZC_FREE (1 << 2) |
840 | # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 |
841 | # define RADEON_RB3D_ZC_BUSY (1 << 31) |
842 | #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 |
843 | # define R300_ZC_FLUSH (1 << 0) |
844 | # define R300_ZC_FREE (1 << 1) |
845 | # define R300_ZC_BUSY (1 << 31) |
846 | #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c |
847 | # define RADEON_RB3D_DC_FLUSH (3 << 0) |
848 | # define RADEON_RB3D_DC_FREE (3 << 2) |
849 | # define RADEON_RB3D_DC_FLUSH_ALL 0xf |
850 | # define RADEON_RB3D_DC_BUSY (1 << 31) |
851 | #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c |
852 | # define R300_RB3D_DC_FLUSH (2 << 0) |
853 | # define R300_RB3D_DC_FREE (2 << 2) |
854 | # define R300_RB3D_DC_FINISH (1 << 4) |
855 | #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c |
856 | # define RADEON_Z_TEST_MASK (7 << 4) |
857 | # define RADEON_Z_TEST_ALWAYS (7 << 4) |
858 | # define RADEON_Z_HIERARCHY_ENABLE (1 << 8) |
859 | # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) |
860 | # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) |
861 | # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) |
862 | # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) |
863 | # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) |
864 | # define RADEON_FORCE_Z_DIRTY (1 << 29) |
865 | # define RADEON_Z_WRITE_ENABLE (1 << 30) |
866 | # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) |
867 | #define RADEON_RBBM_SOFT_RESET 0x00f0 |
868 | # define RADEON_SOFT_RESET_CP (1 << 0) |
869 | # define RADEON_SOFT_RESET_HI (1 << 1) |
870 | # define RADEON_SOFT_RESET_SE (1 << 2) |
871 | # define RADEON_SOFT_RESET_RE (1 << 3) |
872 | # define RADEON_SOFT_RESET_PP (1 << 4) |
873 | # define RADEON_SOFT_RESET_E2 (1 << 5) |
874 | # define RADEON_SOFT_RESET_RB (1 << 6) |
875 | # define RADEON_SOFT_RESET_HDP (1 << 7) |
876 | /* |
877 | * 6:0 Available slots in the FIFO |
878 | * 8 Host Interface active |
879 | * 9 CP request active |
880 | * 10 FIFO request active |
881 | * 11 Host Interface retry active |
882 | * 12 CP retry active |
883 | * 13 FIFO retry active |
884 | * 14 FIFO pipeline busy |
885 | * 15 Event engine busy |
886 | * 16 CP command stream busy |
887 | * 17 2D engine busy |
888 | * 18 2D portion of render backend busy |
889 | * 20 3D setup engine busy |
890 | * 26 GA engine busy |
891 | * 27 CBA 2D engine busy |
892 | * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or |
893 | * command stream queue not empty or Ring Buffer not empty |
894 | */ |
895 | #define RADEON_RBBM_STATUS 0x0e40 |
896 | /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ |
897 | /* #define RADEON_RBBM_STATUS 0x1740 */ |
898 | /* bits 6:0 are dword slots available in the cmd fifo */ |
899 | # define RADEON_RBBM_FIFOCNT_MASK 0x007f |
900 | # define RADEON_HIRQ_ON_RBB (1 << 8) |
901 | # define RADEON_CPRQ_ON_RBB (1 << 9) |
902 | # define RADEON_CFRQ_ON_RBB (1 << 10) |
903 | # define RADEON_HIRQ_IN_RTBUF (1 << 11) |
904 | # define RADEON_CPRQ_IN_RTBUF (1 << 12) |
905 | # define RADEON_CFRQ_IN_RTBUF (1 << 13) |
906 | # define RADEON_PIPE_BUSY (1 << 14) |
907 | # define RADEON_ENG_EV_BUSY (1 << 15) |
908 | # define RADEON_CP_CMDSTRM_BUSY (1 << 16) |
909 | # define RADEON_E2_BUSY (1 << 17) |
910 | # define RADEON_RB2D_BUSY (1 << 18) |
911 | # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ |
912 | # define RADEON_VAP_BUSY (1 << 20) |
913 | # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ |
914 | # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ |
915 | # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ |
916 | # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ |
917 | # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ |
918 | # define RADEON_GA_BUSY (1 << 26) |
919 | # define RADEON_CBA2D_BUSY (1 << 27) |
920 | # define RADEON_RBBM_ACTIVE (1 << 31) |
921 | #define RADEON_RE_LINE_PATTERN 0x1cd0 |
922 | #define RADEON_RE_MISC 0x26c4 |
923 | #define RADEON_RE_TOP_LEFT 0x26c0 |
924 | #define RADEON_RE_WIDTH_HEIGHT 0x1c44 |
925 | #define RADEON_RE_STIPPLE_ADDR 0x1cc8 |
926 | #define RADEON_RE_STIPPLE_DATA 0x1ccc |
927 | |
928 | #define RADEON_SCISSOR_TL_0 0x1cd8 |
929 | #define RADEON_SCISSOR_BR_0 0x1cdc |
930 | #define RADEON_SCISSOR_TL_1 0x1ce0 |
931 | #define RADEON_SCISSOR_BR_1 0x1ce4 |
932 | #define RADEON_SCISSOR_TL_2 0x1ce8 |
933 | #define RADEON_SCISSOR_BR_2 0x1cec |
934 | #define RADEON_SE_COORD_FMT 0x1c50 |
935 | #define RADEON_SE_CNTL 0x1c4c |
936 | # define RADEON_FFACE_CULL_CW (0 << 0) |
937 | # define RADEON_BFACE_SOLID (3 << 1) |
938 | # define RADEON_FFACE_SOLID (3 << 3) |
939 | # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) |
940 | # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) |
941 | # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) |
942 | # define RADEON_ALPHA_SHADE_FLAT (1 << 10) |
943 | # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) |
944 | # define RADEON_SPECULAR_SHADE_FLAT (1 << 12) |
945 | # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) |
946 | # define RADEON_FOG_SHADE_FLAT (1 << 14) |
947 | # define RADEON_FOG_SHADE_GOURAUD (2 << 14) |
948 | # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) |
949 | # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) |
950 | # define RADEON_VTX_PIX_CENTER_OGL (1 << 27) |
951 | # define RADEON_ROUND_MODE_TRUNC (0 << 28) |
952 | # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) |
953 | #define RADEON_SE_CNTL_STATUS 0x2140 |
954 | #define RADEON_SE_LINE_WIDTH 0x1db8 |
955 | #define RADEON_SE_VPORT_XSCALE 0x1d98 |
956 | #define RADEON_SE_ZBIAS_FACTOR 0x1db0 |
957 | #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 |
958 | #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 |
959 | #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 |
960 | # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 |
961 | # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 |
962 | #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 |
963 | #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 |
964 | # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 |
965 | #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C |
966 | #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 |
967 | #define RADEON_SURFACE_ACCESS_CLR 0x0bfc |
968 | #define RADEON_SURFACE_CNTL 0x0b00 |
969 | # define RADEON_SURF_TRANSLATION_DIS (1 << 8) |
970 | # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) |
971 | # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) |
972 | # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) |
973 | # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) |
974 | # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) |
975 | # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) |
976 | # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) |
977 | # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) |
978 | #define RADEON_SURFACE0_INFO 0x0b0c |
979 | # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) |
980 | # define RADEON_SURF_TILE_MODE_MASK (3 << 16) |
981 | # define RADEON_SURF_TILE_MODE_MACRO (0 << 16) |
982 | # define RADEON_SURF_TILE_MODE_MICRO (1 << 16) |
983 | # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) |
984 | # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) |
985 | #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 |
986 | #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 |
987 | # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) |
988 | #define RADEON_SURFACE1_INFO 0x0b1c |
989 | #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 |
990 | #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 |
991 | #define RADEON_SURFACE2_INFO 0x0b2c |
992 | #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 |
993 | #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 |
994 | #define RADEON_SURFACE3_INFO 0x0b3c |
995 | #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 |
996 | #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 |
997 | #define RADEON_SURFACE4_INFO 0x0b4c |
998 | #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 |
999 | #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 |
1000 | #define RADEON_SURFACE5_INFO 0x0b5c |
1001 | #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 |
1002 | #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 |
1003 | #define RADEON_SURFACE6_INFO 0x0b6c |
1004 | #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 |
1005 | #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 |
1006 | #define RADEON_SURFACE7_INFO 0x0b7c |
1007 | #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 |
1008 | #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 |
1009 | #define RADEON_SW_SEMAPHORE 0x013c |
1010 | |
1011 | #define RADEON_WAIT_UNTIL 0x1720 |
1012 | # define RADEON_WAIT_CRTC_PFLIP (1 << 0) |
1013 | # define RADEON_WAIT_2D_IDLE (1 << 14) |
1014 | # define RADEON_WAIT_3D_IDLE (1 << 15) |
1015 | # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) |
1016 | # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) |
1017 | # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) |
1018 | |
1019 | #define RADEON_RB3D_ZMASKOFFSET 0x3234 |
1020 | #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c |
1021 | # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) |
1022 | # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) |
1023 | |
1024 | /* CP registers */ |
1025 | #define RADEON_CP_ME_RAM_ADDR 0x07d4 |
1026 | #define RADEON_CP_ME_RAM_RADDR 0x07d8 |
1027 | #define RADEON_CP_ME_RAM_DATAH 0x07dc |
1028 | #define RADEON_CP_ME_RAM_DATAL 0x07e0 |
1029 | |
1030 | #define RADEON_CP_RB_BASE 0x0700 |
1031 | #define RADEON_CP_RB_CNTL 0x0704 |
1032 | # define RADEON_BUF_SWAP_32BIT (2 << 16) |
1033 | # define RADEON_RB_NO_UPDATE (1 << 27) |
1034 | # define RADEON_RB_RPTR_WR_ENA (1 << 31) |
1035 | #define RADEON_CP_RB_RPTR_ADDR 0x070c |
1036 | #define RADEON_CP_RB_RPTR 0x0710 |
1037 | #define RADEON_CP_RB_WPTR 0x0714 |
1038 | |
1039 | #define RADEON_CP_RB_WPTR_DELAY 0x0718 |
1040 | # define RADEON_PRE_WRITE_TIMER_SHIFT 0 |
1041 | # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 |
1042 | |
1043 | #define RADEON_CP_IB_BASE 0x0738 |
1044 | |
1045 | #define RADEON_CP_CSQ_CNTL 0x0740 |
1046 | # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) |
1047 | # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) |
1048 | # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) |
1049 | # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) |
1050 | # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) |
1051 | # define RADEON_CSQ_PRIBM_INDBM (4 << 28) |
1052 | # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) |
1053 | |
1054 | #define R300_CP_RESYNC_ADDR 0x0778 |
1055 | #define R300_CP_RESYNC_DATA 0x077c |
1056 | |
1057 | #define RADEON_AIC_CNTL 0x01d0 |
1058 | # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) |
1059 | # define RS400_MSI_REARM (1 << 3) |
1060 | #define RADEON_AIC_STAT 0x01d4 |
1061 | #define RADEON_AIC_PT_BASE 0x01d8 |
1062 | #define RADEON_AIC_LO_ADDR 0x01dc |
1063 | #define RADEON_AIC_HI_ADDR 0x01e0 |
1064 | #define RADEON_AIC_TLB_ADDR 0x01e4 |
1065 | #define RADEON_AIC_TLB_DATA 0x01e8 |
1066 | |
1067 | /* CP command packets */ |
1068 | #define RADEON_CP_PACKET0 0x00000000 |
1069 | # define RADEON_ONE_REG_WR (1 << 15) |
1070 | #define RADEON_CP_PACKET1 0x40000000 |
1071 | #define RADEON_CP_PACKET2 0x80000000 |
1072 | #define RADEON_CP_PACKET3 0xC0000000 |
1073 | # define RADEON_CP_NOP 0x00001000 |
1074 | # define RADEON_CP_NEXT_CHAR 0x00001900 |
1075 | # define RADEON_CP_PLY_NEXTSCAN 0x00001D00 |
1076 | # define RADEON_CP_SET_SCISSORS 0x00001E00 |
1077 | /* GEN_INDX_PRIM is unsupported starting with R300 */ |
1078 | # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 |
1079 | # define RADEON_WAIT_FOR_IDLE 0x00002600 |
1080 | # define RADEON_3D_DRAW_VBUF 0x00002800 |
1081 | # define RADEON_3D_DRAW_IMMD 0x00002900 |
1082 | # define RADEON_3D_DRAW_INDX 0x00002A00 |
1083 | # define RADEON_CP_LOAD_PALETTE 0x00002C00 |
1084 | # define RADEON_3D_LOAD_VBPNTR 0x00002F00 |
1085 | # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 |
1086 | # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 |
1087 | # define RADEON_3D_CLEAR_ZMASK 0x00003200 |
1088 | # define RADEON_CP_INDX_BUFFER 0x00003300 |
1089 | # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 |
1090 | # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 |
1091 | # define RADEON_CP_3D_DRAW_INDX_2 0x00003600 |
1092 | # define RADEON_3D_CLEAR_HIZ 0x00003700 |
1093 | # define RADEON_CP_3D_CLEAR_CMASK 0x00003802 |
1094 | # define RADEON_CNTL_HOSTDATA_BLT 0x00009400 |
1095 | # define RADEON_CNTL_PAINT_MULTI 0x00009A00 |
1096 | # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 |
1097 | # define RADEON_CNTL_SET_SCISSORS 0xC0001E00 |
1098 | |
1099 | # define R600_IT_INDIRECT_BUFFER_END 0x00001700 |
1100 | # define R600_IT_SET_PREDICATION 0x00002000 |
1101 | # define R600_IT_REG_RMW 0x00002100 |
1102 | # define R600_IT_COND_EXEC 0x00002200 |
1103 | # define R600_IT_PRED_EXEC 0x00002300 |
1104 | # define R600_IT_START_3D_CMDBUF 0x00002400 |
1105 | # define R600_IT_DRAW_INDEX_2 0x00002700 |
1106 | # define R600_IT_CONTEXT_CONTROL 0x00002800 |
1107 | # define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900 |
1108 | # define R600_IT_INDEX_TYPE 0x00002A00 |
1109 | # define R600_IT_DRAW_INDEX 0x00002B00 |
1110 | # define R600_IT_DRAW_INDEX_AUTO 0x00002D00 |
1111 | # define R600_IT_DRAW_INDEX_IMMD 0x00002E00 |
1112 | # define R600_IT_NUM_INSTANCES 0x00002F00 |
1113 | # define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400 |
1114 | # define R600_IT_INDIRECT_BUFFER_MP 0x00003800 |
1115 | # define R600_IT_MEM_SEMAPHORE 0x00003900 |
1116 | # define R600_IT_MPEG_INDEX 0x00003A00 |
1117 | # define R600_IT_WAIT_REG_MEM 0x00003C00 |
1118 | # define R600_IT_MEM_WRITE 0x00003D00 |
1119 | # define R600_IT_INDIRECT_BUFFER 0x00003200 |
1120 | # define R600_IT_SURFACE_SYNC 0x00004300 |
1121 | # define R600_CB0_DEST_BASE_ENA (1 << 6) |
1122 | # define R600_TC_ACTION_ENA (1 << 23) |
1123 | # define R600_VC_ACTION_ENA (1 << 24) |
1124 | # define R600_CB_ACTION_ENA (1 << 25) |
1125 | # define R600_DB_ACTION_ENA (1 << 26) |
1126 | # define R600_SH_ACTION_ENA (1 << 27) |
1127 | # define R600_SMX_ACTION_ENA (1 << 28) |
1128 | # define R600_IT_ME_INITIALIZE 0x00004400 |
1129 | # define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) |
1130 | # define R600_IT_COND_WRITE 0x00004500 |
1131 | # define R600_IT_EVENT_WRITE 0x00004600 |
1132 | # define R600_IT_EVENT_WRITE_EOP 0x00004700 |
1133 | # define R600_IT_ONE_REG_WRITE 0x00005700 |
1134 | # define R600_IT_SET_CONFIG_REG 0x00006800 |
1135 | # define R600_SET_CONFIG_REG_OFFSET 0x00008000 |
1136 | # define R600_SET_CONFIG_REG_END 0x0000ac00 |
1137 | # define R600_IT_SET_CONTEXT_REG 0x00006900 |
1138 | # define R600_SET_CONTEXT_REG_OFFSET 0x00028000 |
1139 | # define R600_SET_CONTEXT_REG_END 0x00029000 |
1140 | # define R600_IT_SET_ALU_CONST 0x00006A00 |
1141 | # define R600_SET_ALU_CONST_OFFSET 0x00030000 |
1142 | # define R600_SET_ALU_CONST_END 0x00032000 |
1143 | # define R600_IT_SET_BOOL_CONST 0x00006B00 |
1144 | # define R600_SET_BOOL_CONST_OFFSET 0x0003e380 |
1145 | # define R600_SET_BOOL_CONST_END 0x00040000 |
1146 | # define R600_IT_SET_LOOP_CONST 0x00006C00 |
1147 | # define R600_SET_LOOP_CONST_OFFSET 0x0003e200 |
1148 | # define R600_SET_LOOP_CONST_END 0x0003e380 |
1149 | # define R600_IT_SET_RESOURCE 0x00006D00 |
1150 | # define R600_SET_RESOURCE_OFFSET 0x00038000 |
1151 | # define R600_SET_RESOURCE_END 0x0003c000 |
1152 | # define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0 |
1153 | # define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1 |
1154 | # define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2 |
1155 | # define R600_SQ_TEX_VTX_VALID_BUFFER 0x3 |
1156 | # define R600_IT_SET_SAMPLER 0x00006E00 |
1157 | # define R600_SET_SAMPLER_OFFSET 0x0003c000 |
1158 | # define R600_SET_SAMPLER_END 0x0003cff0 |
1159 | # define R600_IT_SET_CTL_CONST 0x00006F00 |
1160 | # define R600_SET_CTL_CONST_OFFSET 0x0003cff0 |
1161 | # define R600_SET_CTL_CONST_END 0x0003e200 |
1162 | # define R600_IT_SURFACE_BASE_UPDATE 0x00007300 |
1163 | |
1164 | #define RADEON_CP_PACKET_MASK 0xC0000000 |
1165 | #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 |
1166 | #define RADEON_CP_PACKET0_REG_MASK 0x000007ff |
1167 | #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff |
1168 | #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 |
1169 | |
1170 | #define RADEON_VTX_Z_PRESENT (1 << 31) |
1171 | #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) |
1172 | |
1173 | #define RADEON_PRIM_TYPE_NONE (0 << 0) |
1174 | #define RADEON_PRIM_TYPE_POINT (1 << 0) |
1175 | #define RADEON_PRIM_TYPE_LINE (2 << 0) |
1176 | #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) |
1177 | #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) |
1178 | #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) |
1179 | #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) |
1180 | #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) |
1181 | #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) |
1182 | #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) |
1183 | #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) |
1184 | #define RADEON_PRIM_TYPE_MASK 0xf |
1185 | #define RADEON_PRIM_WALK_IND (1 << 4) |
1186 | #define RADEON_PRIM_WALK_LIST (2 << 4) |
1187 | #define RADEON_PRIM_WALK_RING (3 << 4) |
1188 | #define RADEON_COLOR_ORDER_BGRA (0 << 6) |
1189 | #define RADEON_COLOR_ORDER_RGBA (1 << 6) |
1190 | #define RADEON_MAOS_ENABLE (1 << 7) |
1191 | #define RADEON_VTX_FMT_R128_MODE (0 << 8) |
1192 | #define RADEON_VTX_FMT_RADEON_MODE (1 << 8) |
1193 | #define RADEON_NUM_VERTICES_SHIFT 16 |
1194 | |
1195 | #define RADEON_COLOR_FORMAT_CI8 2 |
1196 | #define RADEON_COLOR_FORMAT_ARGB1555 3 |
1197 | #define RADEON_COLOR_FORMAT_RGB565 4 |
1198 | #define RADEON_COLOR_FORMAT_ARGB8888 6 |
1199 | #define RADEON_COLOR_FORMAT_RGB332 7 |
1200 | #define RADEON_COLOR_FORMAT_RGB8 9 |
1201 | #define RADEON_COLOR_FORMAT_ARGB4444 15 |
1202 | |
1203 | #define RADEON_TXFORMAT_I8 0 |
1204 | #define RADEON_TXFORMAT_AI88 1 |
1205 | #define RADEON_TXFORMAT_RGB332 2 |
1206 | #define RADEON_TXFORMAT_ARGB1555 3 |
1207 | #define RADEON_TXFORMAT_RGB565 4 |
1208 | #define RADEON_TXFORMAT_ARGB4444 5 |
1209 | #define RADEON_TXFORMAT_ARGB8888 6 |
1210 | #define RADEON_TXFORMAT_RGBA8888 7 |
1211 | #define RADEON_TXFORMAT_Y8 8 |
1212 | #define RADEON_TXFORMAT_VYUY422 10 |
1213 | #define RADEON_TXFORMAT_YVYU422 11 |
1214 | #define RADEON_TXFORMAT_DXT1 12 |
1215 | #define RADEON_TXFORMAT_DXT23 14 |
1216 | #define RADEON_TXFORMAT_DXT45 15 |
1217 | |
1218 | #define R200_PP_TXCBLEND_0 0x2f00 |
1219 | #define R200_PP_TXCBLEND_1 0x2f10 |
1220 | #define R200_PP_TXCBLEND_2 0x2f20 |
1221 | #define R200_PP_TXCBLEND_3 0x2f30 |
1222 | #define R200_PP_TXCBLEND_4 0x2f40 |
1223 | #define R200_PP_TXCBLEND_5 0x2f50 |
1224 | #define R200_PP_TXCBLEND_6 0x2f60 |
1225 | #define R200_PP_TXCBLEND_7 0x2f70 |
1226 | #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 |
1227 | #define R200_PP_TFACTOR_0 0x2ee0 |
1228 | #define R200_SE_VTX_FMT_0 0x2088 |
1229 | #define R200_SE_VAP_CNTL 0x2080 |
1230 | #define R200_SE_TCL_MATRIX_SEL_0 0x2230 |
1231 | #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 |
1232 | #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 |
1233 | #define R200_PP_TXFILTER_5 0x2ca0 |
1234 | #define R200_PP_TXFILTER_4 0x2c80 |
1235 | #define R200_PP_TXFILTER_3 0x2c60 |
1236 | #define R200_PP_TXFILTER_2 0x2c40 |
1237 | #define R200_PP_TXFILTER_1 0x2c20 |
1238 | #define R200_PP_TXFILTER_0 0x2c00 |
1239 | #define R200_PP_TXOFFSET_5 0x2d78 |
1240 | #define R200_PP_TXOFFSET_4 0x2d60 |
1241 | #define R200_PP_TXOFFSET_3 0x2d48 |
1242 | #define R200_PP_TXOFFSET_2 0x2d30 |
1243 | #define R200_PP_TXOFFSET_1 0x2d18 |
1244 | #define R200_PP_TXOFFSET_0 0x2d00 |
1245 | |
1246 | #define R200_PP_CUBIC_FACES_0 0x2c18 |
1247 | #define R200_PP_CUBIC_FACES_1 0x2c38 |
1248 | #define R200_PP_CUBIC_FACES_2 0x2c58 |
1249 | #define R200_PP_CUBIC_FACES_3 0x2c78 |
1250 | #define R200_PP_CUBIC_FACES_4 0x2c98 |
1251 | #define R200_PP_CUBIC_FACES_5 0x2cb8 |
1252 | #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 |
1253 | #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 |
1254 | #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c |
1255 | #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 |
1256 | #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 |
1257 | #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c |
1258 | #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 |
1259 | #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 |
1260 | #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 |
1261 | #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c |
1262 | #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 |
1263 | #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 |
1264 | #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c |
1265 | #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 |
1266 | #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 |
1267 | #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c |
1268 | #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 |
1269 | #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 |
1270 | #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 |
1271 | #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c |
1272 | #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 |
1273 | #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 |
1274 | #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c |
1275 | #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 |
1276 | #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 |
1277 | #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c |
1278 | #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 |
1279 | #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 |
1280 | #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 |
1281 | #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c |
1282 | |
1283 | #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 |
1284 | #define R200_SE_VTE_CNTL 0x20b0 |
1285 | #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 |
1286 | #define R200_PP_TAM_DEBUG3 0x2d9c |
1287 | #define R200_PP_CNTL_X 0x2cc4 |
1288 | #define R200_SE_VAP_CNTL_STATUS 0x2140 |
1289 | #define R200_RE_SCISSOR_TL_0 0x1cd8 |
1290 | #define R200_RE_SCISSOR_TL_1 0x1ce0 |
1291 | #define R200_RE_SCISSOR_TL_2 0x1ce8 |
1292 | #define R200_RB3D_DEPTHXY_OFFSET 0x1d60 |
1293 | #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 |
1294 | #define R200_SE_VTX_STATE_CNTL 0x2180 |
1295 | #define R200_RE_POINTSIZE 0x2648 |
1296 | #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 |
1297 | |
1298 | #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ |
1299 | #define RADEON_PP_TEX_SIZE_1 0x1d0c |
1300 | #define RADEON_PP_TEX_SIZE_2 0x1d14 |
1301 | |
1302 | #define RADEON_PP_CUBIC_FACES_0 0x1d24 |
1303 | #define RADEON_PP_CUBIC_FACES_1 0x1d28 |
1304 | #define RADEON_PP_CUBIC_FACES_2 0x1d2c |
1305 | #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ |
1306 | #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 |
1307 | #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 |
1308 | |
1309 | #define RADEON_SE_TCL_STATE_FLUSH 0x2284 |
1310 | |
1311 | #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 |
1312 | #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 |
1313 | #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 |
1314 | #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 |
1315 | #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 |
1316 | #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 |
1317 | #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 |
1318 | #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b |
1319 | #define R200_3D_DRAW_IMMD_2 0xC0003500 |
1320 | #define R200_SE_VTX_FMT_1 0x208c |
1321 | #define R200_RE_CNTL 0x1c50 |
1322 | |
1323 | #define R200_RB3D_BLENDCOLOR 0x3218 |
1324 | |
1325 | #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 |
1326 | |
1327 | #define R200_PP_TRI_PERF 0x2cf8 |
1328 | |
1329 | #define R200_PP_AFS_0 0x2f80 |
1330 | #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ |
1331 | |
1332 | #define R200_VAP_PVS_CNTL_1 0x22D0 |
1333 | |
1334 | #define RADEON_CRTC_CRNT_FRAME 0x0214 |
1335 | #define RADEON_CRTC2_CRNT_FRAME 0x0314 |
1336 | |
1337 | #define R500_D1CRTC_STATUS 0x609c |
1338 | #define R500_D2CRTC_STATUS 0x689c |
1339 | #define R500_CRTC_V_BLANK (1<<0) |
1340 | |
1341 | #define R500_D1CRTC_FRAME_COUNT 0x60a4 |
1342 | #define R500_D2CRTC_FRAME_COUNT 0x68a4 |
1343 | |
1344 | #define R500_D1MODE_V_COUNTER 0x6530 |
1345 | #define R500_D2MODE_V_COUNTER 0x6d30 |
1346 | |
1347 | #define R500_D1MODE_VBLANK_STATUS 0x6534 |
1348 | #define R500_D2MODE_VBLANK_STATUS 0x6d34 |
1349 | #define R500_VBLANK_OCCURED (1<<0) |
1350 | #define R500_VBLANK_ACK (1<<4) |
1351 | #define R500_VBLANK_STAT (1<<12) |
1352 | #define R500_VBLANK_INT (1<<16) |
1353 | |
1354 | #define R500_DxMODE_INT_MASK 0x6540 |
1355 | #define R500_D1MODE_INT_MASK (1<<0) |
1356 | #define R500_D2MODE_INT_MASK (1<<8) |
1357 | |
1358 | #define R500_DISP_INTERRUPT_STATUS 0x7edc |
1359 | #define R500_D1_VBLANK_INTERRUPT (1 << 4) |
1360 | #define R500_D2_VBLANK_INTERRUPT (1 << 5) |
1361 | |
1362 | /* R6xx/R7xx registers */ |
1363 | #define R600_MC_VM_FB_LOCATION 0x2180 |
1364 | #define R600_MC_VM_AGP_TOP 0x2184 |
1365 | #define R600_MC_VM_AGP_BOT 0x2188 |
1366 | #define R600_MC_VM_AGP_BASE 0x218c |
1367 | #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 |
1368 | #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 |
1369 | #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 |
1370 | |
1371 | #define R700_MC_VM_FB_LOCATION 0x2024 |
1372 | #define R700_MC_VM_AGP_TOP 0x2028 |
1373 | #define R700_MC_VM_AGP_BOT 0x202c |
1374 | #define R700_MC_VM_AGP_BASE 0x2030 |
1375 | #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 |
1376 | #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 |
1377 | #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c |
1378 | |
1379 | #define R600_MCD_RD_A_CNTL 0x219c |
1380 | #define R600_MCD_RD_B_CNTL 0x21a0 |
1381 | |
1382 | #define R600_MCD_WR_A_CNTL 0x21a4 |
1383 | #define R600_MCD_WR_B_CNTL 0x21a8 |
1384 | |
1385 | #define R600_MCD_RD_SYS_CNTL 0x2200 |
1386 | #define R600_MCD_WR_SYS_CNTL 0x2214 |
1387 | |
1388 | #define R600_MCD_RD_GFX_CNTL 0x21fc |
1389 | #define R600_MCD_RD_HDP_CNTL 0x2204 |
1390 | #define R600_MCD_RD_PDMA_CNTL 0x2208 |
1391 | #define R600_MCD_RD_SEM_CNTL 0x220c |
1392 | #define R600_MCD_WR_GFX_CNTL 0x2210 |
1393 | #define R600_MCD_WR_HDP_CNTL 0x2218 |
1394 | #define R600_MCD_WR_PDMA_CNTL 0x221c |
1395 | #define R600_MCD_WR_SEM_CNTL 0x2220 |
1396 | |
1397 | # define R600_MCD_L1_TLB (1 << 0) |
1398 | # define R600_MCD_L1_FRAG_PROC (1 << 1) |
1399 | # define R600_MCD_L1_STRICT_ORDERING (1 << 2) |
1400 | |
1401 | # define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6) |
1402 | # define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) |
1403 | # define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) |
1404 | # define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) |
1405 | # define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) |
1406 | |
1407 | # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) |
1408 | # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) |
1409 | |
1410 | # define R600_MCD_SEMAPHORE_MODE (1 << 10) |
1411 | # define R600_MCD_WAIT_L2_QUERY (1 << 11) |
1412 | # define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12) |
1413 | # define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) |
1414 | |
1415 | #define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654 |
1416 | #define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658 |
1417 | #define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c |
1418 | |
1419 | #define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 |
1420 | #define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 |
1421 | #define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c |
1422 | #define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 |
1423 | |
1424 | # define R700_ENABLE_L1_TLB (1 << 0) |
1425 | # define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) |
1426 | # define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) |
1427 | # define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) |
1428 | # define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15) |
1429 | # define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18) |
1430 | |
1431 | #define R700_MC_ARB_RAMCFG 0x2760 |
1432 | # define R700_NOOFBANK_SHIFT 0 |
1433 | # define R700_NOOFBANK_MASK 0x3 |
1434 | # define R700_NOOFRANK_SHIFT 2 |
1435 | # define R700_NOOFRANK_MASK 0x1 |
1436 | # define R700_NOOFROWS_SHIFT 3 |
1437 | # define R700_NOOFROWS_MASK 0x7 |
1438 | # define R700_NOOFCOLS_SHIFT 6 |
1439 | # define R700_NOOFCOLS_MASK 0x3 |
1440 | # define R700_CHANSIZE_SHIFT 8 |
1441 | # define R700_CHANSIZE_MASK 0x1 |
1442 | # define R700_BURSTLENGTH_SHIFT 9 |
1443 | # define R700_BURSTLENGTH_MASK 0x1 |
1444 | #define R600_RAMCFG 0x2408 |
1445 | # define R600_NOOFBANK_SHIFT 0 |
1446 | # define R600_NOOFBANK_MASK 0x1 |
1447 | # define R600_NOOFRANK_SHIFT 1 |
1448 | # define R600_NOOFRANK_MASK 0x1 |
1449 | # define R600_NOOFROWS_SHIFT 2 |
1450 | # define R600_NOOFROWS_MASK 0x7 |
1451 | # define R600_NOOFCOLS_SHIFT 5 |
1452 | # define R600_NOOFCOLS_MASK 0x3 |
1453 | # define R600_CHANSIZE_SHIFT 7 |
1454 | # define R600_CHANSIZE_MASK 0x1 |
1455 | # define R600_BURSTLENGTH_SHIFT 8 |
1456 | # define R600_BURSTLENGTH_MASK 0x1 |
1457 | |
1458 | #define R600_VM_L2_CNTL 0x1400 |
1459 | # define R600_VM_L2_CACHE_EN (1 << 0) |
1460 | # define R600_VM_L2_FRAG_PROC (1 << 1) |
1461 | # define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9) |
1462 | # define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13) |
1463 | # define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14) |
1464 | |
1465 | #define R600_VM_L2_CNTL2 0x1404 |
1466 | # define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0) |
1467 | # define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1) |
1468 | #define R600_VM_L2_CNTL3 0x1408 |
1469 | # define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0) |
1470 | # define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5) |
1471 | # define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10) |
1472 | # define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0) |
1473 | # define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6) |
1474 | |
1475 | #define R600_VM_L2_STATUS 0x140c |
1476 | |
1477 | #define R600_VM_CONTEXT0_CNTL 0x1410 |
1478 | # define R600_VM_ENABLE_CONTEXT (1 << 0) |
1479 | # define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1) |
1480 | |
1481 | #define R600_VM_CONTEXT0_CNTL2 0x1430 |
1482 | #define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470 |
1483 | #define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 |
1484 | #define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0 |
1485 | #define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 |
1486 | #define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 |
1487 | #define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4 |
1488 | |
1489 | #define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c |
1490 | #define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c |
1491 | #define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c |
1492 | |
1493 | #define R600_HDP_HOST_PATH_CNTL 0x2c00 |
1494 | |
1495 | #define R600_GRBM_CNTL 0x8000 |
1496 | # define R600_GRBM_READ_TIMEOUT(x) ((x) << 0) |
1497 | |
1498 | #define R600_GRBM_STATUS 0x8010 |
1499 | # define R600_CMDFIFO_AVAIL_MASK 0x1f |
1500 | # define R700_CMDFIFO_AVAIL_MASK 0xf |
1501 | # define R600_GUI_ACTIVE (1 << 31) |
1502 | #define R600_GRBM_STATUS2 0x8014 |
1503 | #define R600_GRBM_SOFT_RESET 0x8020 |
1504 | # define R600_SOFT_RESET_CP (1 << 0) |
1505 | #define R600_WAIT_UNTIL 0x8040 |
1506 | |
1507 | #define R600_CP_SEM_WAIT_TIMER 0x85bc |
1508 | #define R600_CP_ME_CNTL 0x86d8 |
1509 | # define R600_CP_ME_HALT (1 << 28) |
1510 | #define R600_CP_QUEUE_THRESHOLDS 0x8760 |
1511 | # define R600_ROQ_IB1_START(x) ((x) << 0) |
1512 | # define R600_ROQ_IB2_START(x) ((x) << 8) |
1513 | #define R600_CP_MEQ_THRESHOLDS 0x8764 |
1514 | # define R700_STQ_SPLIT(x) ((x) << 0) |
1515 | # define R600_MEQ_END(x) ((x) << 16) |
1516 | # define R600_ROQ_END(x) ((x) << 24) |
1517 | #define R600_CP_PERFMON_CNTL 0x87fc |
1518 | #define R600_CP_RB_BASE 0xc100 |
1519 | #define R600_CP_RB_CNTL 0xc104 |
1520 | # define R600_RB_BUFSZ(x) ((x) << 0) |
1521 | # define R600_RB_BLKSZ(x) ((x) << 8) |
1522 | # define R600_BUF_SWAP_32BIT (2 << 16) |
1523 | # define R600_RB_NO_UPDATE (1 << 27) |
1524 | # define R600_RB_RPTR_WR_ENA (1 << 31) |
1525 | #define R600_CP_RB_RPTR_WR 0xc108 |
1526 | #define R600_CP_RB_RPTR_ADDR 0xc10c |
1527 | #define R600_CP_RB_RPTR_ADDR_HI 0xc110 |
1528 | #define R600_CP_RB_WPTR 0xc114 |
1529 | #define R600_CP_RB_WPTR_ADDR 0xc118 |
1530 | #define R600_CP_RB_WPTR_ADDR_HI 0xc11c |
1531 | #define R600_CP_RB_RPTR 0x8700 |
1532 | #define R600_CP_RB_WPTR_DELAY 0x8704 |
1533 | #define R600_CP_PFP_UCODE_ADDR 0xc150 |
1534 | #define R600_CP_PFP_UCODE_DATA 0xc154 |
1535 | #define R600_CP_ME_RAM_RADDR 0xc158 |
1536 | #define R600_CP_ME_RAM_WADDR 0xc15c |
1537 | #define R600_CP_ME_RAM_DATA 0xc160 |
1538 | #define R600_CP_DEBUG 0xc1fc |
1539 | |
1540 | #define R600_PA_CL_ENHANCE 0x8a14 |
1541 | # define R600_CLIP_VTX_REORDER_ENA (1 << 0) |
1542 | # define R600_NUM_CLIP_SEQ(x) ((x) << 1) |
1543 | #define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10 |
1544 | #define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20 |
1545 | #define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24 |
1546 | # define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) |
1547 | # define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) |
1548 | #define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40 |
1549 | #define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44 |
1550 | #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48 |
1551 | #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c |
1552 | # define R600_S0_X(x) ((x) << 0) |
1553 | # define R600_S0_Y(x) ((x) << 4) |
1554 | # define R600_S1_X(x) ((x) << 8) |
1555 | # define R600_S1_Y(x) ((x) << 12) |
1556 | # define R600_S2_X(x) ((x) << 16) |
1557 | # define R600_S2_Y(x) ((x) << 20) |
1558 | # define R600_S3_X(x) ((x) << 24) |
1559 | # define R600_S3_Y(x) ((x) << 28) |
1560 | # define R600_S4_X(x) ((x) << 0) |
1561 | # define R600_S4_Y(x) ((x) << 4) |
1562 | # define R600_S5_X(x) ((x) << 8) |
1563 | # define R600_S5_Y(x) ((x) << 12) |
1564 | # define R600_S6_X(x) ((x) << 16) |
1565 | # define R600_S6_Y(x) ((x) << 20) |
1566 | # define R600_S7_X(x) ((x) << 24) |
1567 | # define R600_S7_Y(x) ((x) << 28) |
1568 | #define R600_PA_SC_FIFO_SIZE 0x8bd0 |
1569 | # define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0) |
1570 | # define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8) |
1571 | # define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16) |
1572 | #define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc |
1573 | # define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0) |
1574 | # define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) |
1575 | # define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) |
1576 | #define R600_PA_SC_ENHANCE 0x8bf0 |
1577 | # define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) |
1578 | # define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) |
1579 | #define R600_PA_SC_CLIPRECT_RULE 0x2820c |
1580 | #define R700_PA_SC_EDGERULE 0x28230 |
1581 | #define R600_PA_SC_LINE_STIPPLE 0x28a0c |
1582 | #define R600_PA_SC_MODE_CNTL 0x28a4c |
1583 | #define R600_PA_SC_AA_CONFIG 0x28c04 |
1584 | |
1585 | #define R600_SX_EXPORT_BUFFER_SIZES 0x900c |
1586 | # define R600_COLOR_BUFFER_SIZE(x) ((x) << 0) |
1587 | # define R600_POSITION_BUFFER_SIZE(x) ((x) << 8) |
1588 | # define R600_SMX_BUFFER_SIZE(x) ((x) << 16) |
1589 | #define R600_SX_DEBUG_1 0x9054 |
1590 | # define R600_SMX_EVENT_RELEASE (1 << 0) |
1591 | # define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16) |
1592 | #define R700_SX_DEBUG_1 0x9058 |
1593 | # define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16) |
1594 | #define R600_SX_MISC 0x28350 |
1595 | |
1596 | #define R600_DB_DEBUG 0x9830 |
1597 | # define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) |
1598 | #define R600_DB_WATERMARKS 0x9838 |
1599 | # define R600_DEPTH_FREE(x) ((x) << 0) |
1600 | # define R600_DEPTH_FLUSH(x) ((x) << 5) |
1601 | # define R600_DEPTH_PENDING_FREE(x) ((x) << 15) |
1602 | # define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20) |
1603 | #define R700_DB_DEBUG3 0x98b0 |
1604 | # define R700_DB_CLK_OFF_DELAY(x) ((x) << 11) |
1605 | #define RV700_DB_DEBUG4 0x9b8c |
1606 | # define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) |
1607 | |
1608 | #define R600_VGT_CACHE_INVALIDATION 0x88c4 |
1609 | # define R600_CACHE_INVALIDATION(x) ((x) << 0) |
1610 | # define R600_VC_ONLY 0 |
1611 | # define R600_TC_ONLY 1 |
1612 | # define R600_VC_AND_TC 2 |
1613 | # define R700_AUTO_INVLD_EN(x) ((x) << 6) |
1614 | # define R700_NO_AUTO 0 |
1615 | # define R700_ES_AUTO 1 |
1616 | # define R700_GS_AUTO 2 |
1617 | # define R700_ES_AND_GS_AUTO 3 |
1618 | #define R600_VGT_GS_PER_ES 0x88c8 |
1619 | #define R600_VGT_ES_PER_GS 0x88cc |
1620 | #define R600_VGT_GS_PER_VS 0x88e8 |
1621 | #define R600_VGT_GS_VERTEX_REUSE 0x88d4 |
1622 | #define R600_VGT_NUM_INSTANCES 0x8974 |
1623 | #define R600_VGT_STRMOUT_EN 0x28ab0 |
1624 | #define R600_VGT_EVENT_INITIATOR 0x28a90 |
1625 | # define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) |
1626 | #define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58 |
1627 | # define R600_VTX_REUSE_DEPTH_MASK 0xff |
1628 | #define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c |
1629 | # define R600_DEALLOC_DIST_MASK 0x7f |
1630 | |
1631 | #define R600_CB_COLOR0_BASE 0x28040 |
1632 | #define R600_CB_COLOR1_BASE 0x28044 |
1633 | #define R600_CB_COLOR2_BASE 0x28048 |
1634 | #define R600_CB_COLOR3_BASE 0x2804c |
1635 | #define R600_CB_COLOR4_BASE 0x28050 |
1636 | #define R600_CB_COLOR5_BASE 0x28054 |
1637 | #define R600_CB_COLOR6_BASE 0x28058 |
1638 | #define R600_CB_COLOR7_BASE 0x2805c |
1639 | #define R600_CB_COLOR7_FRAG 0x280fc |
1640 | |
1641 | #define R600_CB_COLOR0_SIZE 0x28060 |
1642 | #define R600_CB_COLOR0_VIEW 0x28080 |
1643 | #define R600_CB_COLOR0_INFO 0x280a0 |
1644 | #define R600_CB_COLOR0_TILE 0x280c0 |
1645 | #define R600_CB_COLOR0_FRAG 0x280e0 |
1646 | #define R600_CB_COLOR0_MASK 0x28100 |
1647 | |
1648 | #define AVIVO_D1MODE_VLINE_START_END 0x6538 |
1649 | #define AVIVO_D2MODE_VLINE_START_END 0x6d38 |
1650 | #define R600_CP_COHER_BASE 0x85f8 |
1651 | #define R600_DB_DEPTH_BASE 0x2800c |
1652 | #define R600_SQ_PGM_START_FS 0x28894 |
1653 | #define R600_SQ_PGM_START_ES 0x28880 |
1654 | #define R600_SQ_PGM_START_VS 0x28858 |
1655 | #define R600_SQ_PGM_RESOURCES_VS 0x28868 |
1656 | #define R600_SQ_PGM_CF_OFFSET_VS 0x288d0 |
1657 | #define R600_SQ_PGM_START_GS 0x2886c |
1658 | #define R600_SQ_PGM_START_PS 0x28840 |
1659 | #define R600_SQ_PGM_RESOURCES_PS 0x28850 |
1660 | #define R600_SQ_PGM_EXPORTS_PS 0x28854 |
1661 | #define R600_SQ_PGM_CF_OFFSET_PS 0x288cc |
1662 | #define R600_VGT_DMA_BASE 0x287e8 |
1663 | #define R600_VGT_DMA_BASE_HI 0x287e4 |
1664 | #define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10 |
1665 | #define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14 |
1666 | #define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18 |
1667 | #define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c |
1668 | #define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44 |
1669 | #define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48 |
1670 | #define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c |
1671 | #define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50 |
1672 | #define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8 |
1673 | #define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8 |
1674 | #define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8 |
1675 | #define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08 |
1676 | #define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc |
1677 | #define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec |
1678 | #define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc |
1679 | #define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c |
1680 | |
1681 | #define R600_VGT_PRIMITIVE_TYPE 0x8958 |
1682 | |
1683 | #define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030 |
1684 | #define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240 |
1685 | #define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204 |
1686 | |
1687 | #define R600_TC_CNTL 0x9608 |
1688 | # define R600_TC_L2_SIZE(x) ((x) << 5) |
1689 | # define R600_L2_DISABLE_LATE_HIT (1 << 9) |
1690 | |
1691 | #define R600_ARB_POP 0x2418 |
1692 | # define R600_ENABLE_TC128 (1 << 30) |
1693 | #define R600_ARB_GDEC_RD_CNTL 0x246c |
1694 | |
1695 | #define R600_TA_CNTL_AUX 0x9508 |
1696 | # define R600_DISABLE_CUBE_WRAP (1 << 0) |
1697 | # define R600_DISABLE_CUBE_ANISO (1 << 1) |
1698 | # define R700_GETLOD_SELECT(x) ((x) << 2) |
1699 | # define R600_SYNC_GRADIENT (1 << 24) |
1700 | # define R600_SYNC_WALKER (1 << 25) |
1701 | # define R600_SYNC_ALIGNER (1 << 26) |
1702 | # define R600_BILINEAR_PRECISION_6_BIT (0 << 31) |
1703 | # define R600_BILINEAR_PRECISION_8_BIT (1 << 31) |
1704 | |
1705 | #define R700_TCP_CNTL 0x9610 |
1706 | |
1707 | #define R600_SMX_DC_CTL0 0xa020 |
1708 | # define R700_USE_HASH_FUNCTION (1 << 0) |
1709 | # define R700_CACHE_DEPTH(x) ((x) << 1) |
1710 | # define R700_FLUSH_ALL_ON_EVENT (1 << 10) |
1711 | # define R700_STALL_ON_EVENT (1 << 11) |
1712 | #define R700_SMX_EVENT_CTL 0xa02c |
1713 | # define R700_ES_FLUSH_CTL(x) ((x) << 0) |
1714 | # define R700_GS_FLUSH_CTL(x) ((x) << 3) |
1715 | # define R700_ACK_FLUSH_CTL(x) ((x) << 6) |
1716 | # define R700_SYNC_FLUSH_CTL (1 << 8) |
1717 | |
1718 | #define R600_SQ_CONFIG 0x8c00 |
1719 | # define R600_VC_ENABLE (1 << 0) |
1720 | # define R600_EXPORT_SRC_C (1 << 1) |
1721 | # define R600_DX9_CONSTS (1 << 2) |
1722 | # define R600_ALU_INST_PREFER_VECTOR (1 << 3) |
1723 | # define R600_DX10_CLAMP (1 << 4) |
1724 | # define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8) |
1725 | # define R600_PS_PRIO(x) ((x) << 24) |
1726 | # define R600_VS_PRIO(x) ((x) << 26) |
1727 | # define R600_GS_PRIO(x) ((x) << 28) |
1728 | # define R600_ES_PRIO(x) ((x) << 30) |
1729 | #define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04 |
1730 | # define R600_NUM_PS_GPRS(x) ((x) << 0) |
1731 | # define R600_NUM_VS_GPRS(x) ((x) << 16) |
1732 | # define R700_DYN_GPR_ENABLE (1 << 27) |
1733 | # define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) |
1734 | #define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08 |
1735 | # define R600_NUM_GS_GPRS(x) ((x) << 0) |
1736 | # define R600_NUM_ES_GPRS(x) ((x) << 16) |
1737 | #define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c |
1738 | # define R600_NUM_PS_THREADS(x) ((x) << 0) |
1739 | # define R600_NUM_VS_THREADS(x) ((x) << 8) |
1740 | # define R600_NUM_GS_THREADS(x) ((x) << 16) |
1741 | # define R600_NUM_ES_THREADS(x) ((x) << 24) |
1742 | #define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10 |
1743 | # define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0) |
1744 | # define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16) |
1745 | #define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14 |
1746 | # define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0) |
1747 | # define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16) |
1748 | #define R600_SQ_MS_FIFO_SIZES 0x8cf0 |
1749 | # define R600_CACHE_FIFO_SIZE(x) ((x) << 0) |
1750 | # define R600_FETCH_FIFO_HIWATER(x) ((x) << 8) |
1751 | # define R600_DONE_FIFO_HIWATER(x) ((x) << 16) |
1752 | # define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) |
1753 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0 |
1754 | # define R700_SIMDA_RING0(x) ((x) << 0) |
1755 | # define R700_SIMDA_RING1(x) ((x) << 8) |
1756 | # define R700_SIMDB_RING0(x) ((x) << 16) |
1757 | # define R700_SIMDB_RING1(x) ((x) << 24) |
1758 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4 |
1759 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8 |
1760 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc |
1761 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0 |
1762 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4 |
1763 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8 |
1764 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc |
1765 | |
1766 | #define R600_SPI_PS_IN_CONTROL_0 0x286cc |
1767 | # define R600_NUM_INTERP(x) ((x) << 0) |
1768 | # define R600_POSITION_ENA (1 << 8) |
1769 | # define R600_POSITION_CENTROID (1 << 9) |
1770 | # define R600_POSITION_ADDR(x) ((x) << 10) |
1771 | # define R600_PARAM_GEN(x) ((x) << 15) |
1772 | # define R600_PARAM_GEN_ADDR(x) ((x) << 19) |
1773 | # define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26) |
1774 | # define R600_PERSP_GRADIENT_ENA (1 << 28) |
1775 | # define R600_LINEAR_GRADIENT_ENA (1 << 29) |
1776 | # define R600_POSITION_SAMPLE (1 << 30) |
1777 | # define R600_BARYC_AT_SAMPLE_ENA (1 << 31) |
1778 | #define R600_SPI_PS_IN_CONTROL_1 0x286d0 |
1779 | # define R600_GEN_INDEX_PIX (1 << 0) |
1780 | # define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1) |
1781 | # define R600_FRONT_FACE_ENA (1 << 8) |
1782 | # define R600_FRONT_FACE_CHAN(x) ((x) << 9) |
1783 | # define R600_FRONT_FACE_ALL_BITS (1 << 11) |
1784 | # define R600_FRONT_FACE_ADDR(x) ((x) << 12) |
1785 | # define R600_FOG_ADDR(x) ((x) << 17) |
1786 | # define R600_FIXED_PT_POSITION_ENA (1 << 24) |
1787 | # define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25) |
1788 | # define R700_POSITION_ULC (1 << 30) |
1789 | #define R600_SPI_INPUT_Z 0x286d8 |
1790 | |
1791 | #define R600_SPI_CONFIG_CNTL 0x9100 |
1792 | # define R600_GPR_WRITE_PRIORITY(x) ((x) << 0) |
1793 | # define R600_DISABLE_INTERP_1 (1 << 5) |
1794 | #define R600_SPI_CONFIG_CNTL_1 0x913c |
1795 | # define R600_VTX_DONE_DELAY(x) ((x) << 0) |
1796 | # define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4) |
1797 | |
1798 | #define R600_GB_TILING_CONFIG 0x98f0 |
1799 | # define R600_PIPE_TILING(x) ((x) << 1) |
1800 | # define R600_BANK_TILING(x) ((x) << 4) |
1801 | # define R600_GROUP_SIZE(x) ((x) << 6) |
1802 | # define R600_ROW_TILING(x) ((x) << 8) |
1803 | # define R600_BANK_SWAPS(x) ((x) << 11) |
1804 | # define R600_SAMPLE_SPLIT(x) ((x) << 14) |
1805 | # define R600_BACKEND_MAP(x) ((x) << 16) |
1806 | #define R600_DCP_TILING_CONFIG 0x6ca0 |
1807 | #define R600_HDP_TILING_CONFIG 0x2f3c |
1808 | |
1809 | #define R600_CC_RB_BACKEND_DISABLE 0x98f4 |
1810 | #define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88 |
1811 | # define R600_BACKEND_DISABLE(x) ((x) << 16) |
1812 | |
1813 | #define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950 |
1814 | #define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954 |
1815 | # define R600_INACTIVE_QD_PIPES(x) ((x) << 8) |
1816 | # define R600_INACTIVE_QD_PIPES_MASK (0xff << 8) |
1817 | # define R600_INACTIVE_SIMDS(x) ((x) << 16) |
1818 | # define R600_INACTIVE_SIMDS_MASK (0xff << 16) |
1819 | |
1820 | #define R700_CGTS_SYS_TCC_DISABLE 0x3f90 |
1821 | #define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94 |
1822 | #define R700_CGTS_TCC_DISABLE 0x9148 |
1823 | #define R700_CGTS_USER_TCC_DISABLE 0x914c |
1824 | |
1825 | /* Constants */ |
1826 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
1827 | |
1828 | #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 |
1829 | #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 |
1830 | #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 |
1831 | #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 |
1832 | #define RADEON_LAST_DISPATCH 1 |
1833 | |
1834 | #define R600_LAST_FRAME_REG R600_SCRATCH_REG0 |
1835 | #define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1 |
1836 | #define R600_LAST_CLEAR_REG R600_SCRATCH_REG2 |
1837 | #define R600_LAST_SWI_REG R600_SCRATCH_REG3 |
1838 | |
1839 | #define RADEON_MAX_VB_AGE 0x7fffffff |
1840 | #define RADEON_MAX_VB_VERTS (0xffff) |
1841 | |
1842 | #define RADEON_RING_HIGH_MARK 128 |
1843 | |
1844 | #define RADEON_PCIGART_TABLE_SIZE (32*1024) |
1845 | |
1846 | #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) |
1847 | #define RADEON_WRITE(reg, val) \ |
1848 | do { \ |
1849 | if (reg < 0x10000) { \ |
1850 | DRM_WRITE32(dev_priv->mmio, (reg), (val)); \ |
1851 | } else { \ |
1852 | DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \ |
1853 | DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \ |
1854 | } \ |
1855 | } while (0) |
1856 | #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) |
1857 | #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) |
1858 | |
1859 | #define RADEON_WRITE_PLL(addr, val) \ |
1860 | do { \ |
1861 | RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ |
1862 | ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ |
1863 | RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ |
1864 | } while (0) |
1865 | |
1866 | #define RADEON_WRITE_PCIE(addr, val) \ |
1867 | do { \ |
1868 | RADEON_WRITE8(RADEON_PCIE_INDEX, \ |
1869 | ((addr) & 0xff)); \ |
1870 | RADEON_WRITE(RADEON_PCIE_DATA, (val)); \ |
1871 | } while (0) |
1872 | |
1873 | #define R500_WRITE_MCIND(addr, val) \ |
1874 | do { \ |
1875 | RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ |
1876 | RADEON_WRITE(R520_MC_IND_DATA, (val)); \ |
1877 | RADEON_WRITE(R520_MC_IND_INDEX, 0); \ |
1878 | } while (0) |
1879 | |
1880 | #define RS480_WRITE_MCIND(addr, val) \ |
1881 | do { \ |
1882 | RADEON_WRITE(RS480_NB_MC_INDEX, \ |
1883 | ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ |
1884 | RADEON_WRITE(RS480_NB_MC_DATA, (val)); \ |
1885 | RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \ |
1886 | } while (0) |
1887 | |
1888 | #define RS690_WRITE_MCIND(addr, val) \ |
1889 | do { \ |
1890 | RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ |
1891 | RADEON_WRITE(RS690_MC_DATA, val); \ |
1892 | RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ |
1893 | } while (0) |
1894 | |
1895 | #define RS600_WRITE_MCIND(addr, val) \ |
1896 | do { \ |
1897 | RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \ |
1898 | RADEON_WRITE(RS600_MC_DATA, val); \ |
1899 | } while (0) |
1900 | |
1901 | #define IGP_WRITE_MCIND(addr, val) \ |
1902 | do { \ |
1903 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ |
1904 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ |
1905 | RS690_WRITE_MCIND(addr, val); \ |
1906 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \ |
1907 | RS600_WRITE_MCIND(addr, val); \ |
1908 | else \ |
1909 | RS480_WRITE_MCIND(addr, val); \ |
1910 | } while (0) |
1911 | |
1912 | #define CP_PACKET0( reg, n ) \ |
1913 | (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) |
1914 | #define CP_PACKET0_TABLE( reg, n ) \ |
1915 | (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) |
1916 | #define CP_PACKET1( reg0, reg1 ) \ |
1917 | (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) |
1918 | #define CP_PACKET2() \ |
1919 | (RADEON_CP_PACKET2) |
1920 | #define CP_PACKET3( pkt, n ) \ |
1921 | (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) |
1922 | |
1923 | /* ================================================================ |
1924 | * Engine control helper macros |
1925 | */ |
1926 | |
1927 | #define RADEON_WAIT_UNTIL_2D_IDLE() do { \ |
1928 | OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ |
1929 | OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ |
1930 | RADEON_WAIT_HOST_IDLECLEAN) ); \ |
1931 | } while (0) |
1932 | |
1933 | #define RADEON_WAIT_UNTIL_3D_IDLE() do { \ |
1934 | OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ |
1935 | OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ |
1936 | RADEON_WAIT_HOST_IDLECLEAN) ); \ |
1937 | } while (0) |
1938 | |
1939 | #define RADEON_WAIT_UNTIL_IDLE() do { \ |
1940 | OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ |
1941 | OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ |
1942 | RADEON_WAIT_3D_IDLECLEAN | \ |
1943 | RADEON_WAIT_HOST_IDLECLEAN) ); \ |
1944 | } while (0) |
1945 | |
1946 | #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ |
1947 | OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ |
1948 | OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ |
1949 | } while (0) |
1950 | |
1951 | #define RADEON_FLUSH_CACHE() do { \ |
1952 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1953 | OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ |
1954 | OUT_RING(RADEON_RB3D_DC_FLUSH); \ |
1955 | } else { \ |
1956 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ |
1957 | OUT_RING(R300_RB3D_DC_FLUSH); \ |
1958 | } \ |
1959 | } while (0) |
1960 | |
1961 | #define RADEON_PURGE_CACHE() do { \ |
1962 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1963 | OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ |
1964 | OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ |
1965 | } else { \ |
1966 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ |
1967 | OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \ |
1968 | } \ |
1969 | } while (0) |
1970 | |
1971 | #define RADEON_FLUSH_ZCACHE() do { \ |
1972 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1973 | OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ |
1974 | OUT_RING(RADEON_RB3D_ZC_FLUSH); \ |
1975 | } else { \ |
1976 | OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ |
1977 | OUT_RING(R300_ZC_FLUSH); \ |
1978 | } \ |
1979 | } while (0) |
1980 | |
1981 | #define RADEON_PURGE_ZCACHE() do { \ |
1982 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1983 | OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ |
1984 | OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ |
1985 | } else { \ |
1986 | OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ |
1987 | OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ |
1988 | } \ |
1989 | } while (0) |
1990 | |
1991 | /* ================================================================ |
1992 | * Misc helper macros |
1993 | */ |
1994 | |
1995 | /* Perfbox functionality only. |
1996 | */ |
1997 | #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ |
1998 | do { \ |
1999 | if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ |
2000 | u32 head = GET_RING_HEAD( dev_priv ); \ |
2001 | if (head == dev_priv->ring.tail) \ |
2002 | dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ |
2003 | } \ |
2004 | } while (0) |
2005 | |
2006 | #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ |
2007 | do { \ |
2008 | struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \ |
2009 | drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \ |
2010 | if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ |
2011 | int __ret; \ |
2012 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ |
2013 | __ret = r600_do_cp_idle(dev_priv); \ |
2014 | else \ |
2015 | __ret = radeon_do_cp_idle(dev_priv); \ |
2016 | if ( __ret ) return __ret; \ |
2017 | sarea_priv->last_dispatch = 0; \ |
2018 | radeon_freelist_reset( dev ); \ |
2019 | } \ |
2020 | } while (0) |
2021 | |
2022 | #define RADEON_DISPATCH_AGE( age ) do { \ |
2023 | OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ |
2024 | OUT_RING( age ); \ |
2025 | } while (0) |
2026 | |
2027 | #define RADEON_FRAME_AGE( age ) do { \ |
2028 | OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ |
2029 | OUT_RING( age ); \ |
2030 | } while (0) |
2031 | |
2032 | #define RADEON_CLEAR_AGE( age ) do { \ |
2033 | OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ |
2034 | OUT_RING( age ); \ |
2035 | } while (0) |
2036 | |
2037 | #define R600_DISPATCH_AGE(age) do { \ |
2038 | OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ |
2039 | OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ |
2040 | OUT_RING(age); \ |
2041 | } while (0) |
2042 | |
2043 | #define R600_FRAME_AGE(age) do { \ |
2044 | OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ |
2045 | OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ |
2046 | OUT_RING(age); \ |
2047 | } while (0) |
2048 | |
2049 | #define R600_CLEAR_AGE(age) do { \ |
2050 | OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ |
2051 | OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ |
2052 | OUT_RING(age); \ |
2053 | } while (0) |
2054 | |
2055 | /* ================================================================ |
2056 | * Ring control |
2057 | */ |
2058 | |
2059 | #define RADEON_VERBOSE 0 |
2060 | |
2061 | #define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring; |
2062 | |
2063 | #define RADEON_RING_ALIGN 16 |
2064 | |
2065 | #define BEGIN_RING( n ) do { \ |
2066 | if ( RADEON_VERBOSE ) { \ |
2067 | DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ |
2068 | } \ |
2069 | _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN-1)); \ |
2070 | _align_nr += n; \ |
2071 | if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \ |
2072 | COMMIT_RING(); \ |
2073 | radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \ |
2074 | } \ |
2075 | _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ |
2076 | ring = dev_priv->ring.start; \ |
2077 | write = dev_priv->ring.tail; \ |
2078 | mask = dev_priv->ring.tail_mask; \ |
2079 | } while (0) |
2080 | |
2081 | #define ADVANCE_RING() do { \ |
2082 | if ( RADEON_VERBOSE ) { \ |
2083 | DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ |
2084 | write, dev_priv->ring.tail ); \ |
2085 | } \ |
2086 | if (((dev_priv->ring.tail + _nr) & mask) != write) { \ |
2087 | DRM_ERROR( \ |
2088 | "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ |
2089 | ((dev_priv->ring.tail + _nr) & mask), \ |
2090 | write, __LINE__); \ |
2091 | } else \ |
2092 | dev_priv->ring.tail = write; \ |
2093 | } while (0) |
2094 | |
2095 | extern void radeon_commit_ring(drm_radeon_private_t *dev_priv); |
2096 | |
2097 | #define COMMIT_RING() do { \ |
2098 | radeon_commit_ring(dev_priv); \ |
2099 | } while(0) |
2100 | |
2101 | #define OUT_RING( x ) do { \ |
2102 | if ( RADEON_VERBOSE ) { \ |
2103 | DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ |
2104 | (unsigned int)(x), write ); \ |
2105 | } \ |
2106 | ring[write++] = (x); \ |
2107 | write &= mask; \ |
2108 | } while (0) |
2109 | |
2110 | #define OUT_RING_REG( reg, val ) do { \ |
2111 | OUT_RING( CP_PACKET0( reg, 0 ) ); \ |
2112 | OUT_RING( val ); \ |
2113 | } while (0) |
2114 | |
2115 | #define OUT_RING_TABLE( tab, sz ) do { \ |
2116 | int _size = (sz); \ |
2117 | int *_tab = (int *)(tab); \ |
2118 | \ |
2119 | if (write + _size > mask) { \ |
2120 | int _i = (mask+1) - write; \ |
2121 | _size -= _i; \ |
2122 | while (_i > 0 ) { \ |
2123 | *(int *)(ring + write) = *_tab++; \ |
2124 | write++; \ |
2125 | _i--; \ |
2126 | } \ |
2127 | write = 0; \ |
2128 | _tab += _i; \ |
2129 | } \ |
2130 | while (_size > 0) { \ |
2131 | *(ring + write) = *_tab++; \ |
2132 | write++; \ |
2133 | _size--; \ |
2134 | } \ |
2135 | write &= mask; \ |
2136 | } while (0) |
2137 | |
2138 | /** |
2139 | * Copy given number of dwords from drm buffer to the ring buffer. |
2140 | */ |
2141 | #define OUT_RING_DRM_BUFFER(buf, sz) do { \ |
2142 | int _size = (sz) * 4; \ |
2143 | struct drm_buffer *_buf = (buf); \ |
2144 | int _part_size; \ |
2145 | while (_size > 0) { \ |
2146 | _part_size = _size; \ |
2147 | \ |
2148 | if (write + _part_size/4 > mask) \ |
2149 | _part_size = ((mask + 1) - write)*4; \ |
2150 | \ |
2151 | if (drm_buffer_index(_buf) + _part_size > PAGE_SIZE) \ |
2152 | _part_size = PAGE_SIZE - drm_buffer_index(_buf);\ |
2153 | \ |
2154 | \ |
2155 | \ |
2156 | memcpy(ring + write, &_buf->data[drm_buffer_page(_buf)] \ |
2157 | [drm_buffer_index(_buf)], _part_size); \ |
2158 | \ |
2159 | _size -= _part_size; \ |
2160 | write = (write + _part_size/4) & mask; \ |
2161 | drm_buffer_advance(_buf, _part_size); \ |
2162 | } \ |
2163 | } while (0) |
2164 | |
2165 | |
2166 | #endif /* CONFIG_DRM_RADEON_UMS */ |
2167 | |
2168 | #endif /* __RADEON_DRV_H__ */ |
2169 | |