1 | /* $NetBSD: nouveau_dispnv04_hw.c,v 1.2 2014/08/06 15:01:34 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2006 Dave Airlie |
5 | * Copyright 2007 Maarten Maathuis |
6 | * Copyright 2007-2009 Stuart Bennett |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a |
9 | * copy of this software and associated documentation files (the "Software"), |
10 | * to deal in the Software without restriction, including without limitation |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
12 | * and/or sell copies of the Software, and to permit persons to whom the |
13 | * Software is furnished to do so, subject to the following conditions: |
14 | * |
15 | * The above copyright notice and this permission notice shall be included in |
16 | * all copies or substantial portions of the Software. |
17 | * |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
21 | * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
22 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
23 | * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
24 | * SOFTWARE. |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_dispnv04_hw.c,v 1.2 2014/08/06 15:01:34 riastradh Exp $" ); |
29 | |
30 | #include <drm/drmP.h> |
31 | #include "nouveau_drm.h" |
32 | #include "hw.h" |
33 | |
34 | #include <subdev/bios/pll.h> |
35 | #include <subdev/fb.h> |
36 | #include <subdev/clock.h> |
37 | #include <subdev/timer.h> |
38 | |
39 | #define CHIPSET_NFORCE 0x01a0 |
40 | #define CHIPSET_NFORCE2 0x01f0 |
41 | |
42 | /* |
43 | * misc hw access wrappers/control functions |
44 | */ |
45 | |
46 | void |
47 | NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value) |
48 | { |
49 | NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); |
50 | NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value); |
51 | } |
52 | |
53 | uint8_t |
54 | NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index) |
55 | { |
56 | NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); |
57 | return NVReadPRMVIO(dev, head, NV_PRMVIO_SR); |
58 | } |
59 | |
60 | void |
61 | NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value) |
62 | { |
63 | NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); |
64 | NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value); |
65 | } |
66 | |
67 | uint8_t |
68 | NVReadVgaGr(struct drm_device *dev, int head, uint8_t index) |
69 | { |
70 | NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); |
71 | return NVReadPRMVIO(dev, head, NV_PRMVIO_GX); |
72 | } |
73 | |
74 | /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied) |
75 | * it affects only the 8 bit vga io regs, which we access using mmio at |
76 | * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d* |
77 | * in general, the set value of cr44 does not matter: reg access works as |
78 | * expected and values can be set for the appropriate head by using a 0x2000 |
79 | * offset as required |
80 | * however: |
81 | * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and |
82 | * cr44 must be set to 0 or 3 for accessing values on the correct head |
83 | * through the common 0xc03c* addresses |
84 | * b) in tied mode (4) head B is programmed to the values set on head A, and |
85 | * access using the head B addresses can have strange results, ergo we leave |
86 | * tied mode in init once we know to what cr44 should be restored on exit |
87 | * |
88 | * the owner parameter is slightly abused: |
89 | * 0 and 1 are treated as head values and so the set value is (owner * 3) |
90 | * other values are treated as literal values to set |
91 | */ |
92 | void |
93 | NVSetOwner(struct drm_device *dev, int owner) |
94 | { |
95 | struct nouveau_drm *drm = nouveau_drm(dev); |
96 | |
97 | if (owner == 1) |
98 | owner *= 3; |
99 | |
100 | if (nv_device(drm->device)->chipset == 0x11) { |
101 | /* This might seem stupid, but the blob does it and |
102 | * omitting it often locks the system up. |
103 | */ |
104 | NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX); |
105 | NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX); |
106 | } |
107 | |
108 | /* CR44 is always changed on CRTC0 */ |
109 | NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner); |
110 | |
111 | if (nv_device(drm->device)->chipset == 0x11) { /* set me harder */ |
112 | NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); |
113 | NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); |
114 | } |
115 | } |
116 | |
117 | void |
118 | NVBlankScreen(struct drm_device *dev, int head, bool blank) |
119 | { |
120 | unsigned char seq1; |
121 | |
122 | if (nv_two_heads(dev)) |
123 | NVSetOwner(dev, head); |
124 | |
125 | seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); |
126 | |
127 | NVVgaSeqReset(dev, head, true); |
128 | if (blank) |
129 | NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); |
130 | else |
131 | NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); |
132 | NVVgaSeqReset(dev, head, false); |
133 | } |
134 | |
135 | /* |
136 | * PLL getting |
137 | */ |
138 | |
139 | static void |
140 | nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, |
141 | uint32_t pll2, struct nouveau_pll_vals *pllvals) |
142 | { |
143 | struct nouveau_drm *drm = nouveau_drm(dev); |
144 | |
145 | /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ |
146 | |
147 | /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */ |
148 | pllvals->log2P = (pll1 >> 16) & 0x7; |
149 | pllvals->N2 = pllvals->M2 = 1; |
150 | |
151 | if (reg1 <= 0x405c) { |
152 | pllvals->NM1 = pll2 & 0xffff; |
153 | /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */ |
154 | if (!(pll1 & 0x1100)) |
155 | pllvals->NM2 = pll2 >> 16; |
156 | } else { |
157 | pllvals->NM1 = pll1 & 0xffff; |
158 | if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) |
159 | pllvals->NM2 = pll2 & 0xffff; |
160 | else if (nv_device(drm->device)->chipset == 0x30 || nv_device(drm->device)->chipset == 0x35) { |
161 | pllvals->M1 &= 0xf; /* only 4 bits */ |
162 | if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { |
163 | pllvals->M2 = (pll1 >> 4) & 0x7; |
164 | pllvals->N2 = ((pll1 >> 21) & 0x18) | |
165 | ((pll1 >> 19) & 0x7); |
166 | } |
167 | } |
168 | } |
169 | } |
170 | |
171 | int |
172 | nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, |
173 | struct nouveau_pll_vals *pllvals) |
174 | { |
175 | struct nouveau_drm *drm = nouveau_drm(dev); |
176 | struct nouveau_device *device = nv_device(drm->device); |
177 | struct nouveau_bios *bios = nouveau_bios(device); |
178 | uint32_t reg1, pll1, pll2 = 0; |
179 | struct nvbios_pll pll_lim; |
180 | int ret; |
181 | |
182 | ret = nvbios_pll_parse(bios, plltype, &pll_lim); |
183 | if (ret || !(reg1 = pll_lim.reg)) |
184 | return -ENOENT; |
185 | |
186 | pll1 = nv_rd32(device, reg1); |
187 | if (reg1 <= 0x405c) |
188 | pll2 = nv_rd32(device, reg1 + 4); |
189 | else if (nv_two_reg_pll(dev)) { |
190 | uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); |
191 | |
192 | pll2 = nv_rd32(device, reg2); |
193 | } |
194 | |
195 | if (nv_device(drm->device)->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) { |
196 | uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580); |
197 | |
198 | /* check whether vpll has been forced into single stage mode */ |
199 | if (reg1 == NV_PRAMDAC_VPLL_COEFF) { |
200 | if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE) |
201 | pll2 = 0; |
202 | } else |
203 | if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE) |
204 | pll2 = 0; |
205 | } |
206 | |
207 | nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); |
208 | pllvals->refclk = pll_lim.refclk; |
209 | return 0; |
210 | } |
211 | |
212 | int |
213 | nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pv) |
214 | { |
215 | /* Avoid divide by zero if called at an inappropriate time */ |
216 | if (!pv->M1 || !pv->M2) |
217 | return 0; |
218 | |
219 | return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; |
220 | } |
221 | |
222 | int |
223 | nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype) |
224 | { |
225 | struct nouveau_pll_vals pllvals; |
226 | int ret; |
227 | |
228 | if (plltype == PLL_MEMORY && |
229 | (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) { |
230 | uint32_t mpllP; |
231 | |
232 | pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP); |
233 | if (!mpllP) |
234 | mpllP = 4; |
235 | |
236 | return 400000 / mpllP; |
237 | } else |
238 | if (plltype == PLL_MEMORY && |
239 | (dev->pdev->device & 0xff0) == CHIPSET_NFORCE2) { |
240 | uint32_t clock; |
241 | |
242 | pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock); |
243 | return clock; |
244 | } |
245 | |
246 | ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals); |
247 | if (ret) |
248 | return ret; |
249 | |
250 | return nouveau_hw_pllvals_to_clk(&pllvals); |
251 | } |
252 | |
253 | static void |
254 | nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) |
255 | { |
256 | /* the vpll on an unused head can come up with a random value, way |
257 | * beyond the pll limits. for some reason this causes the chip to |
258 | * lock up when reading the dac palette regs, so set a valid pll here |
259 | * when such a condition detected. only seen on nv11 to date |
260 | */ |
261 | |
262 | struct nouveau_drm *drm = nouveau_drm(dev); |
263 | struct nouveau_device *device = nv_device(drm->device); |
264 | struct nouveau_clock *clk = nouveau_clock(device); |
265 | struct nouveau_bios *bios = nouveau_bios(device); |
266 | struct nvbios_pll pll_lim; |
267 | struct nouveau_pll_vals pv; |
268 | enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; |
269 | |
270 | if (nvbios_pll_parse(bios, pll, &pll_lim)) |
271 | return; |
272 | nouveau_hw_get_pllvals(dev, pll, &pv); |
273 | |
274 | if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m && |
275 | pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n && |
276 | pv.log2P <= pll_lim.max_p) |
277 | return; |
278 | |
279 | NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n" , head + 1); |
280 | |
281 | /* set lowest clock within static limits */ |
282 | pv.M1 = pll_lim.vco1.max_m; |
283 | pv.N1 = pll_lim.vco1.min_n; |
284 | pv.log2P = pll_lim.max_p_usable; |
285 | clk->pll_prog(clk, pll_lim.reg, &pv); |
286 | } |
287 | |
288 | /* |
289 | * vga font save/restore |
290 | */ |
291 | |
292 | static void nouveau_vga_font_io(struct drm_device *dev, |
293 | #ifdef __NetBSD__ |
294 | bus_space_tag_t iovramt, |
295 | bus_space_handle_t iovramh, |
296 | #else |
297 | void __iomem *iovram, |
298 | #endif |
299 | bool save, unsigned plane) |
300 | { |
301 | unsigned i; |
302 | |
303 | NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane); |
304 | NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane); |
305 | for (i = 0; i < 16384; i++) { |
306 | if (save) { |
307 | #ifdef __NetBSD__ |
308 | nv04_display(dev)->saved_vga_font[plane][i] = |
309 | bus_space_read_stream_4(iovramt, iovramh, i * 4); |
310 | #else |
311 | nv04_display(dev)->saved_vga_font[plane][i] = |
312 | ioread32_native(iovram + i * 4); |
313 | #endif |
314 | } else { |
315 | #ifdef __NetBSD__ |
316 | bus_space_write_stream_4(iovramt, iovramh, i * 4, |
317 | nv04_display(dev)->saved_vga_font[plane][i]); |
318 | #else |
319 | iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i], |
320 | iovram + i * 4); |
321 | #endif |
322 | } |
323 | } |
324 | } |
325 | |
326 | void |
327 | nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save) |
328 | { |
329 | struct nouveau_drm *drm = nouveau_drm(dev); |
330 | uint8_t misc, gr4, gr5, gr6, seq2, seq4; |
331 | bool graphicsmode; |
332 | unsigned plane; |
333 | #ifdef __NetBSD__ |
334 | bus_space_tag_t iovramt; |
335 | bus_space_handle_t iovramh; |
336 | bus_size_t iovramsz; |
337 | #else |
338 | void __iomem *iovram; |
339 | #endif |
340 | |
341 | if (nv_two_heads(dev)) |
342 | NVSetOwner(dev, 0); |
343 | |
344 | NVSetEnablePalette(dev, 0, true); |
345 | graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1; |
346 | NVSetEnablePalette(dev, 0, false); |
347 | |
348 | if (graphicsmode) /* graphics mode => framebuffer => no need to save */ |
349 | return; |
350 | |
351 | NV_INFO(drm, "%sing VGA fonts\n" , save ? "Sav" : "Restor" ); |
352 | |
353 | /* map first 64KiB of VRAM, holds VGA fonts etc */ |
354 | #ifdef __NetBSD__ |
355 | if (pci_mapreg_map(&dev->pdev->pd_pa, PCI_BAR(1), |
356 | pci_mapreg_type(dev->pdev->pd_pa.pa_pc, |
357 | dev->pdev->pd_pa.pa_tag, PCI_BAR(1)), |
358 | 0, &iovramt, &iovramh, NULL, &iovramsz)) { |
359 | NV_ERROR(drm, "Failed to map VRAM, " |
360 | "cannot save/restore VGA fonts.\n" ); |
361 | return; |
362 | } |
363 | #else |
364 | iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536); |
365 | if (!iovram) { |
366 | NV_ERROR(drm, "Failed to map VRAM, " |
367 | "cannot save/restore VGA fonts.\n" ); |
368 | return; |
369 | } |
370 | #endif |
371 | |
372 | if (nv_two_heads(dev)) |
373 | NVBlankScreen(dev, 1, true); |
374 | NVBlankScreen(dev, 0, true); |
375 | |
376 | /* save control regs */ |
377 | misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ); |
378 | seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX); |
379 | seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX); |
380 | gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX); |
381 | gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX); |
382 | gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX); |
383 | |
384 | NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67); |
385 | NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6); |
386 | NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0); |
387 | NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5); |
388 | |
389 | /* store font in planes 0..3 */ |
390 | for (plane = 0; plane < 4; plane++) |
391 | #ifdef __NetBSD__ |
392 | nouveau_vga_font_io(dev, iovramt, iovramh, save, plane); |
393 | #else |
394 | nouveau_vga_font_io(dev, iovram, save, plane); |
395 | #endif |
396 | |
397 | /* restore control regs */ |
398 | NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc); |
399 | NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4); |
400 | NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5); |
401 | NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6); |
402 | NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2); |
403 | NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4); |
404 | |
405 | if (nv_two_heads(dev)) |
406 | NVBlankScreen(dev, 1, false); |
407 | NVBlankScreen(dev, 0, false); |
408 | |
409 | #ifdef __NetBSD__ |
410 | bus_space_unmap(iovramt, iovramh, iovramsz); |
411 | #else |
412 | iounmap(iovram); |
413 | #endif |
414 | } |
415 | |
416 | /* |
417 | * mode state save/load |
418 | */ |
419 | |
420 | static void |
421 | rd_cio_state(struct drm_device *dev, int head, |
422 | struct nv04_crtc_reg *crtcstate, int index) |
423 | { |
424 | crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); |
425 | } |
426 | |
427 | static void |
428 | wr_cio_state(struct drm_device *dev, int head, |
429 | struct nv04_crtc_reg *crtcstate, int index) |
430 | { |
431 | NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); |
432 | } |
433 | |
434 | static void |
435 | nv_save_state_ramdac(struct drm_device *dev, int head, |
436 | struct nv04_mode_state *state) |
437 | { |
438 | struct nouveau_drm *drm = nouveau_drm(dev); |
439 | struct nv04_crtc_reg *regp = &state->crtc_reg[head]; |
440 | int i; |
441 | |
442 | if (nv_device(drm->device)->card_type >= NV_10) |
443 | regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); |
444 | |
445 | nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); |
446 | state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT); |
447 | if (nv_two_heads(dev)) |
448 | state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); |
449 | if (nv_device(drm->device)->chipset == 0x11) |
450 | regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); |
451 | |
452 | regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); |
453 | |
454 | if (nv_gf4_disp_arch(dev)) |
455 | regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); |
456 | if (nv_device(drm->device)->chipset >= 0x30) |
457 | regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); |
458 | |
459 | regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); |
460 | regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); |
461 | regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); |
462 | regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); |
463 | regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); |
464 | regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); |
465 | regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); |
466 | regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); |
467 | |
468 | for (i = 0; i < 7; i++) { |
469 | uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); |
470 | regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); |
471 | regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); |
472 | } |
473 | |
474 | if (nv_gf4_disp_arch(dev)) { |
475 | regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); |
476 | for (i = 0; i < 3; i++) { |
477 | regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); |
478 | regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); |
479 | } |
480 | } |
481 | |
482 | regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); |
483 | regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); |
484 | if (!nv_gf4_disp_arch(dev) && head == 0) { |
485 | /* early chips don't allow access to PRAMDAC_TMDS_* without |
486 | * the head A FPCLK on (nv11 even locks up) */ |
487 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 & |
488 | ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK); |
489 | } |
490 | regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); |
491 | regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); |
492 | |
493 | regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); |
494 | |
495 | if (nv_gf4_disp_arch(dev)) |
496 | regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); |
497 | |
498 | if (nv_device(drm->device)->card_type == NV_40) { |
499 | regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); |
500 | regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); |
501 | regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); |
502 | |
503 | for (i = 0; i < 38; i++) |
504 | regp->ctv_regs[i] = NVReadRAMDAC(dev, head, |
505 | NV_PRAMDAC_CTV + 4*i); |
506 | } |
507 | } |
508 | |
509 | static void |
510 | nv_load_state_ramdac(struct drm_device *dev, int head, |
511 | struct nv04_mode_state *state) |
512 | { |
513 | struct nouveau_drm *drm = nouveau_drm(dev); |
514 | struct nouveau_clock *clk = nouveau_clock(drm->device); |
515 | struct nv04_crtc_reg *regp = &state->crtc_reg[head]; |
516 | uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; |
517 | int i; |
518 | |
519 | if (nv_device(drm->device)->card_type >= NV_10) |
520 | NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); |
521 | |
522 | clk->pll_prog(clk, pllreg, ®p->pllvals); |
523 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); |
524 | if (nv_two_heads(dev)) |
525 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk); |
526 | if (nv_device(drm->device)->chipset == 0x11) |
527 | NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); |
528 | |
529 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); |
530 | |
531 | if (nv_gf4_disp_arch(dev)) |
532 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); |
533 | if (nv_device(drm->device)->chipset >= 0x30) |
534 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); |
535 | |
536 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); |
537 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); |
538 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); |
539 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); |
540 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); |
541 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); |
542 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); |
543 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); |
544 | |
545 | for (i = 0; i < 7; i++) { |
546 | uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); |
547 | |
548 | NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); |
549 | NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); |
550 | } |
551 | |
552 | if (nv_gf4_disp_arch(dev)) { |
553 | NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); |
554 | for (i = 0; i < 3; i++) { |
555 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); |
556 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); |
557 | } |
558 | } |
559 | |
560 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); |
561 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); |
562 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); |
563 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); |
564 | |
565 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); |
566 | |
567 | if (nv_gf4_disp_arch(dev)) |
568 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); |
569 | |
570 | if (nv_device(drm->device)->card_type == NV_40) { |
571 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); |
572 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); |
573 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); |
574 | |
575 | for (i = 0; i < 38; i++) |
576 | NVWriteRAMDAC(dev, head, |
577 | NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]); |
578 | } |
579 | } |
580 | |
581 | static void |
582 | nv_save_state_vga(struct drm_device *dev, int head, |
583 | struct nv04_mode_state *state) |
584 | { |
585 | struct nv04_crtc_reg *regp = &state->crtc_reg[head]; |
586 | int i; |
587 | |
588 | regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); |
589 | |
590 | for (i = 0; i < 25; i++) |
591 | rd_cio_state(dev, head, regp, i); |
592 | |
593 | NVSetEnablePalette(dev, head, true); |
594 | for (i = 0; i < 21; i++) |
595 | regp->Attribute[i] = NVReadVgaAttr(dev, head, i); |
596 | NVSetEnablePalette(dev, head, false); |
597 | |
598 | for (i = 0; i < 9; i++) |
599 | regp->Graphics[i] = NVReadVgaGr(dev, head, i); |
600 | |
601 | for (i = 0; i < 5; i++) |
602 | regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); |
603 | } |
604 | |
605 | static void |
606 | nv_load_state_vga(struct drm_device *dev, int head, |
607 | struct nv04_mode_state *state) |
608 | { |
609 | struct nv04_crtc_reg *regp = &state->crtc_reg[head]; |
610 | int i; |
611 | |
612 | NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); |
613 | |
614 | for (i = 0; i < 5; i++) |
615 | NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); |
616 | |
617 | nv_lock_vga_crtc_base(dev, head, false); |
618 | for (i = 0; i < 25; i++) |
619 | wr_cio_state(dev, head, regp, i); |
620 | nv_lock_vga_crtc_base(dev, head, true); |
621 | |
622 | for (i = 0; i < 9; i++) |
623 | NVWriteVgaGr(dev, head, i, regp->Graphics[i]); |
624 | |
625 | NVSetEnablePalette(dev, head, true); |
626 | for (i = 0; i < 21; i++) |
627 | NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); |
628 | NVSetEnablePalette(dev, head, false); |
629 | } |
630 | |
631 | static void |
632 | nv_save_state_ext(struct drm_device *dev, int head, |
633 | struct nv04_mode_state *state) |
634 | { |
635 | struct nouveau_drm *drm = nouveau_drm(dev); |
636 | struct nv04_crtc_reg *regp = &state->crtc_reg[head]; |
637 | int i; |
638 | |
639 | rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); |
640 | rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); |
641 | rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); |
642 | rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); |
643 | rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); |
644 | rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); |
645 | rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); |
646 | |
647 | rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); |
648 | rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); |
649 | rd_cio_state(dev, head, regp, NV_CIO_CRE_21); |
650 | |
651 | if (nv_device(drm->device)->card_type >= NV_20) |
652 | rd_cio_state(dev, head, regp, NV_CIO_CRE_47); |
653 | |
654 | if (nv_device(drm->device)->card_type >= NV_30) |
655 | rd_cio_state(dev, head, regp, 0x9f); |
656 | |
657 | rd_cio_state(dev, head, regp, NV_CIO_CRE_49); |
658 | rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); |
659 | rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); |
660 | rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); |
661 | rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); |
662 | |
663 | if (nv_device(drm->device)->card_type >= NV_10) { |
664 | regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); |
665 | regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); |
666 | |
667 | if (nv_device(drm->device)->card_type >= NV_30) |
668 | regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); |
669 | |
670 | if (nv_device(drm->device)->card_type == NV_40) |
671 | regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); |
672 | |
673 | if (nv_two_heads(dev)) |
674 | regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); |
675 | regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); |
676 | } |
677 | |
678 | regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); |
679 | |
680 | rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); |
681 | rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); |
682 | if (nv_device(drm->device)->card_type >= NV_10) { |
683 | rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); |
684 | rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); |
685 | rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); |
686 | rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); |
687 | } |
688 | /* NV11 and NV20 don't have this, they stop at 0x52. */ |
689 | if (nv_gf4_disp_arch(dev)) { |
690 | rd_cio_state(dev, head, regp, NV_CIO_CRE_42); |
691 | rd_cio_state(dev, head, regp, NV_CIO_CRE_53); |
692 | rd_cio_state(dev, head, regp, NV_CIO_CRE_54); |
693 | |
694 | for (i = 0; i < 0x10; i++) |
695 | regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); |
696 | rd_cio_state(dev, head, regp, NV_CIO_CRE_59); |
697 | rd_cio_state(dev, head, regp, NV_CIO_CRE_5B); |
698 | |
699 | rd_cio_state(dev, head, regp, NV_CIO_CRE_85); |
700 | rd_cio_state(dev, head, regp, NV_CIO_CRE_86); |
701 | } |
702 | |
703 | regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); |
704 | } |
705 | |
706 | static void |
707 | nv_load_state_ext(struct drm_device *dev, int head, |
708 | struct nv04_mode_state *state) |
709 | { |
710 | struct nouveau_drm *drm = nouveau_drm(dev); |
711 | struct nouveau_device *device = nv_device(drm->device); |
712 | struct nouveau_timer *ptimer = nouveau_timer(device); |
713 | struct nouveau_fb *pfb = nouveau_fb(device); |
714 | struct nv04_crtc_reg *regp = &state->crtc_reg[head]; |
715 | uint32_t reg900; |
716 | int i; |
717 | |
718 | if (nv_device(drm->device)->card_type >= NV_10) { |
719 | if (nv_two_heads(dev)) |
720 | /* setting ENGINE_CTRL (EC) *must* come before |
721 | * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in |
722 | * EC that should not be overwritten by writing stale EC |
723 | */ |
724 | NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); |
725 | |
726 | nv_wr32(device, NV_PVIDEO_STOP, 1); |
727 | nv_wr32(device, NV_PVIDEO_INTR_EN, 0); |
728 | nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0); |
729 | nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0); |
730 | nv_wr32(device, NV_PVIDEO_LIMIT(0), pfb->ram->size - 1); |
731 | nv_wr32(device, NV_PVIDEO_LIMIT(1), pfb->ram->size - 1); |
732 | nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), pfb->ram->size - 1); |
733 | nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), pfb->ram->size - 1); |
734 | nv_wr32(device, NV_PBUS_POWERCTRL_2, 0); |
735 | |
736 | NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); |
737 | NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); |
738 | NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); |
739 | |
740 | if (nv_device(drm->device)->card_type >= NV_30) |
741 | NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); |
742 | |
743 | if (nv_device(drm->device)->card_type == NV_40) { |
744 | NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); |
745 | |
746 | reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900); |
747 | if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC) |
748 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000); |
749 | else |
750 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000); |
751 | } |
752 | } |
753 | |
754 | NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); |
755 | |
756 | wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); |
757 | wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); |
758 | wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); |
759 | wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); |
760 | wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); |
761 | wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); |
762 | wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); |
763 | wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); |
764 | wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); |
765 | |
766 | if (nv_device(drm->device)->card_type >= NV_20) |
767 | wr_cio_state(dev, head, regp, NV_CIO_CRE_47); |
768 | |
769 | if (nv_device(drm->device)->card_type >= NV_30) |
770 | wr_cio_state(dev, head, regp, 0x9f); |
771 | |
772 | wr_cio_state(dev, head, regp, NV_CIO_CRE_49); |
773 | wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); |
774 | wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); |
775 | wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); |
776 | if (nv_device(drm->device)->card_type == NV_40) |
777 | nv_fix_nv40_hw_cursor(dev, head); |
778 | wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); |
779 | |
780 | wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); |
781 | wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); |
782 | if (nv_device(drm->device)->card_type >= NV_10) { |
783 | wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); |
784 | wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); |
785 | wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); |
786 | wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); |
787 | } |
788 | /* NV11 and NV20 stop at 0x52. */ |
789 | if (nv_gf4_disp_arch(dev)) { |
790 | if (nv_device(drm->device)->card_type < NV_20) { |
791 | /* Not waiting for vertical retrace before modifying |
792 | CRE_53/CRE_54 causes lockups. */ |
793 | nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8); |
794 | nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0); |
795 | } |
796 | |
797 | wr_cio_state(dev, head, regp, NV_CIO_CRE_42); |
798 | wr_cio_state(dev, head, regp, NV_CIO_CRE_53); |
799 | wr_cio_state(dev, head, regp, NV_CIO_CRE_54); |
800 | |
801 | for (i = 0; i < 0x10; i++) |
802 | NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); |
803 | wr_cio_state(dev, head, regp, NV_CIO_CRE_59); |
804 | wr_cio_state(dev, head, regp, NV_CIO_CRE_5B); |
805 | |
806 | wr_cio_state(dev, head, regp, NV_CIO_CRE_85); |
807 | wr_cio_state(dev, head, regp, NV_CIO_CRE_86); |
808 | } |
809 | |
810 | NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); |
811 | } |
812 | |
813 | static void |
814 | nv_save_state_palette(struct drm_device *dev, int head, |
815 | struct nv04_mode_state *state) |
816 | { |
817 | struct nouveau_device *device = nouveau_dev(dev); |
818 | int head_offset = head * NV_PRMDIO_SIZE, i; |
819 | |
820 | nv_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, |
821 | NV_PRMDIO_PIXEL_MASK_MASK); |
822 | nv_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0); |
823 | |
824 | for (i = 0; i < 768; i++) { |
825 | state->crtc_reg[head].DAC[i] = nv_rd08(device, |
826 | NV_PRMDIO_PALETTE_DATA + head_offset); |
827 | } |
828 | |
829 | NVSetEnablePalette(dev, head, false); |
830 | } |
831 | |
832 | void |
833 | nouveau_hw_load_state_palette(struct drm_device *dev, int head, |
834 | struct nv04_mode_state *state) |
835 | { |
836 | struct nouveau_device *device = nouveau_dev(dev); |
837 | int head_offset = head * NV_PRMDIO_SIZE, i; |
838 | |
839 | nv_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, |
840 | NV_PRMDIO_PIXEL_MASK_MASK); |
841 | nv_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0); |
842 | |
843 | for (i = 0; i < 768; i++) { |
844 | nv_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset, |
845 | state->crtc_reg[head].DAC[i]); |
846 | } |
847 | |
848 | NVSetEnablePalette(dev, head, false); |
849 | } |
850 | |
851 | void nouveau_hw_save_state(struct drm_device *dev, int head, |
852 | struct nv04_mode_state *state) |
853 | { |
854 | struct nouveau_drm *drm = nouveau_drm(dev); |
855 | |
856 | if (nv_device(drm->device)->chipset == 0x11) |
857 | /* NB: no attempt is made to restore the bad pll later on */ |
858 | nouveau_hw_fix_bad_vpll(dev, head); |
859 | nv_save_state_ramdac(dev, head, state); |
860 | nv_save_state_vga(dev, head, state); |
861 | nv_save_state_palette(dev, head, state); |
862 | nv_save_state_ext(dev, head, state); |
863 | } |
864 | |
865 | void nouveau_hw_load_state(struct drm_device *dev, int head, |
866 | struct nv04_mode_state *state) |
867 | { |
868 | NVVgaProtect(dev, head, true); |
869 | nv_load_state_ramdac(dev, head, state); |
870 | nv_load_state_ext(dev, head, state); |
871 | nouveau_hw_load_state_palette(dev, head, state); |
872 | nv_load_state_vga(dev, head, state); |
873 | NVVgaProtect(dev, head, false); |
874 | } |
875 | |