1 | /* $NetBSD: hmereg.h,v 1.22 2009/05/07 06:46:54 jdc Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 1999 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Paul Kranenburg. |
9 | * |
10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions |
12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. |
15 | * 2. Redistributions in binary form must reproduce the above copyright |
16 | * notice, this list of conditions and the following disclaimer in the |
17 | * documentation and/or other materials provided with the distribution. |
18 | * |
19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
29 | * POSSIBILITY OF SUCH DAMAGE. |
30 | */ |
31 | |
32 | /* |
33 | * HME Shared Ethernet Block register offsets |
34 | */ |
35 | #define HME_SEBI_RESET (0*4) |
36 | #define HME_SEBI_CFG (1*4) |
37 | #define HME_SEBI_STAT (64*4) |
38 | #define HME_SEBI_IMASK (65*4) |
39 | |
40 | /* HME SEB bits. */ |
41 | #define HME_SEB_RESET_ETX 0x00000001 /* reset external transmitter */ |
42 | #define HME_SEB_RESET_ERX 0x00000002 /* reset external receiver */ |
43 | |
44 | #define HME_SEB_CFG_BURSTMASK 0x00000003 /* covers all burst bits */ |
45 | #define HME_SEB_CFG_BURST16 0x00000000 /* 16 byte bursts */ |
46 | #define HME_SEB_CFG_BURST32 0x00000001 /* 32 byte bursts */ |
47 | #define HME_SEB_CFG_BURST64 0x00000002 /* 64 byte bursts */ |
48 | #define HME_SEB_CFG_64BIT 0x00000004 /* 64-bit CEI/SBus DVMA (94) */ |
49 | #define HME_SEB_CFG_PARITY 0x00000008 /* DVMA & PIO parity check */ |
50 | #define HME_SEB_CFG_VERS 0xf0000000 /* ether channel version */ |
51 | #define 28 |
52 | |
53 | #define HME_SEB_STAT_GOTFRAME 0x00000001 /* frame received */ |
54 | #define HME_SEB_STAT_RCNTEXP 0x00000002 /* rx frame count expired */ |
55 | #define HME_SEB_STAT_ACNTEXP 0x00000004 /* align error count expired */ |
56 | #define HME_SEB_STAT_CCNTEXP 0x00000008 /* crc error count expired */ |
57 | #define HME_SEB_STAT_LCNTEXP 0x00000010 /* length error count expired */ |
58 | #define HME_SEB_STAT_RFIFOVF 0x00000020 /* rx fifo overflow */ |
59 | #define HME_SEB_STAT_CVCNTEXP 0x00000040 /* code violation counter exp */ |
60 | #define HME_SEB_STAT_STSTERR 0x00000080 /* xif sqe test failed */ |
61 | #define HME_SEB_STAT_SENTFRAME 0x00000100 /* frame sent */ |
62 | #define HME_SEB_STAT_TFIFO_UND 0x00000200 /* tx fifo underrun */ |
63 | #define HME_SEB_STAT_MAXPKTERR 0x00000400 /* max-packet size error */ |
64 | #define HME_SEB_STAT_NCNTEXP 0x00000800 /* normal collision count exp */ |
65 | #define HME_SEB_STAT_ECNTEXP 0x00001000 /* excess collision count exp */ |
66 | #define HME_SEB_STAT_LCCNTEXP 0x00002000 /* late collision count exp */ |
67 | #define HME_SEB_STAT_FCNTEXP 0x00004000 /* first collision count exp */ |
68 | #define HME_SEB_STAT_DTIMEXP 0x00008000 /* defer timer expired */ |
69 | #define HME_SEB_STAT_RXTOHOST 0x00010000 /* pkt moved from rx fifo->memory */ |
70 | #define HME_SEB_STAT_NORXD 0x00020000 /* out of receive descriptors */ |
71 | #define HME_SEB_STAT_RXERR 0x00040000 /* rx DMA error */ |
72 | #define HME_SEB_STAT_RXLATERR 0x00080000 /* late error during rx DMA */ |
73 | #define HME_SEB_STAT_RXPERR 0x00100000 /* parity error during rx DMA */ |
74 | #define HME_SEB_STAT_RXTERR 0x00200000 /* tag error during rx DMA */ |
75 | #define HME_SEB_STAT_EOPERR 0x00400000 /* tx descriptor did not set EOP */ |
76 | #define HME_SEB_STAT_MIFIRQ 0x00800000 /* mif needs attention */ |
77 | #define HME_SEB_STAT_HOSTTOTX 0x01000000 /* pkt moved from memory->tx fifo */ |
78 | #define HME_SEB_STAT_TXALL 0x02000000 /* all pkts in fifo transmitted */ |
79 | #define HME_SEB_STAT_TXEACK 0x04000000 /* error during tx DMA */ |
80 | #define HME_SEB_STAT_TXLERR 0x08000000 /* late error during tx DMA */ |
81 | #define HME_SEB_STAT_TXPERR 0x10000000 /* parity error during tx DMA */ |
82 | #define HME_SEB_STAT_TXTERR 0x20000000 /* tag error durig tx DMA */ |
83 | #define HME_SEB_STAT_SLVERR 0x40000000 /* pio access error */ |
84 | #define HME_SEB_STAT_SLVPERR 0x80000000 /* pio access parity error */ |
85 | #define HME_SEB_STAT_BITS "\177\020" \ |
86 | "b\0GOTFRAME\0b\1RCNTEXP\0b\2ACNTEXP\0" \ |
87 | "b\3CCNTEXP\0b\4LCNTEXP\0b\5RFIFOVF\0" \ |
88 | "b\6CVCNTEXP\0b\7STSTERR\0b\10SENTFRAME\0" \ |
89 | "b\11TFIFO_UND\0b\12MAXPKTERR\0b\13NCNTEXP\0" \ |
90 | "b\14ECNTEXP\0b\15LCCNTEXP\0b\16FCNTEXP\0" \ |
91 | "b\17DTIMEXP\0b\20RXTOHOST\0b\21NORXD\0" \ |
92 | "b\22RXERR\0b\23RXLATERR\0b\24RXPERR\0" \ |
93 | "b\25RXTERR\0b\26EOPERR\0b\27MIFIRQ\0" \ |
94 | "b\30HOSTTOTX\0b\31TXALL\0b\32XTEACK\0" \ |
95 | "b\33TXLERR\0b\34TXPERR\0b\35TXTERR\0" \ |
96 | "b\36SLVERR\0b\37SLVPERR\0\0" |
97 | |
98 | #ifdef HMEDEBUG |
99 | #define HME_SEB_STAT_DEBUG_ERRORS (HME_SEB_STAT_DTIMEXP | HME_SEB_STAT_RFIFOVF) |
100 | #else |
101 | #define HME_SEB_STAT_DEBUG_ERRORS 0 |
102 | #endif |
103 | |
104 | #define HME_SEB_STAT_ALL_ERRORS \ |
105 | (HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\ |
106 | HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\ |
107 | HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\ |
108 | HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\ |
109 | HME_SEB_STAT_FCNTEXP | HME_SEB_STAT_LCCNTEXP |\ |
110 | HME_SEB_STAT_ECNTEXP | HME_SEB_STAT_NCNTEXP | HME_SEB_STAT_MAXPKTERR|\ |
111 | HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR | HME_SEB_STAT_CVCNTEXP |\ |
112 | HME_SEB_STAT_LCNTEXP | HME_SEB_STAT_CCNTEXP |\ |
113 | HME_SEB_STAT_ACNTEXP | HME_SEB_STAT_DEBUG_ERRORS) |
114 | |
115 | #define HME_SEB_STAT_VLAN_ERRORS \ |
116 | (HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\ |
117 | HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\ |
118 | HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\ |
119 | HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\ |
120 | HME_SEB_STAT_DTIMEXP | HME_SEB_STAT_FCNTEXP | HME_SEB_STAT_LCCNTEXP |\ |
121 | HME_SEB_STAT_ECNTEXP | HME_SEB_STAT_NCNTEXP | \ |
122 | HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR | HME_SEB_STAT_CVCNTEXP |\ |
123 | HME_SEB_STAT_RFIFOVF | HME_SEB_STAT_LCNTEXP | HME_SEB_STAT_CCNTEXP |\ |
124 | HME_SEB_STAT_ACNTEXP) |
125 | |
126 | /* |
127 | * HME Transmitter register offsets |
128 | */ |
129 | #define HME_ETXI_PENDING (0*4) /* Pending/wakeup */ |
130 | #define HME_ETXI_CFG (1*4) |
131 | #define HME_ETXI_RING (2*4) /* Descriptor Ring pointer */ |
132 | #define HME_ETXI_BBASE (3*4) /* Buffer base address (ro) */ |
133 | #define HME_ETXI_BDISP (4*4) /* Buffer displacement (ro) */ |
134 | #define HME_ETXI_FIFO_WPTR (5*4) /* FIFO write pointer */ |
135 | #define HME_ETXI_FIFO_SWPTR (6*4) /* FIFO shadow write pointer */ |
136 | #define HME_ETXI_FIFO_RPTR (7*4) /* FIFO read pointer */ |
137 | #define HME_ETXI_FIFO_SRPTR (8*4) /* FIFO shadow read pointer */ |
138 | #define HME_ETXI_FIFO_PKTCNT (9*4) /* FIFO packet counter */ |
139 | #define HME_ETXI_STATEMACHINE (10*4) /* State machine */ |
140 | #define HME_ETXI_RSIZE (11*4) /* Ring size */ |
141 | #define HME_ETXI_BPTR (12*4) /* Buffer pointer */ |
142 | |
143 | |
144 | /* TXI_PENDING bits */ |
145 | #define HME_ETX_TP_DMAWAKEUP 0x00000001 /* Start tx (rw, auto-clear) */ |
146 | |
147 | /* TXI_CFG bits */ |
148 | #define HME_ETX_CFG_DMAENABLE 0x00000001 /* Enable TX DMA */ |
149 | #define HME_ETX_CFG_FIFOTHRESH 0x000003fe /* TX fifo threshold */ |
150 | #define HME_ETX_CFG_IRQDAFTER 0x00000400 /* Intr after tx-fifo empty */ |
151 | #define HME_ETX_CFG_IRQDBEFORE 0x00000000 /* Intr before tx-fifo empty */ |
152 | |
153 | |
154 | /* |
155 | * HME Receiver register offsets |
156 | */ |
157 | #define HME_ERXI_CFG (0*4) |
158 | #define HME_ERXI_RING (1*4) /* Descriptor Ring pointer */ |
159 | #define HME_ERXI_BPTR (2*4) /* Data Buffer pointer (ro) */ |
160 | #define HME_ERXI_FIFO_WPTR (3*4) /* FIFO write pointer */ |
161 | #define HME_ERXI_FIFO_SWPTR (4*4) /* FIFO shadow write pointer */ |
162 | #define HME_ERXI_FIFO_RPTR (5*4) /* FIFO read pointer */ |
163 | #define HME_ERXI_FIFO_SRPTR (6*4) /* FIFO shadow read pointer */ |
164 | #define HME_ERXI_STATEMACHINE (7*4) /* State machine */ |
165 | |
166 | /* ERXI_CFG bits */ |
167 | #define HME_ERX_CFG_DMAENABLE 0x00000001 /* Enable RX DMA */ |
168 | #define HME_ERX_CFG_BYTEOFFSET 0x00000038 /* RX first byte offset */ |
169 | #define HME_ERX_CFG_RINGSIZE32 0x00000000 /* Descriptor ring size: 32 */ |
170 | #define HME_ERX_CFG_RINGSIZE64 0x00000200 /* Descriptor ring size: 64 */ |
171 | #define HME_ERX_CFG_RINGSIZE128 0x00000400 /* Descriptor ring size: 128 */ |
172 | #define HME_ERX_CFG_RINGSIZE256 0x00000600 /* Descriptor ring size: 256 */ |
173 | #define HME_ERX_CFG_CSUMSTART 0x007f0000 /* cksum offset (half words) */ |
174 | #define HME_ERX_CFG_CSUMSHIFT 16 |
175 | |
176 | /* |
177 | * HME MAC-core register offsets |
178 | */ |
179 | #define HME_MACI_XIF (0*4) |
180 | #define HME_MACI_TXSWRST (130*4) /* TX reset */ |
181 | #define HME_MACI_TXCFG (131*4) /* TX config */ |
182 | #define HME_MACI_JSIZE (139*4) /* TX jam size */ |
183 | #define HME_MACI_TXSIZE (140*4) /* TX max size */ |
184 | #define HME_MACI_NCCNT (144*4) /* TX normal collision cnt */ |
185 | #define HME_MACI_FCCNT (145*4) /* TX first collision cnt */ |
186 | #define HME_MACI_EXCNT (146*4) /* TX excess collision cnt */ |
187 | #define HME_MACI_LTCNT (147*4) /* TX late collision cnt */ |
188 | #define HME_MACI_RANDSEED (148*4) /* */ |
189 | #define HME_MACI_RXSWRST (194*4) /* RX reset */ |
190 | #define HME_MACI_RXCFG (195*4) /* RX config */ |
191 | #define HME_MACI_RXSIZE (196*4) /* RX max size */ |
192 | #define HME_MACI_MACADDR2 (198*4) /* MAC address */ |
193 | #define HME_MACI_MACADDR1 (199*4) |
194 | #define HME_MACI_MACADDR0 (200*4) |
195 | #define HME_MACI_STAT_RCNT (201*4) /* RX frame count */ |
196 | #define HME_MACI_STAT_LCNT (202*4) /* Length error count */ |
197 | #define HME_MACI_STAT_ACNT (203*4) /* Align error count */ |
198 | #define HME_MACI_STAT_CCNT (204*4) /* FCS error count */ |
199 | #define HME_MACI_STATE (205*4) /* RX_MAC state machine */ |
200 | #define HME_MACI_STAT_CVCNT (206*4) /* Code violation count */ |
201 | #define HME_MACI_HASHTAB3 (208*4) /* Address hash table */ |
202 | #define HME_MACI_HASHTAB2 (209*4) |
203 | #define HME_MACI_HASHTAB1 (210*4) |
204 | #define HME_MACI_HASHTAB0 (211*4) |
205 | #define HME_MACI_AFILTER2 (212*4) /* Address filter */ |
206 | #define HME_MACI_AFILTER1 (213*4) |
207 | #define HME_MACI_AFILTER0 (214*4) |
208 | #define HME_MACI_AFILTER_MASK (215*4) |
209 | |
210 | /* XIF config register. */ |
211 | #define HME_MAC_XIF_OE 0x00000001 /* Output driver enable */ |
212 | #define HME_MAC_XIF_XLBACK 0x00000002 /* Loopback-mode XIF enable */ |
213 | #define HME_MAC_XIF_MLBACK 0x00000004 /* Loopback-mode MII enable */ |
214 | #define HME_MAC_XIF_MIIENABLE 0x00000008 /* MII receive buffer enable */ |
215 | #define HME_MAC_XIF_SQENABLE 0x00000010 /* SQE test enable */ |
216 | #define HME_MAC_XIF_SQETWIN 0x000003e0 /* SQE time window */ |
217 | #define HME_MAC_XIF_LANCE 0x00000010 /* Lance mode enable */ |
218 | #define HME_MAC_XIF_LIPG0 0x000003e0 /* Lance mode IPG0 */ |
219 | #define HME_MAC_XIF_BITS "\177\020" \ |
220 | "b\0OE\0b\1XLBACK\0b\2MLBACK\0" \ |
221 | "b\4MIIENA\0b\4SQEENA\0\0" |
222 | |
223 | /* Transmit config register. */ |
224 | #define HME_MAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */ |
225 | #define HME_MAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */ |
226 | #define HME_MAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */ |
227 | #define HME_MAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */ |
228 | #define HME_MAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */ |
229 | #define HME_MAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */ |
230 | #define HME_MAC_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */ |
231 | #define HME_MAC_TXCFG_BITS "\177\020" \ |
232 | "b\0ENA\0b\6SMODE\0b\7IGNCOLL\0" \ |
233 | "b\x8_FCSOFF\0b\x9_DBACKOFF\0" \ |
234 | "b\xa_FULLDPLX\0b\xc_DGIVEUP\0\0" |
235 | |
236 | /* Receive config register. */ |
237 | #define HME_MAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */ |
238 | #define HME_MAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */ |
239 | #define HME_MAC_RXCFG_PMISC 0x00000040 /* Enable promiscuous mode */ |
240 | #define HME_MAC_RXCFG_DERR 0x00000080 /* Disable error checking */ |
241 | #define HME_MAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */ |
242 | #define HME_MAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */ |
243 | #define HME_MAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */ |
244 | #define HME_MAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */ |
245 | #define HME_MAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */ |
246 | #define HME_MAC_RXCFG_BITS "\177\020" \ |
247 | "b\0ENA\0b\6PSTRIP\0b\7PMISC\0" \ |
248 | "b\x8ERRDIS\0b\x9CRCDIS\0b\xaME\0" \ |
249 | "b\xbPGRP\0b\xcHASHENA\0\xd_ADDRENA\0\0" |
250 | |
251 | /* |
252 | * HME MIF register offsets |
253 | */ |
254 | #define HME_MIFI_BB_CLK (0*4) /* bit-bang clock */ |
255 | #define HME_MIFI_BB_DATA (1*4) /* bit-bang data */ |
256 | #define HME_MIFI_BB_OE (2*4) /* bit-bang output enable */ |
257 | #define HME_MIFI_FO (3*4) /* frame output */ |
258 | #define HME_MIFI_CFG (4*4) /* */ |
259 | #define HME_MIFI_IMASK (5*4) /* Interrupt mask for status change */ |
260 | #define HME_MIFI_STAT (6*4) /* Status (ro, auto-clear) */ |
261 | #define HME_MIFI_SM (7*4) /* State machine (ro) */ |
262 | |
263 | /* MIF Configuration register */ |
264 | #define HME_MIF_CFG_PHY 0x00000001 /* PHY select */ |
265 | #define HME_MIF_CFG_PE 0x00000002 /* Poll enable */ |
266 | #define HME_MIF_CFG_BBMODE 0x00000004 /* Bit-bang mode */ |
267 | #define HME_MIF_CFG_PRADDR 0x000000f8 /* Poll register address */ |
268 | #define HME_MIF_CFG_MDI0 0x00000100 /* MDI_0 (ro) */ |
269 | #define HME_MIF_CFG_MDI1 0x00000200 /* MDI_1 (ro) */ |
270 | #define HME_MIF_CFG_PPADDR 0x00007c00 /* Poll phy address */ |
271 | #define HME_MIF_CFG_BITS "\177\020" \ |
272 | "b\0PHYEXT\0b\1POLLENA\0b\3BBMODE\0" \ |
273 | "b\x8MDI0\0b\x9MDI1\0\0" |
274 | |
275 | /* MIF Frame/Output register */ |
276 | #define HME_MIF_FO_ST 0xc0000000 /* Start of frame */ |
277 | #define HME_MIF_FO_ST_SHIFT 30 /* */ |
278 | #define HME_MIF_FO_OPC 0x30000000 /* Opcode */ |
279 | #define HME_MIF_FO_OPC_SHIFT 28 /* */ |
280 | #define HME_MIF_FO_PHYAD 0x0f800000 /* PHY Address */ |
281 | #define HME_MIF_FO_PHYAD_SHIFT 23 /* */ |
282 | #define HME_MIF_FO_REGAD 0x007c0000 /* Register Address */ |
283 | #define HME_MIF_FO_REGAD_SHIFT 18 /* */ |
284 | #define HME_MIF_FO_TAMSB 0x00020000 /* Turn-around MSB */ |
285 | #define HME_MIF_FO_TALSB 0x00010000 /* Turn-around LSB */ |
286 | #define HME_MIF_FO_DATA 0x0000ffff /* data to read or write */ |
287 | |
288 | /* Wired HME PHY addresses */ |
289 | #define HME_PHYAD_INTERNAL 1 |
290 | #define HME_PHYAD_EXTERNAL 0 |
291 | |
292 | /* |
293 | * Buffer Descriptors. |
294 | */ |
295 | #ifdef notdef |
296 | struct hme_xd { |
297 | volatile uint32_t xd_flags; |
298 | volatile uint32_t xd_addr; /* Buffer address (DMA) */ |
299 | }; |
300 | #endif |
301 | #define HME_XD_SIZE 8 |
302 | #define HME_XD_FLAGS(b, i) ((char *)(b) + ((i) * HME_XD_SIZE) + 0) |
303 | #define HME_XD_ADDR(b, i) ((char *)(b) + ((i) * HME_XD_SIZE) + 4) |
304 | #define HME_XD_GETFLAGS(p, b, i) \ |
305 | (p) ? le32toh(*((uint32_t *)HME_XD_FLAGS(b,i))) : \ |
306 | (*((uint32_t *)HME_XD_FLAGS(b,i))) |
307 | #define HME_XD_SETFLAGS(p, b, i, f) do { \ |
308 | *((uint32_t *)HME_XD_FLAGS(b,i)) = ((p) ? htole32((f)) : (f)); \ |
309 | } while(/* CONSTCOND */ 0) |
310 | #define HME_XD_SETADDR(p, b, i, a) do { \ |
311 | *((uint32_t *)HME_XD_ADDR(b,i)) = ((p) ? htole32((a)) : (a)); \ |
312 | } while(/* CONSTCOND */ 0) |
313 | |
314 | /* Descriptor control word flag values */ |
315 | #define HME_XD_OWN 0x80000000 /* ownership: 1=hw, 0=sw */ |
316 | #define HME_XD_SOP 0x40000000 /* start of packet marker (tx) */ |
317 | #define HME_XD_OFL 0x40000000 /* buffer overflow (rx) */ |
318 | #define HME_XD_EOP 0x20000000 /* end of packet marker (tx) */ |
319 | #define HME_XD_TXCKSUM 0x10000000 /* checksum enable (tx) */ |
320 | #define HME_XD_TXCSSTUFF 0xff00000 /* checksum stuff offset (tx) */ |
321 | #define HME_XD_TXCSSTUFFSHIFT 20 |
322 | #define HME_XD_TXCSSTART 0x000fc000 /* checksum start offset (tx) */ |
323 | #define HME_XD_TXCSSTARTSHIFT 14 |
324 | #define HME_XD_TXLENMSK 0x00003fff /* packet length mask (tx) */ |
325 | |
326 | #define HME_XD_RXLENMSK 0x3fff0000 /* packet length mask (rx) */ |
327 | #define HME_XD_RXLENSHIFT 16 |
328 | #define HME_XD_RXCKSUM 0x0000ffff /* packet checksum (rx), complement */ |
329 | |
330 | /* Macros to encode/decode the receive buffer size from the flags field */ |
331 | #define HME_XD_ENCODE_RSIZE(sz) \ |
332 | (((sz) << HME_XD_RXLENSHIFT) & HME_XD_RXLENMSK) |
333 | #define HME_XD_DECODE_RSIZE(flags) \ |
334 | (((flags) & HME_XD_RXLENMSK) >> HME_XD_RXLENSHIFT) |
335 | |
336 | /* Provide encode/decode macros for the transmit buffers for symmetry */ |
337 | #define HME_XD_ENCODE_TSIZE(sz) \ |
338 | (((sz) << 0) & HME_XD_TXLENMSK) |
339 | #define HME_XD_DECODE_TSIZE(flags) \ |
340 | (((flags) & HME_XD_TXLENMSK) >> 0) |
341 | |
342 | |