1/* $NetBSD: nouveau_dispnv04_arb.c,v 1.2 2014/08/06 15:01:34 riastradh Exp $ */
2
3/*
4 * Copyright 1993-2003 NVIDIA, Corporation
5 * Copyright 2007-2009 Stuart Bennett
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
21 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
22 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 */
25
26#include <sys/cdefs.h>
27__KERNEL_RCSID(0, "$NetBSD: nouveau_dispnv04_arb.c,v 1.2 2014/08/06 15:01:34 riastradh Exp $");
28
29#include <drm/drmP.h>
30
31#include "nouveau_drm.h"
32#include "nouveau_reg.h"
33#include "hw.h"
34
35/****************************************************************************\
36* *
37* The video arbitration routines calculate some "magic" numbers. Fixes *
38* the snow seen when accessing the framebuffer without it. *
39* It just works (I hope). *
40* *
41\****************************************************************************/
42
43struct nv_fifo_info {
44 int lwm;
45 int burst;
46};
47
48struct nv_sim_state {
49 int pclk_khz;
50 int mclk_khz;
51 int nvclk_khz;
52 int bpp;
53 int mem_page_miss;
54 int mem_latency;
55 int memory_type;
56 int memory_width;
57 int two_heads;
58};
59
60static void
61nv04_calc_arb(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
62{
63 int pagemiss, cas, bpp;
64 int nvclks, mclks, crtpagemiss;
65 int found, mclk_extra, mclk_loop, cbs, m1, p1;
66 int mclk_freq, pclk_freq, nvclk_freq;
67 int us_m, us_n, us_p, crtc_drain_rate;
68 int cpm_us, us_crt, clwm;
69
70 pclk_freq = arb->pclk_khz;
71 mclk_freq = arb->mclk_khz;
72 nvclk_freq = arb->nvclk_khz;
73 pagemiss = arb->mem_page_miss;
74 cas = arb->mem_latency;
75 bpp = arb->bpp;
76 cbs = 128;
77
78 nvclks = 10;
79 mclks = 13 + cas;
80 mclk_extra = 3;
81 found = 0;
82
83 while (!found) {
84 found = 1;
85
86 mclk_loop = mclks + mclk_extra;
87 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
88 us_n = nvclks * 1000 * 1000 / nvclk_freq;
89 us_p = nvclks * 1000 * 1000 / pclk_freq;
90
91 crtc_drain_rate = pclk_freq * bpp / 8;
92 crtpagemiss = 2;
93 crtpagemiss += 1;
94 cpm_us = crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
95 us_crt = cpm_us + us_m + us_n + us_p;
96 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
97 clwm++;
98
99 m1 = clwm + cbs - 512;
100 p1 = m1 * pclk_freq / mclk_freq;
101 p1 = p1 * bpp / 8;
102 if ((p1 < m1 && m1 > 0) || clwm > 519) {
103 found = !mclk_extra;
104 mclk_extra--;
105 }
106 if (clwm < 384)
107 clwm = 384;
108
109 fifo->lwm = clwm;
110 fifo->burst = cbs;
111 }
112}
113
114static void
115nv10_calc_arb(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
116{
117 int fill_rate, drain_rate;
118 int pclks, nvclks, mclks, xclks;
119 int pclk_freq, nvclk_freq, mclk_freq;
120 int fill_lat, extra_lat;
121 int max_burst_o, max_burst_l;
122 int fifo_len, min_lwm, max_lwm;
123 const int burst_lat = 80; /* Maximum allowable latency due
124 * to the CRTC FIFO burst. (ns) */
125
126 pclk_freq = arb->pclk_khz;
127 nvclk_freq = arb->nvclk_khz;
128 mclk_freq = arb->mclk_khz;
129
130 fill_rate = mclk_freq * arb->memory_width / 8; /* kB/s */
131 drain_rate = pclk_freq * arb->bpp / 8; /* kB/s */
132
133 fifo_len = arb->two_heads ? 1536 : 1024; /* B */
134
135 /* Fixed FIFO refill latency. */
136
137 pclks = 4; /* lwm detect. */
138
139 nvclks = 3 /* lwm -> sync. */
140 + 2 /* fbi bus cycles (1 req + 1 busy) */
141 + 1 /* 2 edge sync. may be very close to edge so
142 * just put one. */
143 + 1 /* fbi_d_rdv_n */
144 + 1 /* Fbi_d_rdata */
145 + 1; /* crtfifo load */
146
147 mclks = 1 /* 2 edge sync. may be very close to edge so
148 * just put one. */
149 + 1 /* arb_hp_req */
150 + 5 /* tiling pipeline */
151 + 2 /* latency fifo */
152 + 2 /* memory request to fbio block */
153 + 7; /* data returned from fbio block */
154
155 /* Need to accumulate 256 bits for read */
156 mclks += (arb->memory_type == 0 ? 2 : 1)
157 * arb->memory_width / 32;
158
159 fill_lat = mclks * 1000 * 1000 / mclk_freq /* minimum mclk latency */
160 + nvclks * 1000 * 1000 / nvclk_freq /* nvclk latency */
161 + pclks * 1000 * 1000 / pclk_freq; /* pclk latency */
162
163 /* Conditional FIFO refill latency. */
164
165 xclks = 2 * arb->mem_page_miss + mclks /* Extra latency due to
166 * the overlay. */
167 + 2 * arb->mem_page_miss /* Extra pagemiss latency. */
168 + (arb->bpp == 32 ? 8 : 4); /* Margin of error. */
169
170 extra_lat = xclks * 1000 * 1000 / mclk_freq;
171
172 if (arb->two_heads)
173 /* Account for another CRTC. */
174 extra_lat += fill_lat + extra_lat + burst_lat;
175
176 /* FIFO burst */
177
178 /* Max burst not leading to overflows. */
179 max_burst_o = (1 + fifo_len - extra_lat * drain_rate / (1000 * 1000))
180 * (fill_rate / 1000) / ((fill_rate - drain_rate) / 1000);
181 fifo->burst = min(max_burst_o, 1024);
182
183 /* Max burst value with an acceptable latency. */
184 max_burst_l = burst_lat * fill_rate / (1000 * 1000);
185 fifo->burst = min(max_burst_l, fifo->burst);
186
187 fifo->burst = rounddown_pow_of_two(fifo->burst);
188
189 /* FIFO low watermark */
190
191 min_lwm = (fill_lat + extra_lat) * drain_rate / (1000 * 1000) + 1;
192 max_lwm = fifo_len - fifo->burst
193 + fill_lat * drain_rate / (1000 * 1000)
194 + fifo->burst * drain_rate / fill_rate;
195
196 fifo->lwm = min_lwm + 10 * (max_lwm - min_lwm) / 100; /* Empirical. */
197}
198
199static void
200nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
201 int *burst, int *lwm)
202{
203 struct nouveau_drm *drm = nouveau_drm(dev);
204 struct nouveau_device *device = nouveau_dev(dev);
205 struct nv_fifo_info fifo_data;
206 struct nv_sim_state sim_data;
207 int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
208 int NVClk = nouveau_hw_get_clock(dev, PLL_CORE);
209 uint32_t cfg1 = nv_rd32(device, NV04_PFB_CFG1);
210
211 sim_data.pclk_khz = VClk;
212 sim_data.mclk_khz = MClk;
213 sim_data.nvclk_khz = NVClk;
214 sim_data.bpp = bpp;
215 sim_data.two_heads = nv_two_heads(dev);
216 if ((dev->pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ ||
217 (dev->pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) {
218 uint32_t type;
219
220 pci_read_config_dword(pci_get_bus_and_slot(0, 1), 0x7c, &type);
221
222 sim_data.memory_type = (type >> 12) & 1;
223 sim_data.memory_width = 64;
224 sim_data.mem_latency = 3;
225 sim_data.mem_page_miss = 10;
226 } else {
227 sim_data.memory_type = nv_rd32(device, NV04_PFB_CFG0) & 0x1;
228 sim_data.memory_width = (nv_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
229 sim_data.mem_latency = cfg1 & 0xf;
230 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);
231 }
232
233 if (nv_device(drm->device)->card_type == NV_04)
234 nv04_calc_arb(&fifo_data, &sim_data);
235 else
236 nv10_calc_arb(&fifo_data, &sim_data);
237
238 *burst = ilog2(fifo_data.burst >> 4);
239 *lwm = fifo_data.lwm >> 3;
240}
241
242static void
243nv20_update_arb(int *burst, int *lwm)
244{
245 unsigned int fifo_size, burst_size, graphics_lwm;
246
247 fifo_size = 2048;
248 burst_size = 512;
249 graphics_lwm = fifo_size - burst_size;
250
251 *burst = ilog2(burst_size >> 5);
252 *lwm = graphics_lwm >> 3;
253}
254
255void
256nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm)
257{
258 struct nouveau_drm *drm = nouveau_drm(dev);
259
260 if (nv_device(drm->device)->card_type < NV_20)
261 nv04_update_arb(dev, vclk, bpp, burst, lwm);
262 else if ((dev->pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
263 (dev->pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
264 *burst = 128;
265 *lwm = 0x0480;
266 } else
267 nv20_update_arb(burst, lwm);
268}
269