1/* $NetBSD: czreg.h,v 1.3 2015/07/11 10:32:46 kamil Exp $ */
2
3/*-
4 * Copyright (c) 2000 Zembu Labs, Inc.
5 * All rights reserved.
6 *
7 * Author: Jason R. Thorpe <thorpej@zembu.com>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Zembu Labs, Inc.
20 * 4. Neither the name of Zembu Labs nor the names of its employees may
21 * be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS
25 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR-
26 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS-
27 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36/*
37 * Register and firmware communication definitions for the Cyclades
38 * Z series of multi-port serial adapters.
39 */
40
41/*
42 * The Cyclades-Z series is an intelligent multi-port serial controller
43 * comprised of:
44 *
45 * - PLX PCI9060ES PCI bus interface
46 * - Xilinx XC5204 FPGA
47 * - IDT R3052 MIPS CPU
48 *
49 * Communication is performed by modifying structures in board local
50 * RAM or in host RAM. We define offsets into these structures so
51 * that either access method may be used.
52 *
53 * The Cyclades-Z comes in three basic flavors:
54 *
55 * - Cyclades-8Zo rev 1 -- This is an older 8-port board with no
56 * FPGA.
57 *
58 * - Cyclades-8Zo rev 2 -- This is the newer 8-port board, which
59 * uses an octopus cable.
60 *
61 * - Cyclades-Ze -- This is the top-of-the-line of the Cyclades
62 * multiport serial controllers. It uses a SCSI-2 cable to
63 * connect the card to a rack-mountable serial expansion box
64 * (1U high). Each box has 16 RJ45 serial ports, and up to
65 * 4 boxes can be chained together, for a total of 64 ports.
66 * Up to 2 boxes can be used without an extra power supply.
67 * Boxes 3 and 4 require their own external power supply,
68 * otherwise the firmware will refuse to start (as it cannot
69 * communicate with the UARTs in the boxes).
70 *
71 * The 8Zo flavors have not been tested, tho the programming interface
72 * is identical (except for the firmware load phase of the 8Zo rev 1;
73 * no FPGA load is done in that case), so they should work.
74 */
75
76/*
77 * PLX Local Address Base values for the board RAM and FPGA registers.
78 *
79 * These values are specific to the Cyclades-Z.
80 */
81#define LOCAL_ADDR0_RAM (0x00000000 | LASBA_ENABLE)
82#define LOCAL_ADDR0_FPGA (0x14000000 | LASBA_ENABLE)
83
84/*
85 * PLX Mailbox0 values.
86 *
87 * These values are specific to the Cyclades-Z.
88 */
89#define MAILBOX0_8Zo_V1 0 /* Cyclades-8Zo ver. 1 */
90#define MAILBOX0_8Zo_V2 1 /* Cyclades-8Zo ver. 2 */
91#define MAILBOX0_Ze_V1 2 /* Cyclades-Ze ver. 1 */
92
93/*
94 * Bits in the PLX INIT_CTRL register.
95 *
96 * These values are specific to the Cyclades-Z.
97 */
98#define CONTROL_FPGA_LOADED CONTROL_GPI
99
100/*
101 * FPGA registers on the 8Zo boards.
102 */
103#define FPGA_ID 0x00 /* FPGA ID */
104#define FPGA_VERSION 0x04 /* FPGA version */
105#define FPGA_CPU_START 0x08 /* CPU start */
106#define FPGA_CPU_STOP 0x0c /* CPU stop */
107#define FPGA_MISC 0x10 /* Misc. register */
108#define FPGA_IDT_MODE 0x14 /* IDT MIPS R3000 mode */
109#define FPGA_UART_IRQ_STAT 0x18 /* UART interrupt status */
110#define FPGA_CLEAR_TIMER0_IRQ 0x1c /* clear timer 0 interrupt */
111#define FPGA_CLEAR_TIMER1_IRQ 0x20 /* clear timer 1 interrupt */
112#define FPGA_CLEAR_TIMER2_IRQ 0x24 /* clear timer 3 interrupt */
113#define FPGA_TEST 0x28 /* test register */
114#define FPGA_TEST_COUNT 0x2c /* test count register */
115#define FPGA_TIMER_SELECT 0x30 /* timer select */
116#define FPGA_PR_UART_IRQ_STAT 0x34 /* prioritized UART interrupt status */
117#define FPGA_RAM_WAIT_STATE 0x38 /* RAM wait state */
118#define FPGA_UART_WAIT_STATE 0x3c /* UART wait state */
119#define FPGA_TIMER_WAIT_STATE 0x40 /* timer wait state */
120#define FPGA_ACK_WAIT_STATE 0x44 /* ACK wait state */
121
122/*
123 * FPGA registers on the Ze boards. Note that the important registers
124 * (FPGA_ID, FPGA_VERSION, FPGA_CPU_START, FPGA_CPU_STOP) are all in the
125 * same place as on the 8Zo boards, and have the same meanings.
126 */
127#define FPGA_ZE_ID 0x00 /* FPGA ID */
128#define FPGA_ZE_VERSION 0x04 /* FPGA version */
129#define FPGA_ZE_CPU_START 0x08 /* CPU start */
130#define FPGA_ZE_CPU_STOP 0x0c /* CPU stop */
131#define FPGA_ZE_CTRL 0x10 /* CPU control */
132#define FPGA_ZE_ZBUS_WAIT 0x14 /* Z-Bus wait state */
133#define FPGA_ZE_TIMER_DIV 0x18 /* timer divisor */
134#define FPGA_ZE_TIMER_IRQ_ACK 0x1c /* timer interrupt ACK */
135
136/*
137 * Values for FPGA ID.
138 */
139#define FPGA_ID_8Zo_V1 0x95 /* Cyclades-8Zo ver. 1 */
140#define FPGA_ID_8Zo_V2 0x84 /* Cyclades-8Zo ver. 2 */
141#define FPGA_ID_Ze_V1 0x89 /* Cyclades-Ze ver. 1 */
142
143/*
144 * Values for Cyclades-Ze timer divisor.
145 */
146#define ZE_TIMER_DIV_1M 0x00
147#define ZE_TIMER_DIV_256K 0x01
148#define ZE_TIMER_DIV_128K 0x02
149#define ZE_TIMER_DIV_32K 0x03
150
151/*
152 * Firmware interface starts here.
153 *
154 * These values are valid for the following Cyclades-Z firmware:
155 *
156 * @(#) Copyright (c) Cyclades Corporation, 1996, 1999
157 * @(#) ZFIRM Cyclades-Z/PCI Firmware V_3.3.1 09/24/99
158 */
159
160/*
161 * Structure of the firmware header.
162 */
163#define ZFIRM_MAX_BLOCKS 16 /* max. # of firmware/FPGA blocks */
164struct zfirm_header {
165 u_int8_t zfh_name[64];
166 u_int8_t zfh_date[32];
167 u_int8_t zfh_aux[32];
168 u_int32_t zfh_nconfig;
169 u_int32_t zfh_configoff;
170 u_int32_t zfh_nblocks;
171 u_int32_t zfh_blockoff;
172 u_int32_t zfh_reserved[9];
173} __packed;
174
175struct zfirm_config {
176 u_int8_t zfc_name[64];
177 u_int32_t zfc_mailbox;
178 u_int32_t zfc_function;
179 u_int32_t zfc_nblocks;
180 u_int32_t zfc_blocklist[ZFIRM_MAX_BLOCKS];
181} __packed;
182
183#define ZFC_FUNCTION_NORMAL 0 /* normal operation */
184#define ZFC_FUNCTION_TEST 1 /* test mode operation */
185
186struct zfirm_block {
187 u_int32_t zfb_type;
188 u_int32_t zfb_fileoff;
189 u_int32_t zfb_ramoff;
190 u_int32_t zfb_size;
191} __packed;
192
193#define ZFB_TYPE_FIRMWARE 0 /* MIPS firmware */
194#define ZFB_TYPE_FPGA 1 /* FPGA code */
195
196#define ZFIRM_MAX_CHANNELS 64 /* max. # channels per board */
197
198/*
199 * Firmware ID structure, which the firmware sets up after it boots.
200 */
201#define ZFIRM_SIG_OFF 0x00000180 /* offset of signature in board RAM */
202#define ZFIRM_CTRLADDR_OFF 0x00000184 /* offset of offset of control
203 structure */
204#define ZFIRM_SIG 0x5557465A /* ZFIRM signature */
205#define ZFIRM_HLT 0x59505B5C /* Halt due to power problem */
206#define ZFIRM_RST 0x56040674 /* Firmware reset */
207
208/*
209 * The firmware control structures are made up of the following:
210 *
211 * BOARD CONTROL (64 bytes)
212 * CHANNEL CONTROL (96 bytes * ZFIRM_MAX_CHANNELS)
213 * BUFFER CONTROL (64 bytes * ZFIRM_MAX_CHANNELS)
214 */
215
216#define ZFIRM_BRDCTL_SIZE 64
217#define ZFIRM_CHNCTL_SIZE 96
218#define ZFIRM_BUFCTL_SIZE 64
219
220#define ZFIRM_CHNCTL_OFF(chan, reg) \
221 (ZFIRM_BRDCTL_SIZE + ((chan) * ZFIRM_CHNCTL_SIZE) + (reg))
222#define ZFIRM_BUFCTL_OFF(chan, reg) \
223 (ZFIRM_CHNCTL_OFF(ZFIRM_MAX_CHANNELS, 0) + \
224 ((chan) * ZFIRM_BUFCTL_SIZE) + (reg))
225
226/*
227 * Offsets in the BOARD CONTROL structure.
228 */
229 /* static info provided by MIPS */
230#define BRDCTL_NCHANNEL 0x00 /* number of channels */
231#define BRDCTL_FWVERSION 0x04 /* firmware version */
232 /* static info provided by driver */
233#define BRDCTL_C_OS 0x08 /* operating system ID */
234#define BRDCTL_DRVERSION 0x0c /* driver version */
235 /* board control area */
236#define BRDCTL_INACTIVITY 0x10 /* inactivity control */
237 /* host to firmware commands */
238#define BRDCTL_HCMD_CHANNEL 0x14 /* channel number */
239#define BRDCTL_HCMD_PARAM 0x18 /* parameter */
240 /* firmware to host commands */
241#define BRDCTL_FWCMD_CHANNEL 0x1c /* channel number */
242#define BRDCTL_FWCMD_PARAM 0x20 /* parameter */
243#define BRDCTL_INT_QUEUE_OFF 0x24 /* offset to INT_QUEUE structure */
244
245/*
246 * Offsets in the CHANNEL CONTROL structure.
247 */
248#define CHNCTL_OP_MODE 0x00 /* operation mode */
249#define CHNCTL_INTR_ENABLE 0x04 /* interrupt making for UART */
250#define CHNCTL_SW_FLOW 0x08 /* SW flow control */
251#define CHNCTL_FLOW_STATUS 0x0c /* output flow status */
252#define CHNCTL_COMM_BAUD 0x10 /* baud rate -- numerically specified */
253#define CHNCTL_COMM_PARITY 0x14 /* parity */
254#define CHNCTL_COMM_DATA_L 0x18 /* data length/stop */
255#define CHNCTL_COMM_FLAGS 0x1c /* other flags */
256#define CHNCTL_HW_FLOW 0x20 /* HW flow control */
257#define CHNCTL_RS_CONTROL 0x24 /* RS-232 outputs */
258#define CHNCTL_RS_STATUS 0x28 /* RS-232 inputs */
259#define CHNCTL_FLOW_XON 0x2c /* XON character */
260#define CHNCTL_FLOW_XOFF 0x30 /* XOFF character */
261#define CHNCTL_HW_OVERFLOW 0x34 /* HW overflow counter */
262#define CHNCTL_SW_OVERFLOW 0x38 /* SW overflow counter */
263#define CHNCTL_COMM_ERROR 0x3c /* frame/parity error counter */
264#define CHNCTL_ICHAR 0x40 /* special interrupt character */
265
266/*
267 * Offsets in the BUFFER CONTROL structure.
268 */
269#define BUFCTL_FLAG_DMA 0x00 /* buffers are in Host memory */
270#define BUFCTL_TX_BUFADDR 0x04 /* address of Tx buffer */
271#define BUFCTL_TX_BUFSIZE 0x08 /* size of Tx buffer */
272#define BUFCTL_TX_THRESHOLD 0x0c /* Tx low water mark */
273#define BUFCTL_TX_GET 0x10 /* tail index Tx buf */
274#define BUFCTL_TX_PUT 0x14 /* head index Tx buf */
275#define BUFCTL_RX_BUFADDR 0x18 /* address of Rx buffer */
276#define BUFCTL_RX_BUFSIZE 0x1c /* size of Rx buffer */
277#define BUFCTL_RX_THRESHOLD 0x20 /* Rx high water mark */
278#define BUFCTL_RX_GET 0x24 /* tail index Rx buf */
279#define BUFCTL_RX_PUT 0x28 /* head index Rx buf */
280
281/* Values for operating system ID (BOARD CONTROL) */
282#define C_OS_SVR3 0x00000010 /* generic SVR3 */
283#define C_OS_XENIX 0x00000011 /* SCO XENIX */
284#define C_OS_SCO 0x00000012 /* SCO SVR3 */
285#define C_OS_SVR4 0x00000020 /* generic SVR4 */
286#define C_OS_UXWARE 0x00000021 /* UnixWare */
287#define C_OS_LINUX 0x00000030 /* Linux */
288#define C_OS_SOLARIS 0x00000040 /* Solaris */
289#define C_OS_BSD 0x00000050 /* generic BSD */
290#define C_OS_DOS 0x00000070 /* generic DOS */
291#define C_OS_NT 0x00000080 /* Windows NT */
292#define C_OS_OS2 0x00000090 /* IBM OS/2 */
293#define C_OS_MACOS 0x000000a0 /* MacOS */
294#define C_OS_AIX 0x000000b0 /* IBM AIX */
295
296/* Values for op_mode (CHANNEL CONTROL) */
297#define C_CH_DISABLE 0x00000000 /* channel is disabled */
298#define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */
299#define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */
300#define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */
301#define C_CH_LOOPBACK 0x00000004 /* Loopback mode */
302
303/* Values for comm_parity (CHANNEL CONTROL) */
304#define C_PR_NONE 0x00000000 /* None */
305#define C_PR_ODD 0x00000001 /* Odd */
306#define C_PR_EVEN 0x00000002 /* Even */
307#define C_PR_MARK 0x00000004 /* Mark */
308#define C_PR_SPACE 0x00000008 /* Space */
309#define C_PR_PARITY 0x000000ff
310#define C_PR_DISCARD 0x00000100 /* discard char with
311 frame/parity error */
312#define C_PR_IGNORE 0x00000200 /* ignore frame/par error */
313
314/* Values for comm_data_l (CHANNEL CONTROL) */
315#define C_DL_CS5 0x00000001
316#define C_DL_CS6 0x00000002
317#define C_DL_CS7 0x00000004
318#define C_DL_CS8 0x00000008
319#define C_DL_CS 0x0000000f
320#define C_DL_1STOP 0x00000010
321#define C_DL_15STOP 0x00000020
322#define C_DL_2STOP 0x00000040
323#define C_DL_STOP 0x000000f0
324
325/* Values for intr_enable (CHANNEL CONTROL) */
326#define C_IN_DISABLE 0x00000000 /* zero, disable interrupts */
327#define C_IN_TXBEMPTY 0x00000001 /* tx buffer empty */
328#define C_IN_TXLOWWM 0x00000002 /* tx buffer below LWM */
329#define C_IN_TXFEMPTY 0x00000004 /* tx buffer + FIFO +
330 shift reg. empty */
331#define C_IN_RXHIWM 0x00000010 /* rx buffer above HWM */
332#define C_IN_RXNNDT 0x00000020 /* rx no new data timeout */
333#define C_IN_MDCD 0x00000100 /* modem DCD change */
334#define C_IN_MDSR 0x00000200 /* modem DSR change */
335#define C_IN_MRI 0x00000400 /* modem RI change */
336#define C_IN_MCTS 0x00000800 /* modem CTS change */
337#define C_IN_RXBRK 0x00001000 /* Break received */
338#define C_IN_PR_ERROR 0x00002000 /* parity error */
339#define C_IN_FR_ERROR 0x00004000 /* frame error */
340#define C_IN_OVR_ERROR 0x00008000 /* overrun error */
341#define C_IN_RXOFL 0x00010000 /* RX buffer overflow */
342#define C_IN_IOCTLW 0x00020000 /* I/O control w/ wait */
343#define C_IN_MRTS 0x00040000 /* modem RTS drop */
344#define C_IN_ICHAR 0x00080000 /* special intr. char
345 received */
346
347/* Values for flow control (CHANNEL CONTROL) */
348#define C_FL_OXX 0x00000001 /* output Xon/Xoff flow
349 control */
350#define C_FL_IXX 0x00000002 /* input Xon/Xoff flow
351 control */
352#define C_FL_OIXANY 0x00000004 /* output Xon/Xoff (any xon) */
353#define C_FL_SWFLOW 0x0000000f
354
355/* Values for flow status (CHANNEL CONTROL) */
356#define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer
357 or UART */
358#define C_FS_SENDING 0x00000001 /* UART is sending data */
359#define C_FS_SWFLOW 0x00000002 /* Tx is stopped by received
360 Xoff */
361
362/* Values for RS-232 signals (CHANNEL CONTROL) */
363#define C_RS_PARAM 0x80000000 /* indicates presence of
364 parameter in IOCTL command */
365#define C_RS_RTS 0x00000001 /* RTS */
366#define C_RS_DTR 0x00000004 /* DTR */
367#define C_RS_DCD 0x00000100 /* CD */
368#define C_RS_DSR 0x00000200 /* DSR */
369#define C_RS_RI 0x00000400 /* RI */
370#define C_RS_CTS 0x00000800 /* CTS */
371
372/* Commands Host <--> Board */
373#define C_CM_RESET 0x01 /* resets/flushes buffers */
374#define C_CM_IOCTL 0x02 /* re-reads CH_CTRL */
375#define C_CM_IOCTLW 0x03 /* re-reads CH_CTRL, intr when done */
376#define C_CM_IOCTLM 0x04 /* RS-232 outputs change */
377#define C_CM_SENDXOFF 0x10 /* sends Xoff */
378#define C_CM_SENDXON 0x11 /* sends Xon */
379#define C_CM_CLFLOW 0x12 /* Clears flow control (resume) */
380#define C_CM_SENDBRK 0x41 /* sends break */
381#define C_CM_INTBACK 0x42 /* Interrupt back */
382#define C_CM_SET_BREAK 0x43 /* Tx break on */
383#define C_CM_CLR_BREAK 0x44 /* Tx break off */
384#define C_CM_CMD_DONE 0x45 /* Previous command done */
385#define C_CM_INTBACK2 0x46 /* Alternate Interrupt back */
386#define C_CM_TINACT 0x51 /* sets inactivity detection */
387#define C_CM_IRQ_ENBL 0x52 /* enables generation of interrupts */
388#define C_CM_IRQ_DSBL 0x53 /* disables generation of interrupts */
389#define C_CM_ACK_ENBL 0x54 /* enables acknolowdged interrupt
390 mode */
391#define C_CM_ACK_DSBL 0x55 /* disables acknolowdged intr mode */
392#define C_CM_FLUSH_RX 0x56 /* flushes Rx buffer */
393#define C_CM_FLUSH_TX 0x57 /* flushes Tx buffer */
394#define C_CM_Q_ENABLE 0x58 /* enables queue access from the
395 driver */
396#define C_CM_Q_DISABLE 0x59 /* disables queue access from the
397 driver */
398#define C_CM_TXBEMPTY 0x60 /* Tx buffer is empty */
399#define C_CM_TXLOWWM 0x61 /* Tx buffer low water mark */
400#define C_CM_RXHIWM 0x62 /* Rx buffer high water mark */
401#define C_CM_RXNNDT 0x63 /* rx no new data timeout */
402#define C_CM_TXFEMPTY 0x64 /* Tx buffer, FIFO and shift reg.
403 are empty */
404#define C_CM_ICHAR 0x65 /* Special Interrupt Character
405 received */
406#define C_CM_MDCD 0x70 /* modem DCD change */
407#define C_CM_MDSR 0x71 /* modem DSR change */
408#define C_CM_MRI 0x72 /* modem RI change */
409#define C_CM_MCTS 0x73 /* modem CTS change */
410#define C_CM_MRTS 0x74 /* modem RTS drop */
411#define C_CM_RXBRK 0x84 /* Break received */
412#define C_CM_PR_ERROR 0x85 /* Parity error */
413#define C_CM_FR_ERROR 0x86 /* Frame error */
414#define C_CM_OVR_ERROR 0x87 /* Overrun error */
415#define C_CM_RXOFL 0x88 /* RX buffer overflow */
416#define C_CM_CMDERROR 0x90 /* command error */
417#define C_CM_FATAL 0x91 /* fatal error */
418#define C_CM_HW_RESET 0x92 /* reset board */
419