1 | /* $NetBSD: pciidereg.h,v 1.11 2006/11/24 22:04:25 wiz Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved. |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
9 | * 1. Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * 2. Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
14 | * 3. All advertising materials mentioning features or use of this software |
15 | * must display the following acknowledgement: |
16 | * This product includes software developed by Christopher G. Demetriou |
17 | * for the NetBSD Project. |
18 | * 4. The name of the author may not be used to endorse or promote products |
19 | * derived from this software without specific prior written permission |
20 | * |
21 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
22 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
23 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
24 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
25 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
26 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
30 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
31 | */ |
32 | |
33 | /* |
34 | * PCI IDE controller register definitions. |
35 | * |
36 | * Author: Christopher G. Demetriou, March 2, 1998. |
37 | * |
38 | * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and |
39 | * "Programming Interface for Bus Master IDE Controller, Revision 1.0 |
40 | * 5/16/94" from the PCI SIG. |
41 | */ |
42 | |
43 | /* |
44 | * Number of channels per chip. MUST NOT CHANGE (macros in pciide.c and |
45 | * this file depend on its value). |
46 | */ |
47 | #define PCIIDE_NUM_CHANNELS 2 |
48 | |
49 | /* |
50 | * PCI base address register locations (some are per-channel). |
51 | */ |
52 | #define PCIIDE_REG_CMD_BASE(chan) (0x10 + (8 * (chan))) |
53 | #define PCIIDE_REG_CTL_BASE(chan) (0x14 + (8 * (chan))) |
54 | #define PCIIDE_REG_BUS_MASTER_DMA 0x20 |
55 | |
56 | /* |
57 | * Bits in the PCI Programming Interface register (some are per-channel). |
58 | * Bits 6-4 are defined as read-only in PCI 2.1 specification. |
59 | * Microsoft proposed to use these bits for independent channels |
60 | * enable/disable. This feature is enabled based on the value of bit 6. |
61 | */ |
62 | #define PCIIDE_CHANSTATUS_EN 0x40 |
63 | #define PCIIDE_CHAN_EN(chan) (0x20 >> (chan)) |
64 | #define PCIIDE_INTERFACE_PCI(chan) (0x01 << (2 * (chan))) |
65 | #define PCIIDE_INTERFACE_SETTABLE(chan) (0x02 << (2 * (chan))) |
66 | #define PCIIDE_INTERFACE_BUS_MASTER_DMA 0x80 |
67 | |
68 | /* |
69 | * Compatibility address/IRQ definitions (some are per-channel). |
70 | */ |
71 | #define PCIIDE_COMPAT_CMD_BASE(chan) ((chan) == 0 ? 0x1f0 : 0x170) |
72 | #define PCIIDE_COMPAT_CMD_SIZE 8 |
73 | #define PCIIDE_COMPAT_CTL_BASE(chan) ((chan) == 0 ? 0x3f6 : 0x376) |
74 | #define PCIIDE_COMPAT_CTL_SIZE 1 |
75 | #define PCIIDE_COMPAT_IRQ(chan) ((chan) == 0 ? 14 : 15) |
76 | |
77 | #define PCIIDE_CHANNEL_NAME(chan) ((chan) == 0 ? "primary" : "secondary") |
78 | |
79 | /* |
80 | * definitions for IDE DMA |
81 | * XXX maybe this should go elsewhere |
82 | */ |
83 | |
84 | /* secondary channel registers offset */ |
85 | #define IDEDMA_SCH_OFFSET 0x08 |
86 | #define IDEDMA_NREGS 8 |
87 | |
88 | /* Bus master command register */ |
89 | #define IDEDMA_CMD 0x00 |
90 | #define IDEDMA_CMD_WRITE 0x08 |
91 | #define IDEDMA_CMD_START 0x01 |
92 | |
93 | /* Bus master status register */ |
94 | #define IDEDMA_CTL 0x02 |
95 | #define IDEDMA_CTL_DRV_DMA(d) (0x20 << (d)) |
96 | #define IDEDMA_CTL_INTR 0x04 |
97 | #define IDEDMA_CTL_ERR 0x02 |
98 | #define IDEDMA_CTL_ACT 0x01 |
99 | |
100 | /* Bus master table pointer register */ |
101 | #define IDEDMA_TBL 0x04 |
102 | #define IDEDMA_TBL_MASK 0xfffffffc |
103 | #define IDEDMA_TBL_ALIGN 0x00010000 |
104 | |
105 | /* bus master table descriptor */ |
106 | struct idedma_table { |
107 | u_int32_t base_addr; /* physical base addr of memory region */ |
108 | u_int32_t byte_count; /* memory region length */ |
109 | #define IDEDMA_BYTE_COUNT_MASK 0x0000FFFF |
110 | #define IDEDMA_BYTE_COUNT_EOT 0x80000000 |
111 | }; |
112 | |
113 | #define IDEDMA_BYTE_COUNT_MAX 0x00010000 /* Max I/O per table */ |
114 | #define IDEDMA_BYTE_COUNT_ALIGN 0x00010000 |
115 | |