1 | /* $NetBSD: nouveau_engine_disp_nv94.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_disp_nv94.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $" ); |
29 | |
30 | #include <engine/software.h> |
31 | #include <engine/disp.h> |
32 | |
33 | #include <core/class.h> |
34 | |
35 | #include "nv50.h" |
36 | |
37 | /******************************************************************************* |
38 | * EVO master channel object |
39 | ******************************************************************************/ |
40 | |
41 | const struct nv50_disp_mthd_list |
42 | nv94_disp_mast_mthd_sor = { |
43 | .mthd = 0x0040, |
44 | .addr = 0x000008, |
45 | .data = { |
46 | { 0x0600, 0x610794 }, |
47 | {} |
48 | } |
49 | }; |
50 | |
51 | const struct nv50_disp_mthd_chan |
52 | nv94_disp_mast_mthd_chan = { |
53 | .name = "Core" , |
54 | .addr = 0x000000, |
55 | .data = { |
56 | { "Global" , 1, &nv50_disp_mast_mthd_base }, |
57 | { "DAC" , 3, &nv84_disp_mast_mthd_dac }, |
58 | { "SOR" , 4, &nv94_disp_mast_mthd_sor }, |
59 | { "PIOR" , 3, &nv50_disp_mast_mthd_pior }, |
60 | { "HEAD" , 2, &nv84_disp_mast_mthd_head }, |
61 | {} |
62 | } |
63 | }; |
64 | |
65 | /******************************************************************************* |
66 | * Base display object |
67 | ******************************************************************************/ |
68 | |
69 | static struct nouveau_oclass |
70 | nv94_disp_sclass[] = { |
71 | { NV94_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, |
72 | { NV94_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs }, |
73 | { NV94_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs }, |
74 | { NV94_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs }, |
75 | { NV94_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs }, |
76 | {} |
77 | }; |
78 | |
79 | static struct nouveau_omthds |
80 | nv94_disp_base_omthds[] = { |
81 | { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos }, |
82 | { SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd }, |
83 | { SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd }, |
84 | { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd }, |
85 | { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd }, |
86 | { DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd }, |
87 | { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, |
88 | { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, |
89 | { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd }, |
90 | {}, |
91 | }; |
92 | |
93 | static struct nouveau_oclass |
94 | nv94_disp_base_oclass[] = { |
95 | { NV94_DISP_CLASS, &nv50_disp_base_ofuncs, nv94_disp_base_omthds }, |
96 | {} |
97 | }; |
98 | |
99 | /******************************************************************************* |
100 | * Display engine implementation |
101 | ******************************************************************************/ |
102 | |
103 | static int |
104 | nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
105 | struct nouveau_oclass *oclass, void *data, u32 size, |
106 | struct nouveau_object **pobject) |
107 | { |
108 | struct nv50_disp_priv *priv; |
109 | int ret; |
110 | |
111 | ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP" , |
112 | "display" , &priv); |
113 | *pobject = nv_object(priv); |
114 | if (ret) |
115 | return ret; |
116 | |
117 | nv_engine(priv)->sclass = nv94_disp_base_oclass; |
118 | nv_engine(priv)->cclass = &nv50_disp_cclass; |
119 | nv_subdev(priv)->intr = nv50_disp_intr; |
120 | INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); |
121 | priv->sclass = nv94_disp_sclass; |
122 | priv->head.nr = 2; |
123 | priv->dac.nr = 3; |
124 | priv->sor.nr = 4; |
125 | priv->pior.nr = 3; |
126 | priv->dac.power = nv50_dac_power; |
127 | priv->dac.sense = nv50_dac_sense; |
128 | priv->sor.power = nv50_sor_power; |
129 | priv->sor.hdmi = nv84_hdmi_ctrl; |
130 | priv->sor.dp = &nv94_sor_dp_func; |
131 | priv->pior.power = nv50_pior_power; |
132 | priv->pior.dp = &nv50_pior_dp_func; |
133 | return 0; |
134 | } |
135 | |
136 | struct nouveau_oclass * |
137 | nv94_disp_oclass = &(struct nv50_disp_impl) { |
138 | .base.base.handle = NV_ENGINE(DISP, 0x88), |
139 | .base.base.ofuncs = &(struct nouveau_ofuncs) { |
140 | .ctor = nv94_disp_ctor, |
141 | .dtor = _nouveau_disp_dtor, |
142 | .init = _nouveau_disp_init, |
143 | .fini = _nouveau_disp_fini, |
144 | }, |
145 | .mthd.core = &nv94_disp_mast_mthd_chan, |
146 | .mthd.base = &nv84_disp_sync_mthd_chan, |
147 | .mthd.ovly = &nv84_disp_ovly_mthd_chan, |
148 | .mthd.prev = 0x000004, |
149 | }.base.base; |
150 | |