1 | /* $NetBSD: nouveau_engine_fifo_nv10.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_fifo_nv10.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $" ); |
29 | |
30 | #include <core/os.h> |
31 | #include <core/class.h> |
32 | #include <core/engctx.h> |
33 | #include <core/ramht.h> |
34 | |
35 | #include <subdev/instmem.h> |
36 | #include <subdev/instmem/nv04.h> |
37 | #include <subdev/fb.h> |
38 | |
39 | #include <engine/fifo.h> |
40 | |
41 | #include "nv04.h" |
42 | |
43 | static struct ramfc_desc |
44 | nv10_ramfc[] = { |
45 | { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, |
46 | { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, |
47 | { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, |
48 | { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, |
49 | { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, |
50 | { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE }, |
51 | { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, |
52 | { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE }, |
53 | { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 }, |
54 | {} |
55 | }; |
56 | |
57 | /******************************************************************************* |
58 | * FIFO channel objects |
59 | ******************************************************************************/ |
60 | |
61 | static int |
62 | nv10_fifo_chan_ctor(struct nouveau_object *parent, |
63 | struct nouveau_object *engine, |
64 | struct nouveau_oclass *oclass, void *data, u32 size, |
65 | struct nouveau_object **pobject) |
66 | { |
67 | struct nv04_fifo_priv *priv = (void *)engine; |
68 | struct nv04_fifo_chan *chan; |
69 | struct nv03_channel_dma_class *args = data; |
70 | int ret; |
71 | |
72 | if (size < sizeof(*args)) |
73 | return -EINVAL; |
74 | |
75 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, |
76 | 0x10000, args->pushbuf, |
77 | (1ULL << NVDEV_ENGINE_DMAOBJ) | |
78 | (1ULL << NVDEV_ENGINE_SW) | |
79 | (1ULL << NVDEV_ENGINE_GR), &chan); |
80 | *pobject = nv_object(chan); |
81 | if (ret) |
82 | return ret; |
83 | |
84 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; |
85 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; |
86 | nv_parent(chan)->context_attach = nv04_fifo_context_attach; |
87 | chan->ramfc = chan->base.chid * 32; |
88 | |
89 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); |
90 | nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset); |
91 | nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); |
92 | nv_wo32(priv->ramfc, chan->ramfc + 0x14, |
93 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | |
94 | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | |
95 | #ifdef __BIG_ENDIAN |
96 | NV_PFIFO_CACHE1_BIG_ENDIAN | |
97 | #endif |
98 | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); |
99 | return 0; |
100 | } |
101 | |
102 | static struct nouveau_ofuncs |
103 | nv10_fifo_ofuncs = { |
104 | .ctor = nv10_fifo_chan_ctor, |
105 | .dtor = nv04_fifo_chan_dtor, |
106 | .init = nv04_fifo_chan_init, |
107 | .fini = nv04_fifo_chan_fini, |
108 | .rd32 = _nouveau_fifo_channel_rd32, |
109 | .wr32 = _nouveau_fifo_channel_wr32, |
110 | }; |
111 | |
112 | static struct nouveau_oclass |
113 | nv10_fifo_sclass[] = { |
114 | { NV10_CHANNEL_DMA_CLASS, &nv10_fifo_ofuncs }, |
115 | {} |
116 | }; |
117 | |
118 | /******************************************************************************* |
119 | * FIFO context - basically just the instmem reserved for the channel |
120 | ******************************************************************************/ |
121 | |
122 | static struct nouveau_oclass |
123 | nv10_fifo_cclass = { |
124 | .handle = NV_ENGCTX(FIFO, 0x10), |
125 | .ofuncs = &(struct nouveau_ofuncs) { |
126 | .ctor = nv04_fifo_context_ctor, |
127 | .dtor = _nouveau_fifo_context_dtor, |
128 | .init = _nouveau_fifo_context_init, |
129 | .fini = _nouveau_fifo_context_fini, |
130 | .rd32 = _nouveau_fifo_context_rd32, |
131 | .wr32 = _nouveau_fifo_context_wr32, |
132 | }, |
133 | }; |
134 | |
135 | /******************************************************************************* |
136 | * PFIFO engine |
137 | ******************************************************************************/ |
138 | |
139 | static int |
140 | nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
141 | struct nouveau_oclass *oclass, void *data, u32 size, |
142 | struct nouveau_object **pobject) |
143 | { |
144 | struct nv04_instmem_priv *imem = nv04_instmem(parent); |
145 | struct nv04_fifo_priv *priv; |
146 | int ret; |
147 | |
148 | ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv); |
149 | *pobject = nv_object(priv); |
150 | if (ret) |
151 | return ret; |
152 | |
153 | nouveau_ramht_ref(imem->ramht, &priv->ramht); |
154 | nouveau_gpuobj_ref(imem->ramro, &priv->ramro); |
155 | nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); |
156 | |
157 | nv_subdev(priv)->unit = 0x00000100; |
158 | nv_subdev(priv)->intr = nv04_fifo_intr; |
159 | nv_engine(priv)->cclass = &nv10_fifo_cclass; |
160 | nv_engine(priv)->sclass = nv10_fifo_sclass; |
161 | priv->base.pause = nv04_fifo_pause; |
162 | priv->base.start = nv04_fifo_start; |
163 | priv->ramfc_desc = nv10_ramfc; |
164 | return 0; |
165 | } |
166 | |
167 | struct nouveau_oclass * |
168 | nv10_fifo_oclass = &(struct nouveau_oclass) { |
169 | .handle = NV_ENGINE(FIFO, 0x10), |
170 | .ofuncs = &(struct nouveau_ofuncs) { |
171 | .ctor = nv10_fifo_ctor, |
172 | .dtor = nv04_fifo_dtor, |
173 | .init = nv04_fifo_init, |
174 | .fini = _nouveau_fifo_fini, |
175 | }, |
176 | }; |
177 | |