1 | /****************************************************************************** |
2 | |
3 | Copyright (c) 2001-2013, Intel Corporation |
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32 | ******************************************************************************/ |
33 | /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.h 251964 2013-06-18 21:28:19Z jfv $*/ |
34 | /*$NetBSD: ixgbe_phy.h,v 1.5 2015/08/05 04:08:44 msaitoh Exp $*/ |
35 | |
36 | #ifndef _IXGBE_PHY_H_ |
37 | #define _IXGBE_PHY_H_ |
38 | |
39 | #include "ixgbe_type.h" |
40 | #define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0 |
41 | #define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2 |
42 | #define IXGBE_I2C_EEPROM_BANK_LEN 0xFF |
43 | |
44 | /* EEPROM byte offsets */ |
45 | #define IXGBE_SFF_IDENTIFIER 0x0 |
46 | #define IXGBE_SFF_IDENTIFIER_SFP 0x3 |
47 | #define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25 |
48 | #define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26 |
49 | #define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27 |
50 | #define IXGBE_SFF_1GBE_COMP_CODES 0x6 |
51 | #define IXGBE_SFF_10GBE_COMP_CODES 0x3 |
52 | #define IXGBE_SFF_CABLE_TECHNOLOGY 0x8 |
53 | #define IXGBE_SFF_CABLE_SPEC_COMP 0x3C |
54 | #define IXGBE_SFF_SFF_8472_SWAP 0x5C |
55 | #define IXGBE_SFF_SFF_8472_COMP 0x5E |
56 | #define IXGBE_SFF_SFF_8472_OSCB 0x6E |
57 | #define IXGBE_SFF_SFF_8472_ESCB 0x76 |
58 | |
59 | /* Bitmasks */ |
60 | #define IXGBE_SFF_DA_PASSIVE_CABLE 0x4 |
61 | #define IXGBE_SFF_DA_ACTIVE_CABLE 0x8 |
62 | #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 |
63 | #define IXGBE_SFF_1GBASESX_CAPABLE 0x1 |
64 | #define IXGBE_SFF_1GBASELX_CAPABLE 0x2 |
65 | #define IXGBE_SFF_1GBASET_CAPABLE 0x8 |
66 | #define IXGBE_SFF_10GBASESR_CAPABLE 0x10 |
67 | #define IXGBE_SFF_10GBASELR_CAPABLE 0x20 |
68 | #define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8 |
69 | #define IXGBE_SFF_SOFT_RS_SELECT_10G 0x8 |
70 | #define IXGBE_SFF_SOFT_RS_SELECT_1G 0x0 |
71 | #define IXGBE_I2C_EEPROM_READ_MASK 0x100 |
72 | #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 |
73 | #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 |
74 | #define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 |
75 | #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 |
76 | #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 |
77 | |
78 | /* Flow control defines */ |
79 | #define IXGBE_TAF_SYM_PAUSE 0x400 |
80 | #define IXGBE_TAF_ASM_PAUSE 0x800 |
81 | |
82 | /* Bit-shift macros */ |
83 | #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24 |
84 | #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16 |
85 | #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8 |
86 | |
87 | /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ |
88 | #define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 |
89 | #define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500 |
90 | #define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00 |
91 | #define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100 |
92 | |
93 | /* I2C SDA and SCL timing parameters for standard mode */ |
94 | #define IXGBE_I2C_T_HD_STA 4 |
95 | #define IXGBE_I2C_T_LOW 5 |
96 | #define IXGBE_I2C_T_HIGH 4 |
97 | #define IXGBE_I2C_T_SU_STA 5 |
98 | #define IXGBE_I2C_T_HD_DATA 5 |
99 | #define IXGBE_I2C_T_SU_DATA 1 |
100 | #define IXGBE_I2C_T_RISE 1 |
101 | #define IXGBE_I2C_T_FALL 1 |
102 | #define IXGBE_I2C_T_SU_STO 4 |
103 | #define IXGBE_I2C_T_BUF 5 |
104 | |
105 | #define IXGBE_TN_LASI_STATUS_REG 0x9005 |
106 | #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008 |
107 | |
108 | /* SFP+ SFF-8472 Compliance */ |
109 | #define IXGBE_SFF_SFF_8472_UNSUP 0x00 |
110 | #define IXGBE_SFF_SFF_8472_REV_9_3 0x01 |
111 | #define IXGBE_SFF_SFF_8472_REV_9_5 0x02 |
112 | #define IXGBE_SFF_SFF_8472_REV_10_2 0x03 |
113 | #define IXGBE_SFF_SFF_8472_REV_10_4 0x04 |
114 | #define IXGBE_SFF_SFF_8472_REV_11_0 0x05 |
115 | |
116 | s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); |
117 | bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); |
118 | enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); |
119 | s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); |
120 | s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); |
121 | s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); |
122 | s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, |
123 | u16 *phy_data); |
124 | s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, |
125 | u16 phy_data); |
126 | s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, |
127 | u32 device_type, u16 *phy_data); |
128 | s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, |
129 | u32 device_type, u16 phy_data); |
130 | s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw); |
131 | s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, |
132 | ixgbe_link_speed speed, |
133 | bool autoneg_wait_to_complete); |
134 | s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, |
135 | ixgbe_link_speed *speed, |
136 | bool *autoneg); |
137 | |
138 | /* PHY specific */ |
139 | s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, |
140 | ixgbe_link_speed *speed, |
141 | bool *link_up); |
142 | s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw); |
143 | s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, |
144 | u16 *firmware_version); |
145 | s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, |
146 | u16 *firmware_version); |
147 | |
148 | s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); |
149 | s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw); |
150 | s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); |
151 | s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, |
152 | u16 *list_offset, |
153 | u16 *data_offset); |
154 | s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw); |
155 | s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, |
156 | u8 dev_addr, u8 *data); |
157 | s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, |
158 | u8 dev_addr, u8 data); |
159 | s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, |
160 | u8 *eeprom_data); |
161 | s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, |
162 | u8 eeprom_data); |
163 | void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); |
164 | #endif /* _IXGBE_PHY_H_ */ |
165 | |