1/*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: src/sys/dev/ath/ath_hal/ar5212/ar5212reg.h,v 1.4 2010/01/29 10:10:14 rpaulo Exp $
18 */
19#ifndef _DEV_ATH_AR5212REG_H_
20#define _DEV_ATH_AR5212REG_H_
21
22/*
23 * Definitions for the Atheros 5212 chipset.
24 */
25
26/* DMA Control and Interrupt Registers */
27#define AR_CR 0x0008 /* MAC control register */
28#define AR_RXDP 0x000C /* MAC receive queue descriptor pointer */
29#define AR_CFG 0x0014 /* MAC configuration and status register */
30#define AR_IER 0x0024 /* MAC Interrupt enable register */
31/* 0x28 is RTSD0 on the 5211 */
32/* 0x2c is RTSD1 on the 5211 */
33#define AR_TXCFG 0x0030 /* MAC tx DMA size config register */
34#define AR_RXCFG 0x0034 /* MAC rx DMA size config register */
35/* 0x38 is the jumbo descriptor address on the 5211 */
36#define AR_MIBC 0x0040 /* MAC MIB control register */
37#define AR_TOPS 0x0044 /* MAC timeout prescale count */
38#define AR_RXNPTO 0x0048 /* MAC no frame received timeout */
39#define AR_TXNPTO 0x004C /* MAC no frame trasmitted timeout */
40#define AR_RPGTO 0x0050 /* MAC receive frame gap timeout */
41#define AR_RPCNT 0x0054 /* MAC receive frame count limit */
42#define AR_MACMISC 0x0058 /* MAC miscellaneous control/status register */
43#define AR_SPC_0 0x005c /* MAC sleep performance (awake cycles) */
44#define AR_SPC_1 0x0060 /* MAC sleep performance (asleep cycles) */
45/* 0x5c is for QCU/DCU clock gating control on 5311 */
46#define AR_ISR 0x0080 /* MAC Primary interrupt status register */
47#define AR_ISR_S0 0x0084 /* MAC Secondary interrupt status register 0 */
48#define AR_ISR_S1 0x0088 /* MAC Secondary interrupt status register 1 */
49#define AR_ISR_S2 0x008c /* MAC Secondary interrupt status register 2 */
50#define AR_ISR_S3 0x0090 /* MAC Secondary interrupt status register 3 */
51#define AR_ISR_S4 0x0094 /* MAC Secondary interrupt status register 4 */
52#define AR_IMR 0x00a0 /* MAC Primary interrupt mask register */
53#define AR_IMR_S0 0x00a4 /* MAC Secondary interrupt mask register 0 */
54#define AR_IMR_S1 0x00a8 /* MAC Secondary interrupt mask register 1 */
55#define AR_IMR_S2 0x00ac /* MAC Secondary interrupt mask register 2 */
56#define AR_IMR_S3 0x00b0 /* MAC Secondary interrupt mask register 3 */
57#define AR_IMR_S4 0x00b4 /* MAC Secondary interrupt mask register 4 */
58#define AR_ISR_RAC 0x00c0 /* ISR read-and-clear access */
59/* Shadow copies with read-and-clear access */
60#define AR_ISR_S0_S 0x00c4 /* ISR_S0 shadow copy */
61#define AR_ISR_S1_S 0x00c8 /* ISR_S1 shadow copy */
62#define AR_ISR_S2_S 0x00cc /* ISR_S2 shadow copy */
63#define AR_ISR_S3_S 0x00d0 /* ISR_S3 shadow copy */
64#define AR_ISR_S4_S 0x00d4 /* ISR_S4 shadow copy */
65#define AR_DMADBG_0 0x00e0 /* DMA debug 0 */
66#define AR_DMADBG_1 0x00e4 /* DMA debug 1 */
67#define AR_DMADBG_2 0x00e8 /* DMA debug 2 */
68#define AR_DMADBG_3 0x00ec /* DMA debug 3 */
69#define AR_DMADBG_4 0x00f0 /* DMA debug 4 */
70#define AR_DMADBG_5 0x00f4 /* DMA debug 5 */
71#define AR_DMADBG_6 0x00f8 /* DMA debug 6 */
72#define AR_DMADBG_7 0x00fc /* DMA debug 7 */
73#define AR_DCM_A 0x0400 /* Decompression mask address */
74#define AR_DCM_D 0x0404 /* Decompression mask data */
75#define AR_DCCFG 0x0420 /* Decompression configuration */
76#define AR_CCFG 0x0600 /* Compression configuration */
77#define AR_CCUCFG 0x0604 /* Compression catchup configuration */
78#define AR_CPC_0 0x0610 /* Compression performance counter 0 */
79#define AR_CPC_1 0x0614 /* Compression performance counter 1 */
80#define AR_CPC_2 0x0618 /* Compression performance counter 2 */
81#define AR_CPC_3 0x061c /* Compression performance counter 3 */
82#define AR_CPCOVF 0x0620 /* Compression performance overflow status */
83
84#define AR_Q0_TXDP 0x0800 /* MAC Transmit Queue descriptor pointer */
85#define AR_Q1_TXDP 0x0804 /* MAC Transmit Queue descriptor pointer */
86#define AR_Q2_TXDP 0x0808 /* MAC Transmit Queue descriptor pointer */
87#define AR_Q3_TXDP 0x080c /* MAC Transmit Queue descriptor pointer */
88#define AR_Q4_TXDP 0x0810 /* MAC Transmit Queue descriptor pointer */
89#define AR_Q5_TXDP 0x0814 /* MAC Transmit Queue descriptor pointer */
90#define AR_Q6_TXDP 0x0818 /* MAC Transmit Queue descriptor pointer */
91#define AR_Q7_TXDP 0x081c /* MAC Transmit Queue descriptor pointer */
92#define AR_Q8_TXDP 0x0820 /* MAC Transmit Queue descriptor pointer */
93#define AR_Q9_TXDP 0x0824 /* MAC Transmit Queue descriptor pointer */
94#define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2))
95
96#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */
97#define AR_Q_TXD 0x0880 /* MAC Transmit Queue disable */
98
99#define AR_Q0_CBRCFG 0x08c0 /* MAC CBR configuration */
100#define AR_Q1_CBRCFG 0x08c4 /* MAC CBR configuration */
101#define AR_Q2_CBRCFG 0x08c8 /* MAC CBR configuration */
102#define AR_Q3_CBRCFG 0x08cc /* MAC CBR configuration */
103#define AR_Q4_CBRCFG 0x08d0 /* MAC CBR configuration */
104#define AR_Q5_CBRCFG 0x08d4 /* MAC CBR configuration */
105#define AR_Q6_CBRCFG 0x08d8 /* MAC CBR configuration */
106#define AR_Q7_CBRCFG 0x08dc /* MAC CBR configuration */
107#define AR_Q8_CBRCFG 0x08e0 /* MAC CBR configuration */
108#define AR_Q9_CBRCFG 0x08e4 /* MAC CBR configuration */
109#define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2))
110
111#define AR_Q0_RDYTIMECFG 0x0900 /* MAC ReadyTime configuration */
112#define AR_Q1_RDYTIMECFG 0x0904 /* MAC ReadyTime configuration */
113#define AR_Q2_RDYTIMECFG 0x0908 /* MAC ReadyTime configuration */
114#define AR_Q3_RDYTIMECFG 0x090c /* MAC ReadyTime configuration */
115#define AR_Q4_RDYTIMECFG 0x0910 /* MAC ReadyTime configuration */
116#define AR_Q5_RDYTIMECFG 0x0914 /* MAC ReadyTime configuration */
117#define AR_Q6_RDYTIMECFG 0x0918 /* MAC ReadyTime configuration */
118#define AR_Q7_RDYTIMECFG 0x091c /* MAC ReadyTime configuration */
119#define AR_Q8_RDYTIMECFG 0x0920 /* MAC ReadyTime configuration */
120#define AR_Q9_RDYTIMECFG 0x0924 /* MAC ReadyTime configuration */
121#define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2))
122
123#define AR_Q_ONESHOTARM_SC 0x0940 /* MAC OneShotArm set control */
124#define AR_Q_ONESHOTARM_CC 0x0980 /* MAC OneShotArm clear control */
125
126#define AR_Q0_MISC 0x09c0 /* MAC Miscellaneous QCU settings */
127#define AR_Q1_MISC 0x09c4 /* MAC Miscellaneous QCU settings */
128#define AR_Q2_MISC 0x09c8 /* MAC Miscellaneous QCU settings */
129#define AR_Q3_MISC 0x09cc /* MAC Miscellaneous QCU settings */
130#define AR_Q4_MISC 0x09d0 /* MAC Miscellaneous QCU settings */
131#define AR_Q5_MISC 0x09d4 /* MAC Miscellaneous QCU settings */
132#define AR_Q6_MISC 0x09d8 /* MAC Miscellaneous QCU settings */
133#define AR_Q7_MISC 0x09dc /* MAC Miscellaneous QCU settings */
134#define AR_Q8_MISC 0x09e0 /* MAC Miscellaneous QCU settings */
135#define AR_Q9_MISC 0x09e4 /* MAC Miscellaneous QCU settings */
136#define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2))
137
138#define AR_Q0_STS 0x0a00 /* MAC Miscellaneous QCU status */
139#define AR_Q1_STS 0x0a04 /* MAC Miscellaneous QCU status */
140#define AR_Q2_STS 0x0a08 /* MAC Miscellaneous QCU status */
141#define AR_Q3_STS 0x0a0c /* MAC Miscellaneous QCU status */
142#define AR_Q4_STS 0x0a10 /* MAC Miscellaneous QCU status */
143#define AR_Q5_STS 0x0a14 /* MAC Miscellaneous QCU status */
144#define AR_Q6_STS 0x0a18 /* MAC Miscellaneous QCU status */
145#define AR_Q7_STS 0x0a1c /* MAC Miscellaneous QCU status */
146#define AR_Q8_STS 0x0a20 /* MAC Miscellaneous QCU status */
147#define AR_Q9_STS 0x0a24 /* MAC Miscellaneous QCU status */
148#define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2))
149
150#define AR_Q_RDYTIMESHDN 0x0a40 /* MAC ReadyTimeShutdown status */
151#define AR_Q_CBBS 0xb00 /* Compression buffer base select */
152#define AR_Q_CBBA 0xb04 /* Compression buffer base access */
153#define AR_Q_CBC 0xb08 /* Compression buffer configuration */
154
155#define AR_D0_QCUMASK 0x1000 /* MAC QCU Mask */
156#define AR_D1_QCUMASK 0x1004 /* MAC QCU Mask */
157#define AR_D2_QCUMASK 0x1008 /* MAC QCU Mask */
158#define AR_D3_QCUMASK 0x100c /* MAC QCU Mask */
159#define AR_D4_QCUMASK 0x1010 /* MAC QCU Mask */
160#define AR_D5_QCUMASK 0x1014 /* MAC QCU Mask */
161#define AR_D6_QCUMASK 0x1018 /* MAC QCU Mask */
162#define AR_D7_QCUMASK 0x101c /* MAC QCU Mask */
163#define AR_D8_QCUMASK 0x1020 /* MAC QCU Mask */
164#define AR_D9_QCUMASK 0x1024 /* MAC QCU Mask */
165#define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2))
166
167#define AR_D0_LCL_IFS 0x1040 /* MAC DCU-specific IFS settings */
168#define AR_D1_LCL_IFS 0x1044 /* MAC DCU-specific IFS settings */
169#define AR_D2_LCL_IFS 0x1048 /* MAC DCU-specific IFS settings */
170#define AR_D3_LCL_IFS 0x104c /* MAC DCU-specific IFS settings */
171#define AR_D4_LCL_IFS 0x1050 /* MAC DCU-specific IFS settings */
172#define AR_D5_LCL_IFS 0x1054 /* MAC DCU-specific IFS settings */
173#define AR_D6_LCL_IFS 0x1058 /* MAC DCU-specific IFS settings */
174#define AR_D7_LCL_IFS 0x105c /* MAC DCU-specific IFS settings */
175#define AR_D8_LCL_IFS 0x1060 /* MAC DCU-specific IFS settings */
176#define AR_D9_LCL_IFS 0x1064 /* MAC DCU-specific IFS settings */
177#define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2))
178
179#define AR_D0_RETRY_LIMIT 0x1080 /* MAC Retry limits */
180#define AR_D1_RETRY_LIMIT 0x1084 /* MAC Retry limits */
181#define AR_D2_RETRY_LIMIT 0x1088 /* MAC Retry limits */
182#define AR_D3_RETRY_LIMIT 0x108c /* MAC Retry limits */
183#define AR_D4_RETRY_LIMIT 0x1090 /* MAC Retry limits */
184#define AR_D5_RETRY_LIMIT 0x1094 /* MAC Retry limits */
185#define AR_D6_RETRY_LIMIT 0x1098 /* MAC Retry limits */
186#define AR_D7_RETRY_LIMIT 0x109c /* MAC Retry limits */
187#define AR_D8_RETRY_LIMIT 0x10a0 /* MAC Retry limits */
188#define AR_D9_RETRY_LIMIT 0x10a4 /* MAC Retry limits */
189#define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2))
190
191#define AR_D0_CHNTIME 0x10c0 /* MAC ChannelTime settings */
192#define AR_D1_CHNTIME 0x10c4 /* MAC ChannelTime settings */
193#define AR_D2_CHNTIME 0x10c8 /* MAC ChannelTime settings */
194#define AR_D3_CHNTIME 0x10cc /* MAC ChannelTime settings */
195#define AR_D4_CHNTIME 0x10d0 /* MAC ChannelTime settings */
196#define AR_D5_CHNTIME 0x10d4 /* MAC ChannelTime settings */
197#define AR_D6_CHNTIME 0x10d8 /* MAC ChannelTime settings */
198#define AR_D7_CHNTIME 0x10dc /* MAC ChannelTime settings */
199#define AR_D8_CHNTIME 0x10e0 /* MAC ChannelTime settings */
200#define AR_D9_CHNTIME 0x10e4 /* MAC ChannelTime settings */
201#define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2))
202
203#define AR_D0_MISC 0x1100 /* MAC Miscellaneous DCU-specific settings */
204#define AR_D1_MISC 0x1104 /* MAC Miscellaneous DCU-specific settings */
205#define AR_D2_MISC 0x1108 /* MAC Miscellaneous DCU-specific settings */
206#define AR_D3_MISC 0x110c /* MAC Miscellaneous DCU-specific settings */
207#define AR_D4_MISC 0x1110 /* MAC Miscellaneous DCU-specific settings */
208#define AR_D5_MISC 0x1114 /* MAC Miscellaneous DCU-specific settings */
209#define AR_D6_MISC 0x1118 /* MAC Miscellaneous DCU-specific settings */
210#define AR_D7_MISC 0x111c /* MAC Miscellaneous DCU-specific settings */
211#define AR_D8_MISC 0x1120 /* MAC Miscellaneous DCU-specific settings */
212#define AR_D9_MISC 0x1124 /* MAC Miscellaneous DCU-specific settings */
213#define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2))
214
215#define AR_D_SEQNUM 0x1140 /* MAC Frame sequence number */
216
217/* MAC DCU-global IFS settings */
218#define AR_D_GBL_IFS_SIFS 0x1030 /* DCU global SIFS settings */
219#define AR_D_GBL_IFS_SLOT 0x1070 /* DC global slot interval */
220#define AR_D_GBL_IFS_EIFS 0x10b0 /* DCU global EIFS setting */
221#define AR_D_GBL_IFS_MISC 0x10f0 /* DCU global misc. IFS settings */
222#define AR_D_FPCTL 0x1230 /* DCU frame prefetch settings */
223#define AR_D_TXPSE 0x1270 /* DCU transmit pause control/status */
224#define AR_D_TXBLK_CMD 0x1038 /* DCU transmit filter cmd (w/only) */
225#define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) /* DCU transmit filter data */
226#define AR_D_TXBLK_CLR 0x143c /* DCU clear tx filter (w/only) */
227#define AR_D_TXBLK_SET 0x147c /* DCU set tx filter (w/only) */
228
229#define AR_RC 0x4000 /* Warm reset control register */
230#define AR_SCR 0x4004 /* Sleep control register */
231#define AR_INTPEND 0x4008 /* Interrupt Pending register */
232#define AR_SFR 0x400C /* Sleep force register */
233#define AR_PCICFG 0x4010 /* PCI configuration register */
234#define AR_GPIOCR 0x4014 /* GPIO control register */
235#define AR_GPIODO 0x4018 /* GPIO data output access register */
236#define AR_GPIODI 0x401C /* GPIO data input access register */
237#define AR_SREV 0x4020 /* Silicon Revision register */
238#define AR_TXEPOST 0x4028 /* TXE write posting resgister */
239#define AR_QSM 0x402C /* QCU sleep mask */
240
241#define AR_PCIE_PMC 0x4068 /* PCIe power mgt config and status register */
242#define AR_PCIE_SERDES 0x4080 /* PCIe Serdes register */
243#define AR_PCIE_SERDES2 0x4084 /* PCIe Serdes register */
244
245#define AR_EEPROM_ADDR 0x6000 /* EEPROM address register (10 bit) */
246#define AR_EEPROM_DATA 0x6004 /* EEPROM data register (16 bit) */
247#define AR_EEPROM_CMD 0x6008 /* EEPROM command register */
248#define AR_EEPROM_STS 0x600c /* EEPROM status register */
249#define AR_EEPROM_CFG 0x6010 /* EEPROM configuration register */
250
251#define AR_STA_ID0 0x8000 /* MAC station ID0 register - low 32 bits */
252#define AR_STA_ID1 0x8004 /* MAC station ID1 register - upper 16 bits */
253#define AR_BSS_ID0 0x8008 /* MAC BSSID low 32 bits */
254#define AR_BSS_ID1 0x800C /* MAC BSSID upper 16 bits / AID */
255#define AR_SLOT_TIME 0x8010 /* MAC Time-out after a collision */
256#define AR_TIME_OUT 0x8014 /* MAC ACK & CTS time-out */
257#define AR_RSSI_THR 0x8018 /* MAC RSSI warning & missed beacon threshold */
258#define AR_USEC 0x801c /* MAC transmit latency register */
259#define AR_BEACON 0x8020 /* MAC beacon control value/mode bits */
260#define AR_CFP_PERIOD 0x8024 /* MAC CFP Interval (TU/msec) */
261#define AR_TIMER0 0x8028 /* MAC Next beacon time (TU/msec) */
262#define AR_TIMER1 0x802c /* MAC DMA beacon alert time (1/8 TU) */
263#define AR_TIMER2 0x8030 /* MAC Software beacon alert (1/8 TU) */
264#define AR_TIMER3 0x8034 /* MAC ATIM window time */
265#define AR_CFP_DUR 0x8038 /* MAC maximum CFP duration in TU */
266#define AR_RX_FILTER 0x803C /* MAC receive filter register */
267#define AR_MCAST_FIL0 0x8040 /* MAC multicast filter lower 32 bits */
268#define AR_MCAST_FIL1 0x8044 /* MAC multicast filter upper 32 bits */
269#define AR_DIAG_SW 0x8048 /* MAC PCU control register */
270#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */
271#define AR_TSF_U32 0x8050 /* MAC local clock upper 32 bits */
272#define AR_TST_ADDAC 0x8054 /* ADDAC test register */
273#define AR_DEF_ANTENNA 0x8058 /* default antenna register */
274#define AR_QOS_MASK 0x805c /* MAC AES mute mask: QoS field */
275#define AR_SEQ_MASK 0x8060 /* MAC AES mute mask: seqnum field */
276#define AR_OBSERV_2 0x8068 /* Observation bus 2 */
277#define AR_OBSERV_1 0x806c /* Observation bus 1 */
278
279#define AR_LAST_TSTP 0x8080 /* MAC Time stamp of the last beacon received */
280#define AR_NAV 0x8084 /* MAC current NAV value */
281#define AR_RTS_OK 0x8088 /* MAC RTS exchange success counter */
282#define AR_RTS_FAIL 0x808c /* MAC RTS exchange failure counter */
283#define AR_ACK_FAIL 0x8090 /* MAC ACK failure counter */
284#define AR_FCS_FAIL 0x8094 /* FCS check failure counter */
285#define AR_BEACON_CNT 0x8098 /* Valid beacon counter */
286
287#define AR_SLEEP1 0x80d4 /* Enhanced sleep control 1 */
288#define AR_SLEEP2 0x80d8 /* Enhanced sleep control 2 */
289#define AR_SLEEP3 0x80dc /* Enhanced sleep control 3 */
290#define AR_BSSMSKL 0x80e0 /* BSSID mask lower 32 bits */
291#define AR_BSSMSKU 0x80e4 /* BSSID mask upper 16 bits */
292#define AR_TPC 0x80e8 /* Transmit power control for self gen frames */
293#define AR_TFCNT 0x80ec /* Profile count, transmit frames */
294#define AR_RFCNT 0x80f0 /* Profile count, receive frames */
295#define AR_RCCNT 0x80f4 /* Profile count, receive clear */
296#define AR_CCCNT 0x80f8 /* Profile count, cycle counter */
297
298#define AR_QUIET1 0x80fc /* Quiet time programming for TGh */
299#define AR_QUIET1_NEXT_QUIET_S 0 /* TSF of next quiet period (TU) */
300#define AR_QUIET1_NEXT_QUIET 0xffff
301#define AR_QUIET1_QUIET_ENABLE 0x10000 /* Enable Quiet time operation */
302#define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x20000 /* Do we ack/cts during quiet period */
303
304#define AR_QUIET2 0x8100 /* More Quiet time programming */
305#define AR_QUIET2_QUIET_PER_S 0 /* Periodicity of quiet period (TU) */
306#define AR_QUIET2_QUIET_PER 0xffff
307#define AR_QUIET2_QUIET_DUR_S 16 /* Duration of quiet period (TU) */
308#define AR_QUIET2_QUIET_DUR 0xffff0000
309
310#define AR_TSF_PARM 0x8104 /* TSF parameters */
311#define AR_NOACK 0x8108 /* No ack policy in QoS Control Field */
312#define AR_PHY_ERR 0x810c /* Phy error filter */
313
314#define AR_QOS_CONTROL 0x8118 /* Control TKIP MIC for QoS */
315#define AR_QOS_SELECT 0x811c /* MIC QoS select */
316#define AR_MISC_MODE 0x8120 /* PCU Misc. mode control */
317
318/* Hainan MIB counter registers */
319#define AR_FILTOFDM 0x8124 /* Count of filtered OFDM frames */
320#define AR_FILTCCK 0x8128 /* Count of filtered CCK frames */
321#define AR_PHYCNT1 0x812c /* Phy Error 1 counter */
322#define AR_PHYCNTMASK1 0x8130 /* Phy Error 1 counter mask */
323#define AR_PHYCNT2 0x8134 /* Phy Error 2 counter */
324#define AR_PHYCNTMASK2 0x8138 /* Phy Error 2 counter mask */
325#define AR_PHY_COUNTMAX (3 << 22) /* Max value in counter before intr */
326#define AR_MIBCNT_INTRMASK (3<<22) /* Mask for top two bits of counters */
327
328#define AR_RATE_DURATION_0 0x8700 /* base of multi-rate retry */
329#define AR_RATE_DURATION(_n) (AR_RATE_DURATION_0 + ((_n)<<2))
330
331#define AR_KEYTABLE_0 0x8800 /* MAC Key Cache */
332#define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32))
333
334#define AR_CFP_MASK 0x0000ffff /* Mask for next beacon time */
335
336#define AR_CR_RXE 0x00000004 /* Receive enable */
337#define AR_CR_RXD 0x00000020 /* Receive disable */
338#define AR_CR_SWI 0x00000040 /* One-shot software interrupt */
339
340#define AR_CFG_SWTD 0x00000001 /* byteswap tx descriptor words */
341#define AR_CFG_SWTB 0x00000002 /* byteswap tx data buffer words */
342#define AR_CFG_SWRD 0x00000004 /* byteswap rx descriptor words */
343#define AR_CFG_SWRB 0x00000008 /* byteswap rx data buffer words */
344#define AR_CFG_SWRG 0x00000010 /* byteswap register access data words */
345#define AR_CFG_AP_ADHOC_INDICATION 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
346#define AR_CFG_PHOK 0x00000100 /* PHY OK status */
347#define AR_CFG_EEBS 0x00000200 /* EEPROM busy */
348#define AR_5211_CFG_CLK_GATE_DIS 0x00000400 /* Clock gating disable (Oahu only) */
349#define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 /* Mask of PCI core master request queue full threshold */
350#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 /* Shift for PCI core master request queue full threshold */
351
352#define AR_IER_ENABLE 0x00000001 /* Global interrupt enable */
353#define AR_IER_DISABLE 0x00000000 /* Global interrupt disable */
354
355#define AR_DMASIZE_4B 0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */
356#define AR_DMASIZE_8B 0x00000001 /* DMA size 8 bytes */
357#define AR_DMASIZE_16B 0x00000002 /* DMA size 16 bytes */
358#define AR_DMASIZE_32B 0x00000003 /* DMA size 32 bytes */
359#define AR_DMASIZE_64B 0x00000004 /* DMA size 64 bytes */
360#define AR_DMASIZE_128B 0x00000005 /* DMA size 128 bytes */
361#define AR_DMASIZE_256B 0x00000006 /* DMA size 256 bytes */
362#define AR_DMASIZE_512B 0x00000007 /* DMA size 512 bytes */
363
364#define AR_FTRIG 0x000003F0 /* Mask for Frame trigger level */
365#define AR_FTRIG_S 4 /* Shift for Frame trigger level */
366#define AR_FTRIG_IMMED 0x00000000 /* bytes in PCU TX FIFO before air */
367#define AR_FTRIG_64B 0x00000010 /* default */
368#define AR_FTRIG_128B 0x00000020
369#define AR_FTRIG_192B 0x00000030
370#define AR_FTRIG_256B 0x00000040 /* 5 bits total */
371
372#define AR_RXCFG_ZLFDMA 0x00000010 /* Enable DMA of zero-length frame */
373
374#define AR_MIBC_COW 0x00000001 /* counter overflow warning */
375#define AR_MIBC_FMC 0x00000002 /* freeze MIB counters */
376#define AR_MIBC_CMC 0x00000004 /* clear MIB counters */
377#define AR_MIBC_MCS 0x00000008 /* MIB counter strobe, increment all */
378
379#define AR_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */
380
381#define AR_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */
382
383#define AR_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */
384#define AR_TXNPTO_QCU_MASK 0x000FFC00 /* Mask indicating the set of QCUs */
385 /* for which frame completions will cause */
386 /* a reset of the no frame xmit'd timeout */
387
388#define AR_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */
389
390#define AR_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */
391
392#define AR_MACMISC_DMA_OBS 0x000001E0 /* Mask for DMA observation bus mux select */
393#define AR_MACMISC_DMA_OBS_S 5 /* Shift for DMA observation bus mux select */
394#define AR_MACMISC_MISC_OBS 0x00000E00 /* Mask for MISC observation bus mux select */
395#define AR_MACMISC_MISC_OBS_S 9 /* Shift for MISC observation bus mux select */
396#define AR_MACMISC_MAC_OBS_BUS_LSB 0x00007000 /* Mask for MAC observation bus mux select (lsb) */
397#define AR_MACMISC_MAC_OBS_BUS_LSB_S 12 /* Shift for MAC observation bus mux select (lsb) */
398#define AR_MACMISC_MAC_OBS_BUS_MSB 0x00038000 /* Mask for MAC observation bus mux select (msb) */
399#define AR_MACMISC_MAC_OBS_BUS_MSB_S 15 /* Shift for MAC observation bus mux select (msb) */
400
401/*
402 * Interrupt Status Registers
403 *
404 * Only the bits in the ISR_P register and the IMR_P registers
405 * control whether the MAC's INTA# output is asserted. The bits in
406 * the secondary interrupt status/mask registers control what bits
407 * are set in the primary interrupt status register; however the
408 * IMR_S* registers DO NOT determine whether INTA# is asserted.
409 * That is INTA# is asserted only when the logical AND of ISR_P
410 * and IMR_P is non-zero. The secondary interrupt mask/status
411 * registers affect what bits are set in ISR_P but they do not
412 * directly affect whether INTA# is asserted.
413 */
414#define AR_ISR_RXOK 0x00000001 /* At least one frame received sans errors */
415#define AR_ISR_RXDESC 0x00000002 /* Receive interrupt request */
416#define AR_ISR_RXERR 0x00000004 /* Receive error interrupt */
417#define AR_ISR_RXNOPKT 0x00000008 /* No frame received within timeout clock */
418#define AR_ISR_RXEOL 0x00000010 /* Received descriptor empty interrupt */
419#define AR_ISR_RXORN 0x00000020 /* Receive FIFO overrun interrupt */
420#define AR_ISR_TXOK 0x00000040 /* Transmit okay interrupt */
421#define AR_ISR_TXDESC 0x00000080 /* Transmit interrupt request */
422#define AR_ISR_TXERR 0x00000100 /* Transmit error interrupt */
423#define AR_ISR_TXNOPKT 0x00000200 /* No frame transmitted interrupt */
424#define AR_ISR_TXEOL 0x00000400 /* Transmit descriptor empty interrupt */
425#define AR_ISR_TXURN 0x00000800 /* Transmit FIFO underrun interrupt */
426#define AR_ISR_MIB 0x00001000 /* MIB interrupt - see MIBC */
427#define AR_ISR_SWI 0x00002000 /* Software interrupt */
428#define AR_ISR_RXPHY 0x00004000 /* PHY receive error interrupt */
429#define AR_ISR_RXKCM 0x00008000 /* Key-cache miss interrupt */
430#define AR_ISR_SWBA 0x00010000 /* Software beacon alert interrupt */
431#define AR_ISR_BRSSI 0x00020000 /* Beacon threshold interrupt */
432#define AR_ISR_BMISS 0x00040000 /* Beacon missed interrupt */
433#define AR_ISR_HIUERR 0x00080000 /* An unexpected bus error has occurred */
434#define AR_ISR_BNR 0x00100000 /* Beacon not ready interrupt */
435#define AR_ISR_RXCHIRP 0x00200000 /* Phy received a 'chirp' */
436#define AR_ISR_RXDOPPL 0x00400000 /* Phy received a 'doppler chirp' */
437#define AR_ISR_BCNMISC 0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO,
438 CABTO, DTIM bits from ISR_S2 */
439#define AR_ISR_TIM 0x00800000 /* TIM interrupt */
440#define AR_ISR_GPIO 0x01000000 /* GPIO Interrupt */
441#define AR_ISR_QCBROVF 0x02000000 /* QCU CBR overflow interrupt */
442#define AR_ISR_QCBRURN 0x04000000 /* QCU CBR underrun interrupt */
443#define AR_ISR_QTRIG 0x08000000 /* QCU scheduling trigger interrupt */
444#define AR_ISR_RESV0 0xF0000000 /* Reserved */
445
446#define AR_ISR_S0_QCU_TXOK 0x000003FF /* Mask for TXOK (QCU 0-9) */
447#define AR_ISR_S0_QCU_TXOK_S 0
448#define AR_ISR_S0_QCU_TXDESC 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
449#define AR_ISR_S0_QCU_TXDESC_S 16
450
451#define AR_ISR_S1_QCU_TXERR 0x000003FF /* Mask for TXERR (QCU 0-9) */
452#define AR_ISR_S1_QCU_TXERR_S 0
453#define AR_ISR_S1_QCU_TXEOL 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
454#define AR_ISR_S1_QCU_TXEOL_S 16
455
456#define AR_ISR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */
457#define AR_ISR_S2_MCABT 0x00010000 /* Master cycle abort interrupt */
458#define AR_ISR_S2_SSERR 0x00020000 /* SERR interrupt */
459#define AR_ISR_S2_DPERR 0x00040000 /* PCI bus parity error */
460#define AR_ISR_S2_TIM 0x01000000 /* TIM */
461#define AR_ISR_S2_CABEND 0x02000000 /* CABEND */
462#define AR_ISR_S2_DTIMSYNC 0x04000000 /* DTIMSYNC */
463#define AR_ISR_S2_BCNTO 0x08000000 /* BCNTO */
464#define AR_ISR_S2_CABTO 0x10000000 /* CABTO */
465#define AR_ISR_S2_DTIM 0x20000000 /* DTIM */
466#define AR_ISR_S2_TSFOOR 0x40000000 /* TSF OOR */
467#define AR_ISR_S2_TBTT 0x80000000 /* TBTT timer */
468
469#define AR_ISR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
470#define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
471
472#define AR_ISR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */
473#define AR_ISR_S4_RESV0 0xFFFFFC00 /* Reserved */
474
475/*
476 * Interrupt Mask Registers
477 *
478 * Only the bits in the IMR control whether the MAC's INTA#
479 * output will be asserted. The bits in the secondary interrupt
480 * mask registers control what bits get set in the primary
481 * interrupt status register; however the IMR_S* registers
482 * DO NOT determine whether INTA# is asserted.
483 */
484#define AR_IMR_RXOK 0x00000001 /* At least one frame received sans errors */
485#define AR_IMR_RXDESC 0x00000002 /* Receive interrupt request */
486#define AR_IMR_RXERR 0x00000004 /* Receive error interrupt */
487#define AR_IMR_RXNOPKT 0x00000008 /* No frame received within timeout clock */
488#define AR_IMR_RXEOL 0x00000010 /* Received descriptor empty interrupt */
489#define AR_IMR_RXORN 0x00000020 /* Receive FIFO overrun interrupt */
490#define AR_IMR_TXOK 0x00000040 /* Transmit okay interrupt */
491#define AR_IMR_TXDESC 0x00000080 /* Transmit interrupt request */
492#define AR_IMR_TXERR 0x00000100 /* Transmit error interrupt */
493#define AR_IMR_TXNOPKT 0x00000200 /* No frame transmitted interrupt */
494#define AR_IMR_TXEOL 0x00000400 /* Transmit descriptor empty interrupt */
495#define AR_IMR_TXURN 0x00000800 /* Transmit FIFO underrun interrupt */
496#define AR_IMR_MIB 0x00001000 /* MIB interrupt - see MIBC */
497#define AR_IMR_SWI 0x00002000 /* Software interrupt */
498#define AR_IMR_RXPHY 0x00004000 /* PHY receive error interrupt */
499#define AR_IMR_RXKCM 0x00008000 /* Key-cache miss interrupt */
500#define AR_IMR_SWBA 0x00010000 /* Software beacon alert interrupt */
501#define AR_IMR_BRSSI 0x00020000 /* Beacon threshold interrupt */
502#define AR_IMR_BMISS 0x00040000 /* Beacon missed interrupt */
503#define AR_IMR_HIUERR 0x00080000 /* An unexpected bus error has occurred */
504#define AR_IMR_BNR 0x00100000 /* BNR interrupt */
505#define AR_IMR_RXCHIRP 0x00200000 /* RXCHIRP interrupt */
506#define AR_IMR_BCNMISC 0x00800000 /* Venice: BCNMISC */
507#define AR_IMR_TIM 0x00800000 /* TIM interrupt */
508#define AR_IMR_GPIO 0x01000000 /* GPIO Interrupt */
509#define AR_IMR_QCBROVF 0x02000000 /* QCU CBR overflow interrupt */
510#define AR_IMR_QCBRURN 0x04000000 /* QCU CBR underrun interrupt */
511#define AR_IMR_QTRIG 0x08000000 /* QCU scheduling trigger interrupt */
512#define AR_IMR_RESV0 0xF0000000 /* Reserved */
513
514#define AR_IMR_S0_QCU_TXOK 0x000003FF /* TXOK (QCU 0-9) */
515#define AR_IMR_S0_QCU_TXOK_S 0
516#define AR_IMR_S0_QCU_TXDESC 0x03FF0000 /* TXDESC (QCU 0-9) */
517#define AR_IMR_S0_QCU_TXDESC_S 16
518
519#define AR_IMR_S1_QCU_TXERR 0x000003FF /* TXERR (QCU 0-9) */
520#define AR_IMR_S1_QCU_TXERR_S 0
521#define AR_IMR_S1_QCU_TXEOL 0x03FF0000 /* TXEOL (QCU 0-9) */
522#define AR_IMR_S1_QCU_TXEOL_S 16
523
524#define AR_IMR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */
525#define AR_IMR_S2_QCU_TXURN_S 0
526#define AR_IMR_S2_MCABT 0x00010000 /* Master cycle abort interrupt */
527#define AR_IMR_S2_SSERR 0x00020000 /* SERR interrupt */
528#define AR_IMR_S2_DPERR 0x00040000 /* PCI bus parity error */
529#define AR_IMR_S2_TIM 0x01000000 /* TIM */
530#define AR_IMR_S2_CABEND 0x02000000 /* CABEND */
531#define AR_IMR_S2_DTIMSYNC 0x04000000 /* DTIMSYNC */
532#define AR_IMR_S2_BCNTO 0x08000000 /* BCNTO */
533#define AR_IMR_S2_CABTO 0x10000000 /* CABTO */
534#define AR_IMR_S2_DTIM 0x20000000 /* DTIM */
535#define AR_IMR_S2_TSFOOR 0x40000000 /* TSF OOR */
536#define AR_IMR_S2_TBTT 0x80000000 /* TBTT timer */
537
538/* AR_IMR_SR2 bits that correspond to AR_IMR_BCNMISC */
539#define AR_IMR_SR2_BCNMISC \
540 (AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | \
541 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR | \
542 AR_IMR_S2_TBTT)
543
544#define AR_IMR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
545#define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
546#define AR_IMR_S3_QCU_QCBRURN_S 16 /* Shift for QCBRURN (QCU 0-9) */
547
548#define AR_IMR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */
549#define AR_IMR_S4_RESV0 0xFFFFFC00 /* Reserved */
550
551/* QCU registers */
552#define AR_NUM_QCU 10 /* Only use QCU 0-9 for forward QCU compatibility */
553#define AR_QCU_0 0x0001
554#define AR_QCU_1 0x0002
555#define AR_QCU_2 0x0004
556#define AR_QCU_3 0x0008
557#define AR_QCU_4 0x0010
558#define AR_QCU_5 0x0020
559#define AR_QCU_6 0x0040
560#define AR_QCU_7 0x0080
561#define AR_QCU_8 0x0100
562#define AR_QCU_9 0x0200
563
564#define AR_Q_CBRCFG_CBR_INTERVAL 0x00FFFFFF /* Mask for CBR interval (us) */
565#define AR_Q_CBRCFG_CBR_INTERVAL_S 0 /* Shift for CBR interval */
566#define AR_Q_CBRCFG_CBR_OVF_THRESH 0xFF000000 /* Mask for CBR overflow threshold */
567#define AR_Q_CBRCFG_CBR_OVF_THRESH_S 24 /* Shift for CBR overflow thresh */
568
569#define AR_Q_RDYTIMECFG_INT 0x00FFFFFF /* CBR interval (us) */
570#define AR_Q_RDYTIMECFG_INT_S 0 // Shift for ReadyTime Interval (us) */
571#define AR_Q_RDYTIMECFG_ENA 0x01000000 /* CBR enable */
572/* bits 25-31 are reserved */
573
574#define AR_Q_MISC_FSP 0x0000000F /* Frame Scheduling Policy mask */
575#define AR_Q_MISC_FSP_ASAP 0 /* ASAP */
576#define AR_Q_MISC_FSP_CBR 1 /* CBR */
577#define AR_Q_MISC_FSP_DBA_GATED 2 /* DMA Beacon Alert gated */
578#define AR_Q_MISC_FSP_TIM_GATED 3 /* TIM gated */
579#define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */
580#define AR_Q_MISC_FSP_S 0
581#define AR_Q_MISC_ONE_SHOT_EN 0x00000010 /* OneShot enable */
582#define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 /* Disable CBR expired counter incr
583 (empty q) */
584#define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 /* Disable CBR expired counter incr
585 (empty beacon q) */
586#define AR_Q_MISC_BEACON_USE 0x00000080 /* Beacon use indication */
587#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT 0x00000100 /* CBR expired counter limit enable */
588#define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */
589#define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 /* Reset CBR expired counter */
590#define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 /* DCU frame early termination request control */
591#define AR_Q_MISC_QCU_COMP_EN 0x00001000 /* QCU frame compression enable */
592#define AR_Q_MISC_RESV0 0xFFFFF000 /* Reserved */
593
594#define AR_Q_STS_PEND_FR_CNT 0x00000003 /* Mask for Pending Frame Count */
595#define AR_Q_STS_RESV0 0x000000FC /* Reserved */
596#define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 /* Mask for CBR expired counter */
597#define AR_Q_STS_RESV1 0xFFFF0000 /* Reserved */
598
599/* DCU registers */
600#define AR_NUM_DCU 10 /* Only use 10 DCU's for forward QCU/DCU compatibility */
601#define AR_DCU_0 0x0001
602#define AR_DCU_1 0x0002
603#define AR_DCU_2 0x0004
604#define AR_DCU_3 0x0008
605#define AR_DCU_4 0x0010
606#define AR_DCU_5 0x0020
607#define AR_DCU_6 0x0040
608#define AR_DCU_7 0x0080
609#define AR_DCU_8 0x0100
610#define AR_DCU_9 0x0200
611
612#define AR_D_QCUMASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */
613#define AR_D_QCUMASK_RESV0 0xFFFFFC00 /* Reserved */
614
615#define AR_D_LCL_IFS_CWMIN 0x000003FF /* Mask for CW_MIN */
616#define AR_D_LCL_IFS_CWMIN_S 0
617#define AR_D_LCL_IFS_CWMAX 0x000FFC00 /* Mask for CW_MAX */
618#define AR_D_LCL_IFS_CWMAX_S 10
619#define AR_D_LCL_IFS_AIFS 0x0FF00000 /* Mask for AIFS */
620#define AR_D_LCL_IFS_AIFS_S 20
621/*
622 * Note: even though this field is 8 bits wide the
623 * maximum supported AIFS value is 0xfc. Setting the AIFS value
624 * to 0xfd 0xfe, or 0xff will not work correctly and will cause
625 * the DCU to hang.
626 */
627#define AR_D_LCL_IFS_RESV0 0xF0000000 /* Reserved */
628
629#define AR_D_RETRY_LIMIT_FR_SH 0x0000000F /* frame short retry limit */
630#define AR_D_RETRY_LIMIT_FR_SH_S 0
631#define AR_D_RETRY_LIMIT_FR_LG 0x000000F0 /* frame long retry limit */
632#define AR_D_RETRY_LIMIT_FR_LG_S 4
633#define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 /* station short retry limit */
634#define AR_D_RETRY_LIMIT_STA_SH_S 8
635#define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 /* station short retry limit */
636#define AR_D_RETRY_LIMIT_STA_LG_S 14
637#define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 /* Reserved */
638
639#define AR_D_CHNTIME_DUR 0x000FFFFF /* ChannelTime duration (us) */
640#define AR_D_CHNTIME_DUR_S 0 /* Shift for ChannelTime duration */
641#define AR_D_CHNTIME_EN 0x00100000 /* ChannelTime enable */
642#define AR_D_CHNTIME_RESV0 0xFFE00000 /* Reserved */
643
644#define AR_D_MISC_BKOFF_THRESH 0x0000003F /* Backoff threshold */
645#define AR_D_MISC_ETS_RTS 0x00000040 /* End of transmission series
646 station RTS/data failure
647 count reset policy */
648#define AR_D_MISC_ETS_CW 0x00000080 /* End of transmission series
649 CW reset policy */
650#define AR_D_MISC_FRAG_WAIT_EN 0x00000100 /* Wait for next fragment */
651#define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 /* Backoff during a frag burst */
652#define AR_D_MISC_HCF_POLL_EN 0x00000800 /* HFC poll enable */
653#define AR_D_MISC_BKOFF_PERSISTENCE 0x00001000 /* Backoff persistence factor
654 setting */
655#define AR_D_MISC_FR_PREFETCH_EN 0x00002000 /* Frame prefetch enable */
656#define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 /* Mask for Virtual collision
657 handling policy */
658#define AR_D_MISC_VIR_COL_HANDLING_S 14
659/* FOO redefined for venice CW increment policy */
660#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 /* Normal */
661#define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 /* Ignore */
662#define AR_D_MISC_BEACON_USE 0x00010000 /* Beacon use indication */
663#define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 /* DCU arbiter lockout ctl */
664#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 /* DCU arbiter lockout ctl */
665#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 /* No lockout */
666#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame */
667#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 /* Global */
668#define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 /* DCU arbiter lockout ignore control */
669#define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Sequence number increment disable */
670#define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Post-frame backoff disable */
671#define AR_D_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual coll. handling policy */
672#define AR_D_MISC_BLOWN_IFS_POLICY 0x00800000 /* Blown IFS handling policy */
673#define AR_D_MISC_RESV0 0xFE000000 /* Reserved */
674
675#define AR_D_SEQNUM_RESV0 0xFFFFF000 /* Reserved */
676
677#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 /* LFSR slice select */
678#define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode indication */
679#define AR_D_GBL_IFS_MISC_SIFS_DURATION_USEC 0x000003F0 /* SIFS duration (us) */
680#define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 /* microsecond duration */
681#define AR_D_GBL_IFS_MISC_USEC_DURATION_S 10
682#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 /* DCU arbiter delay */
683#define AR_D_GBL_IFS_MISC_RESV0 0xFFC00000 /* Reserved */
684
685/* DMA & PCI Registers in PCI space (usable during sleep) */
686#define AR_RC_MAC 0x00000001 /* MAC reset */
687#define AR_RC_BB 0x00000002 /* Baseband reset */
688#define AR_RC_RESV0 0x00000004 /* Reserved */
689#define AR_RC_RESV1 0x00000008 /* Reserved */
690#define AR_RC_PCI 0x00000010 /* PCI-core reset */
691
692#define AR_SCR_SLDUR 0x0000ffff /* sleep duration, units of 128us */
693#define AR_SCR_SLDUR_S 0
694#define AR_SCR_SLE 0x00030000 /* sleep enable */
695#define AR_SCR_SLE_S 16
696#define AR_SCR_SLE_WAKE 0 /* force wake */
697#define AR_SCR_SLE_SLP 1 /* force sleep */
698#define AR_SCR_SLE_NORM 2 /* sleep logic normal operation */
699#define AR_SCR_SLDTP 0x00040000 /* sleep duration timing policy */
700#define AR_SCR_SLDWP 0x00080000 /* sleep duration write policy */
701#define AR_SCR_SLEPOL 0x00100000 /* sleep policy mode */
702#define AR_SCR_MIBIE 0x00200000 /* sleep perf cntrs MIB intr ena */
703#define AR_SCR_UNKNOWN 0x00400000
704
705#define AR_INTPEND_TRUE 0x00000001 /* interrupt pending */
706
707#define AR_SFR_SLEEP 0x00000001 /* force sleep */
708
709#define AR_PCICFG_SCLK_SEL 0x00000002 /* sleep clock select */
710#define AR_PCICFG_SCLK_SEL_S 1
711#define AR_PCICFG_CLKRUNEN 0x00000004 /* enable PCI CLKRUN function */
712#define AR_PCICFG_EEPROM_SIZE 0x00000018 /* Mask for EEPROM size */
713#define AR_PCICFG_EEPROM_SIZE_4 0 /* EEPROM size 4 Kbit */
714#define AR_PCICFG_EEPROM_SIZE_8K 1 /* EEPROM size 8 Kbit */
715#define AR_PCICFG_EEPROM_SIZE_16K 2 /* EEPROM size 16 Kbit */
716#define AR_PCICFG_EEPROM_SIZE_FAILED 3 /* Failure */
717#define AR_PCICFG_EEPROM_SIZE_S 3
718#define AR_PCICFG_LEDCTL 0x00000060 /* LED control Status */
719#define AR_PCICFG_LEDCTL_NONE 0 /* STA is not associated or trying */
720#define AR_PCICFG_LEDCTL_PEND 1 /* STA is trying to associate */
721#define AR_PCICFG_LEDCTL_ASSOC 2 /* STA is associated */
722#define AR_PCICFG_LEDCTL_S 5
723#define AR_PCICFG_PCI_BUS_SEL 0x00000380 /* PCI observation bus mux select */
724#define AR_PCICFG_DIS_CBE_FIX 0x00000400 /* Disable fix for bad PCI CBE# generation */
725#define AR_PCICFG_SL_INTEN 0x00000800 /* enable interrupt line assertion when asleep */
726#define AR_PCICFG_RETRYFIXEN 0x00001000 /* Enable PCI core retry fix */
727#define AR_PCICFG_SL_INPEN 0x00002000 /* Force asleep when an interrupt is pending */
728#define AR_PCICFG_RESV1 0x0000C000 /* Reserved */
729#define AR_PCICFG_SPWR_DN 0x00010000 /* mask for sleep/awake indication */
730#define AR_PCICFG_LEDMODE 0x000E0000 /* LED mode */
731#define AR_PCICFG_LEDMODE_PROP 0 /* Blink prop to filtered tx/rx */
732#define AR_PCICFG_LEDMODE_RPROP 1 /* Blink prop to unfiltered tx/rx */
733#define AR_PCICFG_LEDMODE_SPLIT 2 /* Blink power for tx/net for rx */
734#define AR_PCICFG_LEDMODE_RAND 3 /* Blink randomly */
735/* NB: s/w led control present in Hainan 1.1 and above */
736#define AR_PCICFG_LEDMODE_OFF 4 /* s/w control + both led's off */
737#define AR_PCICFG_LEDMODE_POWON 5 /* s/w control + power led on */
738#define AR_PCICFG_LEDMODE_NETON 6 /* s/w control + network led on */
739#define AR_PCICFG_LEDMODE_S 17
740#define AR_PCICFG_LEDBLINK 0x00700000 /* LED blink threshold select */
741#define AR_PCICFG_LEDBLINK_S 20
742#define AR_PCICFG_LEDSLOW 0x00800000 /* LED slowest blink rate mode */
743#define AR_PCICFG_LEDSLOW_S 23
744#define AR_PCICFG_SCLK_RATE_IND 0x03000000 /* Sleep clock rate */
745#define AR_PCICFG_SCLK_RATE_IND_S 24
746#define AR_PCICFG_RESV2 0xFC000000 /* Reserved */
747
748#define AR_GPIOCR_CR_SHIFT 2 /* Each CR is 2 bits */
749#define AR_GPIOCR_CR_N(_g) (0 << (AR_GPIOCR_CR_SHIFT * (_g)))
750#define AR_GPIOCR_CR_0(_g) (1 << (AR_GPIOCR_CR_SHIFT * (_g)))
751#define AR_GPIOCR_CR_1(_g) (2 << (AR_GPIOCR_CR_SHIFT * (_g)))
752#define AR_GPIOCR_CR_A(_g) (3 << (AR_GPIOCR_CR_SHIFT * (_g)))
753#define AR_GPIOCR_INT_SHIFT 12 /* Interrupt select field shifter */
754#define AR_GPIOCR_INT(_g) ((_g) << AR_GPIOCR_INT_SHIFT)
755#define AR_GPIOCR_INT_MASK 0x00007000 /* Interrupt select field mask */
756#define AR_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO Interrupt */
757#define AR_GPIOCR_INT_SELL 0x00000000 /* Generate int if pin is low */
758#define AR_GPIOCR_INT_SELH 0x00010000 /* Generate int if pin is high */
759#define AR_GPIOCR_INT_SEL AR_GPIOCR_INT_SELH
760
761#define AR_SREV_ID 0x000000FF /* Mask to read SREV info */
762#define AR_SREV_ID_S 4 /* Mask to shift Major Rev Info */
763#define AR_SREV_REVISION 0x0000000F /* Mask for Chip revision level */
764#define AR_SREV_REVISION_MIN 0 /* lowest revision level */
765#define AR_SREV_REVISION_MAX 0xF /* highest revision level */
766#define AR_SREV_FPGA 1
767#define AR_SREV_D2PLUS 2
768#define AR_SREV_D2PLUS_MS 3 /* metal spin */
769#define AR_SREV_CRETE 4
770#define AR_SREV_CRETE_MS 5 /* FCS metal spin */
771#define AR_SREV_CRETE_MS23 7 /* 2.3 metal spin (6 skipped) */
772#define AR_SREV_CRETE_23 8 /* 2.3 full tape out */
773#define AR_SREV_GRIFFIN_LITE 8
774#define AR_SREV_HAINAN 9
775#define AR_SREV_CONDOR 11
776#define AR_SREV_VERSION 0x000000F0 /* Mask for Chip version */
777#define AR_SREV_VERSION_CRETE 0
778#define AR_SREV_VERSION_MAUI_1 1
779#define AR_SREV_VERSION_MAUI_2 2
780#define AR_SREV_VERSION_SPIRIT 3
781#define AR_SREV_VERSION_OAHU 4
782#define AR_SREV_VERSION_VENICE 5
783#define AR_SREV_VERSION_GRIFFIN 7
784#define AR_SREV_VERSION_CONDOR 9
785#define AR_SREV_VERSION_EAGLE 10
786#define AR_SREV_VERSION_COBRA 11
787#define AR_SREV_2413 AR_SREV_VERSION_GRIFFIN
788#define AR_SREV_5413 AR_SREV_VERSION_EAGLE
789#define AR_SREV_2415 AR_SREV_VERSION_COBRA
790#define AR_SREV_5424 AR_SREV_VERSION_CONDOR
791#define AR_SREV_2425 14 /* SWAN */
792#define AR_SREV_2417 15 /* Nala */
793#define AR_SREV_OAHU_ES 0 /* Engineering Sample */
794#define AR_SREV_OAHU_PROD 2 /* Production */
795
796#define AR_PHYREV_HAINAN 0x43
797#define AR_ANALOG5REV_HAINAN 0x46
798
799#define AR_RADIO_SREV_MAJOR 0xF0
800#define AR_RADIO_SREV_MINOR 0x0F
801#define AR_RAD5111_SREV_MAJOR 0x10 /* All current supported ar5211 5 GHz
802 radios are rev 0x10 */
803#define AR_RAD5111_SREV_PROD 0x15 /* Current production level radios */
804#define AR_RAD2111_SREV_MAJOR 0x20 /* All current supported ar5211 2 GHz
805 radios are rev 0x10 */
806#define AR_RAD5112_SREV_MAJOR 0x30 /* 5112 Major Rev */
807#define AR_RAD5112_SREV_2_0 0x35 /* AR5112 Revision 2.0 */
808#define AR_RAD5112_SREV_2_1 0x36 /* AR5112 Revision 2.1 */
809#define AR_RAD2112_SREV_MAJOR 0x40 /* 2112 Major Rev */
810#define AR_RAD2112_SREV_2_0 0x45 /* AR2112 Revision 2.0 */
811#define AR_RAD2112_SREV_2_1 0x46 /* AR2112 Revision 2.1 */
812#define AR_RAD2413_SREV_MAJOR 0x50 /* 2413 Major Rev */
813#define AR_RAD5413_SREV_MAJOR 0x60 /* 5413 Major Rev */
814#define AR_RAD2316_SREV_MAJOR 0x70 /* 2316 Major Rev */
815#define AR_RAD2317_SREV_MAJOR 0x80 /* 2317 Major Rev */
816#define AR_RAD5424_SREV_MAJOR 0xa0 /* Mostly same as 5413 Major Rev */
817
818#define AR_PCIE_PMC_ENA_L1 0x01 /* enable PCIe core enter L1 when
819 d2_sleep_en is asserted */
820#define AR_PCIE_PMC_ENA_RESET 0x08 /* enable reset on link going down */
821
822/* EEPROM Registers in the MAC */
823#define AR_EEPROM_CMD_READ 0x00000001
824#define AR_EEPROM_CMD_WRITE 0x00000002
825#define AR_EEPROM_CMD_RESET 0x00000004
826
827#define AR_EEPROM_STS_READ_ERROR 0x00000001
828#define AR_EEPROM_STS_READ_COMPLETE 0x00000002
829#define AR_EEPROM_STS_WRITE_ERROR 0x00000004
830#define AR_EEPROM_STS_WRITE_COMPLETE 0x00000008
831
832#define AR_EEPROM_CFG_SIZE 0x00000003 /* size determination override */
833#define AR_EEPROM_CFG_SIZE_AUTO 0
834#define AR_EEPROM_CFG_SIZE_4KBIT 1
835#define AR_EEPROM_CFG_SIZE_8KBIT 2
836#define AR_EEPROM_CFG_SIZE_16KBIT 3
837#define AR_EEPROM_CFG_DIS_WWRCL 0x00000004 /* Disable wait for write completion */
838#define AR_EEPROM_CFG_CLOCK 0x00000018 /* clock rate control */
839#define AR_EEPROM_CFG_CLOCK_S 3 /* clock rate control */
840#define AR_EEPROM_CFG_CLOCK_156KHZ 0
841#define AR_EEPROM_CFG_CLOCK_312KHZ 1
842#define AR_EEPROM_CFG_CLOCK_625KHZ 2
843#define AR_EEPROM_CFG_RESV0 0x000000E0 /* Reserved */
844#define AR_EEPROM_CFG_PKEY 0x00FFFF00 /* protection key */
845#define AR_EEPROM_CFG_PKEY_S 8
846#define AR_EEPROM_CFG_EN_L 0x01000000 /* EPRM_EN_L setting */
847
848/* MAC PCU Registers */
849
850#define AR_STA_ID1_SADH_MASK 0x0000FFFF /* upper 16 bits of MAC addr */
851#define AR_STA_ID1_STA_AP 0x00010000 /* Device is AP */
852#define AR_STA_ID1_ADHOC 0x00020000 /* Device is ad-hoc */
853#define AR_STA_ID1_PWR_SAV 0x00040000 /* Power save reporting in
854 self-generated frames */
855#define AR_STA_ID1_KSRCHDIS 0x00080000 /* Key search disable */
856#define AR_STA_ID1_PCF 0x00100000 /* Observe PCF */
857#define AR_STA_ID1_USE_DEFANT 0x00200000 /* Use default antenna */
858#define AR_STA_ID1_UPD_DEFANT 0x00400000 /* Update default antenna w/
859 TX antenna */
860#define AR_STA_ID1_RTS_USE_DEF 0x00800000 /* Use default antenna to send RTS */
861#define AR_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mb/s rate for ACK & CTS */
862#define AR_STA_ID1_BASE_RATE_11B 0x02000000/* Use 11b base rate for ACK & CTS */
863#define AR_STA_ID1_USE_DA_SG 0x04000000 /* Use default antenna for
864 self-generated frames */
865#define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 /* Enable Michael */
866#define AR_STA_ID1_KSRCH_MODE 0x10000000 /* Look-up key when keyID != 0 */
867#define AR_STA_ID1_PRE_SEQNUM 0x20000000 /* Preserve s/w sequence number */
868#define AR_STA_ID1_CBCIV_ENDIAN 0x40000000
869#define AR_STA_ID1_MCAST_KSRCH 0x80000000 /* Do keycache search for mcast */
870
871#define AR_BSS_ID1_U16 0x0000FFFF /* Upper 16 bits of BSSID */
872#define AR_BSS_ID1_AID 0xFFFF0000 /* Association ID */
873#define AR_BSS_ID1_AID_S 16
874
875#define AR_SLOT_TIME_MASK 0x000007FF /* Slot time mask */
876
877#define AR_TIME_OUT_ACK 0x00003FFF /* ACK time-out */
878#define AR_TIME_OUT_ACK_S 0
879#define AR_TIME_OUT_CTS 0x3FFF0000 /* CTS time-out */
880#define AR_TIME_OUT_CTS_S 16
881
882#define AR_RSSI_THR_MASK 0x000000FF /* Beacon RSSI warning threshold */
883#define AR_RSSI_THR_BM_THR 0x0000FF00 /* Missed beacon threshold */
884#define AR_RSSI_THR_BM_THR_S 8
885
886#define AR_USEC_USEC 0x0000007F /* clock cycles in 1 usec */
887#define AR_USEC_USEC_S 0
888#define AR_USEC_USEC32 0x00003F80 /* 32MHz clock cycles in 1 usec */
889#define AR_USEC_USEC32_S 7
890
891#define AR5212_USEC_TX_LAT_M 0x007FC000 /* Tx latency */
892#define AR5212_USEC_TX_LAT_S 14
893#define AR5212_USEC_RX_LAT_M 0x1F800000 /* Rx latency */
894#define AR5212_USEC_RX_LAT_S 23
895
896#define AR_BEACON_PERIOD 0x0000FFFF /* Beacon period mask in TU/msec */
897#define AR_BEACON_PERIOD_S 0
898#define AR_BEACON_TIM 0x007F0000 /* byte offset of TIM start */
899#define AR_BEACON_TIM_S 16
900#define AR_BEACON_EN 0x00800000 /* Beacon enable */
901#define AR_BEACON_RESET_TSF 0x01000000 /* Clear TSF to 0 */
902
903#define AR_RX_NONE 0x00000000 /* Disallow all frames */
904#define AR_RX_UCAST 0x00000001 /* Allow unicast frames */
905#define AR_RX_MCAST 0x00000002 /* Allow multicast frames */
906#define AR_RX_BCAST 0x00000004 /* Allow broadcast frames */
907#define AR_RX_CONTROL 0x00000008 /* Allow control frames */
908#define AR_RX_BEACON 0x00000010 /* Allow beacon frames */
909#define AR_RX_PROM 0x00000020 /* Promiscuous mode, all packets */
910#define AR_RX_PROBE_REQ 0x00000080 /* Allow probe request frames */
911
912#define AR_DIAG_CACHE_ACK 0x00000001 /* No ACK if no valid key found */
913#define AR_DIAG_ACK_DIS 0x00000002 /* Disable ACK generation */
914#define AR_DIAG_CTS_DIS 0x00000004 /* Disable CTS generation */
915#define AR_DIAG_ENCRYPT_DIS 0x00000008 /* Disable encryption */
916#define AR_DIAG_DECRYPT_DIS 0x00000010 /* Disable decryption */
917#define AR_DIAG_RX_DIS 0x00000020 /* Disable receive */
918#define AR_DIAG_CORR_FCS 0x00000080 /* Corrupt FCS */
919#define AR_DIAG_CHAN_INFO 0x00000100 /* Dump channel info */
920#define AR_DIAG_EN_SCRAMSD 0x00000200 /* Enable fixed scrambler seed */
921#define AR_DIAG_SCRAM_SEED 0x0001FC00 /* Fixed scrambler seed */
922#define AR_DIAG_SCRAM_SEED_S 10
923#define AR_DIAG_FRAME_NV0 0x00020000 /* Accept frames of non-zero
924 protocol version */
925#define AR_DIAG_OBS_PT_SEL 0x000C0000 /* Observation point select */
926#define AR_DIAG_OBS_PT_SEL_S 18
927#define AR_DIAG_RX_CLR_HI 0x00100000 /* Force rx_clear high */
928#define AR_DIAG_IGNORE_CS 0x00200000 /* Force virtual carrier sense */
929#define AR_DIAG_CHAN_IDLE 0x00400000 /* Force channel idle high */
930#define AR_DIAG_PHEAR_ME 0x00800000 /* Uses framed and wait_wep in the pherr_enable_eifs if set to 0 */
931
932#define AR_SLEEP1_NEXT_DTIM 0x0007ffff /* Abs. time(1/8TU) for next DTIM */
933#define AR_SLEEP1_NEXT_DTIM_S 0
934#define AR_SLEEP1_ASSUME_DTIM 0x00080000 /* Assume DTIM present on missent beacon */
935#define AR_SLEEP1_ENH_SLEEP_ENA 0x00100000 /* Enable enhanced sleep logic */
936#define AR_SLEEP1_CAB_TIMEOUT 0xff000000 /* CAB timeout(TU) */
937#define AR_SLEEP1_CAB_TIMEOUT_S 24
938
939#define AR_SLEEP2_NEXT_TIM 0x0007ffff /* Abs. time(1/8TU) for next DTIM */
940#define AR_SLEEP2_NEXT_TIM_S 0
941#define AR_SLEEP2_BEACON_TIMEOUT 0xff000000 /* Beacon timeout(TU) */
942#define AR_SLEEP2_BEACON_TIMEOUT_S 24
943
944#define AR_SLEEP3_TIM_PERIOD 0x0000ffff /* Tim/Beacon period (TU) */
945#define AR_SLEEP3_TIM_PERIOD_S 0
946#define AR_SLEEP3_DTIM_PERIOD 0xffff0000 /* DTIM period (TU) */
947#define AR_SLEEP3_DTIM_PERIOD_S 16
948
949#define AR_TPC_ACK 0x0000003f /* ack frames */
950#define AR_TPC_ACK_S 0
951#define AR_TPC_CTS 0x00003f00 /* cts frames */
952#define AR_TPC_CTS_S 8
953#define AR_TPC_CHIRP 0x003f0000 /* chirp frames */
954#define AR_TPC_CHIRP_S 16
955#define AR_TPC_DOPPLER 0x0f000000 /* doppler chirp span */
956#define AR_TPC_DOPPLER_S 24
957
958#define AR_PHY_ERR_RADAR 0x00000020 /* Radar signal */
959#define AR_PHY_ERR_OFDM_TIMING 0x00020000 /* False detect for OFDM */
960#define AR_PHY_ERR_CCK_TIMING 0x02000000 /* False detect for CCK */
961
962#define AR_TSF_PARM_INCREMENT 0x000000ff
963#define AR_TSF_PARM_INCREMENT_S 0
964
965#define AR_NOACK_2BIT_VALUE 0x0000000f
966#define AR_NOACK_2BIT_VALUE_S 0
967#define AR_NOACK_BIT_OFFSET 0x00000070
968#define AR_NOACK_BIT_OFFSET_S 4
969#define AR_NOACK_BYTE_OFFSET 0x00000180
970#define AR_NOACK_BYTE_OFFSET_S 7
971
972#define AR_MISC_MODE_BSSID_MATCH_FORCE 0x1 /* Force BSSID match */
973#define AR_MISC_MODE_ACKSIFS_MEMORY 0x2 /* ACKSIFS use contents of Rate */
974#define AR_MISC_MODE_MIC_NEW_LOC_ENABLE 0x4 /* Xmit Michael Key same as Rcv */
975#define AR_MISC_MODE_TX_ADD_TSF 0x8 /* Beacon/Probe-Rsp timestamp add (not replace) */
976
977#define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) /* key bit 0-31 */
978#define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) /* key bit 32-47 */
979#define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) /* key bit 48-79 */
980#define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) /* key bit 80-95 */
981#define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) /* key bit 96-127 */
982#define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20) /* key type */
983#define AR_KEYTABLE_TYPE_40 0x00000000 /* WEP 40 bit key */
984#define AR_KEYTABLE_TYPE_104 0x00000001 /* WEP 104 bit key */
985#define AR_KEYTABLE_TYPE_128 0x00000003 /* WEP 128 bit key */
986#define AR_KEYTABLE_TYPE_TKIP 0x00000004 /* TKIP and Michael */
987#define AR_KEYTABLE_TYPE_AES 0x00000005 /* AES/OCB 128 bit key */
988#define AR_KEYTABLE_TYPE_CCM 0x00000006 /* AES/CCM 128 bit key */
989#define AR_KEYTABLE_TYPE_CLR 0x00000007 /* no encryption */
990#define AR_KEYTABLE_ANT 0x00000008 /* previous transmit antenna */
991#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) /* MAC address 1-32 */
992#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) /* MAC address 33-47 */
993#define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */
994
995/* Compress settings */
996#define AR_CCFG_WIN_M 0x00000007 /* mask for AR_CCFG_WIN size */
997#define AR_CCFG_MIB_INT_EN 0x00000008 /* compression performance MIB counter int enable */
998#define AR_CCUCFG_RESET_VAL 0x00100200 /* the should be reset value */
999#define AR_CCUCFG_CATCHUP_EN 0x00000001 /* Compression catchup enable */
1000#define AR_DCM_D_EN 0x00000001 /* all direct frames to be decompressed */
1001#define AR_COMPRESSION_WINDOW_SIZE 4096 /* default comp. window size */
1002
1003#endif /* _DEV_AR5212REG_H_ */
1004