1 | /* $NetBSD: eapreg.h,v 1.13 2008/04/28 20:23:54 martin Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Lennart Augustsson <augustss@NetBSD.org> and Charles M. Hannum. |
9 | * |
10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions |
12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. |
15 | * 2. Redistributions in binary form must reproduce the above copyright |
16 | * notice, this list of conditions and the following disclaimer in the |
17 | * documentation and/or other materials provided with the distribution. |
18 | * |
19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
29 | * POSSIBILITY OF SUCH DAMAGE. |
30 | */ |
31 | |
32 | /* |
33 | * ES1370/ES1371/ES1373 registers |
34 | */ |
35 | |
36 | #define EAP_ICSC 0x00 /* interrupt / chip select control */ |
37 | |
38 | #define EAP_SERR_DISABLE 0x00000001 /* do not present SERR on PCI bus */ |
39 | #define E1371_PCICLKDIS 0x00000001 /* PCIclk to essential modules only*/ |
40 | |
41 | #define EAP_CDC_EN 0x00000002 /* enable codec i/f */ |
42 | #define E1371_XTALCKDIS 0x00000002 /* gate xtal clk to all modules */ |
43 | |
44 | #define EAP_JYSTK_EN 0x00000004 |
45 | #define EAP_UART_EN 0x00000008 |
46 | #define EAP_ADC_EN 0x00000010 |
47 | #define EAP_DAC2_EN 0x00000020 /* intended as CODEC DAC */ |
48 | #define EAP_DAC1_EN 0x00000040 /* intended as CODEC FM DAC */ |
49 | #define EAP_BREQ 0x00000080 |
50 | |
51 | #define EAP_XCTL0 0x00000100 /* a gp out pin on 1370 */ |
52 | #define EAP_M_CB 0x00000200 /* rec src mpeg (!adc) */ |
53 | #define E1371_PDLEV(n) ((n)<<8) /* pwr dwn lvl D0 - D3 */ |
54 | #define E1371_PDLEVBITS 0x00000300 |
55 | |
56 | #define EAP_CCB_INTRM 0x00000400 /* enable CCB module voice intrs */ |
57 | |
58 | #define EAP_DAC_SYNC 0x00000800 |
59 | #define E1371_M_CB 0x00000800 /* rec src i2s (!adc); cf EAP_M_CB!*/ |
60 | |
61 | #define EAP_WTSRSEL 0x00003000 |
62 | #define EAP_WTSRSEL_5 0x00000000 |
63 | #define EAP_WTSRSEL_11 0x00001000 |
64 | #define EAP_WTSRSEL_22 0x00002000 |
65 | #define EAP_WTSRSEL_44 0x00003000 |
66 | #define E1371_PWR_INTRM 0x00001000 /* ena intr on pwr lvl change */ |
67 | #define E1371_ADC_STOP 0x00002000 /* cf EAP_ADC_STOP! */ |
68 | |
69 | #define EAP_M_SBB 0x00004000 |
70 | #define E1371_SYNC_RES 0x00004000 |
71 | |
72 | #define EAP_MSFMTSEL 0x00008000 |
73 | |
74 | #define EAP_DAC_EN(i) (EAP_DAC2_EN << (i)) /* yes, it's twisted */ |
75 | |
76 | #define EAP_SET_PCLKDIV(n) (((n)&0x1fff)<<16) |
77 | #define EAP_GET_PCLKDIV(n) (((n)>>16)&0x1fff) |
78 | #define EAP_PCLKBITS 0x1fff0000 |
79 | #define E1371_OUT_GPIO(n) (((n)&0xf)<<16) |
80 | #define E1371_IN_GPIO(n) (((n)>>20)&0xf) |
81 | #define E1371_OUTGPIOBITS 0x000f0000 |
82 | #define E1371_INGPIOBITS 0x00f00000 |
83 | #define E1371_JOY_ASEL(n) (((n)&3)<<24) |
84 | #define E1371_JOY_ASELBITS 0x03000000 |
85 | #define E1373_SPDIFEN_B 0x04000000 /* spdif generated (!spdif thru) */ |
86 | #define E1373_RECEN_B 0x08000000 /* !(rec monitor to spdif out) */ |
87 | #define E1373_TEST_BIT 0x10000000 /* 0 except to test block preamble */ |
88 | #define E1373_BYPASS_R 0x20000000 /* rec bypass rate converter */ |
89 | #define EAP_XCTL1 0x40000000 /* a gp out pin on 1370 */ |
90 | #define E1373_BYPASS_P2 0x40000000 /* play2 bypass rate converter */ |
91 | #define EAP_ADC_STOP 0x80000000 |
92 | #define E1373_BYPASS_P1 0x80000000 /* play1 bypass rate converter */ |
93 | |
94 | #define EAP_ICSS 0x04 /* interrupt / chip select status */ |
95 | /* on the 5880 control / status */ |
96 | #define EAP_I_ADC 0x00000001 |
97 | #define EAP_I_DAC2 0x00000002 |
98 | #define EAP_I_DAC1 0x00000004 |
99 | #define EAP_I_UART 0x00000008 |
100 | #define EAP_I_MCCB 0x00000010 |
101 | #define EAP_VC 0x00000060 |
102 | |
103 | #define EAP_CWRIP 0x00000100 |
104 | #define E1371_SYNC_ERR 0x00000100 |
105 | |
106 | #define EAP_CBUSY 0x00000200 /* tied 1 on 1371, 1373 */ |
107 | #define EAP_CSTAT 0x00000400 /* tied 1 on 1371, 1373 */ |
108 | #define E1373_GPIO_INT(n) (((n)>>12)&0xf) /* which gpios interrupted */ |
109 | #define E1373_TEST_MODE 0x00010000 |
110 | #define E1373_TEST_SPDIF 0x00020000 |
111 | #define E1373_ENABLE_SPDIF 0x00040000 |
112 | #define E1373_GPIO_INTEN(n) (((n)&0xf)<<20) |
113 | #define EAP_CT5880_AC97_RESET 0x20000000 |
114 | #define EAP_INTR 0x80000000 |
115 | |
116 | #define EAP_UART_DATA 0x08 |
117 | #define EAP_UART_STATUS 0x09 |
118 | #define EAP_US_RXRDY 0x01 |
119 | #define EAP_US_TXRDY 0x02 |
120 | #define EAP_US_TXINT 0x04 |
121 | #define EAP_US_RXINT 0x80 |
122 | #define EAP_UART_CONTROL 0x09 |
123 | #define EAP_UC_CNTRL 0x03 |
124 | #define EAP_UC_TXINTEN 0x20 |
125 | #define EAP_UC_TXINTENBITS 0x60 |
126 | #define EAP_UC_RXINTEN 0x80 |
127 | #define EAP_UART_RESERVED 0x0a |
128 | #define EAP_UR_TEST_MODE 0x01 |
129 | #define EAP_MEMPAGE 0x0c |
130 | #define EAP_CODEC 0x10 |
131 | #define EAP_SET_CODEC(a,d) (((a)<<8) | (d)) |
132 | |
133 | /* |
134 | * ES1371/ES1373 registers |
135 | */ |
136 | |
137 | #define E1371_CODEC 0x14 |
138 | #define E1371_CODEC_VALID 0x80000000 |
139 | #define E1371_CODEC_WIP 0x40000000 |
140 | #define E1371_CODEC_READ 0x00800000 |
141 | #define E1371_SET_CODEC(a,d) (((a)<<16) | (d)) |
142 | |
143 | #define E1371_SRC 0x10 |
144 | #define E1371_SRC_RAMWE 0x01000000 |
145 | #define E1371_SRC_RBUSY 0x00800000 |
146 | #define E1371_SRC_DISABLE 0x00400000 |
147 | #define E1371_SRC_DISP1 0x00200000 |
148 | #define E1371_SRC_DISP2 0x00100000 |
149 | #define E1371_SRC_DISREC 0x00080000 |
150 | #define E1371_SRC_DATAMASK 0x0000ffff |
151 | #define E1371_SRC_ADDR(a) ((a)<<25) |
152 | #define E1371_SRC_DATA(d) ((d) & E1371_SRC_DATAMASK) |
153 | #define E1371_SRC_CTLMASK (E1371_SRC_DISABLE | E1371_SRC_DISP1 | \ |
154 | E1371_SRC_DISP2 | E1371_SRC_DISREC) |
155 | #define E1371_SRC_STATE_MASK 0x00870000 |
156 | #define E1371_SRC_STATE_OK 0x00010000 |
157 | |
158 | #define E1371_LEGACY 0x18 |
159 | |
160 | /* |
161 | * ES1371/ES1373 sample rate converter registers |
162 | */ |
163 | |
164 | #define ESRC_ADC 0x78 |
165 | #define ESRC_DAC1 0x70 |
166 | #define ESRC_DAC2 0x74 |
167 | #define ESRC_ADC_VOLL 0x6c |
168 | #define ESRC_ADC_VOLR 0x6d |
169 | #define ESRC_DAC1_VOLL 0x7c |
170 | #define ESRC_DAC1_VOLR 0x7d |
171 | #define ESRC_DAC2_VOLL 0x7e |
172 | #define ESRC_DAC2_VOLR 0x7f |
173 | #define ESRC_TRUNC_N 0x00 |
174 | #define ESRC_IREGS 0x01 |
175 | #define ESRC_ACF 0x02 |
176 | #define ESRC_VFF 0x03 |
177 | #define ESRC_SET_TRUNC(n) ((n)<<9) |
178 | #define ESRC_SET_N(n) ((n)<<4) |
179 | #define ESRC_SMF 0x8000 |
180 | #define ESRC_SET_VFI(n) ((n)<<10) |
181 | #define ESRC_SET_ACI(n) (n) |
182 | #define ESRC_SET_ADC_VOL(n) ((n)<<8) |
183 | #define ESRC_SET_DAC_VOLI(n) ((n)<<12) |
184 | #define ESRC_SET_DAC_VOLF(n) (n) |
185 | #define SRC_MAGIC ((1<15)|(1<<13)|(1<<11)|(1<<9)) |
186 | |
187 | #define EAP_SIC 0x20 |
188 | #define EAP_P1_S_MB 0x00000001 |
189 | #define EAP_P1_S_EB 0x00000002 |
190 | #define EAP_P2_S_MB 0x00000004 |
191 | #define EAP_P2_S_EB 0x00000008 |
192 | #define EAP_R1_S_MB 0x00000010 |
193 | #define EAP_R1_S_EB 0x00000020 |
194 | #define EAP_P2_DAC_SEN 0x00000040 |
195 | #define EAP_P1_SCT_RLD 0x00000080 |
196 | #define EAP_P1_INTR_EN 0x00000100 |
197 | #define EAP_P2_INTR_EN 0x00000200 |
198 | #define EAP_R1_INTR_EN 0x00000400 |
199 | #define EAP_P1_PAUSE 0x00000800 |
200 | #define EAP_P2_PAUSE 0x00001000 |
201 | #define EAP_P1_LOOP_SEL 0x00002000 |
202 | #define EAP_P2_LOOP_SEL 0x00004000 |
203 | #define EAP_R1_LOOP_SEL 0x00008000 |
204 | #define EAP_S_EB(i) (EAP_P2_S_EB >> 2*(i)) |
205 | #define EAP_S_MB(i) (EAP_P2_S_MB >> 2*(i)) |
206 | #define EAP_P_INTR_EN(i) (EAP_P2_INTR_EN >> (i)) |
207 | #define EAP_SET_P2_ST_INC(i) ((i) << 16) |
208 | #define EAP_SET_P2_END_INC(i) ((i) << 19) |
209 | #define EAP_INC_BITS 0x003f0000 |
210 | |
211 | #define EAP_DAC1_CSR 0x24 |
212 | #define EAP_DAC2_CSR 0x28 |
213 | #define EAP_ADC_CSR 0x2c |
214 | #define EAP_GET_CURRSAMP(r) ((r) >> 16) |
215 | |
216 | #define EAP_DAC_PAGE 0xc |
217 | #define EAP_ADC_PAGE 0xd |
218 | #define EAP_UART_PAGE1 0xe |
219 | #define EAP_UART_PAGE2 0xf |
220 | |
221 | #define EAP_DAC1_ADDR 0x30 |
222 | #define EAP_DAC1_SIZE 0x34 |
223 | #define EAP_DAC2_ADDR 0x38 |
224 | #define EAP_DAC2_SIZE 0x3c |
225 | #define EAP_ADC_ADDR 0x30 |
226 | #define EAP_ADC_SIZE 0x34 |
227 | #define EAP_SET_SIZE(c,s) (((c)<<16) | (s)) |
228 | |
229 | #define EAP_READ_TIMEOUT 5000 |
230 | #define EAP_WRITE_TIMEOUT 5000 |
231 | |
232 | |
233 | #define EAP_XTAL_FREQ 1411200 /* 22.5792 / 16 MHz */ |
234 | |
235 | /* AK4531 registers */ |
236 | #define AK_MASTER_L 0x00 |
237 | #define AK_MASTER_R 0x01 |
238 | #define AK_VOICE_L 0x02 |
239 | #define AK_VOICE_R 0x03 |
240 | #define AK_FM_L 0x04 |
241 | #define AK_FM_R 0x05 |
242 | #define AK_CD_L 0x06 |
243 | #define AK_CD_R 0x07 |
244 | #define AK_LINE_L 0x08 |
245 | #define AK_LINE_R 0x09 |
246 | #define AK_AUX_L 0x0a |
247 | #define AK_AUX_R 0x0b |
248 | #define AK_MONO1 0x0c |
249 | #define AK_MONO2 0x0d |
250 | #define AK_MIC 0x0e |
251 | #define AK_MONO 0x0f |
252 | #define AK_OUT_MIXER1 0x10 |
253 | #define AK_M_FM_L 0x40 |
254 | #define AK_M_FM_R 0x20 |
255 | #define AK_M_LINE_L 0x10 |
256 | #define AK_M_LINE_R 0x08 |
257 | #define AK_M_CD_L 0x04 |
258 | #define AK_M_CD_R 0x02 |
259 | #define AK_M_MIC 0x01 |
260 | #define AK_OUT_MIXER2 0x11 |
261 | #define AK_M_AUX_L 0x20 |
262 | #define AK_M_AUX_R 0x10 |
263 | #define AK_M_VOICE_L 0x08 |
264 | #define AK_M_VOICE_R 0x04 |
265 | #define AK_M_MONO2 0x02 |
266 | #define AK_M_MONO1 0x01 |
267 | #define AK_IN_MIXER1_L 0x12 |
268 | #define AK_IN_MIXER1_R 0x13 |
269 | #define AK_IN_MIXER2_L 0x14 |
270 | #define AK_IN_MIXER2_R 0x15 |
271 | #define AK_M_TMIC 0x80 |
272 | #define AK_M_TMONO1 0x40 |
273 | #define AK_M_TMONO2 0x20 |
274 | #define AK_M2_AUX_L 0x10 |
275 | #define AK_M2_AUX_R 0x08 |
276 | #define AK_M_VOICE 0x04 |
277 | #define AK_M2_MONO2 0x02 |
278 | #define AK_M2_MONO1 0x01 |
279 | #define AK_RESET 0x16 |
280 | #define AK_PD 0x02 |
281 | #define AK_NRST 0x01 |
282 | #define AK_CS 0x17 |
283 | #define AK_ADSEL 0x18 |
284 | #define AK_MGAIN 0x19 |
285 | #define AK_NPORTS 0x20 |
286 | |
287 | /* Not sensical for AC97? */ |
288 | #define VOL_TO_ATT5(v) (0x1f - ((v) >> 3)) |
289 | #define VOL_TO_GAIN5(v) VOL_TO_ATT5(v) |
290 | #define ATT5_TO_VOL(v) ((0x1f - (v)) << 3) |
291 | #define GAIN5_TO_VOL(v) ATT5_TO_VOL(v) |
292 | #define VOL_0DB 200 |
293 | |
294 | /* Futzable parms */ |
295 | #define EAP_MASTER_VOL 0 |
296 | #define EAP_VOICE_VOL 1 |
297 | #define EAP_FM_VOL 2 |
298 | #define EAP_VIDEO_VOL 2 /* ES1371 */ |
299 | #define EAP_CD_VOL 3 |
300 | #define EAP_LINE_VOL 4 |
301 | #define EAP_AUX_VOL 5 |
302 | #define EAP_MIC_VOL 6 |
303 | #define EAP_RECORD_SOURCE 7 |
304 | #define EAP_INPUT_SOURCE 8 |
305 | #define EAP_MIC_PREAMP 9 |
306 | #define EAP_OUTPUT_CLASS 10 |
307 | #define EAP_RECORD_CLASS 11 |
308 | #define EAP_INPUT_CLASS 12 |
309 | |
310 | #define MIDI_BUSY_WAIT 100 |
311 | #define MIDI_BUSY_DELAY 100 /* Delay when UART is busy */ |
312 | |
313 | #define EAP_EV1938_A 0x00 |
314 | #define EAP_CT5880_C 0x02 |
315 | #define EAP_CT5880_D 0x03 |
316 | #define EAP_CT5880_E 0x04 |
317 | #define EAP_ES1373_A 0x04 |
318 | #define EAP_ES1373_B 0x06 |
319 | #define EAP_CT5880_A 0x07 |
320 | #define EAP_ES1373_8 0x08 |
321 | #define EAP_ES1371_B 0x09 |
322 | |