1 | /* $NetBSD: brgphyreg.h,v 1.9 2014/06/17 21:37:20 msaitoh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 2000 |
5 | * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * 3. All advertising materials mentioning features or use of this software |
16 | * must display the following acknowledgement: |
17 | * This product includes software developed by Bill Paul. |
18 | * 4. Neither the name of the author nor the names of any co-contributors |
19 | * may be used to endorse or promote products derived from this software |
20 | * without specific prior written permission. |
21 | * |
22 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
23 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
25 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
26 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
29 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
30 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
31 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
32 | * THE POSSIBILITY OF SUCH DAMAGE. |
33 | * |
34 | * FreeBSD: src/sys/dev/mii/brgphyreg.h,v 1.1 2000/04/22 01:58:17 wpaul Exp |
35 | */ |
36 | |
37 | #ifndef _DEV_MII_BRGPHYREG_H_ |
38 | #define _DEV_MII_BRGPHYREG_H_ |
39 | |
40 | /* |
41 | * Broadcom BCM5400 registers |
42 | */ |
43 | |
44 | #define BRGPHY_MII_1000CTL 0x09 /* 1000baseT control */ |
45 | #define BRGPHY_1000CTL_TST 0xE000 /* Test modes */ |
46 | #define BRGPHY_1000CTL_MSE 0x1000 /* Master/Slave enable */ |
47 | #define BRGPHY_1000CTL_MSC 0x0800 /* Master/Slave configuration */ |
48 | #define BRGPHY_1000CTL_RD 0x0400 /* Repeater/DTE */ |
49 | #define BRGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */ |
50 | #define BRGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */ |
51 | |
52 | #define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */ |
53 | #define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */ |
54 | #define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */ |
55 | #define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* Tx output disabled */ |
56 | #define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */ |
57 | #define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */ |
58 | #define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */ |
59 | #define BRGPHY_PHY_EXTCTL_BY_SCR 0x0200 /* Bypass scrambler */ |
60 | #define BRGPHY_PHY_EXTCTL_BY_MLT3 0x0100 /* Bypass MLT3 encoder */ |
61 | #define BRGPHY_PHY_EXTCTL_BY_RXA 0x0080 /* Bypass RX alignment */ |
62 | #define BRGPHY_PHY_EXTCTL_RES_SCR 0x0040 /* Reset scrambler */ |
63 | #define BRGPHY_PHY_EXTCTL_EN_LTR 0x0020 /* Enable LED traffic mode */ |
64 | #define BRGPHY_PHY_EXTCTL_LED_ON 0x0010 /* Force LEDs on */ |
65 | #define BRGPHY_PHY_EXTCTL_LED_OFF 0x0008 /* Force LEDs off */ |
66 | #define BRGPHY_PHY_EXTCTL_EX_IPG 0x0004 /* Extended TX IPG mode */ |
67 | #define BRGPHY_PHY_EXTCTL_3_LED 0x0002 /* Three link LED mode */ |
68 | #define BRGPHY_PHY_EXTCTL_HIGH_LA 0x0001 /* GMII Fifo Elasticy (?) */ |
69 | |
70 | #define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */ |
71 | #define BRGPHY_PHY_EXTSTS_CROSS_STAT 0x2000 /* MDI crossover status */ |
72 | #define BRGPHY_PHY_EXTSTS_INT_STAT 0x1000 /* Interrupt status */ |
73 | #define BRGPHY_PHY_EXTSTS_RRS 0x0800 /* Remote receiver status */ |
74 | #define BRGPHY_PHY_EXTSTS_LRS 0x0400 /* Local receiver status */ |
75 | #define BRGPHY_PHY_EXTSTS_LOCKED 0x0200 /* Locked */ |
76 | #define BRGPHY_PHY_EXTSTS_LS 0x0100 /* Link status */ |
77 | #define BRGPHY_PHY_EXTSTS_RF 0x0080 /* Remove fault */ |
78 | #define BRGPHY_PHY_EXTSTS_CE_ER 0x0040 /* Carrier ext error */ |
79 | #define BRGPHY_PHY_EXTSTS_BAD_SSD 0x0020 /* Bad SSD */ |
80 | #define BRGPHY_PHY_EXTSTS_BAD_ESD 0x0010 /* Bad ESS */ |
81 | #define BRGPHY_PHY_EXTSTS_RX_ER 0x0008 /* RX error */ |
82 | #define BRGPHY_PHY_EXTSTS_TX_ER 0x0004 /* TX error */ |
83 | #define BRGPHY_PHY_EXTSTS_LOCK_ER 0x0002 /* Lock error */ |
84 | #define BRGPHY_PHY_EXTSTS_MLT3_ER 0x0001 /* MLT3 code error */ |
85 | |
86 | #define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */ |
87 | |
88 | #define BRGPHY_MII_FCERRCNT 0x13 /* False carrier sense counter */ |
89 | #define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */ |
90 | |
91 | #define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */ |
92 | #define BRGPHY_RXNOCNT_LOCAL 0xFF00 /* Local RX not OK counter */ |
93 | #define BRGPHY_RXNOCNT_REMOTE 0x00FF /* Local RX not OK counter */ |
94 | |
95 | #define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */ |
96 | |
97 | #define BRGPHY_MII_EPHY_PTEST 0x17 /* 5906 PHY register */ |
98 | #define BRGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */ |
99 | |
100 | #define BRGPHY_DSP_TAP_NUMBER_MASK 0x00 |
101 | #define BRGPHY_DSP_AGC_A 0x00 |
102 | #define BRGPHY_DSP_AGC_B 0x01 |
103 | #define BRGPHY_DSP_MSE_PAIR_STATUS 0x02 |
104 | #define BRGPHY_DSP_SOFT_DECISION 0x03 |
105 | #define BRGPHY_DSP_PHASE_REG 0x04 |
106 | #define BRGPHY_DSP_SKEW 0x05 |
107 | #define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND 0x06 |
108 | #define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND 0x07 |
109 | #define BRGPHY_DSP_LAST_ECHO 0x08 |
110 | #define BRGPHY_DSP_FREQUENCY 0x09 |
111 | #define BRGPHY_DSP_PLL_BANDWIDTH 0x0A |
112 | #define BRGPHY_DSP_PLL_PHASE_OFFSET 0x0B |
113 | |
114 | #define BRGPHYDSP_FILTER_DCOFFSET 0x0C00 |
115 | #define BRGPHY_DSP_FILTER_FEXT3 0x0B00 |
116 | #define BRGPHY_DSP_FILTER_FEXT2 0x0A00 |
117 | #define BRGPHY_DSP_FILTER_FEXT1 0x0900 |
118 | #define BRGPHY_DSP_FILTER_FEXT0 0x0800 |
119 | #define BRGPHY_DSP_FILTER_NEXT3 0x0700 |
120 | #define BRGPHY_DSP_FILTER_NEXT2 0x0600 |
121 | #define BRGPHY_DSP_FILTER_NEXT1 0x0500 |
122 | #define BRGPHY_DSP_FILTER_NEXT0 0x0400 |
123 | #define BRGPHY_DSP_FILTER_ECHO 0x0300 |
124 | #define BRGPHY_DSP_FILTER_DFE 0x0200 |
125 | #define BRGPHY_DSP_FILTER_FFE 0x0100 |
126 | |
127 | #define BRGPHY_DSP_CONTROL_ALL_FILTERS 0x1000 |
128 | |
129 | #define BRGPHY_DSP_SEL_CH_0 0x0000 |
130 | #define BRGPHY_DSP_SEL_CH_1 0x2000 |
131 | #define BRGPHY_DSP_SEL_CH_2 0x4000 |
132 | #define BRGPHY_DSP_SEL_CH_3 0x6000 |
133 | |
134 | #define BRGPHY_MII_AUXCTL 0x18 /* AUX control */ |
135 | #define BRGPHY_AUXCTL_LOW_SQ 0x8000 /* Low squelch */ |
136 | #define BRGPHY_AUXCTL_LONG_PKT 0x4000 /* RX long packets */ |
137 | #define BRGPHY_AUXCTL_ER_CTL 0x3000 /* Edgerate control */ |
138 | #define BRGPHY_AUXCTL_TX_TST 0x0400 /* TX test, always 1 */ |
139 | #define BRGPHY_AUXCTL_DIS_PRF 0x0080 /* dis part resp filter */ |
140 | #define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */ |
141 | |
142 | #define BRGPHY_MII_AUXSTS 0x19 /* AUX status */ |
143 | #define BRGPHY_AUXSTS_ACOMP 0x8000 /* Autoneg complete */ |
144 | #define BRGPHY_AUXSTS_AN_ACK 0x4000 /* Autoneg complete ack */ |
145 | #define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* Autoneg complete ack detect */ |
146 | #define BRGPHY_AUXSTS_AN_NPW 0x1000 /* Autoneg next page wait */ |
147 | #define BRGPHY_AUXSTS_AN_RES 0x0700 /* Autoneg HCD */ |
148 | #define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */ |
149 | #define BRGPHY_AUXSTS_RF 0x0040 /* Remote fault */ |
150 | #define BRGPHY_AUXSTS_ANP_R 0x0020 /* Autoneg page received */ |
151 | #define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* LP AN ability */ |
152 | #define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* LP Next page ability */ |
153 | #define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */ |
154 | #define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */ |
155 | #define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */ |
156 | |
157 | #define BRGPHY_RES_1000FD 0x0700 /* 1000baseT full duplex */ |
158 | #define BRGPHY_RES_1000HD 0x0600 /* 1000baseT half duplex */ |
159 | #define BRGPHY_RES_100FD 0x0500 /* 100baseT full duplex */ |
160 | #define BRGPHY_RES_100T4 0x0400 /* 100baseT4 */ |
161 | #define BRGPHY_RES_100HD 0x0300 /* 100baseT half duplex */ |
162 | #define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */ |
163 | #define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */ |
164 | |
165 | #define BRGPHY_MII_ISR 0x1A /* Interrupt status */ |
166 | #define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */ |
167 | #define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */ |
168 | #define BRGPHY_ISR_HCT 0x1000 /* Counter above 32K */ |
169 | #define BRGPHY_ISR_LCT 0x0800 /* All counter below 128 */ |
170 | #define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */ |
171 | #define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */ |
172 | #define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */ |
173 | #define BRGPHY_ISR_USHDC 0x0080 /* Negotiated Unsupported HCD */ |
174 | #define BRGPHY_ISR_SCR_S_ERR 0x0040 /* Scrambler sync error */ |
175 | #define BRGPHY_ISR_RRS_CHG 0x0020 /* Remote RX status change */ |
176 | #define BRGPHY_ISR_LRS_CHG 0x0010 /* Local RX status change */ |
177 | #define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */ |
178 | #define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */ |
179 | #define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */ |
180 | #define BRGPHY_ISR_CRCERR 0x0001 /* CRC error */ |
181 | |
182 | #define BRGPHY_MII_IMR 0x1B /* Interrupt mask */ |
183 | #define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */ |
184 | #define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */ |
185 | #define BRGPHY_IMR_HCT 0x1000 /* Counter above 32K */ |
186 | #define BRGPHY_IMR_LCT 0x0800 /* All counter below 128 */ |
187 | #define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */ |
188 | #define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */ |
189 | #define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */ |
190 | #define BRGPHY_IMR_USHDC 0x0080 /* Negotiated Unsupported HCD */ |
191 | #define BRGPHY_IMR_SCR_S_ERR 0x0040 /* Scrambler sync error */ |
192 | #define BRGPHY_IMR_RRS_CHG 0x0020 /* Remote RX status change */ |
193 | #define BRGPHY_IMR_LRS_CHG 0x0010 /* Local RX status change */ |
194 | #define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */ |
195 | #define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */ |
196 | #define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */ |
197 | #define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */ |
198 | |
199 | /*******************************************************/ |
200 | /* Begin: PHY register values for the 5706 PHY */ |
201 | /*******************************************************/ |
202 | |
203 | /* |
204 | * Shadow register 0x1C, bit 15 is write enable, |
205 | * bits 14-10 select function (0x00 to 0x1F). |
206 | */ |
207 | #define BRGPHY_MII_SHADOW_1C 0x1C |
208 | #define BRGPHY_SHADOW_1C_WRITE_EN 0x8000 |
209 | #define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00 |
210 | |
211 | /* Shadow 0x1C Mode Control Register (select value 0x1F) */ |
212 | #define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10) |
213 | /* When set, Regs 0-0x0F are 1000X, else 1000T */ |
214 | #define BRGPHY_SHADOW_1C_ENA_1000X 0x0001 |
215 | |
216 | #define BRGPHY_TEST1 0x1E |
217 | #define BRGPHY_TEST1_TRIM_EN 0x0010 |
218 | #define BRGPHY_TEST1_CRC_EN 0x8000 |
219 | |
220 | #define BRGPHY_MII_TEST2 0x1F |
221 | |
222 | /*******************************************************/ |
223 | /* End: PHY register values for the 5706 PHY */ |
224 | /*******************************************************/ |
225 | |
226 | /*******************************************************/ |
227 | /* Begin: PHY register values for the 5708S SerDes PHY */ |
228 | /*******************************************************/ |
229 | |
230 | #define BRGPHY_5708S_BMCR_2500 0x20 |
231 | |
232 | /* Autoneg Next Page Transmit 1 Regiser */ |
233 | #define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B |
234 | #define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001 |
235 | |
236 | /* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */ |
237 | #define BRGPHY_5708S_BLOCK_ADDR 0x1f |
238 | #define BRGPHY_5708S_DIG_PG0 0x0000 |
239 | #define BRGPHY_5708S_DIG3_PG2 0x0002 |
240 | #define BRGPHY_5708S_TX_MISC_PG5 0x0005 |
241 | |
242 | /* 5708S SerDes "Digital" Registers (page 0) */ |
243 | #define BRGPHY_5708S_PG0_1000X_CTL1 0x10 |
244 | #define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001 |
245 | #define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010 |
246 | |
247 | #define BRGPHY_5708S_PG0_1000X_CTL2 0x11 |
248 | #define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001 |
249 | |
250 | #define BRGPHY_5708S_PG0_1000X_STAT1 0x14 |
251 | #define BRGPHY_5708S_PG0_1000X_STAT1_SGMII 0x0001 |
252 | #define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002 |
253 | #define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004 |
254 | #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018 |
255 | #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3) |
256 | #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3) |
257 | #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3) |
258 | #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3) |
259 | #define BRGPHY_5708S_PG0_1000X_STAT1_TX_PAUSE 0x0020 |
260 | #define BRGPHY_5708S_PG0_1000X_STAT1_RX_PAUSE 0x0040 |
261 | |
262 | /* 5708S SerDes "Digital 3" Registers (page 2) */ |
263 | #define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10 |
264 | #define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001 |
265 | |
266 | /* 5708S SerDes "TX Misc" Registers (page 5) */ |
267 | #define BRGPHY_5708S_PG5_2500STATUS1 0x10 |
268 | |
269 | #define BRGPHY_5708S_PG5_TXACTL1 0x15 |
270 | #define BRGPHY_5708S_PG5_TXACTL1_VCM 0x30 |
271 | |
272 | #define BRGPHY_5708S_PG5_TXACTL3 0x17 |
273 | |
274 | /*******************************************************/ |
275 | /* End: PHY register values for the 5708S SerDes PHY */ |
276 | /*******************************************************/ |
277 | |
278 | /*******************************************************/ |
279 | /* Begin: PHY register values for the 5709S SerDes PHY */ |
280 | /*******************************************************/ |
281 | |
282 | /* 5709S SerDes "General Purpose Status" Registers */ |
283 | #define BRGPHY_BLOCK_ADDR_GP_STATUS 0x8120 |
284 | #define BRGPHY_GP_STATUS_TOP_ANEG_STATUS 0x1B |
285 | #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK 0x3F00 |
286 | #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10 0x0000 |
287 | #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100 0x0100 |
288 | #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G 0x0200 |
289 | #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G 0x0300 |
290 | #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX 0x0D00 |
291 | #define BRGPHY_GP_STATUS_TOP_ANEG_FDX 0x0008 |
292 | #define BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP 0x0004 |
293 | #define BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP 0x0001 |
294 | |
295 | /* 5709S SerDes "SerDes Digital" Registers */ |
296 | #define BRGPHY_BLOCK_ADDR_SERDES_DIG 0x8300 |
297 | #define BRGPHY_SERDES_DIG_1000X_CTL1 0x0010 |
298 | #define BRGPHY_SD_DIG_1000X_CTL1_AUTODET 0x0010 |
299 | #define BRGPHY_SD_DIG_1000X_CTL1_FIBER 0x0001 |
300 | |
301 | /* 5709S SerDes "Over 1G" Registers */ |
302 | #define BRGPHY_BLOCK_ADDR_OVER_1G 0x8320 |
303 | #define BRGPHY_OVER_1G_UNFORMAT_PG1 0x19 |
304 | |
305 | /* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */ |
306 | #define BRGPHY_BLOCK_ADDR_MRBE 0x8350 |
307 | #define BRGPHY_MRBE_MSG_PG5_NP 0x10 |
308 | #define BRGPHY_MRBE_MSG_PG5_NP_MBRE 0x0001 |
309 | #define BRGPHY_MRBE_MSG_PG5_NP_T2 0x0002 |
310 | |
311 | /* 5709S SerDes "IEEE Clause 73 User B0" Registers */ |
312 | #define BRGPHY_BLOCK_ADDR_CL73_USER_B0 0x8370 |
313 | #define BRGPHY_CL73_USER_B0_MBRE_CTL1 0x12 |
314 | #define BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP 0x2000 |
315 | #define BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR 0x4000 |
316 | #define BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG 0x8000 |
317 | |
318 | /* 5709S SerDes "IEEE Clause 73 User B0" Registers */ |
319 | #define BRGPHY_BLOCK_ADDR_ADDR_EXT 0xFFD0 |
320 | |
321 | /* 5709S SerDes "Combo IEEE 0" Registers */ |
322 | #define BRGPHY_BLOCK_ADDR_COMBO_IEEE0 0xFFE0 |
323 | |
324 | #define BRGPHY_ADDR_EXT 0x1E |
325 | #define BRGPHY_BLOCK_ADDR 0x1F |
326 | |
327 | #define BRGPHY_ADDR_EXT_AN_MMD 0x3800 |
328 | |
329 | /*******************************************************/ |
330 | /* End: PHY register values for the 5709S SerDes PHY */ |
331 | /*******************************************************/ |
332 | |
333 | #define BRGPHY_INTRS \ |
334 | ~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG) |
335 | |
336 | #endif /* _DEV_BRGPHY_MIIREG_H_ */ |
337 | |