1/* $NetBSD: nouveau_subdev_fb_ramnv50.c,v 1.1.1.1 2014/08/06 12:36:30 riastradh Exp $ */
2
3/*
4 * Copyright 2013 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26
27#include <sys/cdefs.h>
28__KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_fb_ramnv50.c,v 1.1.1.1 2014/08/06 12:36:30 riastradh Exp $");
29
30#include <subdev/bios.h>
31#include <subdev/bios/bit.h>
32#include <subdev/bios/pll.h>
33#include <subdev/bios/perf.h>
34#include <subdev/bios/timing.h>
35#include <subdev/clock/pll.h>
36#include <subdev/fb.h>
37
38#include <core/option.h>
39#include <core/mm.h>
40
41#include "ramseq.h"
42
43#include "nv50.h"
44
45struct nv50_ramseq {
46 struct hwsq base;
47 struct hwsq_reg r_0x002504;
48 struct hwsq_reg r_0x004008;
49 struct hwsq_reg r_0x00400c;
50 struct hwsq_reg r_0x00c040;
51 struct hwsq_reg r_0x100210;
52 struct hwsq_reg r_0x1002d0;
53 struct hwsq_reg r_0x1002d4;
54 struct hwsq_reg r_0x1002dc;
55 struct hwsq_reg r_0x100da0[8];
56 struct hwsq_reg r_0x100e20;
57 struct hwsq_reg r_0x100e24;
58 struct hwsq_reg r_0x611200;
59 struct hwsq_reg r_timing[9];
60 struct hwsq_reg r_mr[4];
61};
62
63struct nv50_ram {
64 struct nouveau_ram base;
65 struct nv50_ramseq hwsq;
66};
67
68#define QFX5800NVA0 1
69
70static int
71nv50_ram_calc(struct nouveau_fb *pfb, u32 freq)
72{
73 struct nouveau_bios *bios = nouveau_bios(pfb);
74 struct nv50_ram *ram = (void *)pfb->ram;
75 struct nv50_ramseq *hwsq = &ram->hwsq;
76 struct nvbios_perfE perfE;
77 struct nvbios_pll mpll;
78 struct {
79 u32 data;
80 u8 size;
81 } ramcfg, timing;
82 u8 ver, hdr, cnt, len, strap;
83 int N1, M1, N2, M2, P;
84 int ret, i;
85
86 /* lookup closest matching performance table entry for frequency */
87 i = 0;
88 do {
89 ramcfg.data = nvbios_perfEp(bios, i++, &ver, &hdr, &cnt,
90 &ramcfg.size, &perfE);
91 if (!ramcfg.data || (ver < 0x25 || ver >= 0x40) ||
92 (ramcfg.size < 2)) {
93 nv_error(pfb, "invalid/missing perftab entry\n");
94 return -EINVAL;
95 }
96 } while (perfE.memory < freq);
97
98 /* locate specific data set for the attached memory */
99 strap = nvbios_ramcfg_index(nv_subdev(pfb));
100 if (strap >= cnt) {
101 nv_error(pfb, "invalid ramcfg strap\n");
102 return -EINVAL;
103 }
104
105 ramcfg.data += hdr + (strap * ramcfg.size);
106
107 /* lookup memory timings, if bios says they're present */
108 strap = nv_ro08(bios, ramcfg.data + 0x01);
109 if (strap != 0xff) {
110 timing.data = nvbios_timingEe(bios, strap, &ver, &hdr,
111 &cnt, &len);
112 if (!timing.data || ver != 0x10 || hdr < 0x12) {
113 nv_error(pfb, "invalid/missing timing entry "
114 "%02x %04x %02x %02x\n",
115 strap, timing.data, ver, hdr);
116 return -EINVAL;
117 }
118 } else {
119 timing.data = 0;
120 }
121
122 ret = ram_init(hwsq, nv_subdev(pfb));
123 if (ret)
124 return ret;
125
126 ram_wait(hwsq, 0x01, 0x00); /* wait for !vblank */
127 ram_wait(hwsq, 0x01, 0x01); /* wait for vblank */
128 ram_wr32(hwsq, 0x611200, 0x00003300);
129 ram_wr32(hwsq, 0x002504, 0x00000001); /* block fifo */
130 ram_nsec(hwsq, 8000);
131 ram_setf(hwsq, 0x10, 0x00); /* disable fb */
132 ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
133
134 ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */
135 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */
136 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */
137 ram_wr32(hwsq, 0x100210, 0x00000000); /* disable auto-refresh */
138 ram_wr32(hwsq, 0x1002dc, 0x00000001); /* enable self-refresh */
139
140 ret = nvbios_pll_parse(bios, 0x004008, &mpll);
141 mpll.vco2.max_freq = 0;
142 if (ret == 0) {
143 ret = nv04_pll_calc(nv_subdev(pfb), &mpll, freq,
144 &N1, &M1, &N2, &M2, &P);
145 if (ret == 0)
146 ret = -EINVAL;
147 }
148
149 if (ret < 0)
150 return ret;
151
152 ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000);
153 ram_mask(hwsq, 0x004008, 0x00000200, 0x00000200);
154 ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1);
155 ram_mask(hwsq, 0x004008, 0x81ff0000, 0x80000000 | (mpll.bias_p << 19) |
156 (P << 22) | (P << 16));
157#if QFX5800NVA0
158 for (i = 0; i < 8; i++)
159 ram_mask(hwsq, 0x100da0[i], 0x00000000, 0x00000000); /*XXX*/
160#endif
161 ram_nsec(hwsq, 96000); /*XXX*/
162 ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000);
163
164 ram_wr32(hwsq, 0x1002dc, 0x00000000); /* disable self-refresh */
165 ram_wr32(hwsq, 0x100210, 0x80000000); /* enable auto-refresh */
166
167 ram_nsec(hwsq, 12000);
168
169 switch (ram->base.type) {
170 case NV_MEM_TYPE_DDR2:
171 ram_nuke(hwsq, mr[0]); /* force update */
172 ram_mask(hwsq, mr[0], 0x000, 0x000);
173 break;
174 case NV_MEM_TYPE_GDDR3:
175 ram_mask(hwsq, mr[2], 0x000, 0x000);
176 ram_nuke(hwsq, mr[0]); /* force update */
177 ram_mask(hwsq, mr[0], 0x000, 0x000);
178 break;
179 default:
180 break;
181 }
182
183 ram_mask(hwsq, timing[3], 0x00000000, 0x00000000); /*XXX*/
184 ram_mask(hwsq, timing[1], 0x00000000, 0x00000000); /*XXX*/
185 ram_mask(hwsq, timing[6], 0x00000000, 0x00000000); /*XXX*/
186 ram_mask(hwsq, timing[7], 0x00000000, 0x00000000); /*XXX*/
187 ram_mask(hwsq, timing[8], 0x00000000, 0x00000000); /*XXX*/
188 ram_mask(hwsq, timing[0], 0x00000000, 0x00000000); /*XXX*/
189 ram_mask(hwsq, timing[2], 0x00000000, 0x00000000); /*XXX*/
190 ram_mask(hwsq, timing[4], 0x00000000, 0x00000000); /*XXX*/
191 ram_mask(hwsq, timing[5], 0x00000000, 0x00000000); /*XXX*/
192
193 ram_mask(hwsq, timing[0], 0x00000000, 0x00000000); /*XXX*/
194
195#if QFX5800NVA0
196 ram_nuke(hwsq, 0x100e24);
197 ram_mask(hwsq, 0x100e24, 0x00000000, 0x00000000);
198 ram_nuke(hwsq, 0x100e20);
199 ram_mask(hwsq, 0x100e20, 0x00000000, 0x00000000);
200#endif
201
202 ram_mask(hwsq, mr[0], 0x100, 0x100);
203 ram_mask(hwsq, mr[0], 0x100, 0x000);
204
205 ram_setf(hwsq, 0x10, 0x01); /* enable fb */
206 ram_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
207 ram_wr32(hwsq, 0x611200, 0x00003330);
208 ram_wr32(hwsq, 0x002504, 0x00000000); /* un-block fifo */
209 return 0;
210}
211
212static int
213nv50_ram_prog(struct nouveau_fb *pfb)
214{
215 struct nouveau_device *device = nv_device(pfb);
216 struct nv50_ram *ram = (void *)pfb->ram;
217 struct nv50_ramseq *hwsq = &ram->hwsq;
218
219 ram_exec(hwsq, nouveau_boolopt(device->cfgopt, "NvMemExec", false));
220 return 0;
221}
222
223static void
224nv50_ram_tidy(struct nouveau_fb *pfb)
225{
226 struct nv50_ram *ram = (void *)pfb->ram;
227 struct nv50_ramseq *hwsq = &ram->hwsq;
228 ram_exec(hwsq, false);
229}
230
231void
232__nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem *mem)
233{
234 struct nouveau_mm_node *this;
235
236 while (!list_empty(&mem->regions)) {
237 this = list_first_entry(&mem->regions, typeof(*this), rl_entry);
238
239 list_del(&this->rl_entry);
240 nouveau_mm_free(&pfb->vram, &this);
241 }
242
243 nouveau_mm_free(&pfb->tags, &mem->tag);
244}
245
246void
247nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
248{
249 struct nouveau_mem *mem = *pmem;
250
251 *pmem = NULL;
252 if (unlikely(mem == NULL))
253 return;
254
255 mutex_lock(&pfb->base.mutex);
256 __nv50_ram_put(pfb, mem);
257 mutex_unlock(&pfb->base.mutex);
258
259 kfree(mem);
260}
261
262int
263nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
264 u32 memtype, struct nouveau_mem **pmem)
265{
266 struct nouveau_mm *heap = &pfb->vram;
267 struct nouveau_mm *tags = &pfb->tags;
268 struct nouveau_mm_node *r;
269 struct nouveau_mem *mem;
270 int comp = (memtype & 0x300) >> 8;
271 int type = (memtype & 0x07f);
272 int back = (memtype & 0x800);
273 int min, max, ret;
274
275 max = (size >> 12);
276 min = ncmin ? (ncmin >> 12) : max;
277 align >>= 12;
278
279 mem = kzalloc(sizeof(*mem), GFP_KERNEL);
280 if (!mem)
281 return -ENOMEM;
282
283 mutex_lock(&pfb->base.mutex);
284 if (comp) {
285 if (align == 16) {
286 int n = (max >> 4) * comp;
287
288 ret = nouveau_mm_head(tags, 1, n, n, 1, &mem->tag);
289 if (ret)
290 mem->tag = NULL;
291 }
292
293 if (unlikely(!mem->tag))
294 comp = 0;
295 }
296
297 INIT_LIST_HEAD(&mem->regions);
298 mem->memtype = (comp << 7) | type;
299 mem->size = max;
300
301 type = nv50_fb_memtype[type];
302 do {
303 if (back)
304 ret = nouveau_mm_tail(heap, type, max, min, align, &r);
305 else
306 ret = nouveau_mm_head(heap, type, max, min, align, &r);
307 if (ret) {
308 mutex_unlock(&pfb->base.mutex);
309 pfb->ram->put(pfb, &mem);
310 return ret;
311 }
312
313 list_add_tail(&r->rl_entry, &mem->regions);
314 max -= r->length;
315 } while (max);
316 mutex_unlock(&pfb->base.mutex);
317
318 r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
319 mem->offset = (u64)r->offset << 12;
320 *pmem = mem;
321 return 0;
322}
323
324static u32
325nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram)
326{
327 int i, parts, colbits, rowbitsa, rowbitsb, banks;
328 u64 rowsize, predicted;
329 u32 r0, r4, rt, ru, rblock_size;
330
331 r0 = nv_rd32(pfb, 0x100200);
332 r4 = nv_rd32(pfb, 0x100204);
333 rt = nv_rd32(pfb, 0x100250);
334 ru = nv_rd32(pfb, 0x001540);
335 nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);
336
337 for (i = 0, parts = 0; i < 8; i++) {
338 if (ru & (0x00010000 << i))
339 parts++;
340 }
341
342 colbits = (r4 & 0x0000f000) >> 12;
343 rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
344 rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
345 banks = 1 << (((r4 & 0x03000000) >> 24) + 2);
346
347 rowsize = parts * banks * (1 << colbits) * 8;
348 predicted = rowsize << rowbitsa;
349 if (r0 & 0x00000004)
350 predicted += rowsize << rowbitsb;
351
352 if (predicted != ram->size) {
353 nv_warn(pfb, "memory controller reports %d MiB VRAM\n",
354 (u32)(ram->size >> 20));
355 }
356
357 rblock_size = rowsize;
358 if (rt & 1)
359 rblock_size *= 3;
360
361 nv_debug(pfb, "rblock %d bytes\n", rblock_size);
362 return rblock_size;
363}
364
365int
366nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
367 struct nouveau_oclass *oclass, int length, void **pobject)
368{
369 const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
370 const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
371 struct nouveau_bios *bios = nouveau_bios(parent);
372 struct nouveau_fb *pfb = nouveau_fb(parent);
373 struct nouveau_ram *ram;
374 int ret;
375
376 ret = nouveau_ram_create_(parent, engine, oclass, length, pobject);
377 ram = *pobject;
378 if (ret)
379 return ret;
380
381 ram->size = nv_rd32(pfb, 0x10020c);
382 ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32);
383
384 switch (nv_rd32(pfb, 0x100714) & 0x00000007) {
385 case 0: ram->type = NV_MEM_TYPE_DDR1; break;
386 case 1:
387 if (nouveau_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3)
388 ram->type = NV_MEM_TYPE_DDR3;
389 else
390 ram->type = NV_MEM_TYPE_DDR2;
391 break;
392 case 2: ram->type = NV_MEM_TYPE_GDDR3; break;
393 case 3: ram->type = NV_MEM_TYPE_GDDR4; break;
394 case 4: ram->type = NV_MEM_TYPE_GDDR5; break;
395 default:
396 break;
397 }
398
399 ret = nouveau_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) -
400 (rsvd_head + rsvd_tail),
401 nv50_fb_vram_rblock(pfb, ram) >> 12);
402 if (ret)
403 return ret;
404
405 ram->ranks = (nv_rd32(pfb, 0x100200) & 0x4) ? 2 : 1;
406 ram->tags = nv_rd32(pfb, 0x100320);
407 ram->get = nv50_ram_get;
408 ram->put = nv50_ram_put;
409 return 0;
410}
411
412static int
413nv50_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
414 struct nouveau_oclass *oclass, void *data, u32 datasize,
415 struct nouveau_object **pobject)
416{
417 struct nv50_ram *ram;
418 int ret, i;
419
420 ret = nv50_ram_create(parent, engine, oclass, &ram);
421 *pobject = nv_object(ram);
422 if (ret)
423 return ret;
424
425 switch (ram->base.type) {
426 case NV_MEM_TYPE_DDR2:
427 case NV_MEM_TYPE_GDDR3:
428 ram->base.calc = nv50_ram_calc;
429 ram->base.prog = nv50_ram_prog;
430 ram->base.tidy = nv50_ram_tidy;
431 break;
432 default:
433 nv_warn(ram, "reclocking of this ram type unsupported\n");
434 return 0;
435 }
436
437 ram->hwsq.r_0x002504 = hwsq_reg(0x002504);
438 ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040);
439 ram->hwsq.r_0x004008 = hwsq_reg(0x004008);
440 ram->hwsq.r_0x00400c = hwsq_reg(0x00400c);
441 ram->hwsq.r_0x100210 = hwsq_reg(0x100210);
442 ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0);
443 ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4);
444 ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc);
445 for (i = 0; i < 8; i++)
446 ram->hwsq.r_0x100da0[i] = hwsq_reg(0x100da0 + (i * 0x04));
447 ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20);
448 ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24);
449 ram->hwsq.r_0x611200 = hwsq_reg(0x611200);
450
451 for (i = 0; i < 9; i++)
452 ram->hwsq.r_timing[i] = hwsq_reg(0x100220 + (i * 0x04));
453
454 if (ram->base.ranks > 1) {
455 ram->hwsq.r_mr[0] = hwsq_reg2(0x1002c0, 0x1002c8);
456 ram->hwsq.r_mr[1] = hwsq_reg2(0x1002c4, 0x1002cc);
457 ram->hwsq.r_mr[2] = hwsq_reg2(0x1002e0, 0x1002e8);
458 ram->hwsq.r_mr[3] = hwsq_reg2(0x1002e4, 0x1002ec);
459 } else {
460 ram->hwsq.r_mr[0] = hwsq_reg(0x1002c0);
461 ram->hwsq.r_mr[1] = hwsq_reg(0x1002c4);
462 ram->hwsq.r_mr[2] = hwsq_reg(0x1002e0);
463 ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4);
464 }
465
466 return 0;
467}
468
469struct nouveau_oclass
470nv50_ram_oclass = {
471 .ofuncs = &(struct nouveau_ofuncs) {
472 .ctor = nv50_ram_ctor,
473 .dtor = _nouveau_ram_dtor,
474 .init = _nouveau_ram_init,
475 .fini = _nouveau_ram_fini,
476 }
477};
478