1 | /* $NetBSD: nouveau_engine_dmaobj_nv04.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_dmaobj_nv04.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $" ); |
29 | |
30 | #include <core/gpuobj.h> |
31 | #include <core/class.h> |
32 | |
33 | #include <subdev/fb.h> |
34 | #include <subdev/vm/nv04.h> |
35 | |
36 | #include <engine/dmaobj.h> |
37 | |
38 | struct nv04_dmaeng_priv { |
39 | struct nouveau_dmaeng base; |
40 | }; |
41 | |
42 | static int |
43 | nv04_dmaobj_bind(struct nouveau_dmaeng *dmaeng, |
44 | struct nouveau_object *parent, |
45 | struct nouveau_dmaobj *dmaobj, |
46 | struct nouveau_gpuobj **pgpuobj) |
47 | { |
48 | struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaeng); |
49 | struct nouveau_gpuobj *gpuobj; |
50 | u32 flags0 = nv_mclass(dmaobj); |
51 | u32 flags2 = 0x00000000; |
52 | u64 offset = dmaobj->start & 0xfffff000; |
53 | u64 adjust = dmaobj->start & 0x00000fff; |
54 | u32 length = dmaobj->limit - dmaobj->start; |
55 | int ret; |
56 | |
57 | if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { |
58 | switch (nv_mclass(parent->parent)) { |
59 | case NV03_CHANNEL_DMA_CLASS: |
60 | case NV10_CHANNEL_DMA_CLASS: |
61 | case NV17_CHANNEL_DMA_CLASS: |
62 | case NV40_CHANNEL_DMA_CLASS: |
63 | break; |
64 | default: |
65 | return -EINVAL; |
66 | } |
67 | } |
68 | |
69 | if (dmaobj->target == NV_MEM_TARGET_VM) { |
70 | if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass) { |
71 | struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0]; |
72 | if (!dmaobj->start) |
73 | return nouveau_gpuobj_dup(parent, pgt, pgpuobj); |
74 | offset = nv_ro32(pgt, 8 + (offset >> 10)); |
75 | offset &= 0xfffff000; |
76 | } |
77 | |
78 | dmaobj->target = NV_MEM_TARGET_PCI; |
79 | dmaobj->access = NV_MEM_ACCESS_RW; |
80 | } |
81 | |
82 | switch (dmaobj->target) { |
83 | case NV_MEM_TARGET_VRAM: |
84 | flags0 |= 0x00003000; |
85 | break; |
86 | case NV_MEM_TARGET_PCI: |
87 | flags0 |= 0x00023000; |
88 | break; |
89 | case NV_MEM_TARGET_PCI_NOSNOOP: |
90 | flags0 |= 0x00033000; |
91 | break; |
92 | default: |
93 | return -EINVAL; |
94 | } |
95 | |
96 | switch (dmaobj->access) { |
97 | case NV_MEM_ACCESS_RO: |
98 | flags0 |= 0x00004000; |
99 | break; |
100 | case NV_MEM_ACCESS_WO: |
101 | flags0 |= 0x00008000; |
102 | case NV_MEM_ACCESS_RW: |
103 | flags2 |= 0x00000002; |
104 | break; |
105 | default: |
106 | return -EINVAL; |
107 | } |
108 | |
109 | ret = nouveau_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj); |
110 | *pgpuobj = gpuobj; |
111 | if (ret == 0) { |
112 | nv_wo32(*pgpuobj, 0x00, flags0 | (adjust << 20)); |
113 | nv_wo32(*pgpuobj, 0x04, length); |
114 | nv_wo32(*pgpuobj, 0x08, flags2 | offset); |
115 | nv_wo32(*pgpuobj, 0x0c, flags2 | offset); |
116 | } |
117 | |
118 | return ret; |
119 | } |
120 | |
121 | static int |
122 | nv04_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
123 | struct nouveau_oclass *oclass, void *data, u32 size, |
124 | struct nouveau_object **pobject) |
125 | { |
126 | struct nv04_dmaeng_priv *priv; |
127 | int ret; |
128 | |
129 | ret = nouveau_dmaeng_create(parent, engine, oclass, &priv); |
130 | *pobject = nv_object(priv); |
131 | if (ret) |
132 | return ret; |
133 | |
134 | nv_engine(priv)->sclass = nouveau_dmaobj_sclass; |
135 | priv->base.bind = nv04_dmaobj_bind; |
136 | return 0; |
137 | } |
138 | |
139 | struct nouveau_oclass |
140 | nv04_dmaeng_oclass = { |
141 | .handle = NV_ENGINE(DMAOBJ, 0x04), |
142 | .ofuncs = &(struct nouveau_ofuncs) { |
143 | .ctor = nv04_dmaeng_ctor, |
144 | .dtor = _nouveau_dmaeng_dtor, |
145 | .init = _nouveau_dmaeng_init, |
146 | .fini = _nouveau_dmaeng_fini, |
147 | }, |
148 | }; |
149 | |