1/* $NetBSD: if_stgereg.h,v 1.5 2008/04/28 20:23:55 martin Exp $ */
2
3/*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _DEV_PCI_IF_STGEREG_H_
33#define _DEV_PCI_IF_STGEREG_H_
34
35/*
36 * Register description for the Sundance Tech. TC9021 10/100/1000
37 * Ethernet controller.
38 *
39 * Note that while DMA addresses are all in 64-bit fields, only
40 * the lower 40 bits of a DMA address are valid.
41 */
42
43/*
44 * TC9021 buffer fragment descriptor.
45 */
46struct stge_frag {
47 uint64_t frag_word0; /* address, length */
48} __packed;
49
50#define FRAG_ADDR(x) (((uint64_t)(x)) << 0)
51#define FRAG_ADDR_MASK FRAG_ADDR(0xfffffffffULL)
52#define FRAG_LEN(x) (((uint64_t)(x)) << 48)
53#define FRAG_LEN_MASK FRAG_LEN(0xffffULL)
54
55/*
56 * TC9021 Transmit Frame Descriptor. Note the number of fragments
57 * here is arbitrary, but we can't have any more than 15.
58 */
59#define STGE_NTXFRAGS 12
60struct stge_tfd {
61 uint64_t tfd_next; /* next TFD in list */
62 uint64_t tfd_control; /* control bits */
63 /* the buffer fragments */
64 struct stge_frag tfd_frags[STGE_NTXFRAGS];
65} __packed;
66
67#define TFD_FrameId(x) ((x) << 0)
68#define TFD_FrameId_MAX 0xffff
69#define TFD_WordAlign(x) ((x) << 16)
70#define TFD_WordAlign_dword 0 /* align to dword in TxFIFO */
71#define TFD_WordAlign_word 2 /* align to word in TxFIFO */
72#define TFD_WordAlign_disable 1 /* disable alignment */
73#define TFD_TCPChecksumEnable (1ULL << 18)
74#define TFD_UDPChecksumEnable (1ULL << 19)
75#define TFD_IPChecksumEnable (1ULL << 20)
76#define TFD_FcsAppendDisable (1ULL << 21)
77#define TFD_TxIndicate (1ULL << 22)
78#define TFD_TxDMAIndicate (1ULL << 23)
79#define TFD_FragCount(x) ((x) << 24)
80#define TFD_VLANTagInsert (1ULL << 28)
81#define TFD_TFDDone (1ULL << 31)
82#define TFD_VID(x) (((uint64_t)(x)) << 32)
83#define TFD_CFI (1ULL << 44)
84#define TFD_UserPriority(x) (((uint64_t)(x)) << 45)
85
86/*
87 * TC9021 Receive Frame Descriptor. Each RFD has a single fragment
88 * in it, and the chip tells us the beginning and end of the frame.
89 */
90struct stge_rfd {
91 uint64_t rfd_next; /* next RFD in list */
92 uint64_t rfd_status; /* status bits */
93 struct stge_frag rfd_frag; /* the buffer */
94} __packed;
95
96#define RFD_RxDMAFrameLen(x) ((x) & 0xffff)
97#define RFD_RxFIFOOverrun (1ULL << 16)
98#define RFD_RxRuntFrame (1ULL << 17)
99#define RFD_RxAlignmentError (1ULL << 18)
100#define RFD_RxFCSError (1ULL << 19)
101#define RFD_RxOversizedFrame (1ULL << 20)
102#define RFD_RxLengthError (1ULL << 21)
103#define RFD_VLANDetected (1ULL << 22)
104#define RFD_TCPDetected (1ULL << 23)
105#define RFD_TCPError (1ULL << 24)
106#define RFD_UDPDetected (1ULL << 25)
107#define RFD_UDPError (1ULL << 26)
108#define RFD_IPDetected (1ULL << 27)
109#define RFD_IPError (1ULL << 28)
110#define RFD_FrameStart (1ULL << 29)
111#define RFD_FrameEnd (1ULL << 30)
112#define RFD_RFDDone (1ULL << 31)
113#define RFD_TCI(x) ((((uint64_t)(x)) >> 32) & 0xffff)
114
115/*
116 * PCI configuration registers used by the TC9021.
117 */
118
119#define STGE_PCI_IOBA (PCI_MAPREG_START + 0x00)
120#define STGE_PCI_MMBA (PCI_MAPREG_START + 0x04)
121
122/*
123 * EEPROM offsets.
124 */
125#define STGE_EEPROM_ConfigParam 0x00
126#define STGE_EEPROM_AsicCtrl 0x01
127#define STGE_EEPROM_SubSystemVendorId 0x02
128#define STGE_EEPROM_SubSystemId 0x03
129#define STGE_EEPROM_StationAddress0 0x10
130#define STGE_EEPROM_StationAddress1 0x11
131#define STGE_EEPROM_StationAddress2 0x12
132
133/*
134 * The TC9021 register space.
135 */
136
137#define STGE_DMACtrl 0x00
138#define DMAC_RxDMAComplete (1U << 3)
139#define DMAC_RxDMAPollNow (1U << 4)
140#define DMAC_TxDMAComplete (1U << 11)
141#define DMAC_TxDMAPollNow (1U << 12)
142#define DMAC_TxDMAInProg (1U << 15)
143#define DMAC_RxEarlyDisable (1U << 16)
144#define DMAC_MWIDisable (1U << 18)
145#define DMAC_TxWiteBackDisable (1U << 19)
146#define DMAC_TxBurstLimit(x) ((x) << 20)
147#define DMAC_TargetAbort (1U << 30)
148#define DMAC_MasterAbort (1U << 31)
149
150#define STGE_RxDMAStatus 0x08
151
152#define STGE_TFDListPtrLo 0x10
153
154#define STGE_TFDListPtrHi 0x14
155
156#define STGE_TxDMABurstThresh 0x18 /* 8-bit */
157
158#define STGE_TxDMAUrgentThresh 0x19 /* 8-bit */
159
160#define STGE_TxDMAPollPeriod 0x1a /* 8-bit */
161
162#define STGE_RFDListPtrLo 0x1c
163
164#define STGE_RFDListPtrHi 0x20
165
166#define STGE_RxDMABurstThresh 0x24 /* 8-bit */
167
168#define STGE_RxDMAUrgentThresh 0x25 /* 8-bit */
169
170#define STGE_RxDMAPollPeriod 0x26 /* 8-bit */
171
172#define STGE_RxDMAIntCtrl 0x28
173#define RDIC_RxFrameCount(x) ((x) & 0xff)
174#define RDIC_PriorityThresh(x) ((x) << 10)
175#define RDIC_RxDMAWaitTime(x) ((x) << 16)
176
177#define STGE_DebugCtrl 0x2c /* 16-bit */
178#define DC_GPIO0Ctrl (1U << 0)
179#define DC_GPIO1Ctrl (1U << 1)
180#define DC_GPIO0 (1U << 2)
181#define DC_GPIO1 (1U << 3)
182
183#define STGE_AsicCtrl 0x30
184#define AC_ExpRomDisable (1U << 0)
185#define AC_ExpRomSize (1U << 1)
186#define AC_PhySpeed10 (1U << 4)
187#define AC_PhySpeed100 (1U << 5)
188#define AC_PhySpeed1000 (1U << 6)
189#define AC_PhyMedia (1U << 7)
190#define AC_ForcedConfig(x) ((x) << 8)
191#define AC_ForcedConfig_MASK AC_ForcedConfig(7)
192#define AC_D3ResetDisable (1U << 11)
193#define AC_SpeedupMode (1U << 13)
194#define AC_LEDMode (1U << 14)
195#define AC_RstOutPolarity (1U << 15)
196#define AC_GlobalReset (1U << 16)
197#define AC_RxReset (1U << 17)
198#define AC_TxReset (1U << 18)
199#define AC_DMA (1U << 19)
200#define AC_FIFO (1U << 20)
201#define AC_Network (1U << 21)
202#define AC_Host (1U << 22)
203#define AC_AutoInit (1U << 23)
204#define AC_RstOut (1U << 24)
205#define AC_InterruptRequest (1U << 25)
206#define AC_ResetBusy (1U << 26)
207
208#define STGE_FIFOCtrl 0x38 /* 16-bit */
209#define FC_RAMTestMode (1U << 0)
210#define FC_Transmitting (1U << 14)
211#define FC_Receiving (1U << 15)
212
213#define STGE_RxEarlyThresh 0x3a /* 16-bit */
214
215#define STGE_FlowOffThresh 0x3c /* 16-bit */
216
217#define STGE_FlowOnTresh 0x3e /* 16-bit */
218
219#define STGE_TxStartThresh 0x44 /* 16-bit */
220
221#define STGE_EepromData 0x48 /* 16-bit */
222
223#define STGE_EepromCtrl 0x4a /* 16-bit */
224#define EC_EepromAddress(x) ((x) & 0xff)
225#define EC_EepromOpcode(x) ((x) << 8)
226#define EC_OP_WE 0
227#define EC_OP_WR 1
228#define EC_OP_RR 2
229#define EC_OP_ER 3
230#define EC_EepromBusy (1U << 15)
231
232#define STGE_ExpRomAddr 0x4c
233
234#define STGE_ExpRomData 0x50 /* 8-bit */
235
236#define STGE_WakeEvent 0x51 /* 8-bit */
237
238#define STGE_Countdown 0x54
239#define CD_Count(x) ((x) & 0xffff)
240#define CD_CountdownSpeed (1U << 24)
241#define CD_CountdownMode (1U << 25)
242#define CD_CountdownIntEnabled (1U << 26)
243
244#define STGE_IntStatusAck 0x5a /* 16-bit */
245
246#define STGE_IntStatus 0x5e /* 16-bit */
247
248#define STGE_IntEnable 0x5c /* 16-bit */
249
250#define IS_InterruptStatus (1U << 0)
251#define IS_HostError (1U << 1)
252#define IS_TxComplete (1U << 2)
253#define IS_MACControlFrame (1U << 3)
254#define IS_RxComplete (1U << 4)
255#define IS_RxEarly (1U << 5)
256#define IS_InRequested (1U << 6)
257#define IS_UpdateStats (1U << 7)
258#define IS_LinkEvent (1U << 8)
259#define IS_TxDMAComplete (1U << 9)
260#define IS_RxDMAComplete (1U << 10)
261#define IS_RFDListEnd (1U << 11)
262#define IS_RxDMAPriority (1U << 12)
263
264#define STGE_TxStatus 0x60
265#define TS_TxError (1U << 0)
266#define TS_LateCollision (1U << 2)
267#define TS_MaxCollisions (1U << 3)
268#define TS_TxUnderrun (1U << 4)
269#define TS_TxIndicateReqd (1U << 6)
270#define TS_TxComplete (1U << 7)
271#define TS_TxFrameId_get(x) ((x) >> 16)
272
273#define STGE_MACCtrl 0x6c
274#define MC_IFSSelect(x) ((x) & 3)
275#define MC_DuplexSelect (1U << 5)
276#define MC_RcvLargeFrames (1U << 6)
277#define MC_TxFlowControlEnable (1U << 7)
278#define MC_RxFlowControlEnable (1U << 8)
279#define MC_RcvFCS (1U << 9)
280#define MC_FIFOLoopback (1U << 10)
281#define MC_MACLoopback (1U << 11)
282#define MC_AutoVLANtagging (1U << 12)
283#define MC_AutoVLANuntagging (1U << 13)
284#define MC_CollisionDetect (1U << 16)
285#define MC_CarrierSense (1U << 17)
286#define MC_StatisticsEnable (1U << 21)
287#define MC_StatisticsDisable (1U << 22)
288#define MC_StatisticsEnabled (1U << 23)
289#define MC_TxEnable (1U << 24)
290#define MC_TxDisable (1U << 25)
291#define MC_TxEnabled (1U << 26)
292#define MC_RxEnable (1U << 27)
293#define MC_RxDisable (1U << 28)
294#define MC_RxEnabled (1U << 29)
295#define MC_Paused (1U << 30)
296
297#define STGE_VLANTag 0x70
298
299#define STGE_PhyCtrl 0x76 /* 8-bit */
300#define PC_MgmtClk (1U << 0)
301#define PC_MgmtData (1U << 1)
302#define PC_MgmtDir (1U << 2) /* MAC->PHY */
303#define PC_PhyDuplexPolarity (1U << 3)
304#define PC_PhyDuplexStatus (1U << 4)
305#define PC_PhyLnkPolarity (1U << 5)
306#define PC_LinkSpeed(x) (((x) >> 6) & 3)
307#define PC_LinkSpeed_Down 0
308#define PC_LinkSpeed_10 1
309#define PC_LinkSpeed_100 2
310#define PC_LinkSpeed_1000 3
311
312#define STGE_StationAddress0 0x78 /* 16-bit */
313
314#define STGE_StationAddress1 0x7a /* 16-bit */
315
316#define STGE_StationAddress2 0x7c /* 16-bit */
317
318#define STGE_VLANHashTable 0x7e /* 16-bit */
319
320#define STGE_VLANId 0x80
321
322#define STGE_MaxFrameSize 0x84
323
324#define STGE_ReceiveMode 0x88 /* 16-bit */
325#define RM_ReceiveUnicast (1U << 0)
326#define RM_ReceiveMulticast (1U << 1)
327#define RM_ReceiveBroadcast (1U << 2)
328#define RM_ReceiveAllFrames (1U << 3)
329#define RM_ReceiveMulticastHash (1U << 4)
330#define RM_ReceiveIPMulticast (1U << 5)
331#define RM_ReceiveVLANMatch (1U << 8)
332#define RM_ReceiveVLANHash (1U << 9)
333
334#define STGE_HashTable0 0x8c
335
336#define STGE_HashTable1 0x90
337
338#define STGE_RMONStatisticsMask 0x98 /* set to disable */
339
340#define STGE_StatisticsMask 0x9c /* set to disable */
341
342#define STGE_RxJumboFrames 0xbc /* 16-bit */
343
344#define STGE_TCPCheckSumErrors 0xc0 /* 16-bit */
345
346#define STGE_IPCheckSumErrors 0xc2 /* 16-bit */
347
348#define STGE_UDPCheckSumErrors 0xc4 /* 16-bit */
349
350#define STGE_TxJumboFrames 0xf4 /* 16-bit */
351
352/*
353 * TC9021 statistics. Available memory and I/O mapped.
354 */
355
356#define STGE_OctetRcvOk 0xa8
357
358#define STGE_McstOctetRcvdOk 0xac
359
360#define STGE_BcstOctetRcvdOk 0xb0
361
362#define STGE_FramesRcvdOk 0xb4
363
364#define STGE_McstFramesRcvdOk 0xb8
365
366#define STGE_BcstFramesRcvdOk 0xbe /* 16-bit */
367
368#define STGE_MacControlFramesRcvd 0xc6 /* 16-bit */
369
370#define STGE_FrameTooLongErrors 0xc8 /* 16-bit */
371
372#define STGE_InRangeLengthErrors 0xca /* 16-bit */
373
374#define STGE_FramesCheckSeqErrors 0xcc /* 16-bit */
375
376#define STGE_FramesLostRxErrors 0xce /* 16-bit */
377
378#define STGE_OctetXmtdOk 0xd0
379
380#define STGE_McstOctetXmtdOk 0xd4
381
382#define STGE_BcstOctetXmtdOk 0xd8
383
384#define STGE_FramesXmtdOk 0xdc
385
386#define STGE_McstFramesXmtdOk 0xe0
387
388#define STGE_FramesWDeferredXmt 0xe4
389
390#define STGE_LateCollisions 0xe8
391
392#define STGE_MultiColFrames 0xec
393
394#define STGE_SingleColFrames 0xf0
395
396#define STGE_BcstFramesXmtdOk 0xf6 /* 16-bit */
397
398#define STGE_CarrierSenseErrors 0xf8 /* 16-bit */
399
400#define STGE_MacControlFramesXmtd 0xfa /* 16-bit */
401
402#define STGE_FramesAbortXSColls 0xfc /* 16-bit */
403
404#define STGE_FramesWEXDeferal 0xfe /* 16-bit */
405
406/*
407 * RMON-compatible statistics. Only accessible if memory-mapped.
408 */
409
410#define STGE_EtherStatsCollisions 0x100
411
412#define STGE_EtherStatsOctetsTransmit 0x104
413
414#define STGE_EtherStatsPktsTransmit 0x108
415
416#define STGE_EtherStatsPkts64OctetsTransmit 0x10c
417
418#define STGE_EtherStatsPkts64to127OctetsTransmit 0x110
419
420#define STGE_EtherStatsPkts128to255OctetsTransmit 0x114
421
422#define STGE_EtherStatsPkts256to511OctetsTransmit 0x118
423
424#define STGE_EtherStatsPkts512to1023OctetsTransmit 0x11c
425
426#define STGE_EtherStatsPkts1024to1518OctetsTransmit 0x120
427
428#define STGE_EtherStatsCRCAlignErrors 0x124
429
430#define STGE_EtherStatsUndersizePkts 0x128
431
432#define STGE_EtherStatsFragments 0x12c
433
434#define STGE_EtherStatsJabbers 0x130
435
436#define STGE_EtherStatsOctets 0x134
437
438#define STGE_EtherStatsPkts 0x138
439
440#define STGE_EtherStatsPkts64Octets 0x13c
441
442#define STGE_EtherStatsPkts65to127Octets 0x140
443
444#define STGE_EtherStatsPkts128to255Octets 0x144
445
446#define STGE_EtherStatsPkts256to511Octets 0x148
447
448#define STGE_EtherStatsPkts512to1023Octets 0x14c
449
450#define STGE_EtherStatsPkts1024to1518Octets 0x150
451
452#endif /* _DEV_PCI_IF_STGEREG_H_ */
453