1 | /* $NetBSD: nouveau_subdev_therm_nv40.c,v 1.1.1.1 2014/08/06 12:36:32 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | * Martin Peres |
26 | */ |
27 | |
28 | #include <sys/cdefs.h> |
29 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_therm_nv40.c,v 1.1.1.1 2014/08/06 12:36:32 riastradh Exp $" ); |
30 | |
31 | #include "priv.h" |
32 | |
33 | struct nv40_therm_priv { |
34 | struct nouveau_therm_priv base; |
35 | }; |
36 | |
37 | enum nv40_sensor_style { INVALID_STYLE = -1, OLD_STYLE = 0, NEW_STYLE = 1 }; |
38 | |
39 | static enum nv40_sensor_style |
40 | nv40_sensor_style(struct nouveau_therm *therm) |
41 | { |
42 | struct nouveau_device *device = nv_device(therm); |
43 | |
44 | switch (device->chipset) { |
45 | case 0x43: |
46 | case 0x44: |
47 | case 0x4a: |
48 | case 0x47: |
49 | return OLD_STYLE; |
50 | |
51 | case 0x46: |
52 | case 0x49: |
53 | case 0x4b: |
54 | case 0x4e: |
55 | case 0x4c: |
56 | case 0x67: |
57 | case 0x68: |
58 | case 0x63: |
59 | return NEW_STYLE; |
60 | default: |
61 | return INVALID_STYLE; |
62 | } |
63 | } |
64 | |
65 | static int |
66 | nv40_sensor_setup(struct nouveau_therm *therm) |
67 | { |
68 | enum nv40_sensor_style style = nv40_sensor_style(therm); |
69 | |
70 | /* enable ADC readout and disable the ALARM threshold */ |
71 | if (style == NEW_STYLE) { |
72 | nv_mask(therm, 0x15b8, 0x80000000, 0); |
73 | nv_wr32(therm, 0x15b0, 0x80003fff); |
74 | mdelay(20); /* wait for the temperature to stabilize */ |
75 | return nv_rd32(therm, 0x15b4) & 0x3fff; |
76 | } else if (style == OLD_STYLE) { |
77 | nv_wr32(therm, 0x15b0, 0xff); |
78 | mdelay(20); /* wait for the temperature to stabilize */ |
79 | return nv_rd32(therm, 0x15b4) & 0xff; |
80 | } else |
81 | return -ENODEV; |
82 | } |
83 | |
84 | static int |
85 | nv40_temp_get(struct nouveau_therm *therm) |
86 | { |
87 | struct nouveau_therm_priv *priv = (void *)therm; |
88 | struct nvbios_therm_sensor *sensor = &priv->bios_sensor; |
89 | enum nv40_sensor_style style = nv40_sensor_style(therm); |
90 | int core_temp; |
91 | |
92 | if (style == NEW_STYLE) { |
93 | nv_wr32(therm, 0x15b0, 0x80003fff); |
94 | core_temp = nv_rd32(therm, 0x15b4) & 0x3fff; |
95 | } else if (style == OLD_STYLE) { |
96 | nv_wr32(therm, 0x15b0, 0xff); |
97 | core_temp = nv_rd32(therm, 0x15b4) & 0xff; |
98 | } else |
99 | return -ENODEV; |
100 | |
101 | /* if the slope or the offset is unset, do no use the sensor */ |
102 | if (!sensor->slope_div || !sensor->slope_mult || |
103 | !sensor->offset_num || !sensor->offset_den) |
104 | return -ENODEV; |
105 | |
106 | core_temp = core_temp * sensor->slope_mult / sensor->slope_div; |
107 | core_temp = core_temp + sensor->offset_num / sensor->offset_den; |
108 | core_temp = core_temp + sensor->offset_constant - 8; |
109 | |
110 | /* reserve negative temperatures for errors */ |
111 | if (core_temp < 0) |
112 | core_temp = 0; |
113 | |
114 | return core_temp; |
115 | } |
116 | |
117 | static int |
118 | nv40_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable) |
119 | { |
120 | u32 mask = enable ? 0x80000000 : 0x0000000; |
121 | if (line == 2) nv_mask(therm, 0x0010f0, 0x80000000, mask); |
122 | else if (line == 9) nv_mask(therm, 0x0015f4, 0x80000000, mask); |
123 | else { |
124 | nv_error(therm, "unknown pwm ctrl for gpio %d\n" , line); |
125 | return -ENODEV; |
126 | } |
127 | return 0; |
128 | } |
129 | |
130 | static int |
131 | nv40_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty) |
132 | { |
133 | if (line == 2) { |
134 | u32 reg = nv_rd32(therm, 0x0010f0); |
135 | if (reg & 0x80000000) { |
136 | *duty = (reg & 0x7fff0000) >> 16; |
137 | *divs = (reg & 0x00007fff); |
138 | return 0; |
139 | } |
140 | } else |
141 | if (line == 9) { |
142 | u32 reg = nv_rd32(therm, 0x0015f4); |
143 | if (reg & 0x80000000) { |
144 | *divs = nv_rd32(therm, 0x0015f8); |
145 | *duty = (reg & 0x7fffffff); |
146 | return 0; |
147 | } |
148 | } else { |
149 | nv_error(therm, "unknown pwm ctrl for gpio %d\n" , line); |
150 | return -ENODEV; |
151 | } |
152 | |
153 | return -EINVAL; |
154 | } |
155 | |
156 | static int |
157 | nv40_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty) |
158 | { |
159 | if (line == 2) { |
160 | nv_mask(therm, 0x0010f0, 0x7fff7fff, (duty << 16) | divs); |
161 | } else |
162 | if (line == 9) { |
163 | nv_wr32(therm, 0x0015f8, divs); |
164 | nv_mask(therm, 0x0015f4, 0x7fffffff, duty); |
165 | } else { |
166 | nv_error(therm, "unknown pwm ctrl for gpio %d\n" , line); |
167 | return -ENODEV; |
168 | } |
169 | |
170 | return 0; |
171 | } |
172 | |
173 | void |
174 | nv40_therm_intr(struct nouveau_subdev *subdev) |
175 | { |
176 | struct nouveau_therm *therm = nouveau_therm(subdev); |
177 | uint32_t stat = nv_rd32(therm, 0x1100); |
178 | |
179 | /* traitement */ |
180 | |
181 | /* ack all IRQs */ |
182 | nv_wr32(therm, 0x1100, 0x70000); |
183 | |
184 | nv_error(therm, "THERM received an IRQ: stat = %x\n" , stat); |
185 | } |
186 | |
187 | static int |
188 | nv40_therm_ctor(struct nouveau_object *parent, |
189 | struct nouveau_object *engine, |
190 | struct nouveau_oclass *oclass, void *data, u32 size, |
191 | struct nouveau_object **pobject) |
192 | { |
193 | struct nv40_therm_priv *priv; |
194 | int ret; |
195 | |
196 | ret = nouveau_therm_create(parent, engine, oclass, &priv); |
197 | *pobject = nv_object(priv); |
198 | if (ret) |
199 | return ret; |
200 | |
201 | priv->base.base.pwm_ctrl = nv40_fan_pwm_ctrl; |
202 | priv->base.base.pwm_get = nv40_fan_pwm_get; |
203 | priv->base.base.pwm_set = nv40_fan_pwm_set; |
204 | priv->base.base.temp_get = nv40_temp_get; |
205 | priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling; |
206 | nv_subdev(priv)->intr = nv40_therm_intr; |
207 | return nouveau_therm_preinit(&priv->base.base); |
208 | } |
209 | |
210 | static int |
211 | nv40_therm_init(struct nouveau_object *object) |
212 | { |
213 | struct nouveau_therm *therm = (void *)object; |
214 | |
215 | nv40_sensor_setup(therm); |
216 | |
217 | return _nouveau_therm_init(object); |
218 | } |
219 | |
220 | struct nouveau_oclass |
221 | nv40_therm_oclass = { |
222 | .handle = NV_SUBDEV(THERM, 0x40), |
223 | .ofuncs = &(struct nouveau_ofuncs) { |
224 | .ctor = nv40_therm_ctor, |
225 | .dtor = _nouveau_therm_dtor, |
226 | .init = nv40_therm_init, |
227 | .fini = _nouveau_therm_fini, |
228 | }, |
229 | }; |
230 | |