1/* $NetBSD: nouveau_engine_graph_nv20.c,v 1.1.1.1 2014/08/06 12:36:26 riastradh Exp $ */
2
3#include <sys/cdefs.h>
4__KERNEL_RCSID(0, "$NetBSD: nouveau_engine_graph_nv20.c,v 1.1.1.1 2014/08/06 12:36:26 riastradh Exp $");
5
6#include <core/client.h>
7#include <core/os.h>
8#include <core/class.h>
9#include <core/engctx.h>
10#include <core/handle.h>
11#include <core/enum.h>
12
13#include <subdev/timer.h>
14#include <subdev/fb.h>
15
16#include <engine/graph.h>
17#include <engine/fifo.h>
18
19#include "nv20.h"
20#include "regs.h"
21
22/*******************************************************************************
23 * Graphics object classes
24 ******************************************************************************/
25
26static struct nouveau_oclass
27nv20_graph_sclass[] = {
28 { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
29 { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
30 { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
31 { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
32 { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
33 { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
34 { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
35 { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
36 { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
37 { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
38 { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
39 { 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */
40 { 0x0097, &nv04_graph_ofuncs, NULL }, /* kelvin */
41 { 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */
42 { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
43 {},
44};
45
46/*******************************************************************************
47 * PGRAPH context
48 ******************************************************************************/
49
50static int
51nv20_graph_context_ctor(struct nouveau_object *parent,
52 struct nouveau_object *engine,
53 struct nouveau_oclass *oclass, void *data, u32 size,
54 struct nouveau_object **pobject)
55{
56 struct nv20_graph_chan *chan;
57 int ret, i;
58
59 ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
60 0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC,
61 &chan);
62 *pobject = nv_object(chan);
63 if (ret)
64 return ret;
65
66 chan->chid = nouveau_fifo_chan(parent)->chid;
67
68 nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
69 nv_wo32(chan, 0x033c, 0xffff0000);
70 nv_wo32(chan, 0x03a0, 0x0fff0000);
71 nv_wo32(chan, 0x03a4, 0x0fff0000);
72 nv_wo32(chan, 0x047c, 0x00000101);
73 nv_wo32(chan, 0x0490, 0x00000111);
74 nv_wo32(chan, 0x04a8, 0x44400000);
75 for (i = 0x04d4; i <= 0x04e0; i += 4)
76 nv_wo32(chan, i, 0x00030303);
77 for (i = 0x04f4; i <= 0x0500; i += 4)
78 nv_wo32(chan, i, 0x00080000);
79 for (i = 0x050c; i <= 0x0518; i += 4)
80 nv_wo32(chan, i, 0x01012000);
81 for (i = 0x051c; i <= 0x0528; i += 4)
82 nv_wo32(chan, i, 0x000105b8);
83 for (i = 0x052c; i <= 0x0538; i += 4)
84 nv_wo32(chan, i, 0x00080008);
85 for (i = 0x055c; i <= 0x0598; i += 4)
86 nv_wo32(chan, i, 0x07ff0000);
87 nv_wo32(chan, 0x05a4, 0x4b7fffff);
88 nv_wo32(chan, 0x05fc, 0x00000001);
89 nv_wo32(chan, 0x0604, 0x00004000);
90 nv_wo32(chan, 0x0610, 0x00000001);
91 nv_wo32(chan, 0x0618, 0x00040000);
92 nv_wo32(chan, 0x061c, 0x00010000);
93 for (i = 0x1c1c; i <= 0x248c; i += 16) {
94 nv_wo32(chan, (i + 0), 0x10700ff9);
95 nv_wo32(chan, (i + 4), 0x0436086c);
96 nv_wo32(chan, (i + 8), 0x000c001b);
97 }
98 nv_wo32(chan, 0x281c, 0x3f800000);
99 nv_wo32(chan, 0x2830, 0x3f800000);
100 nv_wo32(chan, 0x285c, 0x40000000);
101 nv_wo32(chan, 0x2860, 0x3f800000);
102 nv_wo32(chan, 0x2864, 0x3f000000);
103 nv_wo32(chan, 0x286c, 0x40000000);
104 nv_wo32(chan, 0x2870, 0x3f800000);
105 nv_wo32(chan, 0x2878, 0xbf800000);
106 nv_wo32(chan, 0x2880, 0xbf800000);
107 nv_wo32(chan, 0x34a4, 0x000fe000);
108 nv_wo32(chan, 0x3530, 0x000003f8);
109 nv_wo32(chan, 0x3540, 0x002fe000);
110 for (i = 0x355c; i <= 0x3578; i += 4)
111 nv_wo32(chan, i, 0x001c527c);
112 return 0;
113}
114
115int
116nv20_graph_context_init(struct nouveau_object *object)
117{
118 struct nv20_graph_priv *priv = (void *)object->engine;
119 struct nv20_graph_chan *chan = (void *)object;
120 int ret;
121
122 ret = nouveau_graph_context_init(&chan->base);
123 if (ret)
124 return ret;
125
126 nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
127 return 0;
128}
129
130int
131nv20_graph_context_fini(struct nouveau_object *object, bool suspend)
132{
133 struct nv20_graph_priv *priv = (void *)object->engine;
134 struct nv20_graph_chan *chan = (void *)object;
135 int chid = -1;
136
137 nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
138 if (nv_rd32(priv, 0x400144) & 0x00010000)
139 chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24;
140 if (chan->chid == chid) {
141 nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4);
142 nv_wr32(priv, 0x400788, 0x00000002);
143 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
144 nv_wr32(priv, 0x400144, 0x10000000);
145 nv_mask(priv, 0x400148, 0xff000000, 0x1f000000);
146 }
147 nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
148
149 nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
150 return nouveau_graph_context_fini(&chan->base, suspend);
151}
152
153static struct nouveau_oclass
154nv20_graph_cclass = {
155 .handle = NV_ENGCTX(GR, 0x20),
156 .ofuncs = &(struct nouveau_ofuncs) {
157 .ctor = nv20_graph_context_ctor,
158 .dtor = _nouveau_graph_context_dtor,
159 .init = nv20_graph_context_init,
160 .fini = nv20_graph_context_fini,
161 .rd32 = _nouveau_graph_context_rd32,
162 .wr32 = _nouveau_graph_context_wr32,
163 },
164};
165
166/*******************************************************************************
167 * PGRAPH engine/subdev functions
168 ******************************************************************************/
169
170void
171nv20_graph_tile_prog(struct nouveau_engine *engine, int i)
172{
173 struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
174 struct nouveau_fifo *pfifo = nouveau_fifo(engine);
175 struct nv20_graph_priv *priv = (void *)engine;
176 unsigned long flags;
177
178 pfifo->pause(pfifo, &flags);
179 nv04_graph_idle(priv);
180
181 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
182 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
183 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
184
185 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
186 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit);
187 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
188 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch);
189 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
190 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr);
191
192 if (nv_device(engine)->chipset != 0x34) {
193 nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
194 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
195 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp);
196 }
197
198 pfifo->start(pfifo, &flags);
199}
200
201void
202nv20_graph_intr(struct nouveau_subdev *subdev)
203{
204 struct nouveau_engine *engine = nv_engine(subdev);
205 struct nouveau_object *engctx;
206 struct nouveau_handle *handle;
207 struct nv20_graph_priv *priv = (void *)subdev;
208 u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
209 u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
210 u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
211 u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
212 u32 chid = (addr & 0x01f00000) >> 20;
213 u32 subc = (addr & 0x00070000) >> 16;
214 u32 mthd = (addr & 0x00001ffc);
215 u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
216 u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
217 u32 show = stat;
218
219 engctx = nouveau_engctx_get(engine, chid);
220 if (stat & NV_PGRAPH_INTR_ERROR) {
221 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
222 handle = nouveau_handle_get_class(engctx, class);
223 if (handle && !nv_call(handle->object, mthd, data))
224 show &= ~NV_PGRAPH_INTR_ERROR;
225 nouveau_handle_put(handle);
226 }
227 }
228
229 nv_wr32(priv, NV03_PGRAPH_INTR, stat);
230 nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
231
232 if (show) {
233 nv_error(priv, "%s", "");
234 nouveau_bitfield_print(nv10_graph_intr_name, show);
235 pr_cont(" nsource:");
236 nouveau_bitfield_print(nv04_graph_nsource, nsource);
237 pr_cont(" nstatus:");
238 nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
239 pr_cont("\n");
240 nv_error(priv,
241 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
242 chid, nouveau_client_name(engctx), subc, class, mthd,
243 data);
244 }
245
246 nouveau_engctx_put(engctx);
247}
248
249static int
250nv20_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
251 struct nouveau_oclass *oclass, void *data, u32 size,
252 struct nouveau_object **pobject)
253{
254 struct nv20_graph_priv *priv;
255 int ret;
256
257 ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
258 *pobject = nv_object(priv);
259 if (ret)
260 return ret;
261
262 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
263 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
264 if (ret)
265 return ret;
266
267 nv_subdev(priv)->unit = 0x00001000;
268 nv_subdev(priv)->intr = nv20_graph_intr;
269 nv_engine(priv)->cclass = &nv20_graph_cclass;
270 nv_engine(priv)->sclass = nv20_graph_sclass;
271 nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
272 return 0;
273}
274
275void
276nv20_graph_dtor(struct nouveau_object *object)
277{
278 struct nv20_graph_priv *priv = (void *)object;
279 nouveau_gpuobj_ref(NULL, &priv->ctxtab);
280 nouveau_graph_destroy(&priv->base);
281}
282
283int
284nv20_graph_init(struct nouveau_object *object)
285{
286 struct nouveau_engine *engine = nv_engine(object);
287 struct nv20_graph_priv *priv = (void *)engine;
288 struct nouveau_fb *pfb = nouveau_fb(object);
289 u32 tmp, vramsz;
290 int ret, i;
291
292 ret = nouveau_graph_init(&priv->base);
293 if (ret)
294 return ret;
295
296 nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);
297
298 if (nv_device(priv)->chipset == 0x20) {
299 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
300 for (i = 0; i < 15; i++)
301 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
302 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
303 } else {
304 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
305 for (i = 0; i < 32; i++)
306 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
307 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
308 }
309
310 nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
311 nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
312
313 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
314 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
315 nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700);
316 nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
317 nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000);
318 nv_wr32(priv, 0x40009C , 0x00000040);
319
320 if (nv_device(priv)->chipset >= 0x25) {
321 nv_wr32(priv, 0x400890, 0x00a8cfff);
322 nv_wr32(priv, 0x400610, 0x304B1FB6);
323 nv_wr32(priv, 0x400B80, 0x1cbd3883);
324 nv_wr32(priv, 0x400B84, 0x44000000);
325 nv_wr32(priv, 0x400098, 0x40000080);
326 nv_wr32(priv, 0x400B88, 0x000000ff);
327
328 } else {
329 nv_wr32(priv, 0x400880, 0x0008c7df);
330 nv_wr32(priv, 0x400094, 0x00000005);
331 nv_wr32(priv, 0x400B80, 0x45eae20e);
332 nv_wr32(priv, 0x400B84, 0x24000000);
333 nv_wr32(priv, 0x400098, 0x00000040);
334 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
335 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
336 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
337 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
338 }
339
340 /* Turn all the tiling regions off. */
341 for (i = 0; i < pfb->tile.regions; i++)
342 engine->tile_prog(engine, i);
343
344 nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324));
345 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
346 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324));
347
348 nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
349 nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF);
350
351 tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00;
352 nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
353 tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) | 0x00020100;
354 nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
355
356 /* begin RAM config */
357 vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
358 nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
359 nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
360 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
361 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200));
362 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
363 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204));
364 nv_wr32(priv, 0x400820, 0);
365 nv_wr32(priv, 0x400824, 0);
366 nv_wr32(priv, 0x400864, vramsz - 1);
367 nv_wr32(priv, 0x400868, vramsz - 1);
368
369 /* interesting.. the below overwrites some of the tile setup above.. */
370 nv_wr32(priv, 0x400B20, 0x00000000);
371 nv_wr32(priv, 0x400B04, 0xFFFFFFFF);
372
373 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
374 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
375 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
376 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
377 return 0;
378}
379
380struct nouveau_oclass
381nv20_graph_oclass = {
382 .handle = NV_ENGINE(GR, 0x20),
383 .ofuncs = &(struct nouveau_ofuncs) {
384 .ctor = nv20_graph_ctor,
385 .dtor = nv20_graph_dtor,
386 .init = nv20_graph_init,
387 .fini = _nouveau_graph_fini,
388 },
389};
390