1 | /* $NetBSD: rt2860reg.h,v 1.7 2016/10/08 15:57:11 christos Exp $ */ |
2 | /* $OpenBSD: rt2860reg.h,v 1.33 2016/08/17 11:50:52 stsp Exp $ */ |
3 | /* $FreeBSD: head/sys/dev/ral/rt2860reg.h 301575 2016-06-08 02:37:23Z kevlo */ |
4 | |
5 | /*- |
6 | * Copyright (c) 2007 |
7 | * Damien Bergamini <damien.bergamini@free.fr> |
8 | * |
9 | * Permission to use, copy, modify, and distribute this software for any |
10 | * purpose with or without fee is hereby granted, provided that the above |
11 | * copyright notice and this permission notice appear in all copies. |
12 | * |
13 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
14 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
15 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
16 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
17 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
18 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
19 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
20 | */ |
21 | |
22 | #define RT2860_NOISE_FLOOR -95 |
23 | |
24 | /* PCI registers */ |
25 | #define RT2860_PCI_CFG 0x0000 |
26 | #define RT2860_PCI_EECTRL 0x0004 |
27 | #define RT2860_PCI_MCUCTRL 0x0008 |
28 | #define RT2860_PCI_SYSCTRL 0x000c |
29 | #define RT2860_PCIE_JTAG 0x0010 |
30 | |
31 | #define RT3090_AUX_CTRL 0x010c |
32 | |
33 | #define RT3070_OPT_14 0x0114 |
34 | |
35 | /* SCH/DMA registers */ |
36 | #define RT2860_INT_STATUS 0x0200 |
37 | #define RT2860_INT_MASK 0x0204 |
38 | #define RT2860_WPDMA_GLO_CFG 0x0208 |
39 | #define RT2860_WPDMA_RST_IDX 0x020c |
40 | #define RT2860_DELAY_INT_CFG 0x0210 |
41 | #define RT2860_WMM_AIFSN_CFG 0x0214 |
42 | #define RT2860_WMM_CWMIN_CFG 0x0218 |
43 | #define RT2860_WMM_CWMAX_CFG 0x021c |
44 | #define RT2860_WMM_TXOP0_CFG 0x0220 |
45 | #define RT2860_WMM_TXOP1_CFG 0x0224 |
46 | #define RT2860_GPIO_CTRL 0x0228 |
47 | #define RT2860_MCU_CMD_REG 0x022c |
48 | #define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16) |
49 | #define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16) |
50 | #define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16) |
51 | #define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16) |
52 | #define RT2860_RX_BASE_PTR 0x0290 |
53 | #define RT2860_RX_MAX_CNT 0x0294 |
54 | #define RT2860_RX_CALC_IDX 0x0298 |
55 | #define RT2860_FS_DRX_IDX 0x029c |
56 | #define RT2860_USB_DMA_CFG 0x02a0 /* RT2870 only */ |
57 | #define RT2860_US_CYC_CNT 0x02a4 |
58 | |
59 | /* PBF registers */ |
60 | #define RT2860_SYS_CTRL 0x0400 |
61 | #define RT2860_HOST_CMD 0x0404 |
62 | #define RT2860_PBF_CFG 0x0408 |
63 | #define RT2860_MAX_PCNT 0x040c |
64 | #define RT2860_BUF_CTRL 0x0410 |
65 | #define RT2860_MCU_INT_STA 0x0414 |
66 | #define RT2860_MCU_INT_ENA 0x0418 |
67 | #define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4) |
68 | #define RT2860_RX0Q_IO 0x0424 |
69 | #define RT2860_BCN_OFFSET0 0x042c |
70 | #define RT2860_BCN_OFFSET1 0x0430 |
71 | #define RT2860_TXRXQ_STA 0x0434 |
72 | #define RT2860_TXRXQ_PCNT 0x0438 |
73 | #define RT2860_PBF_DBG 0x043c |
74 | #define RT2860_CAP_CTRL 0x0440 |
75 | |
76 | /* RT3070 registers */ |
77 | #define RT3070_RF_CSR_CFG 0x0500 |
78 | #define RT3070_EFUSE_CTRL 0x0580 |
79 | #define RT3070_EFUSE_DATA0 0x0590 |
80 | #define RT3070_EFUSE_DATA1 0x0594 |
81 | #define RT3070_EFUSE_DATA2 0x0598 |
82 | #define RT3070_EFUSE_DATA3 0x059c |
83 | #define RT3090_OSC_CTRL 0x05a4 |
84 | #define RT3070_LDO_CFG0 0x05d4 |
85 | #define RT3070_GPIO_SWITCH 0x05dc |
86 | |
87 | /* RT5592 registers */ |
88 | #define RT5592_DEBUG_INDEX 0x05e8 |
89 | |
90 | /* MAC registers */ |
91 | #define RT2860_ASIC_VER_ID 0x1000 |
92 | #define RT2860_MAC_SYS_CTRL 0x1004 |
93 | #define RT2860_MAC_ADDR_DW0 0x1008 |
94 | #define RT2860_MAC_ADDR_DW1 0x100c |
95 | #define RT2860_MAC_BSSID_DW0 0x1010 |
96 | #define RT2860_MAC_BSSID_DW1 0x1014 |
97 | #define RT2860_MAX_LEN_CFG 0x1018 |
98 | #define RT2860_BBP_CSR_CFG 0x101c |
99 | #define RT2860_RF_CSR_CFG0 0x1020 |
100 | #define RT2860_RF_CSR_CFG1 0x1024 |
101 | #define RT2860_RF_CSR_CFG2 0x1028 |
102 | #define RT2860_LED_CFG 0x102c |
103 | |
104 | /* undocumented registers */ |
105 | #define RT2860_DEBUG 0x10f4 |
106 | |
107 | /* MAC Timing control registers */ |
108 | #define RT2860_XIFS_TIME_CFG 0x1100 |
109 | #define RT2860_BKOFF_SLOT_CFG 0x1104 |
110 | #define RT2860_NAV_TIME_CFG 0x1108 |
111 | #define RT2860_CH_TIME_CFG 0x110c |
112 | #define RT2860_PBF_LIFE_TIMER 0x1110 |
113 | #define RT2860_BCN_TIME_CFG 0x1114 |
114 | #define RT2860_TBTT_SYNC_CFG 0x1118 |
115 | #define RT2860_TSF_TIMER_DW0 0x111c |
116 | #define RT2860_TSF_TIMER_DW1 0x1120 |
117 | #define RT2860_TBTT_TIMER 0x1124 |
118 | #define RT2860_INT_TIMER_CFG 0x1128 |
119 | #define RT2860_INT_TIMER_EN 0x112c |
120 | #define RT2860_CH_IDLE_TIME 0x1130 |
121 | |
122 | /* MAC Power Save configuration registers */ |
123 | #define RT2860_MAC_STATUS_REG 0x1200 |
124 | #define RT2860_PWR_PIN_CFG 0x1204 |
125 | #define RT2860_AUTO_WAKEUP_CFG 0x1208 |
126 | |
127 | /* MAC TX configuration registers */ |
128 | #define RT2860_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4) |
129 | #define RT2860_EDCA_TID_AC_MAP 0x1310 |
130 | #define RT2860_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4) |
131 | #define RT2860_TX_PIN_CFG 0x1328 |
132 | #define RT2860_TX_BAND_CFG 0x132c |
133 | #define RT2860_TX_SW_CFG0 0x1330 |
134 | #define RT2860_TX_SW_CFG1 0x1334 |
135 | #define RT2860_TX_SW_CFG2 0x1338 |
136 | #define RT2860_TXOP_THRES_CFG 0x133c |
137 | #define RT2860_TXOP_CTRL_CFG 0x1340 |
138 | #define RT2860_TX_RTS_CFG 0x1344 |
139 | #define RT2860_TX_TIMEOUT_CFG 0x1348 |
140 | #define RT2860_TX_RTY_CFG 0x134c |
141 | #define RT2860_TX_LINK_CFG 0x1350 |
142 | #define RT2860_HT_FBK_CFG0 0x1354 |
143 | #define RT2860_HT_FBK_CFG1 0x1358 |
144 | #define RT2860_LG_FBK_CFG0 0x135c |
145 | #define RT2860_LG_FBK_CFG1 0x1360 |
146 | #define RT2860_CCK_PROT_CFG 0x1364 |
147 | #define RT2860_OFDM_PROT_CFG 0x1368 |
148 | #define RT2860_MM20_PROT_CFG 0x136c |
149 | #define RT2860_MM40_PROT_CFG 0x1370 |
150 | #define RT2860_GF20_PROT_CFG 0x1374 |
151 | #define RT2860_GF40_PROT_CFG 0x1378 |
152 | #define RT2860_EXP_CTS_TIME 0x137c |
153 | #define RT2860_EXP_ACK_TIME 0x1380 |
154 | |
155 | /* MAC RX configuration registers */ |
156 | #define RT2860_RX_FILTR_CFG 0x1400 |
157 | #define RT2860_AUTO_RSP_CFG 0x1404 |
158 | #define RT2860_LEGACY_BASIC_RATE 0x1408 |
159 | #define RT2860_HT_BASIC_RATE 0x140c |
160 | #define RT2860_HT_CTRL_CFG 0x1410 |
161 | #define RT2860_SIFS_COST_CFG 0x1414 |
162 | #define RT2860_RX_PARSER_CFG 0x1418 |
163 | |
164 | /* MAC Security configuration registers */ |
165 | #define RT2860_TX_SEC_CNT0 0x1500 |
166 | #define RT2860_RX_SEC_CNT0 0x1504 |
167 | #define RT2860_CCMP_FC_MUTE 0x1508 |
168 | |
169 | /* MAC HCCA/PSMP configuration registers */ |
170 | #define RT2860_TXOP_HLDR_ADDR0 0x1600 |
171 | #define RT2860_TXOP_HLDR_ADDR1 0x1604 |
172 | #define RT2860_TXOP_HLDR_ET 0x1608 |
173 | #define RT2860_QOS_CFPOLL_RA_DW0 0x160c |
174 | #define RT2860_QOS_CFPOLL_A1_DW1 0x1610 |
175 | #define RT2860_QOS_CFPOLL_QC 0x1614 |
176 | |
177 | /* MAC Statistics Counters */ |
178 | #define RT2860_RX_STA_CNT0 0x1700 |
179 | #define RT2860_RX_STA_CNT1 0x1704 |
180 | #define RT2860_RX_STA_CNT2 0x1708 |
181 | #define RT2860_TX_STA_CNT0 0x170c |
182 | #define RT2860_TX_STA_CNT1 0x1710 |
183 | #define RT2860_TX_STA_CNT2 0x1714 |
184 | #define RT2860_TX_STAT_FIFO 0x1718 |
185 | |
186 | /* RX WCID search table */ |
187 | #define RT2860_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8) |
188 | |
189 | #define RT2860_FW_BASE 0x2000 |
190 | #define RT2870_FW_BASE 0x3000 |
191 | |
192 | /* Pair-wise key table */ |
193 | #define RT2860_PKEY(wcid) (0x4000 + (wcid) * 32) |
194 | |
195 | /* IV/EIV table */ |
196 | #define RT2860_IVEIV(wcid) (0x6000 + (wcid) * 8) |
197 | |
198 | /* WCID attribute table */ |
199 | #define RT2860_WCID_ATTR(wcid) (0x6800 + (wcid) * 4) |
200 | |
201 | /* Shared Key Table */ |
202 | #define RT2860_SKEY(vap, kidx) (0x6c00 + (vap) * 128 + (kidx) * 32) |
203 | |
204 | /* Shared Key Mode */ |
205 | #define RT2860_SKEY_MODE_0_7 0x7000 |
206 | #define RT2860_SKEY_MODE_8_15 0x7004 |
207 | #define RT2860_SKEY_MODE_16_23 0x7008 |
208 | #define RT2860_SKEY_MODE_24_31 0x700c |
209 | |
210 | /* Shared Memory between MCU and host */ |
211 | #define RT2860_H2M_MAILBOX 0x7010 |
212 | #define RT2860_H2M_MAILBOX_CID 0x7014 |
213 | #define RT2860_H2M_MAILBOX_STATUS 0x701c |
214 | #define RT2860_H2M_INTSRC 0x7024 |
215 | #define RT2860_H2M_BBPAGENT 0x7028 |
216 | #define RT2860_BCN_BASE(vap) (0x7800 + (vap) * 512) |
217 | |
218 | |
219 | /* possible flags for RT2860_PCI_CFG */ |
220 | #define RT2860_PCI_CFG_USB (1U << 17) |
221 | #define RT2860_PCI_CFG_PCI (1U << 16) |
222 | |
223 | /* possible flags for register RT2860_PCI_EECTRL */ |
224 | #define RT2860_C (1U << 0) |
225 | #define RT2860_S (1U << 1) |
226 | #define RT2860_D (1U << 2) |
227 | #define RT2860_SHIFT_D 2 |
228 | #define RT2860_Q (1U << 3) |
229 | #define RT2860_SHIFT_Q 3 |
230 | |
231 | /* possible flags for registers INT_STATUS/INT_MASK */ |
232 | #define RT2860_TX_COHERENT (1U << 17) |
233 | #define RT2860_RX_COHERENT (1U << 16) |
234 | #define RT2860_MAC_INT_4 (1U << 15) |
235 | #define RT2860_MAC_INT_3 (1U << 14) |
236 | #define RT2860_MAC_INT_2 (1U << 13) |
237 | #define RT2860_MAC_INT_1 (1U << 12) |
238 | #define RT2860_MAC_INT_0 (1U << 11) |
239 | #define RT2860_TX_RX_COHERENT (1U << 10) |
240 | #define RT2860_MCU_CMD_INT (1U << 9) |
241 | #define RT2860_TX_DONE_INT5 (1U << 8) |
242 | #define RT2860_TX_DONE_INT4 (1U << 7) |
243 | #define RT2860_TX_DONE_INT3 (1U << 6) |
244 | #define RT2860_TX_DONE_INT2 (1U << 5) |
245 | #define RT2860_TX_DONE_INT1 (1U << 4) |
246 | #define RT2860_TX_DONE_INT0 (1U << 3) |
247 | #define RT2860_RX_DONE_INT (1U << 2) |
248 | #define RT2860_TX_DLY_INT (1U << 1) |
249 | #define RT2860_RX_DLY_INT (1U << 0) |
250 | |
251 | /* possible flags for register WPDMA_GLO_CFG */ |
252 | #define RT2860_HDR_SEG_LEN_SHIFT 8 |
253 | #define RT2860_BIG_ENDIAN (1U << 7) |
254 | #define RT2860_TX_WB_DDONE (1U << 6) |
255 | #define RT2860_WPDMA_BT_SIZE_SHIFT 4 |
256 | #define RT2860_WPDMA_BT_SIZE16 0 |
257 | #define RT2860_WPDMA_BT_SIZE32 1 |
258 | #define RT2860_WPDMA_BT_SIZE64 2 |
259 | #define RT2860_WPDMA_BT_SIZE128 3 |
260 | #define RT2860_RX_DMA_BUSY (1U << 3) |
261 | #define RT2860_RX_DMA_EN (1U << 2) |
262 | #define RT2860_TX_DMA_BUSY (1U << 1) |
263 | #define RT2860_TX_DMA_EN (1U << 0) |
264 | |
265 | /* flags for register WPDMA_RST_IDX */ |
266 | #define RT2860_RST_DRX_IDX0 (1U << 16) |
267 | #define RT2860_RST_DTX_IDX5 (1U << 5) |
268 | #define RT2860_RST_DTX_IDX4 (1U << 4) |
269 | #define RT2860_RST_DTX_IDX3 (1U << 3) |
270 | #define RT2860_RST_DTX_IDX2 (1U << 2) |
271 | #define RT2860_RST_DTX_IDX1 (1U << 1) |
272 | #define RT2860_RST_DTX_IDX0 (1U << 0) |
273 | |
274 | /* possible flags for register DELAY_INT_CFG */ |
275 | #define RT2860_TXDLY_INT_EN (1U << 31) |
276 | #define RT2860_TXMAX_PINT_SHIFT 24 |
277 | #define RT2860_TXMAX_PTIME_SHIFT 16 |
278 | #define RT2860_RXDLY_INT_EN (1U << 15) |
279 | #define RT2860_RXMAX_PINT_SHIFT 8 |
280 | #define RT2860_RXMAX_PTIME_SHIFT 0 |
281 | |
282 | /* possible flags for register GPIO_CTRL */ |
283 | #define RT2860_GPIO_D_SHIFT 8 |
284 | #define RT2860_GPIO_O_SHIFT 0 |
285 | |
286 | /* possible flags for register USB_DMA_CFG */ |
287 | #define RT2860_USB_TX_BUSY (1U << 31) |
288 | #define RT2860_USB_RX_BUSY (1U << 30) |
289 | #define RT2860_USB_EPOUT_VLD_SHIFT 24 |
290 | #define RT2860_USB_TX_EN (1U << 23) |
291 | #define RT2860_USB_RX_EN (1U << 22) |
292 | #define RT2860_USB_RX_AGG_EN (1U << 21) |
293 | #define RT2860_USB_TXOP_HALT (1U << 20) |
294 | #define RT2860_USB_TX_CLEAR (1U << 19) |
295 | #define RT2860_USB_PHY_WD_EN (1U << 16) |
296 | #define RT2860_USB_PHY_MAN_RST (1U << 15) |
297 | #define RT2860_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */ |
298 | #define RT2860_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */ |
299 | |
300 | /* possible flags for register US_CYC_CNT */ |
301 | #define RT2860_TEST_EN (1U << 24) |
302 | #define RT2860_TEST_SEL_SHIFT 16 |
303 | #define RT2860_BT_MODE_EN (1U << 8) |
304 | #define RT2860_US_CYC_CNT_SHIFT 0 |
305 | |
306 | /* possible flags for register SYS_CTRL */ |
307 | #define RT2860_HST_PM_SEL (1U << 16) |
308 | #define RT2860_CAP_MODE (1U << 14) |
309 | #define RT2860_PME_OEN (1U << 13) |
310 | #define RT2860_CLKSELECT (1U << 12) |
311 | #define RT2860_PBF_CLK_EN (1U << 11) |
312 | #define RT2860_MAC_CLK_EN (1U << 10) |
313 | #define RT2860_DMA_CLK_EN (1U << 9) |
314 | #define RT2860_MCU_READY (1U << 7) |
315 | #define RT2860_ASY_RESET (1U << 4) |
316 | #define RT2860_PBF_RESET (1U << 3) |
317 | #define RT2860_MAC_RESET (1U << 2) |
318 | #define RT2860_DMA_RESET (1U << 1) |
319 | #define RT2860_MCU_RESET (1U << 0) |
320 | |
321 | /* possible values for register HOST_CMD */ |
322 | #define RT2860_MCU_CMD_SLEEP 0x30 |
323 | #define RT2860_MCU_CMD_WAKEUP 0x31 |
324 | #define RT2860_MCU_CMD_LEDS 0x50 |
325 | #define 0x51 |
326 | #define RT2860_MCU_CMD_LED1 0x52 |
327 | #define RT2860_MCU_CMD_LED2 0x53 |
328 | #define RT2860_MCU_CMD_LED3 0x54 |
329 | #define RT2860_MCU_CMD_RFRESET 0x72 |
330 | #define RT2860_MCU_CMD_ANTSEL 0x73 |
331 | #define RT2860_MCU_CMD_BBP 0x80 |
332 | #define RT2860_MCU_CMD_PSLEVEL 0x83 |
333 | |
334 | /* possible flags for register PBF_CFG */ |
335 | #define RT2860_TX1Q_NUM_SHIFT 21 |
336 | #define RT2860_TX2Q_NUM_SHIFT 16 |
337 | #define RT2860_NULL0_MODE (1U << 15) |
338 | #define RT2860_NULL1_MODE (1U << 14) |
339 | #define RT2860_RX_DROP_MODE (1U << 13) |
340 | #define RT2860_TX0Q_MANUAL (1U << 12) |
341 | #define RT2860_TX1Q_MANUAL (1U << 11) |
342 | #define RT2860_TX2Q_MANUAL (1U << 10) |
343 | #define RT2860_RX0Q_MANUAL (1U << 9) |
344 | #define RT2860_HCCA_EN (1U << 8) |
345 | #define RT2860_TX0Q_EN (1U << 4) |
346 | #define RT2860_TX1Q_EN (1U << 3) |
347 | #define RT2860_TX2Q_EN (1U << 2) |
348 | #define RT2860_RX0Q_EN (1U << 1) |
349 | |
350 | /* possible flags for register BUF_CTRL */ |
351 | #define RT2860_WRITE_TXQ(qid) (1U << (11 - (qid))) |
352 | #define RT2860_NULL0_KICK (1U << 7) |
353 | #define RT2860_NULL1_KICK (1U << 6) |
354 | #define RT2860_BUF_RESET (1U << 5) |
355 | #define RT2860_READ_TXQ(qid) (1U << (3 - (qid)) |
356 | #define RT2860_READ_RX0Q (1U << 0) |
357 | |
358 | /* possible flags for registers MCU_INT_STA/MCU_INT_ENA */ |
359 | #define RT2860_MCU_MAC_INT_8 (1U << 24) |
360 | #define RT2860_MCU_MAC_INT_7 (1U << 23) |
361 | #define RT2860_MCU_MAC_INT_6 (1U << 22) |
362 | #define RT2860_MCU_MAC_INT_4 (1U << 20) |
363 | #define RT2860_MCU_MAC_INT_3 (1U << 19) |
364 | #define RT2860_MCU_MAC_INT_2 (1U << 18) |
365 | #define RT2860_MCU_MAC_INT_1 (1U << 17) |
366 | #define RT2860_MCU_MAC_INT_0 (1U << 16) |
367 | #define RT2860_DTX0_INT (1U << 11) |
368 | #define RT2860_DTX1_INT (1U << 10) |
369 | #define RT2860_DTX2_INT (1U << 9) |
370 | #define RT2860_DRX0_INT (1U << 8) |
371 | #define RT2860_HCMD_INT (1U << 7) |
372 | #define RT2860_N0TX_INT (1U << 6) |
373 | #define RT2860_N1TX_INT (1U << 5) |
374 | #define RT2860_BCNTX_INT (1U << 4) |
375 | #define RT2860_MTX0_INT (1U << 3) |
376 | #define RT2860_MTX1_INT (1U << 2) |
377 | #define RT2860_MTX2_INT (1U << 1) |
378 | #define RT2860_MRX0_INT (1U << 0) |
379 | |
380 | /* possible flags for register TXRXQ_PCNT */ |
381 | #define RT2860_RX0Q_PCNT_MASK 0xff000000 |
382 | #define RT2860_TX2Q_PCNT_MASK 0x00ff0000 |
383 | #define RT2860_TX1Q_PCNT_MASK 0x0000ff00 |
384 | #define RT2860_TX0Q_PCNT_MASK 0x000000ff |
385 | |
386 | /* possible flags for register CAP_CTRL */ |
387 | #define RT2860_CAP_ADC_FEQ (1U << 31) |
388 | #define RT2860_CAP_START (1U << 30) |
389 | #define RT2860_MAN_TRIG (1U << 29) |
390 | #define RT2860_TRIG_OFFSET_SHIFT 16 |
391 | #define RT2860_START_ADDR_SHIFT 0 |
392 | |
393 | /* possible flags for register RF_CSR_CFG */ |
394 | #define RT3070_RF_KICK (1U << 17) |
395 | #define RT3070_RF_WRITE (1U << 16) |
396 | |
397 | /* possible flags for register EFUSE_CTRL */ |
398 | #define RT3070_SEL_EFUSE (1U << 31) |
399 | #define RT3070_EFSROM_KICK (1U << 30) |
400 | #define RT3070_EFSROM_AIN_MASK 0x03ff0000 |
401 | #define RT3070_EFSROM_AIN_SHIFT 16 |
402 | #define RT3070_EFSROM_MODE_MASK 0x000000c0 |
403 | #define RT3070_EFUSE_AOUT_MASK 0x0000003f |
404 | |
405 | /* possible flag for register DEBUG_INDEX */ |
406 | #define RT5592_SEL_XTAL (1U << 31) |
407 | |
408 | /* possible flags for register MAC_SYS_CTRL */ |
409 | #define RT2860_RX_TS_EN (1U << 7) |
410 | #define RT2860_WLAN_HALT_EN (1U << 6) |
411 | #define RT2860_PBF_LOOP_EN (1U << 5) |
412 | #define RT2860_CONT_TX_TEST (1U << 4) |
413 | #define RT2860_MAC_RX_EN (1U << 3) |
414 | #define RT2860_MAC_TX_EN (1U << 2) |
415 | #define RT2860_BBP_HRST (1U << 1) |
416 | #define RT2860_MAC_SRST (1U << 0) |
417 | |
418 | /* possible flags for register MAC_BSSID_DW1 */ |
419 | #define RT2860_MULTI_BCN_NUM_SHIFT 18 |
420 | #define RT2860_MULTI_BSSID_MODE_SHIFT 16 |
421 | |
422 | /* possible flags for register MAX_LEN_CFG */ |
423 | #define RT2860_MIN_MPDU_LEN_SHIFT 16 |
424 | #define RT2860_MAX_PSDU_LEN_SHIFT 12 |
425 | #define RT2860_MAX_PSDU_LEN8K 0 |
426 | #define RT2860_MAX_PSDU_LEN16K 1 |
427 | #define RT2860_MAX_PSDU_LEN32K 2 |
428 | #define RT2860_MAX_PSDU_LEN64K 3 |
429 | #define RT2860_MAX_MPDU_LEN_SHIFT 0 |
430 | |
431 | /* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */ |
432 | #define RT2860_BBP_RW_PARALLEL (1U << 19) |
433 | #define RT2860_BBP_PAR_DUR_112_5 (1U << 18) |
434 | #define RT2860_BBP_CSR_KICK (1U << 17) |
435 | #define RT2860_BBP_CSR_READ (1U << 16) |
436 | #define RT2860_BBP_ADDR_SHIFT 8 |
437 | #define RT2860_BBP_DATA_SHIFT 0 |
438 | |
439 | /* possible flags for register RF_CSR_CFG0 */ |
440 | #define RT2860_RF_REG_CTRL (1U << 31) |
441 | #define RT2860_RF_LE_SEL1 (1U << 30) |
442 | #define RT2860_RF_LE_STBY (1U << 29) |
443 | #define RT2860_RF_REG_WIDTH_SHIFT 24 |
444 | #define RT2860_RF_REG_0_SHIFT 0 |
445 | |
446 | /* possible flags for register RF_CSR_CFG1 */ |
447 | #define RT2860_RF_DUR_5 (1U << 24) |
448 | #define RT2860_RF_REG_1_SHIFT 0 |
449 | |
450 | /* possible flags for register LED_CFG */ |
451 | #define RT2860_LED_POL (1U << 30) |
452 | #define RT2860_Y_LED_MODE_SHIFT 28 |
453 | #define RT2860_G_LED_MODE_SHIFT 26 |
454 | #define RT2860_R_LED_MODE_SHIFT 24 |
455 | #define RT2860_LED_MODE_OFF 0 |
456 | #define RT2860_LED_MODE_BLINK_TX 1 |
457 | #define RT2860_LED_MODE_SLOW_BLINK 2 |
458 | #define RT2860_LED_MODE_ON 3 |
459 | #define RT2860_SLOW_BLK_TIME_SHIFT 16 |
460 | #define RT2860_LED_OFF_TIME_SHIFT 8 |
461 | #define RT2860_LED_ON_TIME_SHIFT 0 |
462 | |
463 | /* possible flags for register XIFS_TIME_CFG */ |
464 | #define RT2860_BB_RXEND_EN (1U << 29) |
465 | #define RT2860_EIFS_TIME_SHIFT 20 |
466 | #define RT2860_OFDM_XIFS_TIME_SHIFT 16 |
467 | #define RT2860_OFDM_SIFS_TIME_SHIFT 8 |
468 | #define RT2860_CCK_SIFS_TIME_SHIFT 0 |
469 | |
470 | /* possible flags for register BKOFF_SLOT_CFG */ |
471 | #define RT2860_CC_DELAY_TIME_SHIFT 8 |
472 | #define RT2860_SLOT_TIME 0 |
473 | |
474 | /* possible flags for register NAV_TIME_CFG */ |
475 | #define RT2860_NAV_UPD (1U << 31) |
476 | #define RT2860_NAV_UPD_VAL_SHIFT 16 |
477 | #define RT2860_NAV_CLR_EN (1U << 15) |
478 | #define RT2860_NAV_TIMER_SHIFT 0 |
479 | |
480 | /* possible flags for register CH_TIME_CFG */ |
481 | #define RT2860_EIFS_AS_CH_BUSY (1U << 4) |
482 | #define RT2860_NAV_AS_CH_BUSY (1U << 3) |
483 | #define RT2860_RX_AS_CH_BUSY (1U << 2) |
484 | #define RT2860_TX_AS_CH_BUSY (1U << 1) |
485 | #define RT2860_CH_STA_TIMER_EN (1U << 0) |
486 | |
487 | /* possible values for register BCN_TIME_CFG */ |
488 | #define RT2860_TSF_INS_COMP_SHIFT 24 |
489 | #define RT2860_BCN_TX_EN (1U << 20) |
490 | #define RT2860_TBTT_TIMER_EN (1U << 19) |
491 | #define RT2860_TSF_SYNC_MODE_SHIFT 17 |
492 | #define RT2860_TSF_SYNC_MODE_DIS 0 |
493 | #define RT2860_TSF_SYNC_MODE_STA 1 |
494 | #define RT2860_TSF_SYNC_MODE_IBSS 2 |
495 | #define RT2860_TSF_SYNC_MODE_HOSTAP 3 |
496 | #define RT2860_TSF_TIMER_EN (1U << 16) |
497 | #define RT2860_BCN_INTVAL_SHIFT 0 |
498 | |
499 | /* possible flags for register TBTT_SYNC_CFG */ |
500 | #define RT2860_BCN_CWMIN_SHIFT 20 |
501 | #define RT2860_BCN_AIFSN_SHIFT 16 |
502 | #define RT2860_BCN_EXP_WIN_SHIFT 8 |
503 | #define RT2860_TBTT_ADJUST_SHIFT 0 |
504 | |
505 | /* possible flags for register INT_TIMER_CFG */ |
506 | #define RT2860_GP_TIMER_SHIFT 16 |
507 | #define RT2860_PRE_TBTT_TIMER_SHIFT 0 |
508 | |
509 | /* possible flags for register INT_TIMER_EN */ |
510 | #define RT2860_GP_TIMER_EN (1U << 1) |
511 | #define RT2860_PRE_TBTT_INT_EN (1U << 0) |
512 | |
513 | /* possible flags for register MAC_STATUS_REG */ |
514 | #define RT2860_RX_STATUS_BUSY (1U << 1) |
515 | #define RT2860_TX_STATUS_BUSY (1U << 0) |
516 | |
517 | /* possible flags for register PWR_PIN_CFG */ |
518 | #define RT2860_IO_ADDA_PD (1U << 3) |
519 | #define RT2860_IO_PLL_PD (1U << 2) |
520 | #define RT2860_IO_RA_PE (1U << 1) |
521 | #define RT2860_IO_RF_PE (1U << 0) |
522 | |
523 | /* possible flags for register AUTO_WAKEUP_CFG */ |
524 | #define RT2860_AUTO_WAKEUP_EN (1U << 15) |
525 | #define RT2860_SLEEP_TBTT_NUM_SHIFT 8 |
526 | #define RT2860_WAKEUP_LEAD_TIME_SHIFT 0 |
527 | |
528 | /* possible flags for register TX_PIN_CFG */ |
529 | #define RT3593_LNA_PE_G2_POL (1U << 31) |
530 | #define RT3593_LNA_PE_A2_POL (1U << 30) |
531 | #define RT3593_LNA_PE_G2_EN (1U << 29) |
532 | #define RT3593_LNA_PE_A2_EN (1U << 28) |
533 | #define RT3593_LNA_PE2_EN (RT3593_LNA_PE_A2_EN | RT3593_LNA_PE_G2_EN) |
534 | #define RT3593_PA_PE_G2_POL (1U << 27) |
535 | #define RT3593_PA_PE_A2_POL (1U << 26) |
536 | #define RT3593_PA_PE_G2_EN (1U << 25) |
537 | #define RT3593_PA_PE_A2_EN (1U << 24) |
538 | #define RT2860_TRSW_POL (1U << 19) |
539 | #define RT2860_TRSW_EN (1U << 18) |
540 | #define RT2860_RFTR_POL (1U << 17) |
541 | #define RT2860_RFTR_EN (1U << 16) |
542 | #define RT2860_LNA_PE_G1_POL (1U << 15) |
543 | #define RT2860_LNA_PE_A1_POL (1U << 14) |
544 | #define RT2860_LNA_PE_G0_POL (1U << 13) |
545 | #define RT2860_LNA_PE_A0_POL (1U << 12) |
546 | #define RT2860_LNA_PE_G1_EN (1U << 11) |
547 | #define RT2860_LNA_PE_A1_EN (1U << 10) |
548 | #define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN) |
549 | #define RT2860_LNA_PE_G0_EN (1U << 9) |
550 | #define RT2860_LNA_PE_A0_EN (1U << 8) |
551 | #define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN) |
552 | #define RT2860_PA_PE_G1_POL (1U << 7) |
553 | #define RT2860_PA_PE_A1_POL (1U << 6) |
554 | #define RT2860_PA_PE_G0_POL (1U << 5) |
555 | #define RT2860_PA_PE_A0_POL (1U << 4) |
556 | #define RT2860_PA_PE_G1_EN (1U << 3) |
557 | #define RT2860_PA_PE_A1_EN (1U << 2) |
558 | #define RT2860_PA_PE_G0_EN (1U << 1) |
559 | #define RT2860_PA_PE_A0_EN (1U << 0) |
560 | |
561 | /* possible flags for register TX_BAND_CFG */ |
562 | #define RT2860_5G_BAND_SEL_N (1U << 2) |
563 | #define RT2860_5G_BAND_SEL_P (1U << 1) |
564 | #define RT2860_TX_BAND_SEL (1U << 0) |
565 | |
566 | /* possible flags for register TX_SW_CFG0 */ |
567 | #define RT2860_DLY_RFTR_EN_SHIFT 24 |
568 | #define RT2860_DLY_TRSW_EN_SHIFT 16 |
569 | #define RT2860_DLY_PAPE_EN_SHIFT 8 |
570 | #define RT2860_DLY_TXPE_EN_SHIFT 0 |
571 | |
572 | /* possible flags for register TX_SW_CFG1 */ |
573 | #define RT2860_DLY_RFTR_DIS_SHIFT 16 |
574 | #define RT2860_DLY_TRSW_DIS_SHIFT 8 |
575 | #define RT2860_DLY_PAPE_DIS SHIFT 0 |
576 | |
577 | /* possible flags for register TX_SW_CFG2 */ |
578 | #define RT2860_DLY_LNA_EN_SHIFT 24 |
579 | #define RT2860_DLY_LNA_DIS_SHIFT 16 |
580 | #define RT2860_DLY_DAC_EN_SHIFT 8 |
581 | #define RT2860_DLY_DAC_DIS_SHIFT 0 |
582 | |
583 | /* possible flags for register TXOP_THRES_CFG */ |
584 | #define RT2860_TXOP_REM_THRES_SHIFT 24 |
585 | #define RT2860_CF_END_THRES_SHIFT 16 |
586 | #define RT2860_RDG_IN_THRES 8 |
587 | #define RT2860_RDG_OUT_THRES 0 |
588 | |
589 | /* possible flags for register TXOP_CTRL_CFG */ |
590 | #define RT2860_EXT_CW_MIN_SHIFT 16 |
591 | #define RT2860_EXT_CCA_DLY_SHIFT 8 |
592 | #define RT2860_EXT_CCA_EN (1U << 7) |
593 | #define RT2860_LSIG_TXOP_EN (1U << 6) |
594 | #define RT2860_TXOP_TRUN_EN_MIMOPS (1U << 4) |
595 | #define RT2860_TXOP_TRUN_EN_TXOP (1U << 3) |
596 | #define RT2860_TXOP_TRUN_EN_RATE (1U << 2) |
597 | #define RT2860_TXOP_TRUN_EN_AC (1U << 1) |
598 | #define RT2860_TXOP_TRUN_EN_TIMEOUT (1U << 0) |
599 | |
600 | /* possible flags for register TX_RTS_CFG */ |
601 | #define RT2860_RTS_FBK_EN (1U << 24) |
602 | #define RT2860_RTS_THRES_SHIFT 8 |
603 | #define RT2860_RTS_RTY_LIMIT_SHIFT 0 |
604 | |
605 | /* possible flags for register TX_TIMEOUT_CFG */ |
606 | #define RT2860_TXOP_TIMEOUT_SHIFT 16 |
607 | #define RT2860_RX_ACK_TIMEOUT_SHIFT 8 |
608 | #define RT2860_MPDU_LIFE_TIME_SHIFT 4 |
609 | |
610 | /* possible flags for register TX_RTY_CFG */ |
611 | #define RT2860_TX_AUTOFB_EN (1U << 30) |
612 | #define RT2860_AGG_RTY_MODE_TIMER (1U << 29) |
613 | #define RT2860_NAG_RTY_MODE_TIMER (1U << 28) |
614 | #define RT2860_LONG_RTY_THRES_SHIFT 16 |
615 | #define RT2860_LONG_RTY_LIMIT_SHIFT 8 |
616 | #define RT2860_SHORT_RTY_LIMIT_SHIFT 0 |
617 | |
618 | /* possible flags for register TX_LINK_CFG */ |
619 | #define RT2860_REMOTE_MFS_SHIFT 24 |
620 | #define RT2860_REMOTE_MFB_SHIFT 16 |
621 | #define RT2860_TX_CFACK_EN (1U << 12) |
622 | #define RT2860_TX_RDG_EN (1U << 11) |
623 | #define RT2860_TX_MRQ_EN (1U << 10) |
624 | #define RT2860_REMOTE_UMFS_EN (1U << 9) |
625 | #define RT2860_TX_MFB_EN (1U << 8) |
626 | #define RT2860_REMOTE_MFB_LT_SHIFT 0 |
627 | |
628 | /* possible flags for registers *_PROT_CFG */ |
629 | #define RT2860_RTSTH_EN (1U << 26) |
630 | #define RT2860_TXOP_ALLOW_GF40 (1U << 25) |
631 | #define RT2860_TXOP_ALLOW_GF20 (1U << 24) |
632 | #define RT2860_TXOP_ALLOW_MM40 (1U << 23) |
633 | #define RT2860_TXOP_ALLOW_MM20 (1U << 22) |
634 | #define RT2860_TXOP_ALLOW_OFDM (1U << 21) |
635 | #define RT2860_TXOP_ALLOW_CCK (1U << 20) |
636 | #define RT2860_TXOP_ALLOW_ALL (0x3f << 20) |
637 | #define RT2860_PROT_NAV_SHORT (1U << 18) |
638 | #define RT2860_PROT_NAV_LONG (2 << 18) |
639 | #define RT2860_PROT_CTRL_RTS_CTS (1U << 16) |
640 | #define RT2860_PROT_CTRL_CTS (2 << 16) |
641 | |
642 | /* possible flags for registers EXP_{CTS,ACK}_TIME */ |
643 | #define RT2860_EXP_OFDM_TIME_SHIFT 16 |
644 | #define RT2860_EXP_CCK_TIME_SHIFT 0 |
645 | |
646 | /* possible flags for register RX_FILTR_CFG */ |
647 | #define RT2860_DROP_CTRL_RSV (1U << 16) |
648 | #define RT2860_DROP_BAR (1U << 15) |
649 | #define RT2860_DROP_BA (1U << 14) |
650 | #define RT2860_DROP_PSPOLL (1U << 13) |
651 | #define RT2860_DROP_RTS (1U << 12) |
652 | #define RT2860_DROP_CTS (1U << 11) |
653 | #define RT2860_DROP_ACK (1U << 10) |
654 | #define RT2860_DROP_CFEND (1U << 9) |
655 | #define RT2860_DROP_CFACK (1U << 8) |
656 | #define RT2860_DROP_DUPL (1U << 7) |
657 | #define RT2860_DROP_BC (1U << 6) |
658 | #define RT2860_DROP_MC (1U << 5) |
659 | #define RT2860_DROP_VER_ERR (1U << 4) |
660 | #define RT2860_DROP_NOT_MYBSS (1U << 3) |
661 | #define RT2860_DROP_UC_NOME (1U << 2) |
662 | #define RT2860_DROP_PHY_ERR (1U << 1) |
663 | #define RT2860_DROP_CRC_ERR (1U << 0) |
664 | |
665 | /* possible flags for register AUTO_RSP_CFG */ |
666 | #define RT2860_CTRL_PWR_BIT (1U << 7) |
667 | #define RT2860_BAC_ACK_POLICY (1U << 6) |
668 | #define RT2860_CCK_SHORT_EN (1U << 4) |
669 | #define RT2860_CTS_40M_REF_EN (1U << 3) |
670 | #define RT2860_CTS_40M_MODE_EN (1U << 2) |
671 | #define RT2860_BAC_ACKPOLICY_EN (1U << 1) |
672 | #define RT2860_AUTO_RSP_EN (1U << 0) |
673 | |
674 | /* possible flags for register SIFS_COST_CFG */ |
675 | #define RT2860_OFDM_SIFS_COST_SHIFT 8 |
676 | #define RT2860_CCK_SIFS_COST_SHIFT 0 |
677 | |
678 | /* possible flags for register TXOP_HLDR_ET */ |
679 | #define RT2860_TXOP_ETM1_EN (1U << 25) |
680 | #define RT2860_TXOP_ETM0_EN (1U << 24) |
681 | #define RT2860_TXOP_ETM_THRES_SHIFT 16 |
682 | #define RT2860_TXOP_ETO_EN (1U << 8) |
683 | #define RT2860_TXOP_ETO_THRES_SHIFT 1 |
684 | #define RT2860_PER_RX_RST_EN (1U << 0) |
685 | |
686 | /* possible flags for register TX_STAT_FIFO */ |
687 | #define RT2860_TXQ_MCS_SHIFT 16 |
688 | #define RT2860_TXQ_WCID_SHIFT 8 |
689 | #define RT2860_TXQ_ACKREQ (1U << 7) |
690 | #define RT2860_TXQ_AGG (1U << 6) |
691 | #define RT2860_TXQ_OK (1U << 5) |
692 | #define RT2860_TXQ_PID_SHIFT 1 |
693 | #define RT2860_TXQ_VLD (1U << 0) |
694 | |
695 | /* possible flags for register WCID_ATTR */ |
696 | #define RT2860_MODE_NOSEC 0 |
697 | #define RT2860_MODE_WEP40 1 |
698 | #define RT2860_MODE_WEP104 2 |
699 | #define RT2860_MODE_TKIP 3 |
700 | #define RT2860_MODE_AES_CCMP 4 |
701 | #define RT2860_MODE_CKIP40 5 |
702 | #define RT2860_MODE_CKIP104 6 |
703 | #define RT2860_MODE_CKIP128 7 |
704 | #define RT2860_RX_PKEY_EN (1U << 0) |
705 | |
706 | /* possible flags for register H2M_MAILBOX */ |
707 | #define RT2860_H2M_BUSY (1U << 24) |
708 | #define RT2860_TOKEN_NO_INTR 0xff |
709 | |
710 | |
711 | /* possible flags for MCU command RT2860_MCU_CMD_LEDS */ |
712 | #define RT2860_LED_RADIO (1U << 13) |
713 | #define RT2860_LED_LINK_2GHZ (1U << 14) |
714 | #define RT2860_LED_LINK_5GHZ (1U << 15) |
715 | |
716 | |
717 | /* possible flags for RT3020 RF register 1 */ |
718 | #define RT3070_RF_BLOCK (1U << 0) |
719 | #define RT3070_PLL_PD (1U << 1) |
720 | #define RT3070_RX0_PD (1U << 2) |
721 | #define RT3070_TX0_PD (1U << 3) |
722 | #define RT3070_RX1_PD (1U << 4) |
723 | #define RT3070_TX1_PD (1U << 5) |
724 | #define RT3070_RX2_PD (1U << 6) |
725 | #define RT3070_TX2_PD (1U << 7) |
726 | |
727 | /* possible flags for RT3020 RF register 7 */ |
728 | #define RT3070_TUNE (1U << 0) |
729 | |
730 | /* possible flags for RT3020 RF register 15 */ |
731 | #define RT3070_TX_LO2 (1U << 3) |
732 | |
733 | /* possible flags for RT3020 RF register 17 */ |
734 | #define RT3070_TX_LO1 (1U << 3) |
735 | |
736 | /* possible flags for RT3020 RF register 20 */ |
737 | #define RT3070_RX_LO1 (1U << 3) |
738 | |
739 | /* possible flags for RT3020 RF register 21 */ |
740 | #define RT3070_RX_LO2 (1U << 3) |
741 | #define RT3070_RX_CTB (1U << 7) |
742 | |
743 | /* possible flags for RT3020 RF register 22 */ |
744 | #define RT3070_BB_LOOPBACK (1U << 0) |
745 | |
746 | /* possible flags for RT3053 RF register 1 */ |
747 | #define RT3593_VCO (1U << 0) |
748 | |
749 | /* possible flags for RT3053 RF register 2 */ |
750 | #define RT3593_RESCAL (1U << 7) |
751 | |
752 | /* possible flags for RT3053 RF register 3 */ |
753 | #define RT3593_VCOCAL (1U << 7) |
754 | |
755 | /* possible flags for RT3053 RF register 6 */ |
756 | #define RT3593_VCO_IC (1U << 6) |
757 | |
758 | /* possible flags for RT3053 RF register 18 */ |
759 | #define RT3593_AUTOTUNE_BYPASS (1U << 6) |
760 | |
761 | /* possible flags for RT3053 RF register 20 */ |
762 | #define RT3593_LDO_PLL_VC_MASK 0x0e |
763 | #define RT3593_LDO_RF_VC_MASK 0xe0 |
764 | |
765 | /* possible flags for RT3053 RF register 22 */ |
766 | #define RT3593_CP_IC_MASK 0xe0 |
767 | #define RT3593_CP_IC_SHIFT 5 |
768 | |
769 | /* possible flags for RT3053 RF register 46 */ |
770 | #define RT3593_RX_CTB (1U << 5) |
771 | |
772 | #define RT3090_DEF_LNA 10 |
773 | |
774 | /* possible flags for RT5390 RF register 38. */ |
775 | #define RT5390_RX_LO1 (1U << 5) |
776 | |
777 | /* possible flags for RT5390 RF register 39. */ |
778 | #define RT5390_RX_LO2 (1U << 7) |
779 | |
780 | /* possible flags for RT5390 RF register 42 */ |
781 | #define RT5390_RX_CTB (1U << 6) |
782 | |
783 | /* possible flags for RT3053 RF register 46 */ |
784 | #define RT3593_RX_CTB (1U << 5) |
785 | |
786 | /* possible flags for RT3053 RF register 50 */ |
787 | #define RT3593_TX_LO2 (1U << 4) |
788 | |
789 | /* possible flags for RT3053 RF register 51 */ |
790 | #define RT3593_TX_LO1 (1U << 4) |
791 | |
792 | /* Possible flags for RT5390 RF register 2. */ |
793 | #define RT5390_RESCAL (1 << 7) |
794 | |
795 | /* Possible flags for RT5390 RF register 3. */ |
796 | #define RT5390_VCOCAL (1 << 7) |
797 | |
798 | /* Possible flags for RT5390 BBP register 4. */ |
799 | #define RT5390_MAC_IF_CTRL (1U << 6) |
800 | |
801 | /* possible flags for RT5390 BBP register 105. */ |
802 | #define RT5390_MLD (1U << 2) |
803 | #define RT5390_EN_SIG_MODULATION (1U << 3) |
804 | |
805 | #define RT3090_DEF_LNA 10 |
806 | |
807 | /* RT2860 TX descriptor */ |
808 | struct rt2860_txd { |
809 | uint32_t sdp0; /* Segment Data Pointer 0 */ |
810 | uint16_t sdl1; /* Segment Data Length 1 */ |
811 | #define RT2860_TX_BURST (1U << 15) |
812 | #define RT2860_TX_LS1 (1U << 14) /* SDP1 is the last segment */ |
813 | |
814 | uint16_t sdl0; /* Segment Data Length 0 */ |
815 | #define RT2860_TX_DDONE (1U << 15) |
816 | #define RT2860_TX_LS0 (1U << 14) /* SDP0 is the last segment */ |
817 | |
818 | uint32_t sdp1; /* Segment Data Pointer 1 */ |
819 | uint8_t reserved[3]; |
820 | uint8_t flags; |
821 | #define RT2860_TX_QSEL_SHIFT 1 |
822 | #define RT2860_TX_QSEL_MGMT (0 << 1) |
823 | #define RT2860_TX_QSEL_HCCA (1U << 1) |
824 | #define RT2860_TX_QSEL_EDCA (2 << 1) |
825 | #define RT2860_TX_WIV (1U << 0) |
826 | } __packed; |
827 | |
828 | /* RT2870 TX descriptor */ |
829 | struct rt2870_txd { |
830 | uint16_t len; |
831 | uint8_t pad; |
832 | uint8_t flags; |
833 | } __packed; |
834 | |
835 | /* TX Wireless Information */ |
836 | struct rt2860_txwi { |
837 | uint8_t flags; |
838 | #define RT2860_TX_MPDU_DSITY_SHIFT 5 |
839 | #define RT2860_TX_AMPDU (1U << 4) |
840 | #define RT2860_TX_TS (1U << 3) |
841 | #define RT2860_TX_CFACK (1U << 2) |
842 | #define RT2860_TX_MMPS (1U << 1) |
843 | #define RT2860_TX_FRAG (1U << 0) |
844 | |
845 | uint8_t txop; |
846 | #define RT2860_TX_TXOP_HT 0 |
847 | #define RT2860_TX_TXOP_PIFS 1 |
848 | #define RT2860_TX_TXOP_SIFS 2 |
849 | #define RT2860_TX_TXOP_BACKOFF 3 |
850 | |
851 | uint16_t phy; |
852 | #define RT2860_PHY_MODE 0xc000 |
853 | #define RT2860_PHY_CCK (0 << 14) |
854 | #define RT2860_PHY_OFDM (1U << 14) |
855 | #define RT2860_PHY_HT (2 << 14) |
856 | #define RT2860_PHY_HT_GF (3 << 14) |
857 | #define RT2860_PHY_SGI (1U << 8) |
858 | #define RT2860_PHY_BW40 (1U << 7) |
859 | #define RT2860_PHY_MCS 0x7f |
860 | #define RT2860_PHY_SHPRE (1U << 3) |
861 | |
862 | uint8_t xflags; |
863 | #define RT2860_TX_BAWINSIZE_SHIFT 2 |
864 | #define RT2860_TX_NSEQ (1U << 1) |
865 | #define RT2860_TX_ACK (1U << 0) |
866 | |
867 | uint8_t wcid; /* Wireless Client ID */ |
868 | uint16_t len; |
869 | #define RT2860_TX_PID_SHIFT 12 |
870 | |
871 | uint32_t iv; |
872 | uint32_t eiv; |
873 | } __packed; |
874 | |
875 | /* RT2860 RX descriptor */ |
876 | struct rt2860_rxd { |
877 | uint32_t sdp0; |
878 | uint16_t sdl1; /* unused */ |
879 | uint16_t sdl0; |
880 | #define RT2860_RX_DDONE (1U << 15) |
881 | #define RT2860_RX_LS0 (1U << 14) |
882 | |
883 | uint32_t sdp1; /* unused */ |
884 | uint32_t flags; |
885 | #define RT2860_RX_DEC (1U << 16) |
886 | #define RT2860_RX_AMPDU (1U << 15) |
887 | #define RT2860_RX_L2PAD (1U << 14) |
888 | #define (1U << 13) |
889 | #define RT2860_RX_HTC (1U << 12) |
890 | #define RT2860_RX_AMSDU (1U << 11) |
891 | #define RT2860_RX_MICERR (1U << 10) |
892 | #define RT2860_RX_ICVERR (1U << 9) |
893 | #define RT2860_RX_CRCERR (1U << 8) |
894 | #define RT2860_RX_MYBSS (1U << 7) |
895 | #define RT2860_RX_BC (1U << 6) |
896 | #define RT2860_RX_MC (1U << 5) |
897 | #define RT2860_RX_UC2ME (1U << 4) |
898 | #define RT2860_RX_FRAG (1U << 3) |
899 | #define RT2860_RX_NULL (1U << 2) |
900 | #define RT2860_RX_DATA (1U << 1) |
901 | #define RT2860_RX_BA (1U << 0) |
902 | } __packed; |
903 | |
904 | /* RT2870 RX descriptor */ |
905 | struct rt2870_rxd { |
906 | /* single 32-bit field */ |
907 | uint32_t flags; |
908 | } __packed; |
909 | |
910 | /* RX Wireless Information */ |
911 | struct rt2860_rxwi { |
912 | uint8_t wcid; |
913 | uint8_t keyidx; |
914 | #define RT2860_RX_UDF_SHIFT 5 |
915 | #define RT2860_RX_BSS_IDX_SHIFT 2 |
916 | |
917 | uint16_t len; |
918 | #define RT2860_RX_TID_SHIFT 12 |
919 | |
920 | uint16_t seq; |
921 | uint16_t phy; |
922 | uint8_t [3]; |
923 | uint8_t reserved1; |
924 | uint8_t snr[2]; |
925 | uint16_t reserved2; |
926 | } __packed; |
927 | |
928 | |
929 | /* first DMA segment contains TXWI + 802.11 header + 32-bit padding */ |
930 | #define RT2860_TXWI_DMASZ \ |
931 | (sizeof (struct rt2860_txwi) + \ |
932 | sizeof (struct ieee80211_htframe) + \ |
933 | sizeof (uint16_t)) |
934 | |
935 | #define RT2860_RF1 0 |
936 | #define RT2860_RF2 2 |
937 | #define RT2860_RF3 1 |
938 | #define RT2860_RF4 3 |
939 | |
940 | #define RT2860_RF_2820 0x0001 /* 2T3R */ |
941 | #define RT2860_RF_2850 0x0002 /* dual-band 2T3R */ |
942 | #define RT2860_RF_2720 0x0003 /* 1T2R */ |
943 | #define RT2860_RF_2750 0x0004 /* dual-band 1T2R */ |
944 | #define RT3070_RF_3020 0x0005 /* 1T1R */ |
945 | #define RT3070_RF_2020 0x0006 /* b/g */ |
946 | #define RT3070_RF_3021 0x0007 /* 1T2R */ |
947 | #define RT3070_RF_3022 0x0008 /* 2T2R */ |
948 | #define RT3070_RF_3052 0x0009 /* dual-band 2T2R */ |
949 | #define RT3070_RF_3320 0x000b /* 1T1R */ |
950 | #define RT3070_RF_3053 0x000d /* dual-band 3T3R */ |
951 | #define RT5592_RF_5592 0x000f /* dual-band 2T2R */ |
952 | #define RT5390_RF_5360 0x5360 /* 1T1R */ |
953 | #define RT5390_RF_5370 0x5370 /* 1T1R */ |
954 | #define RT5390_RF_5372 0x5372 /* 2T2R */ |
955 | #define RT5390_RF_5390 0x5390 /* 1T1R */ |
956 | #define RT5390_RF_5392 0x5392 /* 2T2R */ |
957 | |
958 | /* USB commands for RT2870 only */ |
959 | #define RT2870_RESET 1 |
960 | #define RT2870_WRITE_2 2 |
961 | #define RT2870_WRITE_REGION_1 6 |
962 | #define RT2870_READ_REGION_1 7 |
963 | #define RT2870_EEPROM_READ 9 |
964 | |
965 | #define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ |
966 | |
967 | #define RT2860_EEPROM_CHIPID 0x00 |
968 | #define RT2860_EEPROM_VERSION 0x01 |
969 | #define RT2860_EEPROM_MAC01 0x02 |
970 | #define RT2860_EEPROM_MAC23 0x03 |
971 | #define RT2860_EEPROM_MAC45 0x04 |
972 | #define RT2860_EEPROM_PCIE_PSLEVEL 0x11 |
973 | #define RT2860_EEPROM_REV 0x12 |
974 | #define RT2860_EEPROM_ANTENNA 0x1a |
975 | #define RT2860_EEPROM_CONFIG 0x1b |
976 | #define RT2860_EEPROM_COUNTRY 0x1c |
977 | #define RT2860_EEPROM_FREQ_LEDS 0x1d |
978 | #define RT2860_EEPROM_LED1 0x1e |
979 | #define RT2860_EEPROM_LED2 0x1f |
980 | #define RT2860_EEPROM_LED3 0x20 |
981 | #define RT2860_EEPROM_LNA 0x22 |
982 | #define 0x23 |
983 | #define 0x24 |
984 | #define 0x25 |
985 | #define 0x26 |
986 | #define RT2860_EEPROM_DELTAPWR 0x28 |
987 | #define RT2860_EEPROM_PWR2GHZ_BASE1 0x29 |
988 | #define RT2860_EEPROM_PWR2GHZ_BASE2 0x30 |
989 | #define RT2860_EEPROM_TSSI1_2GHZ 0x37 |
990 | #define RT2860_EEPROM_TSSI2_2GHZ 0x38 |
991 | #define RT2860_EEPROM_TSSI3_2GHZ 0x39 |
992 | #define RT2860_EEPROM_TSSI4_2GHZ 0x3a |
993 | #define RT2860_EEPROM_TSSI5_2GHZ 0x3b |
994 | #define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c |
995 | #define RT2860_EEPROM_PWR5GHZ_BASE2 0x53 |
996 | #define RT2860_EEPROM_TSSI1_5GHZ 0x6a |
997 | #define RT2860_EEPROM_TSSI2_5GHZ 0x6b |
998 | #define RT2860_EEPROM_TSSI3_5GHZ 0x6c |
999 | #define RT2860_EEPROM_TSSI4_5GHZ 0x6d |
1000 | #define RT2860_EEPROM_TSSI5_5GHZ 0x6e |
1001 | #define RT2860_EEPROM_RPWR 0x6f |
1002 | #define RT2860_EEPROM_BBP_BASE 0x78 |
1003 | #define RT3071_EEPROM_RF_BASE 0x82 |
1004 | |
1005 | /* EEPROM registers for RT3593. */ |
1006 | #define RT3593_EEPROM_FREQ_LEDS 0x21 |
1007 | #define RT3593_EEPROM_FREQ 0x22 |
1008 | #define RT3593_EEPROM_LED1 0x22 |
1009 | #define RT3593_EEPROM_LED2 0x23 |
1010 | #define RT3593_EEPROM_LED3 0x24 |
1011 | #define RT3593_EEPROM_LNA 0x26 |
1012 | #define RT3593_EEPROM_LNA_5GHZ 0x27 |
1013 | #define 0x28 |
1014 | #define 0x29 |
1015 | #define 0x2a |
1016 | #define 0x2b |
1017 | #define RT3593_EEPROM_PWR2GHZ_BASE1 0x30 |
1018 | #define RT3593_EEPROM_PWR2GHZ_BASE2 0x37 |
1019 | #define RT3593_EEPROM_PWR2GHZ_BASE3 0x3e |
1020 | #define RT3593_EEPROM_PWR5GHZ_BASE1 0x4b |
1021 | #define RT3593_EEPROM_PWR5GHZ_BASE2 0x65 |
1022 | #define RT3593_EEPROM_PWR5GHZ_BASE3 0x7f |
1023 | |
1024 | /* |
1025 | * EEPROM IQ calibration. |
1026 | */ |
1027 | #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ 0x130 |
1028 | #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ 0x131 |
1029 | #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ 0x133 |
1030 | #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ 0x134 |
1031 | #define RT5390_EEPROM_RF_IQ_COMPENSATION_CTL 0x13c |
1032 | #define RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL 0x13d |
1033 | #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ 0x144 |
1034 | #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ 0x145 |
1035 | #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ 0x146 |
1036 | #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ 0x147 |
1037 | #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ 0x148 |
1038 | #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ 0x149 |
1039 | #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ 0x14a |
1040 | #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ 0x14b |
1041 | #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ 0x14c |
1042 | #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ 0x14d |
1043 | #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ 0x14e |
1044 | #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ 0x14f |
1045 | |
1046 | #define RT2860_RIDX_CCK1 0 |
1047 | #define RT2860_RIDX_CCK11 3 |
1048 | #define RT2860_RIDX_OFDM6 4 |
1049 | #define RT2860_RIDX_MAX 11 |
1050 | static const struct rt2860_rate { |
1051 | uint8_t rate; |
1052 | uint8_t mcs; |
1053 | enum ieee80211_phytype phy; |
1054 | uint8_t ctl_ridx; |
1055 | uint16_t sp_ack_dur; |
1056 | uint16_t lp_ack_dur; |
1057 | } rt2860_rates[] = { |
1058 | { 2, 0, IEEE80211_T_DS, 0, 314, 314 }, |
1059 | { 4, 1, IEEE80211_T_DS, 1, 258, 162 }, |
1060 | { 11, 2, IEEE80211_T_DS, 2, 223, 127 }, |
1061 | { 22, 3, IEEE80211_T_DS, 3, 213, 117 }, |
1062 | { 12, 0, IEEE80211_T_OFDM, 4, 60, 60 }, |
1063 | { 18, 1, IEEE80211_T_OFDM, 4, 52, 52 }, |
1064 | { 24, 2, IEEE80211_T_OFDM, 6, 48, 48 }, |
1065 | { 36, 3, IEEE80211_T_OFDM, 6, 44, 44 }, |
1066 | { 48, 4, IEEE80211_T_OFDM, 8, 44, 44 }, |
1067 | { 72, 5, IEEE80211_T_OFDM, 8, 40, 40 }, |
1068 | { 96, 6, IEEE80211_T_OFDM, 8, 40, 40 }, |
1069 | { 108, 7, IEEE80211_T_OFDM, 8, 40, 40 } |
1070 | }; |
1071 | |
1072 | /* |
1073 | * Control and status registers access macros. |
1074 | */ |
1075 | #define RAL_READ(sc, reg) \ |
1076 | bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) |
1077 | |
1078 | #define RAL_WRITE(sc, reg, val) \ |
1079 | bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) |
1080 | |
1081 | #define RAL_BARRIER_WRITE(sc) \ |
1082 | bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \ |
1083 | BUS_SPACE_BARRIER_WRITE) |
1084 | |
1085 | #define RAL_BARRIER_READ_WRITE(sc) \ |
1086 | bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \ |
1087 | BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) |
1088 | |
1089 | #define RAL_WRITE_REGION_1(sc, offset, datap, count) \ |
1090 | bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ |
1091 | (datap), (count)) |
1092 | |
1093 | #define RAL_SET_REGION_4(sc, offset, val, count) \ |
1094 | bus_space_set_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ |
1095 | (val), (count)) |
1096 | |
1097 | /* |
1098 | * EEPROM access macro. |
1099 | */ |
1100 | #define RT2860_EEPROM_CTL(sc, val) do { \ |
1101 | RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \ |
1102 | RAL_BARRIER_READ_WRITE((sc)); \ |
1103 | DELAY(RT2860_EEPROM_DELAY); \ |
1104 | } while (/* CONSTCOND */0) |
1105 | |
1106 | /* |
1107 | * Default values for MAC registers; values taken from the reference driver. |
1108 | */ |
1109 | #define RT2860_DEF_MAC \ |
1110 | { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ |
1111 | { RT2860_BCN_OFFSET1, 0x6f77d0c8 }, \ |
1112 | { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ |
1113 | { RT2860_HT_BASIC_RATE, 0x00008003 }, \ |
1114 | { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ |
1115 | { RT2860_RX_FILTR_CFG, 0x00017f97 }, \ |
1116 | { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ |
1117 | { RT2860_TX_SW_CFG0, 0x00000000 }, \ |
1118 | { RT2860_TX_SW_CFG1, 0x00080606 }, \ |
1119 | { RT2860_TX_LINK_CFG, 0x00001020 }, \ |
1120 | { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ |
1121 | { RT2860_MAX_LEN_CFG, 0x00001f00 }, \ |
1122 | { RT2860_LED_CFG, 0x7f031e46 }, \ |
1123 | { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ |
1124 | { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ |
1125 | { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ |
1126 | { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ |
1127 | { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ |
1128 | { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ |
1129 | { RT2860_CCK_PROT_CFG, 0x05740003 }, \ |
1130 | { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ |
1131 | { RT2860_GF20_PROT_CFG, 0x01744004 }, \ |
1132 | { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ |
1133 | { RT2860_MM20_PROT_CFG, 0x01744004 }, \ |
1134 | { RT2860_MM40_PROT_CFG, 0x03f54084 }, \ |
1135 | { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ |
1136 | { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ |
1137 | { RT2860_TX_RTS_CFG, 0x00092b20 }, \ |
1138 | { RT2860_EXP_ACK_TIME, 0x002400ca }, \ |
1139 | { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ |
1140 | { RT2860_PWR_PIN_CFG, 0x00000003 } |
1141 | |
1142 | /* XXX only a few registers differ from above, try to merge? */ |
1143 | #define RT2870_DEF_MAC \ |
1144 | { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ |
1145 | { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ |
1146 | { RT2860_HT_BASIC_RATE, 0x00008003 }, \ |
1147 | { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ |
1148 | { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ |
1149 | { RT2860_TX_SW_CFG0, 0x00000000 }, \ |
1150 | { RT2860_TX_SW_CFG1, 0x00080606 }, \ |
1151 | { RT2860_TX_LINK_CFG, 0x00001020 }, \ |
1152 | { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ |
1153 | { RT2860_LED_CFG, 0x7f031e46 }, \ |
1154 | { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ |
1155 | { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ |
1156 | { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ |
1157 | { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ |
1158 | { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ |
1159 | { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ |
1160 | { RT2860_CCK_PROT_CFG, 0x05740003 }, \ |
1161 | { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ |
1162 | { RT2860_PBF_CFG, 0x00f40006 }, \ |
1163 | { RT2860_WPDMA_GLO_CFG, 0x00000030 }, \ |
1164 | { RT2860_GF20_PROT_CFG, 0x01744004 }, \ |
1165 | { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ |
1166 | { RT2860_MM20_PROT_CFG, 0x01744004 }, \ |
1167 | { RT2860_MM40_PROT_CFG, 0x03f44084 }, \ |
1168 | { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ |
1169 | { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ |
1170 | { RT2860_TX_RTS_CFG, 0x00092b20 }, \ |
1171 | { RT2860_EXP_ACK_TIME, 0x002400ca }, \ |
1172 | { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ |
1173 | { RT2860_PWR_PIN_CFG, 0x00000003 } |
1174 | |
1175 | /* |
1176 | * Default values for BBP registers; values taken from the reference driver. |
1177 | */ |
1178 | #define RT2860_DEF_BBP \ |
1179 | { 65, 0x2c }, \ |
1180 | { 66, 0x38 }, \ |
1181 | { 68, 0x0b }, \ |
1182 | { 69, 0x12 }, \ |
1183 | { 70, 0x0a }, \ |
1184 | { 73, 0x10 }, \ |
1185 | { 81, 0x37 }, \ |
1186 | { 82, 0x62 }, \ |
1187 | { 83, 0x6a }, \ |
1188 | { 84, 0x99 }, \ |
1189 | { 86, 0x00 }, \ |
1190 | { 91, 0x04 }, \ |
1191 | { 92, 0x00 }, \ |
1192 | { 103, 0x00 }, \ |
1193 | { 105, 0x05 }, \ |
1194 | { 106, 0x35 } |
1195 | |
1196 | #define RT5390_DEF_BBP \ |
1197 | { 31, 0x08 }, \ |
1198 | { 65, 0x2c }, \ |
1199 | { 66, 0x38 }, \ |
1200 | { 68, 0x0b }, \ |
1201 | { 69, 0x0d }, \ |
1202 | { 70, 0x06 }, \ |
1203 | { 73, 0x13 }, \ |
1204 | { 75, 0x46 }, \ |
1205 | { 76, 0x28 }, \ |
1206 | { 77, 0x59 }, \ |
1207 | { 81, 0x37 }, \ |
1208 | { 82, 0x62 }, \ |
1209 | { 83, 0x7a }, \ |
1210 | { 84, 0x9a }, \ |
1211 | { 86, 0x38 }, \ |
1212 | { 91, 0x04 }, \ |
1213 | { 92, 0x02 }, \ |
1214 | { 103, 0xc0 }, \ |
1215 | { 104, 0x92 }, \ |
1216 | { 105, 0x3c }, \ |
1217 | { 106, 0x03 }, \ |
1218 | { 128, 0x12 } |
1219 | |
1220 | #define RT5592_DEF_BBP \ |
1221 | { 20, 0x06 }, \ |
1222 | { 31, 0x08 }, \ |
1223 | { 65, 0x2c }, \ |
1224 | { 66, 0x38 }, \ |
1225 | { 68, 0xdd }, \ |
1226 | { 69, 0x1a }, \ |
1227 | { 70, 0x05 }, \ |
1228 | { 73, 0x13 }, \ |
1229 | { 74, 0x0f }, \ |
1230 | { 75, 0x4f }, \ |
1231 | { 76, 0x28 }, \ |
1232 | { 77, 0x59 }, \ |
1233 | { 81, 0x37 }, \ |
1234 | { 82, 0x62 }, \ |
1235 | { 83, 0x6a }, \ |
1236 | { 84, 0x9a }, \ |
1237 | { 86, 0x38 }, \ |
1238 | { 88, 0x90 }, \ |
1239 | { 91, 0x04 }, \ |
1240 | { 92, 0x02 }, \ |
1241 | { 95, 0x9a }, \ |
1242 | { 98, 0x12 }, \ |
1243 | { 103, 0xc0 }, \ |
1244 | { 104, 0x92 }, \ |
1245 | { 105, 0x3c }, \ |
1246 | { 106, 0x35 }, \ |
1247 | { 128, 0x12 }, \ |
1248 | { 134, 0xd0 }, \ |
1249 | { 135, 0xf6 }, \ |
1250 | { 137, 0x0f } |
1251 | |
1252 | /* |
1253 | * Default settings for RF registers; values derived from the reference driver. |
1254 | */ |
1255 | #define RT2860_RF2850 \ |
1256 | { 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 }, \ |
1257 | { 2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 }, \ |
1258 | { 3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 }, \ |
1259 | { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 }, \ |
1260 | { 5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 }, \ |
1261 | { 6, 0x100bb3, 0x1301e3, 0x05a014, 0x001407 }, \ |
1262 | { 7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402 }, \ |
1263 | { 8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 }, \ |
1264 | { 9, 0x100bb3, 0x1301e5, 0x05a014, 0x001402 }, \ |
1265 | { 10, 0x100bb3, 0x1301e5, 0x05a014, 0x001407 }, \ |
1266 | { 11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 }, \ |
1267 | { 12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 }, \ |
1268 | { 13, 0x100bb3, 0x1301e7, 0x05a014, 0x001402 }, \ |
1269 | { 14, 0x100bb3, 0x1301e8, 0x05a014, 0x001404 }, \ |
1270 | { 36, 0x100bb3, 0x130266, 0x056014, 0x001408 }, \ |
1271 | { 38, 0x100bb3, 0x130267, 0x056014, 0x001404 }, \ |
1272 | { 40, 0x100bb2, 0x1301a0, 0x056014, 0x001400 }, \ |
1273 | { 44, 0x100bb2, 0x1301a0, 0x056014, 0x001408 }, \ |
1274 | { 46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 }, \ |
1275 | { 48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 }, \ |
1276 | { 52, 0x100bb2, 0x1301a2, 0x056014, 0x001404 }, \ |
1277 | { 54, 0x100bb2, 0x1301a2, 0x056014, 0x001408 }, \ |
1278 | { 56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 }, \ |
1279 | { 60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 }, \ |
1280 | { 62, 0x100bb2, 0x1301a4, 0x056014, 0x001404 }, \ |
1281 | { 64, 0x100bb2, 0x1301a4, 0x056014, 0x001408 }, \ |
1282 | { 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 }, \ |
1283 | { 102, 0x100bb2, 0x1701ac, 0x15e014, 0x001404 }, \ |
1284 | { 104, 0x100bb2, 0x1701ac, 0x15e014, 0x001408 }, \ |
1285 | { 108, 0x100bb3, 0x17028c, 0x15e014, 0x001404 }, \ |
1286 | { 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 }, \ |
1287 | { 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 }, \ |
1288 | { 116, 0x100bb3, 0x13028e, 0x05e014, 0x001408 }, \ |
1289 | { 118, 0x100bb3, 0x13028f, 0x05e014, 0x001404 }, \ |
1290 | { 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 }, \ |
1291 | { 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 }, \ |
1292 | { 126, 0x100bb1, 0x1300e0, 0x05e014, 0x001406 }, \ |
1293 | { 128, 0x100bb1, 0x1300e0, 0x05e014, 0x001408 }, \ |
1294 | { 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 }, \ |
1295 | { 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 }, \ |
1296 | { 136, 0x100bb1, 0x1300e1, 0x05e014, 0x001406 }, \ |
1297 | { 140, 0x100bb1, 0x1300e2, 0x05e014, 0x001400 }, \ |
1298 | { 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 }, \ |
1299 | { 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 }, \ |
1300 | { 153, 0x100bb1, 0x1300e3, 0x05e014, 0x001403 }, \ |
1301 | { 157, 0x100bb1, 0x1300e3, 0x05e014, 0x001407 }, \ |
1302 | { 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 }, \ |
1303 | { 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 }, \ |
1304 | { 165, 0x100bb1, 0x1300e4, 0x05e014, 0x001405 }, \ |
1305 | { 167, 0x100bb1, 0x1300f4, 0x05e014, 0x001407 }, \ |
1306 | { 169, 0x100bb1, 0x1300f4, 0x05e014, 0x001409 }, \ |
1307 | { 171, 0x100bb1, 0x1300f5, 0x05e014, 0x001401 }, \ |
1308 | { 173, 0x100bb1, 0x1300f5, 0x05e014, 0x001403 } |
1309 | |
1310 | #define RT3070_RF3052 \ |
1311 | { 0xf1, 2, 2 }, \ |
1312 | { 0xf1, 2, 7 }, \ |
1313 | { 0xf2, 2, 2 }, \ |
1314 | { 0xf2, 2, 7 }, \ |
1315 | { 0xf3, 2, 2 }, \ |
1316 | { 0xf3, 2, 7 }, \ |
1317 | { 0xf4, 2, 2 }, \ |
1318 | { 0xf4, 2, 7 }, \ |
1319 | { 0xf5, 2, 2 }, \ |
1320 | { 0xf5, 2, 7 }, \ |
1321 | { 0xf6, 2, 2 }, \ |
1322 | { 0xf6, 2, 7 }, \ |
1323 | { 0xf7, 2, 2 }, \ |
1324 | { 0xf8, 2, 4 }, \ |
1325 | { 0x56, 0, 4 }, \ |
1326 | { 0x56, 0, 6 }, \ |
1327 | { 0x56, 0, 8 }, \ |
1328 | { 0x57, 0, 0 }, \ |
1329 | { 0x57, 0, 2 }, \ |
1330 | { 0x57, 0, 4 }, \ |
1331 | { 0x57, 0, 8 }, \ |
1332 | { 0x57, 0, 10 }, \ |
1333 | { 0x58, 0, 0 }, \ |
1334 | { 0x58, 0, 4 }, \ |
1335 | { 0x58, 0, 6 }, \ |
1336 | { 0x58, 0, 8 }, \ |
1337 | { 0x5b, 0, 8 }, \ |
1338 | { 0x5b, 0, 10 }, \ |
1339 | { 0x5c, 0, 0 }, \ |
1340 | { 0x5c, 0, 4 }, \ |
1341 | { 0x5c, 0, 6 }, \ |
1342 | { 0x5c, 0, 8 }, \ |
1343 | { 0x5d, 0, 0 }, \ |
1344 | { 0x5d, 0, 2 }, \ |
1345 | { 0x5d, 0, 4 }, \ |
1346 | { 0x5d, 0, 8 }, \ |
1347 | { 0x5d, 0, 10 }, \ |
1348 | { 0x5e, 0, 0 }, \ |
1349 | { 0x5e, 0, 4 }, \ |
1350 | { 0x5e, 0, 6 }, \ |
1351 | { 0x5e, 0, 8 }, \ |
1352 | { 0x5f, 0, 0 }, \ |
1353 | { 0x5f, 0, 9 }, \ |
1354 | { 0x5f, 0, 11 }, \ |
1355 | { 0x60, 0, 1 }, \ |
1356 | { 0x60, 0, 5 }, \ |
1357 | { 0x60, 0, 7 }, \ |
1358 | { 0x60, 0, 9 }, \ |
1359 | { 0x61, 0, 1 }, \ |
1360 | { 0x61, 0, 3 }, \ |
1361 | { 0x61, 0, 5 }, \ |
1362 | { 0x61, 0, 7 }, \ |
1363 | { 0x61, 0, 9 } |
1364 | |
1365 | #define RT5592_RF5592_20MHZ \ |
1366 | { 0x1e2, 4, 10, 3 }, \ |
1367 | { 0x1e3, 4, 10, 3 }, \ |
1368 | { 0x1e4, 4, 10, 3 }, \ |
1369 | { 0x1e5, 4, 10, 3 }, \ |
1370 | { 0x1e6, 4, 10, 3 }, \ |
1371 | { 0x1e7, 4, 10, 3 }, \ |
1372 | { 0x1e8, 4, 10, 3 }, \ |
1373 | { 0x1e9, 4, 10, 3 }, \ |
1374 | { 0x1ea, 4, 10, 3 }, \ |
1375 | { 0x1eb, 4, 10, 3 }, \ |
1376 | { 0x1ec, 4, 10, 3 }, \ |
1377 | { 0x1ed, 4, 10, 3 }, \ |
1378 | { 0x1ee, 4, 10, 3 }, \ |
1379 | { 0x1f0, 8, 10, 3 }, \ |
1380 | { 0xac, 8, 12, 1 }, \ |
1381 | { 0xad, 0, 12, 1 }, \ |
1382 | { 0xad, 4, 12, 1 }, \ |
1383 | { 0xae, 0, 12, 1 }, \ |
1384 | { 0xae, 4, 12, 1 }, \ |
1385 | { 0xae, 8, 12, 1 }, \ |
1386 | { 0xaf, 4, 12, 1 }, \ |
1387 | { 0xaf, 8, 12, 1 }, \ |
1388 | { 0xb0, 0, 12, 1 }, \ |
1389 | { 0xb0, 8, 12, 1 }, \ |
1390 | { 0xb1, 0, 12, 1 }, \ |
1391 | { 0xb1, 4, 12, 1 }, \ |
1392 | { 0xb7, 4, 12, 1 }, \ |
1393 | { 0xb7, 8, 12, 1 }, \ |
1394 | { 0xb8, 0, 12, 1 }, \ |
1395 | { 0xb8, 8, 12, 1 }, \ |
1396 | { 0xb9, 0, 12, 1 }, \ |
1397 | { 0xb9, 4, 12, 1 }, \ |
1398 | { 0xba, 0, 12, 1 }, \ |
1399 | { 0xba, 4, 12, 1 }, \ |
1400 | { 0xba, 8, 12, 1 }, \ |
1401 | { 0xbb, 4, 12, 1 }, \ |
1402 | { 0xbb, 8, 12, 1 }, \ |
1403 | { 0xbc, 0, 12, 1 }, \ |
1404 | { 0xbc, 8, 12, 1 }, \ |
1405 | { 0xbd, 0, 12, 1 }, \ |
1406 | { 0xbd, 4, 12, 1 }, \ |
1407 | { 0xbe, 0, 12, 1 }, \ |
1408 | { 0xbf, 6, 12, 1 }, \ |
1409 | { 0xbf, 10, 12, 1 }, \ |
1410 | { 0xc0, 2, 12, 1 }, \ |
1411 | { 0xc0, 10, 12, 1 }, \ |
1412 | { 0xc1, 2, 12, 1 }, \ |
1413 | { 0xc1, 6, 12, 1 }, \ |
1414 | { 0xc2, 2, 12, 1 }, \ |
1415 | { 0xa4, 0, 12, 1 }, \ |
1416 | { 0xa4, 4, 12, 1 }, \ |
1417 | { 0xa5, 8, 12, 1 }, \ |
1418 | { 0xa6, 0, 12, 1 } |
1419 | |
1420 | #define RT5592_RF5592_40MHZ \ |
1421 | { 0xf1, 2, 10, 3 }, \ |
1422 | { 0xf1, 7, 10, 3 }, \ |
1423 | { 0xf2, 2, 10, 3 }, \ |
1424 | { 0xf2, 7, 10, 3 }, \ |
1425 | { 0xf3, 2, 10, 3 }, \ |
1426 | { 0xf3, 7, 10, 3 }, \ |
1427 | { 0xf4, 2, 10, 3 }, \ |
1428 | { 0xf4, 7, 10, 3 }, \ |
1429 | { 0xf5, 2, 10, 3 }, \ |
1430 | { 0xf5, 7, 10, 3 }, \ |
1431 | { 0xf6, 2, 10, 3 }, \ |
1432 | { 0xf6, 7, 10, 3 }, \ |
1433 | { 0xf7, 2, 10, 3 }, \ |
1434 | { 0xf8, 4, 10, 3 }, \ |
1435 | { 0x56, 4, 12, 1 }, \ |
1436 | { 0x56, 6, 12, 1 }, \ |
1437 | { 0x56, 8, 12, 1 }, \ |
1438 | { 0x57, 0, 12, 1 }, \ |
1439 | { 0x57, 2, 12, 1 }, \ |
1440 | { 0x57, 4, 12, 1 }, \ |
1441 | { 0x57, 8, 12, 1 }, \ |
1442 | { 0x57, 10, 12, 1 }, \ |
1443 | { 0x58, 0, 12, 1 }, \ |
1444 | { 0x58, 4, 12, 1 }, \ |
1445 | { 0x58, 6, 12, 1 }, \ |
1446 | { 0x58, 8, 12, 1 }, \ |
1447 | { 0x5b, 8, 12, 1 }, \ |
1448 | { 0x5b, 10, 12, 1 }, \ |
1449 | { 0x5c, 0, 12, 1 }, \ |
1450 | { 0x5c, 4, 12, 1 }, \ |
1451 | { 0x5c, 6, 12, 1 }, \ |
1452 | { 0x5c, 8, 12, 1 }, \ |
1453 | { 0x5d, 0, 12, 1 }, \ |
1454 | { 0x5d, 2, 12, 1 }, \ |
1455 | { 0x5d, 4, 12, 1 }, \ |
1456 | { 0x5d, 8, 12, 1 }, \ |
1457 | { 0x5d, 10, 12, 1 }, \ |
1458 | { 0x5e, 0, 12, 1 }, \ |
1459 | { 0x5e, 4, 12, 1 }, \ |
1460 | { 0x5e, 6, 12, 1 }, \ |
1461 | { 0x5e, 8, 12, 1 }, \ |
1462 | { 0x5f, 0, 12, 1 }, \ |
1463 | { 0x5f, 9, 12, 1 }, \ |
1464 | { 0x5f, 11, 12, 1 }, \ |
1465 | { 0x60, 1, 12, 1 }, \ |
1466 | { 0x60, 5, 12, 1 }, \ |
1467 | { 0x60, 7, 12, 1 }, \ |
1468 | { 0x60, 9, 12, 1 }, \ |
1469 | { 0x61, 1, 12, 1 }, \ |
1470 | { 0x52, 0, 12, 1 }, \ |
1471 | { 0x52, 4, 12, 1 }, \ |
1472 | { 0x52, 8, 12, 1 }, \ |
1473 | { 0x53, 0, 12, 1 } |
1474 | |
1475 | #define RT3070_DEF_RF \ |
1476 | { 4, 0x40 }, \ |
1477 | { 5, 0x03 }, \ |
1478 | { 6, 0x02 }, \ |
1479 | { 7, 0x60 }, \ |
1480 | { 9, 0x0f }, \ |
1481 | { 10, 0x41 }, \ |
1482 | { 11, 0x21 }, \ |
1483 | { 12, 0x7b }, \ |
1484 | { 14, 0x90 }, \ |
1485 | { 15, 0x58 }, \ |
1486 | { 16, 0xb3 }, \ |
1487 | { 17, 0x92 }, \ |
1488 | { 18, 0x2c }, \ |
1489 | { 19, 0x02 }, \ |
1490 | { 20, 0xba }, \ |
1491 | { 21, 0xdb }, \ |
1492 | { 24, 0x16 }, \ |
1493 | { 25, 0x01 }, \ |
1494 | { 29, 0x1f } |
1495 | |
1496 | #define RT3572_DEF_RF \ |
1497 | { 0, 0x70 }, \ |
1498 | { 1, 0x81 }, \ |
1499 | { 2, 0xf1 }, \ |
1500 | { 3, 0x02 }, \ |
1501 | { 4, 0x4c }, \ |
1502 | { 5, 0x05 }, \ |
1503 | { 6, 0x4a }, \ |
1504 | { 7, 0xd8 }, \ |
1505 | { 9, 0xc3 }, \ |
1506 | { 10, 0xf1 }, \ |
1507 | { 11, 0xb9 }, \ |
1508 | { 12, 0x70 }, \ |
1509 | { 13, 0x65 }, \ |
1510 | { 14, 0xa0 }, \ |
1511 | { 15, 0x53 }, \ |
1512 | { 16, 0x4c }, \ |
1513 | { 17, 0x23 }, \ |
1514 | { 18, 0xac }, \ |
1515 | { 19, 0x93 }, \ |
1516 | { 20, 0xb3 }, \ |
1517 | { 21, 0xd0 }, \ |
1518 | { 22, 0x00 }, \ |
1519 | { 23, 0x3c }, \ |
1520 | { 24, 0x16 }, \ |
1521 | { 25, 0x15 }, \ |
1522 | { 26, 0x85 }, \ |
1523 | { 27, 0x00 }, \ |
1524 | { 28, 0x00 }, \ |
1525 | { 29, 0x9b }, \ |
1526 | { 30, 0x09 }, \ |
1527 | { 31, 0x10 } |
1528 | |
1529 | #define RT3593_DEF_RF \ |
1530 | { 1, 0x03 }, \ |
1531 | { 3, 0x80 }, \ |
1532 | { 5, 0x00 }, \ |
1533 | { 6, 0x40 }, \ |
1534 | { 8, 0xf1 }, \ |
1535 | { 9, 0x02 }, \ |
1536 | { 10, 0xd3 }, \ |
1537 | { 11, 0x40 }, \ |
1538 | { 12, 0x4e }, \ |
1539 | { 13, 0x12 }, \ |
1540 | { 18, 0x40 }, \ |
1541 | { 22, 0x20 }, \ |
1542 | { 30, 0x10 }, \ |
1543 | { 31, 0x80 }, \ |
1544 | { 32, 0x78 }, \ |
1545 | { 33, 0x3b }, \ |
1546 | { 34, 0x3c }, \ |
1547 | { 35, 0xe0 }, \ |
1548 | { 38, 0x86 }, \ |
1549 | { 39, 0x23 }, \ |
1550 | { 44, 0xd3 }, \ |
1551 | { 45, 0xbb }, \ |
1552 | { 46, 0x60 }, \ |
1553 | { 49, 0x81 }, \ |
1554 | { 50, 0x86 }, \ |
1555 | { 51, 0x75 }, \ |
1556 | { 52, 0x45 }, \ |
1557 | { 53, 0x18 }, \ |
1558 | { 54, 0x18 }, \ |
1559 | { 55, 0x18 }, \ |
1560 | { 56, 0xdb }, \ |
1561 | { 57, 0x6e } |
1562 | |
1563 | #define RT5390_DEF_RF \ |
1564 | { 1, 0x0f }, \ |
1565 | { 2, 0x80 }, \ |
1566 | { 3, 0x88 }, \ |
1567 | { 5, 0x10 }, \ |
1568 | { 6, 0xa0 }, \ |
1569 | { 7, 0x00 }, \ |
1570 | { 10, 0x53 }, \ |
1571 | { 11, 0x4a }, \ |
1572 | { 12, 0x46 }, \ |
1573 | { 13, 0x9f }, \ |
1574 | { 14, 0x00 }, \ |
1575 | { 15, 0x00 }, \ |
1576 | { 16, 0x00 }, \ |
1577 | { 18, 0x03 }, \ |
1578 | { 19, 0x00 }, \ |
1579 | { 20, 0x00 }, \ |
1580 | { 21, 0x00 }, \ |
1581 | { 22, 0x20 }, \ |
1582 | { 23, 0x00 }, \ |
1583 | { 24, 0x00 }, \ |
1584 | { 25, 0xc0 }, \ |
1585 | { 26, 0x00 }, \ |
1586 | { 27, 0x09 }, \ |
1587 | { 28, 0x00 }, \ |
1588 | { 29, 0x10 }, \ |
1589 | { 30, 0x10 }, \ |
1590 | { 31, 0x80 }, \ |
1591 | { 32, 0x80 }, \ |
1592 | { 33, 0x00 }, \ |
1593 | { 34, 0x07 }, \ |
1594 | { 35, 0x12 }, \ |
1595 | { 36, 0x00 }, \ |
1596 | { 37, 0x08 }, \ |
1597 | { 38, 0x85 }, \ |
1598 | { 39, 0x1b }, \ |
1599 | { 40, 0x0b }, \ |
1600 | { 41, 0xbb }, \ |
1601 | { 42, 0xd2 }, \ |
1602 | { 43, 0x9a }, \ |
1603 | { 44, 0x0e }, \ |
1604 | { 45, 0xa2 }, \ |
1605 | { 46, 0x7b }, \ |
1606 | { 47, 0x00 }, \ |
1607 | { 48, 0x10 }, \ |
1608 | { 49, 0x94 }, \ |
1609 | { 52, 0x38 }, \ |
1610 | { 53, 0x84 }, \ |
1611 | { 54, 0x78 }, \ |
1612 | { 55, 0x44 }, \ |
1613 | { 56, 0x22 }, \ |
1614 | { 57, 0x80 }, \ |
1615 | { 58, 0x7f }, \ |
1616 | { 59, 0x8f }, \ |
1617 | { 60, 0x45 }, \ |
1618 | { 61, 0xdd }, \ |
1619 | { 62, 0x00 }, \ |
1620 | { 63, 0x00 } |
1621 | |
1622 | #define RT5392_DEF_RF \ |
1623 | { 1, 0x17 }, \ |
1624 | { 3, 0x88 }, \ |
1625 | { 5, 0x10 }, \ |
1626 | { 6, 0xe0 }, \ |
1627 | { 7, 0x00 }, \ |
1628 | { 10, 0x53 }, \ |
1629 | { 11, 0x4a }, \ |
1630 | { 12, 0x46 }, \ |
1631 | { 13, 0x9f }, \ |
1632 | { 14, 0x00 }, \ |
1633 | { 15, 0x00 }, \ |
1634 | { 16, 0x00 }, \ |
1635 | { 18, 0x03 }, \ |
1636 | { 19, 0x4d }, \ |
1637 | { 20, 0x00 }, \ |
1638 | { 21, 0x8d }, \ |
1639 | { 22, 0x20 }, \ |
1640 | { 23, 0x0b }, \ |
1641 | { 24, 0x44 }, \ |
1642 | { 25, 0x80 }, \ |
1643 | { 26, 0x82 }, \ |
1644 | { 27, 0x09 }, \ |
1645 | { 28, 0x00 }, \ |
1646 | { 29, 0x10 }, \ |
1647 | { 30, 0x10 }, \ |
1648 | { 31, 0x80 }, \ |
1649 | { 32, 0x20 }, \ |
1650 | { 33, 0xc0 }, \ |
1651 | { 34, 0x07 }, \ |
1652 | { 35, 0x12 }, \ |
1653 | { 36, 0x00 }, \ |
1654 | { 37, 0x08 }, \ |
1655 | { 38, 0x89 }, \ |
1656 | { 39, 0x1b }, \ |
1657 | { 40, 0x0f }, \ |
1658 | { 41, 0xbb }, \ |
1659 | { 42, 0xd5 }, \ |
1660 | { 43, 0x9b }, \ |
1661 | { 44, 0x0e }, \ |
1662 | { 45, 0xa2 }, \ |
1663 | { 46, 0x73 }, \ |
1664 | { 47, 0x0c }, \ |
1665 | { 48, 0x10 }, \ |
1666 | { 49, 0x94 }, \ |
1667 | { 50, 0x94 }, \ |
1668 | { 51, 0x3a }, \ |
1669 | { 52, 0x48 }, \ |
1670 | { 53, 0x44 }, \ |
1671 | { 54, 0x38 }, \ |
1672 | { 55, 0x43 }, \ |
1673 | { 56, 0xa1 }, \ |
1674 | { 57, 0x00 }, \ |
1675 | { 58, 0x39 }, \ |
1676 | { 59, 0x07 }, \ |
1677 | { 60, 0x45 }, \ |
1678 | { 61, 0x91 }, \ |
1679 | { 62, 0x39 }, \ |
1680 | { 63, 0x07 } |
1681 | |
1682 | #define RT5592_DEF_RF \ |
1683 | { 1, 0x3f }, \ |
1684 | { 3, 0x08 }, \ |
1685 | { 5, 0x10 }, \ |
1686 | { 6, 0xe4 }, \ |
1687 | { 7, 0x00 }, \ |
1688 | { 14, 0x00 }, \ |
1689 | { 15, 0x00 }, \ |
1690 | { 16, 0x00 }, \ |
1691 | { 18, 0x03 }, \ |
1692 | { 19, 0x4d }, \ |
1693 | { 20, 0x10 }, \ |
1694 | { 21, 0x8d }, \ |
1695 | { 26, 0x82 }, \ |
1696 | { 28, 0x00 }, \ |
1697 | { 29, 0x10 }, \ |
1698 | { 33, 0xc0 }, \ |
1699 | { 34, 0x07 }, \ |
1700 | { 35, 0x12 }, \ |
1701 | { 47, 0x0c }, \ |
1702 | { 53, 0x22 }, \ |
1703 | { 63, 0x07 } |
1704 | |
1705 | #define RT5592_2GHZ_DEF_RF \ |
1706 | { 10, 0x90 }, \ |
1707 | { 11, 0x4a }, \ |
1708 | { 12, 0x52 }, \ |
1709 | { 13, 0x42 }, \ |
1710 | { 22, 0x40 }, \ |
1711 | { 24, 0x4a }, \ |
1712 | { 25, 0x80 }, \ |
1713 | { 27, 0x42 }, \ |
1714 | { 36, 0x80 }, \ |
1715 | { 37, 0x08 }, \ |
1716 | { 38, 0x89 }, \ |
1717 | { 39, 0x1b }, \ |
1718 | { 40, 0x0d }, \ |
1719 | { 41, 0x9b }, \ |
1720 | { 42, 0xd5 }, \ |
1721 | { 43, 0x72 }, \ |
1722 | { 44, 0x0e }, \ |
1723 | { 45, 0xa2 }, \ |
1724 | { 46, 0x6b }, \ |
1725 | { 48, 0x10 }, \ |
1726 | { 51, 0x3e }, \ |
1727 | { 52, 0x48 }, \ |
1728 | { 54, 0x38 }, \ |
1729 | { 56, 0xa1 }, \ |
1730 | { 57, 0x00 }, \ |
1731 | { 58, 0x39 }, \ |
1732 | { 60, 0x45 }, \ |
1733 | { 61, 0x91 }, \ |
1734 | { 62, 0x39 } |
1735 | |
1736 | #define RT5592_5GHZ_DEF_RF \ |
1737 | { 10, 0x97 }, \ |
1738 | { 11, 0x40 }, \ |
1739 | { 25, 0xbf }, \ |
1740 | { 27, 0x42 }, \ |
1741 | { 36, 0x00 }, \ |
1742 | { 37, 0x04 }, \ |
1743 | { 38, 0x85 }, \ |
1744 | { 40, 0x42 }, \ |
1745 | { 41, 0xbb }, \ |
1746 | { 42, 0xd7 }, \ |
1747 | { 45, 0x41 }, \ |
1748 | { 48, 0x00 }, \ |
1749 | { 57, 0x77 }, \ |
1750 | { 60, 0x05 }, \ |
1751 | { 61, 0x01 } |
1752 | |
1753 | #define RT5592_CHAN_5GHZ \ |
1754 | { 36, 64, 12, 0x2e }, \ |
1755 | { 100, 165, 12, 0x0e }, \ |
1756 | { 36, 64, 13, 0x22 }, \ |
1757 | { 100, 165, 13, 0x42 }, \ |
1758 | { 36, 64, 22, 0x60 }, \ |
1759 | { 100, 165, 22, 0x40 }, \ |
1760 | { 36, 64, 23, 0x7f }, \ |
1761 | { 100, 153, 23, 0x3c }, \ |
1762 | { 155, 165, 23, 0x38 }, \ |
1763 | { 36, 50, 24, 0x09 }, \ |
1764 | { 52, 64, 24, 0x07 }, \ |
1765 | { 100, 153, 24, 0x06 }, \ |
1766 | { 155, 165, 24, 0x05 }, \ |
1767 | { 36, 64, 39, 0x1c }, \ |
1768 | { 100, 138, 39, 0x1a }, \ |
1769 | { 140, 165, 39, 0x18 }, \ |
1770 | { 36, 64, 43, 0x5b }, \ |
1771 | { 100, 138, 43, 0x3b }, \ |
1772 | { 140, 165, 43, 0x1b }, \ |
1773 | { 36, 64, 44, 0x40 }, \ |
1774 | { 100, 138, 44, 0x20 }, \ |
1775 | { 140, 165, 44, 0x10 }, \ |
1776 | { 36, 64, 46, 0x00 }, \ |
1777 | { 100, 138, 46, 0x18 }, \ |
1778 | { 140, 165, 46, 0x08 }, \ |
1779 | { 36, 64, 51, 0xfe }, \ |
1780 | { 100, 124, 51, 0xfc }, \ |
1781 | { 126, 165, 51, 0xec }, \ |
1782 | { 36, 64, 52, 0x0c }, \ |
1783 | { 100, 138, 52, 0x06 }, \ |
1784 | { 140, 165, 52, 0x06 }, \ |
1785 | { 36, 64, 54, 0xf8 }, \ |
1786 | { 100, 165, 54, 0xeb }, \ |
1787 | { 36, 50, 55, 0x06 }, \ |
1788 | { 52, 64, 55, 0x04 }, \ |
1789 | { 100, 138, 55, 0x01 }, \ |
1790 | { 140, 165, 55, 0x00 }, \ |
1791 | { 36, 50, 56, 0xd3 }, \ |
1792 | { 52, 128, 56, 0xbb }, \ |
1793 | { 130, 165, 56, 0xab }, \ |
1794 | { 36, 64, 58, 0x15 }, \ |
1795 | { 100, 116, 58, 0x1d }, \ |
1796 | { 118, 165, 58, 0x15 }, \ |
1797 | { 36, 64, 59, 0x7f }, \ |
1798 | { 100, 138, 59, 0x3f }, \ |
1799 | { 140, 165, 59, 0x7c }, \ |
1800 | { 36, 64, 62, 0x15 }, \ |
1801 | { 100, 116, 62, 0x1d }, \ |
1802 | { 118, 165, 62, 0x15 } |
1803 | |