1 | /* $NetBSD: nouveau_chan.c,v 1.2 2014/08/06 13:35:13 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_chan.c,v 1.2 2014/08/06 13:35:13 riastradh Exp $" ); |
29 | |
30 | #include <core/object.h> |
31 | #include <core/client.h> |
32 | #include <core/device.h> |
33 | #include <core/class.h> |
34 | |
35 | #include <subdev/fb.h> |
36 | #include <subdev/vm.h> |
37 | #include <subdev/instmem.h> |
38 | |
39 | #include <engine/software.h> |
40 | |
41 | #include "nouveau_drm.h" |
42 | #include "nouveau_dma.h" |
43 | #include "nouveau_bo.h" |
44 | #include "nouveau_chan.h" |
45 | #include "nouveau_fence.h" |
46 | #include "nouveau_abi16.h" |
47 | |
48 | MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM" ); |
49 | static int nouveau_vram_pushbuf; |
50 | module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); |
51 | |
52 | int |
53 | nouveau_channel_idle(struct nouveau_channel *chan) |
54 | { |
55 | struct nouveau_cli *cli = chan->cli; |
56 | struct nouveau_fence *fence = NULL; |
57 | int ret; |
58 | |
59 | ret = nouveau_fence_new(chan, false, &fence); |
60 | if (!ret) { |
61 | ret = nouveau_fence_wait(fence, false, false); |
62 | nouveau_fence_unref(&fence); |
63 | } |
64 | |
65 | if (ret) |
66 | NV_ERROR(cli, "failed to idle channel 0x%08x [%s]\n" , |
67 | chan->handle, cli->base.name); |
68 | return ret; |
69 | } |
70 | |
71 | void |
72 | nouveau_channel_del(struct nouveau_channel **pchan) |
73 | { |
74 | struct nouveau_channel *chan = *pchan; |
75 | if (chan) { |
76 | struct nouveau_object *client = nv_object(chan->cli); |
77 | if (chan->fence) { |
78 | nouveau_channel_idle(chan); |
79 | nouveau_fence(chan->drm)->context_del(chan); |
80 | } |
81 | nouveau_object_del(client, NVDRM_DEVICE, chan->handle); |
82 | nouveau_object_del(client, NVDRM_DEVICE, chan->push.handle); |
83 | nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma); |
84 | nouveau_bo_unmap(chan->push.buffer); |
85 | if (chan->push.buffer && chan->push.buffer->pin_refcnt) |
86 | nouveau_bo_unpin(chan->push.buffer); |
87 | nouveau_bo_ref(NULL, &chan->push.buffer); |
88 | kfree(chan); |
89 | } |
90 | *pchan = NULL; |
91 | } |
92 | |
93 | static int |
94 | nouveau_channel_prep(struct nouveau_drm *drm, struct nouveau_cli *cli, |
95 | u32 parent, u32 handle, u32 size, |
96 | struct nouveau_channel **pchan) |
97 | { |
98 | struct nouveau_device *device = nv_device(drm->device); |
99 | struct nouveau_instmem *imem = nouveau_instmem(device); |
100 | struct nouveau_vmmgr *vmm = nouveau_vmmgr(device); |
101 | struct nouveau_fb *pfb = nouveau_fb(device); |
102 | struct nouveau_client *client = &cli->base; |
103 | static const struct nv_dma_class zero_args; |
104 | struct nv_dma_class args = zero_args; |
105 | struct nouveau_channel *chan; |
106 | struct nouveau_object *push; |
107 | u32 target; |
108 | int ret; |
109 | |
110 | chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); |
111 | if (!chan) |
112 | return -ENOMEM; |
113 | |
114 | chan->cli = cli; |
115 | chan->drm = drm; |
116 | chan->handle = handle; |
117 | |
118 | /* allocate memory for dma push buffer */ |
119 | target = TTM_PL_FLAG_TT; |
120 | if (nouveau_vram_pushbuf) |
121 | target = TTM_PL_FLAG_VRAM; |
122 | |
123 | ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, |
124 | &chan->push.buffer); |
125 | if (ret == 0) { |
126 | ret = nouveau_bo_pin(chan->push.buffer, target); |
127 | if (ret == 0) |
128 | ret = nouveau_bo_map(chan->push.buffer); |
129 | } |
130 | |
131 | if (ret) { |
132 | nouveau_channel_del(pchan); |
133 | return ret; |
134 | } |
135 | |
136 | /* create dma object covering the *entire* memory space that the |
137 | * pushbuf lives in, this is because the GEM code requires that |
138 | * we be able to call out to other (indirect) push buffers |
139 | */ |
140 | chan->push.vma.offset = chan->push.buffer->bo.offset; |
141 | chan->push.handle = NVDRM_PUSH | (handle & 0xffff); |
142 | |
143 | if (device->card_type >= NV_50) { |
144 | ret = nouveau_bo_vma_add(chan->push.buffer, client->vm, |
145 | &chan->push.vma); |
146 | if (ret) { |
147 | nouveau_channel_del(pchan); |
148 | return ret; |
149 | } |
150 | |
151 | args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_VM; |
152 | args.start = 0; |
153 | args.limit = client->vm->vmm->limit - 1; |
154 | } else |
155 | if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { |
156 | u64 limit = pfb->ram->size - imem->reserved - 1; |
157 | if (device->card_type == NV_04) { |
158 | /* nv04 vram pushbuf hack, retarget to its location in |
159 | * the framebuffer bar rather than direct vram access.. |
160 | * nfi why this exists, it came from the -nv ddx. |
161 | */ |
162 | args.flags = NV_DMA_TARGET_PCI | NV_DMA_ACCESS_RDWR; |
163 | args.start = nv_device_resource_start(device, 1); |
164 | args.limit = args.start + limit; |
165 | } else { |
166 | args.flags = NV_DMA_TARGET_VRAM | NV_DMA_ACCESS_RDWR; |
167 | args.start = 0; |
168 | args.limit = limit; |
169 | } |
170 | } else { |
171 | if (chan->drm->agp.stat == ENABLED) { |
172 | args.flags = NV_DMA_TARGET_AGP | NV_DMA_ACCESS_RDWR; |
173 | args.start = chan->drm->agp.base; |
174 | args.limit = chan->drm->agp.base + |
175 | chan->drm->agp.size - 1; |
176 | } else { |
177 | args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_RDWR; |
178 | args.start = 0; |
179 | args.limit = vmm->limit - 1; |
180 | } |
181 | } |
182 | |
183 | ret = nouveau_object_new(nv_object(chan->cli), parent, |
184 | chan->push.handle, 0x0002, |
185 | &args, sizeof(args), &push); |
186 | if (ret) { |
187 | nouveau_channel_del(pchan); |
188 | return ret; |
189 | } |
190 | |
191 | return 0; |
192 | } |
193 | |
194 | static int |
195 | nouveau_channel_ind(struct nouveau_drm *drm, struct nouveau_cli *cli, |
196 | u32 parent, u32 handle, u32 engine, |
197 | struct nouveau_channel **pchan) |
198 | { |
199 | static const u16 oclasses[] = { NVE0_CHANNEL_IND_CLASS, |
200 | NVC0_CHANNEL_IND_CLASS, |
201 | NV84_CHANNEL_IND_CLASS, |
202 | NV50_CHANNEL_IND_CLASS, |
203 | 0 }; |
204 | const u16 *oclass = oclasses; |
205 | struct nve0_channel_ind_class args; |
206 | struct nouveau_channel *chan; |
207 | int ret; |
208 | |
209 | /* allocate dma push buffer */ |
210 | ret = nouveau_channel_prep(drm, cli, parent, handle, 0x12000, &chan); |
211 | *pchan = chan; |
212 | if (ret) |
213 | return ret; |
214 | |
215 | /* create channel object */ |
216 | args.pushbuf = chan->push.handle; |
217 | args.ioffset = 0x10000 + chan->push.vma.offset; |
218 | args.ilength = 0x02000; |
219 | args.engine = engine; |
220 | |
221 | do { |
222 | ret = nouveau_object_new(nv_object(cli), parent, handle, |
223 | *oclass++, &args, sizeof(args), |
224 | &chan->object); |
225 | if (ret == 0) |
226 | return ret; |
227 | } while (*oclass); |
228 | |
229 | nouveau_channel_del(pchan); |
230 | return ret; |
231 | } |
232 | |
233 | static int |
234 | nouveau_channel_dma(struct nouveau_drm *drm, struct nouveau_cli *cli, |
235 | u32 parent, u32 handle, struct nouveau_channel **pchan) |
236 | { |
237 | static const u16 oclasses[] = { NV40_CHANNEL_DMA_CLASS, |
238 | NV17_CHANNEL_DMA_CLASS, |
239 | NV10_CHANNEL_DMA_CLASS, |
240 | NV03_CHANNEL_DMA_CLASS, |
241 | 0 }; |
242 | const u16 *oclass = oclasses; |
243 | struct nv03_channel_dma_class args; |
244 | struct nouveau_channel *chan; |
245 | int ret; |
246 | |
247 | /* allocate dma push buffer */ |
248 | ret = nouveau_channel_prep(drm, cli, parent, handle, 0x10000, &chan); |
249 | *pchan = chan; |
250 | if (ret) |
251 | return ret; |
252 | |
253 | /* create channel object */ |
254 | args.pushbuf = chan->push.handle; |
255 | args.offset = chan->push.vma.offset; |
256 | |
257 | do { |
258 | ret = nouveau_object_new(nv_object(cli), parent, handle, |
259 | *oclass++, &args, sizeof(args), |
260 | &chan->object); |
261 | if (ret == 0) |
262 | return ret; |
263 | } while (ret && *oclass); |
264 | |
265 | nouveau_channel_del(pchan); |
266 | return ret; |
267 | } |
268 | |
269 | static int |
270 | nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) |
271 | { |
272 | struct nouveau_client *client = nv_client(chan->cli); |
273 | struct nouveau_device *device = nv_device(chan->drm->device); |
274 | struct nouveau_instmem *imem = nouveau_instmem(device); |
275 | struct nouveau_vmmgr *vmm = nouveau_vmmgr(device); |
276 | struct nouveau_fb *pfb = nouveau_fb(device); |
277 | struct nouveau_software_chan *swch; |
278 | struct nouveau_object *object; |
279 | static const struct nv_dma_class zero_args; |
280 | struct nv_dma_class args = zero_args; |
281 | int ret, i; |
282 | |
283 | /* allocate dma objects to cover all allowed vram, and gart */ |
284 | if (device->card_type < NV_C0) { |
285 | if (device->card_type >= NV_50) { |
286 | args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_VM; |
287 | args.start = 0; |
288 | args.limit = client->vm->vmm->limit - 1; |
289 | } else { |
290 | args.flags = NV_DMA_TARGET_VRAM | NV_DMA_ACCESS_RDWR; |
291 | args.start = 0; |
292 | args.limit = pfb->ram->size - imem->reserved - 1; |
293 | } |
294 | |
295 | ret = nouveau_object_new(nv_object(client), chan->handle, vram, |
296 | 0x003d, &args, sizeof(args), &object); |
297 | if (ret) |
298 | return ret; |
299 | |
300 | if (device->card_type >= NV_50) { |
301 | args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_VM; |
302 | args.start = 0; |
303 | args.limit = client->vm->vmm->limit - 1; |
304 | } else |
305 | if (chan->drm->agp.stat == ENABLED) { |
306 | args.flags = NV_DMA_TARGET_AGP | NV_DMA_ACCESS_RDWR; |
307 | args.start = chan->drm->agp.base; |
308 | args.limit = chan->drm->agp.base + |
309 | chan->drm->agp.size - 1; |
310 | } else { |
311 | args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_RDWR; |
312 | args.start = 0; |
313 | args.limit = vmm->limit - 1; |
314 | } |
315 | |
316 | ret = nouveau_object_new(nv_object(client), chan->handle, gart, |
317 | 0x003d, &args, sizeof(args), &object); |
318 | if (ret) |
319 | return ret; |
320 | |
321 | chan->vram = vram; |
322 | chan->gart = gart; |
323 | } |
324 | |
325 | /* initialise dma tracking parameters */ |
326 | switch (nv_hclass(chan->object) & 0x00ff) { |
327 | case 0x006b: |
328 | case 0x006e: |
329 | chan->user_put = 0x40; |
330 | chan->user_get = 0x44; |
331 | chan->dma.max = (0x10000 / 4) - 2; |
332 | break; |
333 | default: |
334 | chan->user_put = 0x40; |
335 | chan->user_get = 0x44; |
336 | chan->user_get_hi = 0x60; |
337 | chan->dma.ib_base = 0x10000 / 4; |
338 | chan->dma.ib_max = (0x02000 / 8) - 1; |
339 | chan->dma.ib_put = 0; |
340 | chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; |
341 | chan->dma.max = chan->dma.ib_base; |
342 | break; |
343 | } |
344 | |
345 | chan->dma.put = 0; |
346 | chan->dma.cur = chan->dma.put; |
347 | chan->dma.free = chan->dma.max - chan->dma.cur; |
348 | |
349 | ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); |
350 | if (ret) |
351 | return ret; |
352 | |
353 | for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) |
354 | OUT_RING(chan, 0x00000000); |
355 | |
356 | /* allocate software object class (used for fences on <= nv05) */ |
357 | if (device->card_type < NV_10) { |
358 | ret = nouveau_object_new(nv_object(client), chan->handle, |
359 | NvSw, 0x006e, NULL, 0, &object); |
360 | if (ret) |
361 | return ret; |
362 | |
363 | swch = (void *)object->parent; |
364 | swch->flip = nouveau_flip_complete; |
365 | swch->flip_data = chan; |
366 | |
367 | ret = RING_SPACE(chan, 2); |
368 | if (ret) |
369 | return ret; |
370 | |
371 | BEGIN_NV04(chan, NvSubSw, 0x0000, 1); |
372 | OUT_RING (chan, NvSw); |
373 | FIRE_RING (chan); |
374 | } |
375 | |
376 | /* initialise synchronisation */ |
377 | return nouveau_fence(chan->drm)->context_new(chan); |
378 | } |
379 | |
380 | int |
381 | nouveau_channel_new(struct nouveau_drm *drm, struct nouveau_cli *cli, |
382 | u32 parent, u32 handle, u32 arg0, u32 arg1, |
383 | struct nouveau_channel **pchan) |
384 | { |
385 | int ret; |
386 | |
387 | ret = nouveau_channel_ind(drm, cli, parent, handle, arg0, pchan); |
388 | if (ret) { |
389 | NV_DEBUG(cli, "ib channel create, %d\n" , ret); |
390 | ret = nouveau_channel_dma(drm, cli, parent, handle, pchan); |
391 | if (ret) { |
392 | NV_DEBUG(cli, "dma channel create, %d\n" , ret); |
393 | return ret; |
394 | } |
395 | } |
396 | |
397 | ret = nouveau_channel_init(*pchan, arg0, arg1); |
398 | if (ret) { |
399 | NV_ERROR(cli, "channel failed to initialise, %d\n" , ret); |
400 | nouveau_channel_del(pchan); |
401 | return ret; |
402 | } |
403 | |
404 | return 0; |
405 | } |
406 | |