1/* $NetBSD: nouveau_subdev_therm_nvd0.c,v 1.1.1.1 2014/08/06 12:36:32 riastradh Exp $ */
2
3/*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26
27#include <sys/cdefs.h>
28__KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_therm_nvd0.c,v 1.1.1.1 2014/08/06 12:36:32 riastradh Exp $");
29
30#include "priv.h"
31
32struct nvd0_therm_priv {
33 struct nouveau_therm_priv base;
34};
35
36static int
37pwm_info(struct nouveau_therm *therm, int line)
38{
39 u32 gpio = nv_rd32(therm, 0x00d610 + (line * 0x04));
40
41 switch (gpio & 0x000000c0) {
42 case 0x00000000: /* normal mode, possibly pwm forced off by us */
43 case 0x00000040: /* nvio special */
44 switch (gpio & 0x0000001f) {
45 case 0x00: return 2;
46 case 0x19: return 1;
47 case 0x1c: return 0;
48 case 0x1e: return 2;
49 default:
50 break;
51 }
52 default:
53 break;
54 }
55
56 nv_error(therm, "GPIO %d unknown PWM: 0x%08x\n", line, gpio);
57 return -ENODEV;
58}
59
60static int
61nvd0_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
62{
63 u32 data = enable ? 0x00000040 : 0x00000000;
64 int indx = pwm_info(therm, line);
65 if (indx < 0)
66 return indx;
67 else if (indx < 2)
68 nv_mask(therm, 0x00d610 + (line * 0x04), 0x000000c0, data);
69 /* nothing to do for indx == 2, it seems hardwired to PTHERM */
70 return 0;
71}
72
73static int
74nvd0_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
75{
76 int indx = pwm_info(therm, line);
77 if (indx < 0)
78 return indx;
79 else if (indx < 2) {
80 if (nv_rd32(therm, 0x00d610 + (line * 0x04)) & 0x00000040) {
81 *divs = nv_rd32(therm, 0x00e114 + (indx * 8));
82 *duty = nv_rd32(therm, 0x00e118 + (indx * 8));
83 return 0;
84 }
85 } else if (indx == 2) {
86 *divs = nv_rd32(therm, 0x0200d8) & 0x1fff;
87 *duty = nv_rd32(therm, 0x0200dc) & 0x1fff;
88 return 0;
89 }
90
91 return -EINVAL;
92}
93
94static int
95nvd0_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
96{
97 int indx = pwm_info(therm, line);
98 if (indx < 0)
99 return indx;
100 else if (indx < 2) {
101 nv_wr32(therm, 0x00e114 + (indx * 8), divs);
102 nv_wr32(therm, 0x00e118 + (indx * 8), duty | 0x80000000);
103 } else if (indx == 2) {
104 nv_mask(therm, 0x0200d8, 0x1fff, divs); /* keep the high bits */
105 nv_wr32(therm, 0x0200dc, duty | 0x40000000);
106 }
107 return 0;
108}
109
110static int
111nvd0_fan_pwm_clock(struct nouveau_therm *therm, int line)
112{
113 int indx = pwm_info(therm, line);
114 if (indx < 0)
115 return 0;
116 else if (indx < 2)
117 return (nv_device(therm)->crystal * 1000) / 20;
118 else
119 return nv_device(therm)->crystal * 1000 / 10;
120}
121
122static int
123nvd0_therm_init(struct nouveau_object *object)
124{
125 struct nvd0_therm_priv *priv = (void *)object;
126 int ret;
127
128 ret = nouveau_therm_init(&priv->base.base);
129 if (ret)
130 return ret;
131
132 /* enable fan tach, count revolutions per-second */
133 nv_mask(priv, 0x00e720, 0x00000003, 0x00000002);
134 if (priv->base.fan->tach.func != DCB_GPIO_UNUSED) {
135 nv_mask(priv, 0x00d79c, 0x000000ff, priv->base.fan->tach.line);
136 nv_wr32(priv, 0x00e724, nv_device(priv)->crystal * 1000);
137 nv_mask(priv, 0x00e720, 0x00000001, 0x00000001);
138 }
139 nv_mask(priv, 0x00e720, 0x00000002, 0x00000000);
140
141 return 0;
142}
143
144static int
145nvd0_therm_ctor(struct nouveau_object *parent,
146 struct nouveau_object *engine,
147 struct nouveau_oclass *oclass, void *data, u32 size,
148 struct nouveau_object **pobject)
149{
150 struct nvd0_therm_priv *priv;
151 int ret;
152
153 ret = nouveau_therm_create(parent, engine, oclass, &priv);
154 *pobject = nv_object(priv);
155 if (ret)
156 return ret;
157
158 priv->base.base.pwm_ctrl = nvd0_fan_pwm_ctrl;
159 priv->base.base.pwm_get = nvd0_fan_pwm_get;
160 priv->base.base.pwm_set = nvd0_fan_pwm_set;
161 priv->base.base.pwm_clock = nvd0_fan_pwm_clock;
162 priv->base.base.temp_get = nv84_temp_get;
163 priv->base.base.fan_sense = nva3_therm_fan_sense;
164 priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
165 return nouveau_therm_preinit(&priv->base.base);
166}
167
168struct nouveau_oclass
169nvd0_therm_oclass = {
170 .handle = NV_SUBDEV(THERM, 0xd0),
171 .ofuncs = &(struct nouveau_ofuncs) {
172 .ctor = nvd0_therm_ctor,
173 .dtor = _nouveau_therm_dtor,
174 .init = nvd0_therm_init,
175 .fini = nv84_therm_fini,
176 },
177};
178