1 | /* |
2 | * Copyright © 2013 Intel Corporation |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 | * DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Author: Jani Nikula <jani.nikula@intel.com> |
24 | */ |
25 | |
26 | #include <drm/drmP.h> |
27 | #include <drm/drm_crtc.h> |
28 | #include <drm/drm_edid.h> |
29 | #include <drm/i915_drm.h> |
30 | #include <linux/slab.h> |
31 | #include "i915_drv.h" |
32 | #include "intel_drv.h" |
33 | #include "intel_dsi.h" |
34 | #include "intel_dsi_cmd.h" |
35 | |
36 | #ifdef __NetBSD__ |
37 | static bool |
38 | intel_dsi_dummy_init(struct intel_dsi_device *dev __unused) |
39 | { |
40 | |
41 | return false; |
42 | } |
43 | |
44 | static const struct intel_dsi_dev_ops intel_dsi_dummy = { |
45 | .init = &intel_dsi_dummy_init, |
46 | }; |
47 | #endif |
48 | |
49 | /* the sub-encoders aka panel drivers */ |
50 | static const struct intel_dsi_device intel_dsi_devices[] = { |
51 | #ifdef __NetBSD__ |
52 | { |
53 | .panel_id = 0, |
54 | .name = "dummy" , |
55 | .dev_ops = &intel_dsi_dummy, |
56 | }, |
57 | #endif |
58 | }; |
59 | |
60 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
61 | { |
62 | mutex_lock(&dev_priv->dpio_lock); |
63 | |
64 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
65 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); |
66 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); |
67 | udelay(150); |
68 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); |
69 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); |
70 | |
71 | mutex_unlock(&dev_priv->dpio_lock); |
72 | } |
73 | |
74 | static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector) |
75 | { |
76 | return container_of(intel_attached_encoder(connector), |
77 | struct intel_dsi, base); |
78 | } |
79 | |
80 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
81 | { |
82 | return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE; |
83 | } |
84 | |
85 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) |
86 | { |
87 | return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE; |
88 | } |
89 | |
90 | static void intel_dsi_hot_plug(struct intel_encoder *encoder) |
91 | { |
92 | DRM_DEBUG_KMS("\n" ); |
93 | } |
94 | |
95 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
96 | struct intel_crtc_config *config) |
97 | { |
98 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
99 | base); |
100 | struct intel_connector *intel_connector = intel_dsi->attached_connector; |
101 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
102 | struct drm_display_mode *adjusted_mode = &config->adjusted_mode; |
103 | struct drm_display_mode *mode = &config->requested_mode; |
104 | |
105 | DRM_DEBUG_KMS("\n" ); |
106 | |
107 | if (fixed_mode) |
108 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
109 | |
110 | if (intel_dsi->dev.dev_ops->mode_fixup) |
111 | return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev, |
112 | mode, adjusted_mode); |
113 | |
114 | return true; |
115 | } |
116 | |
117 | static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) |
118 | { |
119 | DRM_DEBUG_KMS("\n" ); |
120 | |
121 | vlv_enable_dsi_pll(encoder); |
122 | } |
123 | |
124 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
125 | { |
126 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
127 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
128 | int pipe = intel_crtc->pipe; |
129 | u32 val; |
130 | |
131 | DRM_DEBUG_KMS("\n" ); |
132 | |
133 | val = I915_READ(MIPI_PORT_CTRL(pipe)); |
134 | I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD); |
135 | usleep_range(1000, 1500); |
136 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT); |
137 | usleep_range(2000, 2500); |
138 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); |
139 | usleep_range(2000, 2500); |
140 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00); |
141 | usleep_range(2000, 2500); |
142 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); |
143 | usleep_range(2000, 2500); |
144 | } |
145 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) |
146 | { |
147 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
148 | |
149 | DRM_DEBUG_KMS("\n" ); |
150 | |
151 | if (intel_dsi->dev.dev_ops->panel_reset) |
152 | intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev); |
153 | |
154 | /* put device in ready state */ |
155 | intel_dsi_device_ready(encoder); |
156 | |
157 | if (intel_dsi->dev.dev_ops->send_otp_cmds) |
158 | intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev); |
159 | } |
160 | |
161 | static void intel_dsi_enable(struct intel_encoder *encoder) |
162 | { |
163 | struct drm_device *dev = encoder->base.dev; |
164 | struct drm_i915_private *dev_priv = dev->dev_private; |
165 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
166 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
167 | int pipe = intel_crtc->pipe; |
168 | u32 temp; |
169 | |
170 | DRM_DEBUG_KMS("\n" ); |
171 | |
172 | if (is_cmd_mode(intel_dsi)) |
173 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); |
174 | else { |
175 | msleep(20); /* XXX */ |
176 | dpi_send_cmd(intel_dsi, TURN_ON); |
177 | msleep(100); |
178 | |
179 | /* assert ip_tg_enable signal */ |
180 | temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; |
181 | temp = temp | intel_dsi->port_bits; |
182 | I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); |
183 | POSTING_READ(MIPI_PORT_CTRL(pipe)); |
184 | } |
185 | |
186 | if (intel_dsi->dev.dev_ops->enable) |
187 | intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); |
188 | } |
189 | |
190 | static void intel_dsi_disable(struct intel_encoder *encoder) |
191 | { |
192 | struct drm_device *dev = encoder->base.dev; |
193 | struct drm_i915_private *dev_priv = dev->dev_private; |
194 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
195 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
196 | int pipe = intel_crtc->pipe; |
197 | u32 temp; |
198 | |
199 | DRM_DEBUG_KMS("\n" ); |
200 | |
201 | if (is_vid_mode(intel_dsi)) { |
202 | dpi_send_cmd(intel_dsi, SHUTDOWN); |
203 | msleep(10); |
204 | |
205 | /* de-assert ip_tg_enable signal */ |
206 | temp = I915_READ(MIPI_PORT_CTRL(pipe)); |
207 | I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); |
208 | POSTING_READ(MIPI_PORT_CTRL(pipe)); |
209 | |
210 | msleep(2); |
211 | } |
212 | |
213 | /* if disable packets are sent before sending shutdown packet then in |
214 | * some next enable sequence send turn on packet error is observed */ |
215 | if (intel_dsi->dev.dev_ops->disable) |
216 | intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); |
217 | } |
218 | |
219 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
220 | { |
221 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
222 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
223 | int pipe = intel_crtc->pipe; |
224 | u32 val; |
225 | |
226 | DRM_DEBUG_KMS("\n" ); |
227 | |
228 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); |
229 | usleep_range(2000, 2500); |
230 | |
231 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT); |
232 | usleep_range(2000, 2500); |
233 | |
234 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); |
235 | usleep_range(2000, 2500); |
236 | |
237 | val = I915_READ(MIPI_PORT_CTRL(pipe)); |
238 | I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD); |
239 | usleep_range(1000, 1500); |
240 | |
241 | if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT) |
242 | == 0x00000), 30)) |
243 | DRM_ERROR("DSI LP not going Low\n" ); |
244 | |
245 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00); |
246 | usleep_range(2000, 2500); |
247 | |
248 | vlv_disable_dsi_pll(encoder); |
249 | } |
250 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
251 | { |
252 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
253 | |
254 | DRM_DEBUG_KMS("\n" ); |
255 | |
256 | intel_dsi_clear_device_ready(encoder); |
257 | |
258 | if (intel_dsi->dev.dev_ops->disable_panel_power) |
259 | intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev); |
260 | } |
261 | |
262 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, |
263 | enum i915_pipe *pipe) |
264 | { |
265 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
266 | enum intel_display_power_domain power_domain; |
267 | u32 port, func; |
268 | enum i915_pipe p; |
269 | |
270 | DRM_DEBUG_KMS("\n" ); |
271 | |
272 | power_domain = intel_display_port_power_domain(encoder); |
273 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
274 | return false; |
275 | |
276 | /* XXX: this only works for one DSI output */ |
277 | for (p = PIPE_A; p <= PIPE_B; p++) { |
278 | port = I915_READ(MIPI_PORT_CTRL(p)); |
279 | func = I915_READ(MIPI_DSI_FUNC_PRG(p)); |
280 | |
281 | if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { |
282 | if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) { |
283 | *pipe = p; |
284 | return true; |
285 | } |
286 | } |
287 | } |
288 | |
289 | return false; |
290 | } |
291 | |
292 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
293 | struct intel_crtc_config *pipe_config) |
294 | { |
295 | DRM_DEBUG_KMS("\n" ); |
296 | |
297 | /* XXX: read flags, set to adjusted_mode */ |
298 | } |
299 | |
300 | static enum drm_mode_status |
301 | intel_dsi_mode_valid(struct drm_connector *connector, |
302 | struct drm_display_mode *mode) |
303 | { |
304 | struct intel_connector *intel_connector = to_intel_connector(connector); |
305 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
306 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); |
307 | |
308 | DRM_DEBUG_KMS("\n" ); |
309 | |
310 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { |
311 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n" ); |
312 | return MODE_NO_DBLESCAN; |
313 | } |
314 | |
315 | if (fixed_mode) { |
316 | if (mode->hdisplay > fixed_mode->hdisplay) |
317 | return MODE_PANEL; |
318 | if (mode->vdisplay > fixed_mode->vdisplay) |
319 | return MODE_PANEL; |
320 | } |
321 | |
322 | return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode); |
323 | } |
324 | |
325 | /* return txclkesc cycles in terms of divider and duration in us */ |
326 | static u16 txclkesc(u32 divider, unsigned int us) |
327 | { |
328 | switch (divider) { |
329 | case ESCAPE_CLOCK_DIVIDER_1: |
330 | default: |
331 | return 20 * us; |
332 | case ESCAPE_CLOCK_DIVIDER_2: |
333 | return 10 * us; |
334 | case ESCAPE_CLOCK_DIVIDER_4: |
335 | return 5 * us; |
336 | } |
337 | } |
338 | |
339 | /* return pixels in terms of txbyteclkhs */ |
340 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count) |
341 | { |
342 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count); |
343 | } |
344 | |
345 | static void set_dsi_timings(struct drm_encoder *encoder, |
346 | const struct drm_display_mode *mode) |
347 | { |
348 | struct drm_device *dev = encoder->dev; |
349 | struct drm_i915_private *dev_priv = dev->dev_private; |
350 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
351 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
352 | int pipe = intel_crtc->pipe; |
353 | unsigned int bpp = intel_crtc->config.pipe_bpp; |
354 | unsigned int lane_count = intel_dsi->lane_count; |
355 | |
356 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
357 | |
358 | hactive = mode->hdisplay; |
359 | hfp = mode->hsync_start - mode->hdisplay; |
360 | hsync = mode->hsync_end - mode->hsync_start; |
361 | hbp = mode->htotal - mode->hsync_end; |
362 | |
363 | vfp = mode->vsync_start - mode->vdisplay; |
364 | vsync = mode->vsync_end - mode->vsync_start; |
365 | vbp = mode->vtotal - mode->vsync_end; |
366 | |
367 | /* horizontal values are in terms of high speed byte clock */ |
368 | hactive = txbyteclkhs(hactive, bpp, lane_count); |
369 | hfp = txbyteclkhs(hfp, bpp, lane_count); |
370 | hsync = txbyteclkhs(hsync, bpp, lane_count); |
371 | hbp = txbyteclkhs(hbp, bpp, lane_count); |
372 | |
373 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); |
374 | I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); |
375 | |
376 | /* meaningful for video mode non-burst sync pulse mode only, can be zero |
377 | * for non-burst sync events and burst modes */ |
378 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync); |
379 | I915_WRITE(MIPI_HBP_COUNT(pipe), hbp); |
380 | |
381 | /* vertical values are in terms of lines */ |
382 | I915_WRITE(MIPI_VFP_COUNT(pipe), vfp); |
383 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync); |
384 | I915_WRITE(MIPI_VBP_COUNT(pipe), vbp); |
385 | } |
386 | |
387 | static void intel_dsi_mode_set(struct intel_encoder *intel_encoder) |
388 | { |
389 | struct drm_encoder *encoder = &intel_encoder->base; |
390 | struct drm_device *dev = encoder->dev; |
391 | struct drm_i915_private *dev_priv = dev->dev_private; |
392 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
393 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
394 | struct drm_display_mode *adjusted_mode = |
395 | &intel_crtc->config.adjusted_mode; |
396 | int pipe = intel_crtc->pipe; |
397 | unsigned int bpp = intel_crtc->config.pipe_bpp; |
398 | u32 val, tmp; |
399 | |
400 | DRM_DEBUG_KMS("pipe %c\n" , pipe_name(pipe)); |
401 | |
402 | /* XXX: Location of the call */ |
403 | band_gap_reset(dev_priv); |
404 | |
405 | /* escape clock divider, 20MHz, shared for A and C. device ready must be |
406 | * off when doing this! txclkesc? */ |
407 | tmp = I915_READ(MIPI_CTRL(0)); |
408 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
409 | I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); |
410 | |
411 | /* read request priority is per pipe */ |
412 | tmp = I915_READ(MIPI_CTRL(pipe)); |
413 | tmp &= ~READ_REQUEST_PRIORITY_MASK; |
414 | I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH); |
415 | |
416 | /* XXX: why here, why like this? handling in irq handler?! */ |
417 | I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff); |
418 | I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff); |
419 | |
420 | I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg); |
421 | |
422 | I915_WRITE(MIPI_DPI_RESOLUTION(pipe), |
423 | adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | |
424 | adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
425 | |
426 | set_dsi_timings(encoder, adjusted_mode); |
427 | |
428 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; |
429 | if (is_cmd_mode(intel_dsi)) { |
430 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; |
431 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ |
432 | } else { |
433 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; |
434 | |
435 | /* XXX: cross-check bpp vs. pixel format? */ |
436 | val |= intel_dsi->pixel_format; |
437 | } |
438 | I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); |
439 | |
440 | /* timeouts for recovery. one frame IIUC. if counter expires, EOT and |
441 | * stop state. */ |
442 | |
443 | /* |
444 | * In burst mode, value greater than one DPI line Time in byte clock |
445 | * (txbyteclkhs) To timeout this timer 1+ of the above said value is |
446 | * recommended. |
447 | * |
448 | * In non-burst mode, Value greater than one DPI frame time in byte |
449 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value |
450 | * is recommended. |
451 | * |
452 | * In DBI only mode, value greater than one DBI frame time in byte |
453 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value |
454 | * is recommended. |
455 | */ |
456 | |
457 | if (is_vid_mode(intel_dsi) && |
458 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { |
459 | I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), |
460 | txbyteclkhs(adjusted_mode->htotal, bpp, |
461 | intel_dsi->lane_count) + 1); |
462 | } else { |
463 | I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), |
464 | txbyteclkhs(adjusted_mode->vtotal * |
465 | adjusted_mode->htotal, |
466 | bpp, intel_dsi->lane_count) + 1); |
467 | } |
468 | I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout); |
469 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val); |
470 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val); |
471 | |
472 | /* dphy stuff */ |
473 | |
474 | /* in terms of low power clock */ |
475 | I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100)); |
476 | |
477 | /* recovery disables */ |
478 | I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable); |
479 | |
480 | /* in terms of txbyteclkhs. actual high to low switch + |
481 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. |
482 | * |
483 | * XXX: write MIPI_STOP_STATE_STALL? |
484 | */ |
485 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), |
486 | intel_dsi->hs_to_lp_count); |
487 | |
488 | /* XXX: low power clock equivalence in terms of byte clock. the number |
489 | * of byte clocks occupied in one low power clock. based on txbyteclkhs |
490 | * and txclkesc. txclkesc time / txbyteclk time * (105 + |
491 | * MIPI_STOP_STATE_STALL) / 105.??? |
492 | */ |
493 | I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk); |
494 | |
495 | /* the bw essential for transmitting 16 long packets containing 252 |
496 | * bytes meant for dcs write memory command is programmed in this |
497 | * register in terms of byte clocks. based on dsi transfer rate and the |
498 | * number of lanes configured the time taken to transmit 16 long packets |
499 | * in a dsi stream varies. */ |
500 | I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer); |
501 | |
502 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe), |
503 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | |
504 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); |
505 | |
506 | if (is_vid_mode(intel_dsi)) |
507 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), |
508 | intel_dsi->video_frmt_cfg_bits | |
509 | intel_dsi->video_mode_format); |
510 | } |
511 | |
512 | static enum drm_connector_status |
513 | intel_dsi_detect(struct drm_connector *connector, bool force) |
514 | { |
515 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); |
516 | struct intel_encoder *intel_encoder = &intel_dsi->base; |
517 | enum intel_display_power_domain power_domain; |
518 | enum drm_connector_status connector_status; |
519 | struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private; |
520 | |
521 | DRM_DEBUG_KMS("\n" ); |
522 | power_domain = intel_display_port_power_domain(intel_encoder); |
523 | |
524 | intel_display_power_get(dev_priv, power_domain); |
525 | connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev); |
526 | intel_display_power_put(dev_priv, power_domain); |
527 | |
528 | return connector_status; |
529 | } |
530 | |
531 | static int intel_dsi_get_modes(struct drm_connector *connector) |
532 | { |
533 | struct intel_connector *intel_connector = to_intel_connector(connector); |
534 | struct drm_display_mode *mode; |
535 | |
536 | DRM_DEBUG_KMS("\n" ); |
537 | |
538 | if (!intel_connector->panel.fixed_mode) { |
539 | DRM_DEBUG_KMS("no fixed mode\n" ); |
540 | return 0; |
541 | } |
542 | |
543 | mode = drm_mode_duplicate(connector->dev, |
544 | intel_connector->panel.fixed_mode); |
545 | if (!mode) { |
546 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n" ); |
547 | return 0; |
548 | } |
549 | |
550 | drm_mode_probed_add(connector, mode); |
551 | return 1; |
552 | } |
553 | |
554 | static void intel_dsi_destroy(struct drm_connector *connector) |
555 | { |
556 | struct intel_connector *intel_connector = to_intel_connector(connector); |
557 | |
558 | DRM_DEBUG_KMS("\n" ); |
559 | intel_panel_fini(&intel_connector->panel); |
560 | drm_connector_cleanup(connector); |
561 | kfree(connector); |
562 | } |
563 | |
564 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
565 | .destroy = intel_encoder_destroy, |
566 | }; |
567 | |
568 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { |
569 | .get_modes = intel_dsi_get_modes, |
570 | .mode_valid = intel_dsi_mode_valid, |
571 | .best_encoder = intel_best_encoder, |
572 | }; |
573 | |
574 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { |
575 | .dpms = intel_connector_dpms, |
576 | .detect = intel_dsi_detect, |
577 | .destroy = intel_dsi_destroy, |
578 | .fill_modes = drm_helper_probe_single_connector_modes, |
579 | }; |
580 | |
581 | bool intel_dsi_init(struct drm_device *dev) |
582 | { |
583 | struct intel_dsi *intel_dsi; |
584 | struct intel_encoder *intel_encoder; |
585 | struct drm_encoder *encoder; |
586 | struct intel_connector *intel_connector; |
587 | struct drm_connector *connector; |
588 | struct drm_display_mode *fixed_mode = NULL; |
589 | const struct intel_dsi_device *dsi; |
590 | unsigned int i; |
591 | |
592 | DRM_DEBUG_KMS("\n" ); |
593 | |
594 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
595 | if (!intel_dsi) |
596 | return false; |
597 | |
598 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
599 | if (!intel_connector) { |
600 | kfree(intel_dsi); |
601 | return false; |
602 | } |
603 | |
604 | intel_encoder = &intel_dsi->base; |
605 | encoder = &intel_encoder->base; |
606 | intel_dsi->attached_connector = intel_connector; |
607 | |
608 | connector = &intel_connector->base; |
609 | |
610 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); |
611 | |
612 | /* XXX: very likely not all of these are needed */ |
613 | intel_encoder->hot_plug = intel_dsi_hot_plug; |
614 | intel_encoder->compute_config = intel_dsi_compute_config; |
615 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; |
616 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
617 | intel_encoder->enable = intel_dsi_enable; |
618 | intel_encoder->mode_set = intel_dsi_mode_set; |
619 | intel_encoder->disable = intel_dsi_disable; |
620 | intel_encoder->post_disable = intel_dsi_post_disable; |
621 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; |
622 | intel_encoder->get_config = intel_dsi_get_config; |
623 | |
624 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
625 | intel_connector->unregister = intel_connector_unregister; |
626 | |
627 | for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { |
628 | dsi = &intel_dsi_devices[i]; |
629 | intel_dsi->dev = *dsi; |
630 | |
631 | if (dsi->dev_ops->init(&intel_dsi->dev)) |
632 | break; |
633 | } |
634 | |
635 | if (i == ARRAY_SIZE(intel_dsi_devices)) { |
636 | DRM_DEBUG_KMS("no device found\n" ); |
637 | goto err; |
638 | } |
639 | |
640 | intel_encoder->type = INTEL_OUTPUT_DSI; |
641 | intel_encoder->crtc_mask = (1 << 0); /* XXX */ |
642 | |
643 | intel_encoder->cloneable = 0; |
644 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
645 | DRM_MODE_CONNECTOR_DSI); |
646 | |
647 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); |
648 | |
649 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ |
650 | connector->interlace_allowed = false; |
651 | connector->doublescan_allowed = false; |
652 | |
653 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
654 | |
655 | drm_sysfs_connector_add(connector); |
656 | |
657 | fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); |
658 | if (!fixed_mode) { |
659 | DRM_DEBUG_KMS("no fixed mode\n" ); |
660 | goto err; |
661 | } |
662 | |
663 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
664 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
665 | |
666 | return true; |
667 | |
668 | err: |
669 | drm_encoder_cleanup(&intel_encoder->base); |
670 | kfree(intel_dsi); |
671 | kfree(intel_connector); |
672 | |
673 | return false; |
674 | } |
675 | |