1 | /* $NetBSD: nouveau_subdev_bios_perf.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Nouveau Community |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Martin Peres |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_bios_perf.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $" ); |
29 | |
30 | #include <subdev/bios.h> |
31 | #include <subdev/bios/bit.h> |
32 | #include <subdev/bios/perf.h> |
33 | |
34 | u16 |
35 | nvbios_perf_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, |
36 | u8 *cnt, u8 *len, u8 *snr, u8 *ssz) |
37 | { |
38 | struct bit_entry bit_P; |
39 | u16 perf = 0x0000; |
40 | |
41 | if (!bit_entry(bios, 'P', &bit_P)) { |
42 | if (bit_P.version <= 2) { |
43 | perf = nv_ro16(bios, bit_P.offset + 0); |
44 | if (perf) { |
45 | *ver = nv_ro08(bios, perf + 0); |
46 | *hdr = nv_ro08(bios, perf + 1); |
47 | if (*ver >= 0x40 && *ver < 0x41) { |
48 | *cnt = nv_ro08(bios, perf + 5); |
49 | *len = nv_ro08(bios, perf + 2); |
50 | *snr = nv_ro08(bios, perf + 4); |
51 | *ssz = nv_ro08(bios, perf + 3); |
52 | return perf; |
53 | } else |
54 | if (*ver >= 0x20 && *ver < 0x40) { |
55 | *cnt = nv_ro08(bios, perf + 2); |
56 | *len = nv_ro08(bios, perf + 3); |
57 | *snr = nv_ro08(bios, perf + 4); |
58 | *ssz = nv_ro08(bios, perf + 5); |
59 | return perf; |
60 | } |
61 | } |
62 | } |
63 | } |
64 | |
65 | if (bios->bmp_offset) { |
66 | if (nv_ro08(bios, bios->bmp_offset + 6) >= 0x25) { |
67 | perf = nv_ro16(bios, bios->bmp_offset + 0x94); |
68 | if (perf) { |
69 | *hdr = nv_ro08(bios, perf + 0); |
70 | *ver = nv_ro08(bios, perf + 1); |
71 | *cnt = nv_ro08(bios, perf + 2); |
72 | *len = nv_ro08(bios, perf + 3); |
73 | *snr = 0; |
74 | *ssz = 0; |
75 | return perf; |
76 | } |
77 | } |
78 | } |
79 | |
80 | return 0x0000; |
81 | } |
82 | |
83 | u16 |
84 | nvbios_perf_entry(struct nouveau_bios *bios, int idx, |
85 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len) |
86 | { |
87 | u8 snr, ssz; |
88 | u16 perf = nvbios_perf_table(bios, ver, hdr, cnt, len, &snr, &ssz); |
89 | if (perf && idx < *cnt) { |
90 | perf = perf + *hdr + (idx * (*len + (snr * ssz))); |
91 | *hdr = *len; |
92 | *cnt = snr; |
93 | *len = ssz; |
94 | return perf; |
95 | } |
96 | return 0x0000; |
97 | } |
98 | |
99 | u16 |
100 | nvbios_perfEp(struct nouveau_bios *bios, int idx, |
101 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, |
102 | struct nvbios_perfE *info) |
103 | { |
104 | u16 perf = nvbios_perf_entry(bios, idx, ver, hdr, cnt, len); |
105 | memset(info, 0x00, sizeof(*info)); |
106 | info->pstate = nv_ro08(bios, perf + 0x00); |
107 | switch (!!perf * *ver) { |
108 | case 0x12: |
109 | case 0x13: |
110 | case 0x14: |
111 | info->core = nv_ro32(bios, perf + 0x01) * 10; |
112 | info->memory = nv_ro32(bios, perf + 0x05) * 20; |
113 | info->fanspeed = nv_ro08(bios, perf + 0x37); |
114 | if (*hdr > 0x38) |
115 | info->voltage = nv_ro08(bios, perf + 0x38); |
116 | break; |
117 | case 0x21: |
118 | case 0x23: |
119 | case 0x24: |
120 | info->fanspeed = nv_ro08(bios, perf + 0x04); |
121 | info->voltage = nv_ro08(bios, perf + 0x05); |
122 | info->shader = nv_ro16(bios, perf + 0x06) * 1000; |
123 | info->core = info->shader + (signed char) |
124 | nv_ro08(bios, perf + 0x08) * 1000; |
125 | switch (nv_device(bios)->chipset) { |
126 | case 0x49: |
127 | case 0x4b: |
128 | info->memory = nv_ro16(bios, perf + 0x0b) * 1000; |
129 | break; |
130 | default: |
131 | info->memory = nv_ro16(bios, perf + 0x0b) * 2000; |
132 | break; |
133 | } |
134 | break; |
135 | case 0x25: |
136 | info->fanspeed = nv_ro08(bios, perf + 0x04); |
137 | info->voltage = nv_ro08(bios, perf + 0x05); |
138 | info->core = nv_ro16(bios, perf + 0x06) * 1000; |
139 | info->shader = nv_ro16(bios, perf + 0x0a) * 1000; |
140 | info->memory = nv_ro16(bios, perf + 0x0c) * 1000; |
141 | break; |
142 | case 0x30: |
143 | info->script = nv_ro16(bios, perf + 0x02); |
144 | case 0x35: |
145 | info->fanspeed = nv_ro08(bios, perf + 0x06); |
146 | info->voltage = nv_ro08(bios, perf + 0x07); |
147 | info->core = nv_ro16(bios, perf + 0x08) * 1000; |
148 | info->shader = nv_ro16(bios, perf + 0x0a) * 1000; |
149 | info->memory = nv_ro16(bios, perf + 0x0c) * 1000; |
150 | info->vdec = nv_ro16(bios, perf + 0x10) * 1000; |
151 | info->disp = nv_ro16(bios, perf + 0x14) * 1000; |
152 | break; |
153 | case 0x40: |
154 | info->voltage = nv_ro08(bios, perf + 0x02); |
155 | break; |
156 | default: |
157 | return 0x0000; |
158 | } |
159 | return perf; |
160 | } |
161 | |
162 | u32 |
163 | nvbios_perfSe(struct nouveau_bios *bios, u32 perfE, int idx, |
164 | u8 *ver, u8 *hdr, u8 cnt, u8 len) |
165 | { |
166 | u32 data = 0x00000000; |
167 | if (idx < cnt) { |
168 | data = perfE + *hdr + (idx * len); |
169 | *hdr = len; |
170 | } |
171 | return data; |
172 | } |
173 | |
174 | u32 |
175 | nvbios_perfSp(struct nouveau_bios *bios, u32 perfE, int idx, |
176 | u8 *ver, u8 *hdr, u8 cnt, u8 len, |
177 | struct nvbios_perfS *info) |
178 | { |
179 | u32 data = nvbios_perfSe(bios, perfE, idx, ver, hdr, cnt, len); |
180 | memset(info, 0x00, sizeof(*info)); |
181 | switch (!!data * *ver) { |
182 | case 0x40: |
183 | info->v40.freq = (nv_ro16(bios, data + 0x00) & 0x3fff) * 1000; |
184 | break; |
185 | default: |
186 | break; |
187 | } |
188 | return data; |
189 | } |
190 | |
191 | int |
192 | nvbios_perf_fan_parse(struct nouveau_bios *bios, |
193 | struct nvbios_perf_fan *fan) |
194 | { |
195 | u8 ver, hdr, cnt, len, snr, ssz; |
196 | u16 perf = nvbios_perf_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz); |
197 | if (!perf) |
198 | return -ENODEV; |
199 | |
200 | if (ver >= 0x20 && ver < 0x40 && hdr > 6) |
201 | fan->pwm_divisor = nv_ro16(bios, perf + 6); |
202 | else |
203 | fan->pwm_divisor = 0; |
204 | |
205 | return 0; |
206 | } |
207 | |