1 | /* $NetBSD: rtl81x9var.h,v 1.55 2015/04/13 16:33:24 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1997, 1998 |
5 | * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * 3. All advertising materials mentioning features or use of this software |
16 | * must display the following acknowledgement: |
17 | * This product includes software developed by Bill Paul. |
18 | * 4. Neither the name of the author nor the names of any co-contributors |
19 | * may be used to endorse or promote products derived from this software |
20 | * without specific prior written permission. |
21 | * |
22 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
23 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
25 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
26 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
29 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
30 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
31 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
32 | * THE POSSIBILITY OF SUCH DAMAGE. |
33 | * |
34 | * FreeBSD Id: if_rlreg.h,v 1.9 1999/06/20 18:56:09 wpaul Exp |
35 | */ |
36 | |
37 | #include <sys/rndsource.h> |
38 | |
39 | #define RTK_ETHER_ALIGN 2 |
40 | #define RTK_RXSTAT_LEN 4 |
41 | |
42 | #ifdef __NO_STRICT_ALIGNMENT |
43 | /* |
44 | * XXX According to PR kern/33763, some 8168 and variants can't DMA |
45 | * XXX RX packet data into unaligned buffer. This means such chips will |
46 | * XXX never work on !__NO_STRICT_ALIGNMENT hosts without copying buffer. |
47 | */ |
48 | #define RE_ETHER_ALIGN 0 |
49 | #else |
50 | #define RE_ETHER_ALIGN 2 |
51 | #endif |
52 | |
53 | struct rtk_type { |
54 | uint16_t rtk_vid; |
55 | uint16_t rtk_did; |
56 | int rtk_basetype; |
57 | #define RTK_8129 1 |
58 | #define RTK_8139 2 |
59 | #define RTK_8139CPLUS 3 |
60 | #define RTK_8169 4 |
61 | #define RTK_8168 5 |
62 | #define RTK_8101E 6 |
63 | const char *rtk_name; |
64 | }; |
65 | |
66 | struct rtk_mii_frame { |
67 | uint8_t mii_stdelim; |
68 | uint8_t mii_opcode; |
69 | uint8_t mii_phyaddr; |
70 | uint8_t mii_regaddr; |
71 | uint8_t mii_turnaround; |
72 | uint16_t mii_data; |
73 | }; |
74 | |
75 | /* |
76 | * MII constants |
77 | */ |
78 | #define RTK_MII_STARTDELIM 0x01 |
79 | #define RTK_MII_READOP 0x02 |
80 | #define RTK_MII_WRITEOP 0x01 |
81 | #define RTK_MII_TURNAROUND 0x02 |
82 | |
83 | |
84 | /* |
85 | * The RealTek doesn't use a fragment-based descriptor mechanism. |
86 | * Instead, there are only four register sets, each or which represents |
87 | * one 'descriptor.' Basically, each TX descriptor is just a contiguous |
88 | * packet buffer (32-bit aligned!) and we place the buffer addresses in |
89 | * the registers so the chip knows where they are. |
90 | * |
91 | * We can sort of kludge together the same kind of buffer management |
92 | * used in previous drivers, but we have to do buffer copies almost all |
93 | * the time, so it doesn't really buy us much. |
94 | * |
95 | * For reception, there's just one large buffer where the chip stores |
96 | * all received packets. |
97 | */ |
98 | |
99 | #ifdef dreamcast |
100 | /* |
101 | * XXX dreamcast has only 32KB DMA'able memory on its PCI bridge. |
102 | * XXX Maybe this should be handled by prop_dictionary, or |
103 | * XXX some other new API which returns available DMA resources. |
104 | */ |
105 | #define RTK_RX_BUF_SZ RTK_RXBUF_16 |
106 | #else |
107 | #define RTK_RX_BUF_SZ RTK_RXBUF_64 |
108 | #endif |
109 | #define RTK_RXBUFLEN RTK_RXBUF_LEN(RTK_RX_BUF_SZ) |
110 | #define RTK_TX_LIST_CNT 4 |
111 | |
112 | /* |
113 | * The 8139C+ and 8169 gigE chips support descriptor-based TX |
114 | * and RX. In fact, they even support TCP large send. Descriptors |
115 | * must be allocated in contiguous blocks that are aligned on a |
116 | * 256-byte boundary. The RX rings can hold a maximum of 64 descriptors. |
117 | * The TX rings can hold upto 64 descriptors on 8139C+, and |
118 | * 1024 descriptors on 8169 gigE chips. |
119 | */ |
120 | #define RE_RING_ALIGN 256 |
121 | |
122 | /* |
123 | * Size of descriptors and TX queue. |
124 | * These numbers must be power of two to simplify RE_NEXT_*() macro. |
125 | */ |
126 | #define RE_RX_DESC_CNT 64 |
127 | #define RE_TX_DESC_CNT_8139 64 |
128 | #define RE_TX_DESC_CNT_8169 1024 |
129 | #define RE_TX_QLEN 64 |
130 | |
131 | #define RE_NTXDESC_RSVD 4 |
132 | |
133 | struct re_rxsoft { |
134 | struct mbuf *rxs_mbuf; |
135 | bus_dmamap_t rxs_dmamap; |
136 | }; |
137 | |
138 | struct re_txq { |
139 | struct mbuf *txq_mbuf; |
140 | bus_dmamap_t txq_dmamap; |
141 | int txq_descidx; |
142 | int txq_nsegs; |
143 | }; |
144 | |
145 | struct re_list_data { |
146 | struct re_txq re_txq[RE_TX_QLEN]; |
147 | int re_txq_considx; |
148 | int re_txq_prodidx; |
149 | int re_txq_free; |
150 | |
151 | bus_dmamap_t re_tx_list_map; |
152 | struct re_desc *re_tx_list; |
153 | int re_tx_free; /* # of free descriptors */ |
154 | int re_tx_nextfree; /* next descriptor to use */ |
155 | int re_tx_desc_cnt; /* # of descriptors */ |
156 | bus_dma_segment_t re_tx_listseg; |
157 | int re_tx_listnseg; |
158 | |
159 | struct re_rxsoft re_rxsoft[RE_RX_DESC_CNT]; |
160 | bus_dmamap_t re_rx_list_map; |
161 | struct re_desc *re_rx_list; |
162 | int re_rx_prodidx; |
163 | bus_dma_segment_t re_rx_listseg; |
164 | int re_rx_listnseg; |
165 | }; |
166 | |
167 | struct rtk_tx_desc { |
168 | SIMPLEQ_ENTRY(rtk_tx_desc) txd_q; |
169 | struct mbuf *txd_mbuf; |
170 | bus_dmamap_t txd_dmamap; |
171 | bus_addr_t txd_txaddr; |
172 | bus_addr_t txd_txstat; |
173 | }; |
174 | |
175 | struct rtk_softc { |
176 | device_t sc_dev; |
177 | struct ethercom ethercom; /* interface info */ |
178 | struct mii_data mii; |
179 | struct callout rtk_tick_ch; /* tick callout */ |
180 | bus_space_tag_t rtk_btag; /* bus space tag */ |
181 | bus_space_handle_t rtk_bhandle; /* bus space handle */ |
182 | bus_size_t rtk_bsize; /* bus space mapping size */ |
183 | u_int sc_quirk; /* chip quirks */ |
184 | #define RTKQ_8129 0x00000001 /* 8129 */ |
185 | #define RTKQ_8139CPLUS 0x00000002 /* 8139C+ */ |
186 | #define RTKQ_8169NONS 0x00000004 /* old non-single 8169 */ |
187 | #define RTKQ_PCIE 0x00000008 /* PCIe variants */ |
188 | #define RTKQ_MACLDPS 0x00000010 /* has LDPS register */ |
189 | #define RTKQ_DESCV2 0x00000020 /* has V2 TX/RX descriptor */ |
190 | #define RTKQ_NOJUMBO 0x00000040 /* no jumbo MTU support */ |
191 | #define RTKQ_NOEECMD 0x00000080 /* unusable EEPROM command */ |
192 | #define RTKQ_MACSTAT 0x00000100 /* set MACSTAT_DIS on init */ |
193 | #define RTKQ_CMDSTOP 0x00000200 /* set STOPREQ on stop */ |
194 | #define RTKQ_PHYWAKE_PM 0x00000400 /* wake PHY from power down */ |
195 | #define RTKQ_RXDV_GATED 0x00000800 |
196 | |
197 | bus_dma_tag_t sc_dmat; |
198 | |
199 | bus_dma_segment_t sc_dmaseg; /* for rtk(4) */ |
200 | int sc_dmanseg; /* for rtk(4) */ |
201 | |
202 | bus_dmamap_t recv_dmamap; /* for rtk(4) */ |
203 | uint8_t *rtk_rx_buf; |
204 | |
205 | struct rtk_tx_desc rtk_tx_descs[RTK_TX_LIST_CNT]; |
206 | SIMPLEQ_HEAD(, rtk_tx_desc) rtk_tx_free; |
207 | SIMPLEQ_HEAD(, rtk_tx_desc) rtk_tx_dirty; |
208 | |
209 | struct re_list_data re_ldata; |
210 | struct mbuf *re_head; |
211 | struct mbuf *re_tail; |
212 | uint32_t re_rxlenmask; |
213 | int re_testmode; |
214 | |
215 | int sc_flags; /* misc flags */ |
216 | #define RTK_ATTACHED 0x00000001 /* attach has succeeded */ |
217 | #define RTK_ENABLED 0x00000002 /* chip is enabled */ |
218 | #define RTK_IS_ENABLED(sc) ((sc)->sc_flags & RTK_ENABLED) |
219 | |
220 | int sc_txthresh; /* Early tx threshold */ |
221 | int sc_rev; /* MII revision */ |
222 | |
223 | /* Power management hooks. */ |
224 | int (*sc_enable) (struct rtk_softc *); |
225 | void (*sc_disable) (struct rtk_softc *); |
226 | |
227 | krndsource_t rnd_source; |
228 | }; |
229 | |
230 | #define RE_TX_DESC_CNT(sc) ((sc)->re_ldata.re_tx_desc_cnt) |
231 | #define RE_TX_LIST_SZ(sc) (RE_TX_DESC_CNT(sc) * sizeof(struct re_desc)) |
232 | #define RE_NEXT_TX_DESC(sc, x) (((x) + 1) & (RE_TX_DESC_CNT(sc) - 1)) |
233 | |
234 | #define RE_RX_LIST_SZ (RE_RX_DESC_CNT * sizeof(struct re_desc)) |
235 | #define RE_NEXT_RX_DESC(sc, x) (((x) + 1) & (RE_RX_DESC_CNT - 1)) |
236 | |
237 | #define RE_NEXT_TXQ(sc, x) (((x) + 1) & (RE_TX_QLEN - 1)) |
238 | |
239 | #define RE_TXDESCSYNC(sc, idx, ops) \ |
240 | bus_dmamap_sync((sc)->sc_dmat, \ |
241 | (sc)->re_ldata.re_tx_list_map, \ |
242 | sizeof(struct re_desc) * (idx), \ |
243 | sizeof(struct re_desc), \ |
244 | (ops)) |
245 | #define RE_RXDESCSYNC(sc, idx, ops) \ |
246 | bus_dmamap_sync((sc)->sc_dmat, \ |
247 | (sc)->re_ldata.re_rx_list_map, \ |
248 | sizeof(struct re_desc) * (idx), \ |
249 | sizeof(struct re_desc), \ |
250 | (ops)) |
251 | |
252 | /* |
253 | * re(4) hardware ip4csum-tx could be mangled with 28 byte or less IP packets |
254 | */ |
255 | #define RE_IP4CSUMTX_MINLEN 28 |
256 | #define RE_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RE_IP4CSUMTX_MINLEN) |
257 | /* |
258 | * XXX |
259 | * We are allocating pad DMA buffer after RX DMA descs for now |
260 | * because RE_TX_LIST_SZ(sc) always occupies whole page but |
261 | * RE_RX_LIST_SZ is less than PAGE_SIZE so there is some unused region. |
262 | */ |
263 | #define RE_RX_DMAMEM_SZ (RE_RX_LIST_SZ + RE_IP4CSUMTX_PADLEN) |
264 | #define RE_TXPADOFF RE_RX_LIST_SZ |
265 | #define RE_TXPADDADDR(sc) \ |
266 | ((sc)->re_ldata.re_rx_list_map->dm_segs[0].ds_addr + RE_TXPADOFF) |
267 | |
268 | |
269 | #define RTK_TXTH_MAX RTK_TXTH_1536 |
270 | |
271 | /* |
272 | * register space access macros |
273 | */ |
274 | #define CSR_WRITE_4(sc, reg, val) \ |
275 | bus_space_write_4(sc->rtk_btag, sc->rtk_bhandle, reg, val) |
276 | #define CSR_WRITE_2(sc, reg, val) \ |
277 | bus_space_write_2(sc->rtk_btag, sc->rtk_bhandle, reg, val) |
278 | #define CSR_WRITE_1(sc, reg, val) \ |
279 | bus_space_write_1(sc->rtk_btag, sc->rtk_bhandle, reg, val) |
280 | |
281 | #define CSR_READ_4(sc, reg) \ |
282 | bus_space_read_4(sc->rtk_btag, sc->rtk_bhandle, reg) |
283 | #define CSR_READ_2(sc, reg) \ |
284 | bus_space_read_2(sc->rtk_btag, sc->rtk_bhandle, reg) |
285 | #define CSR_READ_1(sc, reg) \ |
286 | bus_space_read_1(sc->rtk_btag, sc->rtk_bhandle, reg) |
287 | |
288 | #define RTK_TIMEOUT 1000 |
289 | |
290 | /* |
291 | * PCI low memory base and low I/O base registers |
292 | */ |
293 | |
294 | #define RTK_PCI_LOIO 0x10 |
295 | #define RTK_PCI_LOMEM 0x14 |
296 | |
297 | #ifdef _KERNEL |
298 | uint16_t rtk_read_eeprom(struct rtk_softc *, int, int); |
299 | void rtk_setmulti(struct rtk_softc *); |
300 | void rtk_attach(struct rtk_softc *); |
301 | int rtk_detach(struct rtk_softc *); |
302 | int rtk_activate(device_t, enum devact); |
303 | int rtk_intr(void *); |
304 | #endif /* _KERNEL */ |
305 | |