1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #include <linux/firmware.h> |
25 | #include "drmP.h" |
26 | #include "radeon.h" |
27 | #include "radeon_asic.h" |
28 | #include "radeon_ucode.h" |
29 | #include "cikd.h" |
30 | #include "r600_dpm.h" |
31 | #include "ci_dpm.h" |
32 | #include "atom.h" |
33 | #include <linux/seq_file.h> |
34 | |
35 | #define MC_CG_ARB_FREQ_F0 0x0a |
36 | #define MC_CG_ARB_FREQ_F1 0x0b |
37 | #define MC_CG_ARB_FREQ_F2 0x0c |
38 | #define MC_CG_ARB_FREQ_F3 0x0d |
39 | |
40 | #define SMC_RAM_END 0x40000 |
41 | |
42 | #define VOLTAGE_SCALE 4 |
43 | #define VOLTAGE_VID_OFFSET_SCALE1 625 |
44 | #define VOLTAGE_VID_OFFSET_SCALE2 100 |
45 | |
46 | static const struct ci_pt_defaults defaults_hawaii_xt = |
47 | { |
48 | 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000, |
49 | { 0x84, 0x0, 0x0, 0x7F, 0x0, 0x0, 0x5A, 0x60, 0x51, 0x8E, 0x79, 0x6B, 0x5F, 0x90, 0x79 }, |
50 | { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC } |
51 | }; |
52 | |
53 | static const struct ci_pt_defaults defaults_hawaii_pro = |
54 | { |
55 | 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062, |
56 | { 0x93, 0x0, 0x0, 0x97, 0x0, 0x0, 0x6B, 0x60, 0x51, 0x95, 0x79, 0x6B, 0x5F, 0x90, 0x79 }, |
57 | { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC } |
58 | }; |
59 | |
60 | static const struct ci_pt_defaults defaults_bonaire_xt = |
61 | { |
62 | 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, |
63 | { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 }, |
64 | { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } |
65 | }; |
66 | |
67 | static const struct ci_pt_defaults defaults_bonaire_pro __unused = |
68 | { |
69 | 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062, |
70 | { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F }, |
71 | { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB } |
72 | }; |
73 | |
74 | static const struct ci_pt_defaults defaults_saturn_xt = |
75 | { |
76 | 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000, |
77 | { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D }, |
78 | { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 } |
79 | }; |
80 | |
81 | static const struct ci_pt_defaults defaults_saturn_pro __unused = |
82 | { |
83 | 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000, |
84 | { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A }, |
85 | { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 } |
86 | }; |
87 | |
88 | static const struct ci_pt_config_reg didt_config_ci[] = |
89 | { |
90 | { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
91 | { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
92 | { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
93 | { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
94 | { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
95 | { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
96 | { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
97 | { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
98 | { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
99 | { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
100 | { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
101 | { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
102 | { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, |
103 | { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, |
104 | { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, |
105 | { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, |
106 | { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, |
107 | { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
108 | { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
109 | { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
110 | { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
111 | { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
112 | { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
113 | { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
114 | { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
115 | { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
116 | { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
117 | { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
118 | { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
119 | { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
120 | { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, |
121 | { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, |
122 | { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, |
123 | { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, |
124 | { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, |
125 | { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
126 | { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
127 | { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
128 | { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
129 | { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
130 | { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
131 | { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
132 | { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
133 | { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
134 | { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
135 | { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
136 | { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
137 | { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
138 | { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, |
139 | { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, |
140 | { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, |
141 | { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, |
142 | { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, |
143 | { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
144 | { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
145 | { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
146 | { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
147 | { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
148 | { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
149 | { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
150 | { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
151 | { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
152 | { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
153 | { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
154 | { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
155 | { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
156 | { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, |
157 | { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, |
158 | { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, |
159 | { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, |
160 | { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, |
161 | { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, |
162 | { 0xFFFFFFFF } |
163 | }; |
164 | |
165 | extern u8 rv770_get_memory_module_index(struct radeon_device *rdev); |
166 | extern void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table, |
167 | u32 *max_clock); |
168 | extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, |
169 | u32 arb_freq_src, u32 arb_freq_dest); |
170 | extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock); |
171 | extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode); |
172 | extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, |
173 | u32 max_voltage_steps, |
174 | struct atom_voltage_table *voltage_table); |
175 | extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev); |
176 | extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev); |
177 | extern int ci_mc_load_microcode(struct radeon_device *rdev); |
178 | extern void cik_update_cg(struct radeon_device *rdev, |
179 | u32 block, bool enable); |
180 | |
181 | static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, |
182 | struct atom_voltage_table_entry *voltage_table, |
183 | u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd); |
184 | static int ci_set_power_limit(struct radeon_device *rdev, u32 n); |
185 | #ifndef __NetBSD__ /* XXX unused? */ |
186 | static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, |
187 | u32 target_tdp); |
188 | #endif |
189 | static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate); |
190 | |
191 | static struct ci_power_info *ci_get_pi(struct radeon_device *rdev) |
192 | { |
193 | struct ci_power_info *pi = rdev->pm.dpm.priv; |
194 | |
195 | return pi; |
196 | } |
197 | |
198 | static struct ci_ps *ci_get_ps(struct radeon_ps *rps) |
199 | { |
200 | struct ci_ps *ps = rps->ps_priv; |
201 | |
202 | return ps; |
203 | } |
204 | |
205 | static void ci_initialize_powertune_defaults(struct radeon_device *rdev) |
206 | { |
207 | struct ci_power_info *pi = ci_get_pi(rdev); |
208 | |
209 | switch (rdev->pdev->device) { |
210 | case 0x6649: |
211 | case 0x6650: |
212 | case 0x6651: |
213 | case 0x6658: |
214 | case 0x665C: |
215 | case 0x665D: |
216 | default: |
217 | pi->powertune_defaults = &defaults_bonaire_xt; |
218 | break; |
219 | case 0x6640: |
220 | case 0x6641: |
221 | case 0x6646: |
222 | case 0x6647: |
223 | pi->powertune_defaults = &defaults_saturn_xt; |
224 | break; |
225 | case 0x67B8: |
226 | case 0x67B0: |
227 | pi->powertune_defaults = &defaults_hawaii_xt; |
228 | break; |
229 | case 0x67BA: |
230 | case 0x67B1: |
231 | pi->powertune_defaults = &defaults_hawaii_pro; |
232 | break; |
233 | case 0x67A0: |
234 | case 0x67A1: |
235 | case 0x67A2: |
236 | case 0x67A8: |
237 | case 0x67A9: |
238 | case 0x67AA: |
239 | case 0x67B9: |
240 | case 0x67BE: |
241 | pi->powertune_defaults = &defaults_bonaire_xt; |
242 | break; |
243 | } |
244 | |
245 | pi->dte_tj_offset = 0; |
246 | |
247 | pi->caps_power_containment = true; |
248 | pi->caps_cac = false; |
249 | pi->caps_sq_ramping = false; |
250 | pi->caps_db_ramping = false; |
251 | pi->caps_td_ramping = false; |
252 | pi->caps_tcp_ramping = false; |
253 | |
254 | if (pi->caps_power_containment) { |
255 | pi->caps_cac = true; |
256 | pi->enable_bapm_feature = true; |
257 | pi->enable_tdc_limit_feature = true; |
258 | pi->enable_pkg_pwr_tracking_feature = true; |
259 | } |
260 | } |
261 | |
262 | static u8 ci_convert_to_vid(u16 vddc) |
263 | { |
264 | return (6200 - (vddc * VOLTAGE_SCALE)) / 25; |
265 | } |
266 | |
267 | static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev) |
268 | { |
269 | struct ci_power_info *pi = ci_get_pi(rdev); |
270 | u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; |
271 | u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; |
272 | u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; |
273 | u32 i; |
274 | |
275 | if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) |
276 | return -EINVAL; |
277 | if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) |
278 | return -EINVAL; |
279 | if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != |
280 | rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) |
281 | return -EINVAL; |
282 | |
283 | for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { |
284 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { |
285 | lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); |
286 | hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); |
287 | hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); |
288 | } else { |
289 | lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); |
290 | hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); |
291 | } |
292 | } |
293 | return 0; |
294 | } |
295 | |
296 | static int ci_populate_vddc_vid(struct radeon_device *rdev) |
297 | { |
298 | struct ci_power_info *pi = ci_get_pi(rdev); |
299 | u8 *vid = pi->smc_powertune_table.VddCVid; |
300 | u32 i; |
301 | |
302 | if (pi->vddc_voltage_table.count > 8) |
303 | return -EINVAL; |
304 | |
305 | for (i = 0; i < pi->vddc_voltage_table.count; i++) |
306 | vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); |
307 | |
308 | return 0; |
309 | } |
310 | |
311 | static int ci_populate_svi_load_line(struct radeon_device *rdev) |
312 | { |
313 | struct ci_power_info *pi = ci_get_pi(rdev); |
314 | const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; |
315 | |
316 | pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; |
317 | pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; |
318 | pi->smc_powertune_table.SviLoadLineTrimVddC = 3; |
319 | pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; |
320 | |
321 | return 0; |
322 | } |
323 | |
324 | static int ci_populate_tdc_limit(struct radeon_device *rdev) |
325 | { |
326 | struct ci_power_info *pi = ci_get_pi(rdev); |
327 | const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; |
328 | u16 tdc_limit; |
329 | |
330 | tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; |
331 | pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); |
332 | pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = |
333 | pt_defaults->tdc_vddc_throttle_release_limit_perc; |
334 | pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; |
335 | |
336 | return 0; |
337 | } |
338 | |
339 | static int ci_populate_dw8(struct radeon_device *rdev) |
340 | { |
341 | struct ci_power_info *pi = ci_get_pi(rdev); |
342 | const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; |
343 | int ret; |
344 | |
345 | ret = ci_read_smc_sram_dword(rdev, |
346 | SMU7_FIRMWARE_HEADER_LOCATION + |
347 | offsetof(SMU7_Firmware_Header, PmFuseTable) + |
348 | offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl), |
349 | (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, |
350 | pi->sram_end); |
351 | if (ret) |
352 | return -EINVAL; |
353 | else |
354 | pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; |
355 | |
356 | return 0; |
357 | } |
358 | |
359 | static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev) |
360 | { |
361 | struct ci_power_info *pi = ci_get_pi(rdev); |
362 | u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; |
363 | u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; |
364 | int i, vmin, vmax; |
365 | |
366 | vmin = vmax = hi_vid[0]; |
367 | for (i = 0; i < 8; i++) { |
368 | if (0 != hi_vid[i]) { |
369 | if (vmin > hi_vid[i]) |
370 | vmin = hi_vid[i]; |
371 | if (vmax < hi_vid[i]) |
372 | vmax = hi_vid[i]; |
373 | } |
374 | |
375 | if (0 != lo_vid[i]) { |
376 | if (vmin > lo_vid[i]) |
377 | vmin = lo_vid[i]; |
378 | if (vmax < lo_vid[i]) |
379 | vmax = lo_vid[i]; |
380 | } |
381 | } |
382 | |
383 | if ((vmin == 0) || (vmax == 0)) |
384 | return -EINVAL; |
385 | pi->smc_powertune_table.GnbLPMLMaxVid = (u8)vmax; |
386 | pi->smc_powertune_table.GnbLPMLMinVid = (u8)vmin; |
387 | |
388 | return 0; |
389 | } |
390 | |
391 | static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev) |
392 | { |
393 | struct ci_power_info *pi = ci_get_pi(rdev); |
394 | u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; |
395 | u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; |
396 | struct radeon_cac_tdp_table *cac_tdp_table = |
397 | rdev->pm.dpm.dyn_state.cac_tdp_table; |
398 | |
399 | hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256; |
400 | lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256; |
401 | |
402 | pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); |
403 | pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); |
404 | |
405 | return 0; |
406 | } |
407 | |
408 | static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev) |
409 | { |
410 | struct ci_power_info *pi = ci_get_pi(rdev); |
411 | const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; |
412 | SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; |
413 | struct radeon_cac_tdp_table *cac_tdp_table = |
414 | rdev->pm.dpm.dyn_state.cac_tdp_table; |
415 | struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; |
416 | int i, j, k; |
417 | const u16 *def1; |
418 | const u16 *def2; |
419 | |
420 | dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; |
421 | dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; |
422 | |
423 | dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; |
424 | dpm_table->GpuTjMax = |
425 | (u8)(pi->thermal_temp_setting.temperature_high / 1000); |
426 | dpm_table->GpuTjHyst = 8; |
427 | |
428 | dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; |
429 | |
430 | if (ppm) { |
431 | dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); |
432 | dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); |
433 | } else { |
434 | dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); |
435 | dpm_table->PPM_TemperatureLimit = cpu_to_be16(0); |
436 | } |
437 | |
438 | dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient); |
439 | def1 = pt_defaults->bapmti_r; |
440 | def2 = pt_defaults->bapmti_rc; |
441 | |
442 | for (i = 0; i < SMU7_DTE_ITERATIONS; i++) { |
443 | for (j = 0; j < SMU7_DTE_SOURCES; j++) { |
444 | for (k = 0; k < SMU7_DTE_SINKS; k++) { |
445 | dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1); |
446 | dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2); |
447 | def1++; |
448 | def2++; |
449 | } |
450 | } |
451 | } |
452 | |
453 | return 0; |
454 | } |
455 | |
456 | static int ci_populate_pm_base(struct radeon_device *rdev) |
457 | { |
458 | struct ci_power_info *pi = ci_get_pi(rdev); |
459 | u32 pm_fuse_table_offset; |
460 | int ret; |
461 | |
462 | if (pi->caps_power_containment) { |
463 | ret = ci_read_smc_sram_dword(rdev, |
464 | SMU7_FIRMWARE_HEADER_LOCATION + |
465 | offsetof(SMU7_Firmware_Header, PmFuseTable), |
466 | &pm_fuse_table_offset, pi->sram_end); |
467 | if (ret) |
468 | return ret; |
469 | ret = ci_populate_bapm_vddc_vid_sidd(rdev); |
470 | if (ret) |
471 | return ret; |
472 | ret = ci_populate_vddc_vid(rdev); |
473 | if (ret) |
474 | return ret; |
475 | ret = ci_populate_svi_load_line(rdev); |
476 | if (ret) |
477 | return ret; |
478 | ret = ci_populate_tdc_limit(rdev); |
479 | if (ret) |
480 | return ret; |
481 | ret = ci_populate_dw8(rdev); |
482 | if (ret) |
483 | return ret; |
484 | ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev); |
485 | if (ret) |
486 | return ret; |
487 | ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev); |
488 | if (ret) |
489 | return ret; |
490 | ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset, |
491 | (u8 *)&pi->smc_powertune_table, |
492 | sizeof(SMU7_Discrete_PmFuses), pi->sram_end); |
493 | if (ret) |
494 | return ret; |
495 | } |
496 | |
497 | return 0; |
498 | } |
499 | |
500 | static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable) |
501 | { |
502 | struct ci_power_info *pi = ci_get_pi(rdev); |
503 | u32 data; |
504 | |
505 | if (pi->caps_sq_ramping) { |
506 | data = RREG32_DIDT(DIDT_SQ_CTRL0); |
507 | if (enable) |
508 | data |= DIDT_CTRL_EN; |
509 | else |
510 | data &= ~DIDT_CTRL_EN; |
511 | WREG32_DIDT(DIDT_SQ_CTRL0, data); |
512 | } |
513 | |
514 | if (pi->caps_db_ramping) { |
515 | data = RREG32_DIDT(DIDT_DB_CTRL0); |
516 | if (enable) |
517 | data |= DIDT_CTRL_EN; |
518 | else |
519 | data &= ~DIDT_CTRL_EN; |
520 | WREG32_DIDT(DIDT_DB_CTRL0, data); |
521 | } |
522 | |
523 | if (pi->caps_td_ramping) { |
524 | data = RREG32_DIDT(DIDT_TD_CTRL0); |
525 | if (enable) |
526 | data |= DIDT_CTRL_EN; |
527 | else |
528 | data &= ~DIDT_CTRL_EN; |
529 | WREG32_DIDT(DIDT_TD_CTRL0, data); |
530 | } |
531 | |
532 | if (pi->caps_tcp_ramping) { |
533 | data = RREG32_DIDT(DIDT_TCP_CTRL0); |
534 | if (enable) |
535 | data |= DIDT_CTRL_EN; |
536 | else |
537 | data &= ~DIDT_CTRL_EN; |
538 | WREG32_DIDT(DIDT_TCP_CTRL0, data); |
539 | } |
540 | } |
541 | |
542 | static int ci_program_pt_config_registers(struct radeon_device *rdev, |
543 | const struct ci_pt_config_reg *cac_config_regs) |
544 | { |
545 | const struct ci_pt_config_reg *config_regs = cac_config_regs; |
546 | u32 data; |
547 | u32 cache = 0; |
548 | |
549 | if (config_regs == NULL) |
550 | return -EINVAL; |
551 | |
552 | while (config_regs->offset != 0xFFFFFFFF) { |
553 | if (config_regs->type == CISLANDS_CONFIGREG_CACHE) { |
554 | cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); |
555 | } else { |
556 | switch (config_regs->type) { |
557 | case CISLANDS_CONFIGREG_SMC_IND: |
558 | data = RREG32_SMC(config_regs->offset); |
559 | break; |
560 | case CISLANDS_CONFIGREG_DIDT_IND: |
561 | data = RREG32_DIDT(config_regs->offset); |
562 | break; |
563 | default: |
564 | data = RREG32(config_regs->offset << 2); |
565 | break; |
566 | } |
567 | |
568 | data &= ~config_regs->mask; |
569 | data |= ((config_regs->value << config_regs->shift) & config_regs->mask); |
570 | data |= cache; |
571 | |
572 | switch (config_regs->type) { |
573 | case CISLANDS_CONFIGREG_SMC_IND: |
574 | WREG32_SMC(config_regs->offset, data); |
575 | break; |
576 | case CISLANDS_CONFIGREG_DIDT_IND: |
577 | WREG32_DIDT(config_regs->offset, data); |
578 | break; |
579 | default: |
580 | WREG32(config_regs->offset << 2, data); |
581 | break; |
582 | } |
583 | cache = 0; |
584 | } |
585 | config_regs++; |
586 | } |
587 | return 0; |
588 | } |
589 | |
590 | static int ci_enable_didt(struct radeon_device *rdev, bool enable) |
591 | { |
592 | struct ci_power_info *pi = ci_get_pi(rdev); |
593 | int ret; |
594 | |
595 | if (pi->caps_sq_ramping || pi->caps_db_ramping || |
596 | pi->caps_td_ramping || pi->caps_tcp_ramping) { |
597 | cik_enter_rlc_safe_mode(rdev); |
598 | |
599 | if (enable) { |
600 | ret = ci_program_pt_config_registers(rdev, didt_config_ci); |
601 | if (ret) { |
602 | cik_exit_rlc_safe_mode(rdev); |
603 | return ret; |
604 | } |
605 | } |
606 | |
607 | ci_do_enable_didt(rdev, enable); |
608 | |
609 | cik_exit_rlc_safe_mode(rdev); |
610 | } |
611 | |
612 | return 0; |
613 | } |
614 | |
615 | static int ci_enable_power_containment(struct radeon_device *rdev, bool enable) |
616 | { |
617 | struct ci_power_info *pi = ci_get_pi(rdev); |
618 | PPSMC_Result smc_result; |
619 | int ret = 0; |
620 | |
621 | if (enable) { |
622 | pi->power_containment_features = 0; |
623 | if (pi->caps_power_containment) { |
624 | if (pi->enable_bapm_feature) { |
625 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); |
626 | if (smc_result != PPSMC_Result_OK) |
627 | ret = -EINVAL; |
628 | else |
629 | pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; |
630 | } |
631 | |
632 | if (pi->enable_tdc_limit_feature) { |
633 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable); |
634 | if (smc_result != PPSMC_Result_OK) |
635 | ret = -EINVAL; |
636 | else |
637 | pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; |
638 | } |
639 | |
640 | if (pi->enable_pkg_pwr_tracking_feature) { |
641 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable); |
642 | if (smc_result != PPSMC_Result_OK) { |
643 | ret = -EINVAL; |
644 | } else { |
645 | struct radeon_cac_tdp_table *cac_tdp_table = |
646 | rdev->pm.dpm.dyn_state.cac_tdp_table; |
647 | u32 default_pwr_limit = |
648 | (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); |
649 | |
650 | pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; |
651 | |
652 | ci_set_power_limit(rdev, default_pwr_limit); |
653 | } |
654 | } |
655 | } |
656 | } else { |
657 | if (pi->caps_power_containment && pi->power_containment_features) { |
658 | if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) |
659 | ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable); |
660 | |
661 | if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) |
662 | ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); |
663 | |
664 | if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) |
665 | ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable); |
666 | pi->power_containment_features = 0; |
667 | } |
668 | } |
669 | |
670 | return ret; |
671 | } |
672 | |
673 | static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable) |
674 | { |
675 | struct ci_power_info *pi = ci_get_pi(rdev); |
676 | PPSMC_Result smc_result; |
677 | int ret = 0; |
678 | |
679 | if (pi->caps_cac) { |
680 | if (enable) { |
681 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); |
682 | if (smc_result != PPSMC_Result_OK) { |
683 | ret = -EINVAL; |
684 | pi->cac_enabled = false; |
685 | } else { |
686 | pi->cac_enabled = true; |
687 | } |
688 | } else if (pi->cac_enabled) { |
689 | ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); |
690 | pi->cac_enabled = false; |
691 | } |
692 | } |
693 | |
694 | return ret; |
695 | } |
696 | |
697 | #ifndef __NetBSD__ /* XXX unused? */ |
698 | static int ci_power_control_set_level(struct radeon_device *rdev) |
699 | { |
700 | struct ci_power_info *pi = ci_get_pi(rdev); |
701 | struct radeon_cac_tdp_table *cac_tdp_table = |
702 | rdev->pm.dpm.dyn_state.cac_tdp_table; |
703 | s32 adjust_percent; |
704 | s32 target_tdp; |
705 | int ret = 0; |
706 | bool adjust_polarity = false; /* ??? */ |
707 | |
708 | if (pi->caps_power_containment && |
709 | (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) { |
710 | adjust_percent = adjust_polarity ? |
711 | rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment); |
712 | target_tdp = ((100 + adjust_percent) * |
713 | (s32)cac_tdp_table->configurable_tdp) / 100; |
714 | target_tdp *= 256; |
715 | |
716 | ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp); |
717 | } |
718 | |
719 | return ret; |
720 | } |
721 | #endif |
722 | |
723 | void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate) |
724 | { |
725 | struct ci_power_info *pi = ci_get_pi(rdev); |
726 | |
727 | if (pi->uvd_power_gated == gate) |
728 | return; |
729 | |
730 | pi->uvd_power_gated = gate; |
731 | |
732 | ci_update_uvd_dpm(rdev, gate); |
733 | } |
734 | |
735 | bool ci_dpm_vblank_too_short(struct radeon_device *rdev) |
736 | { |
737 | struct ci_power_info *pi = ci_get_pi(rdev); |
738 | u32 vblank_time = r600_dpm_get_vblank_time(rdev); |
739 | u32 switch_limit = pi->mem_gddr5 ? 450 : 300; |
740 | |
741 | if (vblank_time < switch_limit) |
742 | return true; |
743 | else |
744 | return false; |
745 | |
746 | } |
747 | |
748 | static void ci_apply_state_adjust_rules(struct radeon_device *rdev, |
749 | struct radeon_ps *rps) |
750 | { |
751 | struct ci_ps *ps = ci_get_ps(rps); |
752 | struct ci_power_info *pi = ci_get_pi(rdev); |
753 | struct radeon_clock_and_voltage_limits *max_limits; |
754 | bool disable_mclk_switching; |
755 | u32 sclk, mclk; |
756 | u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; |
757 | int i; |
758 | |
759 | if (rps->vce_active) { |
760 | rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; |
761 | rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; |
762 | } else { |
763 | rps->evclk = 0; |
764 | rps->ecclk = 0; |
765 | } |
766 | |
767 | if ((rdev->pm.dpm.new_active_crtc_count > 1) || |
768 | ci_dpm_vblank_too_short(rdev)) |
769 | disable_mclk_switching = true; |
770 | else |
771 | disable_mclk_switching = false; |
772 | |
773 | if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) |
774 | pi->battery_state = true; |
775 | else |
776 | pi->battery_state = false; |
777 | |
778 | if (rdev->pm.dpm.ac_power) |
779 | max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
780 | else |
781 | max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; |
782 | |
783 | if (rdev->pm.dpm.ac_power == false) { |
784 | for (i = 0; i < ps->performance_level_count; i++) { |
785 | if (ps->performance_levels[i].mclk > max_limits->mclk) |
786 | ps->performance_levels[i].mclk = max_limits->mclk; |
787 | if (ps->performance_levels[i].sclk > max_limits->sclk) |
788 | ps->performance_levels[i].sclk = max_limits->sclk; |
789 | } |
790 | } |
791 | |
792 | /* limit clocks to max supported clocks based on voltage dependency tables */ |
793 | btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, |
794 | &max_sclk_vddc); |
795 | btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, |
796 | &max_mclk_vddci); |
797 | btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, |
798 | &max_mclk_vddc); |
799 | |
800 | for (i = 0; i < ps->performance_level_count; i++) { |
801 | if (max_sclk_vddc) { |
802 | if (ps->performance_levels[i].sclk > max_sclk_vddc) |
803 | ps->performance_levels[i].sclk = max_sclk_vddc; |
804 | } |
805 | if (max_mclk_vddci) { |
806 | if (ps->performance_levels[i].mclk > max_mclk_vddci) |
807 | ps->performance_levels[i].mclk = max_mclk_vddci; |
808 | } |
809 | if (max_mclk_vddc) { |
810 | if (ps->performance_levels[i].mclk > max_mclk_vddc) |
811 | ps->performance_levels[i].mclk = max_mclk_vddc; |
812 | } |
813 | } |
814 | |
815 | /* XXX validate the min clocks required for display */ |
816 | |
817 | if (disable_mclk_switching) { |
818 | mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; |
819 | sclk = ps->performance_levels[0].sclk; |
820 | } else { |
821 | mclk = ps->performance_levels[0].mclk; |
822 | sclk = ps->performance_levels[0].sclk; |
823 | } |
824 | |
825 | if (rps->vce_active) { |
826 | if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) |
827 | sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; |
828 | if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) |
829 | mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; |
830 | } |
831 | |
832 | ps->performance_levels[0].sclk = sclk; |
833 | ps->performance_levels[0].mclk = mclk; |
834 | |
835 | if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk) |
836 | ps->performance_levels[1].sclk = ps->performance_levels[0].sclk; |
837 | |
838 | if (disable_mclk_switching) { |
839 | if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk) |
840 | ps->performance_levels[0].mclk = ps->performance_levels[1].mclk; |
841 | } else { |
842 | if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk) |
843 | ps->performance_levels[1].mclk = ps->performance_levels[0].mclk; |
844 | } |
845 | } |
846 | |
847 | static int ci_set_thermal_temperature_range(struct radeon_device *rdev, |
848 | int min_temp, int max_temp) |
849 | { |
850 | int low_temp = 0 * 1000; |
851 | int high_temp = 255 * 1000; |
852 | u32 tmp; |
853 | |
854 | if (low_temp < min_temp) |
855 | low_temp = min_temp; |
856 | if (high_temp > max_temp) |
857 | high_temp = max_temp; |
858 | if (high_temp < low_temp) { |
859 | DRM_ERROR("invalid thermal range: %d - %d\n" , low_temp, high_temp); |
860 | return -EINVAL; |
861 | } |
862 | |
863 | tmp = RREG32_SMC(CG_THERMAL_INT); |
864 | tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK); |
865 | tmp |= CI_DIG_THERM_INTH(high_temp / 1000) | |
866 | CI_DIG_THERM_INTL(low_temp / 1000); |
867 | WREG32_SMC(CG_THERMAL_INT, tmp); |
868 | |
869 | #if 0 |
870 | /* XXX: need to figure out how to handle this properly */ |
871 | tmp = RREG32_SMC(CG_THERMAL_CTRL); |
872 | tmp &= DIG_THERM_DPM_MASK; |
873 | tmp |= DIG_THERM_DPM(high_temp / 1000); |
874 | WREG32_SMC(CG_THERMAL_CTRL, tmp); |
875 | #endif |
876 | |
877 | return 0; |
878 | } |
879 | |
880 | #if 0 |
881 | static int ci_read_smc_soft_register(struct radeon_device *rdev, |
882 | u16 reg_offset, u32 *value) |
883 | { |
884 | struct ci_power_info *pi = ci_get_pi(rdev); |
885 | |
886 | return ci_read_smc_sram_dword(rdev, |
887 | pi->soft_regs_start + reg_offset, |
888 | value, pi->sram_end); |
889 | } |
890 | #endif |
891 | |
892 | static int ci_write_smc_soft_register(struct radeon_device *rdev, |
893 | u16 reg_offset, u32 value) |
894 | { |
895 | struct ci_power_info *pi = ci_get_pi(rdev); |
896 | |
897 | return ci_write_smc_sram_dword(rdev, |
898 | pi->soft_regs_start + reg_offset, |
899 | value, pi->sram_end); |
900 | } |
901 | |
902 | static void ci_init_fps_limits(struct radeon_device *rdev) |
903 | { |
904 | struct ci_power_info *pi = ci_get_pi(rdev); |
905 | SMU7_Discrete_DpmTable *table = &pi->smc_state_table; |
906 | |
907 | if (pi->caps_fps) { |
908 | u16 tmp; |
909 | |
910 | tmp = 45; |
911 | table->FpsHighT = cpu_to_be16(tmp); |
912 | |
913 | tmp = 30; |
914 | table->FpsLowT = cpu_to_be16(tmp); |
915 | } |
916 | } |
917 | |
918 | static int ci_update_sclk_t(struct radeon_device *rdev) |
919 | { |
920 | struct ci_power_info *pi = ci_get_pi(rdev); |
921 | int ret = 0; |
922 | u32 low_sclk_interrupt_t = 0; |
923 | |
924 | if (pi->caps_sclk_throttle_low_notification) { |
925 | low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); |
926 | |
927 | ret = ci_copy_bytes_to_smc(rdev, |
928 | pi->dpm_table_start + |
929 | offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT), |
930 | (u8 *)&low_sclk_interrupt_t, |
931 | sizeof(u32), pi->sram_end); |
932 | |
933 | } |
934 | |
935 | return ret; |
936 | } |
937 | |
938 | static void ci_get_leakage_voltages(struct radeon_device *rdev) |
939 | { |
940 | struct ci_power_info *pi = ci_get_pi(rdev); |
941 | u16 leakage_id, virtual_voltage_id; |
942 | u16 vddc, vddci; |
943 | int i; |
944 | |
945 | pi->vddc_leakage.count = 0; |
946 | pi->vddci_leakage.count = 0; |
947 | |
948 | if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) { |
949 | for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { |
950 | virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; |
951 | if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci, |
952 | virtual_voltage_id, |
953 | leakage_id) == 0) { |
954 | if (vddc != 0 && vddc != virtual_voltage_id) { |
955 | pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; |
956 | pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; |
957 | pi->vddc_leakage.count++; |
958 | } |
959 | if (vddci != 0 && vddci != virtual_voltage_id) { |
960 | pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; |
961 | pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; |
962 | pi->vddci_leakage.count++; |
963 | } |
964 | } |
965 | } |
966 | } |
967 | } |
968 | |
969 | static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) |
970 | { |
971 | struct ci_power_info *pi = ci_get_pi(rdev); |
972 | bool want_thermal_protection; |
973 | enum radeon_dpm_event_src dpm_event_src; |
974 | u32 tmp; |
975 | |
976 | switch (sources) { |
977 | case 0: |
978 | default: |
979 | want_thermal_protection = false; |
980 | break; |
981 | case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): |
982 | want_thermal_protection = true; |
983 | dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; |
984 | break; |
985 | case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): |
986 | want_thermal_protection = true; |
987 | dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; |
988 | break; |
989 | case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | |
990 | (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): |
991 | want_thermal_protection = true; |
992 | dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; |
993 | break; |
994 | } |
995 | |
996 | if (want_thermal_protection) { |
997 | #if 0 |
998 | /* XXX: need to figure out how to handle this properly */ |
999 | tmp = RREG32_SMC(CG_THERMAL_CTRL); |
1000 | tmp &= DPM_EVENT_SRC_MASK; |
1001 | tmp |= DPM_EVENT_SRC(dpm_event_src); |
1002 | WREG32_SMC(CG_THERMAL_CTRL, tmp); |
1003 | #else |
1004 | (void)dpm_event_src; |
1005 | #endif |
1006 | |
1007 | tmp = RREG32_SMC(GENERAL_PWRMGT); |
1008 | if (pi->thermal_protection) |
1009 | tmp &= ~THERMAL_PROTECTION_DIS; |
1010 | else |
1011 | tmp |= THERMAL_PROTECTION_DIS; |
1012 | WREG32_SMC(GENERAL_PWRMGT, tmp); |
1013 | } else { |
1014 | tmp = RREG32_SMC(GENERAL_PWRMGT); |
1015 | tmp |= THERMAL_PROTECTION_DIS; |
1016 | WREG32_SMC(GENERAL_PWRMGT, tmp); |
1017 | } |
1018 | } |
1019 | |
1020 | static void ci_enable_auto_throttle_source(struct radeon_device *rdev, |
1021 | enum radeon_dpm_auto_throttle_src source, |
1022 | bool enable) |
1023 | { |
1024 | struct ci_power_info *pi = ci_get_pi(rdev); |
1025 | |
1026 | if (enable) { |
1027 | if (!(pi->active_auto_throttle_sources & (1 << source))) { |
1028 | pi->active_auto_throttle_sources |= 1 << source; |
1029 | ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); |
1030 | } |
1031 | } else { |
1032 | if (pi->active_auto_throttle_sources & (1 << source)) { |
1033 | pi->active_auto_throttle_sources &= ~(1 << source); |
1034 | ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); |
1035 | } |
1036 | } |
1037 | } |
1038 | |
1039 | static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev) |
1040 | { |
1041 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) |
1042 | ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt); |
1043 | } |
1044 | |
1045 | static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev) |
1046 | { |
1047 | struct ci_power_info *pi = ci_get_pi(rdev); |
1048 | PPSMC_Result smc_result; |
1049 | |
1050 | if (!pi->need_update_smu7_dpm_table) |
1051 | return 0; |
1052 | |
1053 | if ((!pi->sclk_dpm_key_disabled) && |
1054 | (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { |
1055 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel); |
1056 | if (smc_result != PPSMC_Result_OK) |
1057 | return -EINVAL; |
1058 | } |
1059 | |
1060 | if ((!pi->mclk_dpm_key_disabled) && |
1061 | (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { |
1062 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel); |
1063 | if (smc_result != PPSMC_Result_OK) |
1064 | return -EINVAL; |
1065 | } |
1066 | |
1067 | pi->need_update_smu7_dpm_table = 0; |
1068 | return 0; |
1069 | } |
1070 | |
1071 | static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable) |
1072 | { |
1073 | struct ci_power_info *pi = ci_get_pi(rdev); |
1074 | PPSMC_Result smc_result; |
1075 | |
1076 | if (enable) { |
1077 | if (!pi->sclk_dpm_key_disabled) { |
1078 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable); |
1079 | if (smc_result != PPSMC_Result_OK) |
1080 | return -EINVAL; |
1081 | } |
1082 | |
1083 | if (!pi->mclk_dpm_key_disabled) { |
1084 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable); |
1085 | if (smc_result != PPSMC_Result_OK) |
1086 | return -EINVAL; |
1087 | |
1088 | WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN); |
1089 | |
1090 | WREG32_SMC(LCAC_MC0_CNTL, 0x05); |
1091 | WREG32_SMC(LCAC_MC1_CNTL, 0x05); |
1092 | WREG32_SMC(LCAC_CPL_CNTL, 0x100005); |
1093 | |
1094 | udelay(10); |
1095 | |
1096 | WREG32_SMC(LCAC_MC0_CNTL, 0x400005); |
1097 | WREG32_SMC(LCAC_MC1_CNTL, 0x400005); |
1098 | WREG32_SMC(LCAC_CPL_CNTL, 0x500005); |
1099 | } |
1100 | } else { |
1101 | if (!pi->sclk_dpm_key_disabled) { |
1102 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable); |
1103 | if (smc_result != PPSMC_Result_OK) |
1104 | return -EINVAL; |
1105 | } |
1106 | |
1107 | if (!pi->mclk_dpm_key_disabled) { |
1108 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable); |
1109 | if (smc_result != PPSMC_Result_OK) |
1110 | return -EINVAL; |
1111 | } |
1112 | } |
1113 | |
1114 | return 0; |
1115 | } |
1116 | |
1117 | static int ci_start_dpm(struct radeon_device *rdev) |
1118 | { |
1119 | struct ci_power_info *pi = ci_get_pi(rdev); |
1120 | PPSMC_Result smc_result; |
1121 | int ret; |
1122 | u32 tmp; |
1123 | |
1124 | tmp = RREG32_SMC(GENERAL_PWRMGT); |
1125 | tmp |= GLOBAL_PWRMGT_EN; |
1126 | WREG32_SMC(GENERAL_PWRMGT, tmp); |
1127 | |
1128 | tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); |
1129 | tmp |= DYNAMIC_PM_EN; |
1130 | WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); |
1131 | |
1132 | ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000); |
1133 | |
1134 | WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN); |
1135 | |
1136 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable); |
1137 | if (smc_result != PPSMC_Result_OK) |
1138 | return -EINVAL; |
1139 | |
1140 | ret = ci_enable_sclk_mclk_dpm(rdev, true); |
1141 | if (ret) |
1142 | return ret; |
1143 | |
1144 | if (!pi->pcie_dpm_key_disabled) { |
1145 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable); |
1146 | if (smc_result != PPSMC_Result_OK) |
1147 | return -EINVAL; |
1148 | } |
1149 | |
1150 | return 0; |
1151 | } |
1152 | |
1153 | static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev) |
1154 | { |
1155 | struct ci_power_info *pi = ci_get_pi(rdev); |
1156 | PPSMC_Result smc_result; |
1157 | |
1158 | if (!pi->need_update_smu7_dpm_table) |
1159 | return 0; |
1160 | |
1161 | if ((!pi->sclk_dpm_key_disabled) && |
1162 | (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { |
1163 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel); |
1164 | if (smc_result != PPSMC_Result_OK) |
1165 | return -EINVAL; |
1166 | } |
1167 | |
1168 | if ((!pi->mclk_dpm_key_disabled) && |
1169 | (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { |
1170 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel); |
1171 | if (smc_result != PPSMC_Result_OK) |
1172 | return -EINVAL; |
1173 | } |
1174 | |
1175 | return 0; |
1176 | } |
1177 | |
1178 | static int ci_stop_dpm(struct radeon_device *rdev) |
1179 | { |
1180 | struct ci_power_info *pi = ci_get_pi(rdev); |
1181 | PPSMC_Result smc_result; |
1182 | int ret; |
1183 | u32 tmp; |
1184 | |
1185 | tmp = RREG32_SMC(GENERAL_PWRMGT); |
1186 | tmp &= ~GLOBAL_PWRMGT_EN; |
1187 | WREG32_SMC(GENERAL_PWRMGT, tmp); |
1188 | |
1189 | tmp = RREG32(SCLK_PWRMGT_CNTL); |
1190 | tmp &= ~DYNAMIC_PM_EN; |
1191 | WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); |
1192 | |
1193 | if (!pi->pcie_dpm_key_disabled) { |
1194 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable); |
1195 | if (smc_result != PPSMC_Result_OK) |
1196 | return -EINVAL; |
1197 | } |
1198 | |
1199 | ret = ci_enable_sclk_mclk_dpm(rdev, false); |
1200 | if (ret) |
1201 | return ret; |
1202 | |
1203 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable); |
1204 | if (smc_result != PPSMC_Result_OK) |
1205 | return -EINVAL; |
1206 | |
1207 | return 0; |
1208 | } |
1209 | |
1210 | static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable) |
1211 | { |
1212 | u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); |
1213 | |
1214 | if (enable) |
1215 | tmp &= ~SCLK_PWRMGT_OFF; |
1216 | else |
1217 | tmp |= SCLK_PWRMGT_OFF; |
1218 | WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); |
1219 | } |
1220 | |
1221 | #if 0 |
1222 | static int ci_notify_hw_of_power_source(struct radeon_device *rdev, |
1223 | bool ac_power) |
1224 | { |
1225 | struct ci_power_info *pi = ci_get_pi(rdev); |
1226 | struct radeon_cac_tdp_table *cac_tdp_table = |
1227 | rdev->pm.dpm.dyn_state.cac_tdp_table; |
1228 | u32 power_limit; |
1229 | |
1230 | if (ac_power) |
1231 | power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); |
1232 | else |
1233 | power_limit = (u32)(cac_tdp_table->battery_power_limit * 256); |
1234 | |
1235 | ci_set_power_limit(rdev, power_limit); |
1236 | |
1237 | if (pi->caps_automatic_dc_transition) { |
1238 | if (ac_power) |
1239 | ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC); |
1240 | else |
1241 | ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp); |
1242 | } |
1243 | |
1244 | return 0; |
1245 | } |
1246 | #endif |
1247 | |
1248 | static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev, |
1249 | PPSMC_Msg msg, u32 parameter) |
1250 | { |
1251 | WREG32(SMC_MSG_ARG_0, parameter); |
1252 | return ci_send_msg_to_smc(rdev, msg); |
1253 | } |
1254 | |
1255 | #ifndef __NetBSD__ /* XXX unused? */ |
1256 | static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev, |
1257 | PPSMC_Msg msg, u32 *parameter) |
1258 | { |
1259 | PPSMC_Result smc_result; |
1260 | |
1261 | smc_result = ci_send_msg_to_smc(rdev, msg); |
1262 | |
1263 | if ((smc_result == PPSMC_Result_OK) && parameter) |
1264 | *parameter = RREG32(SMC_MSG_ARG_0); |
1265 | |
1266 | return smc_result; |
1267 | } |
1268 | #endif |
1269 | |
1270 | static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n) |
1271 | { |
1272 | struct ci_power_info *pi = ci_get_pi(rdev); |
1273 | |
1274 | if (!pi->sclk_dpm_key_disabled) { |
1275 | PPSMC_Result smc_result = |
1276 | ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, n); |
1277 | if (smc_result != PPSMC_Result_OK) |
1278 | return -EINVAL; |
1279 | } |
1280 | |
1281 | return 0; |
1282 | } |
1283 | |
1284 | static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n) |
1285 | { |
1286 | struct ci_power_info *pi = ci_get_pi(rdev); |
1287 | |
1288 | if (!pi->mclk_dpm_key_disabled) { |
1289 | PPSMC_Result smc_result = |
1290 | ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_ForceState, n); |
1291 | if (smc_result != PPSMC_Result_OK) |
1292 | return -EINVAL; |
1293 | } |
1294 | |
1295 | return 0; |
1296 | } |
1297 | |
1298 | static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n) |
1299 | { |
1300 | struct ci_power_info *pi = ci_get_pi(rdev); |
1301 | |
1302 | if (!pi->pcie_dpm_key_disabled) { |
1303 | PPSMC_Result smc_result = |
1304 | ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n); |
1305 | if (smc_result != PPSMC_Result_OK) |
1306 | return -EINVAL; |
1307 | } |
1308 | |
1309 | return 0; |
1310 | } |
1311 | |
1312 | static int ci_set_power_limit(struct radeon_device *rdev, u32 n) |
1313 | { |
1314 | struct ci_power_info *pi = ci_get_pi(rdev); |
1315 | |
1316 | if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { |
1317 | PPSMC_Result smc_result = |
1318 | ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n); |
1319 | if (smc_result != PPSMC_Result_OK) |
1320 | return -EINVAL; |
1321 | } |
1322 | |
1323 | return 0; |
1324 | } |
1325 | |
1326 | #ifndef __NetBSD__ /* XXX unused? */ |
1327 | static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, |
1328 | u32 target_tdp) |
1329 | { |
1330 | PPSMC_Result smc_result = |
1331 | ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); |
1332 | if (smc_result != PPSMC_Result_OK) |
1333 | return -EINVAL; |
1334 | return 0; |
1335 | } |
1336 | |
1337 | static int ci_set_boot_state(struct radeon_device *rdev) |
1338 | { |
1339 | return ci_enable_sclk_mclk_dpm(rdev, false); |
1340 | } |
1341 | #endif |
1342 | |
1343 | #ifdef CONFIG_DEBUG_FS |
1344 | static u32 ci_get_average_sclk_freq(struct radeon_device *rdev) |
1345 | { |
1346 | u32 sclk_freq; |
1347 | PPSMC_Result smc_result = |
1348 | ci_send_msg_to_smc_return_parameter(rdev, |
1349 | PPSMC_MSG_API_GetSclkFrequency, |
1350 | &sclk_freq); |
1351 | if (smc_result != PPSMC_Result_OK) |
1352 | sclk_freq = 0; |
1353 | |
1354 | return sclk_freq; |
1355 | } |
1356 | |
1357 | static u32 ci_get_average_mclk_freq(struct radeon_device *rdev) |
1358 | { |
1359 | u32 mclk_freq; |
1360 | PPSMC_Result smc_result = |
1361 | ci_send_msg_to_smc_return_parameter(rdev, |
1362 | PPSMC_MSG_API_GetMclkFrequency, |
1363 | &mclk_freq); |
1364 | if (smc_result != PPSMC_Result_OK) |
1365 | mclk_freq = 0; |
1366 | |
1367 | return mclk_freq; |
1368 | } |
1369 | #endif |
1370 | |
1371 | static void ci_dpm_start_smc(struct radeon_device *rdev) |
1372 | { |
1373 | int i; |
1374 | |
1375 | ci_program_jump_on_start(rdev); |
1376 | ci_start_smc_clock(rdev); |
1377 | ci_start_smc(rdev); |
1378 | for (i = 0; i < rdev->usec_timeout; i++) { |
1379 | if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED) |
1380 | break; |
1381 | } |
1382 | } |
1383 | |
1384 | static void ci_dpm_stop_smc(struct radeon_device *rdev) |
1385 | { |
1386 | ci_reset_smc(rdev); |
1387 | ci_stop_smc_clock(rdev); |
1388 | } |
1389 | |
1390 | static int (struct radeon_device *rdev) |
1391 | { |
1392 | struct ci_power_info *pi = ci_get_pi(rdev); |
1393 | u32 tmp; |
1394 | int ret; |
1395 | |
1396 | ret = ci_read_smc_sram_dword(rdev, |
1397 | SMU7_FIRMWARE_HEADER_LOCATION + |
1398 | offsetof(SMU7_Firmware_Header, DpmTable), |
1399 | &tmp, pi->sram_end); |
1400 | if (ret) |
1401 | return ret; |
1402 | |
1403 | pi->dpm_table_start = tmp; |
1404 | |
1405 | ret = ci_read_smc_sram_dword(rdev, |
1406 | SMU7_FIRMWARE_HEADER_LOCATION + |
1407 | offsetof(SMU7_Firmware_Header, SoftRegisters), |
1408 | &tmp, pi->sram_end); |
1409 | if (ret) |
1410 | return ret; |
1411 | |
1412 | pi->soft_regs_start = tmp; |
1413 | |
1414 | ret = ci_read_smc_sram_dword(rdev, |
1415 | SMU7_FIRMWARE_HEADER_LOCATION + |
1416 | offsetof(SMU7_Firmware_Header, mcRegisterTable), |
1417 | &tmp, pi->sram_end); |
1418 | if (ret) |
1419 | return ret; |
1420 | |
1421 | pi->mc_reg_table_start = tmp; |
1422 | |
1423 | ret = ci_read_smc_sram_dword(rdev, |
1424 | SMU7_FIRMWARE_HEADER_LOCATION + |
1425 | offsetof(SMU7_Firmware_Header, FanTable), |
1426 | &tmp, pi->sram_end); |
1427 | if (ret) |
1428 | return ret; |
1429 | |
1430 | pi->fan_table_start = tmp; |
1431 | |
1432 | ret = ci_read_smc_sram_dword(rdev, |
1433 | SMU7_FIRMWARE_HEADER_LOCATION + |
1434 | offsetof(SMU7_Firmware_Header, mcArbDramTimingTable), |
1435 | &tmp, pi->sram_end); |
1436 | if (ret) |
1437 | return ret; |
1438 | |
1439 | pi->arb_table_start = tmp; |
1440 | |
1441 | return 0; |
1442 | } |
1443 | |
1444 | static void ci_read_clock_registers(struct radeon_device *rdev) |
1445 | { |
1446 | struct ci_power_info *pi = ci_get_pi(rdev); |
1447 | |
1448 | pi->clock_registers.cg_spll_func_cntl = |
1449 | RREG32_SMC(CG_SPLL_FUNC_CNTL); |
1450 | pi->clock_registers.cg_spll_func_cntl_2 = |
1451 | RREG32_SMC(CG_SPLL_FUNC_CNTL_2); |
1452 | pi->clock_registers.cg_spll_func_cntl_3 = |
1453 | RREG32_SMC(CG_SPLL_FUNC_CNTL_3); |
1454 | pi->clock_registers.cg_spll_func_cntl_4 = |
1455 | RREG32_SMC(CG_SPLL_FUNC_CNTL_4); |
1456 | pi->clock_registers.cg_spll_spread_spectrum = |
1457 | RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); |
1458 | pi->clock_registers.cg_spll_spread_spectrum_2 = |
1459 | RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2); |
1460 | pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); |
1461 | pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); |
1462 | pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); |
1463 | pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); |
1464 | pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); |
1465 | pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); |
1466 | pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); |
1467 | pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); |
1468 | pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); |
1469 | } |
1470 | |
1471 | static void ci_init_sclk_t(struct radeon_device *rdev) |
1472 | { |
1473 | struct ci_power_info *pi = ci_get_pi(rdev); |
1474 | |
1475 | pi->low_sclk_interrupt_t = 0; |
1476 | } |
1477 | |
1478 | static void ci_enable_thermal_protection(struct radeon_device *rdev, |
1479 | bool enable) |
1480 | { |
1481 | u32 tmp = RREG32_SMC(GENERAL_PWRMGT); |
1482 | |
1483 | if (enable) |
1484 | tmp &= ~THERMAL_PROTECTION_DIS; |
1485 | else |
1486 | tmp |= THERMAL_PROTECTION_DIS; |
1487 | WREG32_SMC(GENERAL_PWRMGT, tmp); |
1488 | } |
1489 | |
1490 | static void ci_enable_acpi_power_management(struct radeon_device *rdev) |
1491 | { |
1492 | u32 tmp = RREG32_SMC(GENERAL_PWRMGT); |
1493 | |
1494 | tmp |= STATIC_PM_EN; |
1495 | |
1496 | WREG32_SMC(GENERAL_PWRMGT, tmp); |
1497 | } |
1498 | |
1499 | #if 0 |
1500 | static int ci_enter_ulp_state(struct radeon_device *rdev) |
1501 | { |
1502 | |
1503 | WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); |
1504 | |
1505 | udelay(25000); |
1506 | |
1507 | return 0; |
1508 | } |
1509 | |
1510 | static int ci_exit_ulp_state(struct radeon_device *rdev) |
1511 | { |
1512 | int i; |
1513 | |
1514 | WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); |
1515 | |
1516 | udelay(7000); |
1517 | |
1518 | for (i = 0; i < rdev->usec_timeout; i++) { |
1519 | if (RREG32(SMC_RESP_0) == 1) |
1520 | break; |
1521 | udelay(1000); |
1522 | } |
1523 | |
1524 | return 0; |
1525 | } |
1526 | #endif |
1527 | |
1528 | static int ci_notify_smc_display_change(struct radeon_device *rdev, |
1529 | bool has_display) |
1530 | { |
1531 | PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; |
1532 | |
1533 | return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL; |
1534 | } |
1535 | |
1536 | static int ci_enable_ds_master_switch(struct radeon_device *rdev, |
1537 | bool enable) |
1538 | { |
1539 | struct ci_power_info *pi = ci_get_pi(rdev); |
1540 | |
1541 | if (enable) { |
1542 | if (pi->caps_sclk_ds) { |
1543 | if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK) |
1544 | return -EINVAL; |
1545 | } else { |
1546 | if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) |
1547 | return -EINVAL; |
1548 | } |
1549 | } else { |
1550 | if (pi->caps_sclk_ds) { |
1551 | if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) |
1552 | return -EINVAL; |
1553 | } |
1554 | } |
1555 | |
1556 | return 0; |
1557 | } |
1558 | |
1559 | static void ci_program_display_gap(struct radeon_device *rdev) |
1560 | { |
1561 | u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); |
1562 | u32 pre_vbi_time_in_us; |
1563 | u32 frame_time_in_us; |
1564 | u32 ref_clock = rdev->clock.spll.reference_freq; |
1565 | u32 refresh_rate = r600_dpm_get_vrefresh(rdev); |
1566 | u32 vblank_time = r600_dpm_get_vblank_time(rdev); |
1567 | |
1568 | tmp &= ~DISP_GAP_MASK; |
1569 | if (rdev->pm.dpm.new_active_crtc_count > 0) |
1570 | tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); |
1571 | else |
1572 | tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE); |
1573 | WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); |
1574 | |
1575 | if (refresh_rate == 0) |
1576 | refresh_rate = 60; |
1577 | if (vblank_time == 0xffffffff) |
1578 | vblank_time = 500; |
1579 | frame_time_in_us = 1000000 / refresh_rate; |
1580 | pre_vbi_time_in_us = |
1581 | frame_time_in_us - 200 - vblank_time; |
1582 | tmp = pre_vbi_time_in_us * (ref_clock / 100); |
1583 | |
1584 | WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp); |
1585 | ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64); |
1586 | ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); |
1587 | |
1588 | |
1589 | ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1)); |
1590 | |
1591 | } |
1592 | |
1593 | static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable) |
1594 | { |
1595 | struct ci_power_info *pi = ci_get_pi(rdev); |
1596 | u32 tmp; |
1597 | |
1598 | if (enable) { |
1599 | if (pi->caps_sclk_ss_support) { |
1600 | tmp = RREG32_SMC(GENERAL_PWRMGT); |
1601 | tmp |= DYN_SPREAD_SPECTRUM_EN; |
1602 | WREG32_SMC(GENERAL_PWRMGT, tmp); |
1603 | } |
1604 | } else { |
1605 | tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); |
1606 | tmp &= ~SSEN; |
1607 | WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp); |
1608 | |
1609 | tmp = RREG32_SMC(GENERAL_PWRMGT); |
1610 | tmp &= ~DYN_SPREAD_SPECTRUM_EN; |
1611 | WREG32_SMC(GENERAL_PWRMGT, tmp); |
1612 | } |
1613 | } |
1614 | |
1615 | static void ci_program_sstp(struct radeon_device *rdev) |
1616 | { |
1617 | WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); |
1618 | } |
1619 | |
1620 | static void ci_enable_display_gap(struct radeon_device *rdev) |
1621 | { |
1622 | u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); |
1623 | |
1624 | tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK); |
1625 | tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) | |
1626 | DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK)); |
1627 | |
1628 | WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); |
1629 | } |
1630 | |
1631 | static void ci_program_vc(struct radeon_device *rdev) |
1632 | { |
1633 | u32 tmp; |
1634 | |
1635 | tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); |
1636 | tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT); |
1637 | WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); |
1638 | |
1639 | WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0); |
1640 | WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1); |
1641 | WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2); |
1642 | WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3); |
1643 | WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4); |
1644 | WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5); |
1645 | WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6); |
1646 | WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7); |
1647 | } |
1648 | |
1649 | static void ci_clear_vc(struct radeon_device *rdev) |
1650 | { |
1651 | u32 tmp; |
1652 | |
1653 | tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); |
1654 | tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT); |
1655 | WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); |
1656 | |
1657 | WREG32_SMC(CG_FTV_0, 0); |
1658 | WREG32_SMC(CG_FTV_1, 0); |
1659 | WREG32_SMC(CG_FTV_2, 0); |
1660 | WREG32_SMC(CG_FTV_3, 0); |
1661 | WREG32_SMC(CG_FTV_4, 0); |
1662 | WREG32_SMC(CG_FTV_5, 0); |
1663 | WREG32_SMC(CG_FTV_6, 0); |
1664 | WREG32_SMC(CG_FTV_7, 0); |
1665 | } |
1666 | |
1667 | static int ci_upload_firmware(struct radeon_device *rdev) |
1668 | { |
1669 | struct ci_power_info *pi = ci_get_pi(rdev); |
1670 | int i, ret; |
1671 | |
1672 | for (i = 0; i < rdev->usec_timeout; i++) { |
1673 | if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE) |
1674 | break; |
1675 | } |
1676 | WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1); |
1677 | |
1678 | ci_stop_smc_clock(rdev); |
1679 | ci_reset_smc(rdev); |
1680 | |
1681 | ret = ci_load_smc_ucode(rdev, pi->sram_end); |
1682 | |
1683 | return ret; |
1684 | |
1685 | } |
1686 | |
1687 | static int ci_get_svi2_voltage_table(struct radeon_device *rdev, |
1688 | struct radeon_clock_voltage_dependency_table *voltage_dependency_table, |
1689 | struct atom_voltage_table *voltage_table) |
1690 | { |
1691 | u32 i; |
1692 | |
1693 | if (voltage_dependency_table == NULL) |
1694 | return -EINVAL; |
1695 | |
1696 | voltage_table->mask_low = 0; |
1697 | voltage_table->phase_delay = 0; |
1698 | |
1699 | voltage_table->count = voltage_dependency_table->count; |
1700 | for (i = 0; i < voltage_table->count; i++) { |
1701 | voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; |
1702 | voltage_table->entries[i].smio_low = 0; |
1703 | } |
1704 | |
1705 | return 0; |
1706 | } |
1707 | |
1708 | static int ci_construct_voltage_tables(struct radeon_device *rdev) |
1709 | { |
1710 | struct ci_power_info *pi = ci_get_pi(rdev); |
1711 | int ret; |
1712 | |
1713 | if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { |
1714 | ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, |
1715 | VOLTAGE_OBJ_GPIO_LUT, |
1716 | &pi->vddc_voltage_table); |
1717 | if (ret) |
1718 | return ret; |
1719 | } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { |
1720 | ret = ci_get_svi2_voltage_table(rdev, |
1721 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, |
1722 | &pi->vddc_voltage_table); |
1723 | if (ret) |
1724 | return ret; |
1725 | } |
1726 | |
1727 | if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) |
1728 | si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC, |
1729 | &pi->vddc_voltage_table); |
1730 | |
1731 | if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { |
1732 | ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, |
1733 | VOLTAGE_OBJ_GPIO_LUT, |
1734 | &pi->vddci_voltage_table); |
1735 | if (ret) |
1736 | return ret; |
1737 | } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { |
1738 | ret = ci_get_svi2_voltage_table(rdev, |
1739 | &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, |
1740 | &pi->vddci_voltage_table); |
1741 | if (ret) |
1742 | return ret; |
1743 | } |
1744 | |
1745 | if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) |
1746 | si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI, |
1747 | &pi->vddci_voltage_table); |
1748 | |
1749 | if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { |
1750 | ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, |
1751 | VOLTAGE_OBJ_GPIO_LUT, |
1752 | &pi->mvdd_voltage_table); |
1753 | if (ret) |
1754 | return ret; |
1755 | } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { |
1756 | ret = ci_get_svi2_voltage_table(rdev, |
1757 | &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, |
1758 | &pi->mvdd_voltage_table); |
1759 | if (ret) |
1760 | return ret; |
1761 | } |
1762 | |
1763 | if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) |
1764 | si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD, |
1765 | &pi->mvdd_voltage_table); |
1766 | |
1767 | return 0; |
1768 | } |
1769 | |
1770 | static void ci_populate_smc_voltage_table(struct radeon_device *rdev, |
1771 | struct atom_voltage_table_entry *voltage_table, |
1772 | SMU7_Discrete_VoltageLevel *smc_voltage_table) |
1773 | { |
1774 | int ret; |
1775 | |
1776 | ret = ci_get_std_voltage_value_sidd(rdev, voltage_table, |
1777 | &smc_voltage_table->StdVoltageHiSidd, |
1778 | &smc_voltage_table->StdVoltageLoSidd); |
1779 | |
1780 | if (ret) { |
1781 | smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE; |
1782 | smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE; |
1783 | } |
1784 | |
1785 | smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE); |
1786 | smc_voltage_table->StdVoltageHiSidd = |
1787 | cpu_to_be16(smc_voltage_table->StdVoltageHiSidd); |
1788 | smc_voltage_table->StdVoltageLoSidd = |
1789 | cpu_to_be16(smc_voltage_table->StdVoltageLoSidd); |
1790 | } |
1791 | |
1792 | static int ci_populate_smc_vddc_table(struct radeon_device *rdev, |
1793 | SMU7_Discrete_DpmTable *table) |
1794 | { |
1795 | struct ci_power_info *pi = ci_get_pi(rdev); |
1796 | unsigned int count; |
1797 | |
1798 | table->VddcLevelCount = pi->vddc_voltage_table.count; |
1799 | for (count = 0; count < table->VddcLevelCount; count++) { |
1800 | ci_populate_smc_voltage_table(rdev, |
1801 | &pi->vddc_voltage_table.entries[count], |
1802 | &table->VddcLevel[count]); |
1803 | |
1804 | if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) |
1805 | table->VddcLevel[count].Smio |= |
1806 | pi->vddc_voltage_table.entries[count].smio_low; |
1807 | else |
1808 | table->VddcLevel[count].Smio = 0; |
1809 | } |
1810 | table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount); |
1811 | |
1812 | return 0; |
1813 | } |
1814 | |
1815 | static int ci_populate_smc_vddci_table(struct radeon_device *rdev, |
1816 | SMU7_Discrete_DpmTable *table) |
1817 | { |
1818 | unsigned int count; |
1819 | struct ci_power_info *pi = ci_get_pi(rdev); |
1820 | |
1821 | table->VddciLevelCount = pi->vddci_voltage_table.count; |
1822 | for (count = 0; count < table->VddciLevelCount; count++) { |
1823 | ci_populate_smc_voltage_table(rdev, |
1824 | &pi->vddci_voltage_table.entries[count], |
1825 | &table->VddciLevel[count]); |
1826 | |
1827 | if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) |
1828 | table->VddciLevel[count].Smio |= |
1829 | pi->vddci_voltage_table.entries[count].smio_low; |
1830 | else |
1831 | table->VddciLevel[count].Smio = 0; |
1832 | } |
1833 | table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount); |
1834 | |
1835 | return 0; |
1836 | } |
1837 | |
1838 | static int ci_populate_smc_mvdd_table(struct radeon_device *rdev, |
1839 | SMU7_Discrete_DpmTable *table) |
1840 | { |
1841 | struct ci_power_info *pi = ci_get_pi(rdev); |
1842 | unsigned int count; |
1843 | |
1844 | table->MvddLevelCount = pi->mvdd_voltage_table.count; |
1845 | for (count = 0; count < table->MvddLevelCount; count++) { |
1846 | ci_populate_smc_voltage_table(rdev, |
1847 | &pi->mvdd_voltage_table.entries[count], |
1848 | &table->MvddLevel[count]); |
1849 | |
1850 | if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) |
1851 | table->MvddLevel[count].Smio |= |
1852 | pi->mvdd_voltage_table.entries[count].smio_low; |
1853 | else |
1854 | table->MvddLevel[count].Smio = 0; |
1855 | } |
1856 | table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount); |
1857 | |
1858 | return 0; |
1859 | } |
1860 | |
1861 | static int ci_populate_smc_voltage_tables(struct radeon_device *rdev, |
1862 | SMU7_Discrete_DpmTable *table) |
1863 | { |
1864 | int ret; |
1865 | |
1866 | ret = ci_populate_smc_vddc_table(rdev, table); |
1867 | if (ret) |
1868 | return ret; |
1869 | |
1870 | ret = ci_populate_smc_vddci_table(rdev, table); |
1871 | if (ret) |
1872 | return ret; |
1873 | |
1874 | ret = ci_populate_smc_mvdd_table(rdev, table); |
1875 | if (ret) |
1876 | return ret; |
1877 | |
1878 | return 0; |
1879 | } |
1880 | |
1881 | static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, |
1882 | SMU7_Discrete_VoltageLevel *voltage) |
1883 | { |
1884 | struct ci_power_info *pi = ci_get_pi(rdev); |
1885 | u32 i = 0; |
1886 | |
1887 | if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { |
1888 | for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { |
1889 | if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { |
1890 | voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; |
1891 | break; |
1892 | } |
1893 | } |
1894 | |
1895 | if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) |
1896 | return -EINVAL; |
1897 | } |
1898 | |
1899 | return -EINVAL; |
1900 | } |
1901 | |
1902 | static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, |
1903 | struct atom_voltage_table_entry *voltage_table, |
1904 | u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd) |
1905 | { |
1906 | u16 v_index, idx; |
1907 | bool voltage_found = false; |
1908 | *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE; |
1909 | *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE; |
1910 | |
1911 | if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) |
1912 | return -EINVAL; |
1913 | |
1914 | if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { |
1915 | for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { |
1916 | if (voltage_table->value == |
1917 | rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { |
1918 | voltage_found = true; |
1919 | if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) |
1920 | idx = v_index; |
1921 | else |
1922 | idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; |
1923 | *std_voltage_lo_sidd = |
1924 | rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; |
1925 | *std_voltage_hi_sidd = |
1926 | rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; |
1927 | break; |
1928 | } |
1929 | } |
1930 | |
1931 | if (!voltage_found) { |
1932 | for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { |
1933 | if (voltage_table->value <= |
1934 | rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { |
1935 | voltage_found = true; |
1936 | if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) |
1937 | idx = v_index; |
1938 | else |
1939 | idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; |
1940 | *std_voltage_lo_sidd = |
1941 | rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; |
1942 | *std_voltage_hi_sidd = |
1943 | rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; |
1944 | break; |
1945 | } |
1946 | } |
1947 | } |
1948 | } |
1949 | |
1950 | return 0; |
1951 | } |
1952 | |
1953 | static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev, |
1954 | const struct radeon_phase_shedding_limits_table *limits, |
1955 | u32 sclk, |
1956 | u32 *phase_shedding) |
1957 | { |
1958 | unsigned int i; |
1959 | |
1960 | *phase_shedding = 1; |
1961 | |
1962 | for (i = 0; i < limits->count; i++) { |
1963 | if (sclk < limits->entries[i].sclk) { |
1964 | *phase_shedding = i; |
1965 | break; |
1966 | } |
1967 | } |
1968 | } |
1969 | |
1970 | static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev, |
1971 | const struct radeon_phase_shedding_limits_table *limits, |
1972 | u32 mclk, |
1973 | u32 *phase_shedding) |
1974 | { |
1975 | unsigned int i; |
1976 | |
1977 | *phase_shedding = 1; |
1978 | |
1979 | for (i = 0; i < limits->count; i++) { |
1980 | if (mclk < limits->entries[i].mclk) { |
1981 | *phase_shedding = i; |
1982 | break; |
1983 | } |
1984 | } |
1985 | } |
1986 | |
1987 | static int ci_init_arb_table_index(struct radeon_device *rdev) |
1988 | { |
1989 | struct ci_power_info *pi = ci_get_pi(rdev); |
1990 | u32 tmp; |
1991 | int ret; |
1992 | |
1993 | ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, |
1994 | &tmp, pi->sram_end); |
1995 | if (ret) |
1996 | return ret; |
1997 | |
1998 | tmp &= 0x00FFFFFF; |
1999 | tmp |= MC_CG_ARB_FREQ_F1 << 24; |
2000 | |
2001 | return ci_write_smc_sram_dword(rdev, pi->arb_table_start, |
2002 | tmp, pi->sram_end); |
2003 | } |
2004 | |
2005 | static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev, |
2006 | struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table, |
2007 | u32 clock, u32 *voltage) |
2008 | { |
2009 | u32 i = 0; |
2010 | |
2011 | if (allowed_clock_voltage_table->count == 0) |
2012 | return -EINVAL; |
2013 | |
2014 | for (i = 0; i < allowed_clock_voltage_table->count; i++) { |
2015 | if (allowed_clock_voltage_table->entries[i].clk >= clock) { |
2016 | *voltage = allowed_clock_voltage_table->entries[i].v; |
2017 | return 0; |
2018 | } |
2019 | } |
2020 | |
2021 | *voltage = allowed_clock_voltage_table->entries[i-1].v; |
2022 | |
2023 | return 0; |
2024 | } |
2025 | |
2026 | static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev, |
2027 | u32 sclk, u32 min_sclk_in_sr) |
2028 | { |
2029 | u32 i; |
2030 | u32 tmp; |
2031 | u32 vmin = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ? |
2032 | min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK; |
2033 | |
2034 | if (sclk < vmin) |
2035 | return 0; |
2036 | |
2037 | for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { |
2038 | tmp = sclk / (1 << i); |
2039 | if (tmp >= vmin || i == 0) |
2040 | break; |
2041 | } |
2042 | |
2043 | return (u8)i; |
2044 | } |
2045 | |
2046 | static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) |
2047 | { |
2048 | return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); |
2049 | } |
2050 | |
2051 | static int ci_reset_to_default(struct radeon_device *rdev) |
2052 | { |
2053 | return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? |
2054 | 0 : -EINVAL; |
2055 | } |
2056 | |
2057 | static int ci_force_switch_to_arb_f0(struct radeon_device *rdev) |
2058 | { |
2059 | u32 tmp; |
2060 | |
2061 | tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8; |
2062 | |
2063 | if (tmp == MC_CG_ARB_FREQ_F0) |
2064 | return 0; |
2065 | |
2066 | return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); |
2067 | } |
2068 | |
2069 | static int ci_populate_memory_timing_parameters(struct radeon_device *rdev, |
2070 | u32 sclk, |
2071 | u32 mclk, |
2072 | SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs) |
2073 | { |
2074 | u32 dram_timing; |
2075 | u32 dram_timing2; |
2076 | u32 burst_time; |
2077 | |
2078 | radeon_atom_set_engine_dram_timings(rdev, sclk, mclk); |
2079 | |
2080 | dram_timing = RREG32(MC_ARB_DRAM_TIMING); |
2081 | dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); |
2082 | burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; |
2083 | |
2084 | arb_regs->McArbDramTiming = cpu_to_be32(dram_timing); |
2085 | arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2); |
2086 | arb_regs->McArbBurstTime = (u8)burst_time; |
2087 | |
2088 | return 0; |
2089 | } |
2090 | |
2091 | static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev) |
2092 | { |
2093 | struct ci_power_info *pi = ci_get_pi(rdev); |
2094 | SMU7_Discrete_MCArbDramTimingTable arb_regs; |
2095 | u32 i, j; |
2096 | int ret = 0; |
2097 | |
2098 | memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable)); |
2099 | |
2100 | for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { |
2101 | for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { |
2102 | ret = ci_populate_memory_timing_parameters(rdev, |
2103 | pi->dpm_table.sclk_table.dpm_levels[i].value, |
2104 | pi->dpm_table.mclk_table.dpm_levels[j].value, |
2105 | &arb_regs.entries[i][j]); |
2106 | if (ret) |
2107 | break; |
2108 | } |
2109 | } |
2110 | |
2111 | if (ret == 0) |
2112 | ret = ci_copy_bytes_to_smc(rdev, |
2113 | pi->arb_table_start, |
2114 | (u8 *)&arb_regs, |
2115 | sizeof(SMU7_Discrete_MCArbDramTimingTable), |
2116 | pi->sram_end); |
2117 | |
2118 | return ret; |
2119 | } |
2120 | |
2121 | static int ci_program_memory_timing_parameters(struct radeon_device *rdev) |
2122 | { |
2123 | struct ci_power_info *pi = ci_get_pi(rdev); |
2124 | |
2125 | if (pi->need_update_smu7_dpm_table == 0) |
2126 | return 0; |
2127 | |
2128 | return ci_do_program_memory_timing_parameters(rdev); |
2129 | } |
2130 | |
2131 | static void ci_populate_smc_initial_state(struct radeon_device *rdev, |
2132 | struct radeon_ps *radeon_boot_state) |
2133 | { |
2134 | struct ci_ps *boot_state = ci_get_ps(radeon_boot_state); |
2135 | struct ci_power_info *pi = ci_get_pi(rdev); |
2136 | u32 level = 0; |
2137 | |
2138 | for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { |
2139 | if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= |
2140 | boot_state->performance_levels[0].sclk) { |
2141 | pi->smc_state_table.GraphicsBootLevel = level; |
2142 | break; |
2143 | } |
2144 | } |
2145 | |
2146 | for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { |
2147 | if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= |
2148 | boot_state->performance_levels[0].mclk) { |
2149 | pi->smc_state_table.MemoryBootLevel = level; |
2150 | break; |
2151 | } |
2152 | } |
2153 | } |
2154 | |
2155 | static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) |
2156 | { |
2157 | u32 i; |
2158 | u32 mask_value = 0; |
2159 | |
2160 | for (i = dpm_table->count; i > 0; i--) { |
2161 | mask_value = mask_value << 1; |
2162 | if (dpm_table->dpm_levels[i-1].enabled) |
2163 | mask_value |= 0x1; |
2164 | else |
2165 | mask_value &= 0xFFFFFFFE; |
2166 | } |
2167 | |
2168 | return mask_value; |
2169 | } |
2170 | |
2171 | static void ci_populate_smc_link_level(struct radeon_device *rdev, |
2172 | SMU7_Discrete_DpmTable *table) |
2173 | { |
2174 | struct ci_power_info *pi = ci_get_pi(rdev); |
2175 | struct ci_dpm_table *dpm_table = &pi->dpm_table; |
2176 | u32 i; |
2177 | |
2178 | for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { |
2179 | table->LinkLevel[i].PcieGenSpeed = |
2180 | (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; |
2181 | table->LinkLevel[i].PcieLaneCount = |
2182 | r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); |
2183 | table->LinkLevel[i].EnabledForActivity = 1; |
2184 | table->LinkLevel[i].DownT = cpu_to_be32(5); |
2185 | table->LinkLevel[i].UpT = cpu_to_be32(30); |
2186 | } |
2187 | |
2188 | pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; |
2189 | pi->dpm_level_enable_mask.pcie_dpm_enable_mask = |
2190 | ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); |
2191 | } |
2192 | |
2193 | static int ci_populate_smc_uvd_level(struct radeon_device *rdev, |
2194 | SMU7_Discrete_DpmTable *table) |
2195 | { |
2196 | u32 count; |
2197 | struct atom_clock_dividers dividers; |
2198 | int ret = -EINVAL; |
2199 | |
2200 | table->UvdLevelCount = |
2201 | rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; |
2202 | |
2203 | for (count = 0; count < table->UvdLevelCount; count++) { |
2204 | table->UvdLevel[count].VclkFrequency = |
2205 | rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; |
2206 | table->UvdLevel[count].DclkFrequency = |
2207 | rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; |
2208 | table->UvdLevel[count].MinVddc = |
2209 | rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; |
2210 | table->UvdLevel[count].MinVddcPhases = 1; |
2211 | |
2212 | ret = radeon_atom_get_clock_dividers(rdev, |
2213 | COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, |
2214 | table->UvdLevel[count].VclkFrequency, false, ÷rs); |
2215 | if (ret) |
2216 | return ret; |
2217 | |
2218 | table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; |
2219 | |
2220 | ret = radeon_atom_get_clock_dividers(rdev, |
2221 | COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, |
2222 | table->UvdLevel[count].DclkFrequency, false, ÷rs); |
2223 | if (ret) |
2224 | return ret; |
2225 | |
2226 | table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; |
2227 | |
2228 | table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); |
2229 | table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); |
2230 | table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc); |
2231 | } |
2232 | |
2233 | return ret; |
2234 | } |
2235 | |
2236 | static int ci_populate_smc_vce_level(struct radeon_device *rdev, |
2237 | SMU7_Discrete_DpmTable *table) |
2238 | { |
2239 | u32 count; |
2240 | struct atom_clock_dividers dividers; |
2241 | int ret = -EINVAL; |
2242 | |
2243 | table->VceLevelCount = |
2244 | rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; |
2245 | |
2246 | for (count = 0; count < table->VceLevelCount; count++) { |
2247 | table->VceLevel[count].Frequency = |
2248 | rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; |
2249 | table->VceLevel[count].MinVoltage = |
2250 | (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; |
2251 | table->VceLevel[count].MinPhases = 1; |
2252 | |
2253 | ret = radeon_atom_get_clock_dividers(rdev, |
2254 | COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, |
2255 | table->VceLevel[count].Frequency, false, ÷rs); |
2256 | if (ret) |
2257 | return ret; |
2258 | |
2259 | table->VceLevel[count].Divider = (u8)dividers.post_divider; |
2260 | |
2261 | table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); |
2262 | table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); |
2263 | } |
2264 | |
2265 | return ret; |
2266 | |
2267 | } |
2268 | |
2269 | static int ci_populate_smc_acp_level(struct radeon_device *rdev, |
2270 | SMU7_Discrete_DpmTable *table) |
2271 | { |
2272 | u32 count; |
2273 | struct atom_clock_dividers dividers; |
2274 | int ret = -EINVAL; |
2275 | |
2276 | table->AcpLevelCount = (u8) |
2277 | (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); |
2278 | |
2279 | for (count = 0; count < table->AcpLevelCount; count++) { |
2280 | table->AcpLevel[count].Frequency = |
2281 | rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; |
2282 | table->AcpLevel[count].MinVoltage = |
2283 | rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; |
2284 | table->AcpLevel[count].MinPhases = 1; |
2285 | |
2286 | ret = radeon_atom_get_clock_dividers(rdev, |
2287 | COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, |
2288 | table->AcpLevel[count].Frequency, false, ÷rs); |
2289 | if (ret) |
2290 | return ret; |
2291 | |
2292 | table->AcpLevel[count].Divider = (u8)dividers.post_divider; |
2293 | |
2294 | table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency); |
2295 | table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage); |
2296 | } |
2297 | |
2298 | return ret; |
2299 | } |
2300 | |
2301 | static int ci_populate_smc_samu_level(struct radeon_device *rdev, |
2302 | SMU7_Discrete_DpmTable *table) |
2303 | { |
2304 | u32 count; |
2305 | struct atom_clock_dividers dividers; |
2306 | int ret = -EINVAL; |
2307 | |
2308 | table->SamuLevelCount = |
2309 | rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; |
2310 | |
2311 | for (count = 0; count < table->SamuLevelCount; count++) { |
2312 | table->SamuLevel[count].Frequency = |
2313 | rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; |
2314 | table->SamuLevel[count].MinVoltage = |
2315 | rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; |
2316 | table->SamuLevel[count].MinPhases = 1; |
2317 | |
2318 | ret = radeon_atom_get_clock_dividers(rdev, |
2319 | COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, |
2320 | table->SamuLevel[count].Frequency, false, ÷rs); |
2321 | if (ret) |
2322 | return ret; |
2323 | |
2324 | table->SamuLevel[count].Divider = (u8)dividers.post_divider; |
2325 | |
2326 | table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); |
2327 | table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); |
2328 | } |
2329 | |
2330 | return ret; |
2331 | } |
2332 | |
2333 | static int ci_calculate_mclk_params(struct radeon_device *rdev, |
2334 | u32 memory_clock, |
2335 | SMU7_Discrete_MemoryLevel *mclk, |
2336 | bool strobe_mode, |
2337 | bool dll_state_on) |
2338 | { |
2339 | struct ci_power_info *pi = ci_get_pi(rdev); |
2340 | u32 dll_cntl = pi->clock_registers.dll_cntl; |
2341 | u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; |
2342 | u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; |
2343 | u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; |
2344 | u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; |
2345 | u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; |
2346 | u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; |
2347 | u32 mpll_ss1 = pi->clock_registers.mpll_ss1; |
2348 | u32 mpll_ss2 = pi->clock_registers.mpll_ss2; |
2349 | struct atom_mpll_param mpll_param; |
2350 | int ret; |
2351 | |
2352 | ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); |
2353 | if (ret) |
2354 | return ret; |
2355 | |
2356 | mpll_func_cntl &= ~BWCTRL_MASK; |
2357 | mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); |
2358 | |
2359 | mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); |
2360 | mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | |
2361 | CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); |
2362 | |
2363 | mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; |
2364 | mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); |
2365 | |
2366 | if (pi->mem_gddr5) { |
2367 | mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); |
2368 | mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | |
2369 | YCLK_POST_DIV(mpll_param.post_div); |
2370 | } |
2371 | |
2372 | if (pi->caps_mclk_ss_support) { |
2373 | struct radeon_atom_ss ss; |
2374 | u32 freq_nom; |
2375 | u32 tmp; |
2376 | u32 reference_clock = rdev->clock.mpll.reference_freq; |
2377 | |
2378 | if (pi->mem_gddr5) |
2379 | freq_nom = memory_clock * 4; |
2380 | else |
2381 | freq_nom = memory_clock * 2; |
2382 | |
2383 | tmp = (freq_nom / reference_clock); |
2384 | tmp = tmp * tmp; |
2385 | if (radeon_atombios_get_asic_ss_info(rdev, &ss, |
2386 | ASIC_INTERNAL_MEMORY_SS, freq_nom)) { |
2387 | u32 clks = reference_clock * 5 / ss.rate; |
2388 | u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); |
2389 | |
2390 | mpll_ss1 &= ~CLKV_MASK; |
2391 | mpll_ss1 |= CLKV(clkv); |
2392 | |
2393 | mpll_ss2 &= ~CLKS_MASK; |
2394 | mpll_ss2 |= CLKS(clks); |
2395 | } |
2396 | } |
2397 | |
2398 | mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; |
2399 | mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); |
2400 | |
2401 | if (dll_state_on) |
2402 | mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; |
2403 | else |
2404 | mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); |
2405 | |
2406 | mclk->MclkFrequency = memory_clock; |
2407 | mclk->MpllFuncCntl = mpll_func_cntl; |
2408 | mclk->MpllFuncCntl_1 = mpll_func_cntl_1; |
2409 | mclk->MpllFuncCntl_2 = mpll_func_cntl_2; |
2410 | mclk->MpllAdFuncCntl = mpll_ad_func_cntl; |
2411 | mclk->MpllDqFuncCntl = mpll_dq_func_cntl; |
2412 | mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; |
2413 | mclk->DllCntl = dll_cntl; |
2414 | mclk->MpllSs1 = mpll_ss1; |
2415 | mclk->MpllSs2 = mpll_ss2; |
2416 | |
2417 | return 0; |
2418 | } |
2419 | |
2420 | static int ci_populate_single_memory_level(struct radeon_device *rdev, |
2421 | u32 memory_clock, |
2422 | SMU7_Discrete_MemoryLevel *memory_level) |
2423 | { |
2424 | struct ci_power_info *pi = ci_get_pi(rdev); |
2425 | int ret; |
2426 | bool dll_state_on; |
2427 | |
2428 | if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { |
2429 | ret = ci_get_dependency_volt_by_clk(rdev, |
2430 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, |
2431 | memory_clock, &memory_level->MinVddc); |
2432 | if (ret) |
2433 | return ret; |
2434 | } |
2435 | |
2436 | if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { |
2437 | ret = ci_get_dependency_volt_by_clk(rdev, |
2438 | &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, |
2439 | memory_clock, &memory_level->MinVddci); |
2440 | if (ret) |
2441 | return ret; |
2442 | } |
2443 | |
2444 | if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { |
2445 | ret = ci_get_dependency_volt_by_clk(rdev, |
2446 | &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, |
2447 | memory_clock, &memory_level->MinMvdd); |
2448 | if (ret) |
2449 | return ret; |
2450 | } |
2451 | |
2452 | memory_level->MinVddcPhases = 1; |
2453 | |
2454 | if (pi->vddc_phase_shed_control) |
2455 | ci_populate_phase_value_based_on_mclk(rdev, |
2456 | &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, |
2457 | memory_clock, |
2458 | &memory_level->MinVddcPhases); |
2459 | |
2460 | memory_level->EnabledForThrottle = 1; |
2461 | memory_level->EnabledForActivity = 1; |
2462 | memory_level->UpH = 0; |
2463 | memory_level->DownH = 100; |
2464 | memory_level->VoltageDownH = 0; |
2465 | memory_level->ActivityLevel = (u16)pi->mclk_activity_target; |
2466 | |
2467 | memory_level->StutterEnable = false; |
2468 | memory_level->StrobeEnable = false; |
2469 | memory_level->EdcReadEnable = false; |
2470 | memory_level->EdcWriteEnable = false; |
2471 | memory_level->RttEnable = false; |
2472 | |
2473 | memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; |
2474 | |
2475 | if (pi->mclk_stutter_mode_threshold && |
2476 | (memory_clock <= pi->mclk_stutter_mode_threshold) && |
2477 | (pi->uvd_enabled == false) && |
2478 | (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && |
2479 | (rdev->pm.dpm.new_active_crtc_count <= 2)) |
2480 | memory_level->StutterEnable = true; |
2481 | |
2482 | if (pi->mclk_strobe_mode_threshold && |
2483 | (memory_clock <= pi->mclk_strobe_mode_threshold)) |
2484 | memory_level->StrobeEnable = 1; |
2485 | |
2486 | if (pi->mem_gddr5) { |
2487 | memory_level->StrobeRatio = |
2488 | si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable); |
2489 | if (pi->mclk_edc_enable_threshold && |
2490 | (memory_clock > pi->mclk_edc_enable_threshold)) |
2491 | memory_level->EdcReadEnable = true; |
2492 | |
2493 | if (pi->mclk_edc_wr_enable_threshold && |
2494 | (memory_clock > pi->mclk_edc_wr_enable_threshold)) |
2495 | memory_level->EdcWriteEnable = true; |
2496 | |
2497 | if (memory_level->StrobeEnable) { |
2498 | if (si_get_mclk_frequency_ratio(memory_clock, true) >= |
2499 | ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) |
2500 | dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; |
2501 | else |
2502 | dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; |
2503 | } else { |
2504 | dll_state_on = pi->dll_default_on; |
2505 | } |
2506 | } else { |
2507 | memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock); |
2508 | dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; |
2509 | } |
2510 | |
2511 | ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); |
2512 | if (ret) |
2513 | return ret; |
2514 | |
2515 | memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE); |
2516 | memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); |
2517 | memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); |
2518 | memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); |
2519 | |
2520 | memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency); |
2521 | memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel); |
2522 | memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl); |
2523 | memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1); |
2524 | memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2); |
2525 | memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl); |
2526 | memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl); |
2527 | memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl); |
2528 | memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl); |
2529 | memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1); |
2530 | memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2); |
2531 | |
2532 | return 0; |
2533 | } |
2534 | |
2535 | static int ci_populate_smc_acpi_level(struct radeon_device *rdev, |
2536 | SMU7_Discrete_DpmTable *table) |
2537 | { |
2538 | struct ci_power_info *pi = ci_get_pi(rdev); |
2539 | struct atom_clock_dividers dividers; |
2540 | SMU7_Discrete_VoltageLevel voltage_level; |
2541 | u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; |
2542 | u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; |
2543 | u32 dll_cntl = pi->clock_registers.dll_cntl; |
2544 | u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; |
2545 | int ret; |
2546 | |
2547 | table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; |
2548 | |
2549 | if (pi->acpi_vddc) |
2550 | table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); |
2551 | else |
2552 | table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); |
2553 | |
2554 | table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; |
2555 | |
2556 | table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; |
2557 | |
2558 | ret = radeon_atom_get_clock_dividers(rdev, |
2559 | COMPUTE_GPUCLK_INPUT_FLAG_SCLK, |
2560 | table->ACPILevel.SclkFrequency, false, ÷rs); |
2561 | if (ret) |
2562 | return ret; |
2563 | |
2564 | table->ACPILevel.SclkDid = (u8)dividers.post_divider; |
2565 | table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; |
2566 | table->ACPILevel.DeepSleepDivId = 0; |
2567 | |
2568 | spll_func_cntl &= ~SPLL_PWRON; |
2569 | spll_func_cntl |= SPLL_RESET; |
2570 | |
2571 | spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; |
2572 | spll_func_cntl_2 |= SCLK_MUX_SEL(4); |
2573 | |
2574 | table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; |
2575 | table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; |
2576 | table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; |
2577 | table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; |
2578 | table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; |
2579 | table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; |
2580 | table->ACPILevel.CcPwrDynRm = 0; |
2581 | table->ACPILevel.CcPwrDynRm1 = 0; |
2582 | |
2583 | table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags); |
2584 | table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); |
2585 | table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency); |
2586 | table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl); |
2587 | table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2); |
2588 | table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3); |
2589 | table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4); |
2590 | table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum); |
2591 | table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2); |
2592 | table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm); |
2593 | table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1); |
2594 | |
2595 | table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; |
2596 | table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; |
2597 | |
2598 | if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { |
2599 | if (pi->acpi_vddci) |
2600 | table->MemoryACPILevel.MinVddci = |
2601 | cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); |
2602 | else |
2603 | table->MemoryACPILevel.MinVddci = |
2604 | cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); |
2605 | } |
2606 | |
2607 | if (ci_populate_mvdd_value(rdev, 0, &voltage_level)) |
2608 | table->MemoryACPILevel.MinMvdd = 0; |
2609 | else |
2610 | table->MemoryACPILevel.MinMvdd = |
2611 | cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE); |
2612 | |
2613 | mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; |
2614 | mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); |
2615 | |
2616 | dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); |
2617 | |
2618 | table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl); |
2619 | table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl); |
2620 | table->MemoryACPILevel.MpllAdFuncCntl = |
2621 | cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); |
2622 | table->MemoryACPILevel.MpllDqFuncCntl = |
2623 | cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); |
2624 | table->MemoryACPILevel.MpllFuncCntl = |
2625 | cpu_to_be32(pi->clock_registers.mpll_func_cntl); |
2626 | table->MemoryACPILevel.MpllFuncCntl_1 = |
2627 | cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); |
2628 | table->MemoryACPILevel.MpllFuncCntl_2 = |
2629 | cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); |
2630 | table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); |
2631 | table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); |
2632 | |
2633 | table->MemoryACPILevel.EnabledForThrottle = 0; |
2634 | table->MemoryACPILevel.EnabledForActivity = 0; |
2635 | table->MemoryACPILevel.UpH = 0; |
2636 | table->MemoryACPILevel.DownH = 100; |
2637 | table->MemoryACPILevel.VoltageDownH = 0; |
2638 | table->MemoryACPILevel.ActivityLevel = |
2639 | cpu_to_be16((u16)pi->mclk_activity_target); |
2640 | |
2641 | table->MemoryACPILevel.StutterEnable = false; |
2642 | table->MemoryACPILevel.StrobeEnable = false; |
2643 | table->MemoryACPILevel.EdcReadEnable = false; |
2644 | table->MemoryACPILevel.EdcWriteEnable = false; |
2645 | table->MemoryACPILevel.RttEnable = false; |
2646 | |
2647 | return 0; |
2648 | } |
2649 | |
2650 | |
2651 | static int ci_enable_ulv(struct radeon_device *rdev, bool enable) |
2652 | { |
2653 | struct ci_power_info *pi = ci_get_pi(rdev); |
2654 | struct ci_ulv_parm *ulv = &pi->ulv; |
2655 | |
2656 | if (ulv->supported) { |
2657 | if (enable) |
2658 | return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? |
2659 | 0 : -EINVAL; |
2660 | else |
2661 | return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? |
2662 | 0 : -EINVAL; |
2663 | } |
2664 | |
2665 | return 0; |
2666 | } |
2667 | |
2668 | static int ci_populate_ulv_level(struct radeon_device *rdev, |
2669 | SMU7_Discrete_Ulv *state) |
2670 | { |
2671 | struct ci_power_info *pi = ci_get_pi(rdev); |
2672 | u16 ulv_voltage = rdev->pm.dpm.backbias_response_time; |
2673 | |
2674 | state->CcPwrDynRm = 0; |
2675 | state->CcPwrDynRm1 = 0; |
2676 | |
2677 | if (ulv_voltage == 0) { |
2678 | pi->ulv.supported = false; |
2679 | return 0; |
2680 | } |
2681 | |
2682 | if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { |
2683 | if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) |
2684 | state->VddcOffset = 0; |
2685 | else |
2686 | state->VddcOffset = |
2687 | rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; |
2688 | } else { |
2689 | if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) |
2690 | state->VddcOffsetVid = 0; |
2691 | else |
2692 | state->VddcOffsetVid = (u8) |
2693 | ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * |
2694 | VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); |
2695 | } |
2696 | state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; |
2697 | |
2698 | state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm); |
2699 | state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1); |
2700 | state->VddcOffset = cpu_to_be16(state->VddcOffset); |
2701 | |
2702 | return 0; |
2703 | } |
2704 | |
2705 | static int ci_calculate_sclk_params(struct radeon_device *rdev, |
2706 | u32 engine_clock, |
2707 | SMU7_Discrete_GraphicsLevel *sclk) |
2708 | { |
2709 | struct ci_power_info *pi = ci_get_pi(rdev); |
2710 | struct atom_clock_dividers dividers; |
2711 | u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; |
2712 | u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; |
2713 | u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; |
2714 | u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; |
2715 | u32 reference_clock = rdev->clock.spll.reference_freq; |
2716 | u32 reference_divider; |
2717 | u32 fbdiv; |
2718 | int ret; |
2719 | |
2720 | ret = radeon_atom_get_clock_dividers(rdev, |
2721 | COMPUTE_GPUCLK_INPUT_FLAG_SCLK, |
2722 | engine_clock, false, ÷rs); |
2723 | if (ret) |
2724 | return ret; |
2725 | |
2726 | reference_divider = 1 + dividers.ref_div; |
2727 | fbdiv = dividers.fb_div & 0x3FFFFFF; |
2728 | |
2729 | spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; |
2730 | spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); |
2731 | spll_func_cntl_3 |= SPLL_DITHEN; |
2732 | |
2733 | if (pi->caps_sclk_ss_support) { |
2734 | struct radeon_atom_ss ss; |
2735 | u32 vco_freq = engine_clock * dividers.post_div; |
2736 | |
2737 | if (radeon_atombios_get_asic_ss_info(rdev, &ss, |
2738 | ASIC_INTERNAL_ENGINE_SS, vco_freq)) { |
2739 | u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); |
2740 | u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); |
2741 | |
2742 | cg_spll_spread_spectrum &= ~CLK_S_MASK; |
2743 | cg_spll_spread_spectrum |= CLK_S(clk_s); |
2744 | cg_spll_spread_spectrum |= SSEN; |
2745 | |
2746 | cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; |
2747 | cg_spll_spread_spectrum_2 |= CLK_V(clk_v); |
2748 | } |
2749 | } |
2750 | |
2751 | sclk->SclkFrequency = engine_clock; |
2752 | sclk->CgSpllFuncCntl3 = spll_func_cntl_3; |
2753 | sclk->CgSpllFuncCntl4 = spll_func_cntl_4; |
2754 | sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; |
2755 | sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; |
2756 | sclk->SclkDid = (u8)dividers.post_divider; |
2757 | |
2758 | return 0; |
2759 | } |
2760 | |
2761 | static int ci_populate_single_graphic_level(struct radeon_device *rdev, |
2762 | u32 engine_clock, |
2763 | u16 sclk_activity_level_t, |
2764 | SMU7_Discrete_GraphicsLevel *graphic_level) |
2765 | { |
2766 | struct ci_power_info *pi = ci_get_pi(rdev); |
2767 | int ret; |
2768 | |
2769 | ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); |
2770 | if (ret) |
2771 | return ret; |
2772 | |
2773 | ret = ci_get_dependency_volt_by_clk(rdev, |
2774 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, |
2775 | engine_clock, &graphic_level->MinVddc); |
2776 | if (ret) |
2777 | return ret; |
2778 | |
2779 | graphic_level->SclkFrequency = engine_clock; |
2780 | |
2781 | graphic_level->Flags = 0; |
2782 | graphic_level->MinVddcPhases = 1; |
2783 | |
2784 | if (pi->vddc_phase_shed_control) |
2785 | ci_populate_phase_value_based_on_sclk(rdev, |
2786 | &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, |
2787 | engine_clock, |
2788 | &graphic_level->MinVddcPhases); |
2789 | |
2790 | graphic_level->ActivityLevel = sclk_activity_level_t; |
2791 | |
2792 | graphic_level->CcPwrDynRm = 0; |
2793 | graphic_level->CcPwrDynRm1 = 0; |
2794 | graphic_level->EnabledForActivity = 1; |
2795 | graphic_level->EnabledForThrottle = 1; |
2796 | graphic_level->UpH = 0; |
2797 | graphic_level->DownH = 0; |
2798 | graphic_level->VoltageDownH = 0; |
2799 | graphic_level->PowerThrottle = 0; |
2800 | |
2801 | if (pi->caps_sclk_ds) |
2802 | graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev, |
2803 | engine_clock, |
2804 | CISLAND_MINIMUM_ENGINE_CLOCK); |
2805 | |
2806 | graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; |
2807 | |
2808 | graphic_level->Flags = cpu_to_be32(graphic_level->Flags); |
2809 | graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE); |
2810 | graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases); |
2811 | graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency); |
2812 | graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel); |
2813 | graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3); |
2814 | graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4); |
2815 | graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum); |
2816 | graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2); |
2817 | graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm); |
2818 | graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1); |
2819 | |
2820 | return 0; |
2821 | } |
2822 | |
2823 | static int ci_populate_all_graphic_levels(struct radeon_device *rdev) |
2824 | { |
2825 | struct ci_power_info *pi = ci_get_pi(rdev); |
2826 | struct ci_dpm_table *dpm_table = &pi->dpm_table; |
2827 | u32 level_array_address = pi->dpm_table_start + |
2828 | offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); |
2829 | u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) * |
2830 | SMU7_MAX_LEVELS_GRAPHICS; |
2831 | SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; |
2832 | u32 i, ret; |
2833 | |
2834 | memset(levels, 0, level_array_size); |
2835 | |
2836 | for (i = 0; i < dpm_table->sclk_table.count; i++) { |
2837 | ret = ci_populate_single_graphic_level(rdev, |
2838 | dpm_table->sclk_table.dpm_levels[i].value, |
2839 | (u16)pi->activity_target[i], |
2840 | &pi->smc_state_table.GraphicsLevel[i]); |
2841 | if (ret) |
2842 | return ret; |
2843 | if (i == (dpm_table->sclk_table.count - 1)) |
2844 | pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = |
2845 | PPSMC_DISPLAY_WATERMARK_HIGH; |
2846 | } |
2847 | |
2848 | pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; |
2849 | pi->dpm_level_enable_mask.sclk_dpm_enable_mask = |
2850 | ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); |
2851 | |
2852 | ret = ci_copy_bytes_to_smc(rdev, level_array_address, |
2853 | (u8 *)levels, level_array_size, |
2854 | pi->sram_end); |
2855 | if (ret) |
2856 | return ret; |
2857 | |
2858 | return 0; |
2859 | } |
2860 | |
2861 | static int ci_populate_ulv_state(struct radeon_device *rdev, |
2862 | SMU7_Discrete_Ulv *ulv_level) |
2863 | { |
2864 | return ci_populate_ulv_level(rdev, ulv_level); |
2865 | } |
2866 | |
2867 | static int ci_populate_all_memory_levels(struct radeon_device *rdev) |
2868 | { |
2869 | struct ci_power_info *pi = ci_get_pi(rdev); |
2870 | struct ci_dpm_table *dpm_table = &pi->dpm_table; |
2871 | u32 level_array_address = pi->dpm_table_start + |
2872 | offsetof(SMU7_Discrete_DpmTable, MemoryLevel); |
2873 | u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * |
2874 | SMU7_MAX_LEVELS_MEMORY; |
2875 | SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; |
2876 | u32 i, ret; |
2877 | |
2878 | memset(levels, 0, level_array_size); |
2879 | |
2880 | for (i = 0; i < dpm_table->mclk_table.count; i++) { |
2881 | if (dpm_table->mclk_table.dpm_levels[i].value == 0) |
2882 | return -EINVAL; |
2883 | ret = ci_populate_single_memory_level(rdev, |
2884 | dpm_table->mclk_table.dpm_levels[i].value, |
2885 | &pi->smc_state_table.MemoryLevel[i]); |
2886 | if (ret) |
2887 | return ret; |
2888 | } |
2889 | |
2890 | pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); |
2891 | |
2892 | pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; |
2893 | pi->dpm_level_enable_mask.mclk_dpm_enable_mask = |
2894 | ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); |
2895 | |
2896 | pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = |
2897 | PPSMC_DISPLAY_WATERMARK_HIGH; |
2898 | |
2899 | ret = ci_copy_bytes_to_smc(rdev, level_array_address, |
2900 | (u8 *)levels, level_array_size, |
2901 | pi->sram_end); |
2902 | if (ret) |
2903 | return ret; |
2904 | |
2905 | return 0; |
2906 | } |
2907 | |
2908 | static void ci_reset_single_dpm_table(struct radeon_device *rdev, |
2909 | struct ci_single_dpm_table* dpm_table, |
2910 | u32 count) |
2911 | { |
2912 | u32 i; |
2913 | |
2914 | dpm_table->count = count; |
2915 | for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) |
2916 | dpm_table->dpm_levels[i].enabled = false; |
2917 | } |
2918 | |
2919 | static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table, |
2920 | u32 index, u32 pcie_gen, u32 pcie_lanes) |
2921 | { |
2922 | dpm_table->dpm_levels[index].value = pcie_gen; |
2923 | dpm_table->dpm_levels[index].param1 = pcie_lanes; |
2924 | dpm_table->dpm_levels[index].enabled = true; |
2925 | } |
2926 | |
2927 | static int ci_setup_default_pcie_tables(struct radeon_device *rdev) |
2928 | { |
2929 | struct ci_power_info *pi = ci_get_pi(rdev); |
2930 | |
2931 | if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) |
2932 | return -EINVAL; |
2933 | |
2934 | if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { |
2935 | pi->pcie_gen_powersaving = pi->pcie_gen_performance; |
2936 | pi->pcie_lane_powersaving = pi->pcie_lane_performance; |
2937 | } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { |
2938 | pi->pcie_gen_performance = pi->pcie_gen_powersaving; |
2939 | pi->pcie_lane_performance = pi->pcie_lane_powersaving; |
2940 | } |
2941 | |
2942 | ci_reset_single_dpm_table(rdev, |
2943 | &pi->dpm_table.pcie_speed_table, |
2944 | SMU7_MAX_LEVELS_LINK); |
2945 | |
2946 | ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, |
2947 | pi->pcie_gen_powersaving.min, |
2948 | pi->pcie_lane_powersaving.min); |
2949 | ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, |
2950 | pi->pcie_gen_performance.min, |
2951 | pi->pcie_lane_performance.min); |
2952 | ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, |
2953 | pi->pcie_gen_powersaving.min, |
2954 | pi->pcie_lane_powersaving.max); |
2955 | ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, |
2956 | pi->pcie_gen_performance.min, |
2957 | pi->pcie_lane_performance.max); |
2958 | ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, |
2959 | pi->pcie_gen_powersaving.max, |
2960 | pi->pcie_lane_powersaving.max); |
2961 | ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, |
2962 | pi->pcie_gen_performance.max, |
2963 | pi->pcie_lane_performance.max); |
2964 | |
2965 | pi->dpm_table.pcie_speed_table.count = 6; |
2966 | |
2967 | return 0; |
2968 | } |
2969 | |
2970 | static int ci_setup_default_dpm_tables(struct radeon_device *rdev) |
2971 | { |
2972 | struct ci_power_info *pi = ci_get_pi(rdev); |
2973 | struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = |
2974 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; |
2975 | struct radeon_clock_voltage_dependency_table *allowed_mclk_table = |
2976 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; |
2977 | struct radeon_cac_leakage_table *std_voltage_table = |
2978 | &rdev->pm.dpm.dyn_state.cac_leakage_table; |
2979 | u32 i; |
2980 | |
2981 | if (allowed_sclk_vddc_table == NULL) |
2982 | return -EINVAL; |
2983 | if (allowed_sclk_vddc_table->count < 1) |
2984 | return -EINVAL; |
2985 | if (allowed_mclk_table == NULL) |
2986 | return -EINVAL; |
2987 | if (allowed_mclk_table->count < 1) |
2988 | return -EINVAL; |
2989 | |
2990 | memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); |
2991 | |
2992 | ci_reset_single_dpm_table(rdev, |
2993 | &pi->dpm_table.sclk_table, |
2994 | SMU7_MAX_LEVELS_GRAPHICS); |
2995 | ci_reset_single_dpm_table(rdev, |
2996 | &pi->dpm_table.mclk_table, |
2997 | SMU7_MAX_LEVELS_MEMORY); |
2998 | ci_reset_single_dpm_table(rdev, |
2999 | &pi->dpm_table.vddc_table, |
3000 | SMU7_MAX_LEVELS_VDDC); |
3001 | ci_reset_single_dpm_table(rdev, |
3002 | &pi->dpm_table.vddci_table, |
3003 | SMU7_MAX_LEVELS_VDDCI); |
3004 | ci_reset_single_dpm_table(rdev, |
3005 | &pi->dpm_table.mvdd_table, |
3006 | SMU7_MAX_LEVELS_MVDD); |
3007 | |
3008 | pi->dpm_table.sclk_table.count = 0; |
3009 | for (i = 0; i < allowed_sclk_vddc_table->count; i++) { |
3010 | if ((i == 0) || |
3011 | (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != |
3012 | allowed_sclk_vddc_table->entries[i].clk)) { |
3013 | pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = |
3014 | allowed_sclk_vddc_table->entries[i].clk; |
3015 | pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = true; |
3016 | pi->dpm_table.sclk_table.count++; |
3017 | } |
3018 | } |
3019 | |
3020 | pi->dpm_table.mclk_table.count = 0; |
3021 | for (i = 0; i < allowed_mclk_table->count; i++) { |
3022 | if ((i==0) || |
3023 | (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != |
3024 | allowed_mclk_table->entries[i].clk)) { |
3025 | pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = |
3026 | allowed_mclk_table->entries[i].clk; |
3027 | pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = true; |
3028 | pi->dpm_table.mclk_table.count++; |
3029 | } |
3030 | } |
3031 | |
3032 | for (i = 0; i < allowed_sclk_vddc_table->count; i++) { |
3033 | pi->dpm_table.vddc_table.dpm_levels[i].value = |
3034 | allowed_sclk_vddc_table->entries[i].v; |
3035 | pi->dpm_table.vddc_table.dpm_levels[i].param1 = |
3036 | std_voltage_table->entries[i].leakage; |
3037 | pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; |
3038 | } |
3039 | pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; |
3040 | |
3041 | allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; |
3042 | if (allowed_mclk_table) { |
3043 | for (i = 0; i < allowed_mclk_table->count; i++) { |
3044 | pi->dpm_table.vddci_table.dpm_levels[i].value = |
3045 | allowed_mclk_table->entries[i].v; |
3046 | pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; |
3047 | } |
3048 | pi->dpm_table.vddci_table.count = allowed_mclk_table->count; |
3049 | } |
3050 | |
3051 | allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; |
3052 | if (allowed_mclk_table) { |
3053 | for (i = 0; i < allowed_mclk_table->count; i++) { |
3054 | pi->dpm_table.mvdd_table.dpm_levels[i].value = |
3055 | allowed_mclk_table->entries[i].v; |
3056 | pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; |
3057 | } |
3058 | pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; |
3059 | } |
3060 | |
3061 | ci_setup_default_pcie_tables(rdev); |
3062 | |
3063 | return 0; |
3064 | } |
3065 | |
3066 | static int ci_find_boot_level(struct ci_single_dpm_table *table, |
3067 | u32 value, u32 *boot_level) |
3068 | { |
3069 | u32 i; |
3070 | int ret = -EINVAL; |
3071 | |
3072 | for(i = 0; i < table->count; i++) { |
3073 | if (value == table->dpm_levels[i].value) { |
3074 | *boot_level = i; |
3075 | ret = 0; |
3076 | } |
3077 | } |
3078 | |
3079 | return ret; |
3080 | } |
3081 | |
3082 | static int ci_init_smc_table(struct radeon_device *rdev) |
3083 | { |
3084 | struct ci_power_info *pi = ci_get_pi(rdev); |
3085 | struct ci_ulv_parm *ulv = &pi->ulv; |
3086 | struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; |
3087 | SMU7_Discrete_DpmTable *table = &pi->smc_state_table; |
3088 | int ret; |
3089 | |
3090 | ret = ci_setup_default_dpm_tables(rdev); |
3091 | if (ret) |
3092 | return ret; |
3093 | |
3094 | if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) |
3095 | ci_populate_smc_voltage_tables(rdev, table); |
3096 | |
3097 | ci_init_fps_limits(rdev); |
3098 | |
3099 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) |
3100 | table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; |
3101 | |
3102 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) |
3103 | table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; |
3104 | |
3105 | if (pi->mem_gddr5) |
3106 | table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; |
3107 | |
3108 | if (ulv->supported) { |
3109 | ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); |
3110 | if (ret) |
3111 | return ret; |
3112 | WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); |
3113 | } |
3114 | |
3115 | ret = ci_populate_all_graphic_levels(rdev); |
3116 | if (ret) |
3117 | return ret; |
3118 | |
3119 | ret = ci_populate_all_memory_levels(rdev); |
3120 | if (ret) |
3121 | return ret; |
3122 | |
3123 | ci_populate_smc_link_level(rdev, table); |
3124 | |
3125 | ret = ci_populate_smc_acpi_level(rdev, table); |
3126 | if (ret) |
3127 | return ret; |
3128 | |
3129 | ret = ci_populate_smc_vce_level(rdev, table); |
3130 | if (ret) |
3131 | return ret; |
3132 | |
3133 | ret = ci_populate_smc_acp_level(rdev, table); |
3134 | if (ret) |
3135 | return ret; |
3136 | |
3137 | ret = ci_populate_smc_samu_level(rdev, table); |
3138 | if (ret) |
3139 | return ret; |
3140 | |
3141 | ret = ci_do_program_memory_timing_parameters(rdev); |
3142 | if (ret) |
3143 | return ret; |
3144 | |
3145 | ret = ci_populate_smc_uvd_level(rdev, table); |
3146 | if (ret) |
3147 | return ret; |
3148 | |
3149 | table->UvdBootLevel = 0; |
3150 | table->VceBootLevel = 0; |
3151 | table->AcpBootLevel = 0; |
3152 | table->SamuBootLevel = 0; |
3153 | table->GraphicsBootLevel = 0; |
3154 | table->MemoryBootLevel = 0; |
3155 | |
3156 | ret = ci_find_boot_level(&pi->dpm_table.sclk_table, |
3157 | pi->vbios_boot_state.sclk_bootup_value, |
3158 | (u32 *)&pi->smc_state_table.GraphicsBootLevel); |
3159 | |
3160 | ret = ci_find_boot_level(&pi->dpm_table.mclk_table, |
3161 | pi->vbios_boot_state.mclk_bootup_value, |
3162 | (u32 *)&pi->smc_state_table.MemoryBootLevel); |
3163 | |
3164 | table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; |
3165 | table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; |
3166 | table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; |
3167 | |
3168 | ci_populate_smc_initial_state(rdev, radeon_boot_state); |
3169 | |
3170 | ret = ci_populate_bapm_parameters_in_dpm_table(rdev); |
3171 | if (ret) |
3172 | return ret; |
3173 | |
3174 | table->UVDInterval = 1; |
3175 | table->VCEInterval = 1; |
3176 | table->ACPInterval = 1; |
3177 | table->SAMUInterval = 1; |
3178 | table->GraphicsVoltageChangeEnable = 1; |
3179 | table->GraphicsThermThrottleEnable = 1; |
3180 | table->GraphicsInterval = 1; |
3181 | table->VoltageInterval = 1; |
3182 | table->ThermalInterval = 1; |
3183 | table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * |
3184 | CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); |
3185 | table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * |
3186 | CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); |
3187 | table->MemoryVoltageChangeEnable = 1; |
3188 | table->MemoryInterval = 1; |
3189 | table->VoltageResponseTime = 0; |
3190 | table->VddcVddciDelta = 4000; |
3191 | table->PhaseResponseTime = 0; |
3192 | table->MemoryThermThrottleEnable = 1; |
3193 | table->PCIeBootLinkLevel = 0; |
3194 | table->PCIeGenInterval = 1; |
3195 | if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) |
3196 | table->SVI2Enable = 1; |
3197 | else |
3198 | table->SVI2Enable = 0; |
3199 | |
3200 | table->ThermGpio = 17; |
3201 | table->SclkStepSize = 0x4000; |
3202 | |
3203 | table->SystemFlags = cpu_to_be32(table->SystemFlags); |
3204 | table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid); |
3205 | table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase); |
3206 | table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid); |
3207 | table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid); |
3208 | table->SclkStepSize = cpu_to_be32(table->SclkStepSize); |
3209 | table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh); |
3210 | table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow); |
3211 | table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta); |
3212 | table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime); |
3213 | table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime); |
3214 | table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE); |
3215 | table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE); |
3216 | table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE); |
3217 | |
3218 | ret = ci_copy_bytes_to_smc(rdev, |
3219 | pi->dpm_table_start + |
3220 | offsetof(SMU7_Discrete_DpmTable, SystemFlags), |
3221 | (u8 *)&table->SystemFlags, |
3222 | sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController), |
3223 | pi->sram_end); |
3224 | if (ret) |
3225 | return ret; |
3226 | |
3227 | return 0; |
3228 | } |
3229 | |
3230 | static void ci_trim_single_dpm_states(struct radeon_device *rdev, |
3231 | struct ci_single_dpm_table *dpm_table, |
3232 | u32 low_limit, u32 high_limit) |
3233 | { |
3234 | u32 i; |
3235 | |
3236 | for (i = 0; i < dpm_table->count; i++) { |
3237 | if ((dpm_table->dpm_levels[i].value < low_limit) || |
3238 | (dpm_table->dpm_levels[i].value > high_limit)) |
3239 | dpm_table->dpm_levels[i].enabled = false; |
3240 | else |
3241 | dpm_table->dpm_levels[i].enabled = true; |
3242 | } |
3243 | } |
3244 | |
3245 | static void ci_trim_pcie_dpm_states(struct radeon_device *rdev, |
3246 | u32 speed_low, u32 lanes_low, |
3247 | u32 speed_high, u32 lanes_high) |
3248 | { |
3249 | struct ci_power_info *pi = ci_get_pi(rdev); |
3250 | struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; |
3251 | u32 i, j; |
3252 | |
3253 | for (i = 0; i < pcie_table->count; i++) { |
3254 | if ((pcie_table->dpm_levels[i].value < speed_low) || |
3255 | (pcie_table->dpm_levels[i].param1 < lanes_low) || |
3256 | (pcie_table->dpm_levels[i].value > speed_high) || |
3257 | (pcie_table->dpm_levels[i].param1 > lanes_high)) |
3258 | pcie_table->dpm_levels[i].enabled = false; |
3259 | else |
3260 | pcie_table->dpm_levels[i].enabled = true; |
3261 | } |
3262 | |
3263 | for (i = 0; i < pcie_table->count; i++) { |
3264 | if (pcie_table->dpm_levels[i].enabled) { |
3265 | for (j = i + 1; j < pcie_table->count; j++) { |
3266 | if (pcie_table->dpm_levels[j].enabled) { |
3267 | if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) && |
3268 | (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1)) |
3269 | pcie_table->dpm_levels[j].enabled = false; |
3270 | } |
3271 | } |
3272 | } |
3273 | } |
3274 | } |
3275 | |
3276 | static int ci_trim_dpm_states(struct radeon_device *rdev, |
3277 | struct radeon_ps *radeon_state) |
3278 | { |
3279 | struct ci_ps *state = ci_get_ps(radeon_state); |
3280 | struct ci_power_info *pi = ci_get_pi(rdev); |
3281 | u32 high_limit_count; |
3282 | |
3283 | if (state->performance_level_count < 1) |
3284 | return -EINVAL; |
3285 | |
3286 | if (state->performance_level_count == 1) |
3287 | high_limit_count = 0; |
3288 | else |
3289 | high_limit_count = 1; |
3290 | |
3291 | ci_trim_single_dpm_states(rdev, |
3292 | &pi->dpm_table.sclk_table, |
3293 | state->performance_levels[0].sclk, |
3294 | state->performance_levels[high_limit_count].sclk); |
3295 | |
3296 | ci_trim_single_dpm_states(rdev, |
3297 | &pi->dpm_table.mclk_table, |
3298 | state->performance_levels[0].mclk, |
3299 | state->performance_levels[high_limit_count].mclk); |
3300 | |
3301 | ci_trim_pcie_dpm_states(rdev, |
3302 | state->performance_levels[0].pcie_gen, |
3303 | state->performance_levels[0].pcie_lane, |
3304 | state->performance_levels[high_limit_count].pcie_gen, |
3305 | state->performance_levels[high_limit_count].pcie_lane); |
3306 | |
3307 | return 0; |
3308 | } |
3309 | |
3310 | static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev) |
3311 | { |
3312 | struct radeon_clock_voltage_dependency_table *disp_voltage_table = |
3313 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; |
3314 | struct radeon_clock_voltage_dependency_table *vddc_table = |
3315 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; |
3316 | u32 requested_voltage = 0; |
3317 | u32 i; |
3318 | |
3319 | if (disp_voltage_table == NULL) |
3320 | return -EINVAL; |
3321 | if (!disp_voltage_table->count) |
3322 | return -EINVAL; |
3323 | |
3324 | for (i = 0; i < disp_voltage_table->count; i++) { |
3325 | if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk) |
3326 | requested_voltage = disp_voltage_table->entries[i].v; |
3327 | } |
3328 | |
3329 | for (i = 0; i < vddc_table->count; i++) { |
3330 | if (requested_voltage <= vddc_table->entries[i].v) { |
3331 | requested_voltage = vddc_table->entries[i].v; |
3332 | return (ci_send_msg_to_smc_with_parameter(rdev, |
3333 | PPSMC_MSG_VddC_Request, |
3334 | requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ? |
3335 | 0 : -EINVAL; |
3336 | } |
3337 | } |
3338 | |
3339 | return -EINVAL; |
3340 | } |
3341 | |
3342 | static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev) |
3343 | { |
3344 | struct ci_power_info *pi = ci_get_pi(rdev); |
3345 | PPSMC_Result result; |
3346 | |
3347 | if (!pi->sclk_dpm_key_disabled) { |
3348 | if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { |
3349 | result = ci_send_msg_to_smc_with_parameter(rdev, |
3350 | PPSMC_MSG_SCLKDPM_SetEnabledMask, |
3351 | pi->dpm_level_enable_mask.sclk_dpm_enable_mask); |
3352 | if (result != PPSMC_Result_OK) |
3353 | return -EINVAL; |
3354 | } |
3355 | } |
3356 | |
3357 | if (!pi->mclk_dpm_key_disabled) { |
3358 | if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { |
3359 | result = ci_send_msg_to_smc_with_parameter(rdev, |
3360 | PPSMC_MSG_MCLKDPM_SetEnabledMask, |
3361 | pi->dpm_level_enable_mask.mclk_dpm_enable_mask); |
3362 | if (result != PPSMC_Result_OK) |
3363 | return -EINVAL; |
3364 | } |
3365 | } |
3366 | |
3367 | if (!pi->pcie_dpm_key_disabled) { |
3368 | if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { |
3369 | result = ci_send_msg_to_smc_with_parameter(rdev, |
3370 | PPSMC_MSG_PCIeDPM_SetEnabledMask, |
3371 | pi->dpm_level_enable_mask.pcie_dpm_enable_mask); |
3372 | if (result != PPSMC_Result_OK) |
3373 | return -EINVAL; |
3374 | } |
3375 | } |
3376 | |
3377 | ci_apply_disp_minimum_voltage_request(rdev); |
3378 | |
3379 | return 0; |
3380 | } |
3381 | |
3382 | static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev, |
3383 | struct radeon_ps *radeon_state) |
3384 | { |
3385 | struct ci_power_info *pi = ci_get_pi(rdev); |
3386 | struct ci_ps *state = ci_get_ps(radeon_state); |
3387 | struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; |
3388 | u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; |
3389 | struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; |
3390 | u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; |
3391 | u32 i; |
3392 | |
3393 | pi->need_update_smu7_dpm_table = 0; |
3394 | |
3395 | for (i = 0; i < sclk_table->count; i++) { |
3396 | if (sclk == sclk_table->dpm_levels[i].value) |
3397 | break; |
3398 | } |
3399 | |
3400 | if (i >= sclk_table->count) { |
3401 | pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; |
3402 | } else { |
3403 | /* XXX check display min clock requirements */ |
3404 | if (0 != CISLAND_MINIMUM_ENGINE_CLOCK) |
3405 | pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; |
3406 | } |
3407 | |
3408 | for (i = 0; i < mclk_table->count; i++) { |
3409 | if (mclk == mclk_table->dpm_levels[i].value) |
3410 | break; |
3411 | } |
3412 | |
3413 | if (i >= mclk_table->count) |
3414 | pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; |
3415 | |
3416 | if (rdev->pm.dpm.current_active_crtc_count != |
3417 | rdev->pm.dpm.new_active_crtc_count) |
3418 | pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; |
3419 | } |
3420 | |
3421 | static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev, |
3422 | struct radeon_ps *radeon_state) |
3423 | { |
3424 | struct ci_power_info *pi = ci_get_pi(rdev); |
3425 | struct ci_ps *state = ci_get_ps(radeon_state); |
3426 | u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; |
3427 | u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; |
3428 | struct ci_dpm_table *dpm_table = &pi->dpm_table; |
3429 | int ret; |
3430 | |
3431 | if (!pi->need_update_smu7_dpm_table) |
3432 | return 0; |
3433 | |
3434 | if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) |
3435 | dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; |
3436 | |
3437 | if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) |
3438 | dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; |
3439 | |
3440 | if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { |
3441 | ret = ci_populate_all_graphic_levels(rdev); |
3442 | if (ret) |
3443 | return ret; |
3444 | } |
3445 | |
3446 | if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { |
3447 | ret = ci_populate_all_memory_levels(rdev); |
3448 | if (ret) |
3449 | return ret; |
3450 | } |
3451 | |
3452 | return 0; |
3453 | } |
3454 | |
3455 | static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable) |
3456 | { |
3457 | struct ci_power_info *pi = ci_get_pi(rdev); |
3458 | const struct radeon_clock_and_voltage_limits *max_limits; |
3459 | int i; |
3460 | |
3461 | if (rdev->pm.dpm.ac_power) |
3462 | max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
3463 | else |
3464 | max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; |
3465 | |
3466 | if (enable) { |
3467 | pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; |
3468 | |
3469 | for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { |
3470 | if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { |
3471 | pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; |
3472 | |
3473 | if (!pi->caps_uvd_dpm) |
3474 | break; |
3475 | } |
3476 | } |
3477 | |
3478 | ci_send_msg_to_smc_with_parameter(rdev, |
3479 | PPSMC_MSG_UVDDPM_SetEnabledMask, |
3480 | pi->dpm_level_enable_mask.uvd_dpm_enable_mask); |
3481 | |
3482 | if (pi->last_mclk_dpm_enable_mask & 0x1) { |
3483 | pi->uvd_enabled = true; |
3484 | pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; |
3485 | ci_send_msg_to_smc_with_parameter(rdev, |
3486 | PPSMC_MSG_MCLKDPM_SetEnabledMask, |
3487 | pi->dpm_level_enable_mask.mclk_dpm_enable_mask); |
3488 | } |
3489 | } else { |
3490 | if (pi->last_mclk_dpm_enable_mask & 0x1) { |
3491 | pi->uvd_enabled = false; |
3492 | pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; |
3493 | ci_send_msg_to_smc_with_parameter(rdev, |
3494 | PPSMC_MSG_MCLKDPM_SetEnabledMask, |
3495 | pi->dpm_level_enable_mask.mclk_dpm_enable_mask); |
3496 | } |
3497 | } |
3498 | |
3499 | return (ci_send_msg_to_smc(rdev, enable ? |
3500 | PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ? |
3501 | 0 : -EINVAL; |
3502 | } |
3503 | |
3504 | static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable) |
3505 | { |
3506 | struct ci_power_info *pi = ci_get_pi(rdev); |
3507 | const struct radeon_clock_and_voltage_limits *max_limits; |
3508 | int i; |
3509 | |
3510 | if (rdev->pm.dpm.ac_power) |
3511 | max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
3512 | else |
3513 | max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; |
3514 | |
3515 | if (enable) { |
3516 | pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; |
3517 | for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { |
3518 | if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { |
3519 | pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; |
3520 | |
3521 | if (!pi->caps_vce_dpm) |
3522 | break; |
3523 | } |
3524 | } |
3525 | |
3526 | ci_send_msg_to_smc_with_parameter(rdev, |
3527 | PPSMC_MSG_VCEDPM_SetEnabledMask, |
3528 | pi->dpm_level_enable_mask.vce_dpm_enable_mask); |
3529 | } |
3530 | |
3531 | return (ci_send_msg_to_smc(rdev, enable ? |
3532 | PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ? |
3533 | 0 : -EINVAL; |
3534 | } |
3535 | |
3536 | #if 0 |
3537 | static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable) |
3538 | { |
3539 | struct ci_power_info *pi = ci_get_pi(rdev); |
3540 | const struct radeon_clock_and_voltage_limits *max_limits; |
3541 | int i; |
3542 | |
3543 | if (rdev->pm.dpm.ac_power) |
3544 | max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
3545 | else |
3546 | max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; |
3547 | |
3548 | if (enable) { |
3549 | pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0; |
3550 | for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) { |
3551 | if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { |
3552 | pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i; |
3553 | |
3554 | if (!pi->caps_samu_dpm) |
3555 | break; |
3556 | } |
3557 | } |
3558 | |
3559 | ci_send_msg_to_smc_with_parameter(rdev, |
3560 | PPSMC_MSG_SAMUDPM_SetEnabledMask, |
3561 | pi->dpm_level_enable_mask.samu_dpm_enable_mask); |
3562 | } |
3563 | return (ci_send_msg_to_smc(rdev, enable ? |
3564 | PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ? |
3565 | 0 : -EINVAL; |
3566 | } |
3567 | |
3568 | static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable) |
3569 | { |
3570 | struct ci_power_info *pi = ci_get_pi(rdev); |
3571 | const struct radeon_clock_and_voltage_limits *max_limits; |
3572 | int i; |
3573 | |
3574 | if (rdev->pm.dpm.ac_power) |
3575 | max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
3576 | else |
3577 | max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; |
3578 | |
3579 | if (enable) { |
3580 | pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0; |
3581 | for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) { |
3582 | if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { |
3583 | pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i; |
3584 | |
3585 | if (!pi->caps_acp_dpm) |
3586 | break; |
3587 | } |
3588 | } |
3589 | |
3590 | ci_send_msg_to_smc_with_parameter(rdev, |
3591 | PPSMC_MSG_ACPDPM_SetEnabledMask, |
3592 | pi->dpm_level_enable_mask.acp_dpm_enable_mask); |
3593 | } |
3594 | |
3595 | return (ci_send_msg_to_smc(rdev, enable ? |
3596 | PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ? |
3597 | 0 : -EINVAL; |
3598 | } |
3599 | #endif |
3600 | |
3601 | static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate) |
3602 | { |
3603 | struct ci_power_info *pi = ci_get_pi(rdev); |
3604 | u32 tmp; |
3605 | |
3606 | if (!gate) { |
3607 | if (pi->caps_uvd_dpm || |
3608 | (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) |
3609 | pi->smc_state_table.UvdBootLevel = 0; |
3610 | else |
3611 | pi->smc_state_table.UvdBootLevel = |
3612 | rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; |
3613 | |
3614 | tmp = RREG32_SMC(DPM_TABLE_475); |
3615 | tmp &= ~UvdBootLevel_MASK; |
3616 | tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); |
3617 | WREG32_SMC(DPM_TABLE_475, tmp); |
3618 | } |
3619 | |
3620 | return ci_enable_uvd_dpm(rdev, !gate); |
3621 | } |
3622 | |
3623 | static u8 ci_get_vce_boot_level(struct radeon_device *rdev) |
3624 | { |
3625 | u8 i; |
3626 | u32 min_evclk = 30000; /* ??? */ |
3627 | struct radeon_vce_clock_voltage_dependency_table *table = |
3628 | &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; |
3629 | |
3630 | for (i = 0; i < table->count; i++) { |
3631 | if (table->entries[i].evclk >= min_evclk) |
3632 | return i; |
3633 | } |
3634 | |
3635 | return table->count - 1; |
3636 | } |
3637 | |
3638 | static int ci_update_vce_dpm(struct radeon_device *rdev, |
3639 | struct radeon_ps *radeon_new_state, |
3640 | struct radeon_ps *radeon_current_state) |
3641 | { |
3642 | struct ci_power_info *pi = ci_get_pi(rdev); |
3643 | int ret = 0; |
3644 | u32 tmp; |
3645 | |
3646 | if (radeon_current_state->evclk != radeon_new_state->evclk) { |
3647 | if (radeon_new_state->evclk) { |
3648 | /* turn the clocks on when encoding */ |
3649 | cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false); |
3650 | |
3651 | pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); |
3652 | tmp = RREG32_SMC(DPM_TABLE_475); |
3653 | tmp &= ~VceBootLevel_MASK; |
3654 | tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); |
3655 | WREG32_SMC(DPM_TABLE_475, tmp); |
3656 | |
3657 | ret = ci_enable_vce_dpm(rdev, true); |
3658 | } else { |
3659 | /* turn the clocks off when not encoding */ |
3660 | cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true); |
3661 | |
3662 | ret = ci_enable_vce_dpm(rdev, false); |
3663 | } |
3664 | } |
3665 | return ret; |
3666 | } |
3667 | |
3668 | #if 0 |
3669 | static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate) |
3670 | { |
3671 | return ci_enable_samu_dpm(rdev, gate); |
3672 | } |
3673 | |
3674 | static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate) |
3675 | { |
3676 | struct ci_power_info *pi = ci_get_pi(rdev); |
3677 | u32 tmp; |
3678 | |
3679 | if (!gate) { |
3680 | pi->smc_state_table.AcpBootLevel = 0; |
3681 | |
3682 | tmp = RREG32_SMC(DPM_TABLE_475); |
3683 | tmp &= ~AcpBootLevel_MASK; |
3684 | tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel); |
3685 | WREG32_SMC(DPM_TABLE_475, tmp); |
3686 | } |
3687 | |
3688 | return ci_enable_acp_dpm(rdev, !gate); |
3689 | } |
3690 | #endif |
3691 | |
3692 | static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev, |
3693 | struct radeon_ps *radeon_state) |
3694 | { |
3695 | struct ci_power_info *pi = ci_get_pi(rdev); |
3696 | int ret; |
3697 | |
3698 | ret = ci_trim_dpm_states(rdev, radeon_state); |
3699 | if (ret) |
3700 | return ret; |
3701 | |
3702 | pi->dpm_level_enable_mask.sclk_dpm_enable_mask = |
3703 | ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); |
3704 | pi->dpm_level_enable_mask.mclk_dpm_enable_mask = |
3705 | ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); |
3706 | pi->last_mclk_dpm_enable_mask = |
3707 | pi->dpm_level_enable_mask.mclk_dpm_enable_mask; |
3708 | if (pi->uvd_enabled) { |
3709 | if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) |
3710 | pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; |
3711 | } |
3712 | pi->dpm_level_enable_mask.pcie_dpm_enable_mask = |
3713 | ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); |
3714 | |
3715 | return 0; |
3716 | } |
3717 | |
3718 | static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev, |
3719 | u32 level_mask) |
3720 | { |
3721 | u32 level = 0; |
3722 | |
3723 | while ((level_mask & (1 << level)) == 0) |
3724 | level++; |
3725 | |
3726 | return level; |
3727 | } |
3728 | |
3729 | |
3730 | int ci_dpm_force_performance_level(struct radeon_device *rdev, |
3731 | enum radeon_dpm_forced_level level) |
3732 | { |
3733 | struct ci_power_info *pi = ci_get_pi(rdev); |
3734 | PPSMC_Result smc_result; |
3735 | u32 tmp, levels, i; |
3736 | int ret; |
3737 | |
3738 | if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { |
3739 | if ((!pi->sclk_dpm_key_disabled) && |
3740 | pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { |
3741 | levels = 0; |
3742 | tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; |
3743 | while (tmp >>= 1) |
3744 | levels++; |
3745 | if (levels) { |
3746 | ret = ci_dpm_force_state_sclk(rdev, levels); |
3747 | if (ret) |
3748 | return ret; |
3749 | for (i = 0; i < rdev->usec_timeout; i++) { |
3750 | tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & |
3751 | CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; |
3752 | if (tmp == levels) |
3753 | break; |
3754 | udelay(1); |
3755 | } |
3756 | } |
3757 | } |
3758 | if ((!pi->mclk_dpm_key_disabled) && |
3759 | pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { |
3760 | levels = 0; |
3761 | tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; |
3762 | while (tmp >>= 1) |
3763 | levels++; |
3764 | if (levels) { |
3765 | ret = ci_dpm_force_state_mclk(rdev, levels); |
3766 | if (ret) |
3767 | return ret; |
3768 | for (i = 0; i < rdev->usec_timeout; i++) { |
3769 | tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & |
3770 | CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; |
3771 | if (tmp == levels) |
3772 | break; |
3773 | udelay(1); |
3774 | } |
3775 | } |
3776 | } |
3777 | if ((!pi->pcie_dpm_key_disabled) && |
3778 | pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { |
3779 | levels = 0; |
3780 | tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; |
3781 | while (tmp >>= 1) |
3782 | levels++; |
3783 | if (levels) { |
3784 | ret = ci_dpm_force_state_pcie(rdev, level); |
3785 | if (ret) |
3786 | return ret; |
3787 | for (i = 0; i < rdev->usec_timeout; i++) { |
3788 | tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & |
3789 | CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; |
3790 | if (tmp == levels) |
3791 | break; |
3792 | udelay(1); |
3793 | } |
3794 | } |
3795 | } |
3796 | } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { |
3797 | if ((!pi->sclk_dpm_key_disabled) && |
3798 | pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { |
3799 | levels = ci_get_lowest_enabled_level(rdev, |
3800 | pi->dpm_level_enable_mask.sclk_dpm_enable_mask); |
3801 | ret = ci_dpm_force_state_sclk(rdev, levels); |
3802 | if (ret) |
3803 | return ret; |
3804 | for (i = 0; i < rdev->usec_timeout; i++) { |
3805 | tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & |
3806 | CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; |
3807 | if (tmp == levels) |
3808 | break; |
3809 | udelay(1); |
3810 | } |
3811 | } |
3812 | if ((!pi->mclk_dpm_key_disabled) && |
3813 | pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { |
3814 | levels = ci_get_lowest_enabled_level(rdev, |
3815 | pi->dpm_level_enable_mask.mclk_dpm_enable_mask); |
3816 | ret = ci_dpm_force_state_mclk(rdev, levels); |
3817 | if (ret) |
3818 | return ret; |
3819 | for (i = 0; i < rdev->usec_timeout; i++) { |
3820 | tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & |
3821 | CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; |
3822 | if (tmp == levels) |
3823 | break; |
3824 | udelay(1); |
3825 | } |
3826 | } |
3827 | if ((!pi->pcie_dpm_key_disabled) && |
3828 | pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { |
3829 | levels = ci_get_lowest_enabled_level(rdev, |
3830 | pi->dpm_level_enable_mask.pcie_dpm_enable_mask); |
3831 | ret = ci_dpm_force_state_pcie(rdev, levels); |
3832 | if (ret) |
3833 | return ret; |
3834 | for (i = 0; i < rdev->usec_timeout; i++) { |
3835 | tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & |
3836 | CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; |
3837 | if (tmp == levels) |
3838 | break; |
3839 | udelay(1); |
3840 | } |
3841 | } |
3842 | } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { |
3843 | if (!pi->sclk_dpm_key_disabled) { |
3844 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel); |
3845 | if (smc_result != PPSMC_Result_OK) |
3846 | return -EINVAL; |
3847 | } |
3848 | if (!pi->mclk_dpm_key_disabled) { |
3849 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_NoForcedLevel); |
3850 | if (smc_result != PPSMC_Result_OK) |
3851 | return -EINVAL; |
3852 | } |
3853 | if (!pi->pcie_dpm_key_disabled) { |
3854 | smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_UnForceLevel); |
3855 | if (smc_result != PPSMC_Result_OK) |
3856 | return -EINVAL; |
3857 | } |
3858 | } |
3859 | |
3860 | rdev->pm.dpm.forced_level = level; |
3861 | |
3862 | return 0; |
3863 | } |
3864 | |
3865 | static int ci_set_mc_special_registers(struct radeon_device *rdev, |
3866 | struct ci_mc_reg_table *table) |
3867 | { |
3868 | struct ci_power_info *pi = ci_get_pi(rdev); |
3869 | u8 i, j, k; |
3870 | u32 temp_reg; |
3871 | |
3872 | for (i = 0, j = table->last; i < table->last; i++) { |
3873 | if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) |
3874 | return -EINVAL; |
3875 | switch(table->mc_reg_address[i].s1 << 2) { |
3876 | case MC_SEQ_MISC1: |
3877 | temp_reg = RREG32(MC_PMG_CMD_EMRS); |
3878 | table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; |
3879 | table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; |
3880 | for (k = 0; k < table->num_entries; k++) { |
3881 | table->mc_reg_table_entry[k].mc_data[j] = |
3882 | ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); |
3883 | } |
3884 | j++; |
3885 | if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) |
3886 | return -EINVAL; |
3887 | |
3888 | temp_reg = RREG32(MC_PMG_CMD_MRS); |
3889 | table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; |
3890 | table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; |
3891 | for (k = 0; k < table->num_entries; k++) { |
3892 | table->mc_reg_table_entry[k].mc_data[j] = |
3893 | (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); |
3894 | if (!pi->mem_gddr5) |
3895 | table->mc_reg_table_entry[k].mc_data[j] |= 0x100; |
3896 | } |
3897 | j++; |
3898 | if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) |
3899 | return -EINVAL; |
3900 | |
3901 | if (!pi->mem_gddr5) { |
3902 | table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; |
3903 | table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; |
3904 | for (k = 0; k < table->num_entries; k++) { |
3905 | table->mc_reg_table_entry[k].mc_data[j] = |
3906 | (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; |
3907 | } |
3908 | j++; |
3909 | if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) |
3910 | return -EINVAL; |
3911 | } |
3912 | break; |
3913 | case MC_SEQ_RESERVE_M: |
3914 | temp_reg = RREG32(MC_PMG_CMD_MRS1); |
3915 | table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; |
3916 | table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; |
3917 | for (k = 0; k < table->num_entries; k++) { |
3918 | table->mc_reg_table_entry[k].mc_data[j] = |
3919 | (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); |
3920 | } |
3921 | j++; |
3922 | if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) |
3923 | return -EINVAL; |
3924 | break; |
3925 | default: |
3926 | break; |
3927 | } |
3928 | |
3929 | } |
3930 | |
3931 | table->last = j; |
3932 | |
3933 | return 0; |
3934 | } |
3935 | |
3936 | static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) |
3937 | { |
3938 | bool result = true; |
3939 | |
3940 | switch(in_reg) { |
3941 | case MC_SEQ_RAS_TIMING >> 2: |
3942 | *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; |
3943 | break; |
3944 | case MC_SEQ_DLL_STBY >> 2: |
3945 | *out_reg = MC_SEQ_DLL_STBY_LP >> 2; |
3946 | break; |
3947 | case MC_SEQ_G5PDX_CMD0 >> 2: |
3948 | *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2; |
3949 | break; |
3950 | case MC_SEQ_G5PDX_CMD1 >> 2: |
3951 | *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2; |
3952 | break; |
3953 | case MC_SEQ_G5PDX_CTRL >> 2: |
3954 | *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2; |
3955 | break; |
3956 | case MC_SEQ_CAS_TIMING >> 2: |
3957 | *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; |
3958 | break; |
3959 | case MC_SEQ_MISC_TIMING >> 2: |
3960 | *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; |
3961 | break; |
3962 | case MC_SEQ_MISC_TIMING2 >> 2: |
3963 | *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; |
3964 | break; |
3965 | case MC_SEQ_PMG_DVS_CMD >> 2: |
3966 | *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2; |
3967 | break; |
3968 | case MC_SEQ_PMG_DVS_CTL >> 2: |
3969 | *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2; |
3970 | break; |
3971 | case MC_SEQ_RD_CTL_D0 >> 2: |
3972 | *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; |
3973 | break; |
3974 | case MC_SEQ_RD_CTL_D1 >> 2: |
3975 | *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; |
3976 | break; |
3977 | case MC_SEQ_WR_CTL_D0 >> 2: |
3978 | *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; |
3979 | break; |
3980 | case MC_SEQ_WR_CTL_D1 >> 2: |
3981 | *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; |
3982 | break; |
3983 | case MC_PMG_CMD_EMRS >> 2: |
3984 | *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; |
3985 | break; |
3986 | case MC_PMG_CMD_MRS >> 2: |
3987 | *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; |
3988 | break; |
3989 | case MC_PMG_CMD_MRS1 >> 2: |
3990 | *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; |
3991 | break; |
3992 | case MC_SEQ_PMG_TIMING >> 2: |
3993 | *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; |
3994 | break; |
3995 | case MC_PMG_CMD_MRS2 >> 2: |
3996 | *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; |
3997 | break; |
3998 | case MC_SEQ_WR_CTL_2 >> 2: |
3999 | *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; |
4000 | break; |
4001 | default: |
4002 | result = false; |
4003 | break; |
4004 | } |
4005 | |
4006 | return result; |
4007 | } |
4008 | |
4009 | static void ci_set_valid_flag(struct ci_mc_reg_table *table) |
4010 | { |
4011 | u8 i, j; |
4012 | |
4013 | for (i = 0; i < table->last; i++) { |
4014 | for (j = 1; j < table->num_entries; j++) { |
4015 | if (table->mc_reg_table_entry[j-1].mc_data[i] != |
4016 | table->mc_reg_table_entry[j].mc_data[i]) { |
4017 | table->valid_flag |= 1 << i; |
4018 | break; |
4019 | } |
4020 | } |
4021 | } |
4022 | } |
4023 | |
4024 | static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) |
4025 | { |
4026 | u32 i; |
4027 | u16 address; |
4028 | |
4029 | for (i = 0; i < table->last; i++) { |
4030 | table->mc_reg_address[i].s0 = |
4031 | ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? |
4032 | address : table->mc_reg_address[i].s1; |
4033 | } |
4034 | } |
4035 | |
4036 | static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table, |
4037 | struct ci_mc_reg_table *ci_table) |
4038 | { |
4039 | u8 i, j; |
4040 | |
4041 | if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) |
4042 | return -EINVAL; |
4043 | if (table->num_entries > MAX_AC_TIMING_ENTRIES) |
4044 | return -EINVAL; |
4045 | |
4046 | for (i = 0; i < table->last; i++) |
4047 | ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; |
4048 | |
4049 | ci_table->last = table->last; |
4050 | |
4051 | for (i = 0; i < table->num_entries; i++) { |
4052 | ci_table->mc_reg_table_entry[i].mclk_max = |
4053 | table->mc_reg_table_entry[i].mclk_max; |
4054 | for (j = 0; j < table->last; j++) |
4055 | ci_table->mc_reg_table_entry[i].mc_data[j] = |
4056 | table->mc_reg_table_entry[i].mc_data[j]; |
4057 | } |
4058 | ci_table->num_entries = table->num_entries; |
4059 | |
4060 | return 0; |
4061 | } |
4062 | |
4063 | static int ci_initialize_mc_reg_table(struct radeon_device *rdev) |
4064 | { |
4065 | struct ci_power_info *pi = ci_get_pi(rdev); |
4066 | struct atom_mc_reg_table *table; |
4067 | struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; |
4068 | u8 module_index = rv770_get_memory_module_index(rdev); |
4069 | int ret; |
4070 | |
4071 | table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); |
4072 | if (!table) |
4073 | return -ENOMEM; |
4074 | |
4075 | WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); |
4076 | WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); |
4077 | WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY)); |
4078 | WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0)); |
4079 | WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1)); |
4080 | WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL)); |
4081 | WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD)); |
4082 | WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL)); |
4083 | WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); |
4084 | WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); |
4085 | WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); |
4086 | WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); |
4087 | WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); |
4088 | WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); |
4089 | WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); |
4090 | WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); |
4091 | WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); |
4092 | WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); |
4093 | WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); |
4094 | WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); |
4095 | |
4096 | ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); |
4097 | if (ret) |
4098 | goto init_mc_done; |
4099 | |
4100 | ret = ci_copy_vbios_mc_reg_table(table, ci_table); |
4101 | if (ret) |
4102 | goto init_mc_done; |
4103 | |
4104 | ci_set_s0_mc_reg_index(ci_table); |
4105 | |
4106 | ret = ci_set_mc_special_registers(rdev, ci_table); |
4107 | if (ret) |
4108 | goto init_mc_done; |
4109 | |
4110 | ci_set_valid_flag(ci_table); |
4111 | |
4112 | init_mc_done: |
4113 | kfree(table); |
4114 | |
4115 | return ret; |
4116 | } |
4117 | |
4118 | static int ci_populate_mc_reg_addresses(struct radeon_device *rdev, |
4119 | SMU7_Discrete_MCRegisters *mc_reg_table) |
4120 | { |
4121 | struct ci_power_info *pi = ci_get_pi(rdev); |
4122 | u32 i, j; |
4123 | |
4124 | for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { |
4125 | if (pi->mc_reg_table.valid_flag & (1 << j)) { |
4126 | if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) |
4127 | return -EINVAL; |
4128 | mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); |
4129 | mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); |
4130 | i++; |
4131 | } |
4132 | } |
4133 | |
4134 | mc_reg_table->last = (u8)i; |
4135 | |
4136 | return 0; |
4137 | } |
4138 | |
4139 | static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry, |
4140 | SMU7_Discrete_MCRegisterSet *data, |
4141 | u32 num_entries, u32 valid_flag) |
4142 | { |
4143 | u32 i, j; |
4144 | |
4145 | for (i = 0, j = 0; j < num_entries; j++) { |
4146 | if (valid_flag & (1 << j)) { |
4147 | data->value[i] = cpu_to_be32(entry->mc_data[j]); |
4148 | i++; |
4149 | } |
4150 | } |
4151 | } |
4152 | |
4153 | static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, |
4154 | const u32 memory_clock, |
4155 | SMU7_Discrete_MCRegisterSet *mc_reg_table_data) |
4156 | { |
4157 | struct ci_power_info *pi = ci_get_pi(rdev); |
4158 | u32 i = 0; |
4159 | |
4160 | for(i = 0; i < pi->mc_reg_table.num_entries; i++) { |
4161 | if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) |
4162 | break; |
4163 | } |
4164 | |
4165 | if ((i == pi->mc_reg_table.num_entries) && (i > 0)) |
4166 | --i; |
4167 | |
4168 | ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], |
4169 | mc_reg_table_data, pi->mc_reg_table.last, |
4170 | pi->mc_reg_table.valid_flag); |
4171 | } |
4172 | |
4173 | static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev, |
4174 | SMU7_Discrete_MCRegisters *mc_reg_table) |
4175 | { |
4176 | struct ci_power_info *pi = ci_get_pi(rdev); |
4177 | u32 i; |
4178 | |
4179 | for (i = 0; i < pi->dpm_table.mclk_table.count; i++) |
4180 | ci_convert_mc_reg_table_entry_to_smc(rdev, |
4181 | pi->dpm_table.mclk_table.dpm_levels[i].value, |
4182 | &mc_reg_table->data[i]); |
4183 | } |
4184 | |
4185 | static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev) |
4186 | { |
4187 | struct ci_power_info *pi = ci_get_pi(rdev); |
4188 | int ret; |
4189 | |
4190 | memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); |
4191 | |
4192 | ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); |
4193 | if (ret) |
4194 | return ret; |
4195 | ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); |
4196 | |
4197 | return ci_copy_bytes_to_smc(rdev, |
4198 | pi->mc_reg_table_start, |
4199 | (u8 *)&pi->smc_mc_reg_table, |
4200 | sizeof(SMU7_Discrete_MCRegisters), |
4201 | pi->sram_end); |
4202 | } |
4203 | |
4204 | static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev) |
4205 | { |
4206 | struct ci_power_info *pi = ci_get_pi(rdev); |
4207 | |
4208 | if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) |
4209 | return 0; |
4210 | |
4211 | memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); |
4212 | |
4213 | ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); |
4214 | |
4215 | return ci_copy_bytes_to_smc(rdev, |
4216 | pi->mc_reg_table_start + |
4217 | offsetof(SMU7_Discrete_MCRegisters, data[0]), |
4218 | (u8 *)&pi->smc_mc_reg_table.data[0], |
4219 | sizeof(SMU7_Discrete_MCRegisterSet) * |
4220 | pi->dpm_table.mclk_table.count, |
4221 | pi->sram_end); |
4222 | } |
4223 | |
4224 | static void ci_enable_voltage_control(struct radeon_device *rdev) |
4225 | { |
4226 | u32 tmp = RREG32_SMC(GENERAL_PWRMGT); |
4227 | |
4228 | tmp |= VOLT_PWRMGT_EN; |
4229 | WREG32_SMC(GENERAL_PWRMGT, tmp); |
4230 | } |
4231 | |
4232 | static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev, |
4233 | struct radeon_ps *radeon_state) |
4234 | { |
4235 | struct ci_ps *state = ci_get_ps(radeon_state); |
4236 | int i; |
4237 | u16 pcie_speed, max_speed = 0; |
4238 | |
4239 | for (i = 0; i < state->performance_level_count; i++) { |
4240 | pcie_speed = state->performance_levels[i].pcie_gen; |
4241 | if (max_speed < pcie_speed) |
4242 | max_speed = pcie_speed; |
4243 | } |
4244 | |
4245 | return max_speed; |
4246 | } |
4247 | |
4248 | static u16 ci_get_current_pcie_speed(struct radeon_device *rdev) |
4249 | { |
4250 | u32 speed_cntl = 0; |
4251 | |
4252 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; |
4253 | speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; |
4254 | |
4255 | return (u16)speed_cntl; |
4256 | } |
4257 | |
4258 | static int ci_get_current_pcie_lane_number(struct radeon_device *rdev) |
4259 | { |
4260 | u32 link_width = 0; |
4261 | |
4262 | link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; |
4263 | link_width >>= LC_LINK_WIDTH_RD_SHIFT; |
4264 | |
4265 | switch (link_width) { |
4266 | case RADEON_PCIE_LC_LINK_WIDTH_X1: |
4267 | return 1; |
4268 | case RADEON_PCIE_LC_LINK_WIDTH_X2: |
4269 | return 2; |
4270 | case RADEON_PCIE_LC_LINK_WIDTH_X4: |
4271 | return 4; |
4272 | case RADEON_PCIE_LC_LINK_WIDTH_X8: |
4273 | return 8; |
4274 | case RADEON_PCIE_LC_LINK_WIDTH_X12: |
4275 | /* not actually supported */ |
4276 | return 12; |
4277 | case RADEON_PCIE_LC_LINK_WIDTH_X0: |
4278 | case RADEON_PCIE_LC_LINK_WIDTH_X16: |
4279 | default: |
4280 | return 16; |
4281 | } |
4282 | } |
4283 | |
4284 | static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev, |
4285 | struct radeon_ps *radeon_new_state, |
4286 | struct radeon_ps *radeon_current_state) |
4287 | { |
4288 | struct ci_power_info *pi = ci_get_pi(rdev); |
4289 | enum radeon_pcie_gen target_link_speed = |
4290 | ci_get_maximum_link_speed(rdev, radeon_new_state); |
4291 | enum radeon_pcie_gen current_link_speed; |
4292 | |
4293 | if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) |
4294 | current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state); |
4295 | else |
4296 | current_link_speed = pi->force_pcie_gen; |
4297 | |
4298 | pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; |
4299 | pi->pspp_notify_required = false; |
4300 | if (target_link_speed > current_link_speed) { |
4301 | switch (target_link_speed) { |
4302 | #ifdef CONFIG_ACPI |
4303 | case RADEON_PCIE_GEN3: |
4304 | if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) |
4305 | break; |
4306 | pi->force_pcie_gen = RADEON_PCIE_GEN2; |
4307 | if (current_link_speed == RADEON_PCIE_GEN2) |
4308 | break; |
4309 | case RADEON_PCIE_GEN2: |
4310 | if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) |
4311 | break; |
4312 | #endif |
4313 | default: |
4314 | pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); |
4315 | break; |
4316 | } |
4317 | } else { |
4318 | if (target_link_speed < current_link_speed) |
4319 | pi->pspp_notify_required = true; |
4320 | } |
4321 | } |
4322 | |
4323 | static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev, |
4324 | struct radeon_ps *radeon_new_state, |
4325 | struct radeon_ps *radeon_current_state) |
4326 | { |
4327 | struct ci_power_info *pi = ci_get_pi(rdev); |
4328 | enum radeon_pcie_gen target_link_speed = |
4329 | ci_get_maximum_link_speed(rdev, radeon_new_state); |
4330 | u8 request; |
4331 | |
4332 | if (pi->pspp_notify_required) { |
4333 | if (target_link_speed == RADEON_PCIE_GEN3) |
4334 | request = PCIE_PERF_REQ_PECI_GEN3; |
4335 | else if (target_link_speed == RADEON_PCIE_GEN2) |
4336 | request = PCIE_PERF_REQ_PECI_GEN2; |
4337 | else |
4338 | request = PCIE_PERF_REQ_PECI_GEN1; |
4339 | |
4340 | if ((request == PCIE_PERF_REQ_PECI_GEN1) && |
4341 | (ci_get_current_pcie_speed(rdev) > 0)) |
4342 | return; |
4343 | |
4344 | #ifdef CONFIG_ACPI |
4345 | radeon_acpi_pcie_performance_request(rdev, request, false); |
4346 | #endif |
4347 | } |
4348 | } |
4349 | |
4350 | static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev) |
4351 | { |
4352 | struct ci_power_info *pi = ci_get_pi(rdev); |
4353 | struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = |
4354 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; |
4355 | struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table = |
4356 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; |
4357 | struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table = |
4358 | &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; |
4359 | |
4360 | if (allowed_sclk_vddc_table == NULL) |
4361 | return -EINVAL; |
4362 | if (allowed_sclk_vddc_table->count < 1) |
4363 | return -EINVAL; |
4364 | if (allowed_mclk_vddc_table == NULL) |
4365 | return -EINVAL; |
4366 | if (allowed_mclk_vddc_table->count < 1) |
4367 | return -EINVAL; |
4368 | if (allowed_mclk_vddci_table == NULL) |
4369 | return -EINVAL; |
4370 | if (allowed_mclk_vddci_table->count < 1) |
4371 | return -EINVAL; |
4372 | |
4373 | pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; |
4374 | pi->max_vddc_in_pp_table = |
4375 | allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; |
4376 | |
4377 | pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; |
4378 | pi->max_vddci_in_pp_table = |
4379 | allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; |
4380 | |
4381 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = |
4382 | allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; |
4383 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = |
4384 | allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; |
4385 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = |
4386 | allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; |
4387 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = |
4388 | allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; |
4389 | |
4390 | return 0; |
4391 | } |
4392 | |
4393 | static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc) |
4394 | { |
4395 | struct ci_power_info *pi = ci_get_pi(rdev); |
4396 | struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; |
4397 | u32 leakage_index; |
4398 | |
4399 | for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { |
4400 | if (leakage_table->leakage_id[leakage_index] == *vddc) { |
4401 | *vddc = leakage_table->actual_voltage[leakage_index]; |
4402 | break; |
4403 | } |
4404 | } |
4405 | } |
4406 | |
4407 | static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci) |
4408 | { |
4409 | struct ci_power_info *pi = ci_get_pi(rdev); |
4410 | struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; |
4411 | u32 leakage_index; |
4412 | |
4413 | for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { |
4414 | if (leakage_table->leakage_id[leakage_index] == *vddci) { |
4415 | *vddci = leakage_table->actual_voltage[leakage_index]; |
4416 | break; |
4417 | } |
4418 | } |
4419 | } |
4420 | |
4421 | static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, |
4422 | struct radeon_clock_voltage_dependency_table *table) |
4423 | { |
4424 | u32 i; |
4425 | |
4426 | if (table) { |
4427 | for (i = 0; i < table->count; i++) |
4428 | ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); |
4429 | } |
4430 | } |
4431 | |
4432 | static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev, |
4433 | struct radeon_clock_voltage_dependency_table *table) |
4434 | { |
4435 | u32 i; |
4436 | |
4437 | if (table) { |
4438 | for (i = 0; i < table->count; i++) |
4439 | ci_patch_with_vddci_leakage(rdev, &table->entries[i].v); |
4440 | } |
4441 | } |
4442 | |
4443 | static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, |
4444 | struct radeon_vce_clock_voltage_dependency_table *table) |
4445 | { |
4446 | u32 i; |
4447 | |
4448 | if (table) { |
4449 | for (i = 0; i < table->count; i++) |
4450 | ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); |
4451 | } |
4452 | } |
4453 | |
4454 | static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, |
4455 | struct radeon_uvd_clock_voltage_dependency_table *table) |
4456 | { |
4457 | u32 i; |
4458 | |
4459 | if (table) { |
4460 | for (i = 0; i < table->count; i++) |
4461 | ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); |
4462 | } |
4463 | } |
4464 | |
4465 | static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev, |
4466 | struct radeon_phase_shedding_limits_table *table) |
4467 | { |
4468 | u32 i; |
4469 | |
4470 | if (table) { |
4471 | for (i = 0; i < table->count; i++) |
4472 | ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage); |
4473 | } |
4474 | } |
4475 | |
4476 | static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev, |
4477 | struct radeon_clock_and_voltage_limits *table) |
4478 | { |
4479 | if (table) { |
4480 | ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc); |
4481 | ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci); |
4482 | } |
4483 | } |
4484 | |
4485 | static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev, |
4486 | struct radeon_cac_leakage_table *table) |
4487 | { |
4488 | u32 i; |
4489 | |
4490 | if (table) { |
4491 | for (i = 0; i < table->count; i++) |
4492 | ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc); |
4493 | } |
4494 | } |
4495 | |
4496 | static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev) |
4497 | { |
4498 | |
4499 | ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, |
4500 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); |
4501 | ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, |
4502 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); |
4503 | ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, |
4504 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); |
4505 | ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev, |
4506 | &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); |
4507 | ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev, |
4508 | &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); |
4509 | ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev, |
4510 | &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); |
4511 | ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, |
4512 | &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); |
4513 | ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, |
4514 | &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); |
4515 | ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev, |
4516 | &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); |
4517 | ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, |
4518 | &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); |
4519 | ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, |
4520 | &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); |
4521 | ci_patch_cac_leakage_table_with_vddc_leakage(rdev, |
4522 | &rdev->pm.dpm.dyn_state.cac_leakage_table); |
4523 | |
4524 | } |
4525 | |
4526 | static void ci_get_memory_type(struct radeon_device *rdev) |
4527 | { |
4528 | struct ci_power_info *pi = ci_get_pi(rdev); |
4529 | u32 tmp; |
4530 | |
4531 | tmp = RREG32(MC_SEQ_MISC0); |
4532 | |
4533 | if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) == |
4534 | MC_SEQ_MISC0_GDDR5_VALUE) |
4535 | pi->mem_gddr5 = true; |
4536 | else |
4537 | pi->mem_gddr5 = false; |
4538 | |
4539 | } |
4540 | |
4541 | static void ci_update_current_ps(struct radeon_device *rdev, |
4542 | struct radeon_ps *rps) |
4543 | { |
4544 | struct ci_ps *new_ps = ci_get_ps(rps); |
4545 | struct ci_power_info *pi = ci_get_pi(rdev); |
4546 | |
4547 | pi->current_rps = *rps; |
4548 | pi->current_ps = *new_ps; |
4549 | pi->current_rps.ps_priv = &pi->current_ps; |
4550 | } |
4551 | |
4552 | static void ci_update_requested_ps(struct radeon_device *rdev, |
4553 | struct radeon_ps *rps) |
4554 | { |
4555 | struct ci_ps *new_ps = ci_get_ps(rps); |
4556 | struct ci_power_info *pi = ci_get_pi(rdev); |
4557 | |
4558 | pi->requested_rps = *rps; |
4559 | pi->requested_ps = *new_ps; |
4560 | pi->requested_rps.ps_priv = &pi->requested_ps; |
4561 | } |
4562 | |
4563 | int ci_dpm_pre_set_power_state(struct radeon_device *rdev) |
4564 | { |
4565 | struct ci_power_info *pi = ci_get_pi(rdev); |
4566 | struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; |
4567 | struct radeon_ps *new_ps = &requested_ps; |
4568 | |
4569 | ci_update_requested_ps(rdev, new_ps); |
4570 | |
4571 | ci_apply_state_adjust_rules(rdev, &pi->requested_rps); |
4572 | |
4573 | return 0; |
4574 | } |
4575 | |
4576 | void ci_dpm_post_set_power_state(struct radeon_device *rdev) |
4577 | { |
4578 | struct ci_power_info *pi = ci_get_pi(rdev); |
4579 | struct radeon_ps *new_ps = &pi->requested_rps; |
4580 | |
4581 | ci_update_current_ps(rdev, new_ps); |
4582 | } |
4583 | |
4584 | |
4585 | void ci_dpm_setup_asic(struct radeon_device *rdev) |
4586 | { |
4587 | int r; |
4588 | |
4589 | r = ci_mc_load_microcode(rdev); |
4590 | if (r) |
4591 | DRM_ERROR("Failed to load MC firmware!\n" ); |
4592 | ci_read_clock_registers(rdev); |
4593 | ci_get_memory_type(rdev); |
4594 | ci_enable_acpi_power_management(rdev); |
4595 | ci_init_sclk_t(rdev); |
4596 | } |
4597 | |
4598 | int ci_dpm_enable(struct radeon_device *rdev) |
4599 | { |
4600 | struct ci_power_info *pi = ci_get_pi(rdev); |
4601 | struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; |
4602 | int ret; |
4603 | |
4604 | if (ci_is_smc_running(rdev)) |
4605 | return -EINVAL; |
4606 | if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { |
4607 | ci_enable_voltage_control(rdev); |
4608 | ret = ci_construct_voltage_tables(rdev); |
4609 | if (ret) { |
4610 | DRM_ERROR("ci_construct_voltage_tables failed\n" ); |
4611 | return ret; |
4612 | } |
4613 | } |
4614 | if (pi->caps_dynamic_ac_timing) { |
4615 | ret = ci_initialize_mc_reg_table(rdev); |
4616 | if (ret) |
4617 | pi->caps_dynamic_ac_timing = false; |
4618 | } |
4619 | if (pi->dynamic_ss) |
4620 | ci_enable_spread_spectrum(rdev, true); |
4621 | if (pi->thermal_protection) |
4622 | ci_enable_thermal_protection(rdev, true); |
4623 | ci_program_sstp(rdev); |
4624 | ci_enable_display_gap(rdev); |
4625 | ci_program_vc(rdev); |
4626 | ret = ci_upload_firmware(rdev); |
4627 | if (ret) { |
4628 | DRM_ERROR("ci_upload_firmware failed\n" ); |
4629 | return ret; |
4630 | } |
4631 | ret = ci_process_firmware_header(rdev); |
4632 | if (ret) { |
4633 | DRM_ERROR("ci_process_firmware_header failed\n" ); |
4634 | return ret; |
4635 | } |
4636 | ret = ci_initial_switch_from_arb_f0_to_f1(rdev); |
4637 | if (ret) { |
4638 | DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n" ); |
4639 | return ret; |
4640 | } |
4641 | ret = ci_init_smc_table(rdev); |
4642 | if (ret) { |
4643 | DRM_ERROR("ci_init_smc_table failed\n" ); |
4644 | return ret; |
4645 | } |
4646 | ret = ci_init_arb_table_index(rdev); |
4647 | if (ret) { |
4648 | DRM_ERROR("ci_init_arb_table_index failed\n" ); |
4649 | return ret; |
4650 | } |
4651 | if (pi->caps_dynamic_ac_timing) { |
4652 | ret = ci_populate_initial_mc_reg_table(rdev); |
4653 | if (ret) { |
4654 | DRM_ERROR("ci_populate_initial_mc_reg_table failed\n" ); |
4655 | return ret; |
4656 | } |
4657 | } |
4658 | ret = ci_populate_pm_base(rdev); |
4659 | if (ret) { |
4660 | DRM_ERROR("ci_populate_pm_base failed\n" ); |
4661 | return ret; |
4662 | } |
4663 | ci_dpm_start_smc(rdev); |
4664 | ci_enable_vr_hot_gpio_interrupt(rdev); |
4665 | ret = ci_notify_smc_display_change(rdev, false); |
4666 | if (ret) { |
4667 | DRM_ERROR("ci_notify_smc_display_change failed\n" ); |
4668 | return ret; |
4669 | } |
4670 | ci_enable_sclk_control(rdev, true); |
4671 | ret = ci_enable_ulv(rdev, true); |
4672 | if (ret) { |
4673 | DRM_ERROR("ci_enable_ulv failed\n" ); |
4674 | return ret; |
4675 | } |
4676 | ret = ci_enable_ds_master_switch(rdev, true); |
4677 | if (ret) { |
4678 | DRM_ERROR("ci_enable_ds_master_switch failed\n" ); |
4679 | return ret; |
4680 | } |
4681 | ret = ci_start_dpm(rdev); |
4682 | if (ret) { |
4683 | DRM_ERROR("ci_start_dpm failed\n" ); |
4684 | return ret; |
4685 | } |
4686 | ret = ci_enable_didt(rdev, true); |
4687 | if (ret) { |
4688 | DRM_ERROR("ci_enable_didt failed\n" ); |
4689 | return ret; |
4690 | } |
4691 | ret = ci_enable_smc_cac(rdev, true); |
4692 | if (ret) { |
4693 | DRM_ERROR("ci_enable_smc_cac failed\n" ); |
4694 | return ret; |
4695 | } |
4696 | ret = ci_enable_power_containment(rdev, true); |
4697 | if (ret) { |
4698 | DRM_ERROR("ci_enable_power_containment failed\n" ); |
4699 | return ret; |
4700 | } |
4701 | |
4702 | ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); |
4703 | |
4704 | ci_update_current_ps(rdev, boot_ps); |
4705 | |
4706 | return 0; |
4707 | } |
4708 | |
4709 | int ci_dpm_late_enable(struct radeon_device *rdev) |
4710 | { |
4711 | int ret; |
4712 | |
4713 | if (rdev->irq.installed && |
4714 | r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { |
4715 | #if 0 |
4716 | PPSMC_Result result; |
4717 | #endif |
4718 | ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); |
4719 | if (ret) { |
4720 | DRM_ERROR("ci_set_thermal_temperature_range failed\n" ); |
4721 | return ret; |
4722 | } |
4723 | rdev->irq.dpm_thermal = true; |
4724 | radeon_irq_set(rdev); |
4725 | #if 0 |
4726 | result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); |
4727 | |
4728 | if (result != PPSMC_Result_OK) |
4729 | DRM_DEBUG_KMS("Could not enable thermal interrupts.\n" ); |
4730 | #endif |
4731 | } |
4732 | |
4733 | ci_dpm_powergate_uvd(rdev, true); |
4734 | |
4735 | return 0; |
4736 | } |
4737 | |
4738 | void ci_dpm_disable(struct radeon_device *rdev) |
4739 | { |
4740 | struct ci_power_info *pi = ci_get_pi(rdev); |
4741 | struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; |
4742 | |
4743 | ci_dpm_powergate_uvd(rdev, false); |
4744 | |
4745 | if (!ci_is_smc_running(rdev)) |
4746 | return; |
4747 | |
4748 | if (pi->thermal_protection) |
4749 | ci_enable_thermal_protection(rdev, false); |
4750 | ci_enable_power_containment(rdev, false); |
4751 | ci_enable_smc_cac(rdev, false); |
4752 | ci_enable_didt(rdev, false); |
4753 | ci_enable_spread_spectrum(rdev, false); |
4754 | ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); |
4755 | ci_stop_dpm(rdev); |
4756 | ci_enable_ds_master_switch(rdev, true); |
4757 | ci_enable_ulv(rdev, false); |
4758 | ci_clear_vc(rdev); |
4759 | ci_reset_to_default(rdev); |
4760 | ci_dpm_stop_smc(rdev); |
4761 | ci_force_switch_to_arb_f0(rdev); |
4762 | |
4763 | ci_update_current_ps(rdev, boot_ps); |
4764 | } |
4765 | |
4766 | int ci_dpm_set_power_state(struct radeon_device *rdev) |
4767 | { |
4768 | struct ci_power_info *pi = ci_get_pi(rdev); |
4769 | struct radeon_ps *new_ps = &pi->requested_rps; |
4770 | struct radeon_ps *old_ps = &pi->current_rps; |
4771 | int ret; |
4772 | |
4773 | ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps); |
4774 | if (pi->pcie_performance_request) |
4775 | ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); |
4776 | ret = ci_freeze_sclk_mclk_dpm(rdev); |
4777 | if (ret) { |
4778 | DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n" ); |
4779 | return ret; |
4780 | } |
4781 | ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps); |
4782 | if (ret) { |
4783 | DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n" ); |
4784 | return ret; |
4785 | } |
4786 | ret = ci_generate_dpm_level_enable_mask(rdev, new_ps); |
4787 | if (ret) { |
4788 | DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n" ); |
4789 | return ret; |
4790 | } |
4791 | |
4792 | ret = ci_update_vce_dpm(rdev, new_ps, old_ps); |
4793 | if (ret) { |
4794 | DRM_ERROR("ci_update_vce_dpm failed\n" ); |
4795 | return ret; |
4796 | } |
4797 | |
4798 | ret = ci_update_sclk_t(rdev); |
4799 | if (ret) { |
4800 | DRM_ERROR("ci_update_sclk_t failed\n" ); |
4801 | return ret; |
4802 | } |
4803 | if (pi->caps_dynamic_ac_timing) { |
4804 | ret = ci_update_and_upload_mc_reg_table(rdev); |
4805 | if (ret) { |
4806 | DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n" ); |
4807 | return ret; |
4808 | } |
4809 | } |
4810 | ret = ci_program_memory_timing_parameters(rdev); |
4811 | if (ret) { |
4812 | DRM_ERROR("ci_program_memory_timing_parameters failed\n" ); |
4813 | return ret; |
4814 | } |
4815 | ret = ci_unfreeze_sclk_mclk_dpm(rdev); |
4816 | if (ret) { |
4817 | DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n" ); |
4818 | return ret; |
4819 | } |
4820 | ret = ci_upload_dpm_level_enable_mask(rdev); |
4821 | if (ret) { |
4822 | DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n" ); |
4823 | return ret; |
4824 | } |
4825 | if (pi->pcie_performance_request) |
4826 | ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); |
4827 | |
4828 | return 0; |
4829 | } |
4830 | |
4831 | #ifndef __NetBSD__ /* XXX unused? */ |
4832 | int ci_dpm_power_control_set_level(struct radeon_device *rdev) |
4833 | { |
4834 | return ci_power_control_set_level(rdev); |
4835 | } |
4836 | |
4837 | void ci_dpm_reset_asic(struct radeon_device *rdev) |
4838 | { |
4839 | ci_set_boot_state(rdev); |
4840 | } |
4841 | #endif |
4842 | |
4843 | void ci_dpm_display_configuration_changed(struct radeon_device *rdev) |
4844 | { |
4845 | ci_program_display_gap(rdev); |
4846 | } |
4847 | |
4848 | union power_info { |
4849 | struct _ATOM_POWERPLAY_INFO info; |
4850 | struct _ATOM_POWERPLAY_INFO_V2 info_2; |
4851 | struct _ATOM_POWERPLAY_INFO_V3 info_3; |
4852 | struct _ATOM_PPLIB_POWERPLAYTABLE pplib; |
4853 | struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; |
4854 | struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; |
4855 | }; |
4856 | |
4857 | union pplib_clock_info { |
4858 | struct _ATOM_PPLIB_R600_CLOCK_INFO r600; |
4859 | struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; |
4860 | struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; |
4861 | struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; |
4862 | struct _ATOM_PPLIB_SI_CLOCK_INFO si; |
4863 | struct _ATOM_PPLIB_CI_CLOCK_INFO ci; |
4864 | }; |
4865 | |
4866 | union pplib_power_state { |
4867 | struct _ATOM_PPLIB_STATE v1; |
4868 | struct _ATOM_PPLIB_STATE_V2 v2; |
4869 | }; |
4870 | |
4871 | static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev, |
4872 | struct radeon_ps *rps, |
4873 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, |
4874 | u8 table_rev) |
4875 | { |
4876 | rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); |
4877 | rps->class = le16_to_cpu(non_clock_info->usClassification); |
4878 | rps->class2 = le16_to_cpu(non_clock_info->usClassification2); |
4879 | |
4880 | if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { |
4881 | rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); |
4882 | rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); |
4883 | } else { |
4884 | rps->vclk = 0; |
4885 | rps->dclk = 0; |
4886 | } |
4887 | |
4888 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) |
4889 | rdev->pm.dpm.boot_ps = rps; |
4890 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) |
4891 | rdev->pm.dpm.uvd_ps = rps; |
4892 | } |
4893 | |
4894 | static void ci_parse_pplib_clock_info(struct radeon_device *rdev, |
4895 | struct radeon_ps *rps, int index, |
4896 | union pplib_clock_info *clock_info) |
4897 | { |
4898 | struct ci_power_info *pi = ci_get_pi(rdev); |
4899 | struct ci_ps *ps = ci_get_ps(rps); |
4900 | struct ci_pl *pl = &ps->performance_levels[index]; |
4901 | |
4902 | ps->performance_level_count = index + 1; |
4903 | |
4904 | pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); |
4905 | pl->sclk |= clock_info->ci.ucEngineClockHigh << 16; |
4906 | pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); |
4907 | pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16; |
4908 | |
4909 | pl->pcie_gen = r600_get_pcie_gen_support(rdev, |
4910 | pi->sys_pcie_mask, |
4911 | pi->vbios_boot_state.pcie_gen_bootup_value, |
4912 | clock_info->ci.ucPCIEGen); |
4913 | pl->pcie_lane = r600_get_pcie_lane_support(rdev, |
4914 | pi->vbios_boot_state.pcie_lane_bootup_value, |
4915 | le16_to_cpu(clock_info->ci.usPCIELane)); |
4916 | |
4917 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { |
4918 | pi->acpi_pcie_gen = pl->pcie_gen; |
4919 | } |
4920 | |
4921 | if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { |
4922 | pi->ulv.supported = true; |
4923 | pi->ulv.pl = *pl; |
4924 | pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; |
4925 | } |
4926 | |
4927 | /* patch up boot state */ |
4928 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { |
4929 | pl->mclk = pi->vbios_boot_state.mclk_bootup_value; |
4930 | pl->sclk = pi->vbios_boot_state.sclk_bootup_value; |
4931 | pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; |
4932 | pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; |
4933 | } |
4934 | |
4935 | switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { |
4936 | case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: |
4937 | pi->use_pcie_powersaving_levels = true; |
4938 | if (pi->pcie_gen_powersaving.max < pl->pcie_gen) |
4939 | pi->pcie_gen_powersaving.max = pl->pcie_gen; |
4940 | if (pi->pcie_gen_powersaving.min > pl->pcie_gen) |
4941 | pi->pcie_gen_powersaving.min = pl->pcie_gen; |
4942 | if (pi->pcie_lane_powersaving.max < pl->pcie_lane) |
4943 | pi->pcie_lane_powersaving.max = pl->pcie_lane; |
4944 | if (pi->pcie_lane_powersaving.min > pl->pcie_lane) |
4945 | pi->pcie_lane_powersaving.min = pl->pcie_lane; |
4946 | break; |
4947 | case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: |
4948 | pi->use_pcie_performance_levels = true; |
4949 | if (pi->pcie_gen_performance.max < pl->pcie_gen) |
4950 | pi->pcie_gen_performance.max = pl->pcie_gen; |
4951 | if (pi->pcie_gen_performance.min > pl->pcie_gen) |
4952 | pi->pcie_gen_performance.min = pl->pcie_gen; |
4953 | if (pi->pcie_lane_performance.max < pl->pcie_lane) |
4954 | pi->pcie_lane_performance.max = pl->pcie_lane; |
4955 | if (pi->pcie_lane_performance.min > pl->pcie_lane) |
4956 | pi->pcie_lane_performance.min = pl->pcie_lane; |
4957 | break; |
4958 | default: |
4959 | break; |
4960 | } |
4961 | } |
4962 | |
4963 | static int ci_parse_power_table(struct radeon_device *rdev) |
4964 | { |
4965 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
4966 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; |
4967 | union pplib_power_state *power_state; |
4968 | int i, j, k, non_clock_array_index, clock_array_index; |
4969 | union pplib_clock_info *clock_info; |
4970 | struct _StateArray *state_array; |
4971 | struct _ClockInfoArray *clock_info_array; |
4972 | struct _NonClockInfoArray *non_clock_info_array; |
4973 | union power_info *power_info; |
4974 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); |
4975 | u16 data_offset; |
4976 | u8 frev, crev; |
4977 | u8 *power_state_offset; |
4978 | struct ci_ps *ps; |
4979 | |
4980 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, |
4981 | &frev, &crev, &data_offset)) |
4982 | return -EINVAL; |
4983 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); |
4984 | |
4985 | state_array = (struct _StateArray *) |
4986 | (mode_info->atom_context->bios + data_offset + |
4987 | le16_to_cpu(power_info->pplib.usStateArrayOffset)); |
4988 | clock_info_array = (struct _ClockInfoArray *) |
4989 | (mode_info->atom_context->bios + data_offset + |
4990 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); |
4991 | non_clock_info_array = (struct _NonClockInfoArray *) |
4992 | (mode_info->atom_context->bios + data_offset + |
4993 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); |
4994 | |
4995 | rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * |
4996 | state_array->ucNumEntries, GFP_KERNEL); |
4997 | if (!rdev->pm.dpm.ps) |
4998 | return -ENOMEM; |
4999 | power_state_offset = (u8 *)state_array->states; |
5000 | for (i = 0; i < state_array->ucNumEntries; i++) { |
5001 | u8 *idx; |
5002 | power_state = (union pplib_power_state *)power_state_offset; |
5003 | non_clock_array_index = power_state->v2.nonClockInfoIndex; |
5004 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) |
5005 | &non_clock_info_array->nonClockInfo[non_clock_array_index]; |
5006 | if (!rdev->pm.power_state[i].clock_info) |
5007 | return -EINVAL; |
5008 | ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL); |
5009 | if (ps == NULL) { |
5010 | kfree(rdev->pm.dpm.ps); |
5011 | return -ENOMEM; |
5012 | } |
5013 | rdev->pm.dpm.ps[i].ps_priv = ps; |
5014 | ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], |
5015 | non_clock_info, |
5016 | non_clock_info_array->ucEntrySize); |
5017 | k = 0; |
5018 | idx = (u8 *)&power_state->v2.clockInfoIndex[0]; |
5019 | for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { |
5020 | clock_array_index = idx[j]; |
5021 | if (clock_array_index >= clock_info_array->ucNumEntries) |
5022 | continue; |
5023 | if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS) |
5024 | break; |
5025 | clock_info = (union pplib_clock_info *) |
5026 | ((u8 *)&clock_info_array->clockInfo[0] + |
5027 | (clock_array_index * clock_info_array->ucEntrySize)); |
5028 | ci_parse_pplib_clock_info(rdev, |
5029 | &rdev->pm.dpm.ps[i], k, |
5030 | clock_info); |
5031 | k++; |
5032 | } |
5033 | power_state_offset += 2 + power_state->v2.ucNumDPMLevels; |
5034 | } |
5035 | rdev->pm.dpm.num_ps = state_array->ucNumEntries; |
5036 | |
5037 | /* fill in the vce power states */ |
5038 | for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { |
5039 | u32 sclk, mclk; |
5040 | clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; |
5041 | clock_info = (union pplib_clock_info *) |
5042 | &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; |
5043 | sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); |
5044 | sclk |= clock_info->ci.ucEngineClockHigh << 16; |
5045 | mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); |
5046 | mclk |= clock_info->ci.ucMemoryClockHigh << 16; |
5047 | rdev->pm.dpm.vce_states[i].sclk = sclk; |
5048 | rdev->pm.dpm.vce_states[i].mclk = mclk; |
5049 | } |
5050 | |
5051 | return 0; |
5052 | } |
5053 | |
5054 | static int ci_get_vbios_boot_values(struct radeon_device *rdev, |
5055 | struct ci_vbios_boot_state *boot_state) |
5056 | { |
5057 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
5058 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); |
5059 | ATOM_FIRMWARE_INFO_V2_2 *firmware_info; |
5060 | u8 frev, crev; |
5061 | u16 data_offset; |
5062 | |
5063 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
5064 | &frev, &crev, &data_offset)) { |
5065 | firmware_info = |
5066 | (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios + |
5067 | data_offset); |
5068 | boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage); |
5069 | boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage); |
5070 | boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage); |
5071 | boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev); |
5072 | boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev); |
5073 | boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock); |
5074 | boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock); |
5075 | |
5076 | return 0; |
5077 | } |
5078 | return -EINVAL; |
5079 | } |
5080 | |
5081 | void ci_dpm_fini(struct radeon_device *rdev) |
5082 | { |
5083 | int i; |
5084 | |
5085 | for (i = 0; i < rdev->pm.dpm.num_ps; i++) { |
5086 | kfree(rdev->pm.dpm.ps[i].ps_priv); |
5087 | } |
5088 | kfree(rdev->pm.dpm.ps); |
5089 | kfree(rdev->pm.dpm.priv); |
5090 | kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); |
5091 | r600_free_extended_power_table(rdev); |
5092 | } |
5093 | |
5094 | int ci_dpm_init(struct radeon_device *rdev) |
5095 | { |
5096 | int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); |
5097 | u16 data_offset, size; |
5098 | u8 frev, crev; |
5099 | struct ci_power_info *pi; |
5100 | int ret; |
5101 | #ifndef __NetBSD__ |
5102 | u32 mask; |
5103 | #endif |
5104 | |
5105 | pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); |
5106 | if (pi == NULL) |
5107 | return -ENOMEM; |
5108 | rdev->pm.dpm.priv = pi; |
5109 | |
5110 | #ifndef __NetBSD__ |
5111 | ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); |
5112 | if (ret) |
5113 | pi->sys_pcie_mask = 0; |
5114 | else |
5115 | pi->sys_pcie_mask = mask; |
5116 | #endif |
5117 | pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; |
5118 | |
5119 | pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; |
5120 | pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; |
5121 | pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; |
5122 | pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; |
5123 | |
5124 | pi->pcie_lane_performance.max = 0; |
5125 | pi->pcie_lane_performance.min = 16; |
5126 | pi->pcie_lane_powersaving.max = 0; |
5127 | pi->pcie_lane_powersaving.min = 16; |
5128 | |
5129 | ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); |
5130 | if (ret) { |
5131 | ci_dpm_fini(rdev); |
5132 | return ret; |
5133 | } |
5134 | |
5135 | ret = r600_get_platform_caps(rdev); |
5136 | if (ret) { |
5137 | ci_dpm_fini(rdev); |
5138 | return ret; |
5139 | } |
5140 | |
5141 | ret = r600_parse_extended_power_table(rdev); |
5142 | if (ret) { |
5143 | ci_dpm_fini(rdev); |
5144 | return ret; |
5145 | } |
5146 | |
5147 | ret = ci_parse_power_table(rdev); |
5148 | if (ret) { |
5149 | ci_dpm_fini(rdev); |
5150 | return ret; |
5151 | } |
5152 | |
5153 | pi->dll_default_on = false; |
5154 | pi->sram_end = SMC_RAM_END; |
5155 | |
5156 | pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; |
5157 | pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; |
5158 | pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; |
5159 | pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; |
5160 | pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; |
5161 | pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; |
5162 | pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; |
5163 | pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; |
5164 | |
5165 | pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; |
5166 | |
5167 | pi->sclk_dpm_key_disabled = 0; |
5168 | pi->mclk_dpm_key_disabled = 0; |
5169 | pi->pcie_dpm_key_disabled = 0; |
5170 | |
5171 | /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */ |
5172 | if ((rdev->pdev->device == 0x6658) && |
5173 | (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) { |
5174 | pi->mclk_dpm_key_disabled = 1; |
5175 | } |
5176 | |
5177 | pi->caps_sclk_ds = true; |
5178 | |
5179 | pi->mclk_strobe_mode_threshold = 40000; |
5180 | pi->mclk_stutter_mode_threshold = 40000; |
5181 | pi->mclk_edc_enable_threshold = 40000; |
5182 | pi->mclk_edc_wr_enable_threshold = 40000; |
5183 | |
5184 | ci_initialize_powertune_defaults(rdev); |
5185 | |
5186 | pi->caps_fps = false; |
5187 | |
5188 | pi->caps_sclk_throttle_low_notification = false; |
5189 | |
5190 | pi->caps_uvd_dpm = true; |
5191 | pi->caps_vce_dpm = true; |
5192 | |
5193 | ci_get_leakage_voltages(rdev); |
5194 | ci_patch_dependency_tables_with_leakage(rdev); |
5195 | ci_set_private_data_variables_based_on_pptable(rdev); |
5196 | |
5197 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = |
5198 | kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); |
5199 | if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { |
5200 | ci_dpm_fini(rdev); |
5201 | return -ENOMEM; |
5202 | } |
5203 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; |
5204 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; |
5205 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; |
5206 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; |
5207 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; |
5208 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; |
5209 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; |
5210 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; |
5211 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; |
5212 | |
5213 | rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; |
5214 | rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; |
5215 | rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; |
5216 | |
5217 | rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; |
5218 | rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; |
5219 | rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; |
5220 | rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; |
5221 | |
5222 | if (rdev->family == CHIP_HAWAII) { |
5223 | pi->thermal_temp_setting.temperature_low = 94500; |
5224 | pi->thermal_temp_setting.temperature_high = 95000; |
5225 | pi->thermal_temp_setting.temperature_shutdown = 104000; |
5226 | } else { |
5227 | pi->thermal_temp_setting.temperature_low = 99500; |
5228 | pi->thermal_temp_setting.temperature_high = 100000; |
5229 | pi->thermal_temp_setting.temperature_shutdown = 104000; |
5230 | } |
5231 | |
5232 | pi->uvd_enabled = false; |
5233 | |
5234 | pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; |
5235 | pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; |
5236 | pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; |
5237 | if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) |
5238 | pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; |
5239 | else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) |
5240 | pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; |
5241 | |
5242 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { |
5243 | if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) |
5244 | pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; |
5245 | else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) |
5246 | pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; |
5247 | else |
5248 | rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; |
5249 | } |
5250 | |
5251 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { |
5252 | if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) |
5253 | pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; |
5254 | else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) |
5255 | pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; |
5256 | else |
5257 | rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; |
5258 | } |
5259 | |
5260 | pi->vddc_phase_shed_control = true; |
5261 | |
5262 | #if defined(CONFIG_ACPI) |
5263 | pi->pcie_performance_request = |
5264 | radeon_acpi_is_pcie_performance_request_supported(rdev); |
5265 | #else |
5266 | pi->pcie_performance_request = false; |
5267 | #endif |
5268 | |
5269 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, |
5270 | &frev, &crev, &data_offset)) { |
5271 | pi->caps_sclk_ss_support = true; |
5272 | pi->caps_mclk_ss_support = true; |
5273 | pi->dynamic_ss = true; |
5274 | } else { |
5275 | pi->caps_sclk_ss_support = false; |
5276 | pi->caps_mclk_ss_support = false; |
5277 | pi->dynamic_ss = true; |
5278 | } |
5279 | |
5280 | if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) |
5281 | pi->thermal_protection = true; |
5282 | else |
5283 | pi->thermal_protection = false; |
5284 | |
5285 | pi->caps_dynamic_ac_timing = true; |
5286 | |
5287 | pi->uvd_power_gated = false; |
5288 | |
5289 | /* make sure dc limits are valid */ |
5290 | if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || |
5291 | (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) |
5292 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = |
5293 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
5294 | |
5295 | return 0; |
5296 | } |
5297 | |
5298 | #ifdef CONFIG_DEBUG_FS |
5299 | void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
5300 | struct seq_file *m) |
5301 | { |
5302 | u32 sclk = ci_get_average_sclk_freq(rdev); |
5303 | u32 mclk = ci_get_average_mclk_freq(rdev); |
5304 | |
5305 | seq_printf(m, "power level avg sclk: %u mclk: %u\n" , |
5306 | sclk, mclk); |
5307 | } |
5308 | #endif |
5309 | |
5310 | void ci_dpm_print_power_state(struct radeon_device *rdev, |
5311 | struct radeon_ps *rps) |
5312 | { |
5313 | struct ci_ps *ps = ci_get_ps(rps); |
5314 | struct ci_pl *pl; |
5315 | int i; |
5316 | |
5317 | r600_dpm_print_class_info(rps->class, rps->class2); |
5318 | r600_dpm_print_cap_info(rps->caps); |
5319 | printk("\tuvd vclk: %d dclk: %d\n" , rps->vclk, rps->dclk); |
5320 | for (i = 0; i < ps->performance_level_count; i++) { |
5321 | pl = &ps->performance_levels[i]; |
5322 | printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n" , |
5323 | i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane); |
5324 | } |
5325 | r600_dpm_print_ps_status(rdev, rps); |
5326 | } |
5327 | |
5328 | u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low) |
5329 | { |
5330 | struct ci_power_info *pi = ci_get_pi(rdev); |
5331 | struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); |
5332 | |
5333 | if (low) |
5334 | return requested_state->performance_levels[0].sclk; |
5335 | else |
5336 | return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; |
5337 | } |
5338 | |
5339 | u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low) |
5340 | { |
5341 | struct ci_power_info *pi = ci_get_pi(rdev); |
5342 | struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); |
5343 | |
5344 | if (low) |
5345 | return requested_state->performance_levels[0].mclk; |
5346 | else |
5347 | return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; |
5348 | } |
5349 | |