1 | /*- |
2 | * Copyright (c) 2016 The NetBSD Foundation, Inc. |
3 | * All rights reserved. |
4 | * |
5 | * This code is derived from software contributed to The NetBSD Foundation |
6 | * by Masanobu SAITOH. |
7 | * |
8 | * Redistribution and use in source and binary forms, with or without |
9 | * modification, are permitted provided that the following conditions |
10 | * are met: |
11 | * 1. Redistributions of source code must retain the above copyright |
12 | * notice, this list of conditions and the following disclaimer. |
13 | * 2. Redistributions in binary form must reproduce the above copyright |
14 | * notice, this list of conditions and the following disclaimer in the |
15 | * documentation and/or other materials provided with the distribution. |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
18 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
19 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
20 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
21 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
22 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
24 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
25 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
26 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
27 | * POSSIBILITY OF SUCH DAMAGE. |
28 | */ |
29 | |
30 | /*- |
31 | * Copyright (C) 2014 Intel Corporation |
32 | * All rights reserved. |
33 | * |
34 | * Redistribution and use in source and binary forms, with or without |
35 | * modification, are permitted provided that the following conditions |
36 | * are met: |
37 | * 1. Redistributions of source code must retain the above copyright |
38 | * notice, this list of conditions and the following disclaimer. |
39 | * 2. Redistributions in binary form must reproduce the above copyright |
40 | * notice, this list of conditions and the following disclaimer in the |
41 | * documentation and/or other materials provided with the distribution. |
42 | * 3. Neither the name of Intel Corporation nor the names of its |
43 | * contributors may be used to endorse or promote products derived from |
44 | * this software without specific prior written permission. |
45 | * |
46 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
47 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
48 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
49 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
50 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
51 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
52 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
53 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
54 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
55 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
56 | * SUCH DAMAGE. |
57 | */ |
58 | |
59 | #include <sys/cdefs.h> |
60 | #if 0 |
61 | __FBSDID("$FreeBSD: head/sys/dev/ismt/ismt.c 266474 2014-05-20 19:55:06Z jimharris $" ); |
62 | #endif |
63 | __KERNEL_RCSID(0, "$NetBSD: ismt.c,v 1.4 2016/07/11 06:14:51 knakahara Exp $" ); |
64 | |
65 | #include <sys/param.h> |
66 | #include <sys/systm.h> |
67 | #include <sys/device.h> |
68 | #include <sys/errno.h> |
69 | #include <sys/kernel.h> |
70 | #include <sys/module.h> |
71 | #include <sys/mutex.h> |
72 | #include <sys/proc.h> |
73 | |
74 | #include <sys/bus.h> |
75 | |
76 | #include <dev/pci/pcidevs.h> |
77 | #include <dev/pci/pcireg.h> |
78 | #include <dev/pci/pcivar.h> |
79 | |
80 | #include <dev/i2c/i2cvar.h> |
81 | |
82 | #define ISMT_DESC_ENTRIES 32 |
83 | |
84 | /* Hardware Descriptor Constants - Control Field */ |
85 | #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */ |
86 | #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */ |
87 | #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */ |
88 | #define ISMT_DESC_PEC 0x10 /* Packet Error Code */ |
89 | #define ISMT_DESC_I2C 0x20 /* I2C Enable */ |
90 | #define ISMT_DESC_INT 0x40 /* Interrupt */ |
91 | #define ISMT_DESC_SOE 0x80 /* Stop On Error */ |
92 | |
93 | /* Hardware Descriptor Constants - Status Field */ |
94 | #define ISMT_DESC_SCS 0x01 /* Success */ |
95 | #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */ |
96 | #define ISMT_DESC_NAK 0x08 /* NAK Received */ |
97 | #define ISMT_DESC_CRC 0x10 /* CRC Error */ |
98 | #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */ |
99 | #define ISMT_DESC_COL 0x40 /* Collisions */ |
100 | #define ISMT_DESC_LPR 0x80 /* Large Packet Received */ |
101 | |
102 | /* Macros */ |
103 | #define ISMT_DESC_ADDR_RW(addr, is_read) (((addr) << 1) | (is_read)) |
104 | |
105 | /* iSMT General Register address offsets (SMBBAR + <addr>) */ |
106 | #define ISMT_GR_GCTRL 0x000 /* General Control */ |
107 | #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */ |
108 | #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */ |
109 | #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */ |
110 | #define ISMT_GR_ERRSTS 0x018 /* Error Status */ |
111 | #define ISMT_GR_ERRINFO 0x01c /* Error Information */ |
112 | |
113 | /* iSMT Master Registers */ |
114 | #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */ |
115 | #define ISMT_MSTR_MCTRL 0x108 /* Master Control */ |
116 | #define ISMT_MSTR_MSTS 0x10c /* Master Status */ |
117 | #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */ |
118 | #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */ |
119 | |
120 | /* iSMT Miscellaneous Registers */ |
121 | #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */ |
122 | |
123 | /* General Control Register (GCTRL) bit definitions */ |
124 | #define ISMT_GCTRL_TRST 0x04 /* Target Reset */ |
125 | #define ISMT_GCTRL_KILL 0x08 /* Kill */ |
126 | #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */ |
127 | |
128 | /* Master Control Register (MCTRL) bit definitions */ |
129 | #define ISMT_MCTRL_SS 0x01 /* Start/Stop */ |
130 | #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */ |
131 | #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */ |
132 | |
133 | /* Master Status Register (MSTS) bit definitions */ |
134 | #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */ |
135 | #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */ |
136 | #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */ |
137 | #define ISMT_MSTS_IP 0x01 /* In Progress */ |
138 | |
139 | /* Master Descriptor Size (MDS) bit definitions */ |
140 | #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */ |
141 | |
142 | /* SMBus PHY Global Timing Register (SPGT) bit definitions */ |
143 | #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */ |
144 | #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */ |
145 | #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */ |
146 | #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */ |
147 | #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */ |
148 | |
149 | /* MSI Control Register (MSICTL) bit definitions */ |
150 | #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */ |
151 | |
152 | #define ISMT_MAX_BLOCK_SIZE 32 /* per SMBus spec */ |
153 | |
154 | #define ISMT_INTR_TIMEOUT (hz / 50) /* 0.02s */ |
155 | #define ISMT_POLL_DELAY 100 /* 100usec */ |
156 | #define ISMT_POLL_COUNT 200 /* 100usec * 200 = 0.02s */ |
157 | |
158 | //#define ISMT_DEBUG aprint_debug_dev |
159 | #ifndef ISMT_DEBUG |
160 | #define ISMT_DEBUG(...) |
161 | #endif |
162 | |
163 | #define ISMT_LOW(a) ((a) & 0xFFFFFFFFULL) |
164 | #define ISMT_HIGH(a) (((uint64_t)(a) >> 32) & 0xFFFFFFFFFULL) |
165 | |
166 | /* iSMT Hardware Descriptor */ |
167 | struct ismt_desc { |
168 | uint8_t tgtaddr_rw; /* target address & r/w bit */ |
169 | uint8_t wr_len_cmd; /* write length in bytes or a command */ |
170 | uint8_t rd_len; /* read length */ |
171 | uint8_t control; /* control bits */ |
172 | uint8_t status; /* status bits */ |
173 | uint8_t retry; /* collision retry and retry count */ |
174 | uint8_t rxbytes; /* received bytes */ |
175 | uint8_t txbytes; /* transmitted bytes */ |
176 | uint32_t dptr_low; /* lower 32 bit of the data pointer */ |
177 | uint32_t dptr_high; /* upper 32 bit of the data pointer */ |
178 | } __packed; |
179 | |
180 | #define DESC_SIZE (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)) |
181 | |
182 | #define DMA_BUFFER_SIZE 64 |
183 | |
184 | struct ismt_softc { |
185 | device_t pcidev; |
186 | device_t smbdev; |
187 | |
188 | struct i2c_controller sc_i2c_tag; |
189 | kmutex_t sc_i2c_mutex; |
190 | |
191 | pci_chipset_tag_t sc_pc; |
192 | pcitag_t sc_pcitag; |
193 | pci_intr_handle_t *sc_pihp; |
194 | void *sc_ih; |
195 | |
196 | bus_space_tag_t mmio_tag; |
197 | bus_space_handle_t mmio_handle; |
198 | bus_size_t mmio_size; |
199 | |
200 | uint8_t head; |
201 | |
202 | struct ismt_desc *desc; |
203 | bus_dma_tag_t desc_dma_tag; |
204 | bus_dmamap_t desc_dma_map; |
205 | bus_dma_segment_t desc_dma_seg; |
206 | int desc_rseg; |
207 | |
208 | uint8_t *dma_buffer; |
209 | bus_dma_tag_t dma_buffer_dma_tag; |
210 | bus_dmamap_t dma_buffer_dma_map; |
211 | bus_dma_segment_t dma_buffer_dma_seg; |
212 | int dma_buffer_rseg; |
213 | |
214 | uint8_t using_msi; |
215 | }; |
216 | |
217 | static int ismt_intr(void *); |
218 | static int ismt_i2c_acquire_bus(void *, int); |
219 | static void ismt_i2c_release_bus(void *, int); |
220 | static int ismt_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, |
221 | size_t, void *, size_t, int); |
222 | static struct ismt_desc *ismt_alloc_desc(struct ismt_softc *); |
223 | static int ismt_submit(struct ismt_softc *, struct ismt_desc *, |
224 | i2c_addr_t, uint8_t, int); |
225 | static int ismt_quick(struct ismt_softc *, i2c_addr_t, i2c_op_t, int); |
226 | static int ismt_sendb(struct ismt_softc *, i2c_addr_t, i2c_op_t, char, |
227 | int); |
228 | static int ismt_recvb(struct ismt_softc *, i2c_addr_t, i2c_op_t, int); |
229 | static int ismt_writeb(struct ismt_softc *, i2c_addr_t, i2c_op_t, uint8_t, |
230 | char, int); |
231 | static int ismt_writew(struct ismt_softc *, i2c_addr_t, i2c_op_t, uint8_t, |
232 | uint16_t, int); |
233 | static int ismt_readb(struct ismt_softc *, i2c_addr_t, i2c_op_t, char, |
234 | int); |
235 | static int ismt_readw(struct ismt_softc *, i2c_addr_t, i2c_op_t, char, |
236 | int); |
237 | |
238 | static int ismt_match(device_t, cfdata_t, void *); |
239 | static void ismt_attach(device_t, device_t, void *); |
240 | static int ismt_detach(device_t, int); |
241 | static int ismt_rescan(device_t, const char *, const int *); |
242 | static void ismt_config_interrupts(device_t); |
243 | static void ismt_chdet(device_t, device_t); |
244 | |
245 | CFATTACH_DECL3_NEW(ismt, sizeof(struct ismt_softc), |
246 | ismt_match, ismt_attach, ismt_detach, NULL, ismt_rescan, ismt_chdet, |
247 | DVF_DETACH_SHUTDOWN); |
248 | |
249 | static int |
250 | ismt_intr(void *arg) |
251 | { |
252 | struct ismt_softc *sc = arg; |
253 | uint32_t val; |
254 | |
255 | val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MSTS); |
256 | if ((sc->using_msi == 0) |
257 | && (val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)) == 0) |
258 | return 0; /* Not for me */ |
259 | |
260 | ISMT_DEBUG(sc->pcidev, "%s MSTS = 0x%08x\n" , __func__, val); |
261 | |
262 | val |= (ISMT_MSTS_MIS | ISMT_MSTS_MEIS); |
263 | bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MSTS, val); |
264 | |
265 | if (sc->using_msi) |
266 | wakeup(sc); |
267 | |
268 | return 1; |
269 | } |
270 | |
271 | static int |
272 | ismt_i2c_acquire_bus(void *cookie, int flags) |
273 | { |
274 | struct ismt_softc *sc = cookie; |
275 | |
276 | mutex_enter(&sc->sc_i2c_mutex); |
277 | return 0; |
278 | } |
279 | |
280 | static void |
281 | ismt_i2c_release_bus(void *cookie, int flags) |
282 | { |
283 | struct ismt_softc *sc = cookie; |
284 | |
285 | mutex_exit(&sc->sc_i2c_mutex); |
286 | } |
287 | |
288 | static int |
289 | ismt_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, |
290 | const void *cmd, size_t cmdlen, void *buf, size_t buflen, int flags) |
291 | { |
292 | struct ismt_softc *sc = cookie; |
293 | uint8_t *p = buf; |
294 | int rv; |
295 | |
296 | ISMT_DEBUG(sc->pcidev, "exec: op %d, addr 0x%02x, cmdlen %zu, " |
297 | " buflen %zu, flags 0x%02x\n" , op, addr, cmdlen, buflen, flags); |
298 | |
299 | if ((cmdlen == 0) && (buflen == 0)) |
300 | return ismt_quick(sc, addr, op, flags); |
301 | |
302 | if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { |
303 | rv = ismt_recvb(sc, addr, op, flags); |
304 | if (rv == -1) |
305 | return -1; |
306 | *p = (uint8_t)rv; |
307 | return 0; |
308 | } |
309 | |
310 | if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { |
311 | rv = ismt_readb(sc, addr, op, *(const uint8_t*)cmd, flags); |
312 | if (rv == -1) |
313 | return -1; |
314 | *p = (uint8_t)rv; |
315 | return 0; |
316 | } |
317 | |
318 | if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 2)) { |
319 | rv = ismt_readw(sc, addr, op, *(const uint8_t*)cmd, flags); |
320 | if (rv == -1) |
321 | return -1; |
322 | *(uint16_t *)p = (uint16_t)rv; |
323 | return 0; |
324 | } |
325 | |
326 | if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) |
327 | return ismt_sendb(sc, addr, op, *(uint8_t*)buf, flags); |
328 | |
329 | if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) |
330 | return ismt_writeb(sc, addr, op, *(const uint8_t*)cmd, |
331 | *(uint8_t*)buf, flags); |
332 | |
333 | if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 2)) |
334 | return ismt_writew(sc, addr, op, |
335 | *(const uint8_t*)cmd, *((uint16_t *)buf), flags); |
336 | |
337 | return -1; |
338 | } |
339 | |
340 | static struct ismt_desc * |
341 | ismt_alloc_desc(struct ismt_softc *sc) |
342 | { |
343 | struct ismt_desc *desc; |
344 | |
345 | KASSERT(mutex_owned(&sc->sc_i2c_mutex)); |
346 | |
347 | desc = &sc->desc[sc->head++]; |
348 | if (sc->head == ISMT_DESC_ENTRIES) |
349 | sc->head = 0; |
350 | |
351 | memset(desc, 0, sizeof(*desc)); |
352 | |
353 | return (desc); |
354 | } |
355 | |
356 | static int |
357 | ismt_submit(struct ismt_softc *sc, struct ismt_desc *desc, i2c_addr_t slave, |
358 | uint8_t is_read, int flags) |
359 | { |
360 | uint32_t err, fmhp, val; |
361 | int timeout, i; |
362 | |
363 | if (sc->using_msi == 0) |
364 | flags |= I2C_F_POLL; |
365 | desc->control |= ISMT_DESC_FAIR; |
366 | if ((flags & I2C_F_POLL) == 0) |
367 | desc->control |= ISMT_DESC_INT; |
368 | |
369 | desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(slave, is_read); |
370 | desc->dptr_low = ISMT_LOW(sc->dma_buffer_dma_map->dm_segs[0].ds_addr); |
371 | desc->dptr_high = ISMT_HIGH(sc->dma_buffer_dma_map->dm_segs[0].ds_addr); |
372 | |
373 | bus_dmamap_sync(sc->desc_dma_tag, sc->desc_dma_map, |
374 | desc - &sc->desc[0], sizeof(struct ismt_desc), |
375 | BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); |
376 | |
377 | fmhp = sc->head << 16; |
378 | val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL); |
379 | val &= ~ISMT_MCTRL_FMHP; |
380 | val |= fmhp; |
381 | bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL, val); |
382 | |
383 | /* set the start bit */ |
384 | val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL); |
385 | val |= ISMT_MCTRL_SS; |
386 | bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL, val); |
387 | |
388 | i = 0; |
389 | if ((flags & I2C_F_POLL) == 0) { |
390 | timeout = ISMT_INTR_TIMEOUT; |
391 | if (timeout == 0) |
392 | timeout = 1; |
393 | err = tsleep(sc, PWAIT, "ismt_wait" , timeout); |
394 | if (err != 0) { |
395 | ISMT_DEBUG(sc->pcidev, "%s timeout\n" , __func__); |
396 | return -1; |
397 | } |
398 | } else { |
399 | /* Polling */ |
400 | for (i = 0; i < ISMT_POLL_COUNT; i++) { |
401 | val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, |
402 | ISMT_MSTR_MSTS); |
403 | if ((val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)) != 0) { |
404 | ismt_intr(sc); |
405 | err = 0; |
406 | break; |
407 | } |
408 | delay(ISMT_POLL_DELAY); |
409 | } |
410 | if (i >= ISMT_POLL_COUNT) { |
411 | ISMT_DEBUG(sc->pcidev, "%s polling timeout. " |
412 | "MSTS = %08x\n" , __func__, val); |
413 | return -1; |
414 | } |
415 | } |
416 | |
417 | bus_dmamap_sync(sc->desc_dma_tag, sc->desc_dma_map, |
418 | desc - &sc->desc[0], sizeof(struct ismt_desc), |
419 | BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); |
420 | ISMT_DEBUG(sc->pcidev, "%s status=0x%02x\n" , __func__, desc->status); |
421 | |
422 | if (desc->status & ISMT_DESC_SCS) |
423 | return 0; |
424 | |
425 | if (desc->status & ISMT_DESC_NAK) |
426 | return -1; |
427 | |
428 | if (desc->status & ISMT_DESC_CRC) |
429 | return -1; |
430 | |
431 | if (desc->status & ISMT_DESC_COL) |
432 | return -1; |
433 | |
434 | if (desc->status & ISMT_DESC_LPR) |
435 | return -1; |
436 | |
437 | if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO)) |
438 | return -1; |
439 | |
440 | return -1; |
441 | } |
442 | |
443 | static int |
444 | ismt_quick(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, int flags) |
445 | { |
446 | struct ismt_desc *desc; |
447 | int is_read; |
448 | |
449 | ISMT_DEBUG(sc->pcidev, "%s\n" , __func__); |
450 | |
451 | desc = ismt_alloc_desc(sc); |
452 | is_read = I2C_OP_READ_P(op); |
453 | return (ismt_submit(sc, desc, slave, is_read, flags)); |
454 | } |
455 | |
456 | static int |
457 | ismt_sendb(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char byte, |
458 | int flags) |
459 | { |
460 | struct ismt_desc *desc; |
461 | |
462 | ISMT_DEBUG(sc->pcidev, "%s\n" , __func__); |
463 | |
464 | desc = ismt_alloc_desc(sc); |
465 | desc->control = ISMT_DESC_CWRL; |
466 | desc->wr_len_cmd = byte; |
467 | |
468 | return (ismt_submit(sc, desc, slave, 0, flags)); |
469 | } |
470 | |
471 | static int |
472 | ismt_recvb(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, int flags) |
473 | { |
474 | struct ismt_desc *desc; |
475 | int err; |
476 | |
477 | ISMT_DEBUG(sc->pcidev, "%s\n" , __func__); |
478 | |
479 | desc = ismt_alloc_desc(sc); |
480 | desc->rd_len = 1; |
481 | |
482 | err = ismt_submit(sc, desc, slave, 1, flags); |
483 | |
484 | if (err != 0) |
485 | return (err); |
486 | |
487 | return sc->dma_buffer[0]; |
488 | } |
489 | |
490 | static int |
491 | ismt_writeb(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, uint8_t cmd, |
492 | char byte, int flags) |
493 | { |
494 | struct ismt_desc *desc; |
495 | |
496 | ISMT_DEBUG(sc->pcidev, "%s\n" , __func__); |
497 | |
498 | desc = ismt_alloc_desc(sc); |
499 | desc->wr_len_cmd = 2; |
500 | sc->dma_buffer[0] = cmd; |
501 | sc->dma_buffer[1] = byte; |
502 | |
503 | return (ismt_submit(sc, desc, slave, 0, flags)); |
504 | } |
505 | |
506 | static int |
507 | ismt_writew(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, uint8_t cmd, |
508 | uint16_t word, int flags) |
509 | { |
510 | struct ismt_desc *desc; |
511 | |
512 | ISMT_DEBUG(sc->pcidev, "%s\n" , __func__); |
513 | |
514 | desc = ismt_alloc_desc(sc); |
515 | desc->wr_len_cmd = 3; |
516 | sc->dma_buffer[0] = cmd; |
517 | sc->dma_buffer[1] = word & 0xFF; |
518 | sc->dma_buffer[2] = word >> 8; |
519 | |
520 | return (ismt_submit(sc, desc, slave, 0, flags)); |
521 | } |
522 | |
523 | static int |
524 | ismt_readb(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, |
525 | int flags) |
526 | { |
527 | struct ismt_desc *desc; |
528 | int err; |
529 | |
530 | ISMT_DEBUG(sc->pcidev, "%s\n" , __func__); |
531 | |
532 | desc = ismt_alloc_desc(sc); |
533 | desc->control = ISMT_DESC_CWRL; |
534 | desc->wr_len_cmd = cmd; |
535 | desc->rd_len = 1; |
536 | |
537 | err = ismt_submit(sc, desc, slave, 1, flags); |
538 | |
539 | if (err != 0) |
540 | return (err); |
541 | |
542 | return sc->dma_buffer[0]; |
543 | } |
544 | |
545 | static int |
546 | ismt_readw(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, |
547 | int flags) |
548 | { |
549 | struct ismt_desc *desc; |
550 | uint16_t word; |
551 | int err; |
552 | |
553 | ISMT_DEBUG(sc->pcidev, "%s\n" , __func__); |
554 | |
555 | desc = ismt_alloc_desc(sc); |
556 | desc->control = ISMT_DESC_CWRL; |
557 | desc->wr_len_cmd = cmd; |
558 | desc->rd_len = 2; |
559 | |
560 | err = ismt_submit(sc, desc, slave, 1, flags); |
561 | |
562 | if (err != 0) |
563 | return (err); |
564 | |
565 | word = sc->dma_buffer[0] | (sc->dma_buffer[1] << 8); |
566 | |
567 | return word; |
568 | } |
569 | |
570 | #if 0 |
571 | static int |
572 | ismt_pcall(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, |
573 | uint16_t sdata, uint16_t *rdata, int flags) |
574 | { |
575 | struct ismt_desc *desc; |
576 | int err; |
577 | |
578 | ISMT_DEBUG(sc->pcidev, "%s\n" , __func__); |
579 | |
580 | desc = ismt_alloc_desc(sc); |
581 | desc->wr_len_cmd = 3; |
582 | desc->rd_len = 2; |
583 | sc->dma_buffer[0] = cmd; |
584 | sc->dma_buffer[1] = sdata & 0xff; |
585 | sc->dma_buffer[2] = sdata >> 8; |
586 | |
587 | err = ismt_submit(sc, desc, slave, 0, flags); |
588 | |
589 | if (err != 0) |
590 | return (err); |
591 | |
592 | *rdata = sc->dma_buffer[0] | (sc->dma_buffer[1] << 8); |
593 | |
594 | return (err); |
595 | } |
596 | |
597 | static int |
598 | ismt_bwrite(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, |
599 | u_char count, char *buf, int flags) |
600 | { |
601 | struct ismt_desc *desc; |
602 | |
603 | ISMT_DEBUG(sc->pcidev, "%s\n" , __func__); |
604 | |
605 | if (count == 0 || count > ISMT_MAX_BLOCK_SIZE) |
606 | return -1; |
607 | |
608 | desc = ismt_alloc_desc(sc); |
609 | desc->control = ISMT_DESC_I2C; |
610 | desc->wr_len_cmd = count + 1; |
611 | sc->dma_buffer[0] = cmd; |
612 | memcpy(&sc->dma_buffer[1], buf, count); |
613 | |
614 | return (ismt_submit(sc, desc, slave, 0, flags)); |
615 | } |
616 | |
617 | static int |
618 | ismt_bread(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, |
619 | u_char *count, char *buf, int flags) |
620 | { |
621 | struct ismt_desc *desc; |
622 | int err; |
623 | |
624 | ISMT_DEBUG(sc->pcidev, "%s\n" , __func__); |
625 | |
626 | if (*count == 0 || *count > ISMT_MAX_BLOCK_SIZE) |
627 | return -1; |
628 | |
629 | desc = ismt_alloc_desc(sc); |
630 | desc->control = ISMT_DESC_I2C | ISMT_DESC_CWRL; |
631 | desc->wr_len_cmd = cmd; |
632 | desc->rd_len = *count; |
633 | |
634 | err = ismt_submit(sc, desc, slave, 0, flags); |
635 | |
636 | if (err != 0) |
637 | return (err); |
638 | |
639 | memcpy(buf, sc->dma_buffer, desc->rxbytes); |
640 | *count = desc->rxbytes; |
641 | |
642 | return (err); |
643 | } |
644 | #endif |
645 | |
646 | static int |
647 | ismt_detach(device_t self, int flags) |
648 | { |
649 | struct ismt_softc *sc; |
650 | int rv = 0; |
651 | |
652 | ISMT_DEBUG(self, "%s\n" , __func__); |
653 | sc = device_private(self); |
654 | if (sc->smbdev != NULL) { |
655 | rv = config_detach(sc->smbdev, flags); |
656 | if (rv != 0) |
657 | return rv; |
658 | } |
659 | if (sc->sc_ih != NULL) { |
660 | pci_intr_disestablish(sc->sc_pc, sc->sc_ih); |
661 | sc->sc_ih = NULL; |
662 | } |
663 | if (sc->sc_pihp != NULL) { |
664 | pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); |
665 | sc->sc_pihp = NULL; |
666 | } |
667 | |
668 | bus_dmamap_unload(sc->desc_dma_tag, sc->desc_dma_map); |
669 | bus_dmamap_unload(sc->dma_buffer_dma_tag, sc->dma_buffer_dma_map); |
670 | |
671 | bus_dmamem_free(sc->desc_dma_tag, &sc->desc_dma_seg, sc->desc_rseg); |
672 | bus_dmamem_free(sc->dma_buffer_dma_tag, &sc->dma_buffer_dma_seg, |
673 | sc->dma_buffer_rseg); |
674 | |
675 | if (sc->mmio_size) |
676 | bus_space_unmap(sc->mmio_tag, sc->mmio_handle, sc->mmio_size); |
677 | |
678 | mutex_destroy(&sc->sc_i2c_mutex); |
679 | return rv; |
680 | } |
681 | |
682 | static void |
683 | ismt_attach(device_t parent, device_t self, void *aux) |
684 | { |
685 | struct ismt_softc *sc = device_private(self); |
686 | struct pci_attach_args *pa = aux; |
687 | const char *intrstr = NULL; |
688 | char intrbuf[PCI_INTRSTR_LEN]; |
689 | pcireg_t reg; |
690 | int val; |
691 | |
692 | sc->pcidev = self; |
693 | sc->sc_pc = pa->pa_pc; |
694 | sc->sc_pcitag = pa->pa_tag; |
695 | |
696 | /* Enable busmastering */ |
697 | reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); |
698 | reg |= PCI_COMMAND_MASTER_ENABLE; |
699 | pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); |
700 | |
701 | pci_aprint_devinfo(pa, NULL); |
702 | |
703 | /* Map mem space */ |
704 | if (pci_mapreg_map(pa, PCI_BAR0, PCI_MAPREG_TYPE_MEM, 0, |
705 | &sc->mmio_tag, &sc->mmio_handle, NULL, &sc->mmio_size)) { |
706 | aprint_error_dev(self, "can't map mem space\n" ); |
707 | goto fail; |
708 | } |
709 | |
710 | if (pci_dma64_available(pa)) { |
711 | sc->desc_dma_tag = pa->pa_dmat64; |
712 | sc->dma_buffer_dma_tag = pa->pa_dmat64; |
713 | } else { |
714 | sc->desc_dma_tag = pa->pa_dmat; |
715 | sc->dma_buffer_dma_tag = pa->pa_dmat; |
716 | } |
717 | bus_dmamem_alloc(sc->desc_dma_tag, DESC_SIZE, PAGE_SIZE, 0, |
718 | &sc->desc_dma_seg, ISMT_DESC_ENTRIES, &sc->desc_rseg, |
719 | BUS_DMA_WAITOK); |
720 | bus_dmamem_alloc(sc->dma_buffer_dma_tag, DMA_BUFFER_SIZE, PAGE_SIZE, 0, |
721 | &sc->dma_buffer_dma_seg, 1, &sc->dma_buffer_rseg, BUS_DMA_WAITOK); |
722 | |
723 | bus_dmamem_map(sc->desc_dma_tag, &sc->desc_dma_seg, |
724 | sc->desc_rseg, DESC_SIZE, (void **)&sc->desc, BUS_DMA_COHERENT); |
725 | bus_dmamem_map(sc->dma_buffer_dma_tag, &sc->dma_buffer_dma_seg, |
726 | sc->dma_buffer_rseg, DMA_BUFFER_SIZE, (void **)&sc->dma_buffer, |
727 | BUS_DMA_COHERENT); |
728 | |
729 | bus_dmamap_create(sc->desc_dma_tag, DESC_SIZE, 1, |
730 | DESC_SIZE, 0, 0, &sc->desc_dma_map); |
731 | bus_dmamap_create(sc->dma_buffer_dma_tag, DMA_BUFFER_SIZE, 1, |
732 | DMA_BUFFER_SIZE, 0, 0, &sc->dma_buffer_dma_map); |
733 | |
734 | bus_dmamap_load(sc->desc_dma_tag, |
735 | sc->desc_dma_map, sc->desc, DESC_SIZE, NULL, 0); |
736 | bus_dmamap_load(sc->dma_buffer_dma_tag, |
737 | sc->dma_buffer_dma_map, sc->dma_buffer, DMA_BUFFER_SIZE, |
738 | NULL, 0); |
739 | |
740 | bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MDBA, |
741 | ISMT_LOW(sc->desc_dma_map->dm_segs[0].ds_addr)); |
742 | bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MDBA + 4, |
743 | ISMT_HIGH(sc->desc_dma_map->dm_segs[0].ds_addr)); |
744 | |
745 | /* initialize the Master Control Register (MCTRL) */ |
746 | bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL, |
747 | ISMT_MCTRL_MEIE); |
748 | |
749 | /* initialize the Master Status Register (MSTS) */ |
750 | bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MSTS, 0); |
751 | |
752 | /* initialize the Master Descriptor Size (MDS) */ |
753 | val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MDS); |
754 | val &= ~ISMT_MDS_MASK; |
755 | val |= (ISMT_DESC_ENTRIES - 1); |
756 | bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MDS, val); |
757 | |
758 | if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { |
759 | aprint_error_dev(self, "couldn't map interrupt\n" ); |
760 | return; |
761 | } |
762 | intrstr = pci_intr_string(pa->pa_pc, sc->sc_pihp[0], intrbuf, |
763 | sizeof(intrbuf)); |
764 | sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->sc_pihp[0], IPL_BIO, |
765 | ismt_intr, sc); |
766 | if (sc->sc_ih == NULL) { |
767 | aprint_error_dev(sc->pcidev, "unable to establish %s\n" , |
768 | (pci_intr_type(pa->pa_pc, sc->sc_pihp[0]) |
769 | == PCI_INTR_TYPE_MSI) ? "MSI" : "INTx" ); |
770 | /* Polling */ |
771 | } |
772 | |
773 | if (pci_intr_type(pa->pa_pc, sc->sc_pihp[0]) == PCI_INTR_TYPE_MSI) |
774 | sc->using_msi = 1; |
775 | |
776 | aprint_normal_dev(sc->pcidev, "interrupting at %s\n" , intrstr); |
777 | |
778 | sc->smbdev = NULL; |
779 | mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); |
780 | if (!pmf_device_register(self, NULL, NULL)) |
781 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
782 | |
783 | config_interrupts(self, ismt_config_interrupts); |
784 | return; |
785 | |
786 | fail: |
787 | ismt_detach(sc->pcidev, 0); |
788 | |
789 | return; |
790 | } |
791 | |
792 | static int |
793 | ismt_match(device_t parent, cfdata_t match, void *aux) |
794 | { |
795 | struct pci_attach_args *pa = aux; |
796 | |
797 | if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) |
798 | return 0; |
799 | |
800 | switch (PCI_PRODUCT(pa->pa_id)) { |
801 | case PCI_PRODUCT_INTEL_S1200_SMBUS_0: |
802 | case PCI_PRODUCT_INTEL_S1200_SMBUS_1: |
803 | case PCI_PRODUCT_INTEL_C2000_SMBUS: |
804 | break; |
805 | default: |
806 | return 0; |
807 | } |
808 | |
809 | return 1; |
810 | } |
811 | |
812 | static int |
813 | ismt_rescan(device_t self, const char *ifattr, const int *flags) |
814 | { |
815 | struct ismt_softc *sc = device_private(self); |
816 | struct i2cbus_attach_args iba; |
817 | |
818 | if (!ifattr_match(ifattr, "i2cbus" )) |
819 | return 0; |
820 | |
821 | if (sc->smbdev) |
822 | return 0; |
823 | |
824 | /* Attach I2C bus */ |
825 | sc->sc_i2c_tag.ic_cookie = sc; |
826 | sc->sc_i2c_tag.ic_acquire_bus = ismt_i2c_acquire_bus; |
827 | sc->sc_i2c_tag.ic_release_bus = ismt_i2c_release_bus; |
828 | sc->sc_i2c_tag.ic_exec = ismt_i2c_exec; |
829 | |
830 | memset(&iba, 0, sizeof(iba)); |
831 | iba.iba_type = I2C_TYPE_SMBUS; |
832 | iba.iba_tag = &sc->sc_i2c_tag; |
833 | sc->smbdev = config_found_ia(self, ifattr, &iba, iicbus_print); |
834 | |
835 | return 0; |
836 | } |
837 | |
838 | static void |
839 | ismt_config_interrupts(device_t self) |
840 | { |
841 | int flags = 0; |
842 | |
843 | ismt_rescan(self, "i2cbus" , &flags); |
844 | } |
845 | |
846 | static void |
847 | ismt_chdet(device_t self, device_t child) |
848 | { |
849 | struct ismt_softc *sc = device_private(self); |
850 | |
851 | if (sc->smbdev == child) |
852 | sc->smbdev = NULL; |
853 | |
854 | } |
855 | |
856 | MODULE(MODULE_CLASS_DRIVER, ismt, "pci" ); |
857 | |
858 | #ifdef _MODULE |
859 | #include "ioconf.c" |
860 | #endif |
861 | |
862 | static int |
863 | ismt_modcmd(modcmd_t cmd, void *opaque) |
864 | { |
865 | int error = 0; |
866 | |
867 | switch (cmd) { |
868 | case MODULE_CMD_INIT: |
869 | #ifdef _MODULE |
870 | error = config_init_component(cfdriver_ioconf_ismt, |
871 | cfattach_ioconf_ismt, cfdata_ioconf_ismt); |
872 | #endif |
873 | return error; |
874 | case MODULE_CMD_FINI: |
875 | #ifdef _MODULE |
876 | error = config_fini_component(cfdriver_ioconf_ismt, |
877 | cfattach_ioconf_ismt, cfdata_ioconf_ismt); |
878 | #endif |
879 | return error; |
880 | default: |
881 | return ENOTTY; |
882 | } |
883 | } |
884 | |