1 | #ifndef __NV04_FIFO_H__ |
2 | #define __NV04_FIFO_H__ |
3 | |
4 | #include <engine/fifo.h> |
5 | |
6 | #define NV04_PFIFO_DELAY_0 0x00002040 |
7 | #define NV04_PFIFO_DMA_TIMESLICE 0x00002044 |
8 | #define NV04_PFIFO_NEXT_CHANNEL 0x00002050 |
9 | #define NV03_PFIFO_INTR_0 0x00002100 |
10 | #define NV03_PFIFO_INTR_EN_0 0x00002140 |
11 | # define NV_PFIFO_INTR_CACHE_ERROR (1<<0) |
12 | # define NV_PFIFO_INTR_RUNOUT (1<<4) |
13 | # define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<<8) |
14 | # define NV_PFIFO_INTR_DMA_PUSHER (1<<12) |
15 | # define NV_PFIFO_INTR_DMA_PT (1<<16) |
16 | # define NV_PFIFO_INTR_SEMAPHORE (1<<20) |
17 | # define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24) |
18 | #define NV03_PFIFO_RAMHT 0x00002210 |
19 | #define NV03_PFIFO_RAMFC 0x00002214 |
20 | #define NV03_PFIFO_RAMRO 0x00002218 |
21 | #define NV40_PFIFO_RAMFC 0x00002220 |
22 | #define NV03_PFIFO_CACHES 0x00002500 |
23 | #define NV04_PFIFO_MODE 0x00002504 |
24 | #define NV04_PFIFO_DMA 0x00002508 |
25 | #define NV04_PFIFO_SIZE 0x0000250c |
26 | #define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4) |
27 | #define NV50_PFIFO_CTX_TABLE__SIZE 128 |
28 | #define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED (1<<31) |
29 | #define NV50_PFIFO_CTX_TABLE_UNK30_BAD (1<<30) |
30 | #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF |
31 | #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF |
32 | #define NV03_PFIFO_CACHE0_PUSH0 0x00003000 |
33 | #define NV03_PFIFO_CACHE0_PULL0 0x00003040 |
34 | #define NV04_PFIFO_CACHE0_PULL0 0x00003050 |
35 | #define NV04_PFIFO_CACHE0_PULL1 0x00003054 |
36 | #define NV03_PFIFO_CACHE1_PUSH0 0x00003200 |
37 | #define NV03_PFIFO_CACHE1_PUSH1 0x00003204 |
38 | #define NV03_PFIFO_CACHE1_PUSH1_DMA (1<<8) |
39 | #define NV40_PFIFO_CACHE1_PUSH1_DMA (1<<16) |
40 | #define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f |
41 | #define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f |
42 | #define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f |
43 | #define NV03_PFIFO_CACHE1_PUT 0x00003210 |
44 | #define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220 |
45 | #define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224 |
46 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 |
47 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008 |
48 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010 |
49 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018 |
50 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020 |
51 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028 |
52 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030 |
53 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038 |
54 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040 |
55 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048 |
56 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050 |
57 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058 |
58 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060 |
59 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068 |
60 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070 |
61 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078 |
62 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080 |
63 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088 |
64 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090 |
65 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098 |
66 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0 |
67 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8 |
68 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0 |
69 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8 |
70 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0 |
71 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8 |
72 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0 |
73 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8 |
74 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0 |
75 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8 |
76 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0 |
77 | # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8 |
78 | # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000 |
79 | # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 |
80 | # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000 |
81 | # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000 |
82 | # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000 |
83 | # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000 |
84 | # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000 |
85 | # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000 |
86 | # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000 |
87 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000 |
88 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 |
89 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000 |
90 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000 |
91 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000 |
92 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000 |
93 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000 |
94 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000 |
95 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000 |
96 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000 |
97 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000 |
98 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000 |
99 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000 |
100 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000 |
101 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000 |
102 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000 |
103 | # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000 |
104 | # define NV_PFIFO_CACHE1_ENDIAN 0x80000000 |
105 | # define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF |
106 | # define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000 |
107 | #define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228 |
108 | #define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c |
109 | #define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230 |
110 | #define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240 |
111 | #define NV04_PFIFO_CACHE1_DMA_GET 0x00003244 |
112 | #define NV10_PFIFO_CACHE1_REF_CNT 0x00003248 |
113 | #define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C |
114 | #define NV03_PFIFO_CACHE1_PULL0 0x00003240 |
115 | #define NV04_PFIFO_CACHE1_PULL0 0x00003250 |
116 | # define NV04_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000010 |
117 | # define NV04_PFIFO_CACHE1_PULL0_HASH_BUSY 0x00001000 |
118 | #define NV03_PFIFO_CACHE1_PULL1 0x00003250 |
119 | #define NV04_PFIFO_CACHE1_PULL1 0x00003254 |
120 | #define NV04_PFIFO_CACHE1_HASH 0x00003258 |
121 | #define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260 |
122 | #define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264 |
123 | #define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268 |
124 | #define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C |
125 | #define NV03_PFIFO_CACHE1_GET 0x00003270 |
126 | #define NV04_PFIFO_CACHE1_ENGINE 0x00003280 |
127 | #define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0 |
128 | #define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0 |
129 | #define NV40_PFIFO_UNK32E4 0x000032E4 |
130 | #define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8)) |
131 | #define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8)) |
132 | #define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8)) |
133 | #define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8)) |
134 | |
135 | struct ramfc_desc { |
136 | unsigned bits:6; |
137 | unsigned ctxs:5; |
138 | unsigned ctxp:8; |
139 | unsigned regs:5; |
140 | unsigned regp; |
141 | }; |
142 | |
143 | struct nv04_fifo_priv { |
144 | struct nouveau_fifo base; |
145 | struct ramfc_desc *ramfc_desc; |
146 | struct nouveau_ramht *ramht; |
147 | struct nouveau_gpuobj *ramro; |
148 | struct nouveau_gpuobj *ramfc; |
149 | }; |
150 | |
151 | struct nv04_fifo_base { |
152 | struct nouveau_fifo_base base; |
153 | }; |
154 | |
155 | struct nv04_fifo_chan { |
156 | struct nouveau_fifo_chan base; |
157 | u32 subc[8]; |
158 | u32 ramfc; |
159 | }; |
160 | |
161 | int nv04_fifo_object_attach(struct nouveau_object *, |
162 | struct nouveau_object *, u32); |
163 | void nv04_fifo_object_detach(struct nouveau_object *, int); |
164 | |
165 | void nv04_fifo_chan_dtor(struct nouveau_object *); |
166 | int nv04_fifo_chan_init(struct nouveau_object *); |
167 | int nv04_fifo_chan_fini(struct nouveau_object *, bool suspend); |
168 | |
169 | int nv04_fifo_context_ctor(struct nouveau_object *, struct nouveau_object *, |
170 | struct nouveau_oclass *, void *, u32, |
171 | struct nouveau_object **); |
172 | |
173 | void nv04_fifo_dtor(struct nouveau_object *); |
174 | int nv04_fifo_init(struct nouveau_object *); |
175 | void nv04_fifo_pause(struct nouveau_fifo *, unsigned long *); |
176 | void nv04_fifo_start(struct nouveau_fifo *, unsigned long *); |
177 | |
178 | #endif |
179 | |