1 | /* $NetBSD: ikphyreg.h,v 1.3 2016/10/28 05:50:18 msaitoh Exp $ */ |
2 | /******************************************************************************* |
3 | Copyright (c) 2001-2005, Intel Corporation |
4 | All rights reserved. |
5 | |
6 | Redistribution and use in source and binary forms, with or without |
7 | modification, are permitted provided that the following conditions are met: |
8 | |
9 | 1. Redistributions of source code must retain the above copyright notice, |
10 | this list of conditions and the following disclaimer. |
11 | |
12 | 2. Redistributions in binary form must reproduce the above copyright |
13 | notice, this list of conditions and the following disclaimer in the |
14 | documentation and/or other materials provided with the distribution. |
15 | |
16 | 3. Neither the name of the Intel Corporation nor the names of its |
17 | contributors may be used to endorse or promote products derived from |
18 | this software without specific prior written permission. |
19 | |
20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
23 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
24 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
25 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
26 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
27 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
28 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
29 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
30 | POSSIBILITY OF SUCH DAMAGE. |
31 | *******************************************************************************/ |
32 | |
33 | /* |
34 | * Copied from the Intel code, and then modified to match NetBSD |
35 | * style for MII registers more. |
36 | */ |
37 | |
38 | /* Bits... |
39 | * 15-5: page |
40 | * 4-0: register offset |
41 | */ |
42 | #define GG82563_PAGE_SHIFT 5 |
43 | #define GG82563_REG(page, reg) \ |
44 | (((page) << GG82563_PAGE_SHIFT) | ((reg) & MII_ADDRMASK)) |
45 | #define GG82563_MIN_ALT_REG 30 |
46 | |
47 | #define GG82563_MAX_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ |
48 | |
49 | |
50 | /* GG82563 Specific Registers */ |
51 | #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Specific Control */ |
52 | #define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */ |
53 | #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */ |
54 | #define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */ |
55 | #define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */ |
56 | #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 |
57 | #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */ |
58 | #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */ |
59 | #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */ |
60 | #define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */ |
61 | #define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300 |
62 | #define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */ |
63 | #define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */ |
64 | #define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */ |
65 | #define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */ |
66 | #define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */ |
67 | #define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000 |
68 | #define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12 |
69 | |
70 | #define GG82563_PHY_SPEC_STATUS GG82563_REG(0, 17) /* PHY Specific Status */ |
71 | #define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */ |
72 | #define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */ |
73 | #define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */ |
74 | #define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */ |
75 | #define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */ |
76 | #define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */ |
77 | #define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */ |
78 | #define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */ |
79 | #define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */ |
80 | #define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */ |
81 | #define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */ |
82 | #define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */ |
83 | #define GG82563_PSSR_SPEED_MASK 0xC000 |
84 | #define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */ |
85 | #define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */ |
86 | #define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */ |
87 | |
88 | #define GG82563_PHY_INT_ENABLE \ |
89 | GG82563_REG(0, 18) /* Interrupt Enable */ |
90 | |
91 | #define GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) /* PHY Specific Status 2 */ |
92 | #define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */ |
93 | #define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */ |
94 | #define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */ |
95 | #define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */ |
96 | #define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */ |
97 | #define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */ |
98 | #define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */ |
99 | #define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */ |
100 | #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */ |
101 | #define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */ |
102 | #define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */ |
103 | #define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */ |
104 | #define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */ |
105 | |
106 | #define GG82563_PHY_RX_ERR_CNTR GG82563_REG(0, 21) /* Receive Error Counter */ |
107 | |
108 | #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */ |
109 | |
110 | #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Specific Control 2 */ |
111 | #define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative Polarity */ |
112 | #define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C |
113 | #define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal Operation */ |
114 | #define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns Sequence */ |
115 | #define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns Sequence */ |
116 | #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Negotiation */ |
117 | #define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable 1000BASE-T */ |
118 | #define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000 |
119 | #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */ |
120 | #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */ |
121 | |
122 | #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alternate Page Select */ |
123 | #define GG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ |
124 | |
125 | #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) /* MAC Specific Control Register */ |
126 | /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ |
127 | #define GG82563_MSCR_TX_CLK_MASK 0x0007 |
128 | #define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004 |
129 | #define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005 |
130 | #define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006 |
131 | #define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007 |
132 | #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ |
133 | |
134 | #define GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) /* MAC Specific Control 2 */ |
135 | |
136 | #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */ |
137 | #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M; |
138 | 1 = 50-80M; |
139 | 2 = 80-110M; |
140 | 3 = 110-140M; |
141 | 4 = >140M */ |
142 | |
143 | /* Page 193 - Port Control Registers */ |
144 | #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) /* Kumeran Mode Control */ |
145 | #define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */ |
146 | #define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */ |
147 | #define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080 |
148 | #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400 |
149 | #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, 0=0.8MHz */ |
150 | #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 |
151 | |
152 | #define GG82563_PHY_PORT_RESET GG82563_REG(193, 17) /* Port Reset */ |
153 | |
154 | #define GG82563_PHY_REVISION_ID GG82563_REG(193, 18) /* Revision ID */ |
155 | |
156 | #define GG82563_PHY_DEVICE_ID GG82563_REG(193, 19) /* Device ID */ |
157 | |
158 | #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Power Management Control */ |
159 | #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enable SERDES Electrical Idle */ |
160 | #define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */ |
161 | #define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */ |
162 | #define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse Auto-Negotiation */ |
163 | #define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps Auto-Neg in non D0 */ |
164 | #define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps Auto-Neg Always */ |
165 | #define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a Reverse Auto-Negotiation */ |
166 | #define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */ |
167 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300 |
168 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */ |
169 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */ |
170 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */ |
171 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */ |
172 | |
173 | |
174 | #define GG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25) /* Rate Adaptation Control */ |
175 | |
176 | /* Page 194 - KMRN Registers */ |
177 | #define GG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16) /* FIFO's Control/Status */ |
178 | |
179 | #define GG82563_PHY_KMRN_CTRL GG82563_REG(194, 17) /* Control */ |
180 | |
181 | #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Control */ |
182 | #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */ |
183 | |
184 | #define GG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) /* Diagnostic */ |
185 | |
186 | #define GG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) /* Acknowledge Timeouts */ |
187 | |
188 | #define GG82563_PHY_ADV_ABILITY GG82563_REG(194, 21) /* Advertised Ability */ |
189 | |
190 | #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY GG82563_REG(194, 23) /* Link Partner Advertised Ability */ |
191 | |
192 | #define GG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) /* Advertised Next Page */ |
193 | |
194 | #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE GG82563_REG(194, 25) /* Link Partner Advertised Next page */ |
195 | |
196 | #define GG82563_PHY_KMRN_MISC GG82563_REG(194, 26) /* Misc. */ |
197 | |