1 | /* $NetBSD: bmtphyreg.h,v 1.2 2008/04/28 20:23:53 martin Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 2001 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Jason R. Thorpe. |
9 | * |
10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions |
12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. |
15 | * 2. Redistributions in binary form must reproduce the above copyright |
16 | * notice, this list of conditions and the following disclaimer in the |
17 | * documentation and/or other materials provided with the distribution. |
18 | * |
19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
29 | * POSSIBILITY OF SUCH DAMAGE. |
30 | */ |
31 | |
32 | #ifndef _DEV_MII_BMTPHYREG_H_ |
33 | #define _DEV_MII_BMTPHYREG_H_ |
34 | |
35 | /* |
36 | * BCM5201/BCM5202 registers. |
37 | */ |
38 | |
39 | #define MII_BMTPHY_AUX_CTL 0x10 /* auxiliary control */ |
40 | #define AUX_CTL_TXDIS 0x2000 /* transmitter disable */ |
41 | #define AUX_CTL_4B5B_BYPASS 0x0400 /* bypass 4b5b encoder */ |
42 | #define AUX_CTL_SCR_BYPASS 0x0200 /* bypass scrambler */ |
43 | #define AUX_CTL_NRZI_BYPASS 0x0100 /* bypass NRZI encoder */ |
44 | #define AUX_CTL_RXALIGN_BYPASS 0x0080 /* bypass rx symbol alignment */ |
45 | #define AUX_CTL_BASEWANDER_DIS 0x0040 /* disable baseline wander correction */ |
46 | #define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */ |
47 | |
48 | |
49 | #define MII_BMTPHY_AUX_STS 0x11 /* auxiliary status */ |
50 | #define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */ |
51 | #define AUX_STS_LOCKED 0x0200 /* descrambler locked */ |
52 | #define AUX_STS_100BASE_LINK 0x0100 /* 1 = 100base link */ |
53 | #define AUX_STS_REMFAULT 0x0080 /* remote fault */ |
54 | #define AUX_STS_DISCON_STATE 0x0040 /* disconnect state */ |
55 | #define AUX_STS_FCARDET 0x0020 /* false carrier detected */ |
56 | #define AUX_STS_BAD_ESD 0x0010 /* bad ESD detected */ |
57 | #define AUX_STS_RXERROR 0x0008 /* Rx error detected */ |
58 | #define AUX_STS_TXERROR 0x0004 /* Tx error detected */ |
59 | #define AUX_STS_LOCKERROR 0x0002 /* lock error detected */ |
60 | #define AUX_STS_MLT3ERROR 0x0001 /* MLT3 code error detected */ |
61 | |
62 | |
63 | #define MII_BMTPHY_RXERROR_CTR 0x12 /* 100base-X Rx error counter */ |
64 | #define RXERROR_CTR_MASK 0x00ff |
65 | |
66 | |
67 | #define MII_BMTPHY_FCS_CTR 0x13 /* 100base-X false carrier counter */ |
68 | #define FCS_CTR_MASK 0x00ff |
69 | |
70 | |
71 | #define MII_BMTPHY_DIS_CTR 0x14 /* 100base-X disconnect counter */ |
72 | #define DIS_CTR_MASK 0x00ff |
73 | |
74 | |
75 | #define MII_BMTPHY_PTEST 0x17 /* PTEST */ |
76 | |
77 | |
78 | #define MII_BMTPHY_AUX_CSR 0x18 /* auxiliary control/status */ |
79 | #define AUX_CSR_JABBER_DIS 0x8000 /* jabber disable */ |
80 | #define AUX_CSR_FLINK 0x4000 /* force 10baseT link pass */ |
81 | #define AUX_CSR_HSQ 0x0080 /* SQ high */ |
82 | #define AUX_CSR_LSQ 0x0040 /* SQ low */ |
83 | #define AUX_CSR_ER1 0x0020 /* edge rate 1 */ |
84 | #define AUX_CSR_ER0 0x0010 /* edge rate 0 */ |
85 | #define AUX_CSR_ANEG 0x0008 /* auto-negotiation activated */ |
86 | #define AUX_CSR_F100 0x0004 /* force 100base */ |
87 | #define AUX_CSR_SPEED 0x0002 /* 1 = 100, 0 = 10 */ |
88 | #define AUX_CSR_FDX 0x0001 /* full-duplex */ |
89 | |
90 | |
91 | #define MII_BMTPHY_AUX_SS 0x19 /* auxiliary status summary */ |
92 | #define AUX_SS_ACOMP 0x8000 /* auto-negotiation complete */ |
93 | #define AUX_SS_ACOMP_ACK 0x4000 /* auto-negotiation compl. ack */ |
94 | #define AUX_SS_AACK_DET 0x2000 /* auto-neg. ack detected */ |
95 | #define AUX_SS_ANLPAD 0x1000 /* auto-neg. link part. ability det */ |
96 | #define AUX_SS_ANEG_PAUSE 0x0800 /* pause operation bit */ |
97 | #define AUX_SS_HCD 0x0700 /* highest common denominator */ |
98 | #define AUX_SS_HCD_NONE 0x0000 /* none */ |
99 | #define AUX_SS_HCD_10T 0x0100 /* 10baseT */ |
100 | #define AUX_SS_HCD_10T_FDX 0x0200 /* 10baseT-FDX */ |
101 | #define AUX_SS_HCD_100TX 0x0300 /* 100baseTX-FDX */ |
102 | #define AUX_SS_HCD_100T4 0x0400 /* 100baseT4 */ |
103 | #define AUX_SS_HCD_100TX_FDX 0x0500 /* 100baseTX-FDX */ |
104 | #define AUX_SS_PDF 0x0080 /* parallel detection fault */ |
105 | #define AUX_SS_LPRF 0x0040 /* link partner remote fault */ |
106 | #define AUX_SS_LPPR 0x0020 /* link partner page received */ |
107 | #define AUX_SS_LPANA 0x0010 /* link partner auto-neg able */ |
108 | #define AUX_SS_SPEED 0x0008 /* 1 = 100, 0 = 10 */ |
109 | #define AUX_SS_LINK 0x0004 /* link pass */ |
110 | #define AUX_SS_ANEN 0x0002 /* auto-neg. enabled */ |
111 | #define AUX_SS_JABBER 0x0001 /* jabber detected */ |
112 | |
113 | |
114 | #define MII_BMTPHY_INTR 0x1a /* interrupt register */ |
115 | #define INTR_FDX_LED 0x8000 /* full-duplex led enable */ |
116 | #define INTR_INTR_EN 0x4000 /* interrupt enable */ |
117 | #define INTR_FDX_MASK 0x0800 /* full-dupled intr mask */ |
118 | #define INTR_SPD_MASK 0x0400 /* speed intr mask */ |
119 | #define INTR_LINK_MASK 0x0200 /* link intr mask */ |
120 | #define INTR_INTR_MASK 0x0100 /* master interrupt mask */ |
121 | #define INTR_FDX_CHANGE 0x0008 /* full-duplex change */ |
122 | #define INTR_SPD_CHANGE 0x0004 /* speed change */ |
123 | #define INTR_LINK_CHANGE 0x0002 /* link change */ |
124 | #define INTR_INTR_STATUS 0x0001 /* interrupt status */ |
125 | |
126 | |
127 | #define MII_BMTPHY_AUX2 0x1b /* auliliary mode 2 */ |
128 | #define AUX2_BLOCK_RXDV 0x0200 /* block RXDV mode enabled */ |
129 | #define AUX2_ANPDQ 0x0100 /* auto-neg parallel detection Q mode */ |
130 | #define AUX2_TRAFFIC_LED 0x0040 /* traffic meter led enable */ |
131 | #define AUX2_FXMTRCV_LED 0x0020 /* force Tx and Rx LEDs */ |
132 | #define AUX2_HS_TOKEN 0x0010 /* high-speed token ring mode */ |
133 | #define AUX2_AUTO_LP 0x0008 /* auto low-power mode */ |
134 | #define AUX2_TWOLINK_LED 0x0004 /* two link LEDs */ |
135 | #define AUX2_SQE_DIS 0x0002 /* disable SQE pulse */ |
136 | |
137 | |
138 | #define MII_BMTPHY_AUXERR 0x1c /* auxiliary error */ |
139 | #define AUXERR_MANCHESTER 0x0400 /* Manchester code error */ |
140 | #define AUXERR_EOF 0x0200 /* EOF detection error */ |
141 | #define AUXERR_POLARITY 0x0100 /* polarity inversion */ |
142 | #define AUXERR_ANEG 0x0008 /* autonegotiation enabled */ |
143 | #define AUXERR_F100 0x0004 /* force 100base */ |
144 | #define AUXERR_SPEED 0x0002 /* 1 = 100, 0 = 10 */ |
145 | #define AUXERR_FDX 0x0001 /* full-duplex */ |
146 | |
147 | |
148 | #define MII_BMTPHY_AUXMODE 0x1d /* auxiliary mode */ |
149 | #define AUXMODE_ACT_LED_DIS 0x0010 /* activity LED disable */ |
150 | #define AUXMODE_LINK_LED_DIS 0x0008 /* link LED disable */ |
151 | #define AUXMODE_BLOCK_TXEN 0x0002 /* enable block TXEN */ |
152 | |
153 | |
154 | #define MII_BMTPHY_AUXMPHY 0x1e /* auxiliary multiple phy register */ |
155 | #define AUXMPHY_HCD_TX_FDX 0x8000 /* res. is 100baseTX-FDX */ |
156 | #define AUXMPHY_HCD_T4 0x4000 /* res. is 100baseT4 */ |
157 | #define AUXMPHY_HCD_TX 0x2000 /* res. is 100baseTX */ |
158 | #define AUXMPHY_HCD_10T_FDX 0x1000 /* res. is 10baseT-FDX */ |
159 | #define AUXMPHY_HCD_10T 0x0800 /* res. is 10baseT */ |
160 | #define AUXMPHY_RES_ANEG 0x0100 /* restart auto-negotiation */ |
161 | #define AUXMPHY_ANEG_COMP 0x0080 /* auto-negotiation complete */ |
162 | #define AUXMPHY_ACK_COMP 0x0040 /* acknowledge complete */ |
163 | #define AUXMPHY_ACK_DET 0x0020 /* acknowledge detected */ |
164 | #define AUXMPHY_ABILITY_DET 0x0010 /* waiting for LP ability */ |
165 | #define AUXMPHY_SUPER_ISO 0x0008 /* super-isolate mode */ |
166 | #define AUXMPHY_10T_SERIAL 0x0002 /* 10baseT serial mode */ |
167 | |
168 | |
169 | #define MII_BMTPHY_TEST 0x1d /* Broadcom test register */ |
170 | |
171 | |
172 | #endif /* _DEV_MII_BMTPHYREG_H_ */ |
173 | |