1 | /* $NetBSD: awireg.h,v 1.12 2008/04/28 20:23:49 martin Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 1999 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Bill Sommerfeld |
9 | * |
10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions |
12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. |
15 | * 2. Redistributions in binary form must reproduce the above copyright |
16 | * notice, this list of conditions and the following disclaimer in the |
17 | * documentation and/or other materials provided with the distribution. |
18 | * |
19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
29 | * POSSIBILITY OF SUCH DAMAGE. |
30 | */ |
31 | |
32 | #ifndef _DEV_IC_AWIREG_H |
33 | #define _DEV_IC_AWIREG_H |
34 | |
35 | /* |
36 | * The firmware typically loaded onto Am79C930-based 802.11 interfaces |
37 | * uses a 32k or larger shared memory buffer to communicate with the |
38 | * host. |
39 | * |
40 | * Depending on the exact configuration of the device, this buffer may |
41 | * either be mapped into PCMCIA memory space, or accessible a byte at |
42 | * a type through PCMCIA I/O space. |
43 | * |
44 | * This header defines offsets into this shared memory. |
45 | */ |
46 | |
47 | |
48 | /* |
49 | * LAST_TXD block. 5 32-bit words. |
50 | * |
51 | * There are five different output queues; this defines pointers to |
52 | * the last completed descriptor for each one. |
53 | */ |
54 | #define AWI_LAST_TXD 0x3ec /* last completed Tx Descr */ |
55 | |
56 | #define AWI_LAST_BCAST_TXD AWI_LAST_TXD+0 |
57 | #define AWI_LAST_MGT_TXD AWI_LAST_TXD+4 |
58 | #define AWI_LAST_DATA_TXD AWI_LAST_TXD+8 |
59 | #define AWI_LAST_PS_POLL_TXD AWI_LAST_TXD+12 |
60 | #define AWI_LAST_CF_POLL_TXD AWI_LAST_TXD+16 |
61 | |
62 | /* |
63 | * Banner block; null-terminated string. |
64 | * |
65 | * The doc says it contains |
66 | * "PCnetMobile:v2.00 mmddyy APIx.x\0" |
67 | */ |
68 | |
69 | #define AWI_BANNER 0x480 /* Version string */ |
70 | #define AWI_BANNER_LEN 0x20 |
71 | |
72 | /* |
73 | * Command block protocol: |
74 | * write command byte to a zero value. |
75 | * write command status to a zero value. |
76 | * write arguments to AWI_COMMAND_PARAMS |
77 | * write command byte to a non-zero value. |
78 | * wait for command status to be non-zero. |
79 | * write command byte to a zero value. |
80 | * write command status to a zero value. |
81 | */ |
82 | |
83 | #define AWI_CMD 0x4a0 /* Command opcode byte */ |
84 | |
85 | #define AWI_CMD_IDLE 0x0 |
86 | #define AWI_CMD_NOP 0x1 |
87 | |
88 | #define AWI_CMD_SET_MIB 0x2 |
89 | #define AWI_CMD_GET_MIB 0x9 |
90 | #define AWI_CA_MIB_TYPE (AWI_CMD_PARAMS + 0x0) |
91 | #define AWI_CA_MIB_SIZE (AWI_CMD_PARAMS + 0x1) |
92 | #define AWI_CA_MIB_INDEX (AWI_CMD_PARAMS + 0x2) |
93 | #define AWI_CA_MIB_DATA (AWI_CMD_PARAMS + 0x4) |
94 | #define AWI_MIB_LOCAL 0 |
95 | #define AWI_MIB_ADDR 2 |
96 | #define AWI_MIB_MAC 3 |
97 | #define AWI_MIB_STAT 4 |
98 | #define AWI_MIB_MGT 5 |
99 | #define AWI_MIB_DRVR 6 |
100 | #define AWI_MIB_PHY 7 |
101 | |
102 | #define AWI_CMD_INIT_TX 0x3 |
103 | #define AWI_CA_TX_LEN 20 |
104 | #define AWI_CA_TX_DATA (AWI_CMD_PARAMS + 0x0) |
105 | #define AWI_CA_TX_MGT (AWI_CMD_PARAMS + 0x4) |
106 | #define AWI_CA_TX_BCAST (AWI_CMD_PARAMS + 0x8) |
107 | #define AWI_CA_TX_PS (AWI_CMD_PARAMS + 0xc) |
108 | #define AWI_CA_TX_CF (AWI_CMD_PARAMS + 0x10) |
109 | |
110 | #define AWI_CMD_FLUSH_TX 0x4 |
111 | #define AWI_CA_FTX_LEN 5 |
112 | #define AWI_CA_FTX_DATA (AWI_CMD_PARAMS + 0x0) |
113 | #define AWI_CA_FTX_MGT (AWI_CMD_PARAMS + 0x1) |
114 | #define AWI_CA_FTX_BCAST (AWI_CMD_PARAMS + 0x2) |
115 | #define AWI_CA_FTX_PS (AWI_CMD_PARAMS + 0x3) |
116 | #define AWI_CA_FTX_CF (AWI_CMD_PARAMS + 0x4) |
117 | |
118 | #define AWI_CMD_INIT_RX 0x5 |
119 | #define AWI_CA_IRX_LEN 0x8 |
120 | #define AWI_CA_IRX_DATA_DESC (AWI_CMD_PARAMS + 0x0) /* return */ |
121 | #define AWI_CA_IRX_PS_DESC (AWI_CMD_PARAMS + 0x4) /* return */ |
122 | |
123 | #define AWI_CMD_KILL_RX 0x6 |
124 | |
125 | #define AWI_CMD_SLEEP 0x7 |
126 | #define AWI_CA_SLEEP_LEN 8 |
127 | #define AWI_CA_WAKEUP (AWI_CMD_PARAMS + 0x0) /* uint64 */ |
128 | |
129 | #define AWI_CMD_WAKE 0x8 |
130 | |
131 | #define AWI_CMD_SCAN 0xa |
132 | #define AWI_CA_SCAN_LEN 6 |
133 | #define AWI_CA_SCAN_DURATION (AWI_CMD_PARAMS + 0x0) |
134 | #define AWI_CA_SCAN_SET (AWI_CMD_PARAMS + 0x2) |
135 | #define AWI_CA_SCAN_PATTERN (AWI_CMD_PARAMS + 0x3) |
136 | #define AWI_CA_SCAN_IDX (AWI_CMD_PARAMS + 0x4) |
137 | #define AWI_CA_SCAN_SUSP (AWI_CMD_PARAMS + 0x5) |
138 | |
139 | #define AWI_CMD_SYNC 0xb |
140 | #define AWI_CA_SYNC_LEN 20 |
141 | #define AWI_CA_SYNC_SET (AWI_CMD_PARAMS + 0x0) |
142 | #define AWI_CA_SYNC_PATTERN (AWI_CMD_PARAMS + 0x1) |
143 | #define AWI_CA_SYNC_IDX (AWI_CMD_PARAMS + 0x2) |
144 | #define AWI_CA_SYNC_STARTBSS (AWI_CMD_PARAMS + 0x3) |
145 | #define AWI_CA_SYNC_DWELL (AWI_CMD_PARAMS + 0x4) |
146 | #define AWI_CA_SYNC_MBZ (AWI_CMD_PARAMS + 0x6) |
147 | #define AWI_CA_SYNC_TIMESTAMP (AWI_CMD_PARAMS + 0x8) |
148 | #define AWI_CA_SYNC_REFTIME (AWI_CMD_PARAMS + 0x10) |
149 | |
150 | #define AWI_CMD_RESUME 0xc |
151 | |
152 | #define AWI_CMD_STATUS 0x4a1 /* Command status */ |
153 | |
154 | #define AWI_STAT_IDLE 0x0 |
155 | #define AWI_STAT_OK 0x1 |
156 | #define AWI_STAT_BADCMD 0x2 |
157 | #define AWI_STAT_BADPARM 0x3 |
158 | #define AWI_STAT_NOTIMP 0x4 |
159 | #define AWI_STAT_BADRES 0x5 |
160 | #define AWI_STAT_BADMODE 0x6 |
161 | |
162 | #define AWI_ERROR_OFFSET 0x4a2 /* Offset to erroneous parameter */ |
163 | #define AWI_CMD_PARAMS 0x4a4 /* Command parameters */ |
164 | |
165 | #define AWI_CSB 0x4f0 /* Control/Status block */ |
166 | |
167 | #define AWI_SELFTEST 0x4f0 |
168 | |
169 | #define AWI_SELFTEST_INIT 0x00 /* initial */ |
170 | #define AWI_SELFTEST_FIRMCKSUM 0x01 /* firmware cksum running */ |
171 | #define AWI_SELFTEST_HARDWARE 0x02 /* hardware tests running */ |
172 | #define AWI_SELFTEST_MIB 0x03 /* mib initializing */ |
173 | |
174 | #define AWI_SELFTEST_MIB_FAIL 0xfa |
175 | #define AWI_SELFTEST_RADIO_FAIL 0xfb |
176 | #define AWI_SELFTEST_MAC_FAIL 0xfc |
177 | #define AWI_SELFTEST_FLASH_FAIL 0xfd |
178 | #define AWI_SELFTEST_RAM_FAIL 0xfe |
179 | #define AWI_SELFTEST_PASSED 0xff |
180 | |
181 | #define AWI_STA_STATE 0x4f1 |
182 | |
183 | #define AWI_STA_AP 0x20 /* acting as AP */ |
184 | #define AWI_STA_NOPSP 0x10 /* Power Saving disabled */ |
185 | #define AWI_STA_DOZE 0x08 /* about to go to sleep */ |
186 | #define AWI_STA_PSP 0x04 /* enable PSP */ |
187 | #define AWI_STA_RXEN 0x02 /* enable RX */ |
188 | #define AWI_STA_TXEN 0x01 /* enable TX */ |
189 | |
190 | #define AWI_INTSTAT 0x4f3 |
191 | #define AWI_INTMASK 0x4f4 |
192 | |
193 | /* Bits in AWI_INTSTAT/AWI_INTMASK */ |
194 | |
195 | #define AWI_INT_GROGGY 0x80 /* about to wake up */ |
196 | #define AWI_INT_CFP_ENDING 0x40 /* cont. free period ending */ |
197 | #define AWI_INT_DTIM 0x20 /* beacon outgoing */ |
198 | #define AWI_INT_CFP_START 0x10 /* cont. free period starting */ |
199 | #define AWI_INT_SCAN_CMPLT 0x08 /* scan complete */ |
200 | #define AWI_INT_TX 0x04 /* tx done */ |
201 | #define AWI_INT_RX 0x02 /* rx done */ |
202 | #define AWI_INT_CMD 0x01 /* cmd done */ |
203 | |
204 | /* |
205 | * The following are used to implement a locking protocol between host |
206 | * and MAC to protect the interrupt status and mask fields. |
207 | * |
208 | * driver: read lockout_host byte; if zero, set lockout_mac to non-zero, |
209 | * then reread lockout_host byte; if still zero, host has lock. |
210 | * if non-zero, clear lockout_mac, loop. |
211 | */ |
212 | |
213 | #define AWI_LOCKOUT_MAC 0x4f5 |
214 | #define AWI_LOCKOUT_HOST 0x4f6 |
215 | |
216 | |
217 | #define AWI_INTSTAT2 0x4f7 |
218 | #define AWI_INTMASK2 0x4fd |
219 | |
220 | /* Bits in AWI_INTSTAT2/INTMASK2 */ |
221 | #define AWI_INT2_RXMGT 0x80 /* mgt/ps received */ |
222 | #define AWI_INT2_RXDATA 0x40 /* data received */ |
223 | #define AWI_INT2_TXMGT 0x10 /* mgt tx done */ |
224 | #define AWI_INT2_TXCF 0x08 /* CF tx done */ |
225 | #define AWI_INT2_TXPS 0x04 /* PS tx done */ |
226 | #define AWI_INT2_TXBCAST 0x02 /* Broadcast tx done */ |
227 | #define AWI_INT2_TXDATA 0x01 /* data tx done */ |
228 | |
229 | #define AWI_DIS_PWRDN 0x4fc /* disable powerdown if set */ |
230 | |
231 | #define AWI_DRIVERSTATE 0x4fe /* driver state */ |
232 | |
233 | #define AWI_DRV_STATEMASK 0x0f |
234 | |
235 | #define AWI_DRV_RESET 0x0 |
236 | #define AWI_DRV_INFSY 0x1 /* inf synced */ |
237 | #define AWI_DRV_ADHSC 0x2 /* adhoc scan */ |
238 | #define AWI_DRV_ADHSY 0x3 /* adhoc synced */ |
239 | #define AWI_DRV_INFSC 0x4 /* inf scanning */ |
240 | #define AWI_DRV_INFAUTH 0x5 /* inf authed */ |
241 | #define AWI_DRV_INFASSOC 0x6 /* inf associated */ |
242 | #define AWI_DRV_INFTOSS 0x7 /* inf handoff */ |
243 | #define AWI_DRV_APNONE 0x8 /* AP activity: no assoc */ |
244 | #define AWI_DRV_APQUIET 0xc /* AP: >=one assoc, no traffic */ |
245 | #define AWI_DRV_APLO 0xd /* AP: >=one assoc, light tfc */ |
246 | #define AWI_DRV_APMED 0xe /* AP: >=one assoc, mod tfc */ |
247 | #define AWI_DRV_APHIGH 0xf /* AP: >=one assoc, heavy tfc */ |
248 | |
249 | #define AWI_DRV_AUTORXLED 0x10 |
250 | #define AWI_DRV_AUTOTXLED 0x20 |
251 | #define AWI_DRV_RXLED 0x40 |
252 | #define AWI_DRV_TXLED 0x80 |
253 | |
254 | #define AWI_VBM_OFFSET 0x500 /* Virtual Bit Map */ |
255 | #define AWI_VBM_LENGTH 0x501 |
256 | #define AWI_VBM_BITMAP 0x502 |
257 | |
258 | #define AWI_BUFFERS 0x600 /* Buffers */ |
259 | #define AWI_BUFFERS_END 0x6000 |
260 | |
261 | /* |
262 | * Receive descriptors; there are a linked list of these chained |
263 | * through the "NEXT" fields, starting from XXX |
264 | */ |
265 | |
266 | #define AWI_RXD_SIZE 0x18 |
267 | |
268 | #define AWI_RXD_NEXT 0x4 |
269 | #define AWI_RXD_NEXT_LAST 0x80000000 |
270 | |
271 | |
272 | #define AWI_RXD_HOST_DESC_STATE 0x9 |
273 | |
274 | #define AWI_RXD_ST_OWN 0x80 /* host owns this */ |
275 | #define AWI_RXD_ST_CONSUMED 0x40 /* host is done */ |
276 | #define AWI_RXD_ST_LF 0x20 /* last frag */ |
277 | #define AWI_RXD_ST_CRC 0x08 /* CRC error */ |
278 | #define AWI_RXD_ST_OFLO 0x02 /* possible buffer overrun */ |
279 | #define AWI_RXD_ST_RXERROR 0x01 /* this frame is borked; discard me */ |
280 | |
281 | #define 0xa /* 1 byte: radio strength indicator */ |
282 | #define AWI_RXD_INDEX 0xb /* 1 byte: FH hop index or DS channel */ |
283 | #define AWI_RXD_LOCALTIME 0xc /* 4 bytes: local time of RX */ |
284 | #define AWI_RXD_START_FRAME 0x10 /* 4 bytes: ptr to first received byte */ |
285 | #define AWI_RXD_LEN 0x14 /* 2 bytes: rx len in bytes */ |
286 | #define AWI_RXD_RATE 0x16 /* 1 byte: rx rate in 1e5 bps */ |
287 | |
288 | /* |
289 | * Transmit descriptors. |
290 | */ |
291 | |
292 | #define AWI_TXD_SIZE 0x18 |
293 | |
294 | #define AWI_TXD_START 0x00 /* pointer to start of frame */ |
295 | #define AWI_TXD_NEXT 0x04 /* pointer to next TXD */ |
296 | #define AWI_TXD_LENGTH 0x08 /* length of frame */ |
297 | #define AWI_TXD_STATE 0x0a /* state */ |
298 | |
299 | #define AWI_TXD_ST_OWN 0x80 /* MAC owns this */ |
300 | #define AWI_TXD_ST_DONE 0x40 /* MAC is done */ |
301 | #define AWI_TXD_ST_REJ 0x20 /* MAC doesn't like */ |
302 | #define AWI_TXD_ST_MSDU 0x10 /* MSDU timeout */ |
303 | #define AWI_TXD_ST_ABRT 0x08 /* TX aborted */ |
304 | #define AWI_TXD_ST_RETURNED 0x04 /* TX returned */ |
305 | #define AWI_TXD_ST_RETRY 0x02 /* TX retries exceeded */ |
306 | #define AWI_TXD_ST_ERROR 0x01 /* TX error */ |
307 | |
308 | #define AWI_TXD_RATE 0x0b /* rate */ |
309 | |
310 | #define AWI_RATE_1MBIT 10 |
311 | #define AWI_RATE_2MBIT 20 |
312 | |
313 | #define AWI_TXD_NDA 0x0c /* num DIFS attempts */ |
314 | #define AWI_TXD_NDF 0x0d /* num DIFS failures */ |
315 | #define AWI_TXD_NSA 0x0e /* num SIFS attempts */ |
316 | #define AWI_TXD_NSF 0x0f /* num SIFS failures */ |
317 | |
318 | #define AWI_TXD_NRA 0x14 /* num RTS attempts */ |
319 | #define AWI_TXD_NDTA 0x15 /* num data attempts */ |
320 | #define AWI_TXD_CTL 0x16 /* control */ |
321 | |
322 | #define AWI_TXD_CTL_PSN 0x80 /* preserve sequence in MAC frame */ |
323 | #define AWI_TXD_CTL_BURST 0x02 /* host is doing 802.11 fragmt. */ |
324 | #define AWI_TXD_CTL_FRAGS 0x01 /* override normal fragmentation */ |
325 | |
326 | /* |
327 | * MIB structures. |
328 | */ |
329 | |
330 | #define AWI_ESS_ID_SIZE (IEEE80211_NWID_LEN+2) |
331 | struct awi_mib_local { |
332 | u_int8_t Fragmentation_Dis; |
333 | u_int8_t Add_PLCP_Dis; |
334 | u_int8_t MAC_Hdr_Prsv; |
335 | u_int8_t Rx_Mgmt_Que_En; |
336 | u_int8_t Re_Assembly_Dis; |
337 | u_int8_t Strip_PLCP_Dis; |
338 | u_int8_t Rx_Error_Dis; |
339 | u_int8_t Power_Saving_Mode_Dis; |
340 | u_int8_t Accept_All_Multicast_Dis; |
341 | u_int8_t Check_Seq_Cntl_Dis; |
342 | u_int8_t Flush_CFP_Queue_On_CF_End; |
343 | u_int8_t Network_Mode; |
344 | u_int8_t PWD_Lvl; |
345 | u_int8_t CFP_Mode; |
346 | u_int8_t Tx_Buffer_Offset[4]; |
347 | u_int8_t Tx_Buffer_Size[4]; |
348 | u_int8_t Rx_Buffer_Offset[4]; |
349 | u_int8_t Rx_Buffer_Size[4]; |
350 | u_int8_t Acting_as_AP; |
351 | u_int8_t Fill_CFP; |
352 | } __packed; |
353 | |
354 | struct awi_mib_mac { |
355 | u_int8_t _Reserved1[2]; |
356 | u_int8_t _Reserved2[2]; |
357 | u_int8_t aRTS_Threshold[2]; |
358 | u_int8_t aCW_max[2]; |
359 | u_int8_t aCW_min[2]; |
360 | u_int8_t aPromiscuous_Enable; |
361 | u_int8_t _Reserved3; |
362 | u_int8_t _Reserved4[4]; |
363 | u_int8_t aShort_Retry_Limit; |
364 | u_int8_t aLong_Retry_Limit; |
365 | u_int8_t aMax_Frame_Length[2]; |
366 | u_int8_t aFragmentation_Threshold[2]; |
367 | u_int8_t aProbe_Delay[2]; |
368 | u_int8_t aMin_Probe_Response_Time[2]; |
369 | u_int8_t aMax_Probe_Response_Time[2]; |
370 | u_int8_t aMax_Transmit_MSDU_Lifetime[4]; |
371 | u_int8_t aMax_Receive_MSDU_Lifetime[4]; |
372 | u_int8_t aStation_Basic_Rate[2]; |
373 | u_int8_t aDesired_ESS_ID[AWI_ESS_ID_SIZE]; |
374 | } __packed; |
375 | |
376 | struct awi_mib_stat { |
377 | u_int8_t aTransmitted_MPDU_Count[4]; |
378 | u_int8_t aTransmitted_MSDU_Count[4]; |
379 | u_int8_t aOctets_Transmitted_Cnt[4]; |
380 | u_int8_t aMulticast_Transmitted_Frame_Count[2]; |
381 | u_int8_t aBroadcast_Transmitted_Frame_Count[2]; |
382 | u_int8_t aFailed_Count[4]; |
383 | u_int8_t aRetry_Count[4]; |
384 | u_int8_t aMultiple_Retry_Count[4]; |
385 | u_int8_t aFrame_Duplicate_Count[4]; |
386 | u_int8_t aRTS_Success_Count[4]; |
387 | u_int8_t aRTS_Failure_Count[4]; |
388 | u_int8_t aACK_Failure_Count[4]; |
389 | u_int8_t aReceived_Frame_Count [4]; |
390 | u_int8_t aOctets_Received_Count[4]; |
391 | u_int8_t aMulticast_Received_Count[2]; |
392 | u_int8_t aBroadcast_Received_Count[2]; |
393 | u_int8_t aFCS_Error_Count[4]; |
394 | u_int8_t aError_Count[4]; |
395 | u_int8_t aWEP_Undecryptable_Count[4]; |
396 | } __packed; |
397 | |
398 | struct awi_mib_mgt { |
399 | u_int8_t aPower_Mgt_Mode; |
400 | u_int8_t aScan_Mode; |
401 | #define AWI_SCAN_PASSIVE 0x00 |
402 | #define AWI_SCAN_ACTIVE 0x01 |
403 | #define AWI_SCAN_BACKGROUND 0x02 |
404 | u_int8_t aScan_State; |
405 | u_int8_t aDTIM_Period; |
406 | u_int8_t aATIM_Window[2]; |
407 | u_int8_t Wep_Required; |
408 | #define AWI_WEP_ON 0x10 |
409 | #define AWI_WEP_OFF 0x00 |
410 | u_int8_t _Reserved1; |
411 | u_int8_t aBeacon_Period[2]; |
412 | u_int8_t aPassive_Scan_Duration[2]; |
413 | u_int8_t aListen_Interval[2]; |
414 | u_int8_t aMedium_Occupancy_Limit[2]; |
415 | u_int8_t aMax_MPDU_Time[2]; |
416 | u_int8_t aCFP_Max_Duration[2]; |
417 | u_int8_t aCFP_Rate; |
418 | u_int8_t Do_Not_Receive_DTIMs; |
419 | u_int8_t aStation_ID[2]; |
420 | u_int8_t aCurrent_BSS_ID[ETHER_ADDR_LEN]; |
421 | u_int8_t aCurrent_ESS_ID[AWI_ESS_ID_SIZE]; |
422 | } __packed; |
423 | |
424 | #define AWI_GROUP_ADDR_SIZE 4 |
425 | struct awi_mib_addr { |
426 | u_int8_t aMAC_Address[ETHER_ADDR_LEN]; |
427 | u_int8_t aGroup_Addresses[AWI_GROUP_ADDR_SIZE][ETHER_ADDR_LEN]; |
428 | u_int8_t aTransmit_Enable_Status; |
429 | u_int8_t _Reserved1; |
430 | } __packed; |
431 | |
432 | #define AWI_PWR_LEVEL_SIZE 4 |
433 | struct awi_mib_phy { |
434 | u_int8_t aSlot_Time[2]; |
435 | u_int8_t aSIFS[2]; |
436 | u_int8_t aMPDU_Maximum[2]; |
437 | u_int8_t aHop_Time[2]; |
438 | u_int8_t aSuprt_Data_Rates[4]; |
439 | u_int8_t aCurrent_Reg_Domain; |
440 | #define AWI_REG_DOMAIN_US 0x10 |
441 | #define AWI_REG_DOMAIN_CA 0x20 |
442 | #define AWI_REG_DOMAIN_EU 0x30 |
443 | #define AWI_REG_DOMAIN_ES 0x31 |
444 | #define AWI_REG_DOMAIN_FR 0x32 |
445 | #define AWI_REG_DOMAIN_JP 0x40 |
446 | u_int8_t aPreamble_Lngth; |
447 | u_int8_t aPLCP_Hdr_Lngth; |
448 | u_int8_t Pwr_Up_Time[AWI_PWR_LEVEL_SIZE][2]; |
449 | u_int8_t IEEE_PHY_Type; |
450 | #define AWI_PHY_TYPE_FH 1 |
451 | #define AWI_PHY_TYPE_DS 2 |
452 | #define AWI_PHY_TYPE_IR 3 |
453 | u_int8_t RCR_33A_Bits[8]; |
454 | } __packed; |
455 | |
456 | #endif /* _DEV_IC_AWIREG_H */ |
457 | |