1 | /* |
2 | * Copyright (c) 2008 Sam Leffler, Errno Consulting |
3 | * Copyright (c) 2008 Atheros Communications, Inc. |
4 | * |
5 | * Permission to use, copy, modify, and/or distribute this software for any |
6 | * purpose with or without fee is hereby granted, provided that the above |
7 | * copyright notice and this permission notice appear in all copies. |
8 | * |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
16 | * |
17 | * $Id: ah_eeprom_v14.h,v 1.2 2011/02/21 11:06:38 cegger Exp $ |
18 | */ |
19 | #ifndef _AH_EEPROM_V14_H_ |
20 | #define _AH_EEPROM_V14_H_ |
21 | |
22 | #include "ah_eeprom.h" |
23 | |
24 | /* reg_off = 4 * (eep_off) */ |
25 | #define AR5416_EEPROM_S 2 |
26 | #define AR5416_EEPROM_OFFSET 0x2000 |
27 | #define AR5416_EEPROM_START_ADDR 0x503f1200 |
28 | #define AR5416_EEPROM_MAX 0xae0 /* Ignore for the moment used only on the flash implementations */ |
29 | #define AR5416_EEPROM_MAGIC 0xa55a |
30 | #define AR5416_EEPROM_MAGIC_OFFSET 0x0 |
31 | |
32 | #define owl_get_ntxchains(_txchainmask) \ |
33 | (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) |
34 | |
35 | #ifdef __LINUX_ARM_ARCH__ /* AP71 */ |
36 | #define owl_eep_start_loc 0 |
37 | #else |
38 | #define owl_eep_start_loc 256 |
39 | #endif |
40 | |
41 | /* End temp defines */ |
42 | |
43 | #define AR5416_EEP_NO_BACK_VER 0x1 |
44 | #define AR5416_EEP_VER 0xE |
45 | #define AR5416_EEP_VER_MINOR_MASK 0xFFF |
46 | // Adds modal params txFrameToPaOn, txFrametoDataStart, ht40PowerInc |
47 | #define AR5416_EEP_MINOR_VER_2 0x2 |
48 | // Adds modal params bswAtten, bswMargin, swSettle and base OpFlags for HT20/40 Disable |
49 | #define AR5416_EEP_MINOR_VER_3 0x3 |
50 | #define AR5416_EEP_MINOR_VER_7 0x7 |
51 | #define AR5416_EEP_MINOR_VER_9 0x9 |
52 | #define AR5416_EEP_MINOR_VER_16 0x10 |
53 | #define AR5416_EEP_MINOR_VER_17 0x11 |
54 | #define AR5416_EEP_MINOR_VER_19 0x13 |
55 | |
56 | // 16-bit offset location start of calibration struct |
57 | #define AR5416_EEP_START_LOC 256 |
58 | #define AR5416_NUM_5G_CAL_PIERS 8 |
59 | #define AR5416_NUM_2G_CAL_PIERS 4 |
60 | #define AR5416_NUM_5G_20_TARGET_POWERS 8 |
61 | #define AR5416_NUM_5G_40_TARGET_POWERS 8 |
62 | #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 |
63 | #define AR5416_NUM_2G_20_TARGET_POWERS 4 |
64 | #define AR5416_NUM_2G_40_TARGET_POWERS 4 |
65 | #define AR5416_NUM_CTLS 24 |
66 | #define AR5416_NUM_BAND_EDGES 8 |
67 | #define AR5416_NUM_PD_GAINS 4 |
68 | #define AR5416_PD_GAINS_IN_MASK 4 |
69 | #define AR5416_PD_GAIN_ICEPTS 5 |
70 | #define AR5416_EEPROM_MODAL_SPURS 5 |
71 | #define AR5416_MAX_RATE_POWER 63 |
72 | #define AR5416_NUM_PDADC_VALUES 128 |
73 | #define AR5416_NUM_RATES 16 |
74 | #define AR5416_BCHAN_UNUSED 0xFF |
75 | #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 |
76 | #define AR5416_EEPMISC_BIG_ENDIAN 0x01 |
77 | #define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) |
78 | #define AR5416_MAX_CHAINS 3 |
79 | #define AR5416_PWR_TABLE_OFFSET_DB -5 |
80 | #define AR5416_ANT_16S 25 |
81 | |
82 | #define AR5416_NUM_ANT_CHAIN_FIELDS 7 |
83 | #define AR5416_NUM_ANT_COMMON_FIELDS 4 |
84 | #define AR5416_SIZE_ANT_CHAIN_FIELD 3 |
85 | #define AR5416_SIZE_ANT_COMMON_FIELD 4 |
86 | #define AR5416_ANT_CHAIN_MASK 0x7 |
87 | #define AR5416_ANT_COMMON_MASK 0xf |
88 | #define AR5416_CHAIN_0_IDX 0 |
89 | #define AR5416_CHAIN_1_IDX 1 |
90 | #define AR5416_CHAIN_2_IDX 2 |
91 | |
92 | #define AR5416_OPFLAGS_11A 0x01 |
93 | #define AR5416_OPFLAGS_11G 0x02 |
94 | #define AR5416_OPFLAGS_5G_HT40 0x04 |
95 | #define AR5416_OPFLAGS_2G_HT40 0x08 |
96 | #define AR5416_OPFLAGS_5G_HT20 0x10 |
97 | #define AR5416_OPFLAGS_2G_HT20 0x20 |
98 | |
99 | /* RF silent fields in EEPROM */ |
100 | #define EEP_RFSILENT_ENABLED 0x0001 /* enabled/disabled */ |
101 | #define EEP_RFSILENT_ENABLED_S 0 |
102 | #define EEP_RFSILENT_POLARITY 0x0002 /* polarity */ |
103 | #define EEP_RFSILENT_POLARITY_S 1 |
104 | #define EEP_RFSILENT_GPIO_SEL 0x001c /* gpio PIN */ |
105 | #define EEP_RFSILENT_GPIO_SEL_S 2 |
106 | |
107 | /* Rx gain type values */ |
108 | #define AR5416_EEP_RXGAIN_23dB_BACKOFF 0 |
109 | #define AR5416_EEP_RXGAIN_13dB_BACKOFF 1 |
110 | #define AR5416_EEP_RXGAIN_ORIG 2 |
111 | |
112 | /* Tx gain type values */ |
113 | #define AR5416_EEP_TXGAIN_ORIG 0 |
114 | #define AR5416_EEP_TXGAIN_HIGH_POWER 1 |
115 | |
116 | typedef struct spurChanStruct { |
117 | uint16_t spurChan; |
118 | uint8_t spurRangeLow; |
119 | uint8_t spurRangeHigh; |
120 | } __packed SPUR_CHAN; |
121 | |
122 | typedef struct CalTargetPowerLegacy { |
123 | uint8_t bChannel; |
124 | uint8_t tPow2x[4]; |
125 | } __packed CAL_TARGET_POWER_LEG; |
126 | |
127 | typedef struct CalTargetPowerHt { |
128 | uint8_t bChannel; |
129 | uint8_t tPow2x[8]; |
130 | } __packed CAL_TARGET_POWER_HT; |
131 | |
132 | typedef struct CalCtlEdges { |
133 | uint8_t bChannel; |
134 | uint8_t tPowerFlag; /* [0..5] tPower [6..7] flag */ |
135 | #define CAL_CTL_EDGES_POWER 0x3f |
136 | #define CAL_CTL_EDGES_POWER_S 0 |
137 | #define CAL_CTL_EDGES_FLAG 0xc0 |
138 | #define CAL_CTL_EDGES_FLAG_S 6 |
139 | } __packed CAL_CTL_EDGES; |
140 | |
141 | /* |
142 | * NB: The format in EEPROM has words 0 and 2 swapped (i.e. version |
143 | * and length are swapped). We reverse their position after reading |
144 | * the data into host memory so the version field is at the same |
145 | * offset as in previous EEPROM layouts. This makes utilities that |
146 | * inspect the EEPROM contents work without looking at the PCI device |
147 | * id which may or may not be reliable. |
148 | */ |
149 | typedef struct { |
150 | uint16_t ; /* NB: length in EEPROM */ |
151 | uint16_t ; |
152 | uint16_t ; /* NB: version in EEPROM */ |
153 | uint8_t ; |
154 | uint8_t ; |
155 | uint16_t [2]; |
156 | uint8_t [6]; |
157 | uint8_t ; |
158 | uint8_t ; |
159 | uint16_t ; |
160 | uint16_t ; |
161 | uint16_t ; |
162 | uint32_t ; |
163 | uint8_t ; |
164 | uint8_t ; |
165 | uint8_t ; |
166 | uint8_t ; |
167 | uint8_t ; |
168 | uint8_t ; /* use the DAC high power mode (MB91) */ |
169 | uint8_t ;/* 1: use open loop power control, |
170 | 0: use closed loop power control */ |
171 | uint8_t ; |
172 | uint8_t ; /* high power tx gain table support */ |
173 | uint8_t ; /* "1" if the card is an HB93 1x2 */ |
174 | uint8_t [24]; |
175 | } __packed ; // 64 B |
176 | |
177 | typedef struct { |
178 | uint32_t [AR5416_MAX_CHAINS]; // 12 |
179 | uint32_t ; // 4 |
180 | int8_t [AR5416_MAX_CHAINS]; // 3 |
181 | uint8_t ; // 1 |
182 | uint8_t [AR5416_MAX_CHAINS]; // 3 |
183 | uint8_t [AR5416_MAX_CHAINS]; // 3 |
184 | uint8_t ; // 1 |
185 | int8_t ; // 1 |
186 | uint8_t [AR5416_MAX_CHAINS]; // 3 |
187 | uint8_t ; // 1 |
188 | uint8_t ; // 1 |
189 | uint8_t ; // 1 |
190 | uint8_t ; // 1 |
191 | uint8_t [AR5416_MAX_CHAINS]; // 3 |
192 | uint8_t ; // 1 |
193 | uint8_t ; // 1 |
194 | int8_t [AR5416_MAX_CHAINS]; // 1 |
195 | int8_t [AR5416_MAX_CHAINS]; // 1 |
196 | uint8_t ; // 1 |
197 | uint8_t ; // 1 |
198 | uint8_t ; // 1 |
199 | uint8_t ; // 1 |
200 | uint8_t ; // 1 |
201 | uint8_t ; // 1 -> 48 B |
202 | uint8_t ; // 1 |
203 | uint8_t ; // 1 |
204 | uint8_t ; // 1 |
205 | uint8_t [AR5416_MAX_CHAINS]; // 3 |
206 | uint8_t [AR5416_MAX_CHAINS]; // 3 |
207 | uint8_t ; // 1 |
208 | uint8_t [AR5416_MAX_CHAINS]; // 3 -> New for AR9280 (0xa20c/b20c 11:6) |
209 | uint8_t [AR5416_MAX_CHAINS]; // 3 -> New for AR9280 (0xa20c/b20c 21:17) |
210 | uint8_t ; // 1 -> ob and db become chain specific from AR9280 |
211 | uint8_t ; // 1 |
212 | uint8_t ; // 1 |
213 | #define AR5416_EEP_FLAG_USEANT1 0x01 /* +1 configured antenna */ |
214 | #define AR5416_EEP_FLAG_FORCEXPAON 0x02 /* force XPA bit for 5G */ |
215 | #define AR5416_EEP_FLAG_LOCALBIAS 0x04 /* enable local bias */ |
216 | #define AR5416_EEP_FLAG_FEMBANDSELECT 0x08 /* FEM band select used */ |
217 | #define AR5416_EEP_FLAG_XLNABUFIN 0x10 |
218 | #define AR5416_EEP_FLAG_XLNAISEL 0x60 |
219 | #define AR5416_EEP_FLAG_XLNAISEL_S 5 |
220 | #define AR5416_EEP_FLAG_XLNABUFMODE 0x80 |
221 | uint8_t ; // [0..1]: bb_tx_dac_scale_cck |
222 | uint16_t [3]; // 3 |
223 | uint8_t [6]; // 6 |
224 | |
225 | SPUR_CHAN [AR5416_EEPROM_MODAL_SPURS]; // 20 B |
226 | } __packed ; // == 100 B |
227 | |
228 | typedef struct calDataPerFreqOpLoop { |
229 | uint8_t pwrPdg[2][5]; /* power measurement */ |
230 | uint8_t vpdPdg[2][5]; /* pdadc voltage at power measurement */ |
231 | uint8_t pcdac[2][5]; /* pcdac used for power measurement */ |
232 | uint8_t empty[2][5]; /* future use */ |
233 | } __packed CAL_DATA_PER_FREQ_OP_LOOP; |
234 | |
235 | typedef struct CalCtlData { |
236 | CAL_CTL_EDGES ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; |
237 | } __packed CAL_CTL_DATA; |
238 | |
239 | typedef struct calDataPerFreq { |
240 | uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; |
241 | uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; |
242 | } __packed CAL_DATA_PER_FREQ; |
243 | |
244 | struct ar5416eeprom { |
245 | BASE_EEP_HEADER ; // 64 B |
246 | uint8_t custData[64]; // 64 B |
247 | MODAL_EEP_HEADER [2]; // 200 B |
248 | uint8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; |
249 | uint8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; |
250 | CAL_DATA_PER_FREQ calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; |
251 | CAL_DATA_PER_FREQ calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; |
252 | CAL_TARGET_POWER_LEG calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; |
253 | CAL_TARGET_POWER_HT calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; |
254 | CAL_TARGET_POWER_HT calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; |
255 | CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; |
256 | CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; |
257 | CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; |
258 | CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; |
259 | uint8_t ctlIndex[AR5416_NUM_CTLS]; |
260 | CAL_CTL_DATA ctlData[AR5416_NUM_CTLS]; |
261 | uint8_t padding; |
262 | } __packed; |
263 | |
264 | typedef struct { |
265 | struct ar5416eeprom ee_base; |
266 | #define NUM_EDGES 8 |
267 | uint16_t ee_numCtls; |
268 | RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_NUM_CTLS]; |
269 | /* XXX these are dynamically calculated for use by shared code */ |
270 | int8_t ee_antennaGainMax[2]; |
271 | } HAL_EEPROM_v14; |
272 | #endif /* _AH_EEPROM_V14_H_ */ |
273 | |