1/* $NetBSD: smc83c170reg.h,v 1.13 2008/04/28 20:23:51 martin Exp $ */
2
3/*-
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#ifndef _DEV_IC_SMC83C170REG_H_
34#define _DEV_IC_SMC83C170REG_H_
35
36/*
37 * Register description for the Standard Microsystems Corp. 83C170
38 * Ethernet PCI Integrated Controller (EPIC/100).
39 */
40
41/*
42 * EPIC transmit descriptor. Must be 4-byte aligned.
43 */
44struct epic_txdesc {
45 volatile uint32_t et_txstatus; /* transmit status; see below */
46 volatile uint32_t et_bufaddr; /* buffer address */
47 volatile uint32_t et_control; /* control word; see below */
48 volatile uint32_t et_nextdesc; /* next descriptor pointer */
49};
50
51/* et_txstatus */
52#define TXSTAT_TXLENGTH_SHIFT 16 /* TX length in higher 16bits */
53#define TXSTAT_TXLENGTH(x) ((x) << TXSTAT_TXLENGTH_SHIFT)
54
55#define ET_TXSTAT_OWNER 0x8000 /* NIC owns descriptor */
56#define ET_TXSTAT_COLLMASK 0x1f00 /* collisions */
57#define ET_TXSTAT_DEFERRING 0x0080 /* deferring due to jabber */
58#define ET_TXSTAT_OOWCOLL 0x0040 /* out of window collision */
59#define ET_TXSTAT_CDHB 0x0020 /* collision detect heartbeat */
60#define ET_TXSTAT_UNDERRUN 0x0010 /* DMA underrun */
61#define ET_TXSTAT_CARSENSELOST 0x0008 /* carrier lost */
62#define ET_TXSTAT_TXWITHCOLL 0x0004 /* encountered collisions during tx */
63#define ET_TXSTAT_NONDEFERRED 0x0002 /* transmitted without deferring */
64#define ET_TXSTAT_PACKETTX 0x0001 /* packet transmitted successfully */
65
66#define TXSTAT_COLLISIONS(x) (((x) & ET_TXSTAT_COLLMASK) >> 8)
67
68/* et_control */
69#define TXCTL_BUFLENGTH_MASK 0x0000ffff /* buf length in lower 16bits */
70#define TXCTL_BUFLENGTH(x) ((x) & TXCTL_BUFLENGTH_MASK)
71
72#define ET_TXCTL_LASTDESC 0x00100000 /* last descriptor in frame */
73#define ET_TXCTL_NOCRC 0x00080000 /* disable CRC generation */
74#define ET_TXCTL_IAF 0x00040000 /* interrupt after frame */
75#define ET_TXCTL_LFFORM 0x00020000 /* alternate fraglist format */
76#define ET_TXCTL_FRAGLIST 0x00010000 /* descriptor points to fraglist */
77
78/*
79 * EPIC receive descriptor. Must be 4-byte aligned.
80 */
81struct epic_rxdesc {
82 volatile uint32_t er_rxstatus; /* receive status; see below */
83 volatile uint32_t er_bufaddr; /* buffer address */
84 volatile uint32_t er_control; /* control word; see below */
85 volatile uint32_t er_nextdesc; /* next descriptor pointer */
86};
87
88/* er_rxstatus */
89#define RXSTAT_RXLENGTH_SHIFT 16 /* TX length in higher 16bits */
90#define RXSTAT_RXLENGTH(x) ((x) >> RXSTAT_RXLENGTH_SHIFT)
91
92#define ER_RXSTAT_OWNER 0x8000 /* NIC owns descriptor */
93#define ER_RXSTAT_HDRCOPIED 0x4000 /* rx status posted after hdr copy */
94#define ER_RXSTAT_FRAGLISTERR 0x2000 /* ran out of frags to copy frame */
95#define ER_RXSTAT_NETSTATVALID 0x1000 /* length and status are valid */
96#define ER_RXSTAT_RCVRDIS 0x0040 /* receiver disabled */
97#define ER_RXSTAT_BCAST 0x0020 /* broadcast address recognized */
98#define ER_RXSTAT_MCAST 0x0010 /* multicast address recognized */
99#define ER_RXSTAT_MISSEDPKT 0x0008 /* missed packet */
100#define ER_RXSTAT_CRCERROR 0x0004 /* EPIC or MII asserted CRC error */
101#define ER_RXSTAT_ALIGNERROR 0x0002 /* frame not byte-aligned */
102#define ER_RXSTAT_PKTINTACT 0x0001 /* packet received without error */
103
104/* er_control */
105#define RXCTL_BUFLENGTH_MASK 0x0000ffff /* buf length in lower 16bits */
106#define RXCTL_BUFLENGTH(x) ((x) & RXCTL_BUFLENGTH_MASK)
107
108#define ER_RXCTL_HEADER 0x00040000 /* descriptor is for hdr copy */
109#define ER_RXCTL_LFFORM 0x00020000 /* alternate fraglist format */
110#define ER_RXCTL_FRAGLIST 0x00010000 /* descriptor points to fraglist */
111
112/*
113 * This is not really part of the register description, but we need
114 * to define the number of transmit fragments *somewhere*.
115 */
116#define EPIC_NFRAGS 16 /* maximum number of frags in list */
117
118/*
119 * EPIC fraglist descriptor.
120 */
121struct epic_fraglist {
122 volatile uint32_t ef_nfrags; /* number of frags in list */
123 struct {
124 volatile uint32_t ef_addr; /* address of frag */
125 volatile uint32_t ef_length; /* length of frag */
126 } ef_frags[EPIC_NFRAGS];
127};
128
129/*
130 * EPIC control registers.
131 */
132
133#define EPIC_COMMAND 0x00 /* COMMAND */
134#define COMMAND_TXUGO 0x00000080 /* start tx after underrun */
135#define COMMAND_STOP_RDMA 0x00000040 /* stop rx dma */
136#define COMMAND_STOP_TDMA 0x00000020 /* stop tx dma */
137#define COMMAND_NEXTFRAME 0x00000010 /* move onto next rx frame */
138#define COMMAND_RXQUEUED 0x00000008 /* queue a rx descriptor */
139#define COMMAND_TXQUEUED 0x00000004 /* queue a tx descriptor */
140#define COMMAND_START_RX 0x00000002 /* start receiver */
141#define COMMAND_STOP_RX 0x00000001 /* stop receiver */
142
143#define EPIC_INTSTAT 0x04 /* INTERRUPT STATUS */
144#define INTSTAT_PTA 0x08000000 /* PCI target abort */
145#define INTSTAT_PMA 0x04000000 /* PCI master abort */
146#define INTSTAT_APE 0x02000000 /* PCI address parity error */
147#define INTSTAT_DPE 0x01000000 /* PCI data parity error */
148#define INTSTAT_RSV 0x00800000 /* rx status valid */
149#define INTSTAT_RCTS 0x00400000 /* rx copy threshold status */
150#define INTSTAT_RBE 0x00200000 /* rx buffers empty */
151#define INTSTAT_TCIP 0x00100000 /* tx copy in progress */
152#define INTSTAT_RCIP 0x00080000 /* rx copy in progress */
153#define INTSTAT_TXIDLE 0x00040000 /* transmit idle */
154#define INTSTAT_RXIDLE 0x00020000 /* receive idle */
155#define INTSTAT_INT_ACTV 0x00010000 /* interrupt active */
156#define INTSTAT_GP2_INT 0x00008000 /* gpio2 low (PHY event) */
157#define INTSTAT_FATAL_INT 0x00001000 /* fatal error occurred */
158#define INTSTAT_RCT 0x00000800 /* rx copy threshold crossed */
159#define INTSTAT_PREI 0x00000400 /* preemptive interrupt */
160#define INTSTAT_CNT 0x00000200 /* counter overflow */
161#define INTSTAT_TXU 0x00000100 /* transmit underrun */
162#define INTSTAT_TQE 0x00000080 /* transmit queue empty */
163#define INTSTAT_TCC 0x00000040 /* transmit chain complete */
164#define INTSTAT_TXC 0x00000020 /* transmit complete */
165#define INTSTAT_RXE 0x00000010 /* receive error */
166#define INTSTAT_OVW 0x00000008 /* rx buffer overflow */
167#define INTSTAT_RQE 0x00000004 /* receive queue empty */
168#define INTSTAT_HCC 0x00000002 /* header copy complete */
169#define INTSTAT_RCC 0x00000001 /* receive copy complete */
170
171#define EPIC_INTMASK 0x08 /* INTERRUPT MASK */
172 /* Bits 0-15 enable the corresponding interrupt in INTSTAT. */
173
174#define EPIC_GENCTL 0x0c /* GENERAL CONTROL */
175#define GENCTL_RESET_PHY 0x00004000 /* reset PHY */
176#define GENCTL_SOFT1 0x00002000 /* software use */
177#define GENCTL_SOFT0 0x00001000 /* software use */
178#define GENCTL_MEM_READ_CTL1 0x00000800 /* PCI memory control */
179#define GENCTL_MEM_READ_CTL0 0x00000400 /* (see below) */
180#define GENCTL_RX_FIFO_THRESH1 0x00000200 /* rx fifo thresh */
181#define GENCTL_RX_FIFO_THRESH0 0x00000100 /* (see below) */
182#define GENCTL_BIG_ENDIAN 0x00000020 /* big endian mode */
183#define GENCTL_ONECOPY 0x00000010 /* auto-NEXTFRAME */
184#define GENCTL_POWERDOWN 0x00000008 /* powersave sleep mode */
185#define GENCTL_SOFTINT 0x00000004 /* software-generated intr */
186#define GENCTL_INTENA 0x00000002 /* interrupt enable */
187#define GENCTL_SOFTRESET 0x00000001 /* initialize EPIC */
188
189/*
190 * Explanation of MEMORY READ CONTROL:
191 *
192 * These bits control which PCI command the transmit DMA will use when
193 * bursting data over the PCI bus. When CTL1 is set, the transmit DMA
194 * will use the PCI "memory read line" command. When CTL0 is set, the
195 * transmit DMA will use the PCI "memory read multiple" command. When
196 * neither bit is set, the transmit DMA will use the "memory read" command.
197 * Use of "memory read line" or "memory read multiple" may enhance
198 * performance on some systems.
199 */
200
201/*
202 * Explanation of RECEIVE FIFO THRESHOLD:
203 *
204 * Controls the level at which the PCI burst state machine begins to
205 * empty the receive FIFO. Default is "1/2 full" (0,1).
206 *
207 * 0,0 1/4 full 32 bytes
208 * 0,1 1/2 full 64 bytes
209 * 1,0 3/4 full 96 bytes
210 * 1,1 full 128 bytes
211 */
212
213#define EPIC_NVCTL 0x10 /* NON-VOLATILE CONTROL */
214#define NVCTL_IPG_DLY_MASK 0x00000780 /* interpacket delay gap */
215#define NVCTL_CB_MODE 0x00000040 /* CardBus mode */
216#define NVCTL_GPIO2 0x00000020 /* general purpose i/o */
217#define NVCTL_GPIO1 0x00000010 /* ... */
218#define NVCTL_GPOE2 0x00000008 /* general purpose output ena */
219#define NVCTL_GPOE1 0x00000004 /* ... */
220#define NVCTL_CLKRUNSUPP 0x00000002 /* clock run supported */
221#define NVCTL_ENAMEMMAP 0x00000001 /* enable memory map */
222
223#define NVCTL_IPG_DLY(x) (((x) & NVCTL_IPG_DLY_MASK) >> 7)
224
225#define EPIC_EECTL 0x14 /* EEPROM CONTROL */
226#define EECTL_EEPROMSIZE 0x00000040 /* eeprom size; see below */
227#define EECTL_EERDY 0x00000020 /* eeprom ready */
228#define EECTL_EEDO 0x00000010 /* eeprom data out (from) */
229#define EECTL_EEDI 0x00000008 /* eeprom data in (to) */
230#define EECTL_EESK 0x00000004 /* eeprom clock */
231#define EECTL_EECS 0x00000002 /* eeprom chip select */
232#define EECTL_ENABLE 0x00000001 /* eeprom enable */
233
234/*
235 * Explanation of EEPROM SIZE:
236 *
237 * Indicates the size of the serial EEPROM:
238 *
239 * 1 16x16 or 64x16
240 * 0 128x16 or 256x16
241 */
242
243/*
244 * Serial EEPROM opcodes, including start bit:
245 */
246#define EPIC_EEPROM_OPC_WRITE 0x05
247#define EPIC_EEPROM_OPC_READ 0x06
248
249#define EPIC_PBLCNT 0x18 /* PBLCNT */
250#define PBLCNT_MASK 0x0000003f /* programmable burst length */
251
252#define EPIC_TEST 0x1c /* TEST */
253#define TEST_CLOCKTEST 0x00000008
254
255#define EPIC_CRCCNT 0x20 /* CRC ERROR COUNTER */
256#define CRCCNT_MASK 0x0000000f /* crc errs since last read */
257
258#define EPIC_ALICNT 0x24 /* FRAME ALIGNMENT ERROR COUNTER */
259#define ALICNT_MASK 0x0000000f /* align errs since last read */
260
261#define EPIC_MPCNT 0x28 /* MISSED PACKET COUNTER */
262#define MPCNT_MASK 0x0000000f /* miss. pkts since last read */
263
264#define EPIC_RXFIFO 0x2c
265
266#define EPIC_MMCTL 0x30 /* MII MANAGEMENT INTERFACE CONTROL */
267#define MMCTL_PHY_ADDR_MASK 0x00003e00 /* phy address field */
268#define MMCTL_PHY_REG_ADDR_MASK 0x000001f0 /* phy register address field */
269#define MMCTL_RESPONDER 0x00000008 /* phy responder */
270#define MMCTL_WRITE 0x00000002 /* write to phy */
271#define MMCTL_READ 0x00000001 /* read from phy */
272
273#define MMCTL_ARG(phy, reg, cmd) (((phy) << 9) | ((reg) << 4) | (cmd))
274
275#define EPIC_MMDATA 0x34 /* MII MANAGEMENT INTERFACE DATA */
276#define MMDATA_MASK 0x0000ffff /* MII frame data */
277
278#define EPIC_MIICFG 0x38 /* MII CONFIGURATION */
279#define MIICFG_ALTDIR 0x00000080 /* alternate direction */
280#define MIICFG_ALTDATA 0x00000040 /* alternate data */
281#define MIICFG_ALTCLOCK 0x00000020 /* alternate clock source */
282#define MIICFG_ENASER 0x00000010 /* enable serial manag intf */
283#define MIICFG_PHYPRESENT 0x00000008 /* phy present on MII */
284#define MIICFG_LINKSTATUS 0x00000004 /* 694 link status */
285#define MIICFG_ENABLE 0x00000002 /* enable 694 */
286#define MIICFG_SERMODEENA 0x00000001 /* serial mode enable */
287
288#define EPIC_IPG 0x3c /* INTERPACKET GAP */
289#define IPG_INTERFRAME_MASK 0x00007f00 /* interframe gap time */
290#define IPG_INTERPKT_MASK 0x000000ff /* interpacket gap time */
291
292#define EPIC_LAN0 0x40 /* LAN ADDRESS */
293
294#define EPIC_LAN1 0x44
295
296#define EPIC_LAN2 0x48
297
298#define LANn_MASK 0x0000ffff
299
300/*
301 * Explanation of LAN ADDRESS registers:
302 *
303 * LAN address is described as:
304 *
305 * 0000 [n1][n0][n3][n2] | 0000 [n5][n4][n7][n6] | 0000 [n9][n8][n11][n10]
306 *
307 * n == one nibble, mapped as follows:
308 *
309 * LAN0 [15-12] n3
310 * LAN0 [11-8] n2
311 * LAN0 [7-4] n1
312 * LAN0 [3-0] n0
313 * LAN1 [15-12] n7
314 * LAN1 [11-8] n6
315 * LAN1 [7-4] n5
316 * LAN1 [3-0] n4
317 * LAN2 [15-12] n11
318 * LAN2 [11-8] n10
319 * LAN2 [7-4] n9
320 * LAN2 [3-0] n8
321 *
322 * The LAN address is automatically recalled from the EEPROM after a
323 * hard reseet.
324 */
325
326#define EPIC_IDCHK 0x4c /* BOARD ID/CHECKSUM */
327#define IDCHK_ID_MASK 0x0000ff00 /* board ID */
328#define IDCHK_CKSUM_MASK 0x000000ff /* checksum (should be 0xff) */
329
330#define EPIC_MC0 0x50 /* MULTICAST ADDRESS HASH TABLE */
331
332#define EPIC_MC1 0x54
333
334#define EPIC_MC2 0x58
335
336#define EPIC_MC3 0x5c
337
338/*
339 * Explanation of MULTICAST ADDRESS HASH TABLE registers:
340 *
341 * Bits in the hash table are encoded as follows:
342 *
343 * MC0 [15-0]
344 * MC1 [31-16]
345 * MC2 [47-32]
346 * MC3 [53-48]
347 */
348
349#define EPIC_RXCON 0x60 /* RECEIVE CONTROL */
350#define RXCON_EXTBUFSIZESEL1 0x00000200 /* ext buf size; see below */
351#define RXCON_EXTBUFSIZESEL0 0x00000100 /* ... */
352#define RXCON_EARLYRXENABLE 0x00000080 /* early receive enable */
353#define RXCON_MONITORMODE 0x00000040 /* monitor mode */
354#define RXCON_PROMISCMODE 0x00000020 /* promiscuous mode */
355#define RXCON_RXINVADDR 0x00000010 /* rx inv individual addr */
356#define RXCON_RXMULTICAST 0x00000008 /* receive multicast */
357#define RXCON_RXBROADCAST 0x00000004 /* receive broadcast */
358#define RXCON_RXRUNT 0x00000002 /* receive runt frames */
359#define RXCON_SAVEERRPKTS 0x00000001 /* save errored packets */
360
361/*
362 * Explanation of EXTERNAL BUFFER SIZE SELECT:
363 *
364 * 0,0 external buffer access is disabled
365 * 0,1 16k
366 * 1,0 32k
367 * 1,1 128k
368 */
369
370#define EPIC_RXSTAT 0x64 /* RECEIVE STATUS */
371
372#define EPIC_RXCNT 0x68
373
374#define EPIC_RXTEST 0x6c
375
376#define EPIC_TXCON 0x70 /* TRANSMIT CONTROL */
377#define TXCON_SLOTTIME_MASK 0x000000f8 /* slot time */
378#define TXCON_LOOPBACK_D2 0x00000004 /* loopback mode bit 2 */
379#define TXCON_LOOPBACK_D1 0x00000002 /* loopback mode bit 1 */
380#define TXCON_EARLYTX_ENABLE 0x00000001 /* early transmit enable */
381
382/*
383 * Explanation of LOOPBACK MODE BIT:
384 *
385 * 0,0 normal operation
386 * 0,1 internal loopback (before PHY)
387 * 1,0 external loopback (after PHY)
388 * 1,1 full duplex - decouples transmit and receive blocks
389 */
390
391#define EPIC_TXSTAT 0x74 /* TRANSMIT STATUS */
392
393#define EPIC_TDPAR 0x78
394
395#define EPIC_TXTEST 0x7c
396
397#define EPIC_PRFDAR 0x80
398
399#define EPIC_PRCDAR 0x84 /* PCI RECEIVE CURRENT DESCRIPTOR ADDR */
400
401#define EPIC_PRHDAR 0x88
402
403#define EPIC_PRFLAR 0x8c
404
405#define EPIC_PRDLGTH 0x90
406
407#define EPIC_PRFCNT 0x94
408
409#define EPIC_PRLCAR 0x98
410
411#define EPIC_PRLPAR 0x9c
412
413#define EPIC_PREFAR 0xa0
414
415#define EPIC_PRSTAT 0xa4 /* PCI RECEIVE DMA STATUS */
416
417#define EPIC_PRBUF 0xa8
418
419#define EPIC_RDNCAR 0xac
420
421#define EPIC_PRCPTHR 0xb0 /* PCI RECEIVE COPY THRESHOLD */
422
423#define EPIC_ROMDATA 0xb4
424
425#define EPIC_PREEMPR 0xbc
426
427#define EPIC_PTFDAR 0xc0
428
429#define EPIC_PTCDAR 0xc4 /* PCI TRANSMIT CURRENT DESCRIPTOR ADDR */
430
431#define EPIC_PTHDAR 0xc8
432
433#define EPIC_PTFLAR 0xcc
434
435#define EPIC_PTDLGTH 0xd0
436
437#define EPIC_PTFCNT 0xd4
438
439#define EPIC_PTLCAR 0xd8
440
441#define EPIC_ETXTHR 0xdc /* EARLY TRANSMIT THRESHOLD */
442
443#define EPIC_PTETXC 0xe0
444
445#define EPIC_PTSTAT 0xe4
446
447#define EPIC_PTBUF 0xe8
448
449#define EPIC_PTFDAR2 0xec
450
451#define EPIC_FEVTR 0xf0 /* FEVTR (CardBus) */
452
453#define EPIC_FEVTRMSKR 0xf4 /* FEVTRMSKR (CardBus) */
454
455#define EPIC_FPRSTSTR 0xf8 /* FPRSTR (CardBus) */
456
457#define EPIC_FFRCEVTR 0xfc /* PPRCEVTR (CardBus) */
458
459/*
460 * EEPROM format:
461 *
462 * Word Bits Description
463 * ---- ---- -----------
464 * 0 7-0 LAN Address Byte 0
465 * 0 15-8 LAN Address Byte 1
466 * 1 7-0 LAN Address Byte 2
467 * 1 15-8 LAN Address Byte 3
468 * 2 7-0 LAN Address Byte 4
469 * 2 15-8 LAN Address Byte 5
470 * 3 7-0 Board ID
471 * 3 15-8 Checksum
472 * 4 5-0 Non-Volatile Control Register Contents
473 * 5 7-0 PCI Minimum Grant Desired Setting
474 * 5 15-8 PCI Maximum Latency Desired Setting
475 * 6 15-0 Subsystem Vendor ID
476 * 7 14-0 Subsystem ID
477 */
478
479#endif /* _DEV_IC_SMC83C170REG_H_ */
480