1/* $NetBSD: lxtphyreg.h,v 1.2 2008/04/28 20:23:53 martin Exp $ */
2
3/*-
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#ifndef _DEV_MII_LXTPHYREG_H_
34#define _DEV_MII_LXTPHYREG_H_
35
36/*
37 * LXT970 registers.
38 */
39
40#define MII_LXTPHY_MIRROR 0x10 /* Mirror register */
41 /* All bits user-defined */
42
43#define MII_LXTPHY_IER 0x11 /* Interrupt Enable Register */
44#define IER_MIIDRVLVL 0x0008 /* Rediced MII driver levels */
45#define IER_LNK_CRITERIA 0x0004 /* Enhanced Link Loss Criteria */
46#define IER_INTEN 0x0002 /* Interrupt Enable */
47#define IER_TINT 0x0001 /* Force Interrupt */
48
49#define MII_LXTPHY_ISR 0x12 /* Interrupt Status Register */
50#define ISR_MINT 0x8000 /* MII Interrupt Pending */
51#define ISR_XTALOK 0x4000 /* Clocks OK */
52
53#define MII_LXTPHY_CONFIG 0x13 /* Configuration Register */
54#define CONFIG_TXMIT_TEST 0x4000 /* 100base-T Transmit Test */
55#define CONFIG_REPEATER 0x2000 /* Repeater Mode */
56#define CONFIG_MDIO_INT 0x1000 /* Enable intr signalling on MDIO */
57#define CONFIG_TPLOOP 0x0800 /* Disable 10base-T Loopback */
58#define CONFIG_SQE 0x0400 /* Enable SQE */
59#define CONFIG_DISJABBER 0x0200 /* Disable Jabber */
60#define CONFIG_DISLINKTEST 0x0100 /* Disable Link Test */
61#define CONFIG_LEDC1 0x0080 /* LEDC configuration */
62#define CONFIG_LEDC0 0x0040 /* ... */
63 /* 0 0 LEDC indicates collision */
64 /* 0 1 LEDC is off */
65 /* 1 0 LEDC indicates activity */
66 /* 1 1 LEDC is on */
67#define CONFIG_ADVTXCLK 0x0020 /* Advance TX clock */
68#define CONFIG_5BSYMBOL 0x0010 /* 5-bit Symbol mode */
69#define CONFIG_SCRAMBLER 0x0008 /* Bypass scrambler */
70#define CONFIG_100BASEFX 0x0004 /* 100base-FX */
71#define CONFIG_TXDISCON 0x0001 /* Disconnect TP transmitter */
72
73#define MII_LXTPHY_CSR 0x14 /* Chip Status Register */
74#define CSR_LINK 0x2000 /* Link is up */
75#define CSR_DUPLEX 0x1000 /* Full-duplex */
76#define CSR_SPEED 0x0800 /* 100Mbps */
77#define CSR_ACOMP 0x0400 /* Autonegotiation complete */
78#define CSR_PAGERCVD 0x0200 /* Link page received */
79#define CSR_LOWVCC 0x0004 /* Low Voltage Fault */
80
81#endif /* _DEV_MII_LXTPHYREG_H_ */
82