1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
25 | */ |
26 | #include <drm/drmP.h> |
27 | #include <drm/drm_crtc_helper.h> |
28 | #include <drm/radeon_drm.h> |
29 | #include <drm/drm_fixed.h> |
30 | #include "radeon.h" |
31 | #include "radeon_asic.h" |
32 | #include "atom.h" |
33 | #include "atom-bits.h" |
34 | |
35 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
36 | struct drm_display_mode *mode, |
37 | struct drm_display_mode *adjusted_mode) |
38 | { |
39 | struct drm_device *dev = crtc->dev; |
40 | struct radeon_device *rdev = dev->dev_private; |
41 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
42 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; |
43 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); |
44 | int a1, a2; |
45 | |
46 | memset(&args, 0, sizeof(args)); |
47 | |
48 | args.ucCRTC = radeon_crtc->crtc_id; |
49 | |
50 | switch (radeon_crtc->rmx_type) { |
51 | case RMX_CENTER: |
52 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
53 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
54 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); |
55 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); |
56 | break; |
57 | case RMX_ASPECT: |
58 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; |
59 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; |
60 | |
61 | if (a1 > a2) { |
62 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
63 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
64 | } else if (a2 > a1) { |
65 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
66 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
67 | } |
68 | break; |
69 | case RMX_FULL: |
70 | default: |
71 | args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); |
72 | args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); |
73 | args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); |
74 | args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); |
75 | break; |
76 | } |
77 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
78 | } |
79 | |
80 | static void atombios_scaler_setup(struct drm_crtc *crtc) |
81 | { |
82 | struct drm_device *dev = crtc->dev; |
83 | struct radeon_device *rdev = dev->dev_private; |
84 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
85 | ENABLE_SCALER_PS_ALLOCATION args; |
86 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); |
87 | struct radeon_encoder *radeon_encoder = |
88 | to_radeon_encoder(radeon_crtc->encoder); |
89 | /* fixme - fill in enc_priv for atom dac */ |
90 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
91 | bool is_tv = false, is_cv = false; |
92 | |
93 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) |
94 | return; |
95 | |
96 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
97 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
98 | tv_std = tv_dac->tv_std; |
99 | is_tv = true; |
100 | } |
101 | |
102 | memset(&args, 0, sizeof(args)); |
103 | |
104 | args.ucScaler = radeon_crtc->crtc_id; |
105 | |
106 | if (is_tv) { |
107 | switch (tv_std) { |
108 | case TV_STD_NTSC: |
109 | default: |
110 | args.ucTVStandard = ATOM_TV_NTSC; |
111 | break; |
112 | case TV_STD_PAL: |
113 | args.ucTVStandard = ATOM_TV_PAL; |
114 | break; |
115 | case TV_STD_PAL_M: |
116 | args.ucTVStandard = ATOM_TV_PALM; |
117 | break; |
118 | case TV_STD_PAL_60: |
119 | args.ucTVStandard = ATOM_TV_PAL60; |
120 | break; |
121 | case TV_STD_NTSC_J: |
122 | args.ucTVStandard = ATOM_TV_NTSCJ; |
123 | break; |
124 | case TV_STD_SCART_PAL: |
125 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ |
126 | break; |
127 | case TV_STD_SECAM: |
128 | args.ucTVStandard = ATOM_TV_SECAM; |
129 | break; |
130 | case TV_STD_PAL_CN: |
131 | args.ucTVStandard = ATOM_TV_PALCN; |
132 | break; |
133 | } |
134 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
135 | } else if (is_cv) { |
136 | args.ucTVStandard = ATOM_TV_CV; |
137 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
138 | } else { |
139 | switch (radeon_crtc->rmx_type) { |
140 | case RMX_FULL: |
141 | args.ucEnable = ATOM_SCALER_EXPANSION; |
142 | break; |
143 | case RMX_CENTER: |
144 | args.ucEnable = ATOM_SCALER_CENTER; |
145 | break; |
146 | case RMX_ASPECT: |
147 | args.ucEnable = ATOM_SCALER_EXPANSION; |
148 | break; |
149 | default: |
150 | if (ASIC_IS_AVIVO(rdev)) |
151 | args.ucEnable = ATOM_SCALER_DISABLE; |
152 | else |
153 | args.ucEnable = ATOM_SCALER_CENTER; |
154 | break; |
155 | } |
156 | } |
157 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
158 | if ((is_tv || is_cv) |
159 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { |
160 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); |
161 | } |
162 | } |
163 | |
164 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
165 | { |
166 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
167 | struct drm_device *dev = crtc->dev; |
168 | struct radeon_device *rdev = dev->dev_private; |
169 | int index = |
170 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); |
171 | ENABLE_CRTC_PS_ALLOCATION args; |
172 | |
173 | memset(&args, 0, sizeof(args)); |
174 | |
175 | args.ucCRTC = radeon_crtc->crtc_id; |
176 | args.ucEnable = lock; |
177 | |
178 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
179 | } |
180 | |
181 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) |
182 | { |
183 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
184 | struct drm_device *dev = crtc->dev; |
185 | struct radeon_device *rdev = dev->dev_private; |
186 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); |
187 | ENABLE_CRTC_PS_ALLOCATION args; |
188 | |
189 | memset(&args, 0, sizeof(args)); |
190 | |
191 | args.ucCRTC = radeon_crtc->crtc_id; |
192 | args.ucEnable = state; |
193 | |
194 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
195 | } |
196 | |
197 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) |
198 | { |
199 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
200 | struct drm_device *dev = crtc->dev; |
201 | struct radeon_device *rdev = dev->dev_private; |
202 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); |
203 | ENABLE_CRTC_PS_ALLOCATION args; |
204 | |
205 | memset(&args, 0, sizeof(args)); |
206 | |
207 | args.ucCRTC = radeon_crtc->crtc_id; |
208 | args.ucEnable = state; |
209 | |
210 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
211 | } |
212 | |
213 | static const u32 vga_control_regs[6] = |
214 | { |
215 | AVIVO_D1VGA_CONTROL, |
216 | AVIVO_D2VGA_CONTROL, |
217 | EVERGREEN_D3VGA_CONTROL, |
218 | EVERGREEN_D4VGA_CONTROL, |
219 | EVERGREEN_D5VGA_CONTROL, |
220 | EVERGREEN_D6VGA_CONTROL, |
221 | }; |
222 | |
223 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
224 | { |
225 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
226 | struct drm_device *dev = crtc->dev; |
227 | struct radeon_device *rdev = dev->dev_private; |
228 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
229 | BLANK_CRTC_PS_ALLOCATION args; |
230 | u32 vga_control = 0; |
231 | |
232 | memset(&args, 0, sizeof(args)); |
233 | |
234 | if (ASIC_IS_DCE8(rdev)) { |
235 | vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); |
236 | WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); |
237 | } |
238 | |
239 | args.ucCRTC = radeon_crtc->crtc_id; |
240 | args.ucBlanking = state; |
241 | |
242 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
243 | |
244 | if (ASIC_IS_DCE8(rdev)) { |
245 | WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); |
246 | } |
247 | } |
248 | |
249 | static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) |
250 | { |
251 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
252 | struct drm_device *dev = crtc->dev; |
253 | struct radeon_device *rdev = dev->dev_private; |
254 | int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); |
255 | ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; |
256 | |
257 | memset(&args, 0, sizeof(args)); |
258 | |
259 | args.ucDispPipeId = radeon_crtc->crtc_id; |
260 | args.ucEnable = state; |
261 | |
262 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
263 | } |
264 | |
265 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
266 | { |
267 | struct drm_device *dev = crtc->dev; |
268 | struct radeon_device *rdev = dev->dev_private; |
269 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
270 | |
271 | switch (mode) { |
272 | case DRM_MODE_DPMS_ON: |
273 | radeon_crtc->enabled = true; |
274 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
275 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
276 | atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); |
277 | atombios_blank_crtc(crtc, ATOM_DISABLE); |
278 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
279 | radeon_crtc_load_lut(crtc); |
280 | break; |
281 | case DRM_MODE_DPMS_STANDBY: |
282 | case DRM_MODE_DPMS_SUSPEND: |
283 | case DRM_MODE_DPMS_OFF: |
284 | drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
285 | if (radeon_crtc->enabled) |
286 | atombios_blank_crtc(crtc, ATOM_ENABLE); |
287 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
288 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
289 | atombios_enable_crtc(crtc, ATOM_DISABLE); |
290 | radeon_crtc->enabled = false; |
291 | break; |
292 | } |
293 | /* adjust pm to dpms */ |
294 | radeon_pm_compute_clocks(rdev); |
295 | } |
296 | |
297 | static void |
298 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
299 | struct drm_display_mode *mode) |
300 | { |
301 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
302 | struct drm_device *dev = crtc->dev; |
303 | struct radeon_device *rdev = dev->dev_private; |
304 | SET_CRTC_USING_DTD_TIMING_PARAMETERS args; |
305 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
306 | u16 misc = 0; |
307 | |
308 | memset(&args, 0, sizeof(args)); |
309 | args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); |
310 | args.usH_Blanking_Time = |
311 | cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); |
312 | args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); |
313 | args.usV_Blanking_Time = |
314 | cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); |
315 | args.usH_SyncOffset = |
316 | cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); |
317 | args.usH_SyncWidth = |
318 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
319 | args.usV_SyncOffset = |
320 | cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); |
321 | args.usV_SyncWidth = |
322 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
323 | args.ucH_Border = radeon_crtc->h_border; |
324 | args.ucV_Border = radeon_crtc->v_border; |
325 | |
326 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
327 | misc |= ATOM_VSYNC_POLARITY; |
328 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
329 | misc |= ATOM_HSYNC_POLARITY; |
330 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
331 | misc |= ATOM_COMPOSITESYNC; |
332 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
333 | misc |= ATOM_INTERLACE; |
334 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
335 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
336 | |
337 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
338 | args.ucCRTC = radeon_crtc->crtc_id; |
339 | |
340 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
341 | } |
342 | |
343 | static void atombios_crtc_set_timing(struct drm_crtc *crtc, |
344 | struct drm_display_mode *mode) |
345 | { |
346 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
347 | struct drm_device *dev = crtc->dev; |
348 | struct radeon_device *rdev = dev->dev_private; |
349 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; |
350 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
351 | u16 misc = 0; |
352 | |
353 | memset(&args, 0, sizeof(args)); |
354 | args.usH_Total = cpu_to_le16(mode->crtc_htotal); |
355 | args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); |
356 | args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); |
357 | args.usH_SyncWidth = |
358 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
359 | args.usV_Total = cpu_to_le16(mode->crtc_vtotal); |
360 | args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); |
361 | args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); |
362 | args.usV_SyncWidth = |
363 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
364 | |
365 | args.ucOverscanRight = radeon_crtc->h_border; |
366 | args.ucOverscanLeft = radeon_crtc->h_border; |
367 | args.ucOverscanBottom = radeon_crtc->v_border; |
368 | args.ucOverscanTop = radeon_crtc->v_border; |
369 | |
370 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
371 | misc |= ATOM_VSYNC_POLARITY; |
372 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
373 | misc |= ATOM_HSYNC_POLARITY; |
374 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
375 | misc |= ATOM_COMPOSITESYNC; |
376 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
377 | misc |= ATOM_INTERLACE; |
378 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
379 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
380 | |
381 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
382 | args.ucCRTC = radeon_crtc->crtc_id; |
383 | |
384 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
385 | } |
386 | |
387 | static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) |
388 | { |
389 | u32 ss_cntl; |
390 | |
391 | if (ASIC_IS_DCE4(rdev)) { |
392 | switch (pll_id) { |
393 | case ATOM_PPLL1: |
394 | ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); |
395 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
396 | WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); |
397 | break; |
398 | case ATOM_PPLL2: |
399 | ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); |
400 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
401 | WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); |
402 | break; |
403 | case ATOM_DCPLL: |
404 | case ATOM_PPLL_INVALID: |
405 | return; |
406 | } |
407 | } else if (ASIC_IS_AVIVO(rdev)) { |
408 | switch (pll_id) { |
409 | case ATOM_PPLL1: |
410 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); |
411 | ss_cntl &= ~1; |
412 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); |
413 | break; |
414 | case ATOM_PPLL2: |
415 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); |
416 | ss_cntl &= ~1; |
417 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); |
418 | break; |
419 | case ATOM_DCPLL: |
420 | case ATOM_PPLL_INVALID: |
421 | return; |
422 | } |
423 | } |
424 | } |
425 | |
426 | |
427 | union atom_enable_ss { |
428 | ENABLE_LVDS_SS_PARAMETERS lvds_ss; |
429 | ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; |
430 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; |
431 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; |
432 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; |
433 | }; |
434 | |
435 | static void atombios_crtc_program_ss(struct radeon_device *rdev, |
436 | int enable, |
437 | int pll_id, |
438 | int crtc_id, |
439 | struct radeon_atom_ss *ss) |
440 | { |
441 | unsigned i; |
442 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
443 | union atom_enable_ss args; |
444 | |
445 | if (enable) { |
446 | /* Don't mess with SS if percentage is 0 or external ss. |
447 | * SS is already disabled previously, and disabling it |
448 | * again can cause display problems if the pll is already |
449 | * programmed. |
450 | */ |
451 | if (ss->percentage == 0) |
452 | return; |
453 | if (ss->type & ATOM_EXTERNAL_SS_MASK) |
454 | return; |
455 | } else { |
456 | for (i = 0; i < rdev->num_crtc; i++) { |
457 | if (rdev->mode_info.crtcs[i] && |
458 | rdev->mode_info.crtcs[i]->enabled && |
459 | i != crtc_id && |
460 | pll_id == rdev->mode_info.crtcs[i]->pll_id) { |
461 | /* one other crtc is using this pll don't turn |
462 | * off spread spectrum as it might turn off |
463 | * display on active crtc |
464 | */ |
465 | return; |
466 | } |
467 | } |
468 | } |
469 | |
470 | memset(&args, 0, sizeof(args)); |
471 | |
472 | if (ASIC_IS_DCE5(rdev)) { |
473 | args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); |
474 | args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
475 | switch (pll_id) { |
476 | case ATOM_PPLL1: |
477 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; |
478 | break; |
479 | case ATOM_PPLL2: |
480 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; |
481 | break; |
482 | case ATOM_DCPLL: |
483 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; |
484 | break; |
485 | case ATOM_PPLL_INVALID: |
486 | return; |
487 | } |
488 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
489 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
490 | args.v3.ucEnable = enable; |
491 | } else if (ASIC_IS_DCE4(rdev)) { |
492 | args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
493 | args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
494 | switch (pll_id) { |
495 | case ATOM_PPLL1: |
496 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; |
497 | break; |
498 | case ATOM_PPLL2: |
499 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; |
500 | break; |
501 | case ATOM_DCPLL: |
502 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; |
503 | break; |
504 | case ATOM_PPLL_INVALID: |
505 | return; |
506 | } |
507 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
508 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
509 | args.v2.ucEnable = enable; |
510 | } else if (ASIC_IS_DCE3(rdev)) { |
511 | args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
512 | args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
513 | args.v1.ucSpreadSpectrumStep = ss->step; |
514 | args.v1.ucSpreadSpectrumDelay = ss->delay; |
515 | args.v1.ucSpreadSpectrumRange = ss->range; |
516 | args.v1.ucPpll = pll_id; |
517 | args.v1.ucEnable = enable; |
518 | } else if (ASIC_IS_AVIVO(rdev)) { |
519 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
520 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { |
521 | atombios_disable_ss(rdev, pll_id); |
522 | return; |
523 | } |
524 | args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
525 | args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
526 | args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; |
527 | args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; |
528 | args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; |
529 | args.lvds_ss_2.ucEnable = enable; |
530 | } else { |
531 | if (enable == ATOM_DISABLE) { |
532 | atombios_disable_ss(rdev, pll_id); |
533 | return; |
534 | } |
535 | args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
536 | args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
537 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; |
538 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; |
539 | args.lvds_ss.ucEnable = enable; |
540 | } |
541 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
542 | } |
543 | |
544 | union adjust_pixel_clock { |
545 | ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; |
546 | ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; |
547 | }; |
548 | |
549 | static u32 atombios_adjust_pll(struct drm_crtc *crtc, |
550 | struct drm_display_mode *mode) |
551 | { |
552 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
553 | struct drm_device *dev = crtc->dev; |
554 | struct radeon_device *rdev = dev->dev_private; |
555 | struct drm_encoder *encoder = radeon_crtc->encoder; |
556 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
557 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
558 | u32 adjusted_clock = mode->clock; |
559 | int encoder_mode = atombios_get_encoder_mode(encoder); |
560 | u32 dp_clock = mode->clock; |
561 | int bpc = radeon_crtc->bpc; |
562 | bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); |
563 | |
564 | /* reset the pll flags */ |
565 | radeon_crtc->pll_flags = 0; |
566 | |
567 | if (ASIC_IS_AVIVO(rdev)) { |
568 | if ((rdev->family == CHIP_RS600) || |
569 | (rdev->family == CHIP_RS690) || |
570 | (rdev->family == CHIP_RS740)) |
571 | radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ |
572 | RADEON_PLL_PREFER_CLOSEST_LOWER); |
573 | |
574 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ |
575 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
576 | else |
577 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
578 | |
579 | if (rdev->family < CHIP_RV770) |
580 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; |
581 | /* use frac fb div on APUs */ |
582 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) |
583 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
584 | /* use frac fb div on RS780/RS880 */ |
585 | if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) |
586 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
587 | if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) |
588 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
589 | } else { |
590 | radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; |
591 | |
592 | if (mode->clock > 200000) /* range limits??? */ |
593 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
594 | else |
595 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
596 | } |
597 | |
598 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
599 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { |
600 | if (connector) { |
601 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
602 | struct radeon_connector_atom_dig *dig_connector = |
603 | radeon_connector->con_priv; |
604 | |
605 | dp_clock = dig_connector->dp_clock; |
606 | } |
607 | } |
608 | |
609 | /* use recommended ref_div for ss */ |
610 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
611 | if (radeon_crtc->ss_enabled) { |
612 | if (radeon_crtc->ss.refdiv) { |
613 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
614 | radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; |
615 | if (ASIC_IS_AVIVO(rdev)) |
616 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
617 | } |
618 | } |
619 | } |
620 | |
621 | if (ASIC_IS_AVIVO(rdev)) { |
622 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ |
623 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) |
624 | adjusted_clock = mode->clock * 2; |
625 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
626 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; |
627 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
628 | radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; |
629 | } else { |
630 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
631 | radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
632 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) |
633 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
634 | } |
635 | |
636 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock |
637 | * accordingly based on the encoder/transmitter to work around |
638 | * special hw requirements. |
639 | */ |
640 | if (ASIC_IS_DCE3(rdev)) { |
641 | union adjust_pixel_clock args; |
642 | u8 frev, crev; |
643 | int index; |
644 | |
645 | index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); |
646 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
647 | &crev)) |
648 | return adjusted_clock; |
649 | |
650 | memset(&args, 0, sizeof(args)); |
651 | |
652 | switch (frev) { |
653 | case 1: |
654 | switch (crev) { |
655 | case 1: |
656 | case 2: |
657 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); |
658 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; |
659 | args.v1.ucEncodeMode = encoder_mode; |
660 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
661 | args.v1.ucConfig |= |
662 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; |
663 | |
664 | atom_execute_table(rdev->mode_info.atom_context, |
665 | index, (uint32_t *)&args); |
666 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; |
667 | break; |
668 | case 3: |
669 | args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); |
670 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; |
671 | args.v3.sInput.ucEncodeMode = encoder_mode; |
672 | args.v3.sInput.ucDispPllConfig = 0; |
673 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
674 | args.v3.sInput.ucDispPllConfig |= |
675 | DISPPLL_CONFIG_SS_ENABLE; |
676 | if (ENCODER_MODE_IS_DP(encoder_mode)) { |
677 | args.v3.sInput.ucDispPllConfig |= |
678 | DISPPLL_CONFIG_COHERENT_MODE; |
679 | /* 16200 or 27000 */ |
680 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); |
681 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
682 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
683 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) |
684 | /* deep color support */ |
685 | args.v3.sInput.usPixelClock = |
686 | cpu_to_le16((mode->clock * bpc / 8) / 10); |
687 | if (dig->coherent_mode) |
688 | args.v3.sInput.ucDispPllConfig |= |
689 | DISPPLL_CONFIG_COHERENT_MODE; |
690 | if (is_duallink) |
691 | args.v3.sInput.ucDispPllConfig |= |
692 | DISPPLL_CONFIG_DUAL_LINK; |
693 | } |
694 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != |
695 | ENCODER_OBJECT_ID_NONE) |
696 | args.v3.sInput.ucExtTransmitterID = |
697 | radeon_encoder_get_dp_bridge_encoder_id(encoder); |
698 | else |
699 | args.v3.sInput.ucExtTransmitterID = 0; |
700 | |
701 | atom_execute_table(rdev->mode_info.atom_context, |
702 | index, (uint32_t *)&args); |
703 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; |
704 | if (args.v3.sOutput.ucRefDiv) { |
705 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
706 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
707 | radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; |
708 | } |
709 | if (args.v3.sOutput.ucPostDiv) { |
710 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
711 | radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; |
712 | radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; |
713 | } |
714 | break; |
715 | default: |
716 | DRM_ERROR("Unknown table version %d %d\n" , frev, crev); |
717 | return adjusted_clock; |
718 | } |
719 | break; |
720 | default: |
721 | DRM_ERROR("Unknown table version %d %d\n" , frev, crev); |
722 | return adjusted_clock; |
723 | } |
724 | } |
725 | return adjusted_clock; |
726 | } |
727 | |
728 | union set_pixel_clock { |
729 | SET_PIXEL_CLOCK_PS_ALLOCATION base; |
730 | PIXEL_CLOCK_PARAMETERS v1; |
731 | PIXEL_CLOCK_PARAMETERS_V2 v2; |
732 | PIXEL_CLOCK_PARAMETERS_V3 v3; |
733 | PIXEL_CLOCK_PARAMETERS_V5 v5; |
734 | PIXEL_CLOCK_PARAMETERS_V6 v6; |
735 | }; |
736 | |
737 | /* on DCE5, make sure the voltage is high enough to support the |
738 | * required disp clk. |
739 | */ |
740 | static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, |
741 | u32 dispclk) |
742 | { |
743 | u8 frev, crev; |
744 | int index; |
745 | union set_pixel_clock args; |
746 | |
747 | memset(&args, 0, sizeof(args)); |
748 | |
749 | index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
750 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
751 | &crev)) |
752 | return; |
753 | |
754 | switch (frev) { |
755 | case 1: |
756 | switch (crev) { |
757 | case 5: |
758 | /* if the default dcpll clock is specified, |
759 | * SetPixelClock provides the dividers |
760 | */ |
761 | args.v5.ucCRTC = ATOM_CRTC_INVALID; |
762 | args.v5.usPixelClock = cpu_to_le16(dispclk); |
763 | args.v5.ucPpll = ATOM_DCPLL; |
764 | break; |
765 | case 6: |
766 | /* if the default dcpll clock is specified, |
767 | * SetPixelClock provides the dividers |
768 | */ |
769 | args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); |
770 | if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) |
771 | args.v6.ucPpll = ATOM_EXT_PLL1; |
772 | else if (ASIC_IS_DCE6(rdev)) |
773 | args.v6.ucPpll = ATOM_PPLL0; |
774 | else |
775 | args.v6.ucPpll = ATOM_DCPLL; |
776 | break; |
777 | default: |
778 | DRM_ERROR("Unknown table version %d %d\n" , frev, crev); |
779 | return; |
780 | } |
781 | break; |
782 | default: |
783 | DRM_ERROR("Unknown table version %d %d\n" , frev, crev); |
784 | return; |
785 | } |
786 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
787 | } |
788 | |
789 | static void atombios_crtc_program_pll(struct drm_crtc *crtc, |
790 | u32 crtc_id, |
791 | int pll_id, |
792 | u32 encoder_mode, |
793 | u32 encoder_id, |
794 | u32 clock, |
795 | u32 ref_div, |
796 | u32 fb_div, |
797 | u32 frac_fb_div, |
798 | u32 post_div, |
799 | int bpc, |
800 | bool ss_enabled, |
801 | struct radeon_atom_ss *ss) |
802 | { |
803 | struct drm_device *dev = crtc->dev; |
804 | struct radeon_device *rdev = dev->dev_private; |
805 | u8 frev, crev; |
806 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
807 | union set_pixel_clock args; |
808 | |
809 | memset(&args, 0, sizeof(args)); |
810 | |
811 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
812 | &crev)) |
813 | return; |
814 | |
815 | switch (frev) { |
816 | case 1: |
817 | switch (crev) { |
818 | case 1: |
819 | if (clock == ATOM_DISABLE) |
820 | return; |
821 | args.v1.usPixelClock = cpu_to_le16(clock / 10); |
822 | args.v1.usRefDiv = cpu_to_le16(ref_div); |
823 | args.v1.usFbDiv = cpu_to_le16(fb_div); |
824 | args.v1.ucFracFbDiv = frac_fb_div; |
825 | args.v1.ucPostDiv = post_div; |
826 | args.v1.ucPpll = pll_id; |
827 | args.v1.ucCRTC = crtc_id; |
828 | args.v1.ucRefDivSrc = 1; |
829 | break; |
830 | case 2: |
831 | args.v2.usPixelClock = cpu_to_le16(clock / 10); |
832 | args.v2.usRefDiv = cpu_to_le16(ref_div); |
833 | args.v2.usFbDiv = cpu_to_le16(fb_div); |
834 | args.v2.ucFracFbDiv = frac_fb_div; |
835 | args.v2.ucPostDiv = post_div; |
836 | args.v2.ucPpll = pll_id; |
837 | args.v2.ucCRTC = crtc_id; |
838 | args.v2.ucRefDivSrc = 1; |
839 | break; |
840 | case 3: |
841 | args.v3.usPixelClock = cpu_to_le16(clock / 10); |
842 | args.v3.usRefDiv = cpu_to_le16(ref_div); |
843 | args.v3.usFbDiv = cpu_to_le16(fb_div); |
844 | args.v3.ucFracFbDiv = frac_fb_div; |
845 | args.v3.ucPostDiv = post_div; |
846 | args.v3.ucPpll = pll_id; |
847 | if (crtc_id == ATOM_CRTC2) |
848 | args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; |
849 | else |
850 | args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; |
851 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
852 | args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; |
853 | args.v3.ucTransmitterId = encoder_id; |
854 | args.v3.ucEncoderMode = encoder_mode; |
855 | break; |
856 | case 5: |
857 | args.v5.ucCRTC = crtc_id; |
858 | args.v5.usPixelClock = cpu_to_le16(clock / 10); |
859 | args.v5.ucRefDiv = ref_div; |
860 | args.v5.usFbDiv = cpu_to_le16(fb_div); |
861 | args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
862 | args.v5.ucPostDiv = post_div; |
863 | args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ |
864 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
865 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; |
866 | switch (bpc) { |
867 | case 8: |
868 | default: |
869 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; |
870 | break; |
871 | case 10: |
872 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; |
873 | break; |
874 | } |
875 | args.v5.ucTransmitterID = encoder_id; |
876 | args.v5.ucEncoderMode = encoder_mode; |
877 | args.v5.ucPpll = pll_id; |
878 | break; |
879 | case 6: |
880 | args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); |
881 | args.v6.ucRefDiv = ref_div; |
882 | args.v6.usFbDiv = cpu_to_le16(fb_div); |
883 | args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
884 | args.v6.ucPostDiv = post_div; |
885 | args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ |
886 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
887 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; |
888 | switch (bpc) { |
889 | case 8: |
890 | default: |
891 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; |
892 | break; |
893 | case 10: |
894 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; |
895 | break; |
896 | case 12: |
897 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; |
898 | break; |
899 | case 16: |
900 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; |
901 | break; |
902 | } |
903 | args.v6.ucTransmitterID = encoder_id; |
904 | args.v6.ucEncoderMode = encoder_mode; |
905 | args.v6.ucPpll = pll_id; |
906 | break; |
907 | default: |
908 | DRM_ERROR("Unknown table version %d %d\n" , frev, crev); |
909 | return; |
910 | } |
911 | break; |
912 | default: |
913 | DRM_ERROR("Unknown table version %d %d\n" , frev, crev); |
914 | return; |
915 | } |
916 | |
917 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
918 | } |
919 | |
920 | static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
921 | { |
922 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
923 | struct drm_device *dev = crtc->dev; |
924 | struct radeon_device *rdev = dev->dev_private; |
925 | struct radeon_encoder *radeon_encoder = |
926 | to_radeon_encoder(radeon_crtc->encoder); |
927 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); |
928 | |
929 | radeon_crtc->bpc = 8; |
930 | radeon_crtc->ss_enabled = false; |
931 | |
932 | if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
933 | (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { |
934 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
935 | struct drm_connector *connector = |
936 | radeon_get_connector_for_encoder(radeon_crtc->encoder); |
937 | struct radeon_connector *radeon_connector = |
938 | to_radeon_connector(connector); |
939 | struct radeon_connector_atom_dig *dig_connector = |
940 | radeon_connector->con_priv; |
941 | int dp_clock; |
942 | radeon_crtc->bpc = radeon_get_monitor_bpc(connector); |
943 | |
944 | switch (encoder_mode) { |
945 | case ATOM_ENCODER_MODE_DP_MST: |
946 | case ATOM_ENCODER_MODE_DP: |
947 | /* DP/eDP */ |
948 | dp_clock = dig_connector->dp_clock / 10; |
949 | if (ASIC_IS_DCE4(rdev)) |
950 | radeon_crtc->ss_enabled = |
951 | radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, |
952 | ASIC_INTERNAL_SS_ON_DP, |
953 | dp_clock); |
954 | else { |
955 | if (dp_clock == 16200) { |
956 | radeon_crtc->ss_enabled = |
957 | radeon_atombios_get_ppll_ss_info(rdev, |
958 | &radeon_crtc->ss, |
959 | ATOM_DP_SS_ID2); |
960 | if (!radeon_crtc->ss_enabled) |
961 | radeon_crtc->ss_enabled = |
962 | radeon_atombios_get_ppll_ss_info(rdev, |
963 | &radeon_crtc->ss, |
964 | ATOM_DP_SS_ID1); |
965 | } else { |
966 | radeon_crtc->ss_enabled = |
967 | radeon_atombios_get_ppll_ss_info(rdev, |
968 | &radeon_crtc->ss, |
969 | ATOM_DP_SS_ID1); |
970 | } |
971 | /* disable spread spectrum on DCE3 DP */ |
972 | radeon_crtc->ss_enabled = false; |
973 | } |
974 | break; |
975 | case ATOM_ENCODER_MODE_LVDS: |
976 | if (ASIC_IS_DCE4(rdev)) |
977 | radeon_crtc->ss_enabled = |
978 | radeon_atombios_get_asic_ss_info(rdev, |
979 | &radeon_crtc->ss, |
980 | dig->lcd_ss_id, |
981 | mode->clock / 10); |
982 | else |
983 | radeon_crtc->ss_enabled = |
984 | radeon_atombios_get_ppll_ss_info(rdev, |
985 | &radeon_crtc->ss, |
986 | dig->lcd_ss_id); |
987 | break; |
988 | case ATOM_ENCODER_MODE_DVI: |
989 | if (ASIC_IS_DCE4(rdev)) |
990 | radeon_crtc->ss_enabled = |
991 | radeon_atombios_get_asic_ss_info(rdev, |
992 | &radeon_crtc->ss, |
993 | ASIC_INTERNAL_SS_ON_TMDS, |
994 | mode->clock / 10); |
995 | break; |
996 | case ATOM_ENCODER_MODE_HDMI: |
997 | if (ASIC_IS_DCE4(rdev)) |
998 | radeon_crtc->ss_enabled = |
999 | radeon_atombios_get_asic_ss_info(rdev, |
1000 | &radeon_crtc->ss, |
1001 | ASIC_INTERNAL_SS_ON_HDMI, |
1002 | mode->clock / 10); |
1003 | break; |
1004 | default: |
1005 | break; |
1006 | } |
1007 | } |
1008 | |
1009 | /* adjust pixel clock as needed */ |
1010 | radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); |
1011 | |
1012 | return true; |
1013 | } |
1014 | |
1015 | static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
1016 | { |
1017 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1018 | struct drm_device *dev = crtc->dev; |
1019 | struct radeon_device *rdev = dev->dev_private; |
1020 | struct radeon_encoder *radeon_encoder = |
1021 | to_radeon_encoder(radeon_crtc->encoder); |
1022 | u32 pll_clock = mode->clock; |
1023 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
1024 | struct radeon_pll *pll; |
1025 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); |
1026 | |
1027 | switch (radeon_crtc->pll_id) { |
1028 | case ATOM_PPLL1: |
1029 | pll = &rdev->clock.p1pll; |
1030 | break; |
1031 | case ATOM_PPLL2: |
1032 | pll = &rdev->clock.p2pll; |
1033 | break; |
1034 | case ATOM_DCPLL: |
1035 | case ATOM_PPLL_INVALID: |
1036 | default: |
1037 | pll = &rdev->clock.dcpll; |
1038 | break; |
1039 | } |
1040 | |
1041 | /* update pll params */ |
1042 | pll->flags = radeon_crtc->pll_flags; |
1043 | pll->reference_div = radeon_crtc->pll_reference_div; |
1044 | pll->post_div = radeon_crtc->pll_post_div; |
1045 | |
1046 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1047 | /* TV seems to prefer the legacy algo on some boards */ |
1048 | radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1049 | &fb_div, &frac_fb_div, &ref_div, &post_div); |
1050 | else if (ASIC_IS_AVIVO(rdev)) |
1051 | radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1052 | &fb_div, &frac_fb_div, &ref_div, &post_div); |
1053 | else |
1054 | radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1055 | &fb_div, &frac_fb_div, &ref_div, &post_div); |
1056 | |
1057 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, |
1058 | radeon_crtc->crtc_id, &radeon_crtc->ss); |
1059 | |
1060 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
1061 | encoder_mode, radeon_encoder->encoder_id, mode->clock, |
1062 | ref_div, fb_div, frac_fb_div, post_div, |
1063 | radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); |
1064 | |
1065 | if (radeon_crtc->ss_enabled) { |
1066 | /* calculate ss amount and step size */ |
1067 | if (ASIC_IS_DCE4(rdev)) { |
1068 | u32 step_size; |
1069 | u32 amount = (((fb_div * 10) + frac_fb_div) * |
1070 | (u32)radeon_crtc->ss.percentage) / |
1071 | (100 * (u32)radeon_crtc->ss.percentage_divider); |
1072 | radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; |
1073 | radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & |
1074 | ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; |
1075 | if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) |
1076 | step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / |
1077 | (125 * 25 * pll->reference_freq / 100); |
1078 | else |
1079 | step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / |
1080 | (125 * 25 * pll->reference_freq / 100); |
1081 | radeon_crtc->ss.step = step_size; |
1082 | } |
1083 | |
1084 | atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, |
1085 | radeon_crtc->crtc_id, &radeon_crtc->ss); |
1086 | } |
1087 | } |
1088 | |
1089 | static int dce4_crtc_do_set_base(struct drm_crtc *crtc, |
1090 | struct drm_framebuffer *fb, |
1091 | int x, int y, int atomic) |
1092 | { |
1093 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1094 | struct drm_device *dev = crtc->dev; |
1095 | struct radeon_device *rdev = dev->dev_private; |
1096 | struct radeon_framebuffer *radeon_fb; |
1097 | struct drm_framebuffer *target_fb; |
1098 | struct drm_gem_object *obj; |
1099 | struct radeon_bo *rbo; |
1100 | uint64_t fb_location; |
1101 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
1102 | unsigned bankw, bankh, mtaspect, tile_split; |
1103 | u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); |
1104 | u32 tmp, viewport_w, viewport_h; |
1105 | int r; |
1106 | |
1107 | /* no fb bound */ |
1108 | if (!atomic && !crtc->primary->fb) { |
1109 | DRM_DEBUG_KMS("No FB bound\n" ); |
1110 | return 0; |
1111 | } |
1112 | |
1113 | if (atomic) { |
1114 | radeon_fb = to_radeon_framebuffer(fb); |
1115 | target_fb = fb; |
1116 | } |
1117 | else { |
1118 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
1119 | target_fb = crtc->primary->fb; |
1120 | } |
1121 | |
1122 | /* If atomic, assume fb object is pinned & idle & fenced and |
1123 | * just update base pointers |
1124 | */ |
1125 | obj = radeon_fb->obj; |
1126 | rbo = gem_to_radeon_bo(obj); |
1127 | |
1128 | if (atomic) { |
1129 | BUG_ON(rbo->pin_count == 0); |
1130 | fb_location = radeon_bo_gpu_offset(rbo); |
1131 | tiling_flags = 0; |
1132 | } else { |
1133 | r = radeon_bo_reserve(rbo, false); |
1134 | if (unlikely(r != 0)) |
1135 | return r; |
1136 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
1137 | if (unlikely(r != 0)) { |
1138 | radeon_bo_unreserve(rbo); |
1139 | return -EINVAL; |
1140 | } |
1141 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1142 | radeon_bo_unreserve(rbo); |
1143 | } |
1144 | |
1145 | switch (target_fb->bits_per_pixel) { |
1146 | case 8: |
1147 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | |
1148 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); |
1149 | break; |
1150 | case 15: |
1151 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1152 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); |
1153 | break; |
1154 | case 16: |
1155 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
1156 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); |
1157 | #ifdef __BIG_ENDIAN |
1158 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
1159 | #endif |
1160 | break; |
1161 | case 24: |
1162 | case 32: |
1163 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
1164 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); |
1165 | #ifdef __BIG_ENDIAN |
1166 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
1167 | #endif |
1168 | break; |
1169 | default: |
1170 | DRM_ERROR("Unsupported screen depth %d\n" , |
1171 | target_fb->bits_per_pixel); |
1172 | return -EINVAL; |
1173 | } |
1174 | |
1175 | if (tiling_flags & RADEON_TILING_MACRO) { |
1176 | evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); |
1177 | |
1178 | /* Set NUM_BANKS. */ |
1179 | if (rdev->family >= CHIP_TAHITI) { |
1180 | unsigned index, num_banks; |
1181 | |
1182 | if (rdev->family >= CHIP_BONAIRE) { |
1183 | unsigned tileb, tile_split_bytes; |
1184 | |
1185 | /* Calculate the macrotile mode index. */ |
1186 | tile_split_bytes = 64 << tile_split; |
1187 | tileb = 8 * 8 * target_fb->bits_per_pixel / 8; |
1188 | tileb = min(tile_split_bytes, tileb); |
1189 | |
1190 | for (index = 0; tileb > 64; index++) |
1191 | tileb >>= 1; |
1192 | |
1193 | if (index >= 16) { |
1194 | DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n" , |
1195 | target_fb->bits_per_pixel, tile_split); |
1196 | return -EINVAL; |
1197 | } |
1198 | |
1199 | num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; |
1200 | } else { |
1201 | switch (target_fb->bits_per_pixel) { |
1202 | case 8: |
1203 | index = 10; |
1204 | break; |
1205 | case 16: |
1206 | index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP; |
1207 | break; |
1208 | default: |
1209 | case 32: |
1210 | index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP; |
1211 | break; |
1212 | } |
1213 | |
1214 | num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; |
1215 | } |
1216 | |
1217 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); |
1218 | } else { |
1219 | /* NI and older. */ |
1220 | if (rdev->family >= CHIP_CAYMAN) |
1221 | tmp = rdev->config.cayman.tile_config; |
1222 | else |
1223 | tmp = rdev->config.evergreen.tile_config; |
1224 | |
1225 | switch ((tmp & 0xf0) >> 4) { |
1226 | case 0: /* 4 banks */ |
1227 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); |
1228 | break; |
1229 | case 1: /* 8 banks */ |
1230 | default: |
1231 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); |
1232 | break; |
1233 | case 2: /* 16 banks */ |
1234 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); |
1235 | break; |
1236 | } |
1237 | } |
1238 | |
1239 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); |
1240 | fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); |
1241 | fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); |
1242 | fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); |
1243 | fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); |
1244 | if (rdev->family >= CHIP_BONAIRE) { |
1245 | /* XXX need to know more about the surface tiling mode */ |
1246 | fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING); |
1247 | } |
1248 | } else if (tiling_flags & RADEON_TILING_MICRO) |
1249 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); |
1250 | |
1251 | if (rdev->family >= CHIP_BONAIRE) { |
1252 | /* Read the pipe config from the 2D TILED SCANOUT mode. |
1253 | * It should be the same for the other modes too, but not all |
1254 | * modes set the pipe config field. */ |
1255 | u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; |
1256 | |
1257 | fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); |
1258 | } else if ((rdev->family == CHIP_TAHITI) || |
1259 | (rdev->family == CHIP_PITCAIRN)) |
1260 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); |
1261 | else if ((rdev->family == CHIP_VERDE) || |
1262 | (rdev->family == CHIP_OLAND) || |
1263 | (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */ |
1264 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); |
1265 | |
1266 | switch (radeon_crtc->crtc_id) { |
1267 | case 0: |
1268 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
1269 | break; |
1270 | case 1: |
1271 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
1272 | break; |
1273 | case 2: |
1274 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); |
1275 | break; |
1276 | case 3: |
1277 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); |
1278 | break; |
1279 | case 4: |
1280 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); |
1281 | break; |
1282 | case 5: |
1283 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); |
1284 | break; |
1285 | default: |
1286 | break; |
1287 | } |
1288 | |
1289 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
1290 | upper_32_bits(fb_location)); |
1291 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
1292 | upper_32_bits(fb_location)); |
1293 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1294 | (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
1295 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1296 | (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
1297 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
1298 | WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
1299 | |
1300 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
1301 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
1302 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); |
1303 | WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
1304 | WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
1305 | WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); |
1306 | |
1307 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
1308 | WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1309 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
1310 | |
1311 | if (rdev->family >= CHIP_BONAIRE) |
1312 | WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
1313 | target_fb->height); |
1314 | else |
1315 | WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
1316 | target_fb->height); |
1317 | x &= ~3; |
1318 | y &= ~1; |
1319 | WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, |
1320 | (x << 16) | y); |
1321 | viewport_w = crtc->mode.hdisplay; |
1322 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; |
1323 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
1324 | (viewport_w << 16) | viewport_h); |
1325 | |
1326 | /* pageflip setup */ |
1327 | /* make sure flip is at vb rather than hb */ |
1328 | tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
1329 | tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
1330 | WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
1331 | |
1332 | /* set pageflip to happen anywhere in vblank interval */ |
1333 | WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); |
1334 | |
1335 | if (!atomic && fb && fb != crtc->primary->fb) { |
1336 | radeon_fb = to_radeon_framebuffer(fb); |
1337 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
1338 | r = radeon_bo_reserve(rbo, false); |
1339 | if (unlikely(r != 0)) |
1340 | return r; |
1341 | radeon_bo_unpin(rbo); |
1342 | radeon_bo_unreserve(rbo); |
1343 | } |
1344 | |
1345 | /* Bytes per pixel may have changed */ |
1346 | radeon_bandwidth_update(rdev); |
1347 | |
1348 | return 0; |
1349 | } |
1350 | |
1351 | static int avivo_crtc_do_set_base(struct drm_crtc *crtc, |
1352 | struct drm_framebuffer *fb, |
1353 | int x, int y, int atomic) |
1354 | { |
1355 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1356 | struct drm_device *dev = crtc->dev; |
1357 | struct radeon_device *rdev = dev->dev_private; |
1358 | struct radeon_framebuffer *radeon_fb; |
1359 | struct drm_gem_object *obj; |
1360 | struct radeon_bo *rbo; |
1361 | struct drm_framebuffer *target_fb; |
1362 | uint64_t fb_location; |
1363 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
1364 | u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; |
1365 | u32 tmp, viewport_w, viewport_h; |
1366 | int r; |
1367 | |
1368 | /* no fb bound */ |
1369 | if (!atomic && !crtc->primary->fb) { |
1370 | DRM_DEBUG_KMS("No FB bound\n" ); |
1371 | return 0; |
1372 | } |
1373 | |
1374 | if (atomic) { |
1375 | radeon_fb = to_radeon_framebuffer(fb); |
1376 | target_fb = fb; |
1377 | } |
1378 | else { |
1379 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
1380 | target_fb = crtc->primary->fb; |
1381 | } |
1382 | |
1383 | obj = radeon_fb->obj; |
1384 | rbo = gem_to_radeon_bo(obj); |
1385 | |
1386 | /* If atomic, assume fb object is pinned & idle & fenced and |
1387 | * just update base pointers |
1388 | */ |
1389 | if (atomic) { |
1390 | BUG_ON(rbo->pin_count == 0); |
1391 | fb_location = radeon_bo_gpu_offset(rbo); |
1392 | tiling_flags = 0; |
1393 | } else { |
1394 | r = radeon_bo_reserve(rbo, false); |
1395 | if (unlikely(r != 0)) |
1396 | return r; |
1397 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
1398 | if (unlikely(r != 0)) { |
1399 | radeon_bo_unreserve(rbo); |
1400 | return -EINVAL; |
1401 | } |
1402 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1403 | radeon_bo_unreserve(rbo); |
1404 | } |
1405 | |
1406 | switch (target_fb->bits_per_pixel) { |
1407 | case 8: |
1408 | fb_format = |
1409 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
1410 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
1411 | break; |
1412 | case 15: |
1413 | fb_format = |
1414 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
1415 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
1416 | break; |
1417 | case 16: |
1418 | fb_format = |
1419 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
1420 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
1421 | #ifdef __BIG_ENDIAN |
1422 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
1423 | #endif |
1424 | break; |
1425 | case 24: |
1426 | case 32: |
1427 | fb_format = |
1428 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
1429 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
1430 | #ifdef __BIG_ENDIAN |
1431 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; |
1432 | #endif |
1433 | break; |
1434 | default: |
1435 | DRM_ERROR("Unsupported screen depth %d\n" , |
1436 | target_fb->bits_per_pixel); |
1437 | return -EINVAL; |
1438 | } |
1439 | |
1440 | if (rdev->family >= CHIP_R600) { |
1441 | if (tiling_flags & RADEON_TILING_MACRO) |
1442 | fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; |
1443 | else if (tiling_flags & RADEON_TILING_MICRO) |
1444 | fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; |
1445 | } else { |
1446 | if (tiling_flags & RADEON_TILING_MACRO) |
1447 | fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; |
1448 | |
1449 | if (tiling_flags & RADEON_TILING_MICRO) |
1450 | fb_format |= AVIVO_D1GRPH_TILED; |
1451 | } |
1452 | |
1453 | if (radeon_crtc->crtc_id == 0) |
1454 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
1455 | else |
1456 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
1457 | |
1458 | if (rdev->family >= CHIP_RV770) { |
1459 | if (radeon_crtc->crtc_id) { |
1460 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1461 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1462 | } else { |
1463 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1464 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1465 | } |
1466 | } |
1467 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1468 | (u32) fb_location); |
1469 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + |
1470 | radeon_crtc->crtc_offset, (u32) fb_location); |
1471 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
1472 | if (rdev->family >= CHIP_R600) |
1473 | WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
1474 | |
1475 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
1476 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
1477 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
1478 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
1479 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
1480 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); |
1481 | |
1482 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
1483 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1484 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
1485 | |
1486 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
1487 | target_fb->height); |
1488 | x &= ~3; |
1489 | y &= ~1; |
1490 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, |
1491 | (x << 16) | y); |
1492 | viewport_w = crtc->mode.hdisplay; |
1493 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; |
1494 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
1495 | (viewport_w << 16) | viewport_h); |
1496 | |
1497 | /* pageflip setup */ |
1498 | /* make sure flip is at vb rather than hb */ |
1499 | tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
1500 | tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
1501 | WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
1502 | |
1503 | /* set pageflip to happen anywhere in vblank interval */ |
1504 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); |
1505 | |
1506 | if (!atomic && fb && fb != crtc->primary->fb) { |
1507 | radeon_fb = to_radeon_framebuffer(fb); |
1508 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
1509 | r = radeon_bo_reserve(rbo, false); |
1510 | if (unlikely(r != 0)) |
1511 | return r; |
1512 | radeon_bo_unpin(rbo); |
1513 | radeon_bo_unreserve(rbo); |
1514 | } |
1515 | |
1516 | /* Bytes per pixel may have changed */ |
1517 | radeon_bandwidth_update(rdev); |
1518 | |
1519 | return 0; |
1520 | } |
1521 | |
1522 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
1523 | struct drm_framebuffer *old_fb) |
1524 | { |
1525 | struct drm_device *dev = crtc->dev; |
1526 | struct radeon_device *rdev = dev->dev_private; |
1527 | |
1528 | if (ASIC_IS_DCE4(rdev)) |
1529 | return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); |
1530 | else if (ASIC_IS_AVIVO(rdev)) |
1531 | return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); |
1532 | else |
1533 | return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); |
1534 | } |
1535 | |
1536 | int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
1537 | struct drm_framebuffer *fb, |
1538 | int x, int y, enum mode_set_atomic state) |
1539 | { |
1540 | struct drm_device *dev = crtc->dev; |
1541 | struct radeon_device *rdev = dev->dev_private; |
1542 | |
1543 | if (ASIC_IS_DCE4(rdev)) |
1544 | return dce4_crtc_do_set_base(crtc, fb, x, y, 1); |
1545 | else if (ASIC_IS_AVIVO(rdev)) |
1546 | return avivo_crtc_do_set_base(crtc, fb, x, y, 1); |
1547 | else |
1548 | return radeon_crtc_do_set_base(crtc, fb, x, y, 1); |
1549 | } |
1550 | |
1551 | /* properly set additional regs when using atombios */ |
1552 | static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) |
1553 | { |
1554 | struct drm_device *dev = crtc->dev; |
1555 | struct radeon_device *rdev = dev->dev_private; |
1556 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1557 | u32 disp_merge_cntl; |
1558 | |
1559 | switch (radeon_crtc->crtc_id) { |
1560 | case 0: |
1561 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
1562 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
1563 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
1564 | break; |
1565 | case 1: |
1566 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
1567 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
1568 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); |
1569 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); |
1570 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); |
1571 | break; |
1572 | } |
1573 | } |
1574 | |
1575 | /** |
1576 | * radeon_get_pll_use_mask - look up a mask of which pplls are in use |
1577 | * |
1578 | * @crtc: drm crtc |
1579 | * |
1580 | * Returns the mask of which PPLLs (Pixel PLLs) are in use. |
1581 | */ |
1582 | static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) |
1583 | { |
1584 | struct drm_device *dev = crtc->dev; |
1585 | struct drm_crtc *test_crtc; |
1586 | struct radeon_crtc *test_radeon_crtc; |
1587 | u32 pll_in_use = 0; |
1588 | |
1589 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
1590 | if (crtc == test_crtc) |
1591 | continue; |
1592 | |
1593 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
1594 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
1595 | pll_in_use |= (1 << test_radeon_crtc->pll_id); |
1596 | } |
1597 | return pll_in_use; |
1598 | } |
1599 | |
1600 | /** |
1601 | * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP |
1602 | * |
1603 | * @crtc: drm crtc |
1604 | * |
1605 | * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is |
1606 | * also in DP mode. For DP, a single PPLL can be used for all DP |
1607 | * crtcs/encoders. |
1608 | */ |
1609 | static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) |
1610 | { |
1611 | struct drm_device *dev = crtc->dev; |
1612 | struct drm_crtc *test_crtc; |
1613 | struct radeon_crtc *test_radeon_crtc; |
1614 | |
1615 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
1616 | if (crtc == test_crtc) |
1617 | continue; |
1618 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
1619 | if (test_radeon_crtc->encoder && |
1620 | ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { |
1621 | /* for DP use the same PLL for all */ |
1622 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
1623 | return test_radeon_crtc->pll_id; |
1624 | } |
1625 | } |
1626 | return ATOM_PPLL_INVALID; |
1627 | } |
1628 | |
1629 | /** |
1630 | * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc |
1631 | * |
1632 | * @crtc: drm crtc |
1633 | * @encoder: drm encoder |
1634 | * |
1635 | * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can |
1636 | * be shared (i.e., same clock). |
1637 | */ |
1638 | static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) |
1639 | { |
1640 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1641 | struct drm_device *dev = crtc->dev; |
1642 | struct drm_crtc *test_crtc; |
1643 | struct radeon_crtc *test_radeon_crtc; |
1644 | u32 adjusted_clock, test_adjusted_clock; |
1645 | |
1646 | adjusted_clock = radeon_crtc->adjusted_clock; |
1647 | |
1648 | if (adjusted_clock == 0) |
1649 | return ATOM_PPLL_INVALID; |
1650 | |
1651 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
1652 | if (crtc == test_crtc) |
1653 | continue; |
1654 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
1655 | if (test_radeon_crtc->encoder && |
1656 | !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { |
1657 | /* check if we are already driving this connector with another crtc */ |
1658 | if (test_radeon_crtc->connector == radeon_crtc->connector) { |
1659 | /* if we are, return that pll */ |
1660 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
1661 | return test_radeon_crtc->pll_id; |
1662 | } |
1663 | /* for non-DP check the clock */ |
1664 | test_adjusted_clock = test_radeon_crtc->adjusted_clock; |
1665 | if ((crtc->mode.clock == test_crtc->mode.clock) && |
1666 | (adjusted_clock == test_adjusted_clock) && |
1667 | (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && |
1668 | (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) |
1669 | return test_radeon_crtc->pll_id; |
1670 | } |
1671 | } |
1672 | return ATOM_PPLL_INVALID; |
1673 | } |
1674 | |
1675 | /** |
1676 | * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. |
1677 | * |
1678 | * @crtc: drm crtc |
1679 | * |
1680 | * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors |
1681 | * a single PPLL can be used for all DP crtcs/encoders. For non-DP |
1682 | * monitors a dedicated PPLL must be used. If a particular board has |
1683 | * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming |
1684 | * as there is no need to program the PLL itself. If we are not able to |
1685 | * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to |
1686 | * avoid messing up an existing monitor. |
1687 | * |
1688 | * Asic specific PLL information |
1689 | * |
1690 | * DCE 8.x |
1691 | * KB/KV |
1692 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) |
1693 | * CI |
1694 | * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
1695 | * |
1696 | * DCE 6.1 |
1697 | * - PPLL2 is only available to UNIPHYA (both DP and non-DP) |
1698 | * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) |
1699 | * |
1700 | * DCE 6.0 |
1701 | * - PPLL0 is available to all UNIPHY (DP only) |
1702 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
1703 | * |
1704 | * DCE 5.0 |
1705 | * - DCPLL is available to all UNIPHY (DP only) |
1706 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
1707 | * |
1708 | * DCE 3.0/4.0/4.1 |
1709 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
1710 | * |
1711 | */ |
1712 | static int radeon_atom_pick_pll(struct drm_crtc *crtc) |
1713 | { |
1714 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1715 | struct drm_device *dev = crtc->dev; |
1716 | struct radeon_device *rdev = dev->dev_private; |
1717 | struct radeon_encoder *radeon_encoder = |
1718 | to_radeon_encoder(radeon_crtc->encoder); |
1719 | u32 pll_in_use; |
1720 | int pll; |
1721 | |
1722 | if (ASIC_IS_DCE8(rdev)) { |
1723 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1724 | if (rdev->clock.dp_extclk) |
1725 | /* skip PPLL programming if using ext clock */ |
1726 | return ATOM_PPLL_INVALID; |
1727 | else { |
1728 | /* use the same PPLL for all DP monitors */ |
1729 | pll = radeon_get_shared_dp_ppll(crtc); |
1730 | if (pll != ATOM_PPLL_INVALID) |
1731 | return pll; |
1732 | } |
1733 | } else { |
1734 | /* use the same PPLL for all monitors with the same clock */ |
1735 | pll = radeon_get_shared_nondp_ppll(crtc); |
1736 | if (pll != ATOM_PPLL_INVALID) |
1737 | return pll; |
1738 | } |
1739 | /* otherwise, pick one of the plls */ |
1740 | if ((rdev->family == CHIP_KAVERI) || |
1741 | (rdev->family == CHIP_KABINI) || |
1742 | (rdev->family == CHIP_MULLINS)) { |
1743 | /* KB/KV/ML has PPLL1 and PPLL2 */ |
1744 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1745 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1746 | return ATOM_PPLL2; |
1747 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1748 | return ATOM_PPLL1; |
1749 | DRM_ERROR("unable to allocate a PPLL\n" ); |
1750 | return ATOM_PPLL_INVALID; |
1751 | } else { |
1752 | /* CI has PPLL0, PPLL1, and PPLL2 */ |
1753 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1754 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1755 | return ATOM_PPLL2; |
1756 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1757 | return ATOM_PPLL1; |
1758 | if (!(pll_in_use & (1 << ATOM_PPLL0))) |
1759 | return ATOM_PPLL0; |
1760 | DRM_ERROR("unable to allocate a PPLL\n" ); |
1761 | return ATOM_PPLL_INVALID; |
1762 | } |
1763 | } else if (ASIC_IS_DCE61(rdev)) { |
1764 | struct radeon_encoder_atom_dig *dig = |
1765 | radeon_encoder->enc_priv; |
1766 | |
1767 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && |
1768 | (dig->linkb == false)) |
1769 | /* UNIPHY A uses PPLL2 */ |
1770 | return ATOM_PPLL2; |
1771 | else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1772 | /* UNIPHY B/C/D/E/F */ |
1773 | if (rdev->clock.dp_extclk) |
1774 | /* skip PPLL programming if using ext clock */ |
1775 | return ATOM_PPLL_INVALID; |
1776 | else { |
1777 | /* use the same PPLL for all DP monitors */ |
1778 | pll = radeon_get_shared_dp_ppll(crtc); |
1779 | if (pll != ATOM_PPLL_INVALID) |
1780 | return pll; |
1781 | } |
1782 | } else { |
1783 | /* use the same PPLL for all monitors with the same clock */ |
1784 | pll = radeon_get_shared_nondp_ppll(crtc); |
1785 | if (pll != ATOM_PPLL_INVALID) |
1786 | return pll; |
1787 | } |
1788 | /* UNIPHY B/C/D/E/F */ |
1789 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1790 | if (!(pll_in_use & (1 << ATOM_PPLL0))) |
1791 | return ATOM_PPLL0; |
1792 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1793 | return ATOM_PPLL1; |
1794 | DRM_ERROR("unable to allocate a PPLL\n" ); |
1795 | return ATOM_PPLL_INVALID; |
1796 | } else if (ASIC_IS_DCE41(rdev)) { |
1797 | /* Don't share PLLs on DCE4.1 chips */ |
1798 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1799 | if (rdev->clock.dp_extclk) |
1800 | /* skip PPLL programming if using ext clock */ |
1801 | return ATOM_PPLL_INVALID; |
1802 | } |
1803 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1804 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1805 | return ATOM_PPLL1; |
1806 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1807 | return ATOM_PPLL2; |
1808 | DRM_ERROR("unable to allocate a PPLL\n" ); |
1809 | return ATOM_PPLL_INVALID; |
1810 | } else if (ASIC_IS_DCE4(rdev)) { |
1811 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, |
1812 | * depending on the asic: |
1813 | * DCE4: PPLL or ext clock |
1814 | * DCE5: PPLL, DCPLL, or ext clock |
1815 | * DCE6: PPLL, PPLL0, or ext clock |
1816 | * |
1817 | * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip |
1818 | * PPLL/DCPLL programming and only program the DP DTO for the |
1819 | * crtc virtual pixel clock. |
1820 | */ |
1821 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1822 | if (rdev->clock.dp_extclk) |
1823 | /* skip PPLL programming if using ext clock */ |
1824 | return ATOM_PPLL_INVALID; |
1825 | else if (ASIC_IS_DCE6(rdev)) |
1826 | /* use PPLL0 for all DP */ |
1827 | return ATOM_PPLL0; |
1828 | else if (ASIC_IS_DCE5(rdev)) |
1829 | /* use DCPLL for all DP */ |
1830 | return ATOM_DCPLL; |
1831 | else { |
1832 | /* use the same PPLL for all DP monitors */ |
1833 | pll = radeon_get_shared_dp_ppll(crtc); |
1834 | if (pll != ATOM_PPLL_INVALID) |
1835 | return pll; |
1836 | } |
1837 | } else { |
1838 | /* use the same PPLL for all monitors with the same clock */ |
1839 | pll = radeon_get_shared_nondp_ppll(crtc); |
1840 | if (pll != ATOM_PPLL_INVALID) |
1841 | return pll; |
1842 | } |
1843 | /* all other cases */ |
1844 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1845 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1846 | return ATOM_PPLL1; |
1847 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1848 | return ATOM_PPLL2; |
1849 | DRM_ERROR("unable to allocate a PPLL\n" ); |
1850 | return ATOM_PPLL_INVALID; |
1851 | } else { |
1852 | /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ |
1853 | /* some atombios (observed in some DCE2/DCE3) code have a bug, |
1854 | * the matching btw pll and crtc is done through |
1855 | * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the |
1856 | * pll (1 or 2) to select which register to write. ie if using |
1857 | * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 |
1858 | * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to |
1859 | * choose which value to write. Which is reverse order from |
1860 | * register logic. So only case that works is when pllid is |
1861 | * same as crtcid or when both pll and crtc are enabled and |
1862 | * both use same clock. |
1863 | * |
1864 | * So just return crtc id as if crtc and pll were hard linked |
1865 | * together even if they aren't |
1866 | */ |
1867 | return radeon_crtc->crtc_id; |
1868 | } |
1869 | } |
1870 | |
1871 | void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) |
1872 | { |
1873 | /* always set DCPLL */ |
1874 | if (ASIC_IS_DCE6(rdev)) |
1875 | atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); |
1876 | else if (ASIC_IS_DCE4(rdev)) { |
1877 | struct radeon_atom_ss ss; |
1878 | bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, |
1879 | ASIC_INTERNAL_SS_ON_DCPLL, |
1880 | rdev->clock.default_dispclk); |
1881 | if (ss_enabled) |
1882 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); |
1883 | /* XXX: DCE5, make sure voltage, dispclk is high enough */ |
1884 | atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); |
1885 | if (ss_enabled) |
1886 | atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); |
1887 | } |
1888 | |
1889 | } |
1890 | |
1891 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
1892 | struct drm_display_mode *mode, |
1893 | struct drm_display_mode *adjusted_mode, |
1894 | int x, int y, struct drm_framebuffer *old_fb) |
1895 | { |
1896 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1897 | struct drm_device *dev = crtc->dev; |
1898 | struct radeon_device *rdev = dev->dev_private; |
1899 | struct radeon_encoder *radeon_encoder = |
1900 | to_radeon_encoder(radeon_crtc->encoder); |
1901 | bool is_tvcv = false; |
1902 | |
1903 | if (radeon_encoder->active_device & |
1904 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
1905 | is_tvcv = true; |
1906 | |
1907 | if (!radeon_crtc->adjusted_clock) |
1908 | return -EINVAL; |
1909 | |
1910 | atombios_crtc_set_pll(crtc, adjusted_mode); |
1911 | |
1912 | if (ASIC_IS_DCE4(rdev)) |
1913 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
1914 | else if (ASIC_IS_AVIVO(rdev)) { |
1915 | if (is_tvcv) |
1916 | atombios_crtc_set_timing(crtc, adjusted_mode); |
1917 | else |
1918 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
1919 | } else { |
1920 | atombios_crtc_set_timing(crtc, adjusted_mode); |
1921 | if (radeon_crtc->crtc_id == 0) |
1922 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
1923 | radeon_legacy_atom_fixup(crtc); |
1924 | } |
1925 | atombios_crtc_set_base(crtc, x, y, old_fb); |
1926 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
1927 | atombios_scaler_setup(crtc); |
1928 | /* update the hw version fpr dpm */ |
1929 | radeon_crtc->hw_mode = *adjusted_mode; |
1930 | |
1931 | return 0; |
1932 | } |
1933 | |
1934 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
1935 | const struct drm_display_mode *mode, |
1936 | struct drm_display_mode *adjusted_mode) |
1937 | { |
1938 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1939 | struct drm_device *dev = crtc->dev; |
1940 | struct drm_encoder *encoder; |
1941 | |
1942 | /* assign the encoder to the radeon crtc to avoid repeated lookups later */ |
1943 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1944 | if (encoder->crtc == crtc) { |
1945 | radeon_crtc->encoder = encoder; |
1946 | radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); |
1947 | break; |
1948 | } |
1949 | } |
1950 | if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { |
1951 | radeon_crtc->encoder = NULL; |
1952 | radeon_crtc->connector = NULL; |
1953 | return false; |
1954 | } |
1955 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
1956 | return false; |
1957 | if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) |
1958 | return false; |
1959 | /* pick pll */ |
1960 | radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); |
1961 | /* if we can't get a PPLL for a non-DP encoder, fail */ |
1962 | if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && |
1963 | !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) |
1964 | return false; |
1965 | |
1966 | return true; |
1967 | } |
1968 | |
1969 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
1970 | { |
1971 | struct drm_device *dev = crtc->dev; |
1972 | struct radeon_device *rdev = dev->dev_private; |
1973 | |
1974 | /* disable crtc pair power gating before programming */ |
1975 | if (ASIC_IS_DCE6(rdev)) |
1976 | atombios_powergate_crtc(crtc, ATOM_DISABLE); |
1977 | |
1978 | atombios_lock_crtc(crtc, ATOM_ENABLE); |
1979 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
1980 | } |
1981 | |
1982 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
1983 | { |
1984 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
1985 | atombios_lock_crtc(crtc, ATOM_DISABLE); |
1986 | } |
1987 | |
1988 | static void atombios_crtc_disable(struct drm_crtc *crtc) |
1989 | { |
1990 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1991 | struct drm_device *dev = crtc->dev; |
1992 | struct radeon_device *rdev = dev->dev_private; |
1993 | struct radeon_atom_ss ss; |
1994 | int i; |
1995 | |
1996 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
1997 | if (crtc->primary->fb) { |
1998 | int r; |
1999 | struct radeon_framebuffer *radeon_fb; |
2000 | struct radeon_bo *rbo; |
2001 | |
2002 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
2003 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
2004 | r = radeon_bo_reserve(rbo, false); |
2005 | if (unlikely(r)) |
2006 | DRM_ERROR("failed to reserve rbo before unpin\n" ); |
2007 | else { |
2008 | radeon_bo_unpin(rbo); |
2009 | radeon_bo_unreserve(rbo); |
2010 | } |
2011 | } |
2012 | /* disable the GRPH */ |
2013 | if (ASIC_IS_DCE4(rdev)) |
2014 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); |
2015 | else if (ASIC_IS_AVIVO(rdev)) |
2016 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); |
2017 | |
2018 | if (ASIC_IS_DCE6(rdev)) |
2019 | atombios_powergate_crtc(crtc, ATOM_ENABLE); |
2020 | |
2021 | for (i = 0; i < rdev->num_crtc; i++) { |
2022 | if (rdev->mode_info.crtcs[i] && |
2023 | rdev->mode_info.crtcs[i]->enabled && |
2024 | i != radeon_crtc->crtc_id && |
2025 | radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { |
2026 | /* one other crtc is using this pll don't turn |
2027 | * off the pll |
2028 | */ |
2029 | goto done; |
2030 | } |
2031 | } |
2032 | |
2033 | switch (radeon_crtc->pll_id) { |
2034 | case ATOM_PPLL1: |
2035 | case ATOM_PPLL2: |
2036 | /* disable the ppll */ |
2037 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
2038 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
2039 | break; |
2040 | case ATOM_PPLL0: |
2041 | /* disable the ppll */ |
2042 | if ((rdev->family == CHIP_ARUBA) || |
2043 | (rdev->family == CHIP_BONAIRE) || |
2044 | (rdev->family == CHIP_HAWAII)) |
2045 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
2046 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
2047 | break; |
2048 | default: |
2049 | break; |
2050 | } |
2051 | done: |
2052 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; |
2053 | radeon_crtc->adjusted_clock = 0; |
2054 | radeon_crtc->encoder = NULL; |
2055 | radeon_crtc->connector = NULL; |
2056 | } |
2057 | |
2058 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
2059 | .dpms = atombios_crtc_dpms, |
2060 | .mode_fixup = atombios_crtc_mode_fixup, |
2061 | .mode_set = atombios_crtc_mode_set, |
2062 | .mode_set_base = atombios_crtc_set_base, |
2063 | .mode_set_base_atomic = atombios_crtc_set_base_atomic, |
2064 | .prepare = atombios_crtc_prepare, |
2065 | .commit = atombios_crtc_commit, |
2066 | .load_lut = radeon_crtc_load_lut, |
2067 | .disable = atombios_crtc_disable, |
2068 | }; |
2069 | |
2070 | void radeon_atombios_init_crtc(struct drm_device *dev, |
2071 | struct radeon_crtc *radeon_crtc) |
2072 | { |
2073 | struct radeon_device *rdev = dev->dev_private; |
2074 | |
2075 | if (ASIC_IS_DCE4(rdev)) { |
2076 | switch (radeon_crtc->crtc_id) { |
2077 | case 0: |
2078 | default: |
2079 | radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; |
2080 | break; |
2081 | case 1: |
2082 | radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; |
2083 | break; |
2084 | case 2: |
2085 | radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; |
2086 | break; |
2087 | case 3: |
2088 | radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; |
2089 | break; |
2090 | case 4: |
2091 | radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; |
2092 | break; |
2093 | case 5: |
2094 | radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; |
2095 | break; |
2096 | } |
2097 | } else { |
2098 | if (radeon_crtc->crtc_id == 1) |
2099 | radeon_crtc->crtc_offset = |
2100 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
2101 | else |
2102 | radeon_crtc->crtc_offset = 0; |
2103 | } |
2104 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; |
2105 | radeon_crtc->adjusted_clock = 0; |
2106 | radeon_crtc->encoder = NULL; |
2107 | radeon_crtc->connector = NULL; |
2108 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
2109 | } |
2110 | |