1/* $NetBSD: nouveau_engine_device_nve0.c,v 1.2 2015/10/18 15:42:00 jmcneill Exp $ */
2
3/*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26
27#include <sys/cdefs.h>
28__KERNEL_RCSID(0, "$NetBSD: nouveau_engine_device_nve0.c,v 1.2 2015/10/18 15:42:00 jmcneill Exp $");
29
30#include <subdev/bios.h>
31#include <subdev/bus.h>
32#include <subdev/gpio.h>
33#include <subdev/i2c.h>
34#include <subdev/clock.h>
35#include <subdev/therm.h>
36#include <subdev/mxm.h>
37#include <subdev/devinit.h>
38#include <subdev/mc.h>
39#include <subdev/timer.h>
40#include <subdev/fb.h>
41#include <subdev/ltcg.h>
42#include <subdev/ibus.h>
43#include <subdev/instmem.h>
44#include <subdev/vm.h>
45#include <subdev/bar.h>
46#include <subdev/pwr.h>
47#include <subdev/volt.h>
48
49#include <engine/device.h>
50#include <engine/dmaobj.h>
51#include <engine/fifo.h>
52#include <engine/software.h>
53#include <engine/graph.h>
54#include <engine/disp.h>
55#include <engine/copy.h>
56#include <engine/bsp.h>
57#include <engine/vp.h>
58#include <engine/ppp.h>
59#include <engine/perfmon.h>
60
61int
62nve0_identify(struct nouveau_device *device)
63{
64 switch (device->chipset) {
65 case 0xe4:
66 device->cname = "GK104";
67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
68 device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
69 device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
70 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
71 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
72 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
73 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
74 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
75 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
76 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
77 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
78 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
79 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
80 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
81 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
82 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
83 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
84 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
85 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
86 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
87 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
88 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
89 device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
90 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
91 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
92 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
93 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
94 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
95 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
96 device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
97 break;
98 case 0xe7:
99 device->cname = "GK107";
100 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
101 device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
102 device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
103 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
104 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
105 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
106 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
107 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
108 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
109 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
110 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
111 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
112 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
113 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
114 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
115 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
116 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
117 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
118 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
119 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
120 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
121 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
122 device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
123 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
124 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
125 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
126 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
127 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
128 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
129 device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
130 break;
131 case 0xe6:
132 device->cname = "GK106";
133 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
134 device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
135 device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
136 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
137 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
138 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
139 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
140 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
141 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
142 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
143 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
144 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
145 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
146 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
147 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
148 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
149 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
150 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
151 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
152 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
153 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
154 device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
155 device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
156 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
157 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
158 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
159 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
160 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
161 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
162 device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
163 break;
164 case 0xea:
165 device->cname = "GK20A";
166 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
167 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
168 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
169 device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass;
170 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
171 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
172 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
173 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
174 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
175 device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
176 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
177 device->oclass[NVDEV_ENGINE_GR ] = gk20a_graph_oclass;
178 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
179 device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
180 break;
181 case 0xf0:
182 device->cname = "GK110";
183 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
184 device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
185 device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
186 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
187 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
188 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
189 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
190 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
191 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
192 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
193 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
194 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
195 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
196 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
197 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
198 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
199 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
200 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
201 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
202 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
203 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
204 device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass;
205 device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
206 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
207 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
208 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
209#if 0
210 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
211 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
212 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
213#endif
214 device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
215 break;
216 case 0x108:
217 device->cname = "GK208";
218 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
219 device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
220 device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
221 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
222 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
223 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
224 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
225 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
226 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
227 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
228 device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
229 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
230 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
231 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
232 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
233 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
234 device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass;
235 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
236 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
237 device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
238 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
239 device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass;
240 device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
241 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
242 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
243 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
244#if 0
245 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
246 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
247 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
248#endif
249 break;
250 default:
251 nv_fatal(device, "unknown Kepler chipset\n");
252 return -EINVAL;
253 }
254
255 return 0;
256}
257