1 | /****************************************************************************** |
2 | |
3 | Copyright (c) 2001-2013, Intel Corporation |
4 | All rights reserved. |
5 | |
6 | Redistribution and use in source and binary forms, with or without |
7 | modification, are permitted provided that the following conditions are met: |
8 | |
9 | 1. Redistributions of source code must retain the above copyright notice, |
10 | this list of conditions and the following disclaimer. |
11 | |
12 | 2. Redistributions in binary form must reproduce the above copyright |
13 | notice, this list of conditions and the following disclaimer in the |
14 | documentation and/or other materials provided with the distribution. |
15 | |
16 | 3. Neither the name of the Intel Corporation nor the names of its |
17 | contributors may be used to endorse or promote products derived from |
18 | this software without specific prior written permission. |
19 | |
20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
23 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
24 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
25 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
26 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
27 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
28 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
29 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
30 | POSSIBILITY OF SUCH DAMAGE. |
31 | |
32 | ******************************************************************************/ |
33 | /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_dcb_82599.h 251964 2013-06-18 21:28:19Z jfv $*/ |
34 | |
35 | #ifndef _IXGBE_DCB_82599_H_ |
36 | #define _IXGBE_DCB_82599_H_ |
37 | |
38 | /* DCB register definitions */ |
39 | #define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin, |
40 | * 1 WSP - Weighted Strict Priority |
41 | */ |
42 | #define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin, |
43 | * 1 WRR - Weighted Round Robin |
44 | */ |
45 | #define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */ |
46 | #define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */ |
47 | #define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must |
48 | * clear! |
49 | */ |
50 | #define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */ |
51 | |
52 | /* Receive UP2TC mapping */ |
53 | #define IXGBE_RTRUP2TC_UP_SHIFT 3 |
54 | #define IXGBE_RTRUP2TC_UP_MASK 7 |
55 | /* Transmit UP2TC mapping */ |
56 | #define IXGBE_RTTUP2TC_UP_SHIFT 3 |
57 | |
58 | #define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ |
59 | #define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */ |
60 | #define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */ |
61 | #define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */ |
62 | |
63 | #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet |
64 | * buffers enable |
65 | */ |
66 | #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores |
67 | * (RSS) enable |
68 | */ |
69 | |
70 | /* RTRPCS Bit Masks */ |
71 | #define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */ |
72 | /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ |
73 | #define IXGBE_RTRPCS_RAC 0x00000004 |
74 | #define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */ |
75 | |
76 | /* RTTDT2C Bit Masks */ |
77 | #define IXGBE_RTTDT2C_MCL_SHIFT 12 |
78 | #define IXGBE_RTTDT2C_BWG_SHIFT 9 |
79 | #define IXGBE_RTTDT2C_GSP 0x40000000 |
80 | #define IXGBE_RTTDT2C_LSP 0x80000000 |
81 | |
82 | #define IXGBE_RTTPT2C_MCL_SHIFT 12 |
83 | #define IXGBE_RTTPT2C_BWG_SHIFT 9 |
84 | #define IXGBE_RTTPT2C_GSP 0x40000000 |
85 | #define IXGBE_RTTPT2C_LSP 0x80000000 |
86 | |
87 | /* RTTPCS Bit Masks */ |
88 | #define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin, |
89 | * 1 SP - Strict Priority |
90 | */ |
91 | #define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */ |
92 | #define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */ |
93 | #define IXGBE_RTTPCS_ARBD_SHIFT 22 |
94 | #define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */ |
95 | |
96 | #define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */ |
97 | |
98 | /* SECTXMINIFG DCB */ |
99 | #define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer SEC IFG */ |
100 | |
101 | /* BCN register definitions */ |
102 | #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 |
103 | #define IXGBE_RTTBCNRC_RS_ENA 0x80000000 |
104 | |
105 | #define IXGBE_RTTBCNCR_MNG_CMTGI 0x00000001 |
106 | #define IXGBE_RTTBCNCR_MGN_BCNA_MODE 0x00000002 |
107 | #define IXGBE_RTTBCNCR_RSV7_11_SHIFT 5 |
108 | #define IXGBE_RTTBCNCR_G 0x00000400 |
109 | #define IXGBE_RTTBCNCR_I 0x00000800 |
110 | #define IXGBE_RTTBCNCR_H 0x00001000 |
111 | #define IXGBE_RTTBCNCR_VER_SHIFT 14 |
112 | #define IXGBE_RTTBCNCR_CMT_ETH_SHIFT 16 |
113 | |
114 | #define IXGBE_RTTBCNACL_SMAC_L_SHIFT 16 |
115 | |
116 | #define IXGBE_RTTBCNTG_BCNA_MODE 0x80000000 |
117 | |
118 | #define IXGBE_RTTBCNRTT_TS_SHIFT 3 |
119 | #define IXGBE_RTTBCNRTT_TXQ_IDX_SHIFT 16 |
120 | |
121 | #define IXGBE_RTTBCNRD_BCN_CLEAR_ALL 0x00000002 |
122 | #define IXGBE_RTTBCNRD_DRIFT_FAC_SHIFT 2 |
123 | #define IXGBE_RTTBCNRD_DRIFT_INT_SHIFT 16 |
124 | #define IXGBE_RTTBCNRD_DRIFT_ENA 0x80000000 |
125 | |
126 | |
127 | /* DCB driver APIs */ |
128 | |
129 | /* DCB PFC */ |
130 | s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *, u8, u8 *); |
131 | |
132 | /* DCB stats */ |
133 | s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *, |
134 | struct ixgbe_dcb_config *); |
135 | s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *, |
136 | struct ixgbe_hw_stats *, u8); |
137 | s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *, |
138 | struct ixgbe_hw_stats *, u8); |
139 | |
140 | /* DCB config arbiters */ |
141 | s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, |
142 | u8 *, u8 *); |
143 | s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, |
144 | u8 *, u8 *, u8 *); |
145 | s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, u8 *, |
146 | u8 *, u8 *); |
147 | |
148 | /* DCB initialization */ |
149 | s32 ixgbe_dcb_config_82599(struct ixgbe_hw *, |
150 | struct ixgbe_dcb_config *); |
151 | |
152 | s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, |
153 | u8 *, u8 *); |
154 | #endif /* _IXGBE_DCB_82959_H_ */ |
155 | |