1 | /* $NetBSD: tulipreg.h,v 1.37 2012/01/16 17:58:02 jakllsch Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, |
9 | * NASA Ames Research Center. |
10 | * |
11 | * Redistribution and use in source and binary forms, with or without |
12 | * modification, are permitted provided that the following conditions |
13 | * are met: |
14 | * 1. Redistributions of source code must retain the above copyright |
15 | * notice, this list of conditions and the following disclaimer. |
16 | * 2. Redistributions in binary form must reproduce the above copyright |
17 | * notice, this list of conditions and the following disclaimer in the |
18 | * documentation and/or other materials provided with the distribution. |
19 | * |
20 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
21 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
22 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
23 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
24 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
30 | * POSSIBILITY OF SUCH DAMAGE. |
31 | */ |
32 | |
33 | #ifndef _DEV_IC_TULIPREG_H_ |
34 | #define _DEV_IC_TULIPREG_H_ |
35 | |
36 | /* |
37 | * Register description for the Digital Semiconductor ``Tulip'' (21x4x) |
38 | * Ethernet controller family, and a variety of clone chips, including: |
39 | * |
40 | * - Macronix 98713, 98713A, 98715, 98715A, 98725 (PMAC): |
41 | * |
42 | * These chips are fairly straight-forward Tulip clones. |
43 | * The 98713 is a very close 21140A clone. It has GPR |
44 | * and MII media, and a GPIO facility, and uses the ISV |
45 | * SROM format (or, at least, should, because of the GPIO |
46 | * facility). The 98713A has MII, no GPIO facility, and |
47 | * an internal NWay block. The 98715, 98715A, and 98725 |
48 | * have only GPR media and the NWay block. The 98715, |
49 | * 98715A, and 98725 support power management. |
50 | * |
51 | * The 98715AEC adds 802.3x flow Frame based Flow Control to the |
52 | * 98715A. |
53 | * |
54 | * - Lite-On 82C115 (PNIC II): |
55 | * |
56 | * A clone of the Macronix MX98725, with the following differences: |
57 | * |
58 | * - Wake-On-LAN support |
59 | * - 128-bit multicast hash table rather than the |
60 | * standard 512-bit hash table |
61 | * - 802.3x flow control |
62 | * |
63 | * - Lite-On 82C168, 82C169 (PNIC): |
64 | * |
65 | * Pretty close, with only a few minor differences: |
66 | * |
67 | * - EEPROM is accessed completely differently. |
68 | * - MII is accessed completely differently. |
69 | * - No SIO facility (due to the above two differences). |
70 | * - GPIO interface is different than the 21140's. |
71 | * - Boards that lack PHYs use the internal NWay block |
72 | * and transceiver. |
73 | * |
74 | * - Winbond 89C840F |
75 | * |
76 | * Less similar, but still roughly compatible (enough so |
77 | * that the driver can be adapted, at least): |
78 | * |
79 | * - Registers lack the pad word between them. |
80 | * - Instead of a setup frame, there are two station |
81 | * address registers and two multicast hash table |
82 | * registers (64-bit multicast hash table). |
83 | * - Only supported media interface is MII-over-SIO. |
84 | * - Different OPMODE register bits for various things |
85 | * (mostly media related). |
86 | * |
87 | * - ADMtek AL981 |
88 | * |
89 | * Another pretty-close clone: |
90 | * |
91 | * - Wake-On-LAN support |
92 | * - Instead of a setup frame, there are two station |
93 | * address registers and two multicast hash table |
94 | * registers (64-bit multicast hash table). |
95 | * - 802.3x flow control |
96 | * - Only supported media interface is built-in PHY |
97 | * which is accessed through a set of special registers. |
98 | * - Not all registers have the pad word between them, |
99 | * but luckily, there are all AL981-specific registers, |
100 | * so this is easy to deal with. |
101 | * |
102 | * - ADMtek AN983 and AN985 |
103 | * |
104 | * Similar to the ADMtek AL981, but with a few differences. |
105 | * |
106 | * - Xircom X3201-3 |
107 | * |
108 | * CardBus 21143 clone, with a few differences: |
109 | * |
110 | * - No MicroWire SROM; Ethernet address must come |
111 | * from CIS. |
112 | * - Transmit buffers must also be 32-bit aligned. |
113 | * - The BUSMODE_SWR bit is not self-clearing. |
114 | * - Must include FS|LS in setup packet descriptor. |
115 | * - SIA is not 21143-like, and all media attachments |
116 | * are MII-on-SIO. |
117 | * |
118 | * - Davicom DM9102 and DM9102A |
119 | * |
120 | * Pretty similar to the 21140A, with a few differences: |
121 | * |
122 | * - Wake-On-LAN support |
123 | * - DM9102 has built-in 10/100 PHY on MII interface. |
124 | * - DM9102A has built-in 10/100 PHY on MII interface, |
125 | * as well as a HomePNA 1 PHY on an alternate MII |
126 | * interface (selected by clearing OPMODE_PS). |
127 | * - The chip has a bug in the transmit DMA logic, |
128 | * requiring that the packet be comprised of only |
129 | * one DMA segment. |
130 | * - The bus interface is buggy, and the BUSMODE register |
131 | * must be initialized to 0. |
132 | * - There seems to be an interrupt logic bug, requiring |
133 | * that interrupts be disabled on the chip during the |
134 | * interrupt handler. |
135 | * |
136 | * - ASIX AX88140 |
137 | * |
138 | * 21433 clone with a few differences: |
139 | * |
140 | * - Specific broadcast bit in the OPMODE register. |
141 | * - Transmit buffer must be 32-bit aligned. |
142 | * - The BUSMODE_SWR bit is not self-clearing. |
143 | * - External 10BaseT PHY or 10/100 MII. |
144 | * |
145 | * Some of the clone chips have different registers, and some have |
146 | * different bits in the same registers. These will be denoted by |
147 | * PMAC, PNICII, PNIC, DM, WINB, ADM and AX in the register/bit names. |
148 | */ |
149 | |
150 | /* |
151 | * Tulip buffer descriptor. Must be 4-byte aligned. |
152 | * |
153 | * Note for receive descriptors, the byte count fields must |
154 | * be a multiple of 4. |
155 | */ |
156 | struct tulip_desc { |
157 | volatile uint32_t td_status; /* Status */ |
158 | volatile uint32_t td_ctl; /* Control and Byte Counts */ |
159 | volatile uint32_t td_bufaddr1; /* Buffer Address 1 */ |
160 | volatile uint32_t td_bufaddr2; /* Buffer Address 2 */ |
161 | } __packed __aligned(4); |
162 | |
163 | /* |
164 | * Descriptor Status bits common to transmit and receive. |
165 | */ |
166 | #define TDSTAT_OWN 0x80000000 /* Tulip owns descriptor */ |
167 | #define TDSTAT_ES 0x00008000 /* Error Summary */ |
168 | |
169 | /* |
170 | * Descriptor Status bits for Receive Descriptor. |
171 | */ |
172 | #define TDSTAT_Rx_FF 0x40000000 /* Filtering Fail */ |
173 | #define TDSTAT_WINB_Rx_RCMP 0x40000000 /* Receive Complete */ |
174 | #define TDSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */ |
175 | #define TDSTAT_Rx_DE 0x00004000 /* Descriptor Error */ |
176 | #define TDSTAT_Rx_DT 0x00003000 /* Data Type */ |
177 | #define TDSTAT_Rx_RF 0x00000800 /* Runt Frame */ |
178 | #define TDSTAT_Rx_MF 0x00000400 /* Multicast Frame */ |
179 | #define TDSTAT_Rx_FS 0x00000200 /* First Descriptor */ |
180 | #define TDSTAT_Rx_LS 0x00000100 /* Last Descriptor */ |
181 | #define TDSTAT_Rx_TL 0x00000080 /* Frame Too Long */ |
182 | #define TDSTAT_Rx_CS 0x00000040 /* Collision Seen */ |
183 | #define TDSTAT_Rx_RT 0x00000020 /* Frame Type */ |
184 | #define TDSTAT_Rx_RW 0x00000010 /* Receive Watchdog */ |
185 | #define TDSTAT_Rx_RE 0x00000008 /* Report on MII Error */ |
186 | #define TDSTAT_Rx_DB 0x00000004 /* Dribbling Bit */ |
187 | #define TDSTAT_Rx_CE 0x00000002 /* CRC Error */ |
188 | #define TDSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */ |
189 | |
190 | #define TDSTAT_Rx_LENGTH(x) (((x) & TDSTAT_Rx_FL) >> 16) |
191 | |
192 | #define TDSTAT_Rx_DT_SR 0x00000000 /* Serial Received Frame */ |
193 | #define TDSTAT_Rx_DT_IL 0x00001000 /* Internal Loopback Frame */ |
194 | #define TDSTAT_Rx_DT_EL 0x00002000 /* External Loopback Frame */ |
195 | #define TDSTAT_Rx_DT_r 0x00003000 /* Reserved */ |
196 | |
197 | /* |
198 | * Descriptor Status bits for Transmit Descriptor. |
199 | */ |
200 | #define TDSTAT_WINB_Tx_TE 0x00008000 /* Transmit Error */ |
201 | #define TDSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */ |
202 | #define TDSTAT_Tx_LO 0x00000800 /* Loss of Carrier */ |
203 | #define TDSTAT_Tx_NC 0x00000400 /* No Carrier */ |
204 | #define TDSTAT_Tx_LC 0x00000200 /* Late Collision */ |
205 | #define TDSTAT_Tx_EC 0x00000100 /* Excessive Collisions */ |
206 | #define TDSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */ |
207 | #define TDSTAT_Tx_CC 0x00000078 /* Collision Count */ |
208 | #define TDSTAT_Tx_LF 0x00000004 /* Link Fail */ |
209 | #define TDSTAT_Tx_UF 0x00000002 /* Underflow Error */ |
210 | #define TDSTAT_Tx_DE 0x00000001 /* Deferred */ |
211 | |
212 | #define TDSTAT_Tx_COLLISIONS(x) (((x) & TDSTAT_Tx_CC) >> 3) |
213 | |
214 | /* |
215 | * Descriptor Control bits common to transmit and receive. |
216 | */ |
217 | #define TDCTL_SIZE1 0x000007ff /* Size of buffer 1 */ |
218 | #define TDCTL_SIZE1_SHIFT 0 |
219 | |
220 | #define TDCTL_SIZE2 0x003ff800 /* Size of buffer 2 */ |
221 | #define TDCTL_SIZE2_SHIFT 11 |
222 | |
223 | #define TDCTL_ER 0x02000000 /* End of Ring */ |
224 | #define TDCTL_CH 0x01000000 /* Second Address Chained */ |
225 | |
226 | /* |
227 | * Descriptor Control bits for Transmit Descriptor. |
228 | */ |
229 | #define TDCTL_Tx_IC 0x80000000 /* Interrupt on Completion */ |
230 | #define TDCTL_Tx_LS 0x40000000 /* Last Segment */ |
231 | #define TDCTL_Tx_FS 0x20000000 /* First Segment */ |
232 | #define TDCTL_Tx_FT1 0x10000000 /* Filtering Type 1 */ |
233 | #define TDCTL_Tx_SET 0x08000000 /* Setup Packet */ |
234 | #define TDCTL_Tx_AC 0x04000000 /* Add CRC Disable */ |
235 | #define TDCTL_Tx_DPD 0x00800000 /* Disabled Padding */ |
236 | #define TDCTL_Tx_FT0 0x00400000 /* Filtering Type 0 */ |
237 | |
238 | /* |
239 | * The Tulip filter is programmed by "transmitting" a Setup Packet |
240 | * (indicated by TDCTL_Tx_SET). The filtering type is indicated |
241 | * as follows: |
242 | * |
243 | * FT1 FT0 Description |
244 | * --- --- ----------- |
245 | * 0 0 Perfect Filtering: The Tulip interprets the |
246 | * descriptor buffer as a table of 16 MAC addresses |
247 | * that the Tulip should receive. |
248 | * |
249 | * 0 1 Hash Filtering: The Tulip interprets the |
250 | * descriptor buffer as a 512-bit hash table |
251 | * plus one perfect address. If the incoming |
252 | * address is Multicast, the hash table filters |
253 | * the address, else the address is filtered by |
254 | * the perfect address. |
255 | * |
256 | * 1 0 Inverse Filtering: Like Perfect Filtering, except |
257 | * the table is addresses that the Tulip does NOT |
258 | * receive. |
259 | * |
260 | * 1 1 Hash-only Filtering: Like Hash Filtering, but |
261 | * physical addresses are matched by the hash table |
262 | * as well, and not by matching a single perfect |
263 | * address. |
264 | * |
265 | * A Setup Packet must always be 192 bytes long. The Tulip can store |
266 | * 16 MAC addresses. If not all 16 are specified in Perfect Filtering |
267 | * or Inverse Filtering mode, then unused entries should duplicate |
268 | * one of the valid entries. |
269 | */ |
270 | #define TDCTL_Tx_FT_PERFECT 0 |
271 | #define TDCTL_Tx_FT_HASH TDCTL_Tx_FT0 |
272 | #define TDCTL_Tx_FT_INVERSE TDCTL_Tx_FT1 |
273 | #define TDCTL_Tx_FT_HASHONLY (TDCTL_Tx_FT1|TDCTL_Tx_FT0) |
274 | |
275 | #define TULIP_SETUP_PACKET_LEN 192 |
276 | #define TULIP_MAXADDRS 16 |
277 | #define TULIP_MCHASHSIZE 512 |
278 | #define TULIP_PNICII_HASHSIZE 128 |
279 | |
280 | /* |
281 | * Maximum size of a Tulip Ethernet Address ROM or SROM. |
282 | */ |
283 | #define TULIP_ROM_SIZE(bits) (2 << (bits)) |
284 | #define TULIP_MAX_ROM_SIZE 512 |
285 | |
286 | /* |
287 | * Format of the standard Tulip SROM information: |
288 | * |
289 | * Byte offset Size Usage |
290 | * 0 18 reserved |
291 | * 18 1 SROM Format Version |
292 | * 19 1 Chip Count |
293 | * 20 6 IEEE Network Address |
294 | * 26 1 Chip 0 Device Number |
295 | * 27 2 Chip 0 Info Leaf Offset |
296 | * 29 1 Chip 1 Device Number |
297 | * 30 2 Chip 1 Info Leaf Offset |
298 | * 32 1 Chip 2 Device Number |
299 | * 33 2 Chip 2 Info Leaf Offset |
300 | * ... 1 Chip n Device Number |
301 | * ... 2 Chip n Info Leaf Offset |
302 | * ... ... ... |
303 | * Chip Info Leaf Information |
304 | * ... |
305 | * ... |
306 | * ... |
307 | * 126 2 CRC32 checksum |
308 | */ |
309 | #define TULIP_ROM_SROM_FORMAT_VERION 18 /* B */ |
310 | #define TULIP_ROM_CHIP_COUNT 19 /* B */ |
311 | #define TULIP_ROM_IEEE_NETWORK_ADDRESS 20 |
312 | #define TULIP_ROM_CHIPn_DEVICE_NUMBER(n) (26 + ((n) * 3))/* B */ |
313 | #define TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(n) (27 + ((n) * 3))/* W */ |
314 | #define TULIP_ROM_CRC32_CHECKSUM 126 /* W */ |
315 | #define TULIP_ROM_CRC32_CHECKSUM1 94 /* W */ |
316 | |
317 | #define TULIP_ROM_IL_SELECT_CONN_TYPE 0 /* W */ |
318 | #define TULIP_ROM_IL_MEDIA_COUNT 2 /* B */ |
319 | #define TULIP_ROM_IL_MEDIAn_BLOCK_BASE 3 |
320 | |
321 | #define SELECT_CONN_TYPE_TP 0x0000 |
322 | #define SELECT_CONN_TYPE_BNC 0x0001 |
323 | #define SELECT_CONN_TYPE_AUI 0x0002 |
324 | #define SELECT_CONN_TYPE_100TX 0x0003 |
325 | #define SELECT_CONN_TYPE_100T4 0x0006 |
326 | #define SELECT_CONN_TYPE_100FX 0x0007 |
327 | #define SELECT_CONN_TYPE MII_10T 0x0009 |
328 | #define SELECT_CONN_TYPE_MII_100TX 0x000d |
329 | #define SELECT_CONN_TYPE_MII_100T4 0x000f |
330 | #define SELECT_CONN_TYPE_MII_100FX 0x0010 |
331 | #define SELECT_CONN_TYPE_TP_AUTONEG 0x0100 |
332 | #define SELECT_CONN_TYPE_TP_FDX 0x0204 |
333 | #define SELECT_CONN_TYPE_MII_10T_FDX 0x020a |
334 | #define SELECT_CONN_TYPE_100TX_FDX 0x020e |
335 | #define SELECT_CONN_TYPE_MII_100TX_FDX 0x0211 |
336 | #define SELECT_CONN_TYPE_TP_NOLINKPASS 0x0400 |
337 | #define SELECT_CONN_TYPE_ASENSE 0x0800 |
338 | #define SELECT_CONN_TYPE_ASENSE_POWERUP 0x8800 |
339 | #define SELECT_CONN_TYPE_ASENSE_AUTONEG 0x0900 |
340 | |
341 | #define TULIP_ROM_MB_MEDIA_CODE 0x3f |
342 | #define TULIP_ROM_MB_MEDIA_TP 0x00 |
343 | #define TULIP_ROM_MB_MEDIA_BNC 0x01 |
344 | #define TULIP_ROM_MB_MEDIA_AUI 0x02 |
345 | #define TULIP_ROM_MB_MEDIA_100TX 0x03 |
346 | #define TULIP_ROM_MB_MEDIA_TP_FDX 0x04 |
347 | #define TULIP_ROM_MB_MEDIA_100TX_FDX 0x05 |
348 | #define TULIP_ROM_MB_MEDIA_100T4 0x06 |
349 | #define TULIP_ROM_MB_MEDIA_100FX 0x07 |
350 | #define TULIP_ROM_MB_MEDIA_100FX_FDX 0x08 |
351 | |
352 | #define TULIP_ROM_MB_EXT 0x40 |
353 | |
354 | #define TULIP_ROM_MB_CSR13 1 /* W */ |
355 | #define TULIP_ROM_MB_CSR14 3 /* W */ |
356 | #define TULIP_ROM_MB_CSR15 5 /* W */ |
357 | |
358 | #define TULIP_ROM_MB_SIZE(mc) (((mc) & TULIP_ROM_MB_EXT) ? 7 : 1) |
359 | |
360 | #define TULIP_ROM_MB_NOINDICATOR 0x8000 |
361 | #define TULIP_ROM_MB_DEFAULT 0x4000 |
362 | #define TULIP_ROM_MB_POLARITY 0x0080 |
363 | #define TULIP_ROM_MB_OPMODE(x) (((x) & 0x71) << 18) |
364 | #define TULIP_ROM_MB_BITPOS(x) (1 << (((x) & 0x0e) >> 1)) |
365 | |
366 | #define TULIP_ROM_MB_21140_GPR 0 /* 21140[A] GPR block */ |
367 | #define TULIP_ROM_MB_21140_MII 1 /* 21140[A] MII block */ |
368 | #define TULIP_ROM_MB_21142_SIA 2 /* 2114[23] SIA block */ |
369 | #define TULIP_ROM_MB_21142_MII 3 /* 2114[23] MII block */ |
370 | #define TULIP_ROM_MB_21143_SYM 4 /* 21143 SYM block */ |
371 | #define TULIP_ROM_MB_21143_RESET 5 /* 21143 reset block */ |
372 | |
373 | #define TULIP_ROM_GETW(data, off) ((uint32_t)(data)[(off)] | \ |
374 | (uint32_t)((data)[(off) + 1]) << 8) |
375 | |
376 | /* |
377 | * Tulip control registers. |
378 | */ |
379 | |
380 | #define TULIP_CSR0 0x00 |
381 | #define TULIP_CSR1 0x08 |
382 | #define TULIP_CSR2 0x10 |
383 | #define TULIP_CSR3 0x18 |
384 | #define TULIP_CSR4 0x20 |
385 | #define TULIP_CSR5 0x28 |
386 | #define TULIP_CSR6 0x30 |
387 | #define TULIP_CSR7 0x38 |
388 | #define TULIP_CSR8 0x40 |
389 | #define TULIP_CSR9 0x48 |
390 | #define TULIP_CSR10 0x50 |
391 | #define TULIP_CSR11 0x58 |
392 | #define TULIP_CSR12 0x60 |
393 | #define TULIP_CSR13 0x68 |
394 | #define TULIP_CSR14 0x70 |
395 | #define TULIP_CSR15 0x78 |
396 | #define TULIP_CSR16 0x80 |
397 | #define TULIP_CSR17 0x88 |
398 | #define TULIP_CSR18 0x90 |
399 | #define TULIP_CSR19 0x98 |
400 | #define TULIP_CSR20 0xa0 |
401 | #define TULIP_CSR21 0xa8 |
402 | #define TULIP_CSR22 0xb0 |
403 | #define TULIP_CSR23 0xb8 |
404 | #define TULIP_CSR24 0xc0 |
405 | #define TULIP_CSR25 0xc8 |
406 | #define TULIP_CSR26 0xd0 |
407 | #define TULIP_CSR27 0xd8 |
408 | #define TULIP_CSR28 0xe0 |
409 | #define TULIP_CSR29 0xe8 |
410 | #define TULIP_CSR30 0xf0 |
411 | #define TULIP_CSR31 0xf8 |
412 | |
413 | #define TULIP_CSR_INDEX(csr) ((csr) >> 3) |
414 | |
415 | /* CSR0 - Bus Mode */ |
416 | #define CSR_BUSMODE TULIP_CSR0 |
417 | #define BUSMODE_SWR 0x00000001 /* software reset */ |
418 | #define BUSMODE_BAR 0x00000002 /* bus arbitration */ |
419 | #define BUSMODE_DSL 0x0000007c /* descriptor skip length */ |
420 | #define BUSMODE_BLE 0x00000080 /* big endian */ |
421 | /* programmable burst length */ |
422 | #define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */ |
423 | #define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */ |
424 | #define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */ |
425 | #define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */ |
426 | #define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */ |
427 | #define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */ |
428 | #define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */ |
429 | /* cache alignment */ |
430 | #define BUSMODE_CAL_NONE 0x00000000 /* no alignment */ |
431 | #define BUSMODE_CAL_8LW 0x00004000 /* 8 longwords */ |
432 | #define BUSMODE_CAL_16LW 0x00008000 /* 16 longwords */ |
433 | #define BUSMODE_CAL_32LW 0x0000c000 /* 32 longwords */ |
434 | #define BUSMODE_DAS 0x00010000 /* diagnostic address space */ |
435 | /* must be zero on most */ |
436 | /* transmit auto-poll */ |
437 | /* |
438 | * Transmit auto-polling not supported on: |
439 | * Winbond 89C040F |
440 | * Xircom X3201-3 |
441 | * Davicom DM9102 (buggy BUSMODE register) |
442 | * ASIX AX88140 |
443 | */ |
444 | #define BUSMODE_TAP_NONE 0x00000000 /* no auto-polling */ |
445 | #define BUSMODE_TAP_200us 0x00020000 /* 200 uS */ |
446 | #define BUSMODE_TAP_800us 0x00040000 /* 400 uS */ |
447 | #define BUSMODE_TAP_1_6ms 0x00060000 /* 1.6 mS */ |
448 | #define BUSMODE_TAP_12_8us 0x00080000 /* 12.8 uS (21041+) */ |
449 | #define BUSMODE_TAP_25_6us 0x000a0000 /* 25.6 uS (21041+) */ |
450 | #define BUSMODE_TAP_51_2us 0x000c0000 /* 51.2 uS (21041+) */ |
451 | #define BUSMODE_TAP_102_4us 0x000e0000 /* 102.4 uS (21041+) */ |
452 | #define BUSMODE_DBO 0x00100000 /* desc-only b/e (21041+) */ |
453 | #define BUSMODE_RME 0x00200000 /* rd/mult enab (21140+) */ |
454 | #define BUSMODE_WINB_WAIT 0x00200000 /* wait state insertion */ |
455 | #define BUSMODE_RLE 0x00800000 /* rd/line enab (21140+) */ |
456 | #define BUSMODE_WLE 0x01000000 /* wt/line enab (21140+) */ |
457 | #define BUSMODE_PNIC_MBO 0x04000000 /* magic `must be one' bit */ |
458 | /* on Lite-On PNIC */ |
459 | |
460 | |
461 | /* CSR1 - Transmit Poll Demand */ |
462 | #define CSR_TXPOLL TULIP_CSR1 |
463 | #define TXPOLL_TPD 0x00000001 /* transmit poll demand */ |
464 | |
465 | |
466 | /* CSR2 - Receive Poll Demand */ |
467 | #define CSR_RXPOLL TULIP_CSR2 |
468 | #define RXPOLL_RPD 0x00000001 /* receive poll demand */ |
469 | |
470 | |
471 | /* CSR3 - Receive List Base Address */ |
472 | #define CSR_RXLIST TULIP_CSR3 |
473 | |
474 | /* CSR4 - Transmit List Base Address */ |
475 | #define CSR_TXLIST TULIP_CSR4 |
476 | |
477 | /* CSR5 - Status */ |
478 | #define CSR_STATUS TULIP_CSR5 |
479 | #define STATUS_TI 0x00000001 /* transmit interrupt */ |
480 | #define STATUS_TPS 0x00000002 /* transmit process stopped */ |
481 | #define STATUS_TU 0x00000004 /* transmit buffer unavail */ |
482 | #define STATUS_TJT 0x00000008 /* transmit jabber timeout */ |
483 | #define STATUS_WINB_REI 0x00000008 /* receive early interrupt */ |
484 | #define STATUS_LNPANC 0x00000010 /* link pass (21041) */ |
485 | #define STATUS_WINB_RERR 0x00000010 /* receive error */ |
486 | #define STATUS_UNF 0x00000020 /* transmit underflow */ |
487 | #define STATUS_RI 0x00000040 /* receive interrupt */ |
488 | #define STATUS_RU 0x00000080 /* receive buffer unavail */ |
489 | #define STATUS_RPS 0x00000100 /* receive process stopped */ |
490 | #define STATUS_RWT 0x00000200 /* receive watchdog timeout */ |
491 | #define STATUS_AT 0x00000400 /* SIA AUI/TP pin changed |
492 | (21040) */ |
493 | #define STATUS_ETI 0x00000400 /* early transmit interrupt |
494 | (21142/PMAC/Winbond) */ |
495 | #define STATUS_FD 0x00000800 /* full duplex short frame |
496 | received (21040) */ |
497 | #define STATUS_TM 0x00000800 /* timer expired (21041) */ |
498 | #define STATUS_LNF 0x00001000 /* link fail (21040) */ |
499 | #define STATUS_SE 0x00002000 /* system error */ |
500 | #define STATUS_ER 0x00004000 /* early receive (21041) */ |
501 | #define STATUS_AIS 0x00008000 /* abnormal interrupt summary */ |
502 | #define STATUS_NIS 0x00010000 /* normal interrupt summary */ |
503 | #define STATUS_RS 0x000e0000 /* receive process state */ |
504 | #define STATUS_RS_STOPPED 0x00000000 /* Stopped */ |
505 | #define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive |
506 | descriptor */ |
507 | #define STATUS_RS_CHECK 0x00040000 /* Running - check for end |
508 | of receive */ |
509 | #define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */ |
510 | #define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */ |
511 | #define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive |
512 | descriptor */ |
513 | #define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current |
514 | frame from FIFO */ |
515 | #define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current |
516 | frame from FIFO into |
517 | buffer */ |
518 | #define STATUS_DM_RS_STOPPED 0x00000000 /* Stopped */ |
519 | #define STATUS_DM_RS_FETCH 0x00020000 /* Running - fetch receive |
520 | descriptor */ |
521 | #define STATUS_DM_RS_WAIT 0x00040000 /* Running - wait for packet */ |
522 | #define STATUS_DM_RS_QUEUE 0x00060000 /* Running - queue current |
523 | frame from FIFO into |
524 | buffer */ |
525 | #define STATUS_DM_RS_CLOSE_OWN 0x00080000 /* Running - close receive |
526 | descriptor, clear own */ |
527 | #define STATUS_DM_RS_CLOSE_ST 0x000a0000 /* Running - close receive |
528 | descriptor, write status */ |
529 | #define STATUS_DM_RS_SUSPENDED 0x000c0000 /* Suspended */ |
530 | #define STATUS_DM_RS_FLUSH 0x000e0000 /* Running - flush current |
531 | frame from FIFO */ |
532 | #define STATUS_TS 0x00700000 /* transmit process state */ |
533 | #define STATUS_TS_STOPPED 0x00000000 /* Stopped */ |
534 | #define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit |
535 | descriptor */ |
536 | #define STATUS_TS_WAIT 0x00200000 /* Running - wait for end |
537 | of transmission */ |
538 | #define STATUS_TS_READING 0x00300000 /* Running - read buffer from |
539 | memory and queue into |
540 | FIFO */ |
541 | #define STATUS_TS_RESERVED 0x00400000 /* RESERVED */ |
542 | #define STATUS_TS_SETUP 0x00500000 /* Running - Setup packet */ |
543 | #define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */ |
544 | #define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit |
545 | descriptor */ |
546 | #define STATUS_DM_TS_STOPPED 0x00000000 /* Stopped */ |
547 | #define STATUS_DM_TS_FETCH 0x00100000 /* Running - fetch transmit |
548 | descriptor */ |
549 | #define STATUS_DM_TS_SETUP 0x00200000 /* Running - Setup packet */ |
550 | #define STATUS_DM_TS_READING 0x00300000 /* Running - read buffer from |
551 | memory and queue into |
552 | FIFO */ |
553 | #define STATUS_DM_TS_CLOSE_OWN 0x00400000 /* Running - close transmit |
554 | descriptor, clear own */ |
555 | #define STATUS_DM_TS_WAIT 0x00500000 /* Running - wait for end |
556 | of transmission */ |
557 | #define STATUS_DM_TS_CLOSE_ST 0x00600000 /* Running - close transmit |
558 | descriptor, write status */ |
559 | #define STATUS_DM_TS_SUSPENDED 0x00700000 /* Suspended */ |
560 | #define STATUS_EB 0x03800000 /* error bits */ |
561 | #define STATUS_EB_PARITY 0x00000000 /* parity errror */ |
562 | #define STATUS_EB_MABT 0x00800000 /* master abort */ |
563 | #define STATUS_EB_TABT 0x01000000 /* target abort */ |
564 | #define STATUS_GPPI 0x04000000 /* GPIO interrupt (21142) */ |
565 | #define STATUS_PNIC_TXABORT 0x04000000 /* transmit aborted */ |
566 | #define STATUS_LC 0x08000000 /* 100baseTX link change |
567 | (21142/PMAC) */ |
568 | #define STATUS_PMAC_WKUPI 0x10000000 /* wake up event */ |
569 | #define STATUS_X3201_PMEIS 0x10000000 /* power management event |
570 | interrupt summary */ |
571 | #define STATUS_X3201_SFIS 0x80000000 /* second function (Modem) |
572 | interrupt status */ |
573 | |
574 | |
575 | /* CSR6 - Operation Mode */ |
576 | #define CSR_OPMODE TULIP_CSR6 |
577 | #define OPMODE_HP 0x00000001 /* hash/perfect mode (ro) */ |
578 | #define OPMODE_SR 0x00000002 /* start receive */ |
579 | #define OPMODE_HO 0x00000004 /* hash only mode (ro) */ |
580 | #define OPMODE_PB 0x00000008 /* pass bad frames */ |
581 | #define OPMODE_WINB_APP 0x00000008 /* accept all physcal packet */ |
582 | #define OPMODE_IF 0x00000010 /* inverse filter mode (ro) */ |
583 | #define OPMODE_WINB_AMP 0x00000010 /* accept multicast packet */ |
584 | #define OPMODE_SB 0x00000020 /* start backoff counter */ |
585 | #define OPMODE_WINB_ABP 0x00000020 /* accept broadcast packet */ |
586 | #define OPMODE_PR 0x00000040 /* promiscuous mode */ |
587 | #define OPMODE_WINB_ARP 0x00000040 /* accept runt packet */ |
588 | #define OPMODE_PM 0x00000080 /* pass all multicast */ |
589 | #define OPMODE_WINB_AEP 0x00000080 /* accept error packet */ |
590 | #define OPMODE_FKD 0x00000100 /* flaky oscillator disable */ |
591 | #define OPMODE_AX_RB 0x00000100 /* recieve broadcast packets */ |
592 | #define OPMODE_FD 0x00000200 /* full-duplex mode */ |
593 | #define OPMODE_OM 0x00000c00 /* operating mode */ |
594 | #define OPMODE_OM_NORMAL 0x00000000 /* normal mode */ |
595 | #define OPMODE_OM_INTLOOP 0x00000400 /* internal loopback */ |
596 | #define OPMODE_OM_EXTLOOP 0x00000800 /* external loopback */ |
597 | #define OPMODE_FC 0x00001000 /* force collision */ |
598 | #define OPMODE_ST 0x00002000 /* start transmitter */ |
599 | #define OPMODE_TR 0x0000c000 /* threshold control */ |
600 | #define OPMODE_TR_72 0x00000000 /* 72 bytes */ |
601 | #define OPMODE_TR_96 0x00004000 /* 96 bytes */ |
602 | #define OPMODE_TR_128 0x00008000 /* 128 bytes */ |
603 | #define OPMODE_TR_160 0x0000c000 /* 160 bytes */ |
604 | #define OPMODE_WINB_TTH 0x001fc000 /* transmit threshold */ |
605 | #define OPMODE_WINB_TTH_SHIFT 14 |
606 | #define OPMODE_BP 0x00010000 /* backpressure enable */ |
607 | #define OPMODE_CA 0x00020000 /* capture effect enable */ |
608 | #define OPMODE_PNIC_TBEN 0x00020000 /* Tx backoff offset enable */ |
609 | /* |
610 | * On Davicom DM9102, OPMODE_PS and OPMODE_HBD must |
611 | * always be set. |
612 | */ |
613 | #define OPMODE_PS 0x00040000 /* port select: |
614 | 1 = MII/SYM, 0 = SRL |
615 | (21140) */ |
616 | #define OPMODE_HBD 0x00080000 /* heartbeat disable: |
617 | set in MII/SYM 100mbps, |
618 | set according to PHY |
619 | in MII 10mbps mode |
620 | (21140) */ |
621 | #define OPMODE_PNIC_IT 0x00100000 /* immediate transmit */ |
622 | #define OPMODE_SF 0x00200000 /* store and forward mode |
623 | (21140) */ |
624 | #define OPMODE_WINB_REIT 0x1fe00000 /* receive eartly intr thresh */ |
625 | #define OPMODE_WINB_REIT_SHIFT 21 |
626 | #define OPMODE_TTM 0x00400000 /* Transmit Threshold Mode: |
627 | 1 = 10mbps, 0 = 100mbps |
628 | (21140) */ |
629 | #define OPMODE_PCS 0x00800000 /* PCS function (21140) */ |
630 | #define OPMODE_SCR 0x01000000 /* scrambler mode (21140) */ |
631 | #define OPMODE_MBO 0x02000000 /* must be one (21140, |
632 | DM9102) */ |
633 | #define OPMODE_IDAMSB 0x04000000 /* ignore dest addr MSB |
634 | (21142) */ |
635 | #define OPMODE_PNIC_DRC 0x20000000 /* don't include CRC in Rx |
636 | frames (PNIC) */ |
637 | #define OPMODE_WINB_FES 0x20000000 /* fast ethernet select */ |
638 | #define OPMODE_RA 0x40000000 /* receive all (21140) */ |
639 | #define OPMODE_PNIC_EED 0x40000000 /* 1 == ext, 0 == int ENDEC |
640 | (PNIC) */ |
641 | #define OPMODE_WINB_TEIO 0x40000000 /* transmit early intr on */ |
642 | #define OPMODE_SC 0x80000000 /* special capture effect |
643 | enable (21041+) */ |
644 | #define OPMODE_WINB_REIO 0x80000000 /* receive early intr on */ |
645 | |
646 | /* Shorthand for media-related OPMODE bits */ |
647 | #define OPMODE_MEDIA_BITS (OPMODE_FD|OPMODE_PS|OPMODE_TTM|OPMODE_PCS|OPMODE_SCR) |
648 | |
649 | /* CSR7 - Interrupt Enable */ |
650 | #define CSR_INTEN TULIP_CSR7 |
651 | /* See bits for CSR5 -- Status */ |
652 | |
653 | |
654 | /* CSR8 - Missed Frames */ |
655 | #define CSR_MISSED TULIP_CSR8 |
656 | #define MISSED_MFC 0x0000ffff /* missed packet count */ |
657 | #define MISSED_MFO 0x00010000 /* missed packet count |
658 | overflowed */ |
659 | #define MISSED_FOC 0x0ffe0000 /* fifo overflow counter |
660 | (21140) */ |
661 | #define MISSED_OCO 0x10000000 /* overflow counter overflowed |
662 | (21140) */ |
663 | |
664 | #define MISSED_GETMFC(x) ((x) & MISSED_MFC) |
665 | #define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 17) |
666 | |
667 | |
668 | /* CSR9 - MII, SROM, Boot ROM, Ethernet Address ROM register. */ |
669 | #define CSR_MIIROM TULIP_CSR9 |
670 | #define MIIROM_DATA 0x000000ff /* byte of data from |
671 | Ethernet Address ROM |
672 | (21040), byte of data |
673 | to/from Boot ROM (21041+) */ |
674 | #define MIIROM_SROMCS 0x00000001 /* SROM chip select */ |
675 | #define MIIROM_SROMSK 0x00000002 /* SROM clock */ |
676 | #define MIIROM_SROMDI 0x00000004 /* SROM data in (to) */ |
677 | #define MIIROM_SROMDO 0x00000008 /* SROM data out (from) */ |
678 | #define MIIROM_REG 0x00000400 /* external register select */ |
679 | #define MIIROM_SR 0x00000800 /* SROM select */ |
680 | #define MIIROM_BR 0x00001000 /* boot ROM select */ |
681 | #define MIIROM_WR 0x00002000 /* write to boot ROM */ |
682 | #define MIIROM_RD 0x00004000 /* read from boot ROM */ |
683 | #define MIIROM_MOD 0x00008000 /* mode select (ro) (21041) */ |
684 | #define MIIROM_MDC 0x00010000 /* MII clock */ |
685 | #define MIIROM_MDO 0x00020000 /* MII data out */ |
686 | #define MIIROM_MIIDIR 0x00040000 /* MII direction mode |
687 | 1 = PHY in read, |
688 | 0 = PHY in write */ |
689 | #define MIIROM_MDI 0x00080000 /* MII data in */ |
690 | #define MIIROM_DN 0x80000000 /* data not valid (21040) */ |
691 | |
692 | #define MIIROM_PMAC_LED0SEL 0x10000000 /* 0 == LED0 activity (def) |
693 | 1 == LED0 speed */ |
694 | #define MIIROM_PMAC_LED1SEL 0x20000000 /* 0 == LED1 link (def) |
695 | 1 == LED1 link/act */ |
696 | #define MIIROM_PMAC_LED2SEL 0x40000000 /* 0 == LED2 speed (def) |
697 | 1 == LED2 collision */ |
698 | #define MIIROM_PMAC_LED3SEL 0x80000000 /* 0 == LED3 receive (def) |
699 | 1 == LED3 full duplex */ |
700 | |
701 | /* SROM opcodes */ |
702 | #define TULIP_SROM_OPC_ERASE 0x04 |
703 | #define TULIP_SROM_OPC_WRITE 0x05 |
704 | #define TULIP_SROM_OPC_READ 0x06 |
705 | |
706 | /* The Lite-On PNIC does this completely differently */ |
707 | #define PNIC_MIIROM_DATA 0x0000ffff /* mask of data bits ??? */ |
708 | #define PNIC_MIIROM_BUSY 0x80000000 /* EEPROM is busy */ |
709 | |
710 | |
711 | /* CSR10 - Boot ROM address register (21041+). */ |
712 | #define CSR_ROMADDR TULIP_CSR10 |
713 | #define ROMADDR_MASK 0x000003ff /* boot rom address */ |
714 | |
715 | |
716 | /* CSR11 - General Purpose Timer (21041+). */ |
717 | #define CSR_GPT TULIP_CSR11 |
718 | #define GPT_VALUE 0x0000ffff /* timer value */ |
719 | #define GPT_CON 0x00010000 /* continuous mode */ |
720 | /* 21143-PD and 21143-TD Interrupt Mitigation bits */ |
721 | #define GPT_NRX 0x000e0000 /* number of Rx packets */ |
722 | #define GPT_RXT 0x00f00000 /* Rx timer */ |
723 | #define GPT_NTX 0x07000000 /* number of Tx packets */ |
724 | #define GPT_TXT 0x78000000 /* Tx timer */ |
725 | #define GPT_CYCLE 0x80000000 /* cycle size */ |
726 | |
727 | |
728 | /* CSR12 - SIA Status Register. */ |
729 | #define CSR_SIASTAT TULIP_CSR12 |
730 | #define SIASTAT_PAUI 0x00000001 /* pin AUI/TP indication |
731 | (21040) */ |
732 | #define SIASTAT_MRA 0x00000001 /* MII receive activity |
733 | (21142) */ |
734 | #define SIASTAT_NCR 0x00000002 /* network connection error */ |
735 | #define SIASTAT_LS100 0x00000002 /* 100baseT link status |
736 | 0 == pass (21142) */ |
737 | #define SIASTAT_LKF 0x00000004 /* link fail status */ |
738 | #define SIASTAT_LS10 0x00000004 /* 10baseT link status |
739 | 0 == pass (21142) */ |
740 | #define SIASTAT_APS 0x00000008 /* auto polarity status */ |
741 | #define SIASTAT_DSD 0x00000010 /* PLL self test done */ |
742 | #define SIASTAT_DSP 0x00000020 /* PLL self test pass */ |
743 | #define SIASTAT_DAZ 0x00000040 /* PLL all zero */ |
744 | #define SIASTAT_DAO 0x00000080 /* PLL all one */ |
745 | #define SIASTAT_SRA 0x00000100 /* selected port receive |
746 | activity (21041) */ |
747 | #define SIASTAT_ARA 0x00000100 /* AUI receive activity |
748 | (21142) */ |
749 | #define SIASTAT_NRA 0x00000200 /* non-selected port |
750 | receive activity (21041) */ |
751 | #define SIASTAT_TRA 0x00000200 /* 10base-T receive activity |
752 | (21142) */ |
753 | #define SIASTAT_NSN 0x00000400 /* non-stable NLPs detected |
754 | (21041) */ |
755 | #define SIASTAT_TRF 0x00000800 /* transmit remote fault |
756 | (21041) */ |
757 | #define SIASTAT_ANS 0x00007000 /* autonegotiation state |
758 | (21041) */ |
759 | #define SIASTAT_ANS_DIS 0x00000000 /* disabled */ |
760 | #define SIASTAT_ANS_TXDIS 0x00001000 /* transmit disabled */ |
761 | #define SIASTAT_ANS_START 0x00001000 /* (MX98715AEC) */ |
762 | #define SIASTAT_ANS_ABD 0x00002000 /* ability detect */ |
763 | #define SIASTAT_ANS_ACKD 0x00003000 /* acknowledge detect */ |
764 | #define SIASTAT_ANS_ACKC 0x00004000 /* complete acknowledge */ |
765 | #define SIASTAT_ANS_FLPGOOD 0x00005000 /* FLP link good */ |
766 | #define SIASTAT_ANS_LINKCHECK 0x00006000 /* link check */ |
767 | #define SIASTAT_LPN 0x00008000 /* link partner negotiable |
768 | (21041) */ |
769 | #define SIASTAT_LPC 0xffff0000 /* link partner code word */ |
770 | |
771 | #define SIASTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16) |
772 | |
773 | |
774 | /* CSR13 - SIA Connectivity Register. */ |
775 | #define CSR_SIACONN TULIP_CSR13 |
776 | #define SIACONN_SRL 0x00000001 /* SIA reset |
777 | (0 == reset) */ |
778 | #define SIACONN_PS 0x00000002 /* pin AUI/TP selection |
779 | (21040) */ |
780 | #define SIACONN_CAC 0x00000004 /* CSR autoconfiguration */ |
781 | #define SIACONN_AUI 0x00000008 /* select AUI (0 = TP) */ |
782 | #define SIACONN_EDP 0x00000010 /* SIA PLL external input |
783 | enable (21040) */ |
784 | #define SIACONN_ENI 0x00000020 /* encoder input multiplexer |
785 | (21040) */ |
786 | #define SIACONN_SIM 0x00000040 /* serial interface input |
787 | multiplexer (21040) */ |
788 | #define SIACONN_ASE 0x00000080 /* APLL start enable |
789 | (21040) */ |
790 | #define SIACONN_SEL 0x00000f00 /* external port output |
791 | multiplexer select |
792 | (21040) */ |
793 | #define SIACONN_IE 0x00001000 /* input enable (21040) */ |
794 | #define SIACONN_OE1_3 0x00002000 /* output enable 1, 3 |
795 | (21040) */ |
796 | #define SIACONN_OE2_4 0x00004000 /* output enable 2, 4 |
797 | (21040) */ |
798 | #define SIACONN_OE5_6_7 0x00008000 /* output enable 5, 6, 7 |
799 | (21040) */ |
800 | #define SIACONN_SDM 0x0000ef00 /* SIA diagnostic mode; |
801 | always set to this value |
802 | for normal operation |
803 | (21041) */ |
804 | |
805 | |
806 | /* CSR14 - SIA Transmit Receive Register. */ |
807 | #define CSR_SIATXRX TULIP_CSR14 |
808 | #define SIATXRX_ECEN 0x00000001 /* encoder enable */ |
809 | #define SIATXRX_LBK 0x00000002 /* loopback enable */ |
810 | #define SIATXRX_DREN 0x00000004 /* driver enable */ |
811 | #define SIATXRX_LSE 0x00000008 /* link pulse send enable */ |
812 | #define SIATXRX_CPEN 0x00000030 /* compensation enable */ |
813 | #define SIATXRX_CPEN_DIS0 0x00000000 /* disabled */ |
814 | #define SIATXRX_CPEN_DIS1 0x00000010 /* disabled */ |
815 | #define SIATXRX_CPEN_HIGHPWR 0x00000020 /* high power */ |
816 | #define SIATXRX_CPEN_NORMAL 0x00000030 /* normal */ |
817 | #define SIATXRX_MBO 0x00000040 /* must be one (21041 pass 2) */ |
818 | #define SIATXRX_TH 0x00000040 /* 10baseT HDX enable (21142) */ |
819 | #define SIATXRX_ANE 0x00000080 /* autonegotiation enable |
820 | (21041/21142) */ |
821 | #define SIATXRX_RSQ 0x00000100 /* receive squelch enable */ |
822 | #define SIATXRX_CSQ 0x00000200 /* collision squelch enable */ |
823 | #define SIATXRX_CLD 0x00000400 /* collision detect enable */ |
824 | #define SIATXRX_SQE 0x00000800 /* signal quality generation |
825 | enable */ |
826 | #define SIATXRX_LTE 0x00001000 /* link test enable */ |
827 | #define SIATXRX_APE 0x00002000 /* auto-polarity enable */ |
828 | #define SIATXRX_SPP 0x00004000 /* set polarity plus */ |
829 | #define SIATXRX_TAS 0x00008000 /* 10base-T/AUI autosensing |
830 | enable (21041/21142) */ |
831 | #define SIATXRX_THX 0x00010000 /* 100baseTX-HDX (21142) */ |
832 | #define SIATXRX_TXF 0x00020000 /* 100baseTX-FDX (21142) */ |
833 | #define SIATXRX_T4 0x00040000 /* 100baseT4 (21142) */ |
834 | |
835 | |
836 | /* CSR15 - SIA General Register. */ |
837 | #define CSR_SIAGEN TULIP_CSR15 |
838 | #define SIAGEN_JBD 0x00000001 /* jabber disable */ |
839 | #define SIAGEN_HUJ 0x00000002 /* host unjab */ |
840 | #define SIAGEN_JCK 0x00000004 /* jabber clock */ |
841 | #define SIAGEN_ABM 0x00000008 /* BNC select (21041) */ |
842 | #define SIAGEN_RWD 0x00000010 /* receive watchdog disable */ |
843 | #define SIAGEN_RWR 0x00000020 /* receive watchdog release */ |
844 | #define SIAGEN_LE1 0x00000040 /* LED 1 enable (21041) */ |
845 | #define SIAGEN_LV1 0x00000080 /* LED 1 value (21041) */ |
846 | #define SIAGEN_TSCK 0x00000100 /* test clock */ |
847 | #define SIAGEN_FUSQ 0x00000200 /* force unsquelch */ |
848 | #define SIAGEN_FLF 0x00000400 /* force link fail */ |
849 | #define SIAGEN_LSD 0x00000800 /* LED stretch disable |
850 | (21041) */ |
851 | #define SIAGEN_LEE 0x00000800 /* Link extend enable (21142) */ |
852 | #define SIAGEN_DPST 0x00001000 /* PLL self-test start */ |
853 | #define SIAGEN_FRL 0x00002000 /* force receiver low */ |
854 | #define SIAGEN_LE2 0x00004000 /* LED 2 enable (21041) */ |
855 | #define SIAGEN_RMP 0x00004000 /* received magic packet |
856 | (21143) */ |
857 | #define SIAGEN_LV2 0x00008000 /* LED 2 value (21041) */ |
858 | #define SIAGEN_HCKR 0x00008000 /* hacker (21143) */ |
859 | #define SIAGEN_MD 0x000f0000 /* general purpose mode/data */ |
860 | #define SIAGEN_LGS0 0x00100000 /* LED/GEP 0 select */ |
861 | #define SIAGEN_LGS1 0x00200000 /* LED/GEP 1 select */ |
862 | #define SIAGEN_LGS2 0x00400000 /* LED/GEP 2 select */ |
863 | #define SIAGEN_LGS3 0x00800000 /* LED/GEP 3 select */ |
864 | #define SIAGEN_GEI0 0x01000000 /* GEP pin 0 intr enable */ |
865 | #define SIAGEN_GEI1 0x02000000 /* GEP pin 1 intr enable */ |
866 | #define SIAGEN_RME 0x04000000 /* receive match enable */ |
867 | #define SIAGEN_CWE 0x08000000 /* control write enable */ |
868 | #define SIAGEN_GI0 0x10000000 /* GEP pin 0 interrupt */ |
869 | #define SIAGEN_GI1 0x20000000 /* GEP pin 1 interrupt */ |
870 | #define SIAGEN_RMI 0x40000000 /* receive match interrupt */ |
871 | |
872 | |
873 | /* CSR12 - General Purpose Port (21140+). */ |
874 | #define CSR_GPP TULIP_CSR12 |
875 | #define GPP_MD 0x000000ff /* general purpose mode/data */ |
876 | #define GPP_GPC 0x00000100 /* general purpose control */ |
877 | #define GPP_PNIC_GPD 0x0000000f /* general purpose data */ |
878 | #define GPP_PNIC_GPC 0x000000f0 /* general purpose control */ |
879 | |
880 | #define GPP_PNIC_IN(x) (1 << (x)) |
881 | #define GPP_PNIC_OUT(x, on) (((on) << (x)) | (1 << ((x) + 4))) |
882 | |
883 | /* |
884 | * The Lite-On PNIC manual recommends the following for the General Purpose |
885 | * I/O pins: |
886 | * |
887 | * 0 Speed Relay 1 == 100mbps |
888 | * 1 100mbps loopback 1 == loopback |
889 | * 2 BNC DC-DC converter 1 == select BNC |
890 | * 3 Link 100 1 == 100baseTX link status |
891 | */ |
892 | #define GPP_PNIC_PIN_SPEED_RLY 0 |
893 | #define GPP_PNIC_PIN_100M_LPKB 1 |
894 | #define GPP_PNIC_PIN_BNC_XMER 2 |
895 | #define GPP_PNIC_PIN_LNK100X 3 |
896 | |
897 | /* |
898 | * Definitions used for the SMC 9332DST (21140) board. |
899 | */ |
900 | #define GPP_SMC9332DST_PINS 0x3f /* General Purpose Pin directions */ |
901 | #define GPP_SMC9332DST_OK10 0x80 /* 10 Mb/sec Signal Detect gep<7> */ |
902 | #define GPP_SMC9332DST_OK100 0x40 /* 100 Mb/sec Signal Detect gep<6> */ |
903 | #define GPP_SMC9332DST_INIT 0x09 /* No loopback --- point-to-point */ |
904 | |
905 | /* |
906 | * Definitions used for the Cogent EM1x0 (21140) board. |
907 | */ |
908 | #define GPP_COGENT_EM1x0_PINS 0x3f /* General Purpose Pin directions */ |
909 | #define GPP_COGENT_EM1x0_INIT 0x09 /* No loopback --- point-to-point */ |
910 | |
911 | /* |
912 | * Digital EB140 21140 reference design. |
913 | * MC68832 + ML6671 for 100Mb/s. LXT901 for 10Mb/s. |
914 | * |
915 | * (From document EC-QD2SA-TE, figure 1-3.) |
916 | */ |
917 | #define GPP_EB140_OUTPUTS 0x1f /* these GPP pins are driven */ |
918 | #define GPP_EB140_MC68832_LB 0x01 /* 100Mb/s loopback disable 1 */ |
919 | #define GPP_EB140_ML6671_LB 0x02 /* 100Mb/s loopback disable 2 */ |
920 | #define GPP_EB140_LXT901_ILB 0x04 /* 10Mb/s internal LB enable */ |
921 | #define GPP_EB140_LXT901_ELB 0x08 /* 10Mb/s external LB disable */ |
922 | #define GPP_EB140_RESERVED 0x10 /* media switch relay on other boards */ |
923 | #define GPP_EB140_MC68836_SYNC 0x20 /* synced to 100Mb/s PHY */ |
924 | #define GPP_EB140_MC68836_LINK 0x40 /* 100Mb/s signal detect */ |
925 | #define GPP_EB140_LXT901_LINK 0x80 /* 10Mb/s link pass */ |
926 | |
927 | #define GPP_EB140_INIT (GPP_EB140_LXT901_ELB|GPP_EB140_ML6671_LB|GPP_EB140_MC68832_LB) |
928 | |
929 | /* |
930 | * Digital Semiconductor 21040 registers. |
931 | */ |
932 | |
933 | /* CSR11 - Full Duplex Register */ |
934 | #define CSR_21040_FDX TULIP_CSR11 |
935 | #define FDX21040_FDXACV 0x0000ffff /* full duplex |
936 | autoconfiguration value */ |
937 | |
938 | |
939 | /* SIA configuration for 10base-T (from the 21040 manual) */ |
940 | #define SIACONN_21040_10BASET 0x0000ef01 |
941 | #define SIATXRX_21040_10BASET 0x0000ffff |
942 | #define SIAGEN_21040_10BASET 0x00000000 |
943 | |
944 | |
945 | /* SIA configuration for 10base-T full-duplex (from the 21040 manual) */ |
946 | #define SIACONN_21040_10BASET_FDX 0x0000ef01 |
947 | #define SIATXRX_21040_10BASET_FDX 0x0000fffd |
948 | #define SIAGEN_21040_10BASET_FDX 0x00000000 |
949 | |
950 | |
951 | /* SIA configuration for 10base-5 (from the 21040 manual) */ |
952 | #define SIACONN_21040_AUI 0x0000ef09 |
953 | #define SIATXRX_21040_AUI 0x00000705 |
954 | #define SIAGEN_21040_AUI 0x00000006 |
955 | |
956 | |
957 | /* SIA configuration for External SIA (from the 21040 manual) */ |
958 | #define SIACONN_21040_EXTSIA 0x00003041 |
959 | #define SIATXRX_21040_EXTSIA 0x00000000 |
960 | #define SIAGEN_21040_EXTSIA 0x00000006 |
961 | |
962 | |
963 | /* |
964 | * Digital Semiconductor 21041 registers. |
965 | */ |
966 | |
967 | /* SIA configuration for 10base-T (from the 21041 manual) */ |
968 | #define SIACONN_21041_10BASET 0x0000ef01 |
969 | #define SIATXRX_21041_10BASET 0x0000ff3f |
970 | #define SIAGEN_21041_10BASET 0x00000000 |
971 | |
972 | #define SIACONN_21041P2_10BASET SIACONN_21041_10BASET |
973 | #define SIATXRX_21041P2_10BASET 0x0000ffff |
974 | #define SIAGEN_21041P2_10BASET SIAGEN_21041_10BASET |
975 | |
976 | |
977 | /* SIA configuration for 10base-T full-duplex (from the 21041 manual) */ |
978 | #define SIACONN_21041_10BASET_FDX 0x0000ef01 |
979 | #define SIATXRX_21041_10BASET_FDX 0x0000ff3d |
980 | #define SIAGEN_21041_10BASET_FDX 0x00000000 |
981 | |
982 | #define SIACONN_21041P2_10BASET_FDX SIACONN_21041_10BASET_FDX |
983 | #define SIATXRX_21041P2_10BASET_FDX 0x0000ffff |
984 | #define SIAGEN_21041P2_10BASET_FDX SIAGEN_21041_10BASET_FDX |
985 | |
986 | |
987 | /* SIA configuration for 10base-5 (from the 21041 manual) */ |
988 | #define SIACONN_21041_AUI 0x0000ef09 |
989 | #define SIATXRX_21041_AUI 0x0000f73d |
990 | #define SIAGEN_21041_AUI 0x0000000e |
991 | |
992 | #define SIACONN_21041P2_AUI SIACONN_21041_AUI |
993 | #define SIATXRX_21041P2_AUI 0x0000f7fd |
994 | #define SIAGEN_21041P2_AUI SIAGEN_21041_AUI |
995 | |
996 | |
997 | /* SIA configuration for 10base-2 (from the 21041 manual) */ |
998 | #define SIACONN_21041_BNC 0x0000ef09 |
999 | #define SIATXRX_21041_BNC 0x0000f73d |
1000 | #define SIAGEN_21041_BNC 0x00000006 |
1001 | |
1002 | #define SIACONN_21041P2_BNC SIACONN_21041_BNC |
1003 | #define SIATXRX_21041P2_BNC 0x0000f7fd |
1004 | #define SIAGEN_21041P2_BNC SIAGEN_21041_BNC |
1005 | |
1006 | |
1007 | /* |
1008 | * Digital Semiconductor 21142/21143 registers. |
1009 | */ |
1010 | |
1011 | /* SIA configuration for 10baseT (from the 21143 manual) */ |
1012 | #define SIACONN_21142_10BASET 0x00000001 |
1013 | #define SIATXRX_21142_10BASET 0x00007f3f |
1014 | #define SIAGEN_21142_10BASET 0x00000008 |
1015 | |
1016 | |
1017 | /* SIA configuration for 10baseT full-duplex (from the 21143 manual) */ |
1018 | #define SIACONN_21142_10BASET_FDX 0x00000001 |
1019 | #define SIATXRX_21142_10BASET_FDX 0x00007f3d |
1020 | #define SIAGEN_21142_10BASET_FDX 0x00000008 |
1021 | |
1022 | |
1023 | /* SIA configuration for 10base5 (from the 21143 manual) */ |
1024 | #define SIACONN_21142_AUI 0x00000009 |
1025 | #define SIATXRX_21142_AUI 0x00004705 |
1026 | #define SIAGEN_21142_AUI 0x0000000e |
1027 | |
1028 | |
1029 | /* SIA configuration for 10base2 (from the 21143 manual) */ |
1030 | #define SIACONN_21142_BNC 0x00000009 |
1031 | #define SIATXRX_21142_BNC 0x00004705 |
1032 | #define SIAGEN_21142_BNC 0x00000006 |
1033 | |
1034 | |
1035 | /* |
1036 | * Lite-On 82C168/82C169 registers. |
1037 | */ |
1038 | |
1039 | /* ENDEC General Register */ |
1040 | #define CSR_PNIC_ENDEC 0x78 |
1041 | #define PNIC_ENDEC_JDIS 0x00000001 /* jabber disable */ |
1042 | |
1043 | /* SROM Power Register */ |
1044 | #define CSR_PNIC_SROMPWR 0x90 |
1045 | #define PNIC_SROMPWR_MRLE 0x00000001 /* Memory-Read-Line enable */ |
1046 | #define PNIC_SROMPWR_CB 0x00000002 /* cache boundary alignment |
1047 | burst type; 1 == burst to |
1048 | boundary, 0 == single-cycle |
1049 | to boundary */ |
1050 | |
1051 | /* SROM Control Register */ |
1052 | #define CSR_PNIC_SROMCTL 0x98 |
1053 | #define PNIC_SROMCTL_addr 0x0000003f /* mask of address bits */ |
1054 | /* XXX THESE ARE WRONG ACCORDING TO THE MANUAL! */ |
1055 | #define PNIC_SROMCTL_READ 0x00000600 /* read command */ |
1056 | |
1057 | /* MII Access Register */ |
1058 | #define CSR_PNIC_MII 0xa0 |
1059 | #define PNIC_MII_DATA 0x0000ffff /* mask of data bits */ |
1060 | #define PNIC_MII_REG 0x007c0000 /* register mask */ |
1061 | #define PNIC_MII_REGSHIFT 18 |
1062 | #define PNIC_MII_PHY 0x0f800000 /* phy mask */ |
1063 | #define PNIC_MII_PHYSHIFT 23 |
1064 | #define PNIC_MII_OPCODE 0x30000000 /* opcode mask */ |
1065 | #define PNIC_MII_RESERVED 0x00020000 /* must be one/must be zero; |
1066 | 2 bits are described here */ |
1067 | #define PNIC_MII_MBO 0x40000000 /* must be one */ |
1068 | #define PNIC_MII_BUSY 0x80000000 /* MII is busy */ |
1069 | |
1070 | #define PNIC_MII_WRITE 0x10000000 /* write PHY command */ |
1071 | #define PNIC_MII_READ 0x20000000 /* read PHY command */ |
1072 | |
1073 | /* NWAY Register */ |
1074 | #define CSR_PNIC_NWAY 0xb8 |
1075 | #define PNIC_NWAY_RS 0x00000001 /* reset NWay block */ |
1076 | #define PNIC_NWAY_PD 0x00000002 /* power down NWay block */ |
1077 | #define PNIC_NWAY_BX 0x00000004 /* bypass transceiver */ |
1078 | #define PNIC_NWAY_LC 0x00000008 /* AUI low current mode */ |
1079 | #define PNIC_NWAY_UV 0x00000010 /* low squelch voltage */ |
1080 | #define PNIC_NWAY_DX 0x00000020 /* disable TP pol. correction */ |
1081 | #define PNIC_NWAY_TW 0x00000040 /* select TP (0 == AUI) */ |
1082 | #define PNIC_NWAY_AF 0x00000080 /* AUI full/half step input |
1083 | voltage */ |
1084 | #define PNIC_NWAY_FD 0x00000100 /* full duplex mode */ |
1085 | #define PNIC_NWAY_DL 0x00000200 /* disable link integrity |
1086 | test */ |
1087 | #define PNIC_NWAY_DM 0x00000400 /* disable AUI/TP autodetect */ |
1088 | #define PNIC_NWAY_100 0x00000800 /* 1 == 100mbps, 0 == 10mbps */ |
1089 | #define PNIC_NWAY_NW 0x00001000 /* enable NWay block */ |
1090 | #define PNIC_NWAY_CAP10T 0x00002000 /* adv. 10baseT */ |
1091 | #define PNIC_NWAY_CAP10TFDX 0x00004000 /* adv. 10baseT-FDX */ |
1092 | #define PNIC_NWAY_CAP100TXFDX 0x00008000 /* adv. 100baseTX-FDX */ |
1093 | #define PNIC_NWAY_CAP100TX 0x00010000 /* adv. 100baseTX */ |
1094 | #define PNIC_NWAY_CAP100T4 0x00020000 /* adv. 100base-T4 */ |
1095 | #define PNIC_NWAY_RN 0x02000000 /* re-negotiate enable */ |
1096 | #define PNIC_NWAY_RF 0x04000000 /* remote fault detected */ |
1097 | #define PNIC_NWAY_LPAR10T 0x08000000 /* link part. 10baseT */ |
1098 | #define PNIC_NWAY_LPAR10TFDX 0x10000000 /* link part. 10baseT-FDX */ |
1099 | #define PNIC_NWAY_LPAR100TXFDX 0x20000000 /* link part. 100baseTX-FDX */ |
1100 | #define PNIC_NWAY_LPAR100TX 0x40000000 /* link part. 100baseTX */ |
1101 | #define PNIC_NWAY_LPAR100T4 0x80000000 /* link part. 100base-T4 */ |
1102 | #define PNIC_NWAY_LPAR_MASK 0xf8000000 |
1103 | |
1104 | |
1105 | /* |
1106 | * Macronix 98713, 98713A, 98715, 98715A, 98715AEC, 98725 and |
1107 | * Lite-On 82C115 registers. |
1108 | */ |
1109 | |
1110 | /* |
1111 | * Note, the MX98713 is very Tulip-like: |
1112 | * |
1113 | * CSR12 General Purpose Port (like 21140) |
1114 | * CSR13 reserved |
1115 | * CSR14 reserved |
1116 | * CSR15 Watchdog Timer (like 21140) |
1117 | * |
1118 | * The Macronix CSR12, CSR13, CSR14, and CSR15 exist only |
1119 | * on the MX98713A and higher. |
1120 | */ |
1121 | |
1122 | /* CSR12 - 10base-T Status Port (similar to SIASTAT) */ |
1123 | /* See SIASTAT 21142/21143 bits */ |
1124 | #define CSR_PMAC_10TSTAT TULIP_CSR12 |
1125 | #define PMAC_SIASTAT_MASK (SIASTAT_LS100|SIASTAT_LS10| \ |
1126 | SIASTAT_APS|SIASTAT_TRF|SIASTAT_ANS| \ |
1127 | SIASTAT_LPN|SIASTAT_LPC) |
1128 | |
1129 | |
1130 | /* CSR13 - NWAY Reset Register */ |
1131 | #define CSR_PMAC_NWAYRESET TULIP_CSR13 |
1132 | /* See SIACONN 21142/21143 bits */ |
1133 | #define PMAC_SIACONN_MASK (SIACONN_SRL) |
1134 | #define PMAC_NWAYRESET_100TXRESET 0x00000002 /* 100base PMD reset */ |
1135 | |
1136 | |
1137 | /* CSR14 - 10base-T Control Port */ |
1138 | #define CSR_PMAC_10TCTL TULIP_CSR14 |
1139 | /* See SIATXRX 21142/21143 bits */ |
1140 | #define PMAC_SIATXRX_MASK (SIATXRX_LBK|SIATXRX_DREN|SIATXRX_TH| \ |
1141 | SIATXRX_ANE|SIATXRX_RSQ|SIATXRX_LTE| \ |
1142 | SIATXRX_THX|SIATXRX_TXF|SIATXRX_T4) |
1143 | |
1144 | |
1145 | /* CSR15 - Watchdog Timer Register */ |
1146 | /* MX98713: see 21140 CSR15 */ |
1147 | /* others: see SIAGEN 21142/21143 bits */ |
1148 | #define PMAC_SIAGEN_MASK (SIAGEN_JBD|SIAGEN_HUJ|SIAGEN_JCK| \ |
1149 | SIAGEN_RWD|SIAGEN_RWR) |
1150 | |
1151 | |
1152 | /* CSR16 - Test Operation Register (a.k.a. Magic Packet Register) */ |
1153 | #define CSR_PMAC_TOR TULIP_CSR16 |
1154 | #define PMAC_TOR_98713 0x0F370000 |
1155 | #define PMAC_TOR_98715 0x0B3C0000 |
1156 | |
1157 | |
1158 | /* CSR20 - NWAY Status */ |
1159 | #define CSR_PMAC_NWAYSTAT TULIP_CSR20 |
1160 | /* |
1161 | * Note: the MX98715A manual claims that EQTEST and PCITEST |
1162 | * must be set to 1 by software for normal operation, but |
1163 | * this does not appear to be necessary. This is probably |
1164 | * one of the things that frobbing the Test Operation Register |
1165 | * does. |
1166 | * |
1167 | * MX98715AEC uses this register for Auto Compensation. |
1168 | * CSR20<14> and CSR20<9> are called DS130 and DS120 |
1169 | */ |
1170 | #define PMAC_NWAYSTAT_DS120 0x00000200 /* Auto-compensation circ */ |
1171 | #define PMAC_NWAYSTAT_DS130 0x00004000 /* Auto-compensation circ */ |
1172 | #define PMAC_NWAYSTAT_EQTEST 0x00001000 /* EQ test */ |
1173 | #define PMAC_NWAYSTAT_PCITEST 0x00010000 /* PCI test */ |
1174 | #define PMAC_NWAYSTAT_10TXH 0x08000000 /* 10t accepted */ |
1175 | #define PMAC_NWAYSTAT_10TXF 0x10000000 /* 10t-fdx accepted */ |
1176 | #define PMAC_NWAYSTAT_100TXH 0x20000000 /* 100tx accepted */ |
1177 | #define PMAC_NWAYSTAT_100TXF 0x40000000 /* 100tx-fdx accepted */ |
1178 | #define PMAC_NWAYSTAT_T4 0x80000000 /* 100t4 accepted */ |
1179 | |
1180 | |
1181 | /* CSR21 - Flow Control Register */ |
1182 | #define CSR_PNICII_FLOWCTL TULIP_CSR21 |
1183 | #define PNICII_FLOWCTL_WKFCATEN 0x00000010 /* enable wake-up frame |
1184 | catenation feature */ |
1185 | #define PNICII_FLOWCTL_NFCE 0x00000020 /* accept flow control result |
1186 | from NWay */ |
1187 | #define PNICII_FLOWCTL_FCTH0 0x00000040 /* rx flow control thresh 0 */ |
1188 | #define PNICII_FLOWCTL_FCTH1 0x00000080 /* rx flow control thresh 1 */ |
1189 | #define PNICII_FLOWCTL_REJECTFC 0x00000100 /* abort rx flow control */ |
1190 | #define PNICII_FLOWCTL_STOPTX 0x00000200 /* tx flow stopped */ |
1191 | #define PNICII_FLOWCTL_RUFCEN 0x00000400 /* send flow control when |
1192 | RU interrupt occurs */ |
1193 | #define PNICII_FLOWCTL_RXFCEN 0x00000800 /* rx flow control enable */ |
1194 | #define PNICII_FLOWCTL_TXFCEN 0x00001000 /* tx flow control enable */ |
1195 | #define PNICII_FLOWCTL_RESTOP 0x00002000 /* restop mode */ |
1196 | #define PNICII_FLOWCTL_RESTART 0x00004000 /* restart mode */ |
1197 | #define PNICII_FLOWCTL_TEST 0x00008000 /* test flow control timer */ |
1198 | #define PNICII_FLOWCTL_TMVAL 0xffff0000 /* timer value in flow |
1199 | control frame */ |
1200 | |
1201 | #define PNICII_FLOWCTL_TH_512 (PNICII_FLOWCTL_FCTH0|PNICII_FLOWCTL_FCTH1) |
1202 | #define PNICII_FLOWCTL_TH_256 (PNICII_FLOWCTL_FCTH1) |
1203 | #define PNICII_FLOWCTL_TH_128 (PNICII_FLOWCTL_FCTH0) |
1204 | #define PNICII_FLOWCTL_TH_OVFLW (0) |
1205 | |
1206 | |
1207 | /* CSR22 - MAC ID Byte 3-0 Register */ |
1208 | #define CSR_PNICII_MACID0 TULIP_CSR22 |
1209 | #define PNICII_MACID_1 0 /* shift */ |
1210 | #define PNICII_MACID_0 8 /* shift */ |
1211 | #define PNICII_MACID_3 16 /* shift */ |
1212 | #define PNICII_MACID_2 24 /* shift */ |
1213 | |
1214 | |
1215 | /* CSR23 - Magic ID Byte 5,4/MACID Byte 5,4 Register */ |
1216 | #define PNICII_MACID_5 0 /* shift */ |
1217 | #define PNICII_MACID_4 8 /* shift */ |
1218 | #define PNICII_MAGID_5 16 /* shift */ |
1219 | #define PNICII_MAGIC_4 24 /* shift */ |
1220 | |
1221 | |
1222 | /* CSR24 - Magic ID Byte 3-0 Register */ |
1223 | #define PNICII_MAGID_1 0 /* shift */ |
1224 | #define PNICII_MAGID_0 8 /* shift */ |
1225 | #define PNICII_MAGID_3 16 /* shift */ |
1226 | #define PNICII_MAGID_2 24 /* shift */ |
1227 | |
1228 | |
1229 | /* CSR25 - CSR28 - Filter Byte Mask Registers */ |
1230 | #define CSR_PNICII_MASK0 TULIP_CSR25 |
1231 | |
1232 | #define CSR_PNICII_MASK1 TULIP_CSR26 |
1233 | |
1234 | #define CSR_PNICII_MASK2 TULIP_CSR27 |
1235 | |
1236 | #define CSR_PNICII_MASK3 TULIP_CSR28 |
1237 | |
1238 | |
1239 | /* CSR29 - Filter Offset Register */ |
1240 | #define CSR_PNICII_FILOFF TULIP_CSR29 |
1241 | #define PNICII_FILOFF_PAT0 0x0000007f /* pattern 0 offset */ |
1242 | #define PNICII_FILOFF_EN0 0x00000080 /* enable pattern 0 */ |
1243 | #define PNICII_FILOFF_PAT1 0x00007f00 /* pattern 1 offset */ |
1244 | #define PNICII_FILOFF_EN1 0x00008000 /* enable pattern 1 */ |
1245 | #define PNICII_FILOFF_PAT2 0x007f0000 /* pattern 2 offset */ |
1246 | #define PNICII_FILOFF_EN2 0x00800000 /* enable pattern 2 */ |
1247 | #define PNICII_FILOFF_PAT3 0x7f000000 /* pattern 3 offset */ |
1248 | #define PNICII_FILOFF_EN3 0x80000000 /* enable pattern 3 */ |
1249 | |
1250 | |
1251 | /* CSR30 - Filter 1 and 0 CRC-16 Register */ |
1252 | #define CSR_PNICII_FIL01 TULIP_CSR30 |
1253 | #define PNICII_FIL01_CRC0 0x0000ffff /* CRC-16 of pattern 0 */ |
1254 | #define PNICII_FIL01_CRC1 0xffff0000 /* CRC-16 of pattern 1 */ |
1255 | |
1256 | |
1257 | /* CSR31 = Filter 3 and 2 CRC-16 Register */ |
1258 | #define CSR_PNICII_FIL23 TULIP_CSR31 |
1259 | #define PNICII_FIL23_CRC2 0x0000ffff /* CRC-16 of pattern 2 */ |
1260 | #define PNICII_FIL23_CRC3 0xffff0000 /* CRC-16 of pattern 3 */ |
1261 | |
1262 | |
1263 | /* |
1264 | * Winbond 89C840F registers. |
1265 | */ |
1266 | |
1267 | /* CSR12 - Current Receive Descriptor Register */ |
1268 | #define CSR_WINB_CRDAR TULIP_CSR12 |
1269 | |
1270 | |
1271 | /* CSR13 - Current Receive Buffer Register */ |
1272 | #define CSR_WINB_CCRBAR TULIP_CSR13 |
1273 | |
1274 | |
1275 | /* CSR14 - Multicast Address Register 0 */ |
1276 | #define CSR_WINB_CMA0 TULIP_CSR14 |
1277 | |
1278 | |
1279 | /* CSR15 - Multicast Address Register 1 */ |
1280 | #define CSR_WINB_CMA1 TULIP_CSR15 |
1281 | |
1282 | |
1283 | /* CSR16 - Physical Address Register 0 */ |
1284 | #define CSR_WINB_CPA0 TULIP_CSR16 |
1285 | |
1286 | |
1287 | /* CSR17 - Physical Address Register 1 */ |
1288 | #define CSR_WINB_CPA1 TULIP_CSR17 |
1289 | |
1290 | |
1291 | /* CSR18 - Boot ROM Size Register */ |
1292 | #define CSR_WINB_CBRCR TULIP_CSR18 |
1293 | #define WINB_CBRCR_NONE 0x00000000 /* no boot rom */ |
1294 | /* 0x00000001 also no boot rom */ |
1295 | #define WINB_CBRCR_8K 0x00000002 /* 8k */ |
1296 | #define WINB_CBRCR_16K 0x00000003 /* 16k */ |
1297 | #define WINB_CBRCR_32K 0x00000004 /* 32k */ |
1298 | #define WINB_CBRCR_64K 0x00000005 /* 64k */ |
1299 | #define WINB_CBRCR_128K 0x00000006 /* 128k */ |
1300 | #define WINB_CBRCR_256K 0x00000007 |
1301 | |
1302 | |
1303 | /* CSR19 - Current Transmit Descriptor Register */ |
1304 | #define CSR_WINB_CTDAR TULIP_CSR19 |
1305 | |
1306 | |
1307 | /* CSR20 - Current Transmit Buffer Register */ |
1308 | #define CSR_WINB_CTBAR TULIP_CSR20 |
1309 | |
1310 | |
1311 | /* |
1312 | * ADMtek AL981 registers |
1313 | * |
1314 | * We define these as strict byte offsets into PCI space, since |
1315 | * not all of them have consistent access rules. |
1316 | */ |
1317 | |
1318 | /* CSR13 - Wake-up Control/Status Register */ |
1319 | #define CSR_ADM_WCSR 0x68 |
1320 | #define ADM_WCSR_LSC 0x00000001 /* link status changed */ |
1321 | #define ADM_WCSR_MPR 0x00000002 /* magic packet received */ |
1322 | #define ADM_WCSR_WFR 0x00000004 /* wake up frame received */ |
1323 | #define ADM_WCSR_LSCE 0x00000100 /* link status changed en. */ |
1324 | #define ADM_WCSR_MPRE 0x00000200 /* magic packet receive en. */ |
1325 | #define ADM_WCSR_WFRE 0x00000400 /* wake up frame receive en. */ |
1326 | #define ADM_WCSR_LINKON 0x00010000 /* link-on detect en. */ |
1327 | #define ADM_WCSR_LINKOFF 0x00020000 /* link-off detect en. */ |
1328 | #define ADM_WCSR_WP5E 0x02000000 /* wake up pat. 5 en. */ |
1329 | #define ADM_WCSR_WP4E 0x04000000 /* wake up pat. 4 en. */ |
1330 | #define ADM_WCSR_WP3E 0x08000000 /* wake up pat. 3 en. */ |
1331 | #define ADM_WCSR_WP2E 0x10000000 /* wake up pat. 2 en. */ |
1332 | #define ADM_WCSR_WP1E 0x20000000 /* wake up pat. 1 en. */ |
1333 | #define ADM_WCSR_CRCT 0x40000000 /* CRC-16 type: |
1334 | 0 == 0000 initial |
1335 | 1 == ffff initial */ |
1336 | |
1337 | |
1338 | /* CSR14 - Wake-up Pattern Data Register */ |
1339 | #define CSR_ADM_WPDR 0x70 |
1340 | |
1341 | /* |
1342 | * 25 consecutive longword writes are issued to WPDR to |
1343 | * program the wake-up pattern filter. The data written |
1344 | * is as follows: |
1345 | * |
1346 | * XXX |
1347 | */ |
1348 | |
1349 | |
1350 | /* CSR15 - see 21140 CSR15 (Watchdog Timer) */ |
1351 | |
1352 | |
1353 | /* CSR16 - Assistant CSR5 (Status Register 2) */ |
1354 | #define CSR_ADM_ASR 0x80 |
1355 | /* 0 - 14: same as CSR5 */ |
1356 | #define ADM_ASR_AAISS 0x00080000 /* added abnormal int. sum. */ |
1357 | #define ADM_ASR_ANISS 0x00010000 /* added normal int. sum. */ |
1358 | /* XXX Receive state */ |
1359 | /* XXX Transmit state */ |
1360 | #define ADM_ASR_BET 0x03800000 /* bus error type */ |
1361 | #define ADM_ASR_BET_PERR 0x00000000 /* parity error */ |
1362 | #define ADM_ASR_BET_MABT 0x00800000 /* master abort */ |
1363 | #define ADM_ASR_BET_TABT 0x01000000 /* target abort */ |
1364 | #define ADM_ASR_PFR 0x04000000 /* PAUSE frame received */ |
1365 | #define ADM_ASR_TDIS 0x10000000 /* transmit def. int. status */ |
1366 | #define ADM_ASR_XIS 0x20000000 /* xcvr int. status */ |
1367 | #define ADM_ASR_REIS 0x40000000 /* receive early int. status */ |
1368 | #define ADM_ASR_TEIS 0x80000000 /* transmit early int. status */ |
1369 | |
1370 | |
1371 | /* CSR17 - Assistant CSR7 (Interrupt Enable Register 2) */ |
1372 | #define CSR_ADM_AIE 0x84 |
1373 | /* See CSR16 for valid bits */ |
1374 | |
1375 | |
1376 | /* CSR18 - Command Register */ |
1377 | #define CSR_ADM_CR 0x88 |
1378 | #define ADM_CR_ATUR 0x00000001 /* auto. tx underrun recover */ |
1379 | #define ADM_CR_SINT 0x00000002 /* software interrupt */ |
1380 | #define ADM_CR_DRT 0x0000000c /* drain receive threshold */ |
1381 | #define ADM_CR_DRT_8LW 0x00000000 /* 8 longwords */ |
1382 | #define ADM_CR_DRT_16LW 0x00000004 /* 16 longwords */ |
1383 | #define ADM_CR_DRT_SF 0x00000008 /* store-and-forward */ |
1384 | #define ADM_CR_RTE 0x00000010 /* receive threshold enable */ |
1385 | #define ADM_CR_PAUSE 0x00000020 /* enable PAUSE function */ |
1386 | #define ADM_CR_RWP 0x00000040 /* reset wake-up pattern |
1387 | data register pointer */ |
1388 | /* 16 - 31 are automatically recalled from the EEPROM */ |
1389 | #define ADM_CR_WOL 0x00040000 /* wake-on-lan enable */ |
1390 | #define ADM_CR_PM 0x00080000 /* power management enable */ |
1391 | #define ADM_CR_RFS 0x00600000 /* Receive FIFO size */ |
1392 | #define ADM_CR_RFS_1K 0x00600000 /* 1K FIFO */ |
1393 | #define ADM_CR_RFS_2K 0x00400000 /* 2K FIFO */ |
1394 | #define ADM_CR_LEDMODE 0x00800000 /* LED mode */ |
1395 | #define ADM_CR_AUXCL 0x30000000 /* aux current load */ |
1396 | #define ADM_CR_D3CS 0x80000000 /* D3 cold wake up enable */ |
1397 | |
1398 | |
1399 | /* CSR19 - PCI bus performance counter */ |
1400 | #define CSR_ADM_PCIC 0x8c |
1401 | #define ADM_PCIC_DWCNT 0x000000ff /* double-word count of |
1402 | last bus-master |
1403 | transaction */ |
1404 | #define ADM_PCIC_CLKCNT 0xffff0000 /* number of PCI clocks |
1405 | between read request |
1406 | and access completed */ |
1407 | |
1408 | /* CSR20 - Power Management Control/Status Register */ |
1409 | #define CSR_ADM_PMCSR 0x90 |
1410 | /* |
1411 | * This register is also mapped into the PCI configuration |
1412 | * space as the PMCSR. |
1413 | */ |
1414 | |
1415 | |
1416 | /* CSR23 - Transmit Burst Count/Time Out Register */ |
1417 | #define CSR_ADM_TXBR 0x9c |
1418 | #define ADM_TXBR_TTO 0x00000fff /* transmit timeout */ |
1419 | #define ADM_TXBR_TBCNT 0x001f0000 /* transmit burst count */ |
1420 | |
1421 | |
1422 | /* CSR24 - Flash ROM Port Register */ |
1423 | #define CSR_ADM_FROM 0xa0 |
1424 | #define ADM_FROM_DATA 0x000000ff /* data to/from Flash */ |
1425 | #define ADM_FROM_ADDR 0x01ffff00 /* Flash address */ |
1426 | #define ADM_FROM_ADDR_SHIFT 8 |
1427 | #define ADM_FROM_WEN 0x04000000 /* write enable */ |
1428 | #define ADM_FROM_REN 0x08000000 /* read enable */ |
1429 | #define ADM_FROM_bra16on 0x80000000 /* pin 87 is brA16, else |
1430 | pin 87 is fd/col LED pin */ |
1431 | |
1432 | |
1433 | /* CSR25 - Physical Address Register 0 */ |
1434 | #define CSR_ADM_PAR0 0xa4 |
1435 | |
1436 | |
1437 | /* CSR26 - Physical Address Register 1 */ |
1438 | #define CSR_ADM_PAR1 0xa8 |
1439 | |
1440 | |
1441 | /* CSR27 - Multicast Address Register 0 */ |
1442 | #define CSR_ADM_MAR0 0xac |
1443 | |
1444 | |
1445 | /* CSR28 - Multicast Address Register 1 */ |
1446 | #define CSR_ADM_MAR1 0xb0 |
1447 | |
1448 | |
1449 | /* Internal PHY registers are mapped here (lower 16 bits valid) */ |
1450 | |
1451 | #define CSR_ADM_BMCR 0xb4 |
1452 | #define CSR_ADM_BMSR 0xb8 |
1453 | #define CSR_ADM_PHYIDR1 0xbc |
1454 | #define CSR_ADM_PHYIDR2 0xc0 |
1455 | #define CSR_ADM_ANAR 0xc4 |
1456 | #define CSR_ADM_ANLPAR 0xc8 |
1457 | #define CSR_ADM_ANER 0xcc |
1458 | |
1459 | /* XCVR Mode Control Register */ |
1460 | #define CSR_ADM_XMC 0xd0 |
1461 | #define ADM_XMC_LD 0x00000800 /* long distance mode |
1462 | (low squelch enable) */ |
1463 | |
1464 | |
1465 | /* XCVR Configuration Information and Interrupt Status Register */ |
1466 | #define CSR_ADM_XCIIS 0xd4 |
1467 | #define ADM_XCIIS_REF 0x0001 /* 64 error packets received */ |
1468 | #define ADM_XCIIS_ANPR 0x0002 /* autoneg page received */ |
1469 | #define ADM_XCIIS_PDF 0x0004 /* parallel detection fault */ |
1470 | #define ADM_XCIIS_ANAR 0x0008 /* autoneg ACK */ |
1471 | #define ADM_XCIIS_LS 0x0010 /* link status (1 == fail) */ |
1472 | #define ADM_XCIIS_RFD 0x0020 /* remote fault */ |
1473 | #define ADM_XCIIS_ANC 0x0040 /* autoneg completed */ |
1474 | #define ADM_XCIIS_PAUSE 0x0080 /* PAUSE enabled */ |
1475 | #define ADM_XCIIS_DUPLEX 0x0100 /* full duplex */ |
1476 | #define ADM_XCIIS_SPEED 0x0200 /* 100Mb/s */ |
1477 | |
1478 | |
1479 | /* XCVR Interrupt Enable Register */ |
1480 | #define CSR_ADM_XIE 0xd8 |
1481 | /* Bits are as for XCIIS */ |
1482 | |
1483 | |
1484 | /* XCVR 100baseTX PHY Control/Status Register */ |
1485 | #define CSR_ADM_100CTR 0xdc |
1486 | #define ADM_100CTR_DISCRM 0x0001 /* disable scrambler */ |
1487 | #define ADM_100CTR_DISMLT 0x0002 /* disable MLT3 ENDEC */ |
1488 | #define ADM_100CTR_CMODE 0x001c /* current operating mode */ |
1489 | #define ADM_100CTR_CMODE_AUTO 0x0000 /* in autoneg */ |
1490 | #define ADM_100CTR_CMODE_10 0x0004 /* 10baseT */ |
1491 | #define ADM_100CTR_CMODE_100 0x0008 /* 100baseTX */ |
1492 | /* 0x000c reserved */ |
1493 | /* 0x0010 reserved */ |
1494 | #define ADM_100CTR_CMODE_10FD 0x0014 /* 10baseT-FDX */ |
1495 | #define ADM_100CTR_CMODE_100FD 0x0018 /* 100baseTX-FDX */ |
1496 | #define ADM_100CTR_CMODE_ISO 0x001c /* isolated */ |
1497 | #define ADM_100CTR_ISOTX 0x0020 /* transmit isolation */ |
1498 | #define ADM_100CTR_ENRZI 0x0080 /* enable NRZ <> NRZI conv. */ |
1499 | #define ADM_100CTR_ENDCR 0x0100 /* enable DC restoration */ |
1500 | #define ADM_100CTR_ENRLB 0x0200 /* enable remote loopback */ |
1501 | #define ADM_100CTR_RXVPP 0x0800 /* peak Rx voltage: |
1502 | 0 == 1.0 VPP |
1503 | 1 == 1.4 VPP */ |
1504 | #define ADM_100CTR_ANC 0x1000 /* autoneg completed */ |
1505 | #define ADM_100CTR_DISRER 0x2000 /* disable Rx error counter */ |
1506 | |
1507 | /* Operation Mode Register (AN983) */ |
1508 | #define CSR_ADM983_OPMODE 0xfc |
1509 | #define ADM983_OPMODE_SPEED 0x80000000 /* 1 == 100, 0 == 10 */ |
1510 | #define ADM983_OPMODE_FD 0x40000000 /* 1 == fd, 0 == hd */ |
1511 | #define ADM983_OPMODE_LINK 0x20000000 /* 1 == link, 0 == no link */ |
1512 | #define ADM983_OPMODE_EERLOD 0x04000000 /* reload from EEPROM */ |
1513 | #define ADM983_OPMODE_SingleChip 0x00000007 /* single-chip mode */ |
1514 | #define ADM983_OPMODE_MacOnly 0x00000004 /* MAC-only mode */ |
1515 | |
1516 | /* |
1517 | * Xircom X3201-3 registers |
1518 | */ |
1519 | |
1520 | /* Power Management Register */ |
1521 | #define CSR_X3201_PMR TULIP_CSR16 |
1522 | #define X3201_PMR_EDINT 0x0000000f /* energy detect interval */ |
1523 | #define X3201_PMR_EDEN 0x00000100 /* energy detect enable */ |
1524 | #define X3201_PMR_MPEN 0x00000200 /* magic packet enable */ |
1525 | #define X3201_PMR_WOLEN 0x00000400 /* Wake On Lan enable */ |
1526 | #define X3201_PMR_PMGP0EN 0x00001000 /* GP0 change enable */ |
1527 | #define X3201_PMR_PMLCEN 0x00002000 /* link change enable */ |
1528 | #define X3201_PMR_WOLTMEN 0x00008000 /* WOL template mem enable */ |
1529 | #define X3201_PMR_EP 0x00010000 /* energy present */ |
1530 | #define X3201_PMR_LP 0x00200000 /* link present */ |
1531 | #define X3201_PMR_EDES 0x01000000 /* ED event status */ |
1532 | #define X3201_PMR_MPES 0x02000000 /* MP event status */ |
1533 | #define X3201_PMR_WOLES 0x04000000 /* WOL event status */ |
1534 | #define X3201_PMR_WOLPS 0x08000000 /* WOL process status */ |
1535 | #define X3201_PMR_GP0ES 0x10000000 /* GP0 event status */ |
1536 | #define X3201_PMR_LCES 0x20000000 /* LC event status */ |
1537 | |
1538 | /* |
1539 | * Davicom DM9102 registers. |
1540 | */ |
1541 | |
1542 | /* PHY Status Register */ |
1543 | #define CSR_DM_PHYSTAT TULIP_CSR12 |
1544 | #define DM_PHYSTAT_10 0x00000001 /* 10Mb/s */ |
1545 | #define DM_PHYSTAT_100 0x00000002 /* 100Mb/s */ |
1546 | #define DM_PHYSTAT_FDX 0x00000004 /* full-duplex */ |
1547 | #define DM_PHYSTAT_LINK 0x00000008 /* link up */ |
1548 | #define DM_PHYSTAT_RXLOCK 0x00000010 /* RX-lock */ |
1549 | #define DM_PHYSTAT_SIGNAL 0x00000020 /* signal detection */ |
1550 | #define DM_PHYSTAT_UTPSIG 0x00000040 /* UTP SIG */ |
1551 | #define DM_PHYSTAT_GPED 0x00000080 /* general PHY reset control */ |
1552 | #define DM_PHYSTAT_GEPC 0x00000100 /* GPED bits control */ |
1553 | |
1554 | |
1555 | /* Sample Frame Access Register */ |
1556 | #define CSR_DM_SFAR TULIP_CSR13 |
1557 | |
1558 | |
1559 | /* Sample Frame Data Register */ |
1560 | #define CSR_DM_SFDR TULIP_CSR14 |
1561 | /* See 21143 SIAGEN register */ |
1562 | |
1563 | /* |
1564 | * ASIX AX88140A and AX88141 registers. |
1565 | */ |
1566 | |
1567 | /* CSR13 - Filtering Index */ |
1568 | #define CSR_AX_FILTIDX TULIP_CSR13 |
1569 | |
1570 | /* CSR14 - Filtering data */ |
1571 | #define CSR_AX_FILTDATA TULIP_CSR14 |
1572 | |
1573 | /* Filtering Index values */ |
1574 | #define AX_FILTIDX_PAR0 0x00000000 |
1575 | #define AX_FILTIDX_PAR1 0x00000001 |
1576 | #define AX_FILTIDX_MAR0 0x00000002 |
1577 | #define AX_FILTIDX_MAR1 0x00000003 |
1578 | |
1579 | #endif /* _DEV_IC_TULIPREG_H_ */ |
1580 | |