1 | /*- |
2 | * $NetBSD: if_lmc.h,v 1.23 2016/04/28 00:16:56 ozaki-r Exp $ |
3 | * |
4 | * Copyright (c) 2002-2006 David Boggs. (boggs@boggs.palo-alto.ca.us) |
5 | * All rights reserved. |
6 | * |
7 | * BSD LICENSE: |
8 | * |
9 | * Redistribution and use in source and binary forms, with or without |
10 | * modification, are permitted provided that the following conditions |
11 | * are met: |
12 | * 1. Redistributions of source code must retain the above copyright |
13 | * notice, this list of conditions and the following disclaimer. |
14 | * 2. Redistributions in binary form must reproduce the above copyright |
15 | * notice, this list of conditions and the following disclaimer in the |
16 | * documentation and/or other materials provided with the distribution. |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
28 | * SUCH DAMAGE. |
29 | * |
30 | * GNU GENERAL PUBLIC LICENSE: |
31 | * |
32 | * This program is free software; you can redistribute it and/or modify it |
33 | * under the terms of the GNU General Public License as published by the Free |
34 | * Software Foundation; either version 2 of the License, or (at your option) |
35 | * any later version. |
36 | * |
37 | * This program is distributed in the hope that it will be useful, but WITHOUT |
38 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
39 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
40 | * more details. |
41 | * |
42 | * You should have received a copy of the GNU General Public License along with |
43 | * this program; if not, write to the Free Software Foundation, Inc., 59 |
44 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
45 | */ |
46 | |
47 | #ifndef IF_LMC_H |
48 | #define IF_LMC_H |
49 | |
50 | #include <sys/ioccom.h> |
51 | |
52 | |
53 | #define DEVICE_NAME "lmc" |
54 | |
55 | #define VER_YEAR 2006 |
56 | #define VER_MONTH 4 |
57 | #define VER_DAY 11 |
58 | |
59 | /* netgraph stuff */ |
60 | #define NG_LMC_NODE_TYPE "if_"DEVICE_NAME |
61 | #define NGM_LMC_COOKIE 1144752198 /* date -u +'%s' */ |
62 | |
63 | /* Tulip PCI configuration registers */ |
64 | #define TLP_CFID 0x00 /* 0: CFg ID register */ |
65 | #define TLP_CFCS 0x04 /* 1: CFg Command/Status */ |
66 | #define TLP_CFRV 0x08 /* 2: CFg ReVision */ |
67 | #define TLP_CFLT 0x0C /* 3: CFg Latency Timer */ |
68 | #define TLP_CBIO 0x10 /* 4: Cfg Base IO address */ |
69 | #define TLP_CBMA 0x14 /* 5: Cfg Base Mem Addr */ |
70 | #define TLP_CSID 0x2C /* 11: Cfg Subsys ID reg */ |
71 | #define TLP_CFIT 0x3C /* 15: CFg InTerrupt */ |
72 | #define TLP_CFDD 0x40 /* 16: CFg Driver Data */ |
73 | |
74 | #define TLP_CFID_TULIP 0x00091011 /* DEC 21140A Ethernet chip */ |
75 | |
76 | #define TLP_CFCS_MSTR_ABORT 0x20000000 |
77 | #define TLP_CFCS_TARG_ABORT 0x10000000 |
78 | #define TLP_CFCS_SYS_ERROR 0x00000100 |
79 | #define TLP_CFCS_PAR_ERROR 0x00000040 |
80 | #define TLP_CFCS_MWI_ENABLE 0x00000010 |
81 | #define TLP_CFCS_BUS_MASTER 0x00000004 |
82 | #define TLP_CFCS_MEM_ENABLE 0x00000002 |
83 | #define TLP_CFCS_IO_ENABLE 0x00000001 |
84 | |
85 | #define TLP_CFLT_LATENCY 0x0000FF00 |
86 | #define TLP_CFLT_CACHE 0x000000FF |
87 | |
88 | #define CSID_LMC_HSSI 0x00031376 /* LMC 5200 HSSI card */ |
89 | #define CSID_LMC_T3 0x00041376 /* LMC 5245 T3 card */ |
90 | #define CSID_LMC_SSI 0x00051376 /* LMC 1000 SSI card */ |
91 | #define CSID_LMC_T1E1 0x00061376 /* LMC 1200 T1E1 card */ |
92 | #define CSID_LMC_HSSIc 0x00071376 /* LMC 5200 HSSI cPCI */ |
93 | #define CSID_LMC_SDSL 0x00081376 /* LMC 1168 SDSL card */ |
94 | |
95 | #define TLP_CFIT_MAX_LAT 0xFF000000 |
96 | |
97 | #define TLP_CFDD_SLEEP 0x80000000 |
98 | #define TLP_CFDD_SNOOZE 0x40000000 |
99 | |
100 | /* Tulip Control and Status Registers */ |
101 | #define TLP_CSR_STRIDE 8 /* 64 bits */ |
102 | #define TLP_BUS_MODE 0 * TLP_CSR_STRIDE |
103 | #define TLP_TX_POLL 1 * TLP_CSR_STRIDE |
104 | #define TLP_RX_POLL 2 * TLP_CSR_STRIDE |
105 | #define TLP_RX_LIST 3 * TLP_CSR_STRIDE |
106 | #define TLP_TX_LIST 4 * TLP_CSR_STRIDE |
107 | #define TLP_STATUS 5 * TLP_CSR_STRIDE |
108 | #define TLP_OP_MODE 6 * TLP_CSR_STRIDE |
109 | #define TLP_INT_ENBL 7 * TLP_CSR_STRIDE |
110 | #define TLP_MISSED 8 * TLP_CSR_STRIDE |
111 | #define TLP_SROM_MII 9 * TLP_CSR_STRIDE |
112 | #define TLP_BIOS_ROM 10 * TLP_CSR_STRIDE |
113 | #define TLP_TIMER 11 * TLP_CSR_STRIDE |
114 | #define TLP_GPIO 12 * TLP_CSR_STRIDE |
115 | #define TLP_CSR13 13 * TLP_CSR_STRIDE |
116 | #define TLP_CSR14 14 * TLP_CSR_STRIDE |
117 | #define TLP_WDOG 15 * TLP_CSR_STRIDE |
118 | #define TLP_CSR_SIZE 128 /* IO bus space size */ |
119 | |
120 | /* CSR 0 - PCI Bus Mode Register */ |
121 | #define TLP_BUS_WRITE_INVAL 0x01000000 /* DONT USE! */ |
122 | #define TLP_BUS_READ_LINE 0x00800000 |
123 | #define TLP_BUS_READ_MULT 0x00200000 |
124 | #define TLP_BUS_DESC_BIGEND 0x00100000 |
125 | #define TLP_BUS_TAP 0x000E0000 |
126 | #define TLP_BUS_CAL 0x0000C000 |
127 | #define TLP_BUS_PBL 0x00003F00 |
128 | #define TLP_BUS_DATA_BIGEND 0x00000080 |
129 | #define TLP_BUS_DSL 0x0000007C |
130 | #define TLP_BUS_ARB 0x00000002 |
131 | #define TLP_BUS_RESET 0x00000001 |
132 | #define TLP_BUS_CAL_SHIFT 14 |
133 | #define TLP_BUS_PBL_SHIFT 8 |
134 | |
135 | /* CSR 5 - Status Register */ |
136 | #define TLP_STAT_FATAL_BITS 0x03800000 |
137 | #define TLP_STAT_TX_FSM 0x00700000 |
138 | #define TLP_STAT_RX_FSM 0x000E0000 |
139 | #define TLP_STAT_FATAL_ERROR 0x00002000 |
140 | #define TLP_STAT_TX_UNDERRUN 0x00000020 |
141 | #define TLP_STAT_FATAL_SHIFT 23 |
142 | |
143 | /* CSR 6 - Operating Mode Register */ |
144 | #define TLP_OP_RECEIVE_ALL 0x40000000 |
145 | #define TLP_OP_MUST_BE_ONE 0x02000000 |
146 | #define TLP_OP_NO_HEART_BEAT 0x00080000 |
147 | #define TLP_OP_PORT_SELECT 0x00040000 |
148 | #define TLP_OP_TX_THRESH 0x0000C000 |
149 | #define TLP_OP_TX_RUN 0x00002000 |
150 | #define TLP_OP_LOOP_MODE 0x00000C00 |
151 | #define TLP_OP_EXT_LOOP 0x00000800 |
152 | #define TLP_OP_INT_LOOP 0x00000400 |
153 | #define TLP_OP_FULL_DUPLEX 0x00000200 |
154 | #define TLP_OP_PROMISCUOUS 0x00000040 |
155 | #define TLP_OP_PASS_BAD_PKT 0x00000008 |
156 | #define TLP_OP_RX_RUN 0x00000002 |
157 | #define TLP_OP_TR_SHIFT 14 |
158 | #define TLP_OP_INIT (TLP_OP_PORT_SELECT | \ |
159 | TLP_OP_FULL_DUPLEX | \ |
160 | TLP_OP_MUST_BE_ONE | \ |
161 | TLP_OP_NO_HEART_BEAT | \ |
162 | TLP_OP_RECEIVE_ALL | \ |
163 | TLP_OP_PROMISCUOUS | \ |
164 | TLP_OP_PASS_BAD_PKT | \ |
165 | TLP_OP_RX_RUN | \ |
166 | TLP_OP_TX_RUN) |
167 | |
168 | /* CSR 7 - Interrupt Enable Register */ |
169 | #define TLP_INT_NORMAL_INTR 0x00010000 |
170 | #define TLP_INT_ABNRML_INTR 0x00008000 |
171 | #define TLP_INT_FATAL_ERROR 0x00002000 |
172 | #define TLP_INT_RX_NO_BUFS 0x00000080 |
173 | #define TLP_INT_RX_INTR 0x00000040 |
174 | #define TLP_INT_TX_UNDERRUN 0x00000020 |
175 | #define TLP_INT_TX_INTR 0x00000001 |
176 | #define TLP_INT_DISABLE 0 |
177 | #define TLP_INT_TX (TLP_INT_NORMAL_INTR | \ |
178 | TLP_INT_ABNRML_INTR | \ |
179 | TLP_INT_FATAL_ERROR | \ |
180 | TLP_INT_TX_UNDERRUN | \ |
181 | TLP_INT_TX_INTR) |
182 | #define TLP_INT_RX (TLP_INT_NORMAL_INTR | \ |
183 | TLP_INT_ABNRML_INTR | \ |
184 | TLP_INT_FATAL_ERROR | \ |
185 | TLP_INT_RX_NO_BUFS | \ |
186 | TLP_INT_RX_INTR) |
187 | #define TLP_INT_TXRX (TLP_INT_TX | TLP_INT_RX) |
188 | |
189 | /* CSR 8 - RX Missed Frames & Overrun Register */ |
190 | #define TLP_MISS_OCO 0x10000000 |
191 | #define TLP_MISS_OVERRUN 0x0FFE0000 |
192 | #define TLP_MISS_MFO 0x00010000 |
193 | #define TLP_MISS_MISSED 0x0000FFFF |
194 | #define TLP_OVERRUN_SHIFT 17 |
195 | |
196 | /* CSR 9 - SROM & MII & Boot ROM Register */ |
197 | #define TLP_MII_MDIN 0x00080000 |
198 | #define TLP_MII_MDOE 0x00040000 |
199 | #define TLP_MII_MDOUT 0x00020000 |
200 | #define TLP_MII_MDC 0x00010000 |
201 | |
202 | #define TLP_BIOS_RD 0x00004000 |
203 | #define TLP_BIOS_WR 0x00002000 |
204 | #define TLP_BIOS_SEL 0x00001000 |
205 | |
206 | #define TLP_SROM_RD 0x00004000 |
207 | #define TLP_SROM_SEL 0x00000800 |
208 | #define TLP_SROM_DOUT 0x00000008 |
209 | #define TLP_SROM_DIN 0x00000004 |
210 | #define TLP_SROM_CLK 0x00000002 |
211 | #define TLP_SROM_CS 0x00000001 |
212 | |
213 | /* CSR 12 - General Purpose IO register */ |
214 | #define TLP_GPIO_DIR 0x00000100 |
215 | |
216 | /* CSR 15 - Watchdog Timer Register */ |
217 | #define TLP_WDOG_RX_OFF 0x00000010 |
218 | #define TLP_WDOG_TX_OFF 0x00000001 |
219 | #define TLP_WDOG_INIT (TLP_WDOG_TX_OFF | \ |
220 | TLP_WDOG_RX_OFF) |
221 | |
222 | /* GPIO bits common to all cards */ |
223 | #define GPIO_INIT 0x01 /* from Xilinx */ |
224 | #define GPIO_RESET 0x02 /* to Xilinx */ |
225 | /* bits 2 and 3 vary with card type -- see below */ |
226 | #define GPIO_MODE 0x10 /* to Xilinx */ |
227 | #define GPIO_DP 0x20 /* to/from Xilinx */ |
228 | #define GPIO_DATA 0x40 /* serial data */ |
229 | #define GPIO_CLK 0x80 /* serial clock */ |
230 | |
231 | /* HSSI GPIO bits */ |
232 | #define GPIO_HSSI_ST 0x04 /* send timing sense (deprecated) */ |
233 | #define GPIO_HSSI_TXCLK 0x08 /* clock source */ |
234 | |
235 | /* HSSIc GPIO bits */ |
236 | #define GPIO_HSSI_SYNTH 0x04 /* Synth osc chip select */ |
237 | #define GPIO_HSSI_DCE 0x08 /* provide clock on TXCLOCK output */ |
238 | |
239 | /* T3 GPIO bits */ |
240 | #define GPIO_T3_DAC 0x04 /* DAC chip select */ |
241 | #define GPIO_T3_INTEN 0x08 /* Framer Interupt enable */ |
242 | |
243 | /* SSI GPIO bits */ |
244 | #define GPIO_SSI_SYNTH 0x04 /* Synth osc chip select */ |
245 | #define GPIO_SSI_DCE 0x08 /* provide clock on TXCLOCK output */ |
246 | |
247 | /* T1E1 GPIO bits */ |
248 | #define GPIO_T1_INTEN 0x08 /* Framer Interupt enable */ |
249 | |
250 | /* MII register 16 bits common to all cards */ |
251 | /* NB: LEDs for HSSI & SSI are in DIFFERENT bits than for T1E1 & T3; oops */ |
252 | /* NB: CRC32 for HSSI & SSI is in DIFFERENT bit than for T1E1 & T3; oops */ |
253 | #define MII16_LED_ALL 0x0780 /* RW: LED bit mask */ |
254 | #define MII16_FIFO 0x0800 /* RW: 1=reset, 0=not reset */ |
255 | |
256 | /* MII register 16 bits for HSSI */ |
257 | #define MII16_HSSI_TA 0x0001 /* RW: host ready; host->modem */ |
258 | #define MII16_HSSI_CA 0x0002 /* RO: modem ready; modem->host */ |
259 | #define MII16_HSSI_LA 0x0004 /* RW: loopback A; host->modem */ |
260 | #define MII16_HSSI_LB 0x0008 /* RW: loopback B; host->modem */ |
261 | #define MII16_HSSI_LC 0x0010 /* RO: loopback C; modem->host */ |
262 | #define MII16_HSSI_TM 0x0020 /* RO: test mode; modem->host */ |
263 | #define MII16_HSSI_CRC32 0x0040 /* RW: CRC length 16/32 */ |
264 | #define MII16_HSSI_LED_LL 0x0080 /* RW: lower left - green */ |
265 | #define MII16_HSSI_LED_LR 0x0100 /* RW: lower right - green */ |
266 | #define MII16_HSSI_LED_UL 0x0200 /* RW: upper left - green */ |
267 | #define MII16_HSSI_LED_UR 0x0400 /* RW: upper right - red */ |
268 | #define MII16_HSSI_FIFO 0x0800 /* RW: reset fifos */ |
269 | #define MII16_HSSI_FORCECA 0x1000 /* RW: [cPCI] force CA on */ |
270 | #define MII16_HSSI_CLKMUX 0x6000 /* RW: [cPCI] TX clock selection */ |
271 | #define MII16_HSSI_LOOP 0x8000 /* RW: [cPCI] LOOP TX into RX */ |
272 | #define MII16_HSSI_MODEM 0x003F /* TA+CA+LA+LB+LC+TM */ |
273 | |
274 | /* MII register 16 bits for DS3 */ |
275 | #define MII16_DS3_ZERO 0x0001 /* RW: short/long cables */ |
276 | #define MII16_DS3_TRLBK 0x0002 /* RW: loop towards host */ |
277 | #define MII16_DS3_LNLBK 0x0004 /* RW: loop towards net */ |
278 | #define MII16_DS3_RAIS 0x0008 /* RO: LIU receive AIS (depr) */ |
279 | #define MII16_DS3_TAIS 0x0010 /* RW: LIU transmit AIS (depr) */ |
280 | #define MII16_DS3_BIST 0x0020 /* RO: LIU QRSS patt match (depr) */ |
281 | #define MII16_DS3_DLOS 0x0040 /* RO: LIU Digital LOS (depr) */ |
282 | #define MII16_DS3_LED_BLU 0x0080 /* RW: lower right - blue */ |
283 | #define MII16_DS3_LED_YEL 0x0100 /* RW: lower left - yellow */ |
284 | #define MII16_DS3_LED_RED 0x0200 /* RW: upper right - red */ |
285 | #define MII16_DS3_LED_GRN 0x0400 /* RW: upper left - green */ |
286 | #define MII16_DS3_FIFO 0x0800 /* RW: reset fifos */ |
287 | #define MII16_DS3_CRC32 0x1000 /* RW: CRC length 16/32 */ |
288 | #define MII16_DS3_SCRAM 0x2000 /* RW: payload scrambler */ |
289 | #define MII16_DS3_POLY 0x4000 /* RW: 1=Larse, 0=DigLink|Kentrox */ |
290 | #define MII16_DS3_FRAME 0x8000 /* RW: 1=stop txframe pulses */ |
291 | |
292 | /* MII register 16 bits for SSI */ |
293 | #define MII16_SSI_DTR 0x0001 /* RW: DTR host->modem */ |
294 | #define MII16_SSI_DSR 0x0002 /* RO: DSR modem->host */ |
295 | #define MII16_SSI_RTS 0x0004 /* RW: RTS host->modem */ |
296 | #define MII16_SSI_CTS 0x0008 /* RO: CTS modem->host */ |
297 | #define MII16_SSI_DCD 0x0010 /* RW: DCD modem<->host */ |
298 | #define MII16_SSI_RI 0x0020 /* RO: RI modem->host */ |
299 | #define MII16_SSI_CRC32 0x0040 /* RW: CRC length 16/32 */ |
300 | #define MII16_SSI_LED_LL 0x0080 /* RW: lower left - green */ |
301 | #define MII16_SSI_LED_LR 0x0100 /* RW: lower right - green */ |
302 | #define MII16_SSI_LED_UL 0x0200 /* RW: upper left - green */ |
303 | #define MII16_SSI_LED_UR 0x0400 /* RW: upper right - red */ |
304 | #define MII16_SSI_FIFO 0x0800 /* RW: reset fifos */ |
305 | #define MII16_SSI_LL 0x1000 /* RW: LL: host->modem */ |
306 | #define MII16_SSI_RL 0x2000 /* RW: RL: host->modem */ |
307 | #define MII16_SSI_TM 0x4000 /* RO: TM: modem->host */ |
308 | #define MII16_SSI_LOOP 0x8000 /* RW: Loop at ext conn */ |
309 | #define MII16_SSI_MODEM 0x703F /* DTR+DSR+RTS+CTS+DCD+RI+LL+RL+TM */ |
310 | |
311 | /* Mii register 17 has the SSI cable bits */ |
312 | #define MII17_SSI_CABLE_SHIFT 3 /* shift to get cable type */ |
313 | #define MII17_SSI_CABLE_MASK 0x0038 /* RO: mask to get cable type */ |
314 | #define MII17_SSI_PRESCALE 0x0040 /* RW: divide by: 0=16; 1=512 */ |
315 | #define MII17_SSI_ITF 0x0100 /* RW: fill with: 0=flags; 1=ones */ |
316 | #define MII17_SSI_NRZI 0x0400 /* RW: coding: NRZ= 0; NRZI=1 */ |
317 | |
318 | /* MII register 16 bits for T1/E1 */ |
319 | #define MII16_T1_UNUSED1 0x0001 |
320 | #define MII16_T1_INVERT 0x0002 /* RW: invert data (for SF/AMI) */ |
321 | #define MII16_T1_XOE 0x0004 /* RW: TX Output Enable; 0=disable */ |
322 | #define MII16_T1_RST 0x0008 /* RW: Bt8370 chip reset */ |
323 | #define MII16_T1_Z 0x0010 /* RW: output impedance T1=1 E1=0 */ |
324 | #define MII16_T1_INTR 0x0020 /* RO: interrupt from Bt8370 */ |
325 | #define MII16_T1_ONESEC 0x0040 /* RO: one second square wave */ |
326 | #define MII16_T1_LED_BLU 0x0080 /* RW: lower right - blue */ |
327 | #define MII16_T1_LED_YEL 0x0100 /* RW: lower left - yellow */ |
328 | #define MII16_T1_LED_RED 0x0200 /* RW: upper right - red */ |
329 | #define MII16_T1_LED_GRN 0x0400 /* RW: upper left - green */ |
330 | #define MII16_T1_FIFO 0x0800 /* RW: reset fifos */ |
331 | #define MII16_T1_CRC32 0x1000 /* RW: CRC length 16/32 */ |
332 | #define MII16_T1_UNUSED2 0xE000 |
333 | |
334 | /* T3 framer: RW=Read/Write; RO=Read-Only; RC=Read/Clr; WO=Write-Only */ |
335 | #define T3CSR_STAT0 0x00 /* RO: real-time status */ |
336 | #define T3CSR_CTL1 0x01 /* RW: global control bits */ |
337 | #define T3CSR_FEBE 0x02 /* RC: Far End Block Error Counter */ |
338 | #define T3CSR_CERR 0x03 /* RC: C-bit Parity Error Counter */ |
339 | #define T3CSR_PERR 0x04 /* RC: P-bit Parity Error Counter */ |
340 | #define T3CSR_TX_FEAC 0x05 /* RW: Far End Alarm & Control */ |
341 | #define T3CSR_RX_FEAC 0x06 /* RO: Far End Alarm & Control */ |
342 | #define T3CSR_STAT7 0x07 /* RL: latched real-time status */ |
343 | #define T3CSR_CTL8 0x08 /* RW: extended global ctl bits */ |
344 | #define T3CSR_STAT9 0x09 /* RL: extended status bits */ |
345 | #define T3CSR_FERR 0x0A /* RC: F-bit Error Counter */ |
346 | #define T3CSR_MERR 0x0B /* RC: M-bit Error Counter */ |
347 | #define T3CSR_CTL12 0x0C /* RW: more extended ctl bits */ |
348 | #define T3CSR_DBL_FEAC 0x0D /* RW: TX double FEAC */ |
349 | #define T3CSR_CTL14 0x0E /* RW: even more extended ctl bits */ |
350 | #define T3CSR_FEAC_STK 0x0F /* RO: RX FEAC stack */ |
351 | #define T3CSR_STAT16 0x10 /* RL: extended latched status */ |
352 | #define T3CSR_INTEN 0x11 /* RW: interrupt enable */ |
353 | #define T3CSR_CVLO 0x12 /* RC: coding violation cntr LSB */ |
354 | #define T3CSR_CVHI 0x13 /* RC: coding violation cntr MSB */ |
355 | #define T3CSR_CTL20 0x14 /* RW: yet more extended ctl bits */ |
356 | |
357 | #define CTL1_XTX 0x01 /* Transmit X-bit value */ |
358 | #define CTL1_3LOOP 0x02 /* framer loop back */ |
359 | #define CTL1_SER 0x04 /* SERial interface selected */ |
360 | #define CTL1_M13MODE 0x08 /* M13 frame format */ |
361 | #define CTL1_TXIDL 0x10 /* Transmit Idle signal */ |
362 | #define CTL1_ENAIS 0x20 /* Enable AIS upon LOS */ |
363 | #define CTL1_TXAIS 0x40 /* Transmit Alarm Indication Sig */ |
364 | #define CTL1_NOFEBE 0x80 /* No Far End Block Errors */ |
365 | |
366 | #define CTL5_EMODE 0x80 /* rev B Extended features enabled */ |
367 | #define CTL5_START 0x40 /* transmit the FEAC msg now */ |
368 | |
369 | #define CTL8_FBEC 0x80 /* F-Bit Error Count control */ |
370 | #define CTL8_TBLU 0x20 /* Transmit Blue signal */ |
371 | #define CTL8_OUT_DIS 0x10 /* Output Disable */ |
372 | |
373 | #define STAT9_SEF 0x80 /* Severely Errored Frame */ |
374 | #define STAT9_RBLU 0x20 /* Receive Blue signal */ |
375 | |
376 | #define CTL12_RTPLLEN 0x80 /* Rx-to-Tx Payload Lpbk Lock ENbl */ |
377 | #define CTL12_RTPLOOP 0x40 /* Rx-to-Tx Payload Loopback */ |
378 | #define CTL12_DLCB1 0x08 /* Data Link C-Bits forced to 1 */ |
379 | #define CTL12_C21 0x04 /* C2 forced to 1 */ |
380 | #define CTL12_MCB1 0x02 /* Most C-Bits forced to 1 */ |
381 | |
382 | #define CTL13_DFEXEC 0x40 /* Execute Double FEAC */ |
383 | |
384 | #define CTL14_FEAC10 0x80 /* Transmit FEAC word 10 times */ |
385 | #define CTL14_RGCEN 0x20 /* Receive Gapped Clock Out Enbl */ |
386 | #define CTL14_TGCEN 0x10 /* Timing Gen Gapped Clk Out Enbl */ |
387 | |
388 | #define FEAC_STK_MORE 0x80 /* FEAC stack has more FEACs */ |
389 | #define FEAC_STK_VALID 0x40 /* FEAC stack is valid */ |
390 | #define FEAC_STK_FEAC 0x3F /* FEAC stack FEAC data */ |
391 | |
392 | #define STAT16_XERR 0x01 /* X-bit Error */ |
393 | #define STAT16_SEF 0x02 /* Severely Errored Frame */ |
394 | #define STAT16_RTLOC 0x04 /* Rx/Tx Loss Of Clock */ |
395 | #define STAT16_FEAC 0x08 /* new FEAC msg */ |
396 | #define STAT16_RIDL 0x10 /* channel IDLe signal */ |
397 | #define STAT16_RAIS 0x20 /* Alarm Indication Signal */ |
398 | #define STAT16_ROOF 0x40 /* Out Of Frame sync */ |
399 | #define STAT16_RLOS 0x80 /* Loss Of Signal */ |
400 | |
401 | #define CTL20_CVEN 0x01 /* Coding Violation Counter Enbl */ |
402 | |
403 | /* T1.107 Bit Oriented C-Bit Parity Far End Alarm Control and Status codes */ |
404 | #define T3BOP_OOF 0x00 /* Yellow alarm status */ |
405 | #define T3BOP_LINE_UP 0x07 /* line loopback activate */ |
406 | #define T3BOP_LINE_DOWN 0x1C /* line loopback deactivate */ |
407 | #define T3BOP_LOOP_DS3 0x1B /* loopback full DS3 */ |
408 | #define T3BOP_IDLE 0x1A /* IDLE alarm status */ |
409 | #define T3BOP_AIS 0x16 /* AIS alarm status */ |
410 | #define T3BOP_LOS 0x0E /* LOS alarm status */ |
411 | |
412 | /* T1E1 regs; RW=Read/Write; RO=Read-Only; RC=Read/Clr; WO=Write-Only */ |
413 | #define Bt8370_DID 0x000 /* RO: Device ID */ |
414 | #define Bt8370_CR0 0x001 /* RW; Primary Control Register */ |
415 | #define Bt8370_JAT_CR 0x002 /* RW: Jitter Attenuator CR */ |
416 | #define Bt8370_IRR 0x003 /* RO: Interrupt Request Reg */ |
417 | #define Bt8370_ISR7 0x004 /* RC: Alarm 1 Interrupt Status */ |
418 | #define Bt8370_ISR6 0x005 /* RC: Alarm 2 Interrupt Status */ |
419 | #define Bt8370_ISR5 0x006 /* RC: Error Interrupt Status */ |
420 | #define Bt8370_ISR4 0x007 /* RC; Cntr Ovfl Interrupt Status */ |
421 | #define Bt8370_ISR3 0x008 /* RC: Timer Interrupt Status */ |
422 | #define Bt8370_ISR2 0x009 /* RC: Data Link 1 Int Status */ |
423 | #define Bt8370_ISR1 0x00A /* RC: Data Link 2 Int Status */ |
424 | #define Bt8370_ISR0 0x00B /* RC: Pattrn Interrupt Status */ |
425 | #define Bt8370_IER7 0x00C /* RW: Alarm 1 Interrupt Enable */ |
426 | #define Bt8370_IER6 0x00D /* RW: Alarm 2 Interrupt Enable */ |
427 | #define Bt8370_IER5 0x00E /* RW: Error Interrupt Enable */ |
428 | #define Bt8370_IER4 0x00F /* RW: Cntr Ovfl Interrupt Enable */ |
429 | |
430 | #define Bt8370_IER3 0x010 /* RW: Timer Interrupt Enable */ |
431 | #define Bt8370_IER2 0x011 /* RW: Data Link 1 Int Enable */ |
432 | #define Bt8370_IER1 0x012 /* RW: Data Link 2 Int Enable */ |
433 | #define Bt8370_IER0 0x013 /* RW: Pattern Interrupt Enable */ |
434 | #define Bt8370_LOOP 0x014 /* RW: Loopback Config Reg */ |
435 | #define Bt8370_DL3_TS 0x015 /* RW: External Data Link Channel */ |
436 | #define Bt8370_DL3_BIT 0x016 /* RW: External Data Link Bit */ |
437 | #define Bt8370_FSTAT 0x017 /* RO: Offline Framer Status */ |
438 | #define Bt8370_PIO 0x018 /* RW: Programmable Input/Output */ |
439 | #define Bt8370_POE 0x019 /* RW: Programmable Output Enable */ |
440 | #define Bt8370_CMUX 0x01A /* RW: Clock Input Mux */ |
441 | #define Bt8370_TMUX 0x01B /* RW: Test Mux Config */ |
442 | #define Bt8370_TEST 0x01C /* RW: Test Config */ |
443 | |
444 | #define Bt8370_LIU_CR 0x020 /* RW: Line Intf Unit Config Reg */ |
445 | #define Bt8370_RSTAT 0x021 /* RO; Receive LIU Status */ |
446 | #define Bt8370_RLIU_CR 0x022 /* RW: Receive LIU Config */ |
447 | #define Bt8370_LPF 0x023 /* RW: RPLL Low Pass Filter */ |
448 | #define Bt8370_VGA_MAX 0x024 /* RW: Variable Gain Amplifier Max */ |
449 | #define Bt8370_EQ_DAT 0x025 /* RW: Equalizer Coeff Data Reg */ |
450 | #define Bt8370_EQ_PTR 0x026 /* RW: Equzlizer Coeff Table Ptr */ |
451 | #define Bt8370_DSLICE 0x027 /* RW: Data Slicer Threshold */ |
452 | #define Bt8370_EQ_OUT 0x028 /* RW: Equalizer Output Levels */ |
453 | #define Bt8370_VGA 0x029 /* RO: Variable Gain Ampl Status */ |
454 | #define Bt8370_PRE_EQ 0x02A /* RW: Pre-Equalizer */ |
455 | |
456 | #define Bt8370_COEFF0 0x030 /* RO: LMS Adj Eq Coeff Status */ |
457 | #define Bt8370_GAIN0 0x038 /* RW: Equalizer Gain Thresh */ |
458 | #define Bt8370_GAIN1 0x039 /* RW: Equalizer Gain Thresh */ |
459 | #define Bt8370_GAIN2 0x03A /* RW: Equalizer Gain Thresh */ |
460 | #define Bt8370_GAIN3 0x03B /* RW: Equalizer Gain Thresh */ |
461 | #define Bt8370_GAIN4 0x03C /* RW: Equalizer Gain Thresh */ |
462 | |
463 | #define Bt8370_RCR0 0x040 /* RW: Rx Configuration */ |
464 | #define Bt8370_RPATT 0x041 /* RW: Rx Test Pattern Config */ |
465 | #define Bt8370_RLB 0x042 /* RW: Rx Loopback Code Detr Conf */ |
466 | #define Bt8370_LBA 0x043 /* RW: Loopback Activate Code Patt */ |
467 | #define Bt8370_LBD 0x044 /* RW: Loopback Deact Code Patt */ |
468 | #define Bt8370_RALM 0x045 /* RW: Rx Alarm Signal Config */ |
469 | #define Bt8370_LATCH 0x046 /* RW: Alarm/Err/Cntr Latch Config */ |
470 | #define Bt8370_ALM1 0x047 /* RO: Alarm 1 Status */ |
471 | #define Bt8370_ALM2 0x048 /* RO: Alarm 2 Status */ |
472 | #define Bt8370_ALM3 0x049 /* RO: Alarm 3 Status */ |
473 | |
474 | #define Bt8370_FERR_LO 0x050 /* RC: Framing Bit Error Cntr LSB */ |
475 | #define Bt8370_FERR_HI 0x051 /* RC: Framing Bit Error Cntr MSB */ |
476 | #define Bt8370_CRC_LO 0x052 /* RC: CRC Error Counter LSB */ |
477 | #define Bt8370_CRC_HI 0x053 /* RC: CRC Error Counter MSB */ |
478 | #define Bt8370_LCV_LO 0x054 /* RC: Line Code Viol Counter LSB */ |
479 | #define Bt8370_LCV_HI 0x055 /* RC: Line Code Viol Counter MSB */ |
480 | #define Bt8370_FEBE_LO 0x056 /* RC: Far End Block Err Cntr LSB */ |
481 | #define Bt8370_FEBE_HI 0x057 /* RC: Far End Block Err Cntr MSB */ |
482 | #define Bt8370_BERR_LO 0x058 /* RC: PRBS Bit Error Counter LSB */ |
483 | #define Bt8370_BERR_HI 0x059 /* RC: PRBS Bit Error Counter MSB */ |
484 | #define Bt8370_AERR 0x05A /* RC: SEF/LOF/COFA counter */ |
485 | #define Bt8370_RSA4 0x05B /* RO: Rx Sa4 Byte Buffer */ |
486 | #define Bt8370_RSA5 0x05C /* RO: Rx Sa5 Byte Buffer */ |
487 | #define Bt8370_RSA6 0x05D /* RO: Rx Sa6 Byte Buffer */ |
488 | #define Bt8370_RSA7 0x05E /* RO: Rx Sa7 Byte Buffer */ |
489 | #define Bt8370_RSA8 0x05F /* RO: Rx Sa8 Byte Buffer */ |
490 | |
491 | #define Bt8370_SHAPE0 0x060 /* RW: Tx Pulse Shape Config */ |
492 | #define Bt8370_TLIU_CR 0x068 /* RW: Tx LIU Config Reg */ |
493 | |
494 | #define Bt8370_TCR0 0x070 /* RW: Tx Framer Config */ |
495 | #define Bt8370_TCR1 0x071 /* RW: Txter Configuration */ |
496 | #define Bt8370_TFRM 0x072 /* RW: Tx Frame Format */ |
497 | #define Bt8370_TERROR 0x073 /* RW: Tx Error Insert */ |
498 | #define Bt8370_TMAN 0x074 /* RW: Tx Manual Sa/FEBE Config */ |
499 | #define Bt8370_TALM 0x075 /* RW: Tx Alarm Signal Config */ |
500 | #define Bt8370_TPATT 0x076 /* RW: Tx Test Pattern Config */ |
501 | #define Bt8370_TLB 0x077 /* RW: Tx Inband Loopback Config */ |
502 | #define Bt8370_LBP 0x078 /* RW: Tx Inband Loopback Patt */ |
503 | #define Bt8370_TSA4 0x07B /* RW: Tx Sa4 Byte Buffer */ |
504 | #define Bt8370_TSA5 0x07C /* RW: Tx Sa5 Byte Buffer */ |
505 | #define Bt8370_TSA6 0x07D /* RW: Tx Sa6 Byte Buffer */ |
506 | #define Bt8370_TSA7 0x07E /* RW: Tx Sa7 Byte Buffer */ |
507 | #define Bt8370_TSA8 0x07F /* RW: Tx Sa8 Byte Buffer */ |
508 | |
509 | #define Bt8370_CLAD_CR 0x090 /* RW: Clock Rate Adapter Config */ |
510 | #define Bt8370_CSEL 0x091 /* RW: CLAD Frequency Select */ |
511 | #define Bt8370_CPHASE 0x092 /* RW: CLAD Phase Det Scale Factor */ |
512 | #define Bt8370_CTEST 0x093 /* RW: CLAD Test */ |
513 | |
514 | #define Bt8370_BOP 0x0A0 /* RW: Bit Oriented Protocol Xcvr */ |
515 | #define Bt8370_TBOP 0x0A1 /* RW: Tx BOP Codeword */ |
516 | #define Bt8370_RBOP 0x0A2 /* RO; Rx BOP Codeword */ |
517 | #define Bt8370_BOP_STAT 0x0A3 /* RO: BOP Status */ |
518 | #define Bt8370_DL1_TS 0x0A4 /* RW: DL1 Time Slot Enable */ |
519 | #define Bt8370_DL1_BIT 0x0A5 /* RW: DL1 Bit Enable */ |
520 | #define Bt8370_DL1_CTL 0x0A6 /* RW: DL1 Control */ |
521 | #define Bt8370_RDL1_FFC 0x0A7 /* RW: RDL1 FIFO Fill Control */ |
522 | #define Bt8370_RDL1 0x0A8 /* RO: RDL1 FIFO */ |
523 | #define Bt8370_RDL1_STAT 0x0A9 /* RO: RDL1 Status */ |
524 | #define Bt8370_PRM 0x0AA /* RW: Performance Report Message */ |
525 | #define Bt8370_TDL1_FEC 0x0AB /* RW: TDL1 FIFO Empty Control */ |
526 | #define Bt8370_TDL1_EOM 0x0AC /* WO: TDL1 End Of Message Control */ |
527 | #define Bt8370_TDL1 0x0AD /* RW: TDL1 FIFO */ |
528 | #define Bt8370_TDL1_STAT 0x0AE /* RO: TDL1 Status */ |
529 | #define Bt8370_DL2_TS 0x0AF /* RW: DL2 Time Slot Enable */ |
530 | |
531 | #define Bt8370_DL2_BIT 0x0B0 /* RW: DL2 Bit Enable */ |
532 | #define Bt8370_DL2_CTL 0x0B1 /* RW: DL2 Control */ |
533 | #define Bt8370_RDL2_FFC 0x0B2 /* RW: RDL2 FIFO Fill Control */ |
534 | #define Bt8370_RDL2 0x0B3 /* RO: RDL2 FIFO */ |
535 | #define Bt8370_RDL2_STAT 0x0B4 /* RO: RDL2 Status */ |
536 | #define Bt8370_TDL2_FEC 0x0B6 /* RW: TDL2 FIFO Empty Control */ |
537 | #define Bt8370_TDL2_EOM 0x0B7 /* WO; TDL2 End Of Message Control */ |
538 | #define Bt8370_TDL2 0x0B8 /* RW: TDL2 FIFO */ |
539 | #define Bt8370_TDL2_STAT 0x0B9 /* RO: TDL2 Status */ |
540 | #define Bt8370_DL_TEST1 0x0BA /* RW: DLINK Test Config */ |
541 | #define Bt8370_DL_TEST2 0x0BB /* RW: DLINK Test Status */ |
542 | #define Bt8370_DL_TEST3 0x0BC /* RW: DLINK Test Status */ |
543 | #define Bt8370_DL_TEST4 0x0BD /* RW: DLINK Test Control */ |
544 | #define Bt8370_DL_TEST5 0x0BE /* RW: DLINK Test Control */ |
545 | |
546 | #define Bt8370_SBI_CR 0x0D0 /* RW: System Bus Interface Config */ |
547 | #define Bt8370_RSB_CR 0x0D1 /* RW: Rx System Bus Config */ |
548 | #define Bt8370_RSYNC_BIT 0x0D2 /* RW: Rx System Bus Sync Bit Offs */ |
549 | #define Bt8370_RSYNC_TS 0x0D3 /* RW: Rx System Bus Sync TS Offs */ |
550 | #define Bt8370_TSB_CR 0x0D4 /* RW: Tx System Bus Config */ |
551 | #define Bt8370_TSYNC_BIT 0x0D5 /* RW: Tx System Bus Sync Bit OFfs */ |
552 | #define Bt8370_TSYNC_TS 0x0D6 /* RW: Tx System Bus Sync TS Offs */ |
553 | #define Bt8370_RSIG_CR 0x0D7 /* RW: Rx Siganalling Config */ |
554 | #define Bt8370_RSYNC_FRM 0x0D8 /* RW: Sig Reinsertion Frame Offs */ |
555 | #define Bt8370_SSTAT 0x0D9 /* RO: Slip Buffer Status */ |
556 | #define Bt8370_STACK 0x0DA /* RO: Rx Signalling Stack */ |
557 | #define Bt8370_RPHASE 0x0DB /* RO: RSLIP Phase Status */ |
558 | #define Bt8370_TPHASE 0x0DC /* RO: TSLIP Phase Status */ |
559 | #define Bt8370_PERR 0x0DD /* RO: RAM Parity Status */ |
560 | |
561 | #define Bt8370_SBCn 0x0E0 /* RW: System Bus Per-Channel Ctl */ |
562 | #define Bt8370_TPCn 0x100 /* RW: Tx Per-Channel Control */ |
563 | #define Bt8370_TSIGn 0x120 /* RW: Tx Signalling Buffer */ |
564 | #define Bt8370_TSLIP_LOn 0x140 /* RW: Tx PCM Slip Buffer Lo */ |
565 | #define Bt8370_TSLIP_HIn 0x160 /* RW: Tx PCM Slip Buffer Hi */ |
566 | #define Bt8370_RPCn 0x180 /* RW: Rx Per-Channel Control */ |
567 | #define Bt8370_RSIGn 0x1A0 /* RW: Rx Signalling Buffer */ |
568 | #define Bt8370_RSLIP_LOn 0x1C0 /* RW: Rx PCM Slip Buffer Lo */ |
569 | #define Bt8370_RSLIP_HIn 0x1E0 /* RW: Rx PCM Slip Buffer Hi */ |
570 | |
571 | /* Bt8370_LOOP (0x14) framer loopback control register bits */ |
572 | #define LOOP_ANALOG 0x01 /* inward loop thru LIU */ |
573 | #define LOOP_FRAMER 0x02 /* inward loop thru framer */ |
574 | #define LOOP_LINE 0x04 /* outward loop thru LIU */ |
575 | #define LOOP_PAYLOAD 0x08 /* outward loop of payload */ |
576 | #define LOOP_DUAL 0x06 /* inward framer + outward line */ |
577 | |
578 | /* Bt8370_ALM1 (0x47) receiver alarm status register bits */ |
579 | #define ALM1_SIGFRZ 0x01 /* Rx Signalling Freeze */ |
580 | #define ALM1_RLOF 0x02 /* Rx loss of frame alignment */ |
581 | #define ALM1_RLOS 0x04 /* Rx digital loss of signal */ |
582 | #define ALM1_RALOS 0x08 /* Rx analog loss of signal */ |
583 | #define ALM1_RAIS 0x10 /* Rx Alarm Indication Signal */ |
584 | #define ALM1_RYEL 0x40 /* Rx Yellow alarm indication */ |
585 | #define ALM1_RMYEL 0x80 /* Rx multiframe YELLOW alarm */ |
586 | |
587 | /* Bt8370_ALM3 (0x49) receive framer status register bits */ |
588 | #define ALM3_FRED 0x04 /* Rx Out Of T1/FAS alignment */ |
589 | #define ALM3_MRED 0x08 /* Rx Out Of MFAS alignment */ |
590 | #define ALM3_SRED 0x10 /* Rx Out Of CAS alignment */ |
591 | #define ALM3_SEF 0x20 /* Rx Severely Errored Frame */ |
592 | #define ALM3_RMAIS 0x40 /* Rx TS16 AIS (CAS) */ |
593 | |
594 | /* Bt8370_TALM (0x75) transmit alarm control register bits */ |
595 | #define TALM_TAIS 0x01 /* Tx Alarm Indication Signal */ |
596 | #define TALM_TYEL 0x02 /* Tx Yellow alarm */ |
597 | #define TALM_TMYEL 0x04 /* Tx Multiframe Yellow alarm */ |
598 | #define TALM_AUTO_AIS 0x08 /* auto send AIS on LOS */ |
599 | #define TALM_AUTO_YEL 0x10 /* auto send YEL on LOF */ |
600 | #define TALM_AUTO_MYEL 0x20 /* auto send E1-Y16 on loss-of-CAS */ |
601 | |
602 | /* 8370 BOP (Bit Oriented Protocol) command fragments */ |
603 | #define RBOP_OFF 0x00 /* BOP Rx disabled */ |
604 | #define RBOP_25 0xE0 /* BOP Rx requires 25 BOPs */ |
605 | #define TBOP_OFF 0x00 /* BOP Tx disabled */ |
606 | #define TBOP_25 0x0B /* BOP Tx sends 25 BOPs */ |
607 | #define TBOP_CONT 0x0F /* BOP Tx sends continuously */ |
608 | |
609 | /* T1.403 Bit-Oriented ESF Data-Link Message codes */ |
610 | #define T1BOP_OOF 0x00 /* Yellow alarm status */ |
611 | #define T1BOP_LINE_UP 0x07 /* line loopback activate */ |
612 | #define T1BOP_LINE_DOWN 0x1C /* line loopback deactivate */ |
613 | #define T1BOP_PAY_UP 0x0A /* payload loopback activate */ |
614 | #define T1BOP_PAY_DOWN 0x19 /* payload loopback deactivate */ |
615 | #define T1BOP_NET_UP 0x09 /* network loopback activate */ |
616 | #define T1BOP_NET_DOWN 0x12 /* network loopback deactivate */ |
617 | |
618 | /* Unix & Linux reserve 16 device-private IOCTLs */ |
619 | #if BSD |
620 | # define LMCIOCGSTAT _IOWR('i', 240, struct status) |
621 | # define LMCIOCGCFG _IOWR('i', 241, struct config) |
622 | # define LMCIOCSCFG _IOW('i', 242, struct config) |
623 | # define LMCIOCREAD _IOWR('i', 243, struct ioctl) |
624 | # define LMCIOCWRITE _IOW('i', 244, struct ioctl) |
625 | # define LMCIOCTL _IOWR('i', 245, struct ioctl) |
626 | #endif |
627 | |
628 | struct iohdr /* all LMCIOCs begin with this */ |
629 | { |
630 | char ifname[IFNAMSIZ]; /* interface name, e.g. "lmc0" */ |
631 | u_int32_t cookie; /* interface version number */ |
632 | u_int16_t direction; /* missing in Linux IOCTL */ |
633 | u_int16_t length; /* missing in Linux IOCTL */ |
634 | struct iohdr *iohdr; /* missing in Linux IOCTL */ |
635 | u_int32_t spare; /* pad this struct to **32 bytes** */ |
636 | }; |
637 | |
638 | #define DIR_IO 0 |
639 | #define DIR_IOW 1 /* copy data user->kernel */ |
640 | #define DIR_IOR 2 /* copy data kernel->user */ |
641 | #define DIR_IOWR 3 /* copy data kernel<->user */ |
642 | |
643 | struct hssi_snmp |
644 | { |
645 | u_int16_t sigs; /* MII16_HSSI & MII16_HSSI_MODEM */ |
646 | }; |
647 | |
648 | struct ssi_snmp |
649 | { |
650 | u_int16_t sigs; /* MII16_SSI & MII16_SSI_MODEM */ |
651 | }; |
652 | |
653 | struct t3_snmp |
654 | { |
655 | u_int16_t febe; /* 8 bits - Far End Block err cnt */ |
656 | u_int16_t lcv; /* 16 bits - BPV err cnt */ |
657 | u_int16_t pcv; /* 8 bits - P-bit err cnt */ |
658 | u_int16_t ccv; /* 8 bits - C-bit err cnt */ |
659 | u_int16_t line; /* line status bit vector */ |
660 | u_int16_t loop; /* loop status bit vector */ |
661 | }; |
662 | |
663 | struct t1_snmp |
664 | { |
665 | u_int16_t prm[4]; /* T1.403 Performance Report Msg */ |
666 | u_int16_t febe; /* 10 bits - E1 FAR CRC err cnt */ |
667 | u_int16_t lcv; /* 16 bits - BPV + EXZ err cnt */ |
668 | u_int16_t fe; /* 12 bits - Ft/Fs/FPS/FAS err cnt */ |
669 | u_int16_t crc; /* 10 bits - CRC6/CRC4 err cnt */ |
670 | u_int16_t line; /* line status bit vector */ |
671 | u_int16_t loop; /* loop status bit vector */ |
672 | }; |
673 | |
674 | /* SNMP trunk MIB Send codes */ |
675 | #define TSEND_NORMAL 1 /* Send data (normal or looped) */ |
676 | #define TSEND_LINE 2 /* Send 'line loopback activate' */ |
677 | #define TSEND_PAYLOAD 3 /* Send 'payload loop activate' */ |
678 | #define TSEND_RESET 4 /* Send 'loopback deactivate' */ |
679 | #define TSEND_QRS 5 /* Send Quasi Random Signal */ |
680 | |
681 | /* ANSI T1.403 Performance Report Msg -- once a second from the far end */ |
682 | #define T1PRM_FE 0x8000 /* Frame Sync Bit Error Event >= 1 */ |
683 | #define T1PRM_SE 0x4000 /* Severely Err Framing Event >= 1 */ |
684 | #define T1PRM_LB 0x2000 /* Payload Loopback Activated */ |
685 | #define T1PRM_G1 0x1000 /* CRC Error Event = 1 */ |
686 | #define T1PRM_R 0x0800 /* Reserved */ |
687 | #define T1PRM_G2 0x0400 /* 1 < CRC Error Event <= 5 */ |
688 | #define T1PRM_SEQ 0x0300 /* modulo 4 counter */ |
689 | #define T1PRM_G3 0x0080 /* 5 < CRC Error Event <= 10 */ |
690 | #define T1PRM_LV 0x0040 /* Line Code Violation Event >= 1 */ |
691 | #define T1PRM_G4 0x0020 /* 10 < CRC Error Event <= 100 */ |
692 | #define T1PRM_U 0x0018 /* Under study for synchronization */ |
693 | #define T1PRM_G5 0x0004 /* 100 < CRC Error Event <= 319 */ |
694 | #define T1PRM_SL 0x0002 /* Slip Event >= 1 */ |
695 | #define T1PRM_G6 0x0001 /* CRC Error Event >= 320 */ |
696 | |
697 | /* SNMP Line Status */ |
698 | #define TLINE_NORM 0x0001 /* no alarm present */ |
699 | #define TLINE_RX_RAI 0x0002 /* receiving RAI = Yellow alarm */ |
700 | #define TLINE_TX_RAI 0x0004 /* sending RAI = Yellow alarm */ |
701 | #define TLINE_RX_AIS 0x0008 /* receiving AIS = blue alarm */ |
702 | #define TLINE_TX_AIS 0x0010 /* sending AIS = blue alarm */ |
703 | #define TLINE_LOF 0x0020 /* near end LOF = red alarm */ |
704 | #define TLINE_LOS 0x0040 /* near end loss of Signal */ |
705 | #define TLINE_LOOP 0x0080 /* near end is looped */ |
706 | #define T1LINE_RX_TS16_AIS 0x0100 /* near end receiving TS16 AIS */ |
707 | #define T1LINE_RX_TS16_LOMF 0x0200 /* near end sending TS16 LOMF */ |
708 | #define T1LINE_TX_TS16_LOMF 0x0400 /* near end receiving TS16 LOMF */ |
709 | #define T1LINE_RX_TEST 0x0800 /* near end receiving QRS Signal */ |
710 | #define T1LINE_SEF 0x1000 /* near end severely errored frame */ |
711 | #define T3LINE_RX_IDLE 0x0100 /* near end receiving IDLE signal */ |
712 | #define T3LINE_SEF 0x0200 /* near end severely errored frame */ |
713 | |
714 | /* SNMP Loopback Status */ |
715 | #define TLOOP_NONE 0x01 /* no loopback */ |
716 | #define TLOOP_NEAR_PAYLOAD 0x02 /* near end payload loopback */ |
717 | #define TLOOP_NEAR_LINE 0x04 /* near end line loopback */ |
718 | #define TLOOP_NEAR_OTHER 0x08 /* near end looped somehow */ |
719 | #define TLOOP_NEAR_INWARD 0x10 /* near end looped inward */ |
720 | #define TLOOP_FAR_PAYLOAD 0x20 /* far end payload loopback */ |
721 | #define TLOOP_FAR_LINE 0x40 /* far end line loopback */ |
722 | |
723 | /* event counters record interesting statistics */ |
724 | struct cntrs |
725 | { |
726 | struct timeval reset_time; /* time when cntrs were reset */ |
727 | u_int64_t ibytes; /* Rx bytes with good status */ |
728 | u_int64_t obytes; /* Tx bytes */ |
729 | u_int64_t ipackets; /* Rx packets with good status */ |
730 | u_int64_t opackets; /* Tx packets */ |
731 | u_int32_t ierrors; /* Rx packets with bad status */ |
732 | u_int32_t oerrors; /* Tx packets with bad status */ |
733 | u_int32_t idrops; /* Rx packets dropped by SW */ |
734 | u_int32_t missed; /* Rx pkts missed: no DMA descs */ |
735 | u_int32_t odrops; /* Tx packets dropped by SW */ |
736 | u_int32_t fifo_over; /* Rx fifo overruns from DMA desc */ |
737 | u_int32_t overruns; /* Rx fifo overruns from CSR */ |
738 | u_int32_t fifo_under; /* Tx fifo underruns from DMA desc */ |
739 | u_int32_t underruns; /* Rx fifo underruns from CSR */ |
740 | u_int32_t fdl_pkts; /* Rx T1 Facility Data Link pkts */ |
741 | u_int32_t crc_errs; /* Rx T1 frame CRC errors */ |
742 | u_int32_t lcv_errs; /* Rx T1 T3 Line Coding Violation */ |
743 | u_int32_t frm_errs; /* Rx T1 T3 Frame bit errors */ |
744 | u_int32_t febe_errs; /* Rx T1 T3 Far End Bit Errors */ |
745 | u_int32_t par_errs; /* Rx T3 P-bit parity errors */ |
746 | u_int32_t cpar_errs; /* Rx T3 C-bit parity errors */ |
747 | u_int32_t mfrm_errs; /* Rx T3 Multi-frame bit errors */ |
748 | u_int32_t rxbuf; /* Rx out of packet buffers */ |
749 | u_int32_t txdma; /* Tx out of DMA desciptors */ |
750 | u_int32_t lck_watch; /* lock conflict in watchdog */ |
751 | u_int32_t lck_intr; /* lock conflict in interrupt */ |
752 | u_int32_t spare1; /* debugging temp */ |
753 | u_int32_t spare2; /* debugging temp */ |
754 | u_int32_t spare3; /* debugging temp */ |
755 | u_int32_t spare4; /* debugging temp */ |
756 | }; |
757 | |
758 | /* sc->status is the READ ONLY status of the card. */ |
759 | /* Accessed using socket IO control calls or netgraph control messages. */ |
760 | struct status |
761 | { |
762 | struct iohdr iohdr; /* common ioctl header */ |
763 | u_int32_t card_type; /* PCI device number */ |
764 | u_int16_t link_state; /* actual state: up, down, test */ |
765 | u_int32_t tx_speed; /* measured TX bits/sec */ |
766 | u_int32_t cable_type; /* SSI only: cable type */ |
767 | u_int32_t time_slots; /* T1E1 only: actual TSs in use */ |
768 | u_int32_t stack; /* actual line stack in use */ |
769 | u_int32_t proto; /* actual line proto in use */ |
770 | u_int32_t keep_alive; /* actual keep-alive status */ |
771 | u_int32_t ticks; /* incremented by watchdog @ 1 Hz */ |
772 | struct cntrs cntrs; /* event counters */ |
773 | union |
774 | { |
775 | struct hssi_snmp hssi; /* data for RFC-???? HSSI MIB */ |
776 | struct t3_snmp t3; /* data for RFC-2496 T3 MIB */ |
777 | struct ssi_snmp ssi; /* data for RFC-1659 RS232 MIB */ |
778 | struct t1_snmp t1; /* data for RFC-2495 T1 MIB */ |
779 | } snmp; |
780 | }; |
781 | |
782 | /* protocol stack codes */ |
783 | #define STACK_NONE 0 /* not set fnobl */ |
784 | #define STACK_RAWIP 1 /* driver yyyyy */ |
785 | #define STACK_SPPP 2 /* fbsd, nbsd, obsd yyynn */ |
786 | #define STACK_P2P 3 /* bsd/os nnnyn */ |
787 | #define STACK_GEN_HDLC 4 /* linux nnnny */ |
788 | #define STACK_SYNC_PPP 5 /* linux nnnny */ |
789 | #define STACK_NETGRAPH 6 /* fbsd ynnnn */ |
790 | |
791 | /* line protocol codes */ |
792 | #define PROTO_NONE 0 /* not set fnobl */ |
793 | #define PROTO_IP_HDLC 1 /* raw IP4/6 pkts in HDLC yyyyy */ |
794 | #define PROTO_PPP 2 /* Point-to-Point Protocol yyyyy */ |
795 | #define PROTO_C_HDLC 3 /* Cisco HDLC Protocol yyyyy */ |
796 | #define PROTO_FRM_RLY 4 /* Frame Relay Protocol ynnyy */ |
797 | #define PROTO_ETH_HDLC 5 /* raw Ether pkts in HDLC nnnny */ |
798 | #define PROTO_X25 6 /* X.25/LAPB Protocol nnnny */ |
799 | |
800 | /* oper_status codes (same as SNMP status codes) */ |
801 | #define STATE_UP 1 /* may/will tx/rx pkts */ |
802 | #define STATE_DOWN 2 /* can't/won't tx/rx pkts */ |
803 | #define STATE_TEST 3 /* currently not used */ |
804 | |
805 | struct synth /* programmable oscillator params */ |
806 | { |
807 | unsigned n:7; /* numerator (3..127) */ |
808 | unsigned m:7; /* denominator (3..127) */ |
809 | unsigned v:1; /* mul by 1|8 */ |
810 | unsigned x:2; /* div by 1|2|4|8 */ |
811 | unsigned r:2; /* div by 1|2|4|8 */ |
812 | unsigned prescale:13; /* log(final divisor): 2, 4 or 9 */ |
813 | } __packed; |
814 | |
815 | #define SYNTH_FREF 20e6 /* reference xtal = 20 MHz */ |
816 | #define SYNTH_FMIN 50e6 /* internal VCO min 50 MHz */ |
817 | #define SYNTH_FMAX 250e6 /* internal VCO max 250 MHz */ |
818 | |
819 | /* sc->config is the READ/WRITE configuration of the card. */ |
820 | /* Accessed using socket IO control calls or netgraph control messages. */ |
821 | struct config |
822 | { |
823 | struct iohdr iohdr; /* common ioctl header */ |
824 | u_int32_t crc_len; /* ALL: CRC-16 or CRC-32 or none */ |
825 | u_int32_t loop_back; /* ALL: many kinds of loopbacks */ |
826 | u_int32_t tx_clk_src; /* T1, HSSI: ST, RT, int, ext */ |
827 | u_int32_t format; /* T3, T1: ckt framing format */ |
828 | u_int32_t time_slots; /* T1: 64Kb time slot config */ |
829 | u_int32_t cable_len; /* T3, T1: cable length in meters */ |
830 | u_int32_t scrambler; /* T3: payload scrambler config */ |
831 | u_int32_t dte_dce; /* SSI, HSSIc: drive TXCLK */ |
832 | struct synth synth; /* SSI, HSSIc: synth oscil params */ |
833 | u_int32_t rx_gain_max; /* T1: receiver gain limit 0-50 dB */ |
834 | u_int32_t tx_pulse; /* T1: transmitter pulse shape */ |
835 | u_int32_t tx_lbo; /* T1: transmitter atten 0-22.5 dB */ |
836 | u_int32_t debug; /* ALL: extra printout */ |
837 | u_int32_t stack; /* ALL: use this line stack */ |
838 | u_int32_t proto; /* ALL: use this line proto */ |
839 | u_int32_t keep_alive; /* SPPP: use keep-alive packets */ |
840 | }; |
841 | |
842 | #define CFG_CRC_0 0 /* no CRC */ |
843 | #define CFG_CRC_16 2 /* X^16+X^12+X^5+1 (default) */ |
844 | #define CFG_CRC_32 4 /* X^32+X^26+X^23+X^22+X^16+X^12+ */ |
845 | /* X^11+X^10+X^8+X^7+X^5+X^4+X^2+X+1 */ |
846 | #define CFG_LOOP_NONE 1 /* SNMP don't loop back anything */ |
847 | #define CFG_LOOP_PAYLOAD 2 /* SNMP loop outward thru framer */ |
848 | #define CFG_LOOP_LINE 3 /* SNMP loop outward thru LIU */ |
849 | #define CFG_LOOP_OTHER 4 /* SNMP loop inward thru LIU */ |
850 | #define CFG_LOOP_INWARD 5 /* SNMP loop inward thru framer */ |
851 | #define CFG_LOOP_DUAL 6 /* SNMP loop inward & outward */ |
852 | #define CFG_LOOP_TULIP 16 /* ALL: loop inward thru Tulip */ |
853 | #define CFG_LOOP_PINS 17 /* HSSIc, SSI: loop inward-pins */ |
854 | #define CFG_LOOP_LL 18 /* HSSI, SSI: assert LA/LL mdm pin */ |
855 | #define CFG_LOOP_RL 19 /* HSSI, SSI: assert LB/RL mdm pin */ |
856 | |
857 | #define CFG_CLKMUX_ST 1 /* TX clk <- Send timing */ |
858 | #define CFG_CLKMUX_INT 2 /* TX clk <- internal source */ |
859 | #define CFG_CLKMUX_RT 3 /* TX clk <- Receive (loop) timing */ |
860 | #define CFG_CLKMUX_EXT 4 /* TX clk <- ext connector */ |
861 | |
862 | /* values 0-31 are Bt8370 CR0 register values (LSB is zero if E1). */ |
863 | /* values 32-99 are reserved for other T1E1 formats, (even number if E1) */ |
864 | /* values 100 and up are used for T3 frame formats. */ |
865 | #define CFG_FORMAT_T1SF 9 /* T1-SF AMI */ |
866 | #define CFG_FORMAT_T1ESF 27 /* T1-ESF+CRC B8ZS X^6+X+1 */ |
867 | #define CFG_FORMAT_E1FAS 0 /* E1-FAS HDB3 TS0 */ |
868 | #define CFG_FORMAT_E1FASCRC 8 /* E1-FAS+CRC HDB3 TS0 X^4+X+1 */ |
869 | #define CFG_FORMAT_E1FASCAS 16 /* E1-FAS +CAS HDB3 TS0 & TS16 */ |
870 | #define CFG_FORMAT_E1FASCRCCAS 24 /* E1-FAS+CRC+CAS HDB3 TS0 & TS16 */ |
871 | #define CFG_FORMAT_E1NONE 32 /* E1-NO framing HDB3 */ |
872 | #define CFG_FORMAT_T3CPAR 100 /* T3-C-Bit par B3ZS */ |
873 | #define CFG_FORMAT_T3M13 101 /* T3-M13 format B3ZS */ |
874 | |
875 | /* format aliases that improve code readability */ |
876 | #define FORMAT_T1ANY ((sc->config.format & 1)==1) |
877 | #define FORMAT_E1ANY ((sc->config.format & 1)==0) |
878 | #define FORMAT_E1CAS ((sc->config.format & 0x11)==0x10) |
879 | #define FORMAT_E1CRC ((sc->config.format & 0x09)==0x08) |
880 | #define FORMAT_E1NONE (sc->config.format == CFG_FORMAT_E1NONE) |
881 | #define FORMAT_T1ESF (sc->config.format == CFG_FORMAT_T1ESF) |
882 | #define FORMAT_T1SF (sc->config.format == CFG_FORMAT_T1SF) |
883 | #define FORMAT_T3CPAR (sc->config.format == CFG_FORMAT_T3CPAR) |
884 | |
885 | #define CFG_SCRAM_OFF 1 /* DS3 payload scrambler off */ |
886 | #define CFG_SCRAM_DL_KEN 2 /* DS3 DigitalLink/Kentrox X^43+1 */ |
887 | #define CFG_SCRAM_LARS 3 /* DS3 Larscom X^20+X^17+1 w/28ZS */ |
888 | |
889 | #define CFG_DTE 1 /* HSSIc, SSI: rcv TXCLK; rcv DCD */ |
890 | #define CFG_DCE 2 /* HSSIc, SSI: drv TXCLK; drv DCD */ |
891 | |
892 | #define CFG_GAIN_SHORT 0x24 /* 0-20 dB of equalized gain */ |
893 | #define CFG_GAIN_MEDIUM 0x2C /* 0-30 dB of equalized gain */ |
894 | #define CFG_GAIN_LONG 0x34 /* 0-40 dB of equalized gain */ |
895 | #define CFG_GAIN_EXTEND 0x3F /* 0-64 dB of equalized gain */ |
896 | #define CFG_GAIN_AUTO 0xFF /* auto-set based on cable length */ |
897 | |
898 | #define CFG_PULSE_T1DSX0 0 /* T1 DSX 0- 40 meters */ |
899 | #define CFG_PULSE_T1DSX1 2 /* T1 DSX 40- 80 meters */ |
900 | #define CFG_PULSE_T1DSX2 4 /* T1 DSX 80-120 meters */ |
901 | #define CFG_PULSE_T1DSX3 6 /* T1 DSX 120-160 meters */ |
902 | #define CFG_PULSE_T1DSX4 8 /* T1 DSX 160-200 meters */ |
903 | #define CFG_PULSE_E1COAX 10 /* E1 75 ohm coax pair */ |
904 | #define CFG_PULSE_E1TWIST 12 /* E1 120 ohm twisted pairs */ |
905 | #define CFG_PULSE_T1CSU 14 /* T1 CSU 200-2000 meters; set LBO */ |
906 | #define CFG_PULSE_AUTO 0xFF /* auto-set based on cable length */ |
907 | |
908 | #define CFG_LBO_0DB 0 /* T1CSU LBO = 0.0 dB; FCC opt A */ |
909 | #define CFG_LBO_7DB 16 /* T1CSU LBO = 7.5 dB; FCC opt B */ |
910 | #define CFG_LBO_15DB 32 /* T1CSU LBO = 15.0 dB; FCC opt C */ |
911 | #define CFG_LBO_22DB 48 /* T1CSU LBO = 22.5 dB; final span */ |
912 | #define CFG_LBO_AUTO 0xFF /* auto-set based on cable length */ |
913 | |
914 | struct ioctl |
915 | { |
916 | struct iohdr iohdr; /* common ioctl header */ |
917 | u_int32_t cmd; /* command */ |
918 | u_int32_t address; /* command address */ |
919 | u_int32_t data; /* command data */ |
920 | char *ucode; /* user-land address of ucode */ |
921 | }; |
922 | |
923 | #define IOCTL_RW_PCI 1 /* RW: Tulip PCI config registers */ |
924 | #define IOCTL_RW_CSR 2 /* RW: Tulip Control & Status Regs */ |
925 | #define IOCTL_RW_SROM 3 /* RW: Tulip Serial Rom */ |
926 | #define IOCTL_RW_BIOS 4 /* RW: Tulip Boot rom */ |
927 | #define IOCTL_RW_MII 5 /* RW: MII registers */ |
928 | #define IOCTL_RW_FRAME 6 /* RW: Framer registers */ |
929 | #define IOCTL_WO_SYNTH 7 /* WO: Synthesized oscillator */ |
930 | #define IOCTL_WO_DAC 8 /* WO: Digital/Analog Converter */ |
931 | |
932 | #define IOCTL_XILINX_RESET 16 /* reset Xilinx: all FFs set to 0 */ |
933 | #define IOCTL_XILINX_ROM 17 /* load Xilinx program from ROM */ |
934 | #define IOCTL_XILINX_FILE 18 /* load Xilinx program from file */ |
935 | |
936 | #define IOCTL_SET_STATUS 50 /* set mdm ctrl bits (internal) */ |
937 | #define IOCTL_SNMP_SEND 51 /* trunk MIB send code */ |
938 | #define IOCTL_SNMP_LOOP 52 /* trunk MIB loop configuration */ |
939 | #define IOCTL_SNMP_SIGS 53 /* RS232-like modem control sigs */ |
940 | #define IOCTL_RESET_CNTRS 54 /* reset event counters */ |
941 | |
942 | /* storage for these strings is allocated here! */ |
943 | const char *ssi_cables[] = |
944 | { |
945 | "V.10/EIA423" , |
946 | "V.11/EIA530A" , |
947 | "RESERVED" , |
948 | "X.21" , |
949 | "V.35" , |
950 | "V.36/EIA449" , |
951 | "V.28/EIA232" , |
952 | "NO CABLE" , |
953 | NULL, |
954 | }; |
955 | |
956 | /***************************************************************************/ |
957 | /* Declarations above here are shared with the user lmcconfig program. */ |
958 | /* Declarations below here are private to the kernel device driver. */ |
959 | /***************************************************************************/ |
960 | |
961 | #if KERNEL || _KERNEL || __KERNEL__ |
962 | |
963 | /* Hide the minor differences between Operating Systems */ |
964 | |
965 | typedef int intr_return_t; |
966 | # define READ_PCI_CFG(sc, addr) pci_conf_read ((sc)->pa_pc, (sc)->pa_tag, addr) |
967 | # define WRITE_PCI_CFG(sc, addr, data) pci_conf_write((sc)->pa_pc, (sc)->pa_tag, addr, data) |
968 | # define READ_CSR(sc, csr) bus_space_read_4 ((sc)->csr_tag, (sc)->csr_handle, csr) |
969 | # define WRITE_CSR(sc, csr, val) bus_space_write_4((sc)->csr_tag, (sc)->csr_handle, csr, val) |
970 | # define NAME_UNIT device_xname(sc->sc_dev) |
971 | # define BOOT_VERBOSE (boothowto & AB_VERBOSE) |
972 | # define TOP_LOCK(sc) (mutex_spin_enter(&(sc)->top_lock), 0) |
973 | # define TOP_TRYLOCK(sc) mutex_tryenter(&(sc)->top_lock) |
974 | # define TOP_UNLOCK(sc) mutex_spin_exit(&(sc)->top_lock) |
975 | # define BOTTOM_TRYLOCK(sc) __cpu_simple_lock_try(&(sc)->bottom_lock) |
976 | # define BOTTOM_UNLOCK(sc) __cpu_simple_unlock (&(sc)->bottom_lock) |
977 | # define CHECK_CAP kauth_authorize_network(curlwp->l_cred, KAUTH_NETWORK_INTERFACE, KAUTH_REQ_NETWORK_INTERFACE_FIRMWARE, sc->ifp, NULL, NULL) |
978 | # define DISABLE_INTR int spl = splnet() |
979 | # define ENABLE_INTR splx(spl) |
980 | # define IRQ_NONE 0 |
981 | # define IRQ_HANDLED 1 |
982 | # define IFP2SC(ifp) (ifp)->if_softc |
983 | # define COPY_BREAK MHLEN |
984 | # define SLEEP(usecs) tsleep(sc, PZERO, DEVICE_NAME, 1+(usecs/tick)) |
985 | # define DMA_SYNC(map, size, flags) bus_dmamap_sync(ring->tag, map, 0, size, flags) |
986 | # define DMA_LOAD(map, addr, size) bus_dmamap_load(ring->tag, map, addr, size, 0, BUS_DMA_NOWAIT) |
987 | # define LMC_BPF_MTAP(sc, mbuf) bpf_mtap((sc)->ifp, mbuf) |
988 | # define LMC_BPF_ATTACH(sc, dlt, len) bpf_attach((sc)->ifp, dlt, len) |
989 | # define LMC_BPF_DETACH(sc) bpf_detach((sc)->ifp) |
990 | |
991 | static int driver_announced = 0; /* print driver info once only */ |
992 | |
993 | #define SNDQ_MAXLEN 32 /* packets awaiting transmission */ |
994 | #define DESCS_PER_PKT 4 /* DMA descriptors per TX pkt */ |
995 | #define NUM_TX_DESCS (DESCS_PER_PKT * SNDQ_MAXLEN) |
996 | /* Increase DESCS_PER_PKT if status.cntrs.txdma increments. */ |
997 | |
998 | /* A Tulip DMA descriptor can point to two chunks of memory. |
999 | * Each chunk has a max length of 2047 bytes (ask the VMS guys). |
1000 | * 2047 isn't a multiple of a cache line size (32 bytes typically). |
1001 | * So back off to 2048-32 = 2016 bytes per chunk (2 chunks per descr). |
1002 | */ |
1003 | #define MAX_CHUNK_LEN (2048-32) |
1004 | #define MAX_DESC_LEN (2 * MAX_CHUNK_LEN) |
1005 | |
1006 | /* Tulip DMA descriptor; THIS STRUCT MUST MATCH THE HARDWARE */ |
1007 | struct dma_desc |
1008 | { |
1009 | u_int32_t status; /* hardware->to->software */ |
1010 | #if BYTE_ORDER == LITTLE_ENDIAN /* left-to-right packing */ |
1011 | unsigned length1:11; /* buffer1 length */ |
1012 | unsigned length2:11; /* buffer2 length */ |
1013 | unsigned control:10; /* software->to->hardware */ |
1014 | #else /* right-to-left packing */ |
1015 | unsigned control:10; /* software->to->hardware */ |
1016 | unsigned length2:11; /* buffer2 length */ |
1017 | unsigned length1:11; /* buffer1 length */ |
1018 | #endif |
1019 | u_int32_t address1; /* buffer1 bus address */ |
1020 | u_int32_t address2; /* buffer2 bus address */ |
1021 | bus_dmamap_t map; /* bus dmamap for this descriptor */ |
1022 | # define TLP_BUS_DSL_VAL (sizeof(bus_dmamap_t) & TLP_BUS_DSL) |
1023 | } __packed; |
1024 | |
1025 | /* Tulip DMA descriptor status bits */ |
1026 | #define TLP_DSTS_OWNER 0x80000000 |
1027 | #define TLP_DSTS_RX_DESC_ERR 0x00004000 |
1028 | #define TLP_DSTS_RX_FIRST_DESC 0x00000200 |
1029 | #define TLP_DSTS_RX_LAST_DESC 0x00000100 |
1030 | #define TLP_DSTS_RX_MII_ERR 0x00000008 |
1031 | #define TLP_DSTS_RX_DRIBBLE 0x00000004 |
1032 | #define TLP_DSTS_TX_UNDERRUN 0x00000002 |
1033 | #define TLP_DSTS_RX_OVERRUN 0x00000001 /* not documented in rev AF */ |
1034 | #define TLP_DSTS_RX_BAD (TLP_DSTS_RX_MII_ERR | \ |
1035 | TLP_DSTS_RX_DRIBBLE | \ |
1036 | TLP_DSTS_RX_DESC_ERR | \ |
1037 | TLP_DSTS_RX_OVERRUN) |
1038 | |
1039 | /* Tulip DMA descriptor control bits */ |
1040 | #define TLP_DCTL_TX_INTERRUPT 0x0200 |
1041 | #define TLP_DCTL_TX_LAST_SEG 0x0100 |
1042 | #define TLP_DCTL_TX_FIRST_SEG 0x0080 |
1043 | #define TLP_DCTL_TX_NO_CRC 0x0010 |
1044 | #define TLP_DCTL_END_RING 0x0008 |
1045 | #define TLP_DCTL_TX_NO_PAD 0x0002 |
1046 | |
1047 | /* DMA descriptors are kept in a ring. |
1048 | * Ring is empty when (read == write). |
1049 | * Ring is full when (read == wrap(write+1)), |
1050 | * The ring also contains a tailq of data buffers. |
1051 | */ |
1052 | struct desc_ring |
1053 | { |
1054 | struct dma_desc *read; /* next descriptor to be read */ |
1055 | struct dma_desc *write; /* next descriptor to be written */ |
1056 | struct dma_desc *first; /* first descriptor in ring */ |
1057 | struct dma_desc *last; /* last descriptor in ring */ |
1058 | struct dma_desc *temp; /* temporary write pointer for tx */ |
1059 | u_int32_t dma_addr; /* bus addr for desc array XXX */ |
1060 | int size_descs; /* bus_dmamap_sync needs this */ |
1061 | int num_descs; /* used to set rx quota */ |
1062 | #if IFNET || NETGRAPH |
1063 | struct mbuf *head; /* tail-queue of mbufs */ |
1064 | struct mbuf *tail; |
1065 | #elif NETDEV |
1066 | struct sk_buff *head; /* tail-queue of skbuffs */ |
1067 | struct sk_buff *tail; |
1068 | #endif |
1069 | bus_dma_tag_t tag; /* bus_dma_tag for desc array */ |
1070 | bus_dmamap_t map; /* bus_dmamap for desc array */ |
1071 | bus_dma_segment_t segs[2]; /* bus_dmamap_load() or bus_dmamem_alloc() */ |
1072 | int nsegs; /* bus_dmamap_load() or bus_dmamem_alloc() */ |
1073 | }; |
1074 | |
1075 | /* break circular definition */ |
1076 | typedef struct softc softc_t; |
1077 | |
1078 | struct card /* an object */ |
1079 | { |
1080 | void (*ident) (softc_t *); |
1081 | void (*watchdog) (softc_t *); |
1082 | int (*ioctl) (softc_t *, struct ioctl *); |
1083 | void (*attach) (softc_t *, struct config *); |
1084 | void (*detach) (softc_t *); |
1085 | }; |
1086 | |
1087 | struct stack /* an object */ |
1088 | { |
1089 | #if IFNET || NETGRAPH |
1090 | int (*ioctl) (softc_t *, u_long, void *); |
1091 | void (*input) (softc_t *, struct mbuf *); |
1092 | void (*output) (softc_t *); |
1093 | #elif NETDEV |
1094 | int (*ioctl) (softc_t *, struct ifreq *, int); |
1095 | int (*type) (softc_t *, struct sk_buff *); |
1096 | int (*mtu) (softc_t *, int); |
1097 | #endif |
1098 | void (*watchdog) (softc_t *); |
1099 | int (*open) (softc_t *, struct config *); |
1100 | int (*attach) (softc_t *, struct config *); |
1101 | int (*detach) (softc_t *); |
1102 | }; |
1103 | |
1104 | /* This is the instance data, or "software context" for the device driver. */ |
1105 | struct softc |
1106 | { |
1107 | |
1108 | device_t sc_dev; |
1109 | pcitag_t pa_tag; |
1110 | pci_chipset_tag_t pa_pc; |
1111 | bus_dma_tag_t pa_dmat; |
1112 | bus_space_tag_t csr_tag; |
1113 | bus_space_handle_t csr_handle; |
1114 | pci_intr_handle_t intr_handle; |
1115 | void *irq_cookie; |
1116 | void *sdh_cookie; |
1117 | struct mbuf *tx_mbuf; /* hang mbuf here while building dma descs */ |
1118 | kmutex_t top_lock; /* lock card->watchdog vs ioctls */ |
1119 | __cpu_simple_lock_t bottom_lock; /* lock buf queues & descriptor rings */ |
1120 | |
1121 | /* State for kernel-resident Line Protocols */ |
1122 | #if IFNET |
1123 | # if SPPP |
1124 | struct sppp spppcom; |
1125 | struct sppp *sppp; |
1126 | # elif P2P |
1127 | struct p2pcom p2pcom; |
1128 | struct p2pcom *p2p; |
1129 | # else |
1130 | struct ifnet ifnet; |
1131 | # endif |
1132 | struct ifnet *ifp; |
1133 | struct ifmedia ifm; |
1134 | #endif /* IFNET */ |
1135 | |
1136 | #if NETDEV |
1137 | # if GEN_HDLC |
1138 | hdlc_device *hdlcdev; /* contains struct net_device_stats */ |
1139 | # else |
1140 | struct net_device_stats netdev_stats; |
1141 | # endif |
1142 | # if SYNC_PPP |
1143 | struct ppp_device *ppd; |
1144 | struct ppp_device ppp_dev; /* contains a struct sppp */ |
1145 | struct sppp *sppp; |
1146 | # endif |
1147 | struct net_device *netdev; |
1148 | #endif /* NETDEV */ |
1149 | |
1150 | |
1151 | |
1152 | |
1153 | /* State used by all card types; lock with top_lock. */ |
1154 | struct status status; /* lmcconfig can read */ |
1155 | struct config config; /* lmcconfig can read/write */ |
1156 | const char *dev_desc; /* string describing card */ |
1157 | struct card *card; /* card methods */ |
1158 | struct stack *stack; /* line methods */ |
1159 | u_int32_t gpio_dir; /* s/w copy of GPIO direction reg */ |
1160 | u_int16_t led_state; /* last value written to mii16 */ |
1161 | int quota; /* used for packet flow control */ |
1162 | |
1163 | /* State used by card-specific watchdogs; lock with top_lock. */ |
1164 | u_int32_t last_mii16; /* SSI, HSSI: MII reg 16 one sec ago */ |
1165 | u_int32_t last_stat16; /* T3: framer reg 16 one sec ago */ |
1166 | u_int32_t last_alm1; /* T1E1: framer reg 47 one sec ago */ |
1167 | u_int32_t last_link_state; /* ALL: status.link_state 1 ec ago */ |
1168 | u_int32_t last_FEAC; /* T3: last FEAC msg code received */ |
1169 | u_int32_t loop_timer; /* T1E1, T3: secs until loop ends */ |
1170 | |
1171 | /* State used by the interrupt code; lock with bottom_lock. */ |
1172 | struct desc_ring txring; /* tx descriptor ring state */ |
1173 | struct desc_ring rxring; /* rx descriptor ring state */ |
1174 | }; /* end of softc */ |
1175 | |
1176 | |
1177 | #define HSSI_DESC "LMC5200 HSSI Card" |
1178 | #define T3_DESC "LMC5245 T3 Card" |
1179 | #define SSI_DESC "LMC1000 SSI Card" |
1180 | #define T1E1_DESC "LMC1200 T1E1 Card" |
1181 | |
1182 | /* procedure prototypes */ |
1183 | |
1184 | static void srom_shift_bits(softc_t *, u_int32_t, u_int32_t); |
1185 | static u_int16_t srom_read(softc_t *, u_int8_t); |
1186 | static void srom_write(softc_t *, u_int8_t, u_int16_t); |
1187 | |
1188 | static u_int8_t bios_read(softc_t *, u_int32_t); |
1189 | static void bios_write_phys(softc_t *, u_int32_t, u_int8_t); |
1190 | static void bios_write(softc_t *, u_int32_t, u_int8_t); |
1191 | static void bios_erase(softc_t *); |
1192 | |
1193 | static void mii_shift_bits(softc_t *, u_int32_t, u_int32_t); |
1194 | static u_int16_t mii_read(softc_t *, u_int8_t); |
1195 | static void mii_write(softc_t *, u_int8_t, u_int16_t); |
1196 | |
1197 | static void mii16_set_bits(softc_t *, u_int16_t); |
1198 | static void mii16_clr_bits(softc_t *, u_int16_t); |
1199 | static void mii17_set_bits(softc_t *, u_int16_t); |
1200 | static void mii17_clr_bits(softc_t *, u_int16_t); |
1201 | |
1202 | static void led_off(softc_t *, u_int16_t); |
1203 | static void led_on(softc_t *, u_int16_t); |
1204 | static void led_inv(softc_t *, u_int16_t); |
1205 | |
1206 | static void framer_write(softc_t *, u_int16_t, u_int8_t); |
1207 | static u_int8_t framer_read(softc_t *, u_int16_t); |
1208 | |
1209 | static void gpio_make_input(softc_t *, u_int32_t); |
1210 | static void gpio_make_output(softc_t *, u_int32_t); |
1211 | static u_int32_t gpio_read(softc_t *); |
1212 | static void gpio_set_bits(softc_t *, u_int32_t); |
1213 | static void gpio_clr_bits(softc_t *, u_int32_t); |
1214 | |
1215 | static void xilinx_reset(softc_t *); |
1216 | static void xilinx_load_from_rom(softc_t *); |
1217 | static int xilinx_load_from_file(softc_t *, char *, u_int32_t); |
1218 | |
1219 | static void synth_shift_bits(softc_t *, u_int32_t, u_int32_t); |
1220 | static void synth_write(softc_t *, struct synth *); |
1221 | |
1222 | static void dac_write(softc_t *, u_int16_t); |
1223 | |
1224 | static void hssi_ident(softc_t *); |
1225 | static void hssi_watchdog(softc_t *); |
1226 | static int hssi_ioctl(softc_t *, struct ioctl *); |
1227 | static void hssi_attach(softc_t *, struct config *); |
1228 | static void hssi_detach(softc_t *); |
1229 | |
1230 | static void t3_ident(softc_t *); |
1231 | static void t3_watchdog(softc_t *); |
1232 | static int t3_ioctl(softc_t *, struct ioctl *); |
1233 | static void t3_send_dbl_feac(softc_t *, int, int); |
1234 | static void t3_attach(softc_t *, struct config *); |
1235 | static void t3_detach(softc_t *); |
1236 | |
1237 | static void ssi_ident(softc_t *); |
1238 | static void ssi_watchdog(softc_t *); |
1239 | static int ssi_ioctl(softc_t *, struct ioctl *); |
1240 | static void ssi_attach(softc_t *, struct config *); |
1241 | static void ssi_detach(softc_t *); |
1242 | |
1243 | static void t1_ident(softc_t *); |
1244 | static void t1_watchdog(softc_t *); |
1245 | static int t1_ioctl(softc_t *, struct ioctl *); |
1246 | static void t1_send_bop(softc_t *, int); |
1247 | static void t1_attach(softc_t *, struct config *); |
1248 | static void t1_detach(softc_t *); |
1249 | |
1250 | |
1251 | #if SYNC_PPP |
1252 | static int sync_ppp_ioctl(softc_t *, struct ifreq *, int); |
1253 | static int sync_ppp_type(softc_t *, struct sk_buff *); |
1254 | static int sync_ppp_mtu(softc_t *, int); |
1255 | static void sync_ppp_watchdog(softc_t *); |
1256 | static int sync_ppp_open(softc_t *, struct config *); |
1257 | static int sync_ppp_attach(softc_t *, struct config *); |
1258 | static int sync_ppp_detach(softc_t *); |
1259 | #endif /* SYNC_PPP */ |
1260 | |
1261 | #if GEN_HDLC |
1262 | static int gen_hdlc_ioctl(softc_t *, struct ifreq *, int); |
1263 | static int gen_hdlc_type(softc_t *, struct sk_buff *); |
1264 | static int gen_hdlc_mtu(softc_t *, int); |
1265 | static void gen_hdlc_watchdog(softc_t *); |
1266 | static int gen_hdlc_open(softc_t *, struct config *); |
1267 | static int gen_hdlc_attach(softc_t *, struct config *); |
1268 | static int gen_hdlc_detach(softc_t *); |
1269 | static int gen_hdlc_card_params(struct net_device *, unsigned short, |
1270 | unsigned short); |
1271 | #endif /* GEN_HDLC */ |
1272 | |
1273 | #if P2P |
1274 | static int p2p_stack_ioctl(softc_t *, u_long, void *); |
1275 | static void p2p_stack_input(softc_t *, struct mbuf *); |
1276 | static void p2p_stack_output(softc_t *); |
1277 | static void p2p_stack_watchdog(softc_t *); |
1278 | static int p2p_stack_open(softc_t *, struct config *); |
1279 | static int p2p_stack_attach(softc_t *, struct config *); |
1280 | static int p2p_stack_detach(softc_t *); |
1281 | static int p2p_getmdm(struct p2pcom *, void *); |
1282 | static int p2p_mdmctl(struct p2pcom *, int); |
1283 | #endif /* P2P */ |
1284 | |
1285 | #if SPPP |
1286 | static int sppp_stack_ioctl(softc_t *, u_long, void *); |
1287 | static void sppp_stack_input(softc_t *, struct mbuf *); |
1288 | static void sppp_stack_output(softc_t *); |
1289 | static void sppp_stack_watchdog(softc_t *); |
1290 | static int sppp_stack_open(softc_t *, struct config *); |
1291 | static int sppp_stack_attach(softc_t *, struct config *); |
1292 | static int sppp_stack_detach(softc_t *); |
1293 | static void sppp_tls(struct sppp *); |
1294 | static void sppp_tlf(struct sppp *); |
1295 | #endif /* SPPP */ |
1296 | |
1297 | #if IFNET |
1298 | static int rawip_ioctl(softc_t *, u_long, void *); |
1299 | static void rawip_input(softc_t *, struct mbuf *); |
1300 | static void rawip_output(softc_t *); |
1301 | #elif NETDEV |
1302 | static int rawip_ioctl(softc_t *, struct ifreq *, int); |
1303 | static int rawip_type(softc_t *, struct sk_buff *); |
1304 | static int rawip_mtu(softc_t *, int); |
1305 | #endif |
1306 | static void rawip_watchdog(softc_t *); |
1307 | static int rawip_open(softc_t *, struct config *); |
1308 | static int rawip_attach(softc_t *, struct config *); |
1309 | static int rawip_detach(softc_t *); |
1310 | |
1311 | #if IFNET |
1312 | static void ifnet_input(struct ifnet *, struct mbuf *); |
1313 | static int ifnet_output(struct ifnet *, struct mbuf *, |
1314 | const struct sockaddr *, const struct rtentry *); |
1315 | static int ifnet_ioctl(struct ifnet *, u_long, void *); |
1316 | static void ifnet_start(struct ifnet *); |
1317 | static void ifnet_watchdog(struct ifnet *); |
1318 | |
1319 | static void ifnet_setup(struct ifnet *); |
1320 | static int ifnet_attach(softc_t *); |
1321 | static void ifnet_detach(softc_t *); |
1322 | |
1323 | static void ifmedia_setup(softc_t *); |
1324 | static int lmc_ifmedia_change(struct ifnet *); |
1325 | static void ifmedia_status(struct ifnet *, struct ifmediareq *); |
1326 | #endif /* IFNET */ |
1327 | |
1328 | #if NETDEV |
1329 | static int netdev_open(struct net_device *); |
1330 | static int netdev_stop(struct net_device *); |
1331 | static int netdev_start(struct sk_buff *, struct net_device *); |
1332 | # if NAPI |
1333 | static int netdev_poll(struct net_device *, int *); |
1334 | # endif |
1335 | static int netdev_ioctl(struct net_device *, struct ifreq *, int); |
1336 | static int netdev_mtu(struct net_device *, int); |
1337 | static void netdev_timeout(struct net_device *); |
1338 | static struct net_device_stats *netdev_stats(struct net_device *); |
1339 | static void netdev_watchdog(unsigned long); |
1340 | |
1341 | static void netdev_setup(struct net_device *); |
1342 | static int netdev_attach(softc_t *); |
1343 | static void netdev_detach(softc_t *); |
1344 | #endif /* NETDEV */ |
1345 | |
1346 | |
1347 | #if BSD |
1348 | static int create_ring(softc_t *, struct desc_ring *, int); |
1349 | static void destroy_ring(softc_t *, struct desc_ring *); |
1350 | |
1351 | static void mbuf_enqueue(struct desc_ring *, struct mbuf *); |
1352 | static struct mbuf *mbuf_dequeue(struct desc_ring *); |
1353 | |
1354 | static int rxintr_cleanup(softc_t *); |
1355 | static int rxintr_setup(softc_t *); |
1356 | static int txintr_cleanup(softc_t *); |
1357 | static int txintr_setup_mbuf(softc_t *, struct mbuf *); |
1358 | static int txintr_setup(softc_t *); |
1359 | |
1360 | static intr_return_t bsd_interrupt(void *); |
1361 | # if DEVICE_POLLING |
1362 | static void bsd_poll(struct ifnet *, enum poll_cmd, int); |
1363 | # endif |
1364 | #endif /* BSD */ |
1365 | |
1366 | static int open_proto(softc_t *, struct config *); |
1367 | static int attach_stack(softc_t *, struct config *); |
1368 | |
1369 | static int lmc_ioctl(softc_t *, u_long, void *); |
1370 | static void lmc_watchdog(softc_t *); |
1371 | |
1372 | static void set_ready(softc_t *, int); |
1373 | static void reset_cntrs(softc_t *); |
1374 | |
1375 | static void lmc_interrupt(void *, int, int); |
1376 | static void check_intr_status(softc_t *); |
1377 | |
1378 | static int lmc_attach(softc_t *); |
1379 | static void lmc_detach(softc_t *); |
1380 | |
1381 | static void tulip_loop(softc_t *, struct config *); |
1382 | static int tulip_attach(softc_t *); |
1383 | static void tulip_detach(void *); |
1384 | |
1385 | static void print_driver_info(void); |
1386 | |
1387 | static int nbsd_match(device_t, cfdata_t, void *); |
1388 | static void nbsd_attach(device_t, device_t, void *); |
1389 | static int nbsd_detach(device_t, int); |
1390 | |
1391 | #endif /* KERNEL */ |
1392 | |
1393 | #endif /* IF_LMC_H */ |
1394 | |