1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Christian König
28 */
29#include <linux/jiffies.h>
30#include <linux/seq_file.h>
31#include <linux/slab.h>
32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
34#include "radeon_reg.h"
35#include "radeon.h"
36#include "atom.h"
37
38/*
39 * IB
40 * IBs (Indirect Buffers) and areas of GPU accessible memory where
41 * commands are stored. You can put a pointer to the IB in the
42 * command ring and the hw will fetch the commands from the IB
43 * and execute them. Generally userspace acceleration drivers
44 * produce command buffers which are send to the kernel and
45 * put in IBs for execution by the requested ring.
46 */
47static int radeon_debugfs_sa_init(struct radeon_device *rdev);
48
49/**
50 * radeon_ib_get - request an IB (Indirect Buffer)
51 *
52 * @rdev: radeon_device pointer
53 * @ring: ring index the IB is associated with
54 * @ib: IB object returned
55 * @size: requested IB size
56 *
57 * Request an IB (all asics). IBs are allocated using the
58 * suballocator.
59 * Returns 0 on success, error on failure.
60 */
61int radeon_ib_get(struct radeon_device *rdev, int ring,
62 struct radeon_ib *ib, struct radeon_vm *vm,
63 unsigned size)
64{
65 int r;
66
67 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256);
68 if (r) {
69 dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
70 return r;
71 }
72
73 r = radeon_semaphore_create(rdev, &ib->semaphore);
74 if (r) {
75 return r;
76 }
77
78 ib->ring = ring;
79 ib->fence = NULL;
80 ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
81 ib->vm = vm;
82 if (vm) {
83 /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
84 * space and soffset is the offset inside the pool bo
85 */
86 ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
87 } else {
88 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
89 }
90 ib->is_const_ib = false;
91
92 return 0;
93}
94
95/**
96 * radeon_ib_free - free an IB (Indirect Buffer)
97 *
98 * @rdev: radeon_device pointer
99 * @ib: IB object to free
100 *
101 * Free an IB (all asics).
102 */
103void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
104{
105 radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);
106 radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
107 radeon_fence_unref(&ib->fence);
108}
109
110/**
111 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
112 *
113 * @rdev: radeon_device pointer
114 * @ib: IB object to schedule
115 * @const_ib: Const IB to schedule (SI only)
116 *
117 * Schedule an IB on the associated ring (all asics).
118 * Returns 0 on success, error on failure.
119 *
120 * On SI, there are two parallel engines fed from the primary ring,
121 * the CE (Constant Engine) and the DE (Drawing Engine). Since
122 * resource descriptors have moved to memory, the CE allows you to
123 * prime the caches while the DE is updating register state so that
124 * the resource descriptors will be already in cache when the draw is
125 * processed. To accomplish this, the userspace driver submits two
126 * IBs, one for the CE and one for the DE. If there is a CE IB (called
127 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
128 * to SI there was just a DE IB.
129 */
130int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
131 struct radeon_ib *const_ib)
132{
133 struct radeon_ring *ring = &rdev->ring[ib->ring];
134 int r = 0;
135
136 if (!ib->length_dw || !ring->ready) {
137 /* TODO: Nothings in the ib we should report. */
138 dev_err(rdev->dev, "couldn't schedule ib\n");
139 return -EINVAL;
140 }
141
142 /* 64 dwords should be enough for fence too */
143 r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8);
144 if (r) {
145 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
146 return r;
147 }
148
149 /* grab a vm id if necessary */
150 if (ib->vm) {
151 struct radeon_fence *vm_id_fence;
152 vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring);
153 radeon_semaphore_sync_to(ib->semaphore, vm_id_fence);
154 }
155
156 /* sync with other rings */
157 r = radeon_semaphore_sync_rings(rdev, ib->semaphore, ib->ring);
158 if (r) {
159 dev_err(rdev->dev, "failed to sync rings (%d)\n", r);
160 radeon_ring_unlock_undo(rdev, ring);
161 return r;
162 }
163
164 if (ib->vm)
165 radeon_vm_flush(rdev, ib->vm, ib->ring);
166
167 if (const_ib) {
168 radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
169 radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
170 }
171 radeon_ring_ib_execute(rdev, ib->ring, ib);
172 r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
173 if (r) {
174 dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
175 radeon_ring_unlock_undo(rdev, ring);
176 return r;
177 }
178 if (const_ib) {
179 const_ib->fence = radeon_fence_ref(ib->fence);
180 }
181
182 if (ib->vm)
183 radeon_vm_fence(rdev, ib->vm, ib->fence);
184
185 radeon_ring_unlock_commit(rdev, ring);
186 return 0;
187}
188
189/**
190 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
191 *
192 * @rdev: radeon_device pointer
193 *
194 * Initialize the suballocator to manage a pool of memory
195 * for use as IBs (all asics).
196 * Returns 0 on success, error on failure.
197 */
198int radeon_ib_pool_init(struct radeon_device *rdev)
199{
200 int r;
201
202 if (rdev->ib_pool_ready) {
203 return 0;
204 }
205 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
206 RADEON_IB_POOL_SIZE*64*1024,
207 RADEON_GPU_PAGE_SIZE,
208 RADEON_GEM_DOMAIN_GTT);
209 if (r) {
210 return r;
211 }
212
213 r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
214 if (r) {
215 return r;
216 }
217
218 rdev->ib_pool_ready = true;
219 if (radeon_debugfs_sa_init(rdev)) {
220 dev_err(rdev->dev, "failed to register debugfs file for SA\n");
221 }
222 return 0;
223}
224
225/**
226 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
227 *
228 * @rdev: radeon_device pointer
229 *
230 * Tear down the suballocator managing the pool of memory
231 * for use as IBs (all asics).
232 */
233void radeon_ib_pool_fini(struct radeon_device *rdev)
234{
235 if (rdev->ib_pool_ready) {
236 radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
237 radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
238 rdev->ib_pool_ready = false;
239 }
240}
241
242/**
243 * radeon_ib_ring_tests - test IBs on the rings
244 *
245 * @rdev: radeon_device pointer
246 *
247 * Test an IB (Indirect Buffer) on each ring.
248 * If the test fails, disable the ring.
249 * Returns 0 on success, error if the primary GFX ring
250 * IB test fails.
251 */
252int radeon_ib_ring_tests(struct radeon_device *rdev)
253{
254 unsigned i;
255 int r;
256
257 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
258 struct radeon_ring *ring = &rdev->ring[i];
259
260 if (!ring->ready)
261 continue;
262
263 r = radeon_ib_test(rdev, i, ring);
264 if (r) {
265 ring->ready = false;
266 rdev->needs_reset = false;
267
268 if (i == RADEON_RING_TYPE_GFX_INDEX) {
269 /* oh, oh, that's really bad */
270 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
271 rdev->accel_working = false;
272 return r;
273
274 } else {
275 /* still not good, but we can live with it */
276 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
277 }
278 }
279 }
280 return 0;
281}
282
283/*
284 * Rings
285 * Most engines on the GPU are fed via ring buffers. Ring
286 * buffers are areas of GPU accessible memory that the host
287 * writes commands into and the GPU reads commands out of.
288 * There is a rptr (read pointer) that determines where the
289 * GPU is currently reading, and a wptr (write pointer)
290 * which determines where the host has written. When the
291 * pointers are equal, the ring is idle. When the host
292 * writes commands to the ring buffer, it increments the
293 * wptr. The GPU then starts fetching commands and executes
294 * them until the pointers are equal again.
295 */
296static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
297
298/**
299 * radeon_ring_write - write a value to the ring
300 *
301 * @ring: radeon_ring structure holding ring information
302 * @v: dword (dw) value to write
303 *
304 * Write a value to the requested ring buffer (all asics).
305 */
306void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
307{
308#if DRM_DEBUG_CODE
309 if (ring->count_dw <= 0) {
310 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
311 }
312#endif
313 ring->ring[ring->wptr++] = v;
314 ring->wptr &= ring->ptr_mask;
315 ring->count_dw--;
316 ring->ring_free_dw--;
317}
318
319/**
320 * radeon_ring_supports_scratch_reg - check if the ring supports
321 * writing to scratch registers
322 *
323 * @rdev: radeon_device pointer
324 * @ring: radeon_ring structure holding ring information
325 *
326 * Check if a specific ring supports writing to scratch registers (all asics).
327 * Returns true if the ring supports writing to scratch regs, false if not.
328 */
329bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
330 struct radeon_ring *ring)
331{
332 switch (ring->idx) {
333 case RADEON_RING_TYPE_GFX_INDEX:
334 case CAYMAN_RING_TYPE_CP1_INDEX:
335 case CAYMAN_RING_TYPE_CP2_INDEX:
336 return true;
337 default:
338 return false;
339 }
340}
341
342/**
343 * radeon_ring_free_size - update the free size
344 *
345 * @rdev: radeon_device pointer
346 * @ring: radeon_ring structure holding ring information
347 *
348 * Update the free dw slots in the ring buffer (all asics).
349 */
350void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
351{
352 uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
353
354 /* This works because ring_size is a power of 2 */
355 ring->ring_free_dw = rptr + (ring->ring_size / 4);
356 ring->ring_free_dw -= ring->wptr;
357 ring->ring_free_dw &= ring->ptr_mask;
358 if (!ring->ring_free_dw) {
359 /* this is an empty ring */
360 ring->ring_free_dw = ring->ring_size / 4;
361 /* update lockup info to avoid false positive */
362 radeon_ring_lockup_update(rdev, ring);
363 }
364}
365
366/**
367 * radeon_ring_alloc - allocate space on the ring buffer
368 *
369 * @rdev: radeon_device pointer
370 * @ring: radeon_ring structure holding ring information
371 * @ndw: number of dwords to allocate in the ring buffer
372 *
373 * Allocate @ndw dwords in the ring buffer (all asics).
374 * Returns 0 on success, error on failure.
375 */
376int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
377{
378 int r;
379
380 /* make sure we aren't trying to allocate more space than there is on the ring */
381 if (ndw > (ring->ring_size / 4))
382 return -ENOMEM;
383 /* Align requested size with padding so unlock_commit can
384 * pad safely */
385 radeon_ring_free_size(rdev, ring);
386 ndw = (ndw + ring->align_mask) & ~ring->align_mask;
387 while (ndw > (ring->ring_free_dw - 1)) {
388 radeon_ring_free_size(rdev, ring);
389 if (ndw < ring->ring_free_dw) {
390 break;
391 }
392 r = radeon_fence_wait_next(rdev, ring->idx);
393 if (r)
394 return r;
395 }
396 ring->count_dw = ndw;
397 ring->wptr_old = ring->wptr;
398 return 0;
399}
400
401/**
402 * radeon_ring_lock - lock the ring and allocate space on it
403 *
404 * @rdev: radeon_device pointer
405 * @ring: radeon_ring structure holding ring information
406 * @ndw: number of dwords to allocate in the ring buffer
407 *
408 * Lock the ring and allocate @ndw dwords in the ring buffer
409 * (all asics).
410 * Returns 0 on success, error on failure.
411 */
412int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
413{
414 int r;
415
416 mutex_lock(&rdev->ring_lock);
417 r = radeon_ring_alloc(rdev, ring, ndw);
418 if (r) {
419 mutex_unlock(&rdev->ring_lock);
420 return r;
421 }
422 return 0;
423}
424
425/**
426 * radeon_ring_commit - tell the GPU to execute the new
427 * commands on the ring buffer
428 *
429 * @rdev: radeon_device pointer
430 * @ring: radeon_ring structure holding ring information
431 *
432 * Update the wptr (write pointer) to tell the GPU to
433 * execute new commands on the ring buffer (all asics).
434 */
435void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
436{
437 /* We pad to match fetch size */
438 while (ring->wptr & ring->align_mask) {
439 radeon_ring_write(ring, ring->nop);
440 }
441 mb();
442 radeon_ring_set_wptr(rdev, ring);
443}
444
445/**
446 * radeon_ring_unlock_commit - tell the GPU to execute the new
447 * commands on the ring buffer and unlock it
448 *
449 * @rdev: radeon_device pointer
450 * @ring: radeon_ring structure holding ring information
451 *
452 * Call radeon_ring_commit() then unlock the ring (all asics).
453 */
454void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
455{
456 radeon_ring_commit(rdev, ring);
457 mutex_unlock(&rdev->ring_lock);
458}
459
460/**
461 * radeon_ring_undo - reset the wptr
462 *
463 * @ring: radeon_ring structure holding ring information
464 *
465 * Reset the driver's copy of the wptr (all asics).
466 */
467void radeon_ring_undo(struct radeon_ring *ring)
468{
469 ring->wptr = ring->wptr_old;
470}
471
472/**
473 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
474 *
475 * @ring: radeon_ring structure holding ring information
476 *
477 * Call radeon_ring_undo() then unlock the ring (all asics).
478 */
479void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
480{
481 radeon_ring_undo(ring);
482 mutex_unlock(&rdev->ring_lock);
483}
484
485/**
486 * radeon_ring_lockup_update - update lockup variables
487 *
488 * @ring: radeon_ring structure holding ring information
489 *
490 * Update the last rptr value and timestamp (all asics).
491 */
492void radeon_ring_lockup_update(struct radeon_device *rdev,
493 struct radeon_ring *ring)
494{
495 atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring));
496 atomic64_set(&ring->last_activity, jiffies_64);
497}
498
499/**
500 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
501 * @rdev: radeon device structure
502 * @ring: radeon_ring structure holding ring information
503 *
504 */
505bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
506{
507 uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
508 uint64_t last = atomic64_read(&ring->last_activity);
509 uint64_t elapsed;
510
511 if (rptr != atomic_read(&ring->last_rptr)) {
512 /* ring is still working, no lockup */
513 radeon_ring_lockup_update(rdev, ring);
514 return false;
515 }
516
517 elapsed = jiffies_to_msecs(jiffies_64 - last);
518 if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
519 dev_err(rdev->dev, "ring %d stalled for more than %"PRIu64"msec\n",
520 ring->idx, elapsed);
521 return true;
522 }
523 /* give a chance to the GPU ... */
524 return false;
525}
526
527/**
528 * radeon_ring_backup - Back up the content of a ring
529 *
530 * @rdev: radeon_device pointer
531 * @ring: the ring we want to back up
532 *
533 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
534 */
535unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
536 uint32_t **data)
537{
538 unsigned size, ptr, i;
539
540 /* just in case lock the ring */
541 mutex_lock(&rdev->ring_lock);
542 *data = NULL;
543
544 if (ring->ring_obj == NULL) {
545 mutex_unlock(&rdev->ring_lock);
546 return 0;
547 }
548
549 /* it doesn't make sense to save anything if all fences are signaled */
550 if (!radeon_fence_count_emitted(rdev, ring->idx)) {
551 mutex_unlock(&rdev->ring_lock);
552 return 0;
553 }
554
555 /* calculate the number of dw on the ring */
556 if (ring->rptr_save_reg)
557 ptr = RREG32(ring->rptr_save_reg);
558 else if (rdev->wb.enabled)
559 ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
560 else {
561 /* no way to read back the next rptr */
562 mutex_unlock(&rdev->ring_lock);
563 return 0;
564 }
565
566 size = ring->wptr + (ring->ring_size / 4);
567 size -= ptr;
568 size &= ring->ptr_mask;
569 if (size == 0) {
570 mutex_unlock(&rdev->ring_lock);
571 return 0;
572 }
573
574 /* and then save the content of the ring */
575 *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
576 if (!*data) {
577 mutex_unlock(&rdev->ring_lock);
578 return 0;
579 }
580 for (i = 0; i < size; ++i) {
581 (*data)[i] = ring->ring[ptr++];
582 ptr &= ring->ptr_mask;
583 }
584
585 mutex_unlock(&rdev->ring_lock);
586 return size;
587}
588
589/**
590 * radeon_ring_restore - append saved commands to the ring again
591 *
592 * @rdev: radeon_device pointer
593 * @ring: ring to append commands to
594 * @size: number of dwords we want to write
595 * @data: saved commands
596 *
597 * Allocates space on the ring and restore the previously saved commands.
598 */
599int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
600 unsigned size, uint32_t *data)
601{
602 int i, r;
603
604 if (!size || !data)
605 return 0;
606
607 /* restore the saved ring content */
608 r = radeon_ring_lock(rdev, ring, size);
609 if (r)
610 return r;
611
612 for (i = 0; i < size; ++i) {
613 radeon_ring_write(ring, data[i]);
614 }
615
616 radeon_ring_unlock_commit(rdev, ring);
617 kfree(data);
618 return 0;
619}
620
621/**
622 * radeon_ring_init - init driver ring struct.
623 *
624 * @rdev: radeon_device pointer
625 * @ring: radeon_ring structure holding ring information
626 * @ring_size: size of the ring
627 * @rptr_offs: offset of the rptr writeback location in the WB buffer
628 * @nop: nop packet for this ring
629 *
630 * Initialize the driver information for the selected ring (all asics).
631 * Returns 0 on success, error on failure.
632 */
633int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
634 unsigned rptr_offs, u32 nop)
635{
636 int r;
637
638 ring->ring_size = ring_size;
639 ring->rptr_offs = rptr_offs;
640 ring->nop = nop;
641 /* Allocate ring buffer */
642 if (ring->ring_obj == NULL) {
643 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
644 RADEON_GEM_DOMAIN_GTT,
645 NULL, &ring->ring_obj);
646 if (r) {
647 dev_err(rdev->dev, "(%d) ring create failed\n", r);
648 return r;
649 }
650 r = radeon_bo_reserve(ring->ring_obj, false);
651 if (unlikely(r != 0))
652 return r;
653 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
654 &ring->gpu_addr);
655 if (r) {
656 radeon_bo_unreserve(ring->ring_obj);
657 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
658 return r;
659 }
660 r = radeon_bo_kmap(ring->ring_obj,
661 (void **)__UNVOLATILE(&ring->ring));
662 radeon_bo_unreserve(ring->ring_obj);
663 if (r) {
664 dev_err(rdev->dev, "(%d) ring map failed\n", r);
665 return r;
666 }
667 }
668 ring->ptr_mask = (ring->ring_size / 4) - 1;
669 ring->ring_free_dw = ring->ring_size / 4;
670 if (rdev->wb.enabled) {
671 u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
672 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
673 ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
674 }
675 if (radeon_debugfs_ring_init(rdev, ring)) {
676 DRM_ERROR("Failed to register debugfs file for rings !\n");
677 }
678 radeon_ring_lockup_update(rdev, ring);
679 return 0;
680}
681
682/**
683 * radeon_ring_fini - tear down the driver ring struct.
684 *
685 * @rdev: radeon_device pointer
686 * @ring: radeon_ring structure holding ring information
687 *
688 * Tear down the driver information for the selected ring (all asics).
689 */
690void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
691{
692 int r;
693 struct radeon_bo *ring_obj;
694
695 mutex_lock(&rdev->ring_lock);
696 ring_obj = ring->ring_obj;
697 ring->ready = false;
698 ring->ring = NULL;
699 ring->ring_obj = NULL;
700 mutex_unlock(&rdev->ring_lock);
701
702 if (ring_obj) {
703 r = radeon_bo_reserve(ring_obj, false);
704 if (likely(r == 0)) {
705 radeon_bo_kunmap(ring_obj);
706 radeon_bo_unpin(ring_obj);
707 radeon_bo_unreserve(ring_obj);
708 }
709 radeon_bo_unref(&ring_obj);
710 }
711}
712
713/*
714 * Debugfs info
715 */
716#if defined(CONFIG_DEBUG_FS)
717
718static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
719{
720 struct drm_info_node *node = (struct drm_info_node *) m->private;
721 struct drm_device *dev = node->minor->dev;
722 struct radeon_device *rdev = dev->dev_private;
723 int ridx = *(int*)node->info_ent->data;
724 struct radeon_ring *ring = &rdev->ring[ridx];
725
726 uint32_t rptr, wptr, rptr_next;
727 unsigned count, i, j;
728
729 radeon_ring_free_size(rdev, ring);
730 count = (ring->ring_size / 4) - ring->ring_free_dw;
731
732 wptr = radeon_ring_get_wptr(rdev, ring);
733 seq_printf(m, "wptr: 0x%08x [%5d]\n",
734 wptr, wptr);
735
736 rptr = radeon_ring_get_rptr(rdev, ring);
737 seq_printf(m, "rptr: 0x%08x [%5d]\n",
738 rptr, rptr);
739
740 if (ring->rptr_save_reg) {
741 rptr_next = RREG32(ring->rptr_save_reg);
742 seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n",
743 ring->rptr_save_reg, rptr_next, rptr_next);
744 } else
745 rptr_next = ~0;
746
747 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
748 ring->wptr, ring->wptr);
749 seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
750 ring->last_semaphore_signal_addr);
751 seq_printf(m, "last semaphore wait addr : 0x%016llx\n",
752 ring->last_semaphore_wait_addr);
753 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
754 seq_printf(m, "%u dwords in ring\n", count);
755
756 if (!ring->ready)
757 return 0;
758
759 /* print 8 dw before current rptr as often it's the last executed
760 * packet that is the root issue
761 */
762 i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
763 for (j = 0; j <= (count + 32); j++) {
764 seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
765 if (rptr == i)
766 seq_puts(m, " *");
767 if (rptr_next == i)
768 seq_puts(m, " #");
769 seq_puts(m, "\n");
770 i = (i + 1) & ring->ptr_mask;
771 }
772 return 0;
773}
774
775static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
776static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
777static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
778static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
779static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
780static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
781static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX;
782static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX;
783
784static struct drm_info_list radeon_debugfs_ring_info_list[] = {
785 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
786 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index},
787 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index},
788 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
789 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
790 {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
791 {"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index},
792 {"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index},
793};
794
795static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
796{
797 struct drm_info_node *node = (struct drm_info_node *) m->private;
798 struct drm_device *dev = node->minor->dev;
799 struct radeon_device *rdev = dev->dev_private;
800
801 radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
802
803 return 0;
804
805}
806
807static struct drm_info_list radeon_debugfs_sa_list[] = {
808 {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
809};
810
811#endif
812
813static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
814{
815#if defined(CONFIG_DEBUG_FS)
816 unsigned i;
817 for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
818 struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
819 int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
820 unsigned r;
821
822 if (&rdev->ring[ridx] != ring)
823 continue;
824
825 r = radeon_debugfs_add_files(rdev, info, 1);
826 if (r)
827 return r;
828 }
829#endif
830 return 0;
831}
832
833static int radeon_debugfs_sa_init(struct radeon_device *rdev)
834{
835#if defined(CONFIG_DEBUG_FS)
836 return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
837#else
838 return 0;
839#endif
840}
841