1 | /* $NetBSD: nouveau_engine_dmaobj_nvc0.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_dmaobj_nvc0.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $" ); |
29 | |
30 | #include <core/device.h> |
31 | #include <core/gpuobj.h> |
32 | #include <core/class.h> |
33 | |
34 | #include <subdev/fb.h> |
35 | #include <engine/dmaobj.h> |
36 | |
37 | struct nvc0_dmaeng_priv { |
38 | struct nouveau_dmaeng base; |
39 | }; |
40 | |
41 | static int |
42 | nvc0_dmaobj_bind(struct nouveau_dmaeng *dmaeng, |
43 | struct nouveau_object *parent, |
44 | struct nouveau_dmaobj *dmaobj, |
45 | struct nouveau_gpuobj **pgpuobj) |
46 | { |
47 | u32 flags0 = nv_mclass(dmaobj); |
48 | u32 flags5 = 0x00000000; |
49 | int ret; |
50 | |
51 | if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { |
52 | switch (nv_mclass(parent->parent)) { |
53 | case NVA3_DISP_MAST_CLASS: |
54 | case NVA3_DISP_SYNC_CLASS: |
55 | case NVA3_DISP_OVLY_CLASS: |
56 | break; |
57 | default: |
58 | return -EINVAL; |
59 | } |
60 | } else |
61 | return 0; |
62 | |
63 | if (!(dmaobj->conf0 & NVC0_DMA_CONF0_ENABLE)) { |
64 | if (dmaobj->target == NV_MEM_TARGET_VM) { |
65 | dmaobj->conf0 = NVC0_DMA_CONF0_PRIV_VM; |
66 | dmaobj->conf0 |= NVC0_DMA_CONF0_TYPE_VM; |
67 | } else { |
68 | dmaobj->conf0 = NVC0_DMA_CONF0_PRIV_US; |
69 | dmaobj->conf0 |= NVC0_DMA_CONF0_TYPE_LINEAR; |
70 | dmaobj->conf0 |= 0x00020000; |
71 | } |
72 | } |
73 | |
74 | flags0 |= (dmaobj->conf0 & NVC0_DMA_CONF0_TYPE) << 22; |
75 | flags0 |= (dmaobj->conf0 & NVC0_DMA_CONF0_PRIV); |
76 | flags5 |= (dmaobj->conf0 & NVC0_DMA_CONF0_UNKN); |
77 | |
78 | switch (dmaobj->target) { |
79 | case NV_MEM_TARGET_VM: |
80 | flags0 |= 0x00000000; |
81 | break; |
82 | case NV_MEM_TARGET_VRAM: |
83 | flags0 |= 0x00010000; |
84 | break; |
85 | case NV_MEM_TARGET_PCI: |
86 | flags0 |= 0x00020000; |
87 | break; |
88 | case NV_MEM_TARGET_PCI_NOSNOOP: |
89 | flags0 |= 0x00030000; |
90 | break; |
91 | default: |
92 | return -EINVAL; |
93 | } |
94 | |
95 | switch (dmaobj->access) { |
96 | case NV_MEM_ACCESS_VM: |
97 | break; |
98 | case NV_MEM_ACCESS_RO: |
99 | flags0 |= 0x00040000; |
100 | break; |
101 | case NV_MEM_ACCESS_WO: |
102 | case NV_MEM_ACCESS_RW: |
103 | flags0 |= 0x00080000; |
104 | break; |
105 | } |
106 | |
107 | ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); |
108 | if (ret == 0) { |
109 | nv_wo32(*pgpuobj, 0x00, flags0); |
110 | nv_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->limit)); |
111 | nv_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->start)); |
112 | nv_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->limit) << 24 | |
113 | upper_32_bits(dmaobj->start)); |
114 | nv_wo32(*pgpuobj, 0x10, 0x00000000); |
115 | nv_wo32(*pgpuobj, 0x14, flags5); |
116 | } |
117 | |
118 | return ret; |
119 | } |
120 | |
121 | static int |
122 | nvc0_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
123 | struct nouveau_oclass *oclass, void *data, u32 size, |
124 | struct nouveau_object **pobject) |
125 | { |
126 | struct nvc0_dmaeng_priv *priv; |
127 | int ret; |
128 | |
129 | ret = nouveau_dmaeng_create(parent, engine, oclass, &priv); |
130 | *pobject = nv_object(priv); |
131 | if (ret) |
132 | return ret; |
133 | |
134 | nv_engine(priv)->sclass = nouveau_dmaobj_sclass; |
135 | priv->base.bind = nvc0_dmaobj_bind; |
136 | return 0; |
137 | } |
138 | |
139 | struct nouveau_oclass |
140 | nvc0_dmaeng_oclass = { |
141 | .handle = NV_ENGINE(DMAOBJ, 0xc0), |
142 | .ofuncs = &(struct nouveau_ofuncs) { |
143 | .ctor = nvc0_dmaeng_ctor, |
144 | .dtor = _nouveau_dmaeng_dtor, |
145 | .init = _nouveau_dmaeng_init, |
146 | .fini = _nouveau_dmaeng_fini, |
147 | }, |
148 | }; |
149 | |