1 | /* $NetBSD: if_xireg.h,v 1.8 2005/12/11 12:23:23 christos Exp $ */ |
2 | /* OpenBSD: if_xereg.h,v 1.1 1999/05/18 19:18:21 niklas Exp */ |
3 | |
4 | /* |
5 | * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas |
6 | * All rights reserved. |
7 | * |
8 | * Redistribution and use in source and binary forms, with or without |
9 | * modification, are permitted provided that the following conditions |
10 | * are met: |
11 | * 1. Redistributions of source code must retain the above copyright |
12 | * notice, this list of conditions and the following disclaimer. |
13 | * 2. Redistributions in binary form must reproduce the above copyright |
14 | * notice, this list of conditions and the following disclaimer in the |
15 | * documentation and/or other materials provided with the distribution. |
16 | * 3. All advertising materials mentioning features or use of this software |
17 | * must display the following acknowledgement: |
18 | * This product includes software developed by Niklas Hallqvist, |
19 | * Brandon Creighton and Job de Haas. |
20 | * 4. The name of the author may not be used to endorse or promote products |
21 | * derived from this software without specific prior written permission |
22 | * |
23 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
24 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
25 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
26 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
28 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
29 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
30 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
32 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
33 | */ |
34 | |
35 | #define PCMCIA_CCR_ECOR |
36 | |
37 | /* Additional Card Configuration Registers (CCR) on Dingo */ |
38 | |
39 | #define PCMCIA_CCR_DCOR0 0x20 |
40 | #define PCMCIA_CCR_DCOR0_MRST_SFRST 0x80 |
41 | #define PCMCIA_CCR_DCOR0_MRST_SFPWDN 0x40 |
42 | #define PCMCIA_CCR_DCOR0_LED3_SFRST 0x20 |
43 | #define PCMCIA_CCR_DCOR0_LED3_SFPWDN 0x10 |
44 | #define PCMCIA_CCR_DCOR0_BUS 0x08 |
45 | #define PCMCIA_CCR_DCOR0_DECODE 0x04 |
46 | #define PCMCIA_CCR_DCOR0_SFINT 0x01 |
47 | #define PCMCIA_CCR_DCOR1 0x22 |
48 | #define PCMCIA_CCR_DCOR1_SFCSR_WAIT 0xC0 |
49 | #define PCMCIA_CCR_DCOR1_SHADOW_SFIOB 0x20 |
50 | #define PCMCIA_CCR_DCOR1_SHADOW_SFCSR 0x10 |
51 | #define PCMCIA_CCR_DCOR1_FORCE_LEVIREQ 0x08 |
52 | #define PCMCIA_CCR_DCOR1_D6 0x04 |
53 | #define PCMCIA_CCR_DCOR1_SF_STSCHG 0x02 |
54 | #define PCMCIA_CCR_DCOR1_SF_IREQ 0x01 |
55 | #define PCMCIA_CCR_DCOR2 0x24 |
56 | #define PCMCIA_CCR_DCOR2_SHADOW_SFCOR 0x10 |
57 | #define PCMCIA_CCR_DCOR2_SMEM_BASE 0x0F |
58 | #define PCMCIA_CCR_DCOR3 0x26 |
59 | #define PCMCIA_CCR_DCOR4 0x28 |
60 | #define PCMCIA_CCR_SFCOR 0x40 |
61 | #define PCMCIA_CCR_SFCOR_SRESET 0x80 |
62 | #define PCMCIA_CCR_SFCOR_LEVIREQ 0x40 |
63 | #define PCMCIA_CCR_SFCOR_IRQ_STSCHG 0x20 |
64 | #define PCMCIA_CCR_SFCOR_CFINDEX 0x18 |
65 | #define PCMCIA_CCR_SFCOR_IREQ_ENABLE 0x04 |
66 | #define PCMCIA_CCR_SFCOR_ADDR_DECODE 0x02 |
67 | #define PCMCIA_CCR_SFCOR_FUNC_ENABLE 0x01 |
68 | #define PCMCIA_CCR_SFCSR 0x42 |
69 | #define PCMCIA_CCR_SFCSR_IOIS8 0x20 |
70 | #define PCMCIA_CCR_SFCSR_AUDIO 0x08 |
71 | #define PCMCIA_CCR_SFCSR_PWRDWN 0x04 |
72 | #define PCMCIA_CCR_SFCSR_INTR 0x02 |
73 | #define PCMCIA_CCR_SFCSR_INTRACK 0x01 |
74 | #define PCMCIA_CCR_SFIOBASE0 0x4A |
75 | #define PCMCIA_CCR_SFIOBASE1 0x4C |
76 | #define PCMCIA_CCR_SFILR 0x52 |
77 | |
78 | #define PCMCIA_CCR_SIZE_DINGO 0x54 |
79 | |
80 | #define XI_IOSIZE 16 |
81 | |
82 | /* All pages */ |
83 | #define CR 0x0 /* W - Command register */ |
84 | #define ESR 0x0 /* R - Ethernet status register */ |
85 | #define PR 0x1 /* RW - Page register select */ |
86 | #define EDP 0x4 /* RW - Ethernet data port, 4 registers */ |
87 | #define ISR0 0x6 /* R - Ethernet interrupt status register */ |
88 | #define GIR 0x7 /* RW - Global interrupt register - dingo only */ |
89 | #define PTR 0xd /* R - Packets Transmitted register */ |
90 | |
91 | /* Page 0 */ |
92 | #define TSO 0x8 /* R - Transmit space open, 3 registers */ |
93 | #define TRS 0xa /* W - Transmit reservation size */ |
94 | #define DO0 0xc /* W - Data offset, 2 registers */ |
95 | #define DO1 0xd |
96 | #define RSR 0xc /* R - Rx status register */ |
97 | #define TPR 0xd /* R - Tx packets register */ |
98 | #define RBC0 0xe /* R - Rx byte count, 2 registers */ |
99 | #define RBC1 0xf |
100 | |
101 | /* Page 1 */ |
102 | #define IMR0 0xc /* RW - Interrupt mask, 2 registers */ |
103 | #define IMR1 0xd |
104 | #define ECR 0xe /* RW - Ethernet config register */ |
105 | |
106 | /* Page 2 */ |
107 | #define RBS0 0x8 /* RW - Receive buffer start, 2 registers */ |
108 | #define RBS1 0x9 |
109 | #define LED 0xa /* RW - LED control register */ |
110 | #define LED3 0xb /* RW - LED3 control register */ |
111 | #define MSR 0xc /* RW - Misc. setup register */ |
112 | #define GP2 0xd /* RW - General purpose register 2 */ |
113 | |
114 | /* Page 3 */ |
115 | #define TPT0 0xa /* RW - Tx packet threshold, 2 registers */ |
116 | #define TPT1 0xb |
117 | |
118 | /* Page 4 */ |
119 | #define GP0 0x8 /* RW - General purpose register 0 */ |
120 | #define GP1 0x9 /* RW - General purpose register 1 */ |
121 | #define BV 0xa /* R - Bonding version register */ |
122 | #define EES 0xb /* RW - EEPROM control register */ |
123 | |
124 | /* Page 5 */ |
125 | #define RHSA0 0xa /* RX host start address */ |
126 | |
127 | /* Page 6 */ |
128 | |
129 | /* Page 7 */ |
130 | |
131 | /* Page 8 */ |
132 | |
133 | /* Page 16 */ |
134 | |
135 | /* Page 0x40 */ |
136 | #define CMD0 0x8 /* W - Receive status register */ |
137 | #define RXST0 0x9 /* RW - Receive status register */ |
138 | #define TXST0 0xb /* RW - Transmit status, 2 registers */ |
139 | #define TXST1 0xc |
140 | #define RX0MSK 0xd /* RW - Receive status mask register */ |
141 | #define TX0MSK 0xe /* RW - Transmit status mask, 2 registers */ |
142 | #define TX1MSK 0xf /* RW - Dingo does not define this register */ |
143 | |
144 | /* Page 0x42 */ |
145 | #define SWC0 0x8 /* RW - Software configuration, 2 registers */ |
146 | #define SWC1 0x9 |
147 | |
148 | /* Page 0x50-0x57 */ |
149 | #define IA 0x8 /* RW - Individual address */ |
150 | |
151 | /* CR register bits */ |
152 | #define TX_PKT 0x01 /* Transmit packet. */ |
153 | #define SOFT_RESET 0x02 /* Software reset. */ |
154 | #define ENABLE_INT 0x04 /* Enable interrupt. */ |
155 | #define FORCE_INT 0x08 /* Force interrupt. */ |
156 | #define CLR_TX_FIFO 0x10 /* Clear transmit FIFO. */ |
157 | #define CLR_RX_OVERRUN 0x20 /* Clear receive overrun. */ |
158 | #define RESTART_TX 0x40 /* Restart transmit process. */ |
159 | |
160 | /* ESR register bits */ |
161 | #define FULL_PKT_RCV 0x01 /* Full packet received. */ |
162 | #define PKT_REJECTED 0x04 /* A packet was rejected. */ |
163 | #define TX_PKT_PEND 0x08 /* TX Packet Pending. */ |
164 | #define INCOR_POLARITY 0x10 /* XXX from linux driver, but not used there */ |
165 | #define MEDIA_SELECT 0x20 /* set if TP, clear if AUI */ |
166 | |
167 | /* DO register bits */ |
168 | #define DO_OFF_MASK 0x1fff /* Mask for offset value. */ |
169 | #define DO_CHG_OFFSET 0x2000 /* Change offset command. */ |
170 | #define DO_SHM_MODE 0x4000 /* Shared memory mode. */ |
171 | #define DO_SKIP_RX_PKT 0x8000 /* Skip Rx packet. */ |
172 | |
173 | /* RBC register bits */ |
174 | #define RBC_COUNT_MASK 0x1fff /* Mask for byte count. */ |
175 | #define RBC_RX_FULL 0x2000 /* Receive full packet. */ |
176 | #define RBC_RX_PARTIAL 0x4000 /* Receive partial packet. */ |
177 | #define RBC_RX_PKT_REJ 0x8000 /* Receive packet rejected. */ |
178 | |
179 | /* ISR0(/IMR0) register bits */ |
180 | #define ISR_TX_OFLOW 0x01 /* Transmit buffer overflow. */ |
181 | #define ISR_PKT_TX 0x02 /* Packet transmitted. */ |
182 | #define ISR_MAC_INT 0x04 /* MAC interrupt. */ |
183 | #define ISR_RX_EARLY 0x10 /* Receive early packet. */ |
184 | #define ISR_RX_FULL 0x20 /* Receive full packet. */ |
185 | #define ISR_RX_PKT_REJ 0x40 /* Receive packet rejected. */ |
186 | #define ISR_FORCED_INT 0x80 /* Forced interrupt. */ |
187 | |
188 | /* ECR register bits */ |
189 | #define ECR_EARLY_TX 0x01 /* Early transmit mode. */ |
190 | #define ECR_EARLY_RX 0x02 /* Early receive mode. */ |
191 | #define ECR_FULL_DUPLEX 0x04 /* Full duplex select. */ |
192 | #define ECR_LNK_PLS_DIS 0x20 /* Link pulse disable. */ |
193 | #define ECR_SW_COMPAT 0x80 /* Software compatibility switch. */ |
194 | |
195 | /* GP0 register bits */ |
196 | #define GP1_WR 0x01 /* GP1 pin output value. */ |
197 | #define GP2_WR 0x02 /* GP2 pin output value. */ |
198 | #define GP1_OUT 0x04 /* GP1 pin output select. */ |
199 | #define GP2_OUT 0x08 /* GP2 pin output select. */ |
200 | #define GP1_RD 0x10 /* GP1 pin input value. */ |
201 | #define GP2_RD 0x20 /* GP2 pin input value. */ |
202 | |
203 | /* GP1 register bits */ |
204 | #define POWER_UP 0x01 /* When 0, power down analogue part of chip. */ |
205 | |
206 | /* LED register bits */ |
207 | #define LED0_SHIFT 0 /* LED0 Output shift & mask */ |
208 | #define LED0_MASK 0x7 |
209 | #define LED1_SHIFT 3 /* LED1 Output shift & mask */ |
210 | #define LED1_MASK 0x38 |
211 | #define LED0_RX_ENA 0x40 /* LED0 - receive enable */ |
212 | #define LED1_RX_ENA 0x80 /* LED1 - receive enable */ |
213 | |
214 | /* LED3 register bits */ |
215 | #define LED3_SHIFT 0 /* LED0 output shift & mask */ |
216 | #define LED3_MASK 0x7 |
217 | #define LED3_RX_ENA 0x40 /* LED0 - receive enable */ |
218 | |
219 | /* LED output values */ |
220 | #define LED_DISABLE 0 /* LED disabled */ |
221 | #define LED_COLL_ACT 1 /* Collision activity */ |
222 | #define LED_COLL_INACT 2 /* (NOT) Collision activity */ |
223 | #define LED_10MB_LINK 3 /* 10 Mb link detected */ |
224 | #define LED_100MB_LINK 4 /* 100 Mb link detected */ |
225 | #define LED_LINK 5 /* 10 Mb or 100 Mb link detected */ |
226 | #define LED_AUTO 6 /* Automatic assertion */ |
227 | #define LED_TX_ACT 7 /* Transmit activity */ |
228 | |
229 | /* MSR register bits */ |
230 | #define SRAM_128K_EXT 0x01 /* 128K SRAM extension */ |
231 | #define RBS_BIT16 0x02 /* RBS bit 16 */ |
232 | #define SELECT_MII 0x08 /* Select MII */ |
233 | #define HASH_TBL_ENA 0x20 /* Hash table enable */ |
234 | |
235 | /* GP2 register bits */ |
236 | #define GP3_WR 0x01 /* GP3 pin output value. */ |
237 | #define GP4_WR 0x02 /* GP4 pin output value. */ |
238 | #define GP3_OUT 0x04 /* GP3 pin output select. */ |
239 | #define GP4_OUT 0x08 /* GP4 pin output select. */ |
240 | #define GP3_RD 0x10 /* GP3 pin input value. */ |
241 | #define GP4_RD 0x20 /* GP4 pin input value. */ |
242 | |
243 | /* RSR register bits */ |
244 | #define RSR_NOTMCAST 0x01 /* clear when multicast packet */ |
245 | #define RSR_BCAST 0x02 /* set when broadcast packet */ |
246 | #define RSR_TOO_LONG 0x04 /* set if packet is longer than 1518 octets */ |
247 | #define RSR_ALIGNERR 0x10 /* incorrect CRC and last octet not complete */ |
248 | #define RSR_CRCERR 0x20 /* incorrect CRC and last octet complete */ |
249 | #define RSR_RX_OK 0x80 /* packet received okay */ |
250 | |
251 | /* CMD0 register bits */ |
252 | #define ONLINE 0x04 /* Online */ |
253 | #define OFFLINE 0x08 /* Online */ |
254 | #define ENABLE_RX 0x20 /* Enable reciever */ |
255 | #define DISABLE_RX 0x80 /* Disable receiver */ |
256 | |
257 | /* RX0Msk register bits */ |
258 | #define PKT_TOO_LONG 0x02 /* Packet too long mask. */ |
259 | #define CRC_ERR 0x08 /* CRC error mask. */ |
260 | #define RX_OVERRUN 0x10 /* Receive overrun mask. */ |
261 | #define RX_ABORT 0x40 /* Receive abort mask. */ |
262 | #define RX_OK 0x80 /* Receive OK mask. */ |
263 | |
264 | /* TX0Msk register bits */ |
265 | #define CARRIER_LOST 0x01 /* Carrier sense lost. */ |
266 | #define EXCESSIVE_COLL 0x02 /* Excessive collisions mask. */ |
267 | #define TX_UNDERRUN 0x08 /* Transmit underrun mask. */ |
268 | #define LATE_COLLISION 0x10 /* Late collision mask. */ |
269 | #define SQE 0x20 /* Signal quality error mask.. */ |
270 | #define TX_ABORT 0x40 /* Transmit abort mask. */ |
271 | #define TX_OK 0x80 /* Transmit OK mask. */ |
272 | |
273 | /* SWC1 register bits */ |
274 | #define SWC1_IND_ADDR 0x01 /* Individual address enable. */ |
275 | #define SWC1_MCAST_PROM 0x02 /* Multicast promiscuous enable. */ |
276 | #define SWC1_PROMISC 0x04 /* Promiscuous mode enable. */ |
277 | #define SWC1_BCAST_DIS 0x08 /* Broadcast disable. */ |
278 | #define SWC1_MEDIA_SEL 0x40 /* Media select (Mohawk). */ |
279 | #define SWC1_AUTO_MEDIA 0x80 /* Automatic media select (Mohawk). */ |
280 | |
281 | /* Misc. defines. */ |
282 | |
283 | #define PAGE(sc, page) \ |
284 | bus_space_write_1((sc->sc_bst), (sc->sc_bsh), PR, (page)) |
285 | |
286 | /* |
287 | * GP3 is connected to the MDC pin of the NS DP83840A PHY, GP4 is |
288 | * connected to the MDIO pin. These are utility macros to enhance |
289 | * readability of the code. |
290 | */ |
291 | #define MDC_LOW GP3_OUT |
292 | #define MDC_HIGH (GP3_OUT | GP3_WR) |
293 | #define MDIO_LOW GP4_OUT |
294 | #define MDIO_HIGH (GP4_OUT | GP4_WR) |
295 | #define MDIO GP4_RD |
296 | |
297 | /* Values found in MANFID. */ |
298 | #define XIMEDIA_ETHER 0x01 |
299 | #define XIMEDIA_TOKEN 0x02 |
300 | #define XIMEDIA_ARC 0x04 |
301 | #define XIMEDIA_WIRELESS 0x08 |
302 | #define XIMEDIA_MODEM 0x10 |
303 | #define XIMEDIA_GSM 0x20 |
304 | |
305 | #define XIPROD_IDMASK 0x0f |
306 | #define XIPROD_POCKET 0x10 |
307 | #define XIPROD_EXTERNAL 0x20 |
308 | #define XIPROD_CREDITCARD 0x40 |
309 | #define XIPROD_CARDBUS 0x80 |
310 | |