1 | /* $NetBSD */ |
2 | /*- |
3 | * Copyright (c) 2010 The NetBSD Foundation, Inc. |
4 | * All rights reserved. |
5 | * |
6 | * This code is derived from software contributed to The NetBSD Foundation |
7 | * by Jean-Yves Migeon <jym@NetBSD.org> |
8 | * |
9 | * Redistribution and use in source and binary forms, with or without |
10 | * modification, are permitted provided that the following conditions |
11 | * are met: |
12 | * 1. Redistributions of source code must retain the above copyright |
13 | * notice, this list of conditions and the following disclaimer. |
14 | * 2. Redistributions in binary form must reproduce the above copyright |
15 | * notice, this list of conditions and the following disclaimer in the |
16 | * documentation and/or other materials provided with the distribution. |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
19 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
20 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
21 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
22 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
28 | * POSSIBILITY OF SUCH DAMAGE. |
29 | * |
30 | * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.4 2006/05/04 00:34:07 mjacob Exp $ |
31 | */ |
32 | |
33 | #ifndef _DEV_PCI_IF_BNXVAR_H_ |
34 | #define _DEV_PCI_IF_BNXVAR_H_ |
35 | |
36 | #ifdef _KERNEL_OPT |
37 | #include "opt_inet.h" |
38 | #endif |
39 | |
40 | #include <sys/param.h> |
41 | #include <sys/systm.h> |
42 | #include <sys/sockio.h> |
43 | #include <sys/mbuf.h> |
44 | #include <sys/malloc.h> |
45 | #include <sys/kernel.h> |
46 | #include <sys/device.h> |
47 | #include <sys/socket.h> |
48 | #include <sys/sysctl.h> |
49 | #include <sys/workqueue.h> |
50 | |
51 | #include <net/if.h> |
52 | #include <net/if_dl.h> |
53 | #include <net/if_media.h> |
54 | #include <net/if_ether.h> |
55 | |
56 | #ifdef INET |
57 | #include <netinet/in.h> |
58 | #include <netinet/in_systm.h> |
59 | #include <netinet/in_var.h> |
60 | #include <netinet/ip.h> |
61 | #include <netinet/if_inarp.h> |
62 | #endif |
63 | |
64 | #include <net/if_vlanvar.h> |
65 | |
66 | #include <net/bpf.h> |
67 | |
68 | #include <dev/pci/pcireg.h> |
69 | #include <dev/pci/pcivar.h> |
70 | #include <dev/pci/pcidevs.h> |
71 | |
72 | #include <dev/mii/mii.h> |
73 | #include <dev/mii/miivar.h> |
74 | #include <dev/mii/miidevs.h> |
75 | #include <dev/mii/brgphyreg.h> |
76 | |
77 | /* |
78 | * PCI registers defined in the PCI 2.2 spec. |
79 | */ |
80 | #define BNX_PCI_BAR0 0x10 |
81 | #define BNX_PCI_PCIX_CMD 0x40 |
82 | |
83 | /****************************************************************************/ |
84 | /* Convenience definitions. */ |
85 | /****************************************************************************/ |
86 | #define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val) |
87 | #define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val) |
88 | #define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg) |
89 | #define REG_RD_IND(sc, offset) bnx_reg_rd_ind(sc, offset) |
90 | #define REG_WR_IND(sc, offset, val) bnx_reg_wr_ind(sc, offset, val) |
91 | #define CTX_WR(sc, cid_addr, offset, val) bnx_ctx_wr(sc, cid_addr, offset, val) |
92 | #define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) |
93 | #define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) |
94 | #define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) |
95 | #define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) |
96 | |
97 | /****************************************************************************/ |
98 | /* BNX Device State Data Structure */ |
99 | /****************************************************************************/ |
100 | |
101 | #define BNX_STATUS_BLK_SZ sizeof(struct status_block) |
102 | #define BNX_STATS_BLK_SZ sizeof(struct statistics_block) |
103 | #define BNX_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE |
104 | #define BNX_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE |
105 | |
106 | struct bnx_pkt { |
107 | TAILQ_ENTRY(bnx_pkt) pkt_entry; |
108 | bus_dmamap_t pkt_dmamap; |
109 | struct mbuf *pkt_mbuf; |
110 | uint16_t pkt_end_desc; |
111 | }; |
112 | |
113 | TAILQ_HEAD(bnx_pkt_list, bnx_pkt); |
114 | |
115 | struct bnx_softc |
116 | { |
117 | device_t bnx_dev; |
118 | struct ethercom bnx_ec; |
119 | struct pci_attach_args bnx_pa; |
120 | |
121 | struct ifmedia bnx_ifmedia; /* TBI media info */ |
122 | |
123 | bus_space_tag_t bnx_btag; /* Device bus tag */ |
124 | bus_space_handle_t bnx_bhandle; /* Device bus handle */ |
125 | bus_size_t bnx_size; |
126 | |
127 | void *bnx_intrhand; /* Interrupt handler */ |
128 | |
129 | /* packet allocation workqueue */ |
130 | struct workqueue *bnx_wq; |
131 | |
132 | /* ASIC Chip ID. */ |
133 | uint32_t bnx_chipid; |
134 | |
135 | /* General controller flags. */ |
136 | uint32_t bnx_flags; |
137 | |
138 | /* Controller capability flags. */ |
139 | uint32_t bnx_cap_flags; |
140 | #define BNX_MSI_CAPABLE_FLAG 0x00000001 |
141 | #define BNX_MSIX_CAPABLE_FLAG 0x00000002 |
142 | #define BNX_PCIE_CAPABLE_FLAG 0x00000004 |
143 | #define BNX_PCIX_CAPABLE_FLAG 0x00000008 |
144 | |
145 | /* PHY specific flags. */ |
146 | uint32_t bnx_phy_flags; |
147 | |
148 | /* Values that need to be shared with the PHY driver. */ |
149 | uint32_t bnx_shared_hw_cfg; |
150 | uint32_t bnx_port_hw_cfg; |
151 | |
152 | uint16_t bus_speed_mhz; /* PCI bus speed */ |
153 | uint16_t link_width; /* PCIe link width */ |
154 | uint16_t link_speed; /* PCIe link speed */ |
155 | struct flash_spec *bnx_flash_info; /* Flash NVRAM settings */ |
156 | uint32_t bnx_flash_size; /* Flash NVRAM size */ |
157 | uint32_t bnx_shmem_base;/* Shared Memory base address */ |
158 | char * bnx_name; /* Name string */ |
159 | |
160 | /* Tracks the version of bootcode firmware. */ |
161 | uint32_t bnx_fw_ver; |
162 | |
163 | /* Tracks the state of the firmware. 0 = Running while any */ |
164 | /* other value indicates that the firmware is not responding. */ |
165 | uint16_t bnx_fw_timed_out; |
166 | |
167 | /* An incrementing sequence used to coordinate messages passed */ |
168 | /* from the driver to the firmware. */ |
169 | uint16_t bnx_fw_wr_seq; |
170 | |
171 | /* An incrementing sequence used to let the firmware know that */ |
172 | /* the driver is still operating. Without the pulse, management */ |
173 | /* firmware such as IPMI or UMP will operate in OS absent state. */ |
174 | uint16_t bnx_fw_drv_pulse_wr_seq; |
175 | |
176 | /* Ethernet MAC address. */ |
177 | u_char eaddr[6]; |
178 | |
179 | /* These setting are used by the host coalescing (HC) block to */ |
180 | /* to control how often the status block, statistics block and */ |
181 | /* interrupts are generated. */ |
182 | uint16_t bnx_tx_quick_cons_trip_int; |
183 | uint16_t bnx_tx_quick_cons_trip; |
184 | uint16_t bnx_rx_quick_cons_trip_int; |
185 | uint16_t bnx_rx_quick_cons_trip; |
186 | uint16_t bnx_comp_prod_trip_int; |
187 | uint16_t bnx_comp_prod_trip; |
188 | uint16_t bnx_tx_ticks_int; |
189 | uint16_t bnx_tx_ticks; |
190 | uint16_t bnx_rx_ticks_int; |
191 | uint16_t bnx_rx_ticks; |
192 | uint16_t bnx_com_ticks_int; |
193 | uint16_t bnx_com_ticks; |
194 | uint16_t bnx_cmd_ticks_int; |
195 | uint16_t bnx_cmd_ticks; |
196 | uint32_t bnx_stats_ticks; |
197 | |
198 | /* The address of the integrated PHY on the MII bus. */ |
199 | int bnx_phy_addr; |
200 | |
201 | /* The device handle for the MII bus child device. */ |
202 | struct mii_data bnx_mii; |
203 | |
204 | /* Driver maintained TX chain pointers and byte counter. */ |
205 | uint16_t rx_prod; |
206 | uint16_t rx_cons; |
207 | uint32_t rx_prod_bseq; /* Counts the bytes used. */ |
208 | uint16_t tx_prod; |
209 | uint16_t tx_cons; |
210 | uint32_t tx_prod_bseq; /* Counts the bytes used. */ |
211 | |
212 | struct callout bnx_timeout; |
213 | |
214 | /* Frame size and mbuf allocation size for RX frames. */ |
215 | uint32_t max_frame_size; |
216 | int mbuf_alloc_size; |
217 | |
218 | /* Receive mode settings (i.e promiscuous, multicast, etc.). */ |
219 | uint32_t rx_mode; |
220 | |
221 | /* Bus tag for the bnx controller. */ |
222 | bus_dma_tag_t bnx_dmatag; |
223 | |
224 | /* H/W maintained TX buffer descriptor chain structure. */ |
225 | bus_dma_segment_t tx_bd_chain_seg[TX_PAGES]; |
226 | int tx_bd_chain_rseg[TX_PAGES]; |
227 | bus_dmamap_t tx_bd_chain_map[TX_PAGES]; |
228 | struct tx_bd *tx_bd_chain[TX_PAGES]; |
229 | bus_addr_t tx_bd_chain_paddr[TX_PAGES]; |
230 | |
231 | /* H/W maintained RX buffer descriptor chain structure. */ |
232 | bus_dma_segment_t rx_bd_chain_seg[RX_PAGES]; |
233 | int rx_bd_chain_rseg[RX_PAGES]; |
234 | bus_dmamap_t rx_bd_chain_map[RX_PAGES]; |
235 | struct rx_bd *rx_bd_chain[RX_PAGES]; |
236 | bus_addr_t rx_bd_chain_paddr[RX_PAGES]; |
237 | |
238 | /* H/W maintained status block. */ |
239 | bus_dma_segment_t status_seg; |
240 | int status_rseg; |
241 | bus_dmamap_t status_map; |
242 | struct status_block *status_block; /* virtual address */ |
243 | bus_addr_t status_block_paddr; /* Physical address */ |
244 | |
245 | /* H/W maintained context block */ |
246 | int ctx_pages; |
247 | bus_dma_segment_t ctx_segs[4]; |
248 | int ctx_rsegs[4]; |
249 | bus_dmamap_t ctx_map[4]; |
250 | void *ctx_block[4]; |
251 | |
252 | /* Driver maintained status block values. */ |
253 | uint16_t last_status_idx; |
254 | uint16_t hw_rx_cons; |
255 | uint16_t hw_tx_cons; |
256 | |
257 | /* H/W maintained statistics block. */ |
258 | bus_dma_segment_t stats_seg; |
259 | int stats_rseg; |
260 | bus_dmamap_t stats_map; |
261 | struct statistics_block *stats_block; /* Virtual address */ |
262 | bus_addr_t stats_block_paddr; /* Physical address */ |
263 | |
264 | /* Bus tag for RX/TX mbufs. */ |
265 | bus_dma_segment_t rx_mbuf_seg; |
266 | int rx_mbuf_rseg; |
267 | bus_dma_segment_t tx_mbuf_seg; |
268 | int tx_mbuf_rseg; |
269 | |
270 | /* S/W maintained mbuf TX chain structure. */ |
271 | kmutex_t tx_pkt_mtx; |
272 | uint tx_pkt_count; |
273 | struct bnx_pkt_list tx_free_pkts; |
274 | struct bnx_pkt_list tx_used_pkts; |
275 | |
276 | /* S/W maintained mbuf RX chain structure. */ |
277 | bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD]; |
278 | struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD]; |
279 | |
280 | /* Track the number of rx_bd and tx_bd's in use. */ |
281 | uint16_t free_rx_bd; |
282 | uint16_t max_rx_bd; |
283 | uint16_t used_tx_bd; |
284 | uint16_t max_tx_bd; |
285 | |
286 | /* Provides access to hardware statistics through sysctl. */ |
287 | uint64_t stat_IfHCInOctets; |
288 | uint64_t stat_IfHCInBadOctets; |
289 | uint64_t stat_IfHCOutOctets; |
290 | uint64_t stat_IfHCOutBadOctets; |
291 | uint64_t stat_IfHCInUcastPkts; |
292 | uint64_t stat_IfHCInMulticastPkts; |
293 | uint64_t stat_IfHCInBroadcastPkts; |
294 | uint64_t stat_IfHCOutUcastPkts; |
295 | uint64_t stat_IfHCOutMulticastPkts; |
296 | uint64_t stat_IfHCOutBroadcastPkts; |
297 | |
298 | uint32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; |
299 | uint32_t stat_Dot3StatsCarrierSenseErrors; |
300 | uint32_t stat_Dot3StatsFCSErrors; |
301 | uint32_t stat_Dot3StatsAlignmentErrors; |
302 | uint32_t stat_Dot3StatsSingleCollisionFrames; |
303 | uint32_t stat_Dot3StatsMultipleCollisionFrames; |
304 | uint32_t stat_Dot3StatsDeferredTransmissions; |
305 | uint32_t stat_Dot3StatsExcessiveCollisions; |
306 | uint32_t stat_Dot3StatsLateCollisions; |
307 | uint32_t stat_EtherStatsCollisions; |
308 | uint32_t stat_EtherStatsFragments; |
309 | uint32_t stat_EtherStatsJabbers; |
310 | uint32_t stat_EtherStatsUndersizePkts; |
311 | uint32_t stat_EtherStatsOverrsizePkts; |
312 | uint32_t stat_EtherStatsPktsRx64Octets; |
313 | uint32_t stat_EtherStatsPktsRx65Octetsto127Octets; |
314 | uint32_t stat_EtherStatsPktsRx128Octetsto255Octets; |
315 | uint32_t stat_EtherStatsPktsRx256Octetsto511Octets; |
316 | uint32_t stat_EtherStatsPktsRx512Octetsto1023Octets; |
317 | uint32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; |
318 | uint32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; |
319 | uint32_t stat_EtherStatsPktsTx64Octets; |
320 | uint32_t stat_EtherStatsPktsTx65Octetsto127Octets; |
321 | uint32_t stat_EtherStatsPktsTx128Octetsto255Octets; |
322 | uint32_t stat_EtherStatsPktsTx256Octetsto511Octets; |
323 | uint32_t stat_EtherStatsPktsTx512Octetsto1023Octets; |
324 | uint32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; |
325 | uint32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; |
326 | uint32_t stat_XonPauseFramesReceived; |
327 | uint32_t stat_XoffPauseFramesReceived; |
328 | uint32_t stat_OutXonSent; |
329 | uint32_t stat_OutXoffSent; |
330 | uint32_t stat_FlowControlDone; |
331 | uint32_t stat_MacControlFramesReceived; |
332 | uint32_t stat_XoffStateEntered; |
333 | uint32_t stat_IfInFramesL2FilterDiscards; |
334 | uint32_t stat_IfInRuleCheckerDiscards; |
335 | uint32_t stat_IfInFTQDiscards; |
336 | uint32_t stat_IfInMBUFDiscards; |
337 | uint32_t stat_IfInRuleCheckerP4Hit; |
338 | uint32_t stat_CatchupInRuleCheckerDiscards; |
339 | uint32_t stat_CatchupInFTQDiscards; |
340 | uint32_t stat_CatchupInMBUFDiscards; |
341 | uint32_t stat_CatchupInRuleCheckerP4Hit; |
342 | |
343 | /* Mbuf allocation failure counter. */ |
344 | uint32_t mbuf_alloc_failed; |
345 | |
346 | /* TX DMA mapping failure counter. */ |
347 | uint32_t tx_dma_map_failures; |
348 | |
349 | #ifdef BNX_DEBUG |
350 | /* Track the number of enqueued mbufs. */ |
351 | int tx_mbuf_alloc; |
352 | int rx_mbuf_alloc; |
353 | |
354 | /* Track the distribution buffer segments. */ |
355 | uint32_t rx_mbuf_segs[BNX_MAX_SEGMENTS+1]; |
356 | |
357 | /* Track how many and what type of interrupts are generated. */ |
358 | uint32_t interrupts_generated; |
359 | uint32_t interrupts_handled; |
360 | uint32_t rx_interrupts; |
361 | uint32_t tx_interrupts; |
362 | |
363 | uint32_t rx_low_watermark; /* Lowest number of rx_bd's free. */ |
364 | uint32_t rx_empty_count; /* Number of times the RX chain was empty. */ |
365 | uint32_t tx_hi_watermark; /* Greatest number of tx_bd's used. */ |
366 | uint32_t tx_full_count; /* Number of times the TX chain was full. */ |
367 | uint32_t mbuf_sim_alloc_failed;/* Mbuf simulated allocation failure counter. */ |
368 | uint32_t l2fhdr_status_errors; |
369 | uint32_t unexpected_attentions; |
370 | uint32_t lost_status_block_updates; |
371 | #endif |
372 | }; |
373 | |
374 | struct { |
375 | int ; |
376 | int ; |
377 | int ; |
378 | uint32_t ; |
379 | uint32_t ; |
380 | int ; |
381 | uint32_t ; |
382 | int ; |
383 | uint32_t ; |
384 | int ; |
385 | uint32_t ; |
386 | int ; |
387 | uint32_t ; |
388 | int ; |
389 | |
390 | int ; |
391 | int ; |
392 | int ; |
393 | uint32_t ; |
394 | uint32_t ; |
395 | int ; |
396 | uint32_t ; |
397 | int ; |
398 | uint32_t ; |
399 | int ; |
400 | uint32_t ; |
401 | int ; |
402 | uint32_t ; |
403 | int ; |
404 | |
405 | int ; |
406 | int ; |
407 | int ; |
408 | uint32_t ; |
409 | uint32_t ; |
410 | int ; |
411 | uint32_t ; |
412 | int ; |
413 | uint32_t ; |
414 | int ; |
415 | uint32_t ; |
416 | int ; |
417 | uint32_t ; |
418 | int ; |
419 | |
420 | int ; |
421 | int ; |
422 | int ; |
423 | uint32_t ; |
424 | uint32_t ; |
425 | int ; |
426 | uint32_t ; |
427 | int ; |
428 | uint32_t ; |
429 | int ; |
430 | uint32_t ; |
431 | int ; |
432 | uint32_t ; |
433 | int ; |
434 | |
435 | /* Followed by blocks of data, each sized according to |
436 | * the (rather obvious) block length stated above. |
437 | * |
438 | * bnx_COM_FwText, bnx_COM_FwData, bnx_COM_FwRodata, |
439 | * bnx_COM_FwBss, bnx_COM_FwSbss, |
440 | * |
441 | * bnx_RXP_FwText, bnx_RXP_FwData, bnx_RXP_FwRodata, |
442 | * bnx_RXP_FwBss, bnx_RXP_FwSbss, |
443 | * |
444 | * bnx_TPAT_FwText, bnx_TPAT_FwData, bnx_TPAT_FwRodata, |
445 | * bnx_TPAT_FwBss, bnx_TPAT_FwSbss, |
446 | * |
447 | * bnx_TXP_FwText, bnx_TXP_FwData, bnx_TXP_FwRodata, |
448 | * bnx_TXP_FwBss, bnx_TXP_FwSbss, |
449 | */ |
450 | }; |
451 | |
452 | #endif /* _DEV_PCI_IF_BNXVAR_H_ */ |
453 | |