1 | /* $NetBSD: cs4280reg.h,v 1.7 2006/04/15 21:20:47 jmcneill Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
9 | * 1. Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * 2. Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
14 | * 3. All advertising materials mentioning features or use of this software |
15 | * must display the following acknowledgement: |
16 | * This product includes software developed by Tatoku Ogaito |
17 | * for the NetBSD Project. |
18 | * 4. The name of the author may not be used to endorse or promote products |
19 | * derived from this software without specific prior written permission |
20 | * |
21 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
22 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
23 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
24 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
25 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
26 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
30 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
31 | */ |
32 | |
33 | |
34 | #define CS4280_BA0_SIZE 0x2000 |
35 | #define CS4280_BA1_SIZE 0x40000 |
36 | |
37 | /* BA0 */ |
38 | |
39 | /* Interrupt Reporting Registers */ |
40 | #define CS4280_HISR 0x000 /* Host Interrupt Status Register */ |
41 | #define HISR_INTENA 0x80000000 |
42 | #define HISR_MIDI 0x00100000 |
43 | #define HISR_CINT 0x00000002 |
44 | #define HISR_PINT 0x00000001 |
45 | #define CS4280_HICR 0x008 /* Host Interrupt Control Register */ |
46 | #define HICR_CHGM 0x00000002 |
47 | #define HICR_IEV 0x00000001 |
48 | |
49 | /* Clock Control Registers */ |
50 | #define CS4280_CLKCR1 0x400 /* Clock Control Register 1 */ |
51 | #define CLKCR1_PLLSS_SPBC 0x00000000 |
52 | #define CLKCR1_PLLSS_RSV 0x00000004 |
53 | #define CLKCR1_PLLSS_PCI 0x00000008 |
54 | #define CLKCR1_PLLSS_RSV2 0x0000000c |
55 | #define CLKCR1_PLLP 0x00000010 |
56 | #define CLKCR1_SWCE 0x00000020 |
57 | |
58 | #define CS4280_CLKCR2 0x404 /* Clock Control Register 2 */ |
59 | #define CLKCR2_PDIVS_RSV 0x00000002 |
60 | #define CLKCR2_PDIVS_8 0x00000008 |
61 | #define CLKCR2_PDIVS_16 0x00000000 |
62 | |
63 | #define CS4280_PLLM 0x408 /* PLL Multiplier Register */ |
64 | #define PLLM_STATE 0x0000003a |
65 | |
66 | #define CS4280_PLLCC 0x40c /* PLL Capacitor Coefficient Register */ |
67 | #define PLLCC_CDR_STATE 0x00000006 |
68 | #define PLLCC_LPF_STATE 0x00000078 |
69 | |
70 | /* General Configuration Registers */ |
71 | #define CS4280_SERMC1 0x420 /* Serial Port Master Control Register 1 */ |
72 | #define SERMC1_MSPE 0x00000001 |
73 | #define SERMC1_PTC_MASK 0x0000000e |
74 | #define SERMC1_PTC_CS423X 0x00000000 |
75 | #define SERMC1_PTC_AC97 0x00000002 |
76 | #define SERMC1_PLB_EN 0x00000010 |
77 | #define SERMC1_XLB_EN 0x00000020 |
78 | #define CS4280_SERC1 0x428 /* Serial Port Configuration Register 1 */ |
79 | #define SERC1_SO1EN 0x00000001 |
80 | #define SERC1_SO1F_MASK 0x0000000e |
81 | #define SERC1_SO1F_CS423X 0x00000000 |
82 | #define SERC1_SO1F_AC97 0x00000002 |
83 | #define SERC1_SO1F_DAC 0x00000004 |
84 | #define SERC1_SO1F_SPDIF 0x00000006 |
85 | #define CS4280_SERC2 0x42c /* Serial Port Configuration Register 2 */ |
86 | #define SERC2_SI1EN 0x00000001 |
87 | #define SERC2_SI1F_MASK 0x0000000e |
88 | #define SERC2_SI1F_CS423X 0x00000000 |
89 | #define SERC2_SI1F_AC97 0x00000002 |
90 | #define SERC2_SI1F_ADC 0x00000004 |
91 | #define SERC2_SI1F_SPDIF 0x00000006 |
92 | |
93 | #define CS4280_SERBSP 0x43c |
94 | #define SERBSP_FSP_MASK 0x0000000f |
95 | |
96 | #define CS4280_SERBST 0x440 |
97 | #define SERBST_RRDY 0x00000001 |
98 | #define SERBST_WBSY 0x00000002 |
99 | #define CS4280_SERBCM 0x444 |
100 | #define SERBCM_RDC 0x000000001 |
101 | #define SERBCM_WRC 0x000000002 |
102 | #define CS4280_SERBAD 0x448 |
103 | #define CS4280_SERBCF 0x44C |
104 | #define SERBCF_HBP 0x00000001 |
105 | #define CS4280_SERBWP 0x450 |
106 | |
107 | /* |
108 | * AC97 Registers are moved to cs428xreg.h since |
109 | * they are common for CS4280 and CS4281 |
110 | */ |
111 | |
112 | /* Host Access Methods */ |
113 | #define CS4280_GPIOR 0x4b8 /* General Purpose I/O Register */ |
114 | #define CS4280_EGPIODR 0x4bc /* Extended GPIO Direction Register */ |
115 | #define CS4280_EGPIOPTR 0x4c0 /* Extended GPIO Polarity/Type Register */ |
116 | #define CS4280_EGPIOTR 0x4c4 /* Extended GPIO Sticky Register */ |
117 | #define CS4280_EGPIOWR 0x4c8 /* Extended GPIO Wakeup Register */ |
118 | #define CS4280_EGPIOSR 0x4cc /* Extended GPIO Status Register */ |
119 | |
120 | /* Control Register */ |
121 | #define CS4280_CFGI 0x4b0 /* Configuration Interface Register */ |
122 | |
123 | #define CS4280_SERACC 0x4d8 |
124 | #define SERACC_CTYPE_MASK 0x00000001 |
125 | #define SERACC_CTYPE_1_03 0x00000000 |
126 | #define SERACC_CTYPE_2_0 0x00000001 |
127 | #define SERACC_TWO_CODECS 0x00000002 |
128 | #define SERACC_MDM 0x00000004 |
129 | #define SERACC_HSP 0x00000008 |
130 | |
131 | /* Midi Port */ |
132 | #define CS4280_MIDCR 0x490 /* MIDI Control Register */ |
133 | #define MIDCR_TXE 0x00000001 /* MIDI Transmit Enable */ |
134 | #define MIDCR_RXE 0x00000002 /* MIDI Receive Enable */ |
135 | #define MIDCR_RIE 0x00000004 /* MIDI Receive Interrupt Enable */ |
136 | #define MIDCR_TIE 0x00000008 /* MIDI Transmit Interrupt Enable */ |
137 | #define MIDCR_MLB 0x00000010 /* MIDI Loop Back Enable */ |
138 | #define MIDCR_MRST 0x00000020 /* MIDI Reset */ |
139 | #define MIDCR_MASK 0x0000003f |
140 | #define CS4280_MIDSR 0x494 /* Host MIDI Status Register */ |
141 | #define MIDSR_TBF 0x00000001 /* Transmit Buffer Full */ |
142 | #define MIDSR_RBE 0x00000002 /* Receive Buffer Empty */ |
143 | #define CS4280_MIDWP 0x498 /* MIDI Write Port */ |
144 | #define MIDWP_MASK 0x000000ff |
145 | #define CS4280_MIDRP 0x49c /* MIDI Read Port */ |
146 | #define MIDRP_MASK 0x000000ff |
147 | |
148 | /* Joy Stick Port */ |
149 | #define CS4280_JSPT 0x480 /* Joystick Poll/Trigger Register */ |
150 | #define CS4280_JSCTL 0x484 /* Joystick Control Register */ |
151 | #define CS4280_JSC1 0x488 /* Joystick Coordinate Register 1 */ |
152 | #define CS4280_JSC2 0x48c /* Joystick Coordinate Register 2 */ |
153 | |
154 | |
155 | /* BA1 */ |
156 | |
157 | /* Playback Parameters */ |
158 | #define CS4280_PDTC 0x00c0 /* Playback DMA Transaction Count */ |
159 | #define PDTC_MASK 0x000003ff |
160 | #define CS4280_MK_PDTC(x) ((x)/2 - 1) |
161 | #define CS4280_PFIE 0x00c4 /* Playback Format and Interrupt Enable */ |
162 | #define PFIE_UNSIGNED 0x00008000 /* Playback Format is unsigned */ |
163 | #define PFIE_SWAPPED 0x00004000 /* Playback Format is need swapped */ |
164 | #define PFIE_MONO 0x00002000 /* Playback Format is monoral */ |
165 | #define PFIE_8BIT 0x00001000 /* Playback Format is 8bit */ |
166 | #define PFIE_PI_ENABLE 0x00000000 /* Playback Interrupt Enabled */ |
167 | #define PFIE_PI_DISABLE 0x00000010 /* Playback Interrupt Disabled */ |
168 | #define PFIE_PI_MASK 0x0000003f |
169 | #define PFIE_MASK 0x0000f03f |
170 | #define CS4280_PBA 0x00c8 /* Playback Buffer Address */ |
171 | #define CS4280_PVOL 0x00f8 /* Playback Volume */ |
172 | #define CS4280_PSRC 0x0288 /* Playback Sample Rate Correction */ |
173 | #define PSRC_MASK 0xffff0000 |
174 | #define CS4280_MK_PSRC(psrc, py) ((((psrc) << 16) & 0xffff0000) | ((py) & 0xffff)) |
175 | #define CS4280_PCTL 0x02a4 /* Playback Control */ |
176 | #define PCTL_MASK 0xffff0000 |
177 | #define CS4280_PPI 0x02b4 /* Playback Phase Increment */ |
178 | |
179 | /* Capture Parameters */ |
180 | #define CS4280_CCTL 0x0064 /* Capture Control */ |
181 | #define CCTL_MASK 0x0000ffff |
182 | #define CS4280_CDTC 0x0100 /* Capture DMA Transaction Count */ |
183 | #define CS4280_CIE 0x0104 /* Capture Interrupt Enable */ |
184 | #define CIE_CI_ENABLE 0x00000001 /* Capture Interrupt enabled */ |
185 | #define CIE_CI_DISABLE 0x00000011 /* Capture Interrupt disabled */ |
186 | #define CIE_CI_MASK 0x0000003f |
187 | #define CS4280_CBA 0x010c /* Capture Buffer Address */ |
188 | #define CS4280_CSRC 0x02c8 /* Capture Sample Rate Correction */ |
189 | #define CSRC_MASK 0xffff0000 |
190 | #define CS4280_MK_CSRC(csrc, cy) ((((csrc) << 16) & 0xffff0000) | ((cy) & 0xffff)) |
191 | #define CS4280_CCI 0x02d8 /* Capture Coefficient Increment */ |
192 | #define CCI_MASK 0xffff0000 |
193 | #define CS4280_CD 0x02e0 /* Capture Delay */ |
194 | #define CD_MASK 0xfffc000 |
195 | #define CS4280_CPI 0x02f4 /* Capture Phase Incremnt */ |
196 | #define CS4280_CGL 0x0134 /* Capture Group Length */ |
197 | #define CGL_MASK 0x0000ffff |
198 | #define CS4280_CNT 0x0340 /* Capture Number of Triplets */ |
199 | #define CS4280_CGC 0x0138 /* Capture Group Count */ |
200 | #define CGC_MASK 0x0000ffff |
201 | #define CS4280_CVOL 0x02f8 /* Capture Volume */ |
202 | |
203 | /* Processor Registers */ |
204 | #define CS4280_SPCR 0x30000 /* Processor Control Register */ |
205 | #define SPCR_RUN 0x00000001 |
206 | #define SPCR_STPFR 0x00000002 |
207 | #define SPCR_RUNFR 0x00000004 |
208 | #define SPCR_DRQEN 0x00000020 |
209 | #define SPCR_RSTSP 0x00000040 |
210 | #define CS4280_DREG 0x30004 |
211 | #define CS4280_DSRWP 0x30008 |
212 | #define CS4280_TWPR 0x3000c /* Trap Write Port Register */ |
213 | #define CS4280_SPWR 0x30010 |
214 | #define CS4280_SPCS 0x30028 /* Processor Clock Status Register */ |
215 | #define SPCS_SPRUN 0x00000100 |
216 | #define CS4280_FRMT 0x30030 /* Frame Timer Register */ |
217 | #define FRMT_FTV 0x00000adf |
218 | |
219 | |
220 | #define CF_MONO 0x01 |
221 | #define CF_8BIT 0x02 |
222 | |
223 | #define CF_16BIT_STEREO 0x00 |
224 | #define CF_16BIT_MONO 0x01 |
225 | #define CF_8BIT_STEREO 0x02 |
226 | #define CF_8BIT_MONO 0x03 |
227 | |
228 | #define MIDI_BUSY_WAIT 100 |
229 | #define MIDI_BUSY_DELAY 100 /* Delay when UART is busy */ |
230 | |
231 | /* 3*1024 parameter, 3.5*1024 sample, 2*3.5*1024 code */ |
232 | #define BA1_DWORD_SIZE (13 * 1024 + 512) |
233 | #define BA1_MEMORY_COUNT 3 |
234 | |
235 | struct BA1struct { |
236 | struct { |
237 | uint32_t offset; |
238 | uint32_t size; |
239 | } memory[BA1_MEMORY_COUNT]; |
240 | uint32_t map[BA1_DWORD_SIZE]; |
241 | }; |
242 | |
243 | #define CS4280_ICHUNK 2048 /* Bytes between interrupts */ |
244 | #define CS4280_DCHUNK 4096 /* Bytes of DMA memory */ |
245 | #define CS4280_DALIGN 4096 /* Alignment of DMA memory */ |
246 | |
247 | /* for AC97_REG_POWER */ |
248 | #define CS4280_POWER_DOWN_ALL 0x7f0f |
249 | |