1 | /* $NetBSD: aic79xx.c,v 1.50 2014/10/18 08:33:27 snj Exp $ */ |
2 | |
3 | /* |
4 | * Core routines and tables shareable across OS platforms. |
5 | * |
6 | * Copyright (c) 1994-2002 Justin T. Gibbs. |
7 | * Copyright (c) 2000-2003 Adaptec Inc. |
8 | * All rights reserved. |
9 | * |
10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions |
12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions, and the following disclaimer, |
15 | * without modification. |
16 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer |
17 | * substantially similar to the "NO WARRANTY" disclaimer below |
18 | * ("Disclaimer") and any redistribution must be conditioned upon |
19 | * including a substantially similar Disclaimer requirement for further |
20 | * binary redistribution. |
21 | * 3. Neither the names of the above-listed copyright holders nor the names |
22 | * of any contributors may be used to endorse or promote products derived |
23 | * from this software without specific prior written permission. |
24 | * |
25 | * Alternatively, this software may be distributed under the terms of the |
26 | * GNU General Public License ("GPL") version 2 as published by the Free |
27 | * Software Foundation. |
28 | * |
29 | * NO WARRANTY |
30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
31 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
32 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR |
33 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
34 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
35 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
36 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
37 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
38 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
39 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
40 | * POSSIBILITY OF SUCH DAMAGES. |
41 | * |
42 | * Id: //depot/aic7xxx/aic7xxx/aic79xx.c#202 $ |
43 | * |
44 | * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.c,v 1.24 2003/06/28 04:46:54 gibbs Exp $ |
45 | */ |
46 | /* |
47 | * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. |
48 | * - April 2003 |
49 | */ |
50 | |
51 | #include <sys/cdefs.h> |
52 | __KERNEL_RCSID(0, "$NetBSD: aic79xx.c,v 1.50 2014/10/18 08:33:27 snj Exp $" ); |
53 | |
54 | #include <dev/ic/aic79xx_osm.h> |
55 | #include <dev/ic/aic79xx_inline.h> |
56 | #include <dev/ic/aic7xxx_cam.h> |
57 | |
58 | #include <dev/microcode/aic7xxx/aicasm.h> |
59 | #include <dev/microcode/aic7xxx/aicasm_insformat.h> |
60 | |
61 | |
62 | /******************************** Globals *************************************/ |
63 | struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq); |
64 | |
65 | /***************************** Lookup Tables **********************************/ |
66 | const char *ahd_chip_names[] = |
67 | { |
68 | "NONE" , |
69 | "aic7901" , |
70 | "aic7902" , |
71 | "aic7901A" |
72 | }; |
73 | |
74 | /* |
75 | * Hardware error codes. |
76 | */ |
77 | struct ahd_hard_error_entry { |
78 | uint8_t errno; |
79 | const char *errmesg; |
80 | }; |
81 | |
82 | static struct ahd_hard_error_entry ahd_hard_errors[] = { |
83 | { DSCTMOUT, "Discard Timer has timed out" }, |
84 | { ILLOPCODE, "Illegal Opcode in sequencer program" }, |
85 | { SQPARERR, "Sequencer Parity Error" }, |
86 | { DPARERR, "Data-path Parity Error" }, |
87 | { MPARERR, "Scratch or SCB Memory Parity Error" }, |
88 | { CIOPARERR, "CIOBUS Parity Error" }, |
89 | }; |
90 | static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors); |
91 | |
92 | static struct ahd_phase_table_entry ahd_phase_table[] = |
93 | { |
94 | { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, |
95 | { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, |
96 | { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, |
97 | { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, |
98 | { P_COMMAND, MSG_NOOP, "in Command phase" }, |
99 | { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, |
100 | { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, |
101 | { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, |
102 | { P_BUSFREE, MSG_NOOP, "while idle" }, |
103 | { 0, MSG_NOOP, "in unknown phase" } |
104 | }; |
105 | |
106 | /* |
107 | * In most cases we only wish to itterate over real phases, so |
108 | * exclude the last element from the count. |
109 | */ |
110 | static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1; |
111 | |
112 | /* Our Sequencer Program */ |
113 | #include <dev/microcode/aic7xxx/aic79xx_seq.h> |
114 | |
115 | /**************************** Function Declarations ***************************/ |
116 | static void ahd_handle_transmission_error(struct ahd_softc *ahd); |
117 | static void ahd_handle_lqiphase_error(struct ahd_softc *ahd, |
118 | u_int lqistat1); |
119 | static int ahd_handle_pkt_busfree(struct ahd_softc *ahd, |
120 | u_int busfreetime); |
121 | static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd); |
122 | static void ahd_handle_proto_violation(struct ahd_softc *ahd); |
123 | static void ahd_force_renegotiation(struct ahd_softc *ahd, |
124 | struct ahd_devinfo *devinfo); |
125 | |
126 | static struct ahd_tmode_tstate* |
127 | ahd_alloc_tstate(struct ahd_softc *ahd, |
128 | u_int scsi_id, char channel); |
129 | #ifdef AHD_TARGET_MODE |
130 | static void ahd_free_tstate(struct ahd_softc *ahd, |
131 | u_int scsi_id, char channel, int force); |
132 | #endif |
133 | static void ahd_devlimited_syncrate(struct ahd_softc *ahd, |
134 | struct ahd_initiator_tinfo *, |
135 | u_int *period, |
136 | u_int *ppr_options, |
137 | role_t role); |
138 | static void ahd_update_neg_table(struct ahd_softc *ahd, |
139 | struct ahd_devinfo *devinfo, |
140 | struct ahd_transinfo *tinfo); |
141 | static void ahd_update_pending_scbs(struct ahd_softc *ahd); |
142 | static void ahd_fetch_devinfo(struct ahd_softc *ahd, |
143 | struct ahd_devinfo *devinfo); |
144 | static void ahd_scb_devinfo(struct ahd_softc *ahd, |
145 | struct ahd_devinfo *devinfo, |
146 | struct scb *scb); |
147 | static void ahd_setup_initiator_msgout(struct ahd_softc *ahd, |
148 | struct ahd_devinfo *devinfo, |
149 | struct scb *scb); |
150 | static void ahd_build_transfer_msg(struct ahd_softc *ahd, |
151 | struct ahd_devinfo *devinfo); |
152 | static void ahd_construct_sdtr(struct ahd_softc *ahd, |
153 | struct ahd_devinfo *devinfo, |
154 | u_int period, u_int offset); |
155 | static void ahd_construct_wdtr(struct ahd_softc *ahd, |
156 | struct ahd_devinfo *devinfo, |
157 | u_int bus_width); |
158 | static void ahd_construct_ppr(struct ahd_softc *ahd, |
159 | struct ahd_devinfo *devinfo, |
160 | u_int period, u_int offset, |
161 | u_int bus_width, u_int ppr_options); |
162 | static void ahd_clear_msg_state(struct ahd_softc *ahd); |
163 | static void ahd_handle_message_phase(struct ahd_softc *ahd); |
164 | typedef enum { |
165 | AHDMSG_1B, |
166 | AHDMSG_2B, |
167 | AHDMSG_EXT |
168 | } ahd_msgtype; |
169 | static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, |
170 | u_int msgval, int full); |
171 | static int ahd_parse_msg(struct ahd_softc *ahd, |
172 | struct ahd_devinfo *devinfo); |
173 | static int ahd_handle_msg_reject(struct ahd_softc *ahd, |
174 | struct ahd_devinfo *devinfo); |
175 | static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd, |
176 | struct ahd_devinfo *devinfo); |
177 | static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd); |
178 | static void ahd_handle_devreset(struct ahd_softc *ahd, |
179 | struct ahd_devinfo *devinfo, |
180 | u_int lun, cam_status status, |
181 | const char *message, |
182 | int verbose_level); |
183 | #if AHD_TARGET_MODE |
184 | static void ahd_setup_target_msgin(struct ahd_softc *ahd, |
185 | struct ahd_devinfo *devinfo, |
186 | struct scb *scb); |
187 | #endif |
188 | |
189 | static u_int ahd_sglist_size(struct ahd_softc *ahd); |
190 | static u_int ahd_sglist_allocsize(struct ahd_softc *ahd); |
191 | static void ahd_initialize_hscbs(struct ahd_softc *ahd); |
192 | static int ahd_init_scbdata(struct ahd_softc *ahd); |
193 | static void ahd_fini_scbdata(struct ahd_softc *ahd); |
194 | static void ahd_setup_iocell_workaround(struct ahd_softc *ahd); |
195 | static void ahd_iocell_first_selection(struct ahd_softc *ahd); |
196 | static void ahd_add_col_list(struct ahd_softc *ahd, |
197 | struct scb *scb, u_int col_idx); |
198 | static void ahd_rem_col_list(struct ahd_softc *ahd, |
199 | struct scb *scb); |
200 | static void ahd_chip_init(struct ahd_softc *ahd); |
201 | static void ahd_qinfifo_requeue(struct ahd_softc *ahd, |
202 | struct scb *prev_scb, |
203 | struct scb *scb); |
204 | static int ahd_qinfifo_count(struct ahd_softc *ahd); |
205 | static int ahd_search_scb_list(struct ahd_softc *ahd, int target, |
206 | char channel, int lun, u_int tag, |
207 | role_t role, uint32_t status, |
208 | ahd_search_action action, |
209 | u_int *list_head, u_int tid); |
210 | static void ahd_stitch_tid_list(struct ahd_softc *ahd, |
211 | u_int tid_prev, u_int tid_cur, |
212 | u_int tid_next); |
213 | static void ahd_add_scb_to_free_list(struct ahd_softc *ahd, |
214 | u_int scbid); |
215 | static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, |
216 | u_int prev, u_int next, u_int tid); |
217 | static void ahd_reset_current_bus(struct ahd_softc *ahd); |
218 | static ahd_callback_t ahd_reset_poll; |
219 | static ahd_callback_t ahd_stat_timer; |
220 | #ifdef AHD_DUMP_SEQ |
221 | static void ahd_dumpseq(struct ahd_softc *ahd); |
222 | #endif |
223 | static void ahd_loadseq(struct ahd_softc *ahd); |
224 | static int ahd_check_patch(struct ahd_softc *ahd, |
225 | struct patch **start_patch, |
226 | u_int start_instr, u_int *skip_addr); |
227 | static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd, |
228 | u_int address); |
229 | static void ahd_download_instr(struct ahd_softc *ahd, |
230 | u_int instrptr, uint8_t *dconsts); |
231 | static int ahd_probe_stack_size(struct ahd_softc *ahd); |
232 | static int ahd_scb_active_in_fifo(struct ahd_softc *ahd, |
233 | struct scb *scb); |
234 | static void ahd_run_data_fifo(struct ahd_softc *ahd, |
235 | struct scb *scb); |
236 | |
237 | #ifdef AHD_TARGET_MODE |
238 | static void ahd_queue_lstate_event(struct ahd_softc *ahd, |
239 | struct ahd_tmode_lstate *lstate, |
240 | u_int initiator_id, |
241 | u_int event_type, |
242 | u_int event_arg); |
243 | static void ahd_update_scsiid(struct ahd_softc *ahd, |
244 | u_int targid_mask); |
245 | static int ahd_handle_target_cmd(struct ahd_softc *ahd, |
246 | struct target_cmd *cmd); |
247 | #endif |
248 | |
249 | /************************** Added for porting to NetBSD ***********************/ |
250 | static int ahd_createdmamem(bus_dma_tag_t tag, |
251 | int size, |
252 | int flags, |
253 | bus_dmamap_t *mapp, |
254 | void **vaddr, |
255 | bus_addr_t *baddr, |
256 | bus_dma_segment_t *seg, |
257 | int *nseg, |
258 | const char *myname, const char *what); |
259 | |
260 | static void ahd_freedmamem(bus_dma_tag_t tag, |
261 | int size, |
262 | bus_dmamap_t map, |
263 | void *vaddr, |
264 | bus_dma_segment_t *seg, |
265 | int nseg); |
266 | |
267 | /******************************** Private Inlines *****************************/ |
268 | static inline void ahd_assert_atn(struct ahd_softc *ahd); |
269 | static inline int ahd_currently_packetized(struct ahd_softc *ahd); |
270 | static inline int ahd_set_active_fifo(struct ahd_softc *ahd); |
271 | |
272 | static inline void |
273 | ahd_assert_atn(struct ahd_softc *ahd) |
274 | { |
275 | ahd_outb(ahd, SCSISIGO, ATNO); |
276 | } |
277 | |
278 | /* |
279 | * Determine if the current connection has a packetized |
280 | * agreement. This does not necessarily mean that we |
281 | * are currently in a packetized transfer. We could |
282 | * just as easily be sending or receiving a message. |
283 | */ |
284 | static inline int |
285 | ahd_currently_packetized(struct ahd_softc *ahd) |
286 | { |
287 | ahd_mode_state saved_modes; |
288 | int packetized; |
289 | |
290 | saved_modes = ahd_save_modes(ahd); |
291 | if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) { |
292 | /* |
293 | * The packetized bit refers to the last |
294 | * connection, not the current one. Check |
295 | * for non-zero LQISTATE instead. |
296 | */ |
297 | ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); |
298 | packetized = ahd_inb(ahd, LQISTATE) != 0; |
299 | } else { |
300 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
301 | packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED; |
302 | } |
303 | ahd_restore_modes(ahd, saved_modes); |
304 | return (packetized); |
305 | } |
306 | |
307 | static inline int |
308 | ahd_set_active_fifo(struct ahd_softc *ahd) |
309 | { |
310 | u_int active_fifo; |
311 | |
312 | AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); |
313 | active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; |
314 | switch (active_fifo) { |
315 | case 0: |
316 | case 1: |
317 | ahd_set_modes(ahd, active_fifo, active_fifo); |
318 | return (1); |
319 | default: |
320 | return (0); |
321 | } |
322 | } |
323 | |
324 | /************************* Sequencer Execution Control ************************/ |
325 | /* |
326 | * Restart the sequencer program from address zero |
327 | */ |
328 | void |
329 | ahd_restart(struct ahd_softc *ahd) |
330 | { |
331 | |
332 | ahd_pause(ahd); |
333 | |
334 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
335 | |
336 | /* No more pending messages */ |
337 | ahd_clear_msg_state(ahd); |
338 | ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */ |
339 | ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */ |
340 | ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET); |
341 | ahd_outb(ahd, SEQINTCTL, 0); |
342 | ahd_outb(ahd, LASTPHASE, P_BUSFREE); |
343 | ahd_outb(ahd, SEQ_FLAGS, 0); |
344 | ahd_outb(ahd, SAVED_SCSIID, 0xFF); |
345 | ahd_outb(ahd, SAVED_LUN, 0xFF); |
346 | |
347 | /* |
348 | * Ensure that the sequencer's idea of TQINPOS |
349 | * matches our own. The sequencer increments TQINPOS |
350 | * only after it sees a DMA complete and a reset could |
351 | * occur before the increment leaving the kernel to believe |
352 | * the command arrived but the sequencer to not. |
353 | */ |
354 | ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); |
355 | |
356 | /* Always allow reselection */ |
357 | ahd_outb(ahd, SCSISEQ1, |
358 | ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); |
359 | ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); |
360 | ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); |
361 | ahd_unpause(ahd); |
362 | } |
363 | |
364 | void |
365 | ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo) |
366 | { |
367 | ahd_mode_state saved_modes; |
368 | |
369 | #ifdef AHD_DEBUG |
370 | if ((ahd_debug & AHD_SHOW_FIFOS) != 0) |
371 | printf("%s: Clearing FIFO %d\n" , ahd_name(ahd), fifo); |
372 | #endif |
373 | saved_modes = ahd_save_modes(ahd); |
374 | ahd_set_modes(ahd, fifo, fifo); |
375 | ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); |
376 | if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) |
377 | ahd_outb(ahd, CCSGCTL, CCSGRESET); |
378 | ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); |
379 | ahd_outb(ahd, SG_STATE, 0); |
380 | ahd_restore_modes(ahd, saved_modes); |
381 | } |
382 | |
383 | /************************* Input/Output Queues ********************************/ |
384 | /* |
385 | * Flush and completed commands that are sitting in the command |
386 | * complete queues down on the chip but have yet to be DMA'ed back up. |
387 | */ |
388 | void |
389 | ahd_flush_qoutfifo(struct ahd_softc *ahd) |
390 | { |
391 | struct scb *scb; |
392 | ahd_mode_state saved_modes; |
393 | u_int saved_scbptr; |
394 | u_int ccscbctl; |
395 | u_int scbid; |
396 | u_int next_scbid; |
397 | |
398 | saved_modes = ahd_save_modes(ahd); |
399 | |
400 | /* |
401 | * Complete any SCBs that just finished being |
402 | * DMA'ed into the qoutfifo. |
403 | */ |
404 | ahd_run_qoutfifo(ahd); |
405 | |
406 | /* |
407 | * Flush the good status FIFO for compelted packetized commands. |
408 | */ |
409 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
410 | saved_scbptr = ahd_get_scbptr(ahd); |
411 | while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) { |
412 | u_int fifo_mode; |
413 | u_int i; |
414 | |
415 | scbid = (ahd_inb(ahd, GSFIFO+1) << 8) |
416 | | ahd_inb(ahd, GSFIFO); |
417 | scb = ahd_lookup_scb(ahd, scbid); |
418 | if (scb == NULL) { |
419 | printf("%s: Warning - GSFIFO SCB %d invalid\n" , |
420 | ahd_name(ahd), scbid); |
421 | continue; |
422 | } |
423 | /* |
424 | * Determine if this transaction is still active in |
425 | * any FIFO. If it is, we must flush that FIFO to |
426 | * the host before completing the command. |
427 | */ |
428 | fifo_mode = 0; |
429 | for (i = 0; i < 2; i++) { |
430 | /* Toggle to the other mode. */ |
431 | fifo_mode ^= 1; |
432 | ahd_set_modes(ahd, fifo_mode, fifo_mode); |
433 | if (ahd_scb_active_in_fifo(ahd, scb) == 0) |
434 | continue; |
435 | |
436 | ahd_run_data_fifo(ahd, scb); |
437 | |
438 | /* |
439 | * Clearing this transaction in this FIFO may |
440 | * cause a CFG4DATA for this same transaction |
441 | * to assert in the other FIFO. Make sure we |
442 | * loop one more time and check the other FIFO. |
443 | */ |
444 | i = 0; |
445 | } |
446 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
447 | ahd_set_scbptr(ahd, scbid); |
448 | if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0 |
449 | && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0 |
450 | || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR) |
451 | & SG_LIST_NULL) != 0)) { |
452 | u_int comp_head; |
453 | |
454 | /* |
455 | * The transfer completed with a residual. |
456 | * Place this SCB on the complete DMA list |
457 | * so that we Update our in-core copy of the |
458 | * SCB before completing the command. |
459 | */ |
460 | ahd_outb(ahd, SCB_SCSI_STATUS, 0); |
461 | ahd_outb(ahd, SCB_SGPTR, |
462 | ahd_inb_scbram(ahd, SCB_SGPTR) |
463 | | SG_STATUS_VALID); |
464 | ahd_outw(ahd, SCB_TAG, SCB_GET_TAG(scb)); |
465 | comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); |
466 | ahd_outw(ahd, SCB_NEXT_COMPLETE, comp_head); |
467 | if (SCBID_IS_NULL(comp_head)) |
468 | ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, |
469 | SCB_GET_TAG(scb)); |
470 | } else |
471 | ahd_complete_scb(ahd, scb); |
472 | } |
473 | ahd_set_scbptr(ahd, saved_scbptr); |
474 | |
475 | /* |
476 | * Setup for command channel portion of flush. |
477 | */ |
478 | ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); |
479 | |
480 | /* |
481 | * Wait for any inprogress DMA to complete and clear DMA state |
482 | * if this if for an SCB in the qinfifo. |
483 | */ |
484 | while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) { |
485 | |
486 | if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) { |
487 | if ((ccscbctl & ARRDONE) != 0) |
488 | break; |
489 | } else if ((ccscbctl & CCSCBDONE) != 0) |
490 | break; |
491 | ahd_delay(200); |
492 | } |
493 | if ((ccscbctl & CCSCBDIR) != 0) |
494 | ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN)); |
495 | |
496 | saved_scbptr = ahd_get_scbptr(ahd); |
497 | /* |
498 | * Manually update/complete any completed SCBs that are waiting to be |
499 | * DMA'ed back up to the host. |
500 | */ |
501 | scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); |
502 | while (!SCBID_IS_NULL(scbid)) { |
503 | uint8_t *hscb_ptr; |
504 | u_int i; |
505 | |
506 | ahd_set_scbptr(ahd, scbid); |
507 | next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); |
508 | scb = ahd_lookup_scb(ahd, scbid); |
509 | if (scb == NULL) { |
510 | printf("%s: Warning - DMA-up and complete " |
511 | "SCB %d invalid\n" , ahd_name(ahd), scbid); |
512 | continue; |
513 | } |
514 | hscb_ptr = (uint8_t *)scb->hscb; |
515 | for (i = 0; i < sizeof(struct hardware_scb); i++) |
516 | *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i); |
517 | |
518 | ahd_complete_scb(ahd, scb); |
519 | scbid = next_scbid; |
520 | } |
521 | ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); |
522 | |
523 | scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD); |
524 | while (!SCBID_IS_NULL(scbid)) { |
525 | |
526 | ahd_set_scbptr(ahd, scbid); |
527 | next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); |
528 | scb = ahd_lookup_scb(ahd, scbid); |
529 | if (scb == NULL) { |
530 | printf("%s: Warning - Complete SCB %d invalid\n" , |
531 | ahd_name(ahd), scbid); |
532 | continue; |
533 | } |
534 | |
535 | ahd_complete_scb(ahd, scb); |
536 | scbid = next_scbid; |
537 | } |
538 | ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); |
539 | |
540 | /* |
541 | * Restore state. |
542 | */ |
543 | ahd_set_scbptr(ahd, saved_scbptr); |
544 | ahd_restore_modes(ahd, saved_modes); |
545 | ahd->flags |= AHD_UPDATE_PEND_CMDS; |
546 | } |
547 | |
548 | /* |
549 | * Determine if an SCB for a packetized transaction |
550 | * is active in a FIFO. |
551 | */ |
552 | static int |
553 | ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb) |
554 | { |
555 | |
556 | /* |
557 | * The FIFO is only active for our transaction if |
558 | * the SCBPTR matches the SCB's ID and the firmware |
559 | * has installed a handler for the FIFO or we have |
560 | * a pending SAVEPTRS or CFG4DATA interrupt. |
561 | */ |
562 | if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb) |
563 | || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0 |
564 | && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0)) |
565 | return (0); |
566 | |
567 | return (1); |
568 | } |
569 | |
570 | /* |
571 | * Run a data fifo to completion for a transaction we know |
572 | * has completed across the SCSI bus (good status has been |
573 | * received). We are already set to the correct FIFO mode |
574 | * on entry to this routine. |
575 | * |
576 | * This function attempts to operate exactly as the firmware |
577 | * would when running this FIFO. Care must be taken to update |
578 | * this routine any time the firmware's FIFO algorithm is |
579 | * changed. |
580 | */ |
581 | static void |
582 | ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb) |
583 | { |
584 | u_int seqintsrc; |
585 | |
586 | while (1) { |
587 | seqintsrc = ahd_inb(ahd, SEQINTSRC); |
588 | if ((seqintsrc & CFG4DATA) != 0) { |
589 | uint32_t datacnt; |
590 | uint32_t sgptr; |
591 | |
592 | /* |
593 | * Clear full residual flag. |
594 | */ |
595 | sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID; |
596 | ahd_outb(ahd, SCB_SGPTR, sgptr); |
597 | |
598 | /* |
599 | * Load datacnt and address. |
600 | */ |
601 | datacnt = ahd_inl_scbram(ahd, SCB_DATACNT); |
602 | if ((datacnt & AHD_DMA_LAST_SEG) != 0) { |
603 | sgptr |= LAST_SEG; |
604 | ahd_outb(ahd, SG_STATE, 0); |
605 | } else |
606 | ahd_outb(ahd, SG_STATE, LOADING_NEEDED); |
607 | ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR)); |
608 | ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK); |
609 | ahd_outb(ahd, SG_CACHE_PRE, sgptr); |
610 | ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); |
611 | |
612 | /* |
613 | * Initialize Residual Fields. |
614 | */ |
615 | ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24); |
616 | ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK); |
617 | |
618 | /* |
619 | * Mark the SCB as having a FIFO in use. |
620 | */ |
621 | ahd_outb(ahd, SCB_FIFO_USE_COUNT, |
622 | ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1); |
623 | |
624 | /* |
625 | * Install a "fake" handler for this FIFO. |
626 | */ |
627 | ahd_outw(ahd, LONGJMP_ADDR, 0); |
628 | |
629 | /* |
630 | * Notify the hardware that we have satisfied |
631 | * this sequencer interrupt. |
632 | */ |
633 | ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA); |
634 | } else if ((seqintsrc & SAVEPTRS) != 0) { |
635 | uint32_t sgptr; |
636 | uint32_t resid; |
637 | |
638 | if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) { |
639 | /* |
640 | * Snapshot Save Pointers. Clear |
641 | * the snapshot and continue. |
642 | */ |
643 | ahd_outb(ahd, DFFSXFRCTL, CLRCHN); |
644 | continue; |
645 | } |
646 | |
647 | /* |
648 | * Disable S/G fetch so the DMA engine |
649 | * is available to future users. |
650 | */ |
651 | if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) |
652 | ahd_outb(ahd, CCSGCTL, 0); |
653 | ahd_outb(ahd, SG_STATE, 0); |
654 | |
655 | /* |
656 | * Flush the data FIFO. Strickly only |
657 | * necessary for Rev A parts. |
658 | */ |
659 | ahd_outb(ahd, DFCNTRL, |
660 | ahd_inb(ahd, DFCNTRL) | FIFOFLUSH); |
661 | |
662 | /* |
663 | * Calculate residual. |
664 | */ |
665 | sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); |
666 | resid = ahd_inl(ahd, SHCNT); |
667 | resid |= |
668 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24; |
669 | ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid); |
670 | if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) { |
671 | /* |
672 | * Must back up to the correct S/G element. |
673 | * Typically this just means resetting our |
674 | * low byte to the offset in the SG_CACHE, |
675 | * but if we wrapped, we have to correct |
676 | * the other bytes of the sgptr too. |
677 | */ |
678 | if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0 |
679 | && (sgptr & 0x80) == 0) |
680 | sgptr -= 0x100; |
681 | sgptr &= ~0xFF; |
682 | sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW) |
683 | & SG_ADDR_MASK; |
684 | ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); |
685 | ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0); |
686 | } else if ((resid & AHD_SG_LEN_MASK) == 0) { |
687 | ahd_outb(ahd, SCB_RESIDUAL_SGPTR, |
688 | sgptr | SG_LIST_NULL); |
689 | } |
690 | /* |
691 | * Save Pointers. |
692 | */ |
693 | ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR)); |
694 | ahd_outl(ahd, SCB_DATACNT, resid); |
695 | ahd_outl(ahd, SCB_SGPTR, sgptr); |
696 | ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS); |
697 | ahd_outb(ahd, SEQIMODE, |
698 | ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS); |
699 | /* |
700 | * If the data is to the SCSI bus, we are |
701 | * done, otherwise wait for FIFOEMP. |
702 | */ |
703 | if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0) |
704 | break; |
705 | } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) { |
706 | uint32_t sgptr; |
707 | uint64_t data_addr; |
708 | uint32_t data_len; |
709 | u_int dfcntrl; |
710 | |
711 | /* |
712 | * Disable S/G fetch so the DMA engine |
713 | * is available to future users. |
714 | */ |
715 | if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) { |
716 | ahd_outb(ahd, CCSGCTL, 0); |
717 | ahd_outb(ahd, SG_STATE, LOADING_NEEDED); |
718 | } |
719 | |
720 | /* |
721 | * Wait for the DMA engine to notice that the |
722 | * host transfer is enabled and that there is |
723 | * space in the S/G FIFO for new segments before |
724 | * loading more segments. |
725 | */ |
726 | if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) == 0) |
727 | continue; |
728 | if ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) == 0) |
729 | continue; |
730 | |
731 | /* |
732 | * Determine the offset of the next S/G |
733 | * element to load. |
734 | */ |
735 | sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); |
736 | sgptr &= SG_PTR_MASK; |
737 | if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { |
738 | struct ahd_dma64_seg *sg; |
739 | |
740 | sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); |
741 | data_addr = sg->addr; |
742 | data_len = sg->len; |
743 | sgptr += sizeof(*sg); |
744 | } else { |
745 | struct ahd_dma_seg *sg; |
746 | |
747 | sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); |
748 | data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK; |
749 | data_addr <<= 8; |
750 | data_addr |= sg->addr; |
751 | data_len = sg->len; |
752 | sgptr += sizeof(*sg); |
753 | } |
754 | |
755 | /* |
756 | * Update residual information. |
757 | */ |
758 | ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24); |
759 | ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); |
760 | |
761 | /* |
762 | * Load the S/G. |
763 | */ |
764 | if (data_len & AHD_DMA_LAST_SEG) { |
765 | sgptr |= LAST_SEG; |
766 | ahd_outb(ahd, SG_STATE, 0); |
767 | } |
768 | ahd_outq(ahd, HADDR, data_addr); |
769 | ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK); |
770 | ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF); |
771 | |
772 | /* |
773 | * Advertise the segment to the hardware. |
774 | */ |
775 | dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN; |
776 | if ((ahd->features & AHD_NEW_DFCNTRL_OPTS)!=0) { |
777 | /* |
778 | * Use SCSIENWRDIS so that SCSIEN |
779 | * is never modified by this |
780 | * operation. |
781 | */ |
782 | dfcntrl |= SCSIENWRDIS; |
783 | } |
784 | ahd_outb(ahd, DFCNTRL, dfcntrl); |
785 | } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) |
786 | & LAST_SEG_DONE) != 0) { |
787 | |
788 | /* |
789 | * Transfer completed to the end of SG list |
790 | * and has flushed to the host. |
791 | */ |
792 | ahd_outb(ahd, SCB_SGPTR, |
793 | ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL); |
794 | break; |
795 | } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) { |
796 | break; |
797 | } |
798 | ahd_delay(200); |
799 | } |
800 | /* |
801 | * Clear any handler for this FIFO, decrement |
802 | * the FIFO use count for the SCB, and release |
803 | * the FIFO. |
804 | */ |
805 | ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); |
806 | ahd_outb(ahd, SCB_FIFO_USE_COUNT, |
807 | ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1); |
808 | ahd_outb(ahd, DFFSXFRCTL, CLRCHN); |
809 | } |
810 | |
811 | void |
812 | ahd_run_qoutfifo(struct ahd_softc *ahd) |
813 | { |
814 | struct scb *scb; |
815 | u_int scb_index; |
816 | |
817 | if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0) |
818 | panic("ahd_run_qoutfifo recursion" ); |
819 | ahd->flags |= AHD_RUNNING_QOUTFIFO; |
820 | ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD); |
821 | while ((ahd->qoutfifo[ahd->qoutfifonext] |
822 | & QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag) { |
823 | |
824 | scb_index = ahd_le16toh(ahd->qoutfifo[ahd->qoutfifonext] |
825 | & ~QOUTFIFO_ENTRY_VALID_LE); |
826 | scb = ahd_lookup_scb(ahd, scb_index); |
827 | if (scb == NULL) { |
828 | printf("%s: WARNING no command for scb %d " |
829 | "(cmdcmplt)\nQOUTPOS = %d\n" , |
830 | ahd_name(ahd), scb_index, |
831 | ahd->qoutfifonext); |
832 | ahd_dump_card_state(ahd); |
833 | } else |
834 | ahd_complete_scb(ahd, scb); |
835 | |
836 | ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1); |
837 | if (ahd->qoutfifonext == 0) |
838 | ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID_LE; |
839 | } |
840 | ahd->flags &= ~AHD_RUNNING_QOUTFIFO; |
841 | } |
842 | |
843 | /************************* Interrupt Handling *********************************/ |
844 | void |
845 | ahd_handle_hwerrint(struct ahd_softc *ahd) |
846 | { |
847 | /* |
848 | * Some catastrophic hardware error has occurred. |
849 | * Print it for the user and disable the controller. |
850 | */ |
851 | int i; |
852 | int error; |
853 | |
854 | error = ahd_inb(ahd, ERROR); |
855 | for (i = 0; i < num_errors; i++) { |
856 | if ((error & ahd_hard_errors[i].errno) != 0) |
857 | printf("%s: hwerrint, %s\n" , |
858 | ahd_name(ahd), ahd_hard_errors[i].errmesg); |
859 | } |
860 | |
861 | ahd_dump_card_state(ahd); |
862 | panic("BRKADRINT" ); |
863 | |
864 | /* Tell everyone that this HBA is no longer available */ |
865 | ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, |
866 | CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, |
867 | CAM_NO_HBA); |
868 | |
869 | /* Tell the system that this controller has gone away. */ |
870 | ahd_free(ahd); |
871 | } |
872 | |
873 | void |
874 | ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat) |
875 | { |
876 | u_int seqintcode; |
877 | |
878 | /* |
879 | * Save the sequencer interrupt code and clear the SEQINT |
880 | * bit. We will unpause the sequencer, if appropriate, |
881 | * after servicing the request. |
882 | */ |
883 | seqintcode = ahd_inb(ahd, SEQINTCODE); |
884 | ahd_outb(ahd, CLRINT, CLRSEQINT); |
885 | if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { |
886 | /* |
887 | * Unpause the sequencer and let it clear |
888 | * SEQINT by writing NO_SEQINT to it. This |
889 | * will cause the sequencer to be paused again, |
890 | * which is the expected state of this routine. |
891 | */ |
892 | ahd_unpause(ahd); |
893 | while (!ahd_is_paused(ahd)) |
894 | ; |
895 | ahd_outb(ahd, CLRINT, CLRSEQINT); |
896 | } |
897 | ahd_update_modes(ahd); |
898 | #ifdef AHD_DEBUG |
899 | if ((ahd_debug & AHD_SHOW_MISC) != 0) |
900 | printf("%s: Handle Seqint Called for code %d\n" , |
901 | ahd_name(ahd), seqintcode); |
902 | #endif |
903 | switch (seqintcode) { |
904 | case BAD_SCB_STATUS: |
905 | { |
906 | struct scb *scb; |
907 | u_int scbid; |
908 | int cmds_pending; |
909 | |
910 | scbid = ahd_get_scbptr(ahd); |
911 | scb = ahd_lookup_scb(ahd, scbid); |
912 | if (scb != NULL) { |
913 | ahd_complete_scb(ahd, scb); |
914 | } else { |
915 | printf("%s: WARNING no command for scb %d " |
916 | "(bad status)\n" , ahd_name(ahd), scbid); |
917 | ahd_dump_card_state(ahd); |
918 | } |
919 | cmds_pending = ahd_inw(ahd, CMDS_PENDING); |
920 | if (cmds_pending > 0) |
921 | ahd_outw(ahd, CMDS_PENDING, cmds_pending - 1); |
922 | break; |
923 | } |
924 | case ENTERING_NONPACK: |
925 | { |
926 | struct scb *scb; |
927 | u_int scbid; |
928 | |
929 | AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), |
930 | ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); |
931 | scbid = ahd_get_scbptr(ahd); |
932 | scb = ahd_lookup_scb(ahd, scbid); |
933 | if (scb == NULL) { |
934 | /* |
935 | * Somehow need to know if this |
936 | * is from a selection or reselection. |
937 | * From that, we can determine target |
938 | * ID so we at least have an I_T nexus. |
939 | */ |
940 | } else { |
941 | ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); |
942 | ahd_outb(ahd, SAVED_LUN, scb->hscb->lun); |
943 | ahd_outb(ahd, SEQ_FLAGS, 0x0); |
944 | } |
945 | if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0 |
946 | && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { |
947 | /* |
948 | * Phase change after read stream with |
949 | * CRC error with P0 asserted on last |
950 | * packet. |
951 | */ |
952 | #ifdef AHD_DEBUG |
953 | if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) |
954 | printf("%s: Assuming LQIPHASE_NLQ with " |
955 | "P0 assertion\n" , ahd_name(ahd)); |
956 | #endif |
957 | } |
958 | #ifdef AHD_DEBUG |
959 | if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) |
960 | printf("%s: Entering NONPACK\n" , ahd_name(ahd)); |
961 | #endif |
962 | break; |
963 | } |
964 | case INVALID_SEQINT: |
965 | printf("%s: Invalid Sequencer interrupt occurred.\n" , |
966 | ahd_name(ahd)); |
967 | ahd_dump_card_state(ahd); |
968 | ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); |
969 | break; |
970 | case STATUS_OVERRUN: |
971 | { |
972 | struct scb *scb; |
973 | u_int scbid; |
974 | |
975 | scbid = ahd_get_scbptr(ahd); |
976 | scb = ahd_lookup_scb(ahd, scbid); |
977 | if (scb != NULL) |
978 | ahd_print_path(ahd, scb); |
979 | else |
980 | printf("%s: " , ahd_name(ahd)); |
981 | printf("SCB %d Packetized Status Overrun" , scbid); |
982 | ahd_dump_card_state(ahd); |
983 | ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); |
984 | break; |
985 | } |
986 | case CFG4ISTAT_INTR: |
987 | { |
988 | struct scb *scb; |
989 | u_int scbid; |
990 | |
991 | scbid = ahd_get_scbptr(ahd); |
992 | scb = ahd_lookup_scb(ahd, scbid); |
993 | if (scb == NULL) { |
994 | ahd_dump_card_state(ahd); |
995 | printf("CFG4ISTAT: Free SCB %d referenced" , scbid); |
996 | panic("For safety" ); |
997 | } |
998 | ahd_outq(ahd, HADDR, scb->sense_busaddr); |
999 | ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE); |
1000 | ahd_outb(ahd, HCNT + 2, 0); |
1001 | ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG); |
1002 | ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); |
1003 | break; |
1004 | } |
1005 | case ILLEGAL_PHASE: |
1006 | { |
1007 | u_int bus_phase; |
1008 | |
1009 | bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; |
1010 | printf("%s: ILLEGAL_PHASE 0x%x\n" , |
1011 | ahd_name(ahd), bus_phase); |
1012 | |
1013 | switch (bus_phase) { |
1014 | case P_DATAOUT: |
1015 | case P_DATAIN: |
1016 | case P_DATAOUT_DT: |
1017 | case P_DATAIN_DT: |
1018 | case P_MESGOUT: |
1019 | case P_STATUS: |
1020 | case P_MESGIN: |
1021 | ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); |
1022 | printf("%s: Issued Bus Reset.\n" , ahd_name(ahd)); |
1023 | break; |
1024 | case P_COMMAND: |
1025 | { |
1026 | struct ahd_devinfo devinfo; |
1027 | struct scb *scb; |
1028 | #ifdef notdef |
1029 | struct ahd_initiator_tinfo *targ_info; |
1030 | struct ahd_tmode_tstate *tstate; |
1031 | #endif |
1032 | u_int scbid; |
1033 | |
1034 | /* |
1035 | * If a target takes us into the command phase |
1036 | * assume that it has been externally reset and |
1037 | * has thus lost our previous packetized negotiation |
1038 | * agreement. Since we have not sent an identify |
1039 | * message and may not have fully qualified the |
1040 | * connection, we change our command to TUR, assert |
1041 | * ATN and ABORT the task when we go to message in |
1042 | * phase. The OSM will see the REQUEUE_REQUEST |
1043 | * status and retry the command. |
1044 | */ |
1045 | scbid = ahd_get_scbptr(ahd); |
1046 | scb = ahd_lookup_scb(ahd, scbid); |
1047 | if (scb == NULL) { |
1048 | printf("Invalid phase with no valid SCB. " |
1049 | "Resetting bus.\n" ); |
1050 | ahd_reset_channel(ahd, 'A', |
1051 | /*Initiate Reset*/TRUE); |
1052 | break; |
1053 | } |
1054 | ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), |
1055 | SCB_GET_TARGET(ahd, scb), |
1056 | SCB_GET_LUN(scb), |
1057 | SCB_GET_CHANNEL(ahd, scb), |
1058 | ROLE_INITIATOR); |
1059 | #ifdef notdef |
1060 | targ_info = ahd_fetch_transinfo(ahd, |
1061 | devinfo.channel, |
1062 | devinfo.our_scsiid, |
1063 | devinfo.target, |
1064 | &tstate); |
1065 | #endif |
1066 | ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, |
1067 | AHD_TRANS_ACTIVE, /*paused*/TRUE); |
1068 | ahd_set_syncrate(ahd, &devinfo, /*period*/0, |
1069 | /*offset*/0, /*ppr_options*/0, |
1070 | AHD_TRANS_ACTIVE, /*paused*/TRUE); |
1071 | ahd_outb(ahd, SCB_CDB_STORE, 0); |
1072 | ahd_outb(ahd, SCB_CDB_STORE+1, 0); |
1073 | ahd_outb(ahd, SCB_CDB_STORE+2, 0); |
1074 | ahd_outb(ahd, SCB_CDB_STORE+3, 0); |
1075 | ahd_outb(ahd, SCB_CDB_STORE+4, 0); |
1076 | ahd_outb(ahd, SCB_CDB_STORE+5, 0); |
1077 | ahd_outb(ahd, SCB_CDB_LEN, 6); |
1078 | scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE); |
1079 | scb->hscb->control |= MK_MESSAGE; |
1080 | ahd_outb(ahd, SCB_CONTROL, scb->hscb->control); |
1081 | ahd_outb(ahd, MSG_OUT, HOST_MSG); |
1082 | ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); |
1083 | /* |
1084 | * The lun is 0, regardless of the SCB's lun |
1085 | * as we have not sent an identify message. |
1086 | */ |
1087 | ahd_outb(ahd, SAVED_LUN, 0); |
1088 | ahd_outb(ahd, SEQ_FLAGS, 0); |
1089 | ahd_assert_atn(ahd); |
1090 | scb->flags &= ~(SCB_PACKETIZED); |
1091 | scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT; |
1092 | ahd_freeze_devq(ahd, scb); |
1093 | ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); |
1094 | ahd_freeze_scb(scb); |
1095 | |
1096 | /* |
1097 | * Allow the sequencer to continue with |
1098 | * non-pack processing. |
1099 | */ |
1100 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
1101 | ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT); |
1102 | if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { |
1103 | ahd_outb(ahd, CLRLQOINT1, 0); |
1104 | } |
1105 | #ifdef AHD_DEBUG |
1106 | if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { |
1107 | ahd_print_path(ahd, scb); |
1108 | printf("Unexpected command phase from " |
1109 | "packetized target\n" ); |
1110 | } |
1111 | #endif |
1112 | break; |
1113 | } |
1114 | } |
1115 | break; |
1116 | } |
1117 | case CFG4OVERRUN: |
1118 | { |
1119 | struct scb *scb; |
1120 | u_int scb_index; |
1121 | |
1122 | #ifdef AHD_DEBUG |
1123 | if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { |
1124 | printf("%s: CFG4OVERRUN mode = %x\n" , ahd_name(ahd), |
1125 | ahd_inb(ahd, MODE_PTR)); |
1126 | } |
1127 | #endif |
1128 | scb_index = ahd_get_scbptr(ahd); |
1129 | scb = ahd_lookup_scb(ahd, scb_index); |
1130 | if (scb == NULL) { |
1131 | /* |
1132 | * Attempt to transfer to an SCB that is |
1133 | * not outstanding. |
1134 | */ |
1135 | ahd_assert_atn(ahd); |
1136 | ahd_outb(ahd, MSG_OUT, HOST_MSG); |
1137 | ahd->msgout_buf[0] = MSG_ABORT_TASK; |
1138 | ahd->msgout_len = 1; |
1139 | ahd->msgout_index = 0; |
1140 | ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; |
1141 | /* |
1142 | * Clear status received flag to prevent any |
1143 | * attempt to complete this bogus SCB. |
1144 | */ |
1145 | ahd_outb(ahd, SCB_CONTROL, |
1146 | ahd_inb_scbram(ahd, SCB_CONTROL) |
1147 | & ~STATUS_RCVD); |
1148 | } |
1149 | break; |
1150 | } |
1151 | case DUMP_CARD_STATE: |
1152 | { |
1153 | ahd_dump_card_state(ahd); |
1154 | break; |
1155 | } |
1156 | case PDATA_REINIT: |
1157 | { |
1158 | #ifdef AHD_DEBUG |
1159 | if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { |
1160 | printf("%s: PDATA_REINIT - DFCNTRL = 0x%x " |
1161 | "SG_CACHE_SHADOW = 0x%x\n" , |
1162 | ahd_name(ahd), ahd_inb(ahd, DFCNTRL), |
1163 | ahd_inb(ahd, SG_CACHE_SHADOW)); |
1164 | } |
1165 | #endif |
1166 | ahd_reinitialize_dataptrs(ahd); |
1167 | break; |
1168 | } |
1169 | case HOST_MSG_LOOP: |
1170 | { |
1171 | struct ahd_devinfo devinfo; |
1172 | |
1173 | /* |
1174 | * The sequencer has encountered a message phase |
1175 | * that requires host assistance for completion. |
1176 | * While handling the message phase(s), we will be |
1177 | * notified by the sequencer after each byte is |
1178 | * transferred so we can track bus phase changes. |
1179 | * |
1180 | * If this is the first time we've seen a HOST_MSG_LOOP |
1181 | * interrupt, initialize the state of the host message |
1182 | * loop. |
1183 | */ |
1184 | ahd_fetch_devinfo(ahd, &devinfo); |
1185 | if (ahd->msg_type == MSG_TYPE_NONE) { |
1186 | struct scb *scb; |
1187 | u_int scb_index; |
1188 | u_int bus_phase; |
1189 | |
1190 | bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; |
1191 | if (bus_phase != P_MESGIN |
1192 | && bus_phase != P_MESGOUT) { |
1193 | printf("ahd_intr: HOST_MSG_LOOP bad " |
1194 | "phase 0x%x\n" , bus_phase); |
1195 | /* |
1196 | * Probably transitioned to bus free before |
1197 | * we got here. Just punt the message. |
1198 | */ |
1199 | ahd_dump_card_state(ahd); |
1200 | ahd_clear_intstat(ahd); |
1201 | ahd_restart(ahd); |
1202 | return; |
1203 | } |
1204 | |
1205 | scb_index = ahd_get_scbptr(ahd); |
1206 | scb = ahd_lookup_scb(ahd, scb_index); |
1207 | if (devinfo.role == ROLE_INITIATOR) { |
1208 | if (bus_phase == P_MESGOUT) |
1209 | ahd_setup_initiator_msgout(ahd, |
1210 | &devinfo, |
1211 | scb); |
1212 | else { |
1213 | ahd->msg_type = |
1214 | MSG_TYPE_INITIATOR_MSGIN; |
1215 | ahd->msgin_index = 0; |
1216 | } |
1217 | } |
1218 | #if AHD_TARGET_MODE |
1219 | else { |
1220 | if (bus_phase == P_MESGOUT) { |
1221 | ahd->msg_type = |
1222 | MSG_TYPE_TARGET_MSGOUT; |
1223 | ahd->msgin_index = 0; |
1224 | } |
1225 | else |
1226 | ahd_setup_target_msgin(ahd, |
1227 | &devinfo, |
1228 | scb); |
1229 | } |
1230 | #endif |
1231 | } |
1232 | |
1233 | ahd_handle_message_phase(ahd); |
1234 | break; |
1235 | } |
1236 | case NO_MATCH: |
1237 | { |
1238 | /* Ensure we don't leave the selection hardware on */ |
1239 | AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); |
1240 | ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); |
1241 | |
1242 | printf("%s:%c:%d: no active SCB for reconnecting " |
1243 | "target - issuing BUS DEVICE RESET\n" , |
1244 | ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4); |
1245 | printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " |
1246 | "REG0 == 0x%x ACCUM = 0x%x\n" , |
1247 | ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN), |
1248 | ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM)); |
1249 | printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " |
1250 | "SINDEX == 0x%x\n" , |
1251 | ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd), |
1252 | ahd_find_busy_tcl(ahd, |
1253 | BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID), |
1254 | ahd_inb(ahd, SAVED_LUN))), |
1255 | ahd_inw(ahd, SINDEX)); |
1256 | printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " |
1257 | "SCB_CONTROL == 0x%x\n" , |
1258 | ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID), |
1259 | ahd_inb_scbram(ahd, SCB_LUN), |
1260 | ahd_inb_scbram(ahd, SCB_CONTROL)); |
1261 | printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n" , |
1262 | ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI)); |
1263 | printf("SXFRCTL0 == 0x%x\n" , ahd_inb(ahd, SXFRCTL0)); |
1264 | printf("SEQCTL0 == 0x%x\n" , ahd_inb(ahd, SEQCTL0)); |
1265 | ahd_dump_card_state(ahd); |
1266 | ahd->msgout_buf[0] = MSG_BUS_DEV_RESET; |
1267 | ahd->msgout_len = 1; |
1268 | ahd->msgout_index = 0; |
1269 | ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; |
1270 | ahd_outb(ahd, MSG_OUT, HOST_MSG); |
1271 | ahd_assert_atn(ahd); |
1272 | break; |
1273 | } |
1274 | case PROTO_VIOLATION: |
1275 | { |
1276 | ahd_handle_proto_violation(ahd); |
1277 | break; |
1278 | } |
1279 | case IGN_WIDE_RES: |
1280 | { |
1281 | struct ahd_devinfo devinfo; |
1282 | |
1283 | ahd_fetch_devinfo(ahd, &devinfo); |
1284 | ahd_handle_ign_wide_residue(ahd, &devinfo); |
1285 | break; |
1286 | } |
1287 | case BAD_PHASE: |
1288 | { |
1289 | u_int lastphase; |
1290 | |
1291 | lastphase = ahd_inb(ahd, LASTPHASE); |
1292 | printf("%s:%c:%d: unknown scsi bus phase %x, " |
1293 | "lastphase = 0x%x. Attempting to continue\n" , |
1294 | ahd_name(ahd), 'A', |
1295 | SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), |
1296 | lastphase, ahd_inb(ahd, SCSISIGI)); |
1297 | break; |
1298 | } |
1299 | case MISSED_BUSFREE: |
1300 | { |
1301 | u_int lastphase; |
1302 | |
1303 | lastphase = ahd_inb(ahd, LASTPHASE); |
1304 | printf("%s:%c:%d: Missed busfree. " |
1305 | "Lastphase = 0x%x, Curphase = 0x%x\n" , |
1306 | ahd_name(ahd), 'A', |
1307 | SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), |
1308 | lastphase, ahd_inb(ahd, SCSISIGI)); |
1309 | ahd_restart(ahd); |
1310 | return; |
1311 | } |
1312 | case DATA_OVERRUN: |
1313 | { |
1314 | /* |
1315 | * When the sequencer detects an overrun, it |
1316 | * places the controller in "BITBUCKET" mode |
1317 | * and allows the target to complete its transfer. |
1318 | * Unfortunately, none of the counters get updated |
1319 | * when the controller is in this mode, so we have |
1320 | * no way of knowing how large the overrun was. |
1321 | */ |
1322 | struct scb *scb; |
1323 | u_int scbindex; |
1324 | #ifdef AHD_DEBUG |
1325 | u_int lastphase; |
1326 | #endif |
1327 | |
1328 | scbindex = ahd_get_scbptr(ahd); |
1329 | scb = ahd_lookup_scb(ahd, scbindex); |
1330 | #ifdef AHD_DEBUG |
1331 | lastphase = ahd_inb(ahd, LASTPHASE); |
1332 | if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { |
1333 | ahd_print_path(ahd, scb); |
1334 | printf("data overrun detected %s. Tag == 0x%x.\n" , |
1335 | ahd_lookup_phase_entry(lastphase)->phasemsg, |
1336 | SCB_GET_TAG(scb)); |
1337 | ahd_print_path(ahd, scb); |
1338 | printf("%s seen Data Phase. Length = %ld. " |
1339 | "NumSGs = %d.\n" , |
1340 | ahd_inb(ahd, SEQ_FLAGS) & DPHASE |
1341 | ? "Have" : "Haven't" , |
1342 | ahd_get_transfer_length(scb), scb->sg_count); |
1343 | ahd_dump_sglist(scb); |
1344 | } |
1345 | #endif |
1346 | |
1347 | /* |
1348 | * Set this and it will take effect when the |
1349 | * target does a command complete. |
1350 | */ |
1351 | ahd_freeze_devq(ahd, scb); |
1352 | ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); |
1353 | ahd_freeze_scb(scb); |
1354 | break; |
1355 | } |
1356 | case MKMSG_FAILED: |
1357 | { |
1358 | struct ahd_devinfo devinfo; |
1359 | struct scb *scb; |
1360 | u_int scbid; |
1361 | |
1362 | ahd_fetch_devinfo(ahd, &devinfo); |
1363 | printf("%s:%c:%d:%d: Attempt to issue message failed\n" , |
1364 | ahd_name(ahd), devinfo.channel, devinfo.target, |
1365 | devinfo.lun); |
1366 | scbid = ahd_get_scbptr(ahd); |
1367 | scb = ahd_lookup_scb(ahd, scbid); |
1368 | if (scb != NULL |
1369 | && (scb->flags & SCB_RECOVERY_SCB) != 0) |
1370 | /* |
1371 | * Ensure that we didn't put a second instance of this |
1372 | * SCB into the QINFIFO. |
1373 | */ |
1374 | ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), |
1375 | SCB_GET_CHANNEL(ahd, scb), |
1376 | SCB_GET_LUN(scb), SCB_GET_TAG(scb), |
1377 | ROLE_INITIATOR, /*status*/0, |
1378 | SEARCH_REMOVE); |
1379 | ahd_outb(ahd, SCB_CONTROL, |
1380 | ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); |
1381 | break; |
1382 | } |
1383 | case TASKMGMT_FUNC_COMPLETE: |
1384 | { |
1385 | u_int scbid; |
1386 | struct scb *scb; |
1387 | |
1388 | scbid = ahd_get_scbptr(ahd); |
1389 | scb = ahd_lookup_scb(ahd, scbid); |
1390 | if (scb != NULL) { |
1391 | u_int lun; |
1392 | u_int tag; |
1393 | cam_status error; |
1394 | |
1395 | ahd_print_path(ahd, scb); |
1396 | printf("Task Management Func 0x%x Complete\n" , |
1397 | scb->hscb->task_management); |
1398 | lun = CAM_LUN_WILDCARD; |
1399 | tag = SCB_LIST_NULL; |
1400 | |
1401 | switch (scb->hscb->task_management) { |
1402 | case SIU_TASKMGMT_ABORT_TASK: |
1403 | tag = SCB_GET_TAG(scb); |
1404 | case SIU_TASKMGMT_ABORT_TASK_SET: |
1405 | case SIU_TASKMGMT_CLEAR_TASK_SET: |
1406 | lun = scb->hscb->lun; |
1407 | error = CAM_REQ_ABORTED; |
1408 | ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), |
1409 | 'A', lun, tag, ROLE_INITIATOR, |
1410 | error); |
1411 | break; |
1412 | case SIU_TASKMGMT_LUN_RESET: |
1413 | lun = scb->hscb->lun; |
1414 | case SIU_TASKMGMT_TARGET_RESET: |
1415 | { |
1416 | struct ahd_devinfo devinfo; |
1417 | |
1418 | ahd_scb_devinfo(ahd, &devinfo, scb); |
1419 | error = CAM_BDR_SENT; |
1420 | ahd_handle_devreset(ahd, &devinfo, lun, |
1421 | CAM_BDR_SENT, |
1422 | lun != CAM_LUN_WILDCARD |
1423 | ? "Lun Reset" |
1424 | : "Target Reset" , |
1425 | /*verbose_level*/0); |
1426 | break; |
1427 | } |
1428 | default: |
1429 | panic("Unexpected TaskMgmt Func\n" ); |
1430 | break; |
1431 | } |
1432 | } |
1433 | break; |
1434 | } |
1435 | case TASKMGMT_CMD_CMPLT_OKAY: |
1436 | { |
1437 | u_int scbid; |
1438 | struct scb *scb; |
1439 | |
1440 | /* |
1441 | * An ABORT TASK TMF failed to be delivered before |
1442 | * the targeted command completed normally. |
1443 | */ |
1444 | scbid = ahd_get_scbptr(ahd); |
1445 | scb = ahd_lookup_scb(ahd, scbid); |
1446 | if (scb != NULL) { |
1447 | /* |
1448 | * Remove the second instance of this SCB from |
1449 | * the QINFIFO if it is still there. |
1450 | */ |
1451 | ahd_print_path(ahd, scb); |
1452 | printf("SCB completes before TMF\n" ); |
1453 | /* |
1454 | * Handle losing the race. Wait until any |
1455 | * current selection completes. We will then |
1456 | * set the TMF back to zero in this SCB so that |
1457 | * the sequencer doesn't bother to issue another |
1458 | * sequencer interrupt for its completion. |
1459 | */ |
1460 | while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 |
1461 | && (ahd_inb(ahd, SSTAT0) & SELDO) == 0 |
1462 | && (ahd_inb(ahd, SSTAT1) & SELTO) == 0) |
1463 | ; |
1464 | ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0); |
1465 | ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), |
1466 | SCB_GET_CHANNEL(ahd, scb), |
1467 | SCB_GET_LUN(scb), SCB_GET_TAG(scb), |
1468 | ROLE_INITIATOR, /*status*/0, |
1469 | SEARCH_REMOVE); |
1470 | } |
1471 | break; |
1472 | } |
1473 | case TRACEPOINT0: |
1474 | case TRACEPOINT1: |
1475 | case TRACEPOINT2: |
1476 | case TRACEPOINT3: |
1477 | printf("%s: Tracepoint %d\n" , ahd_name(ahd), |
1478 | seqintcode - TRACEPOINT0); |
1479 | break; |
1480 | case NO_SEQINT: |
1481 | break; |
1482 | case SAW_HWERR: |
1483 | ahd_handle_hwerrint(ahd); |
1484 | break; |
1485 | default: |
1486 | printf("%s: Unexpected SEQINTCODE %d\n" , ahd_name(ahd), |
1487 | seqintcode); |
1488 | break; |
1489 | } |
1490 | /* |
1491 | * The sequencer is paused immediately on |
1492 | * a SEQINT, so we should restart it when |
1493 | * we're done. |
1494 | */ |
1495 | ahd_unpause(ahd); |
1496 | } |
1497 | |
1498 | void |
1499 | ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) |
1500 | { |
1501 | struct scb *scb; |
1502 | u_int status0; |
1503 | u_int status3; |
1504 | u_int status; |
1505 | u_int lqistat1; |
1506 | u_int lqostat0; |
1507 | u_int scbid; |
1508 | u_int busfreetime; |
1509 | |
1510 | ahd_update_modes(ahd); |
1511 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
1512 | |
1513 | status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR); |
1514 | status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO); |
1515 | status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); |
1516 | lqistat1 = ahd_inb(ahd, LQISTAT1); |
1517 | lqostat0 = ahd_inb(ahd, LQOSTAT0); |
1518 | busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; |
1519 | if ((status0 & (SELDI|SELDO)) != 0) { |
1520 | u_int simode0; |
1521 | |
1522 | ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); |
1523 | simode0 = ahd_inb(ahd, SIMODE0); |
1524 | status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO); |
1525 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
1526 | } |
1527 | scbid = ahd_get_scbptr(ahd); |
1528 | scb = ahd_lookup_scb(ahd, scbid); |
1529 | if (scb != NULL |
1530 | && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) |
1531 | scb = NULL; |
1532 | |
1533 | /* Make sure the sequencer is in a safe location. */ |
1534 | ahd_clear_critical_section(ahd); |
1535 | |
1536 | if ((status0 & IOERR) != 0) { |
1537 | u_int now_lvd; |
1538 | |
1539 | now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40; |
1540 | printf("%s: Transceiver State Has Changed to %s mode\n" , |
1541 | ahd_name(ahd), now_lvd ? "LVD" : "SE" ); |
1542 | ahd_outb(ahd, CLRSINT0, CLRIOERR); |
1543 | /* |
1544 | * A change in I/O mode is equivalent to a bus reset. |
1545 | */ |
1546 | ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); |
1547 | ahd_pause(ahd); |
1548 | ahd_setup_iocell_workaround(ahd); |
1549 | ahd_unpause(ahd); |
1550 | } else if ((status0 & OVERRUN) != 0) { |
1551 | printf("%s: SCSI offset overrun detected. Resetting bus.\n" , |
1552 | ahd_name(ahd)); |
1553 | ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); |
1554 | } else if ((status & SCSIRSTI) != 0) { |
1555 | printf("%s: Someone reset channel A\n" , ahd_name(ahd)); |
1556 | ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); |
1557 | } else if ((status & SCSIPERR) != 0) { |
1558 | ahd_handle_transmission_error(ahd); |
1559 | } else if (lqostat0 != 0) { |
1560 | printf("%s: lqostat0 == 0x%x!\n" , ahd_name(ahd), lqostat0); |
1561 | ahd_outb(ahd, CLRLQOINT0, lqostat0); |
1562 | if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { |
1563 | ahd_outb(ahd, CLRLQOINT1, 0); |
1564 | } |
1565 | } else if ((status & SELTO) != 0) { |
1566 | u_int scbid1; |
1567 | |
1568 | /* Stop the selection */ |
1569 | ahd_outb(ahd, SCSISEQ0, 0); |
1570 | |
1571 | /* No more pending messages */ |
1572 | ahd_clear_msg_state(ahd); |
1573 | |
1574 | /* Clear interrupt state */ |
1575 | ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); |
1576 | |
1577 | /* |
1578 | * Although the driver does not care about the |
1579 | * 'Selection in Progress' status bit, the busy |
1580 | * LED does. SELINGO is only cleared by a sucessfull |
1581 | * selection, so we must manually clear it to insure |
1582 | * the LED turns off just incase no future successful |
1583 | * selections occur (e.g. no devices on the bus). |
1584 | */ |
1585 | ahd_outb(ahd, CLRSINT0, CLRSELINGO); |
1586 | |
1587 | scbid1 = ahd_inw(ahd, WAITING_TID_HEAD); |
1588 | scb = ahd_lookup_scb(ahd, scbid1); |
1589 | if (scb == NULL) { |
1590 | printf("%s: ahd_intr - referenced scb not " |
1591 | "valid during SELTO scb(0x%x)\n" , |
1592 | ahd_name(ahd), scbid1); |
1593 | ahd_dump_card_state(ahd); |
1594 | } else { |
1595 | struct ahd_devinfo devinfo; |
1596 | #ifdef AHD_DEBUG |
1597 | if ((ahd_debug & AHD_SHOW_SELTO) != 0) { |
1598 | ahd_print_path(ahd, scb); |
1599 | printf("Saw Selection Timeout for SCB 0x%x\n" , |
1600 | scbid1); |
1601 | } |
1602 | #endif |
1603 | /* |
1604 | * Force a renegotiation with this target just in |
1605 | * case the cable was pulled and will later be |
1606 | * re-attached. The target may forget its negotiation |
1607 | * settings with us should it attempt to reselect |
1608 | * during the interruption. The target will not issue |
1609 | * a unit attention in this case, so we must always |
1610 | * renegotiate. |
1611 | */ |
1612 | ahd_scb_devinfo(ahd, &devinfo, scb); |
1613 | ahd_force_renegotiation(ahd, &devinfo); |
1614 | ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT); |
1615 | ahd_freeze_devq(ahd, scb); |
1616 | } |
1617 | ahd_outb(ahd, CLRINT, CLRSCSIINT); |
1618 | ahd_iocell_first_selection(ahd); |
1619 | ahd_unpause(ahd); |
1620 | } else if ((status0 & (SELDI|SELDO)) != 0) { |
1621 | ahd_iocell_first_selection(ahd); |
1622 | ahd_unpause(ahd); |
1623 | } else if (status3 != 0) { |
1624 | printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n" , |
1625 | ahd_name(ahd), status3); |
1626 | ahd_outb(ahd, CLRSINT3, status3); |
1627 | } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) { |
1628 | ahd_handle_lqiphase_error(ahd, lqistat1); |
1629 | } else if ((lqistat1 & LQICRCI_NLQ) != 0) { |
1630 | /* |
1631 | * This status can be delayed during some |
1632 | * streaming operations. The SCSIPHASE |
1633 | * handler has already dealt with this case |
1634 | * so just clear the error. |
1635 | */ |
1636 | ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ); |
1637 | } else if ((status & BUSFREE) != 0) { |
1638 | u_int lqostat1; |
1639 | int restart; |
1640 | int clear_fifo; |
1641 | int packetized; |
1642 | u_int mode; |
1643 | |
1644 | /* |
1645 | * Clear our selection hardware as soon as possible. |
1646 | * We may have an entry in the waiting Q for this target, |
1647 | * that is affected by this busfree and we don't want to |
1648 | * go about selecting the target while we handle the event. |
1649 | */ |
1650 | ahd_outb(ahd, SCSISEQ0, 0); |
1651 | |
1652 | /* |
1653 | * Determine what we were up to at the time of |
1654 | * the busfree. |
1655 | */ |
1656 | mode = AHD_MODE_SCSI; |
1657 | busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; |
1658 | lqostat1 = ahd_inb(ahd, LQOSTAT1); |
1659 | switch (busfreetime) { |
1660 | case BUSFREE_DFF0: |
1661 | case BUSFREE_DFF1: |
1662 | { |
1663 | u_int scbid1; |
1664 | struct scb *scb1; |
1665 | |
1666 | mode = busfreetime == BUSFREE_DFF0 |
1667 | ? AHD_MODE_DFF0 : AHD_MODE_DFF1; |
1668 | ahd_set_modes(ahd, mode, mode); |
1669 | scbid1 = ahd_get_scbptr(ahd); |
1670 | scb1 = ahd_lookup_scb(ahd, scbid1); |
1671 | if (scb1 == NULL) { |
1672 | printf("%s: Invalid SCB %d in DFF%d " |
1673 | "during unexpected busfree\n" , |
1674 | ahd_name(ahd), scbid1, mode); |
1675 | packetized = 0; |
1676 | } else |
1677 | packetized = |
1678 | (scb1->flags & SCB_PACKETIZED) != 0; |
1679 | clear_fifo = 1; |
1680 | break; |
1681 | } |
1682 | case BUSFREE_LQO: |
1683 | clear_fifo = 0; |
1684 | packetized = 1; |
1685 | break; |
1686 | default: |
1687 | clear_fifo = 0; |
1688 | packetized = (lqostat1 & LQOBUSFREE) != 0; |
1689 | if (!packetized |
1690 | && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) |
1691 | packetized = 1; |
1692 | break; |
1693 | } |
1694 | |
1695 | #ifdef AHD_DEBUG |
1696 | if ((ahd_debug & AHD_SHOW_MISC) != 0) |
1697 | printf("Saw Busfree. Busfreetime = 0x%x.\n" , |
1698 | busfreetime); |
1699 | #endif |
1700 | /* |
1701 | * Busfrees that occur in non-packetized phases are |
1702 | * handled by the nonpkt_busfree handler. |
1703 | */ |
1704 | if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) { |
1705 | restart = ahd_handle_pkt_busfree(ahd, busfreetime); |
1706 | } else { |
1707 | packetized = 0; |
1708 | restart = ahd_handle_nonpkt_busfree(ahd); |
1709 | } |
1710 | /* |
1711 | * Clear the busfree interrupt status. The setting of |
1712 | * the interrupt is a pulse, so in a perfect world, we |
1713 | * would not need to muck with the ENBUSFREE logic. This |
1714 | * would ensure that if the bus moves on to another |
1715 | * connection, busfree protection is still in force. If |
1716 | * BUSFREEREV is broken, however, we must manually clear |
1717 | * the ENBUSFREE if the busfree occurred during a non-pack |
1718 | * connection so that we don't get false positives during |
1719 | * future, packetized, connections. |
1720 | */ |
1721 | ahd_outb(ahd, CLRSINT1, CLRBUSFREE); |
1722 | if (packetized == 0 |
1723 | && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0) |
1724 | ahd_outb(ahd, SIMODE1, |
1725 | ahd_inb(ahd, SIMODE1) & ~ENBUSFREE); |
1726 | |
1727 | if (clear_fifo) |
1728 | ahd_clear_fifo(ahd, mode); |
1729 | |
1730 | ahd_clear_msg_state(ahd); |
1731 | ahd_outb(ahd, CLRINT, CLRSCSIINT); |
1732 | if (restart) { |
1733 | ahd_restart(ahd); |
1734 | } else { |
1735 | ahd_unpause(ahd); |
1736 | } |
1737 | } else { |
1738 | printf("%s: Missing case in ahd_handle_scsiint. status = %x\n" , |
1739 | ahd_name(ahd), status); |
1740 | ahd_dump_card_state(ahd); |
1741 | ahd_clear_intstat(ahd); |
1742 | ahd_unpause(ahd); |
1743 | } |
1744 | } |
1745 | |
1746 | static void |
1747 | ahd_handle_transmission_error(struct ahd_softc *ahd) |
1748 | { |
1749 | struct scb *scb; |
1750 | u_int scbid; |
1751 | u_int lqistat1; |
1752 | u_int msg_out; |
1753 | u_int curphase; |
1754 | u_int lastphase; |
1755 | u_int perrdiag; |
1756 | u_int cur_col; |
1757 | int silent; |
1758 | |
1759 | scb = NULL; |
1760 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
1761 | lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ); |
1762 | (void)ahd_inb(ahd, LQISTAT2); |
1763 | if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0 |
1764 | && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) { |
1765 | u_int lqistate; |
1766 | |
1767 | ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); |
1768 | lqistate = ahd_inb(ahd, LQISTATE); |
1769 | if ((lqistate >= 0x1E && lqistate <= 0x24) |
1770 | || (lqistate == 0x29)) { |
1771 | #ifdef AHD_DEBUG |
1772 | if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { |
1773 | printf("%s: NLQCRC found via LQISTATE\n" , |
1774 | ahd_name(ahd)); |
1775 | } |
1776 | #endif |
1777 | lqistat1 |= LQICRCI_NLQ; |
1778 | } |
1779 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
1780 | } |
1781 | |
1782 | ahd_outb(ahd, CLRLQIINT1, lqistat1); |
1783 | lastphase = ahd_inb(ahd, LASTPHASE); |
1784 | curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; |
1785 | perrdiag = ahd_inb(ahd, PERRDIAG); |
1786 | msg_out = MSG_INITIATOR_DET_ERR; |
1787 | ahd_outb(ahd, CLRSINT1, CLRSCSIPERR); |
1788 | |
1789 | /* |
1790 | * Try to find the SCB associated with this error. |
1791 | */ |
1792 | silent = FALSE; |
1793 | if (lqistat1 == 0 |
1794 | || (lqistat1 & LQICRCI_NLQ) != 0) { |
1795 | if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0) |
1796 | ahd_set_active_fifo(ahd); |
1797 | scbid = ahd_get_scbptr(ahd); |
1798 | scb = ahd_lookup_scb(ahd, scbid); |
1799 | if (scb != NULL && SCB_IS_SILENT(scb)) |
1800 | silent = TRUE; |
1801 | } |
1802 | |
1803 | cur_col = 0; |
1804 | if (silent == FALSE) { |
1805 | printf("%s: Transmission error detected\n" , ahd_name(ahd)); |
1806 | ahd_lqistat1_print(lqistat1, &cur_col, 50); |
1807 | ahd_lastphase_print(lastphase, &cur_col, 50); |
1808 | ahd_scsisigi_print(curphase, &cur_col, 50); |
1809 | ahd_perrdiag_print(perrdiag, &cur_col, 50); |
1810 | printf("\n" ); |
1811 | ahd_dump_card_state(ahd); |
1812 | } |
1813 | |
1814 | if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) { |
1815 | if (silent == FALSE) { |
1816 | printf("%s: Gross protocol error during incoming " |
1817 | "packet. lqistat1 == 0x%x. Resetting bus.\n" , |
1818 | ahd_name(ahd), lqistat1); |
1819 | } |
1820 | ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); |
1821 | return; |
1822 | } else if ((lqistat1 & LQICRCI_LQ) != 0) { |
1823 | /* |
1824 | * A CRC error has been detected on an incoming LQ. |
1825 | * The bus is currently hung on the last ACK. |
1826 | * Hit LQIRETRY to release the last ack, and |
1827 | * wait for the sequencer to determine that ATNO |
1828 | * is asserted while in message out to take us |
1829 | * to our host message loop. No NONPACKREQ or |
1830 | * LQIPHASE type errors will occur in this |
1831 | * scenario. After this first LQIRETRY, the LQI |
1832 | * manager will be in ISELO where it will |
1833 | * happily sit until another packet phase begins. |
1834 | * Unexpected bus free detection is enabled |
1835 | * through any phases that occur after we release |
1836 | * this last ack until the LQI manager sees a |
1837 | * packet phase. This implies we may have to |
1838 | * ignore a perfectly valid "unexected busfree" |
1839 | * after our "initiator detected error" message is |
1840 | * sent. A busfree is the expected response after |
1841 | * we tell the target that its L_Q was corrupted. |
1842 | * (SPI4R09 10.7.3.3.3) |
1843 | */ |
1844 | ahd_outb(ahd, LQCTL2, LQIRETRY); |
1845 | printf("LQIRetry for LQICRCI_LQ to release ACK\n" ); |
1846 | } else if ((lqistat1 & LQICRCI_NLQ) != 0) { |
1847 | /* |
1848 | * We detected a CRC error in a NON-LQ packet. |
1849 | * The hardware has varying behavior in this situation |
1850 | * depending on whether this packet was part of a |
1851 | * stream or not. |
1852 | * |
1853 | * PKT by PKT mode: |
1854 | * The hardware has already acked the complete packet. |
1855 | * If the target honors our outstanding ATN condition, |
1856 | * we should be (or soon will be) in MSGOUT phase. |
1857 | * This will trigger the LQIPHASE_LQ status bit as the |
1858 | * hardware was expecting another LQ. Unexpected |
1859 | * busfree detection is enabled. Once LQIPHASE_LQ is |
1860 | * true (first entry into host message loop is much |
1861 | * the same), we must clear LQIPHASE_LQ and hit |
1862 | * LQIRETRY so the hardware is ready to handle |
1863 | * a future LQ. NONPACKREQ will not be asserted again |
1864 | * once we hit LQIRETRY until another packet is |
1865 | * processed. The target may either go busfree |
1866 | * or start another packet in response to our message. |
1867 | * |
1868 | * Read Streaming P0 asserted: |
1869 | * If we raise ATN and the target completes the entire |
1870 | * stream (P0 asserted during the last packet), the |
1871 | * hardware will ack all data and return to the ISTART |
1872 | * state. When the target reponds to our ATN condition, |
1873 | * LQIPHASE_LQ will be asserted. We should respond to |
1874 | * this with an LQIRETRY to prepare for any future |
1875 | * packets. NONPACKREQ will not be asserted again |
1876 | * once we hit LQIRETRY until another packet is |
1877 | * processed. The target may either go busfree or |
1878 | * start another packet in response to our message. |
1879 | * Busfree detection is enabled. |
1880 | * |
1881 | * Read Streaming P0 not asserted: |
1882 | * If we raise ATN and the target transitions to |
1883 | * MSGOUT in or after a packet where P0 is not |
1884 | * asserted, the hardware will assert LQIPHASE_NLQ. |
1885 | * We should respond to the LQIPHASE_NLQ with an |
1886 | * LQIRETRY. Should the target stay in a non-pkt |
1887 | * phase after we send our message, the hardware |
1888 | * will assert LQIPHASE_LQ. Recovery is then just as |
1889 | * listed above for the read streaming with P0 asserted. |
1890 | * Busfree detection is enabled. |
1891 | */ |
1892 | if (silent == FALSE) |
1893 | printf("LQICRC_NLQ\n" ); |
1894 | if (scb == NULL) { |
1895 | printf("%s: No SCB valid for LQICRC_NLQ. " |
1896 | "Resetting bus\n" , ahd_name(ahd)); |
1897 | ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); |
1898 | return; |
1899 | } |
1900 | } else if ((lqistat1 & LQIBADLQI) != 0) { |
1901 | printf("Need to handle BADLQI!\n" ); |
1902 | ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); |
1903 | return; |
1904 | } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) { |
1905 | if ((curphase & ~P_DATAIN_DT) != 0) { |
1906 | /* Ack the byte. So we can continue. */ |
1907 | if (silent == FALSE) |
1908 | printf("Acking %s to clear perror\n" , |
1909 | ahd_lookup_phase_entry(curphase)->phasemsg); |
1910 | ahd_inb(ahd, SCSIDAT); |
1911 | } |
1912 | |
1913 | if (curphase == P_MESGIN) |
1914 | msg_out = MSG_PARITY_ERROR; |
1915 | } |
1916 | |
1917 | /* |
1918 | * We've set the hardware to assert ATN if we |
1919 | * get a parity error on "in" phases, so all we |
1920 | * need to do is stuff the message buffer with |
1921 | * the appropriate message. "In" phases have set |
1922 | * mesg_out to something other than MSG_NOP. |
1923 | */ |
1924 | ahd->send_msg_perror = msg_out; |
1925 | if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR) |
1926 | scb->flags |= SCB_TRANSMISSION_ERROR; |
1927 | ahd_outb(ahd, MSG_OUT, HOST_MSG); |
1928 | ahd_outb(ahd, CLRINT, CLRSCSIINT); |
1929 | ahd_unpause(ahd); |
1930 | } |
1931 | |
1932 | static void |
1933 | ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1) |
1934 | { |
1935 | /* |
1936 | * Clear the sources of the interrupts. |
1937 | */ |
1938 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
1939 | ahd_outb(ahd, CLRLQIINT1, lqistat1); |
1940 | |
1941 | /* |
1942 | * If the "illegal" phase changes were in response |
1943 | * to our ATN to flag a CRC error, AND we ended up |
1944 | * on packet boundaries, clear the error, restart the |
1945 | * LQI manager as appropriate, and go on our merry |
1946 | * way toward sending the message. Otherwise, reset |
1947 | * the bus to clear the error. |
1948 | */ |
1949 | ahd_set_active_fifo(ahd); |
1950 | if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0 |
1951 | && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) { |
1952 | if ((lqistat1 & LQIPHASE_LQ) != 0) { |
1953 | printf("LQIRETRY for LQIPHASE_LQ\n" ); |
1954 | ahd_outb(ahd, LQCTL2, LQIRETRY); |
1955 | } else if ((lqistat1 & LQIPHASE_NLQ) != 0) { |
1956 | printf("LQIRETRY for LQIPHASE_NLQ\n" ); |
1957 | ahd_outb(ahd, LQCTL2, LQIRETRY); |
1958 | } else |
1959 | panic("ahd_handle_lqiphase_error: No phase errors\n" ); |
1960 | ahd_dump_card_state(ahd); |
1961 | ahd_outb(ahd, CLRINT, CLRSCSIINT); |
1962 | ahd_unpause(ahd); |
1963 | } else { |
1964 | printf("Reseting Channel for LQI Phase error\n" ); |
1965 | ahd_dump_card_state(ahd); |
1966 | ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); |
1967 | } |
1968 | } |
1969 | |
1970 | /* |
1971 | * Packetized unexpected or expected busfree. |
1972 | * Entered in mode based on busfreetime. |
1973 | */ |
1974 | static int |
1975 | ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime) |
1976 | { |
1977 | u_int lqostat1; |
1978 | |
1979 | AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), |
1980 | ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); |
1981 | lqostat1 = ahd_inb(ahd, LQOSTAT1); |
1982 | if ((lqostat1 & LQOBUSFREE) != 0) { |
1983 | struct scb *scb; |
1984 | u_int scbid; |
1985 | u_int saved_scbptr; |
1986 | u_int waiting_h; |
1987 | u_int waiting_t; |
1988 | u_int next; |
1989 | |
1990 | if ((busfreetime & BUSFREE_LQO) == 0) |
1991 | printf("%s: Warning, BUSFREE time is 0x%x. " |
1992 | "Expected BUSFREE_LQO.\n" , |
1993 | ahd_name(ahd), busfreetime); |
1994 | /* |
1995 | * The LQO manager detected an unexpected busfree |
1996 | * either: |
1997 | * |
1998 | * 1) During an outgoing LQ. |
1999 | * 2) After an outgoing LQ but before the first |
2000 | * REQ of the command packet. |
2001 | * 3) During an outgoing command packet. |
2002 | * |
2003 | * In all cases, CURRSCB is pointing to the |
2004 | * SCB that encountered the failure. Clean |
2005 | * up the queue, clear SELDO and LQOBUSFREE, |
2006 | * and allow the sequencer to restart the select |
2007 | * out at its lesure. |
2008 | */ |
2009 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
2010 | scbid = ahd_inw(ahd, CURRSCB); |
2011 | scb = ahd_lookup_scb(ahd, scbid); |
2012 | if (scb == NULL) |
2013 | panic("SCB not valid during LQOBUSFREE" ); |
2014 | /* |
2015 | * Clear the status. |
2016 | */ |
2017 | ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE); |
2018 | if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) |
2019 | ahd_outb(ahd, CLRLQOINT1, 0); |
2020 | ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); |
2021 | ahd_flush_device_writes(ahd); |
2022 | ahd_outb(ahd, CLRSINT0, CLRSELDO); |
2023 | |
2024 | /* |
2025 | * Return the LQO manager to its idle loop. It will |
2026 | * not do this automatically if the busfree occurs |
2027 | * after the first REQ of either the LQ or command |
2028 | * packet or between the LQ and command packet. |
2029 | */ |
2030 | ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE); |
2031 | |
2032 | /* |
2033 | * Update the waiting for selection queue so |
2034 | * we restart on the correct SCB. |
2035 | */ |
2036 | waiting_h = ahd_inw(ahd, WAITING_TID_HEAD); |
2037 | saved_scbptr = ahd_get_scbptr(ahd); |
2038 | if (waiting_h != scbid) { |
2039 | |
2040 | ahd_outw(ahd, WAITING_TID_HEAD, scbid); |
2041 | waiting_t = ahd_inw(ahd, WAITING_TID_TAIL); |
2042 | if (waiting_t == waiting_h) { |
2043 | ahd_outw(ahd, WAITING_TID_TAIL, scbid); |
2044 | next = SCB_LIST_NULL; |
2045 | } else { |
2046 | ahd_set_scbptr(ahd, waiting_h); |
2047 | next = ahd_inw_scbram(ahd, SCB_NEXT2); |
2048 | } |
2049 | ahd_set_scbptr(ahd, scbid); |
2050 | ahd_outw(ahd, SCB_NEXT2, next); |
2051 | } |
2052 | ahd_set_scbptr(ahd, saved_scbptr); |
2053 | if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) { |
2054 | if (SCB_IS_SILENT(scb) == FALSE) { |
2055 | ahd_print_path(ahd, scb); |
2056 | printf("Probable outgoing LQ CRC error. " |
2057 | "Retrying command\n" ); |
2058 | } |
2059 | scb->crc_retry_count++; |
2060 | } else { |
2061 | ahd_set_transaction_status(scb, CAM_UNCOR_PARITY); |
2062 | ahd_freeze_scb(scb); |
2063 | ahd_freeze_devq(ahd, scb); |
2064 | } |
2065 | /* Return unpausing the sequencer. */ |
2066 | return (0); |
2067 | } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) { |
2068 | /* |
2069 | * Ignore what are really parity errors that |
2070 | * occur on the last REQ of a free running |
2071 | * clock prior to going busfree. Some drives |
2072 | * do not properly active negate just before |
2073 | * going busfree resulting in a parity glitch. |
2074 | */ |
2075 | ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE); |
2076 | #ifdef AHD_DEBUG |
2077 | if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0) |
2078 | printf("%s: Parity on last REQ detected " |
2079 | "during busfree phase.\n" , |
2080 | ahd_name(ahd)); |
2081 | #endif |
2082 | /* Return unpausing the sequencer. */ |
2083 | return (0); |
2084 | } |
2085 | if (ahd->src_mode != AHD_MODE_SCSI) { |
2086 | u_int scbid; |
2087 | struct scb *scb; |
2088 | |
2089 | scbid = ahd_get_scbptr(ahd); |
2090 | scb = ahd_lookup_scb(ahd, scbid); |
2091 | ahd_print_path(ahd, scb); |
2092 | printf("Unexpected PKT busfree condition\n" ); |
2093 | ahd_dump_card_state(ahd); |
2094 | ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A', |
2095 | SCB_GET_LUN(scb), SCB_GET_TAG(scb), |
2096 | ROLE_INITIATOR, CAM_UNEXP_BUSFREE); |
2097 | |
2098 | /* Return restarting the sequencer. */ |
2099 | return (1); |
2100 | } |
2101 | printf("%s: Unexpected PKT busfree condition\n" , ahd_name(ahd)); |
2102 | ahd_dump_card_state(ahd); |
2103 | /* Restart the sequencer. */ |
2104 | return (1); |
2105 | } |
2106 | |
2107 | /* |
2108 | * Non-packetized unexpected or expected busfree. |
2109 | */ |
2110 | static int |
2111 | ahd_handle_nonpkt_busfree(struct ahd_softc *ahd) |
2112 | { |
2113 | struct ahd_devinfo devinfo; |
2114 | struct scb *scb; |
2115 | u_int lastphase; |
2116 | u_int saved_scsiid; |
2117 | u_int saved_lun; |
2118 | u_int target; |
2119 | u_int initiator_role_id; |
2120 | u_int scbid; |
2121 | u_int ppr_busfree; |
2122 | int printerror; |
2123 | |
2124 | /* |
2125 | * Look at what phase we were last in. If its message out, |
2126 | * chances are pretty good that the busfree was in response |
2127 | * to one of our abort requests. |
2128 | */ |
2129 | lastphase = ahd_inb(ahd, LASTPHASE); |
2130 | saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); |
2131 | saved_lun = ahd_inb(ahd, SAVED_LUN); |
2132 | target = SCSIID_TARGET(ahd, saved_scsiid); |
2133 | initiator_role_id = SCSIID_OUR_ID(saved_scsiid); |
2134 | ahd_compile_devinfo(&devinfo, initiator_role_id, |
2135 | target, saved_lun, 'A', ROLE_INITIATOR); |
2136 | printerror = 1; |
2137 | |
2138 | scbid = ahd_get_scbptr(ahd); |
2139 | scb = ahd_lookup_scb(ahd, scbid); |
2140 | if (scb != NULL |
2141 | && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) |
2142 | scb = NULL; |
2143 | |
2144 | ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0; |
2145 | if (lastphase == P_MESGOUT) { |
2146 | u_int tag; |
2147 | |
2148 | tag = SCB_LIST_NULL; |
2149 | if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE) |
2150 | || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) { |
2151 | int found; |
2152 | int sent_msg; |
2153 | |
2154 | if (scb == NULL) { |
2155 | ahd_print_devinfo(ahd, &devinfo); |
2156 | printf("Abort for unidentified " |
2157 | "connection completed.\n" ); |
2158 | /* restart the sequencer. */ |
2159 | return (1); |
2160 | } |
2161 | sent_msg = ahd->msgout_buf[ahd->msgout_index - 1]; |
2162 | ahd_print_path(ahd, scb); |
2163 | printf("SCB %d - Abort%s Completed.\n" , |
2164 | SCB_GET_TAG(scb), |
2165 | sent_msg == MSG_ABORT_TAG ? "" : " Tag" ); |
2166 | |
2167 | if (sent_msg == MSG_ABORT_TAG) |
2168 | tag = SCB_GET_TAG(scb); |
2169 | |
2170 | if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) { |
2171 | /* |
2172 | * This abort is in response to an |
2173 | * unexpected switch to command phase |
2174 | * for a packetized connection. Since |
2175 | * the identify message was never sent, |
2176 | * "saved lun" is 0. We really want to |
2177 | * abort only the SCB that encountered |
2178 | * this error, which could have a different |
2179 | * lun. The SCB will be retried so the OS |
2180 | * will see the UA after renegotiating to |
2181 | * packetized. |
2182 | */ |
2183 | tag = SCB_GET_TAG(scb); |
2184 | saved_lun = scb->hscb->lun; |
2185 | } |
2186 | found = ahd_abort_scbs(ahd, target, 'A', saved_lun, |
2187 | tag, ROLE_INITIATOR, |
2188 | CAM_REQ_ABORTED); |
2189 | printf("found == 0x%x\n" , found); |
2190 | printerror = 0; |
2191 | } else if (ahd_sent_msg(ahd, AHDMSG_1B, |
2192 | MSG_BUS_DEV_RESET, TRUE)) { |
2193 | #ifdef __FreeBSD__ |
2194 | /* |
2195 | * Don't mark the user's request for this BDR |
2196 | * as completing with CAM_BDR_SENT. CAM3 |
2197 | * specifies CAM_REQ_CMP. |
2198 | */ |
2199 | if (scb != NULL |
2200 | && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV |
2201 | && ahd_match_scb(ahd, scb, target, 'A', |
2202 | CAM_LUN_WILDCARD, SCB_LIST_NULL, |
2203 | ROLE_INITIATOR)) |
2204 | ahd_set_transaction_status(scb, CAM_REQ_CMP); |
2205 | #endif |
2206 | ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD, |
2207 | CAM_BDR_SENT, "Bus Device Reset" , |
2208 | /*verbose_level*/0); |
2209 | printerror = 0; |
2210 | } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE) |
2211 | && ppr_busfree == 0) { |
2212 | struct ahd_initiator_tinfo *tinfo; |
2213 | struct ahd_tmode_tstate *tstate; |
2214 | |
2215 | /* |
2216 | * PPR Rejected. Try non-ppr negotiation |
2217 | * and retry command. |
2218 | */ |
2219 | #ifdef AHD_DEBUG |
2220 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) |
2221 | printf("PPR negotiation rejected busfree.\n" ); |
2222 | #endif |
2223 | tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, |
2224 | devinfo.our_scsiid, |
2225 | devinfo.target, &tstate); |
2226 | tinfo->curr.transport_version = 2; |
2227 | tinfo->goal.transport_version = 2; |
2228 | tinfo->goal.ppr_options = 0; |
2229 | ahd_qinfifo_requeue_tail(ahd, scb); |
2230 | printerror = 0; |
2231 | } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE) |
2232 | && ppr_busfree == 0) { |
2233 | /* |
2234 | * Negotiation Rejected. Go-narrow and |
2235 | * retry command. |
2236 | */ |
2237 | #ifdef AHD_DEBUG |
2238 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) |
2239 | printf("WDTR Negotiation rejected busfree.\n" ); |
2240 | #endif |
2241 | ahd_set_width(ahd, &devinfo, |
2242 | MSG_EXT_WDTR_BUS_8_BIT, |
2243 | AHD_TRANS_CUR|AHD_TRANS_GOAL, |
2244 | /*paused*/TRUE); |
2245 | ahd_qinfifo_requeue_tail(ahd, scb); |
2246 | printerror = 0; |
2247 | } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE) |
2248 | && ppr_busfree == 0) { |
2249 | /* |
2250 | * Negotiation Rejected. Go-async and |
2251 | * retry command. |
2252 | */ |
2253 | #ifdef AHD_DEBUG |
2254 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) |
2255 | printf("SDTR negotiation rejected busfree.\n" ); |
2256 | #endif |
2257 | ahd_set_syncrate(ahd, &devinfo, |
2258 | /*period*/0, /*offset*/0, |
2259 | /*ppr_options*/0, |
2260 | AHD_TRANS_CUR|AHD_TRANS_GOAL, |
2261 | /*paused*/TRUE); |
2262 | ahd_qinfifo_requeue_tail(ahd, scb); |
2263 | printerror = 0; |
2264 | } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0 |
2265 | && ahd_sent_msg(ahd, AHDMSG_1B, |
2266 | MSG_INITIATOR_DET_ERR, TRUE)) { |
2267 | |
2268 | #ifdef AHD_DEBUG |
2269 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) |
2270 | printf("Expected IDE Busfree\n" ); |
2271 | #endif |
2272 | printerror = 0; |
2273 | } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE) |
2274 | && ahd_sent_msg(ahd, AHDMSG_1B, |
2275 | MSG_MESSAGE_REJECT, TRUE)) { |
2276 | |
2277 | #ifdef AHD_DEBUG |
2278 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) |
2279 | printf("Expected QAS Reject Busfree\n" ); |
2280 | #endif |
2281 | printerror = 0; |
2282 | } |
2283 | } |
2284 | |
2285 | /* |
2286 | * The busfree required flag is honored at the end of |
2287 | * the message phases. We check it last in case we |
2288 | * had to send some other message that caused a busfree. |
2289 | */ |
2290 | if (printerror != 0 |
2291 | && (lastphase == P_MESGIN || lastphase == P_MESGOUT) |
2292 | && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) { |
2293 | |
2294 | ahd_freeze_devq(ahd, scb); |
2295 | ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); |
2296 | ahd_freeze_scb(scb); |
2297 | if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) { |
2298 | ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), |
2299 | SCB_GET_CHANNEL(ahd, scb), |
2300 | SCB_GET_LUN(scb), SCB_LIST_NULL, |
2301 | ROLE_INITIATOR, CAM_REQ_ABORTED); |
2302 | } else { |
2303 | #ifdef AHD_DEBUG |
2304 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) |
2305 | printf("PPR Negotiation Busfree.\n" ); |
2306 | #endif |
2307 | ahd_done(ahd, scb); |
2308 | } |
2309 | printerror = 0; |
2310 | } |
2311 | if (printerror != 0) { |
2312 | int aborted; |
2313 | |
2314 | aborted = 0; |
2315 | if (scb != NULL) { |
2316 | u_int tag; |
2317 | |
2318 | if ((scb->hscb->control & TAG_ENB) != 0) |
2319 | tag = SCB_GET_TAG(scb); |
2320 | else |
2321 | tag = SCB_LIST_NULL; |
2322 | ahd_print_path(ahd, scb); |
2323 | aborted = ahd_abort_scbs(ahd, target, 'A', |
2324 | SCB_GET_LUN(scb), tag, |
2325 | ROLE_INITIATOR, |
2326 | CAM_UNEXP_BUSFREE); |
2327 | } else { |
2328 | /* |
2329 | * We had not fully identified this connection, |
2330 | * so we cannot abort anything. |
2331 | */ |
2332 | printf("%s: " , ahd_name(ahd)); |
2333 | } |
2334 | if (lastphase != P_BUSFREE) |
2335 | ahd_force_renegotiation(ahd, &devinfo); |
2336 | printf("Unexpected busfree %s, %d SCBs aborted, " |
2337 | "PRGMCNT == 0x%x\n" , |
2338 | ahd_lookup_phase_entry(lastphase)->phasemsg, |
2339 | aborted, |
2340 | ahd_inb(ahd, PRGMCNT) |
2341 | | (ahd_inb(ahd, PRGMCNT+1) << 8)); |
2342 | ahd_dump_card_state(ahd); |
2343 | } |
2344 | /* Always restart the sequencer. */ |
2345 | return (1); |
2346 | } |
2347 | |
2348 | static void |
2349 | ahd_handle_proto_violation(struct ahd_softc *ahd) |
2350 | { |
2351 | struct ahd_devinfo devinfo; |
2352 | struct scb *scb; |
2353 | u_int scbid; |
2354 | u_int seq_flags; |
2355 | u_int curphase; |
2356 | u_int lastphase; |
2357 | int found; |
2358 | |
2359 | ahd_fetch_devinfo(ahd, &devinfo); |
2360 | scbid = ahd_get_scbptr(ahd); |
2361 | scb = ahd_lookup_scb(ahd, scbid); |
2362 | seq_flags = ahd_inb(ahd, SEQ_FLAGS); |
2363 | curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; |
2364 | lastphase = ahd_inb(ahd, LASTPHASE); |
2365 | if ((seq_flags & NOT_IDENTIFIED) != 0) { |
2366 | |
2367 | /* |
2368 | * The reconnecting target either did not send an |
2369 | * identify message, or did, but we didn't find an SCB |
2370 | * to match. |
2371 | */ |
2372 | ahd_print_devinfo(ahd, &devinfo); |
2373 | printf("Target did not send an IDENTIFY message. " |
2374 | "LASTPHASE = 0x%x.\n" , lastphase); |
2375 | scb = NULL; |
2376 | } else if (scb == NULL) { |
2377 | /* |
2378 | * We don't seem to have an SCB active for this |
2379 | * transaction. Print an error and reset the bus. |
2380 | */ |
2381 | ahd_print_devinfo(ahd, &devinfo); |
2382 | printf("No SCB found during protocol violation\n" ); |
2383 | goto proto_violation_reset; |
2384 | } else { |
2385 | ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL); |
2386 | if ((seq_flags & NO_CDB_SENT) != 0) { |
2387 | ahd_print_path(ahd, scb); |
2388 | printf("No or incomplete CDB sent to device.\n" ); |
2389 | } else if ((ahd_inb_scbram(ahd, SCB_CONTROL) |
2390 | & STATUS_RCVD) == 0) { |
2391 | /* |
2392 | * The target never bothered to provide status to |
2393 | * us prior to completing the command. Since we don't |
2394 | * know the disposition of this command, we must attempt |
2395 | * to abort it. Assert ATN and prepare to send an abort |
2396 | * message. |
2397 | */ |
2398 | ahd_print_path(ahd, scb); |
2399 | printf("Completed command without status.\n" ); |
2400 | } else { |
2401 | ahd_print_path(ahd, scb); |
2402 | printf("Unknown protocol violation.\n" ); |
2403 | ahd_dump_card_state(ahd); |
2404 | } |
2405 | } |
2406 | if ((lastphase & ~P_DATAIN_DT) == 0 |
2407 | || lastphase == P_COMMAND) { |
2408 | proto_violation_reset: |
2409 | /* |
2410 | * Target either went directly to data |
2411 | * phase or didn't respond to our ATN. |
2412 | * The only safe thing to do is to blow |
2413 | * it away with a bus reset. |
2414 | */ |
2415 | found = ahd_reset_channel(ahd, 'A', TRUE); |
2416 | printf("%s: Issued Channel %c Bus Reset. " |
2417 | "%d SCBs aborted\n" , ahd_name(ahd), 'A', found); |
2418 | } else { |
2419 | /* |
2420 | * Leave the selection hardware off in case |
2421 | * this abort attempt will affect yet to |
2422 | * be sent commands. |
2423 | */ |
2424 | ahd_outb(ahd, SCSISEQ0, |
2425 | ahd_inb(ahd, SCSISEQ0) & ~ENSELO); |
2426 | ahd_assert_atn(ahd); |
2427 | ahd_outb(ahd, MSG_OUT, HOST_MSG); |
2428 | if (scb == NULL) { |
2429 | ahd_print_devinfo(ahd, &devinfo); |
2430 | ahd->msgout_buf[0] = MSG_ABORT_TASK; |
2431 | ahd->msgout_len = 1; |
2432 | ahd->msgout_index = 0; |
2433 | ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; |
2434 | } else { |
2435 | ahd_print_path(ahd, scb); |
2436 | scb->flags |= SCB_ABORT; |
2437 | } |
2438 | printf("Protocol violation %s. Attempting to abort.\n" , |
2439 | ahd_lookup_phase_entry(curphase)->phasemsg); |
2440 | } |
2441 | } |
2442 | |
2443 | /* |
2444 | * Force renegotiation to occur the next time we initiate |
2445 | * a command to the current device. |
2446 | */ |
2447 | static void |
2448 | ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) |
2449 | { |
2450 | struct ahd_initiator_tinfo *targ_info; |
2451 | struct ahd_tmode_tstate *tstate; |
2452 | |
2453 | #ifdef AHD_DEBUG |
2454 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { |
2455 | ahd_print_devinfo(ahd, devinfo); |
2456 | printf("Forcing renegotiation\n" ); |
2457 | } |
2458 | #endif |
2459 | targ_info = ahd_fetch_transinfo(ahd, |
2460 | devinfo->channel, |
2461 | devinfo->our_scsiid, |
2462 | devinfo->target, |
2463 | &tstate); |
2464 | ahd_update_neg_request(ahd, devinfo, tstate, |
2465 | targ_info, AHD_NEG_IF_NON_ASYNC); |
2466 | } |
2467 | |
2468 | #define AHD_MAX_STEPS 2000 |
2469 | void |
2470 | ahd_clear_critical_section(struct ahd_softc *ahd) |
2471 | { |
2472 | ahd_mode_state saved_modes; |
2473 | int stepping; |
2474 | int steps; |
2475 | int first_instr; |
2476 | u_int simode0; |
2477 | u_int simode1; |
2478 | u_int simode3; |
2479 | u_int lqimode0; |
2480 | u_int lqimode1; |
2481 | u_int lqomode0; |
2482 | u_int lqomode1; |
2483 | |
2484 | if (ahd->num_critical_sections == 0) |
2485 | return; |
2486 | |
2487 | stepping = FALSE; |
2488 | steps = 0; |
2489 | first_instr = 0; |
2490 | simode0 = 0; |
2491 | simode1 = 0; |
2492 | simode3 = 0; |
2493 | lqimode0 = 0; |
2494 | lqimode1 = 0; |
2495 | lqomode0 = 0; |
2496 | lqomode1 = 0; |
2497 | saved_modes = ahd_save_modes(ahd); |
2498 | for (;;) { |
2499 | struct cs *cs; |
2500 | u_int seqaddr; |
2501 | u_int i; |
2502 | |
2503 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
2504 | seqaddr = ahd_inb(ahd, CURADDR) |
2505 | | (ahd_inb(ahd, CURADDR+1) << 8); |
2506 | |
2507 | cs = ahd->critical_sections; |
2508 | for (i = 0; i < ahd->num_critical_sections; i++, cs++) { |
2509 | |
2510 | if (cs->begin < seqaddr && cs->end >= seqaddr) |
2511 | break; |
2512 | } |
2513 | |
2514 | if (i == ahd->num_critical_sections) |
2515 | break; |
2516 | |
2517 | if (steps > AHD_MAX_STEPS) { |
2518 | printf("%s: Infinite loop in critical section\n" |
2519 | "%s: First Instruction 0x%x now 0x%x\n" , |
2520 | ahd_name(ahd), ahd_name(ahd), first_instr, |
2521 | seqaddr); |
2522 | ahd_dump_card_state(ahd); |
2523 | panic("critical section loop" ); |
2524 | } |
2525 | |
2526 | steps++; |
2527 | #ifdef AHD_DEBUG |
2528 | if ((ahd_debug & AHD_SHOW_MISC) != 0) |
2529 | printf("%s: Single stepping at 0x%x\n" , ahd_name(ahd), |
2530 | seqaddr); |
2531 | #endif |
2532 | if (stepping == FALSE) { |
2533 | |
2534 | first_instr = seqaddr; |
2535 | ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); |
2536 | simode0 = ahd_inb(ahd, SIMODE0); |
2537 | simode3 = ahd_inb(ahd, SIMODE3); |
2538 | lqimode0 = ahd_inb(ahd, LQIMODE0); |
2539 | lqimode1 = ahd_inb(ahd, LQIMODE1); |
2540 | lqomode0 = ahd_inb(ahd, LQOMODE0); |
2541 | lqomode1 = ahd_inb(ahd, LQOMODE1); |
2542 | ahd_outb(ahd, SIMODE0, 0); |
2543 | ahd_outb(ahd, SIMODE3, 0); |
2544 | ahd_outb(ahd, LQIMODE0, 0); |
2545 | ahd_outb(ahd, LQIMODE1, 0); |
2546 | ahd_outb(ahd, LQOMODE0, 0); |
2547 | ahd_outb(ahd, LQOMODE1, 0); |
2548 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
2549 | simode1 = ahd_inb(ahd, SIMODE1); |
2550 | /* |
2551 | * We don't clear ENBUSFREE. Unfortunately |
2552 | * we cannot re-enable busfree detection within |
2553 | * the current connection, so we must leave it |
2554 | * on while single stepping. |
2555 | */ |
2556 | ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE); |
2557 | ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP); |
2558 | stepping = TRUE; |
2559 | } |
2560 | ahd_outb(ahd, CLRSINT1, CLRBUSFREE); |
2561 | ahd_outb(ahd, CLRINT, CLRSCSIINT); |
2562 | ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); |
2563 | ahd_outb(ahd, HCNTRL, ahd->unpause); |
2564 | while (!ahd_is_paused(ahd)) |
2565 | ahd_delay(200); |
2566 | ahd_update_modes(ahd); |
2567 | } |
2568 | if (stepping) { |
2569 | ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); |
2570 | ahd_outb(ahd, SIMODE0, simode0); |
2571 | ahd_outb(ahd, SIMODE3, simode3); |
2572 | ahd_outb(ahd, LQIMODE0, lqimode0); |
2573 | ahd_outb(ahd, LQIMODE1, lqimode1); |
2574 | ahd_outb(ahd, LQOMODE0, lqomode0); |
2575 | ahd_outb(ahd, LQOMODE1, lqomode1); |
2576 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
2577 | ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP); |
2578 | ahd_outb(ahd, SIMODE1, simode1); |
2579 | /* |
2580 | * SCSIINT seems to glitch occassionally when |
2581 | * the interrupt masks are restored. Clear SCSIINT |
2582 | * one more time so that only persistent errors |
2583 | * are seen as a real interrupt. |
2584 | */ |
2585 | ahd_outb(ahd, CLRINT, CLRSCSIINT); |
2586 | } |
2587 | ahd_restore_modes(ahd, saved_modes); |
2588 | } |
2589 | |
2590 | /* |
2591 | * Clear any pending interrupt status. |
2592 | */ |
2593 | void |
2594 | ahd_clear_intstat(struct ahd_softc *ahd) |
2595 | { |
2596 | AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), |
2597 | ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); |
2598 | /* Clear any interrupt conditions this may have caused */ |
2599 | ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2 |
2600 | |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD); |
2601 | ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT |
2602 | |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI |
2603 | |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ); |
2604 | ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ |
2605 | |CLRLQOATNPKT|CLRLQOTCRC); |
2606 | ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS |
2607 | |CLRLQOBUSFREE|CLRLQOPHACHGINPKT); |
2608 | if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { |
2609 | ahd_outb(ahd, CLRLQOINT0, 0); |
2610 | ahd_outb(ahd, CLRLQOINT1, 0); |
2611 | } |
2612 | ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR); |
2613 | ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI |
2614 | |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT); |
2615 | ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO |
2616 | |CLRIOERR|CLROVERRUN); |
2617 | ahd_outb(ahd, CLRINT, CLRSCSIINT); |
2618 | } |
2619 | |
2620 | /**************************** Debugging Routines ******************************/ |
2621 | #ifdef AHD_DEBUG |
2622 | uint32_t ahd_debug = AHD_DEBUG_OPTS; |
2623 | #endif |
2624 | void |
2625 | ahd_print_scb(struct scb *scb) |
2626 | { |
2627 | struct hardware_scb *hscb; |
2628 | int i; |
2629 | |
2630 | hscb = scb->hscb; |
2631 | printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n" , |
2632 | (void *)scb, |
2633 | hscb->control, |
2634 | hscb->scsiid, |
2635 | hscb->lun, |
2636 | hscb->cdb_len); |
2637 | printf("Shared Data: " ); |
2638 | for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++) |
2639 | printf("%#02x" , hscb->shared_data.idata.cdb[i]); |
2640 | printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n" , |
2641 | (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF), |
2642 | (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF), |
2643 | ahd_le32toh(hscb->datacnt), |
2644 | ahd_le32toh(hscb->sgptr), |
2645 | SCB_GET_TAG(scb)); |
2646 | ahd_dump_sglist(scb); |
2647 | } |
2648 | |
2649 | void |
2650 | ahd_dump_sglist(struct scb *scb) |
2651 | { |
2652 | int i; |
2653 | |
2654 | if (scb->sg_count > 0) { |
2655 | if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) { |
2656 | struct ahd_dma64_seg *sg_list; |
2657 | |
2658 | sg_list = (struct ahd_dma64_seg*)scb->sg_list; |
2659 | for (i = 0; i < scb->sg_count; i++) { |
2660 | uint64_t addr; |
2661 | |
2662 | addr = ahd_le64toh(sg_list[i].addr); |
2663 | printf("sg[%d] - Addr 0x%x%x : Length %d%s\n" , |
2664 | i, |
2665 | (uint32_t)((addr >> 32) & 0xFFFFFFFF), |
2666 | (uint32_t)(addr & 0xFFFFFFFF), |
2667 | sg_list[i].len & AHD_SG_LEN_MASK, |
2668 | (sg_list[i].len & AHD_DMA_LAST_SEG) |
2669 | ? " Last" : "" ); |
2670 | } |
2671 | } else { |
2672 | struct ahd_dma_seg *sg_list; |
2673 | |
2674 | sg_list = (struct ahd_dma_seg*)scb->sg_list; |
2675 | for (i = 0; i < scb->sg_count; i++) { |
2676 | uint32_t len; |
2677 | |
2678 | len = ahd_le32toh(sg_list[i].len); |
2679 | printf("sg[%d] - Addr 0x%x%x : Length %d%s\n" , |
2680 | i, |
2681 | (len & AHD_SG_HIGH_ADDR_MASK) >> 24, |
2682 | ahd_le32toh(sg_list[i].addr), |
2683 | len & AHD_SG_LEN_MASK, |
2684 | len & AHD_DMA_LAST_SEG ? " Last" : "" ); |
2685 | } |
2686 | } |
2687 | } |
2688 | } |
2689 | |
2690 | /************************* Transfer Negotiation *******************************/ |
2691 | /* |
2692 | * Allocate per target mode instance (ID we respond to as a target) |
2693 | * transfer negotiation data structures. |
2694 | */ |
2695 | static struct ahd_tmode_tstate * |
2696 | ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel) |
2697 | { |
2698 | struct ahd_tmode_tstate *master_tstate; |
2699 | struct ahd_tmode_tstate *tstate; |
2700 | int i; |
2701 | |
2702 | master_tstate = ahd->enabled_targets[ahd->our_id]; |
2703 | if (ahd->enabled_targets[scsi_id] != NULL |
2704 | && ahd->enabled_targets[scsi_id] != master_tstate) |
2705 | panic("%s: ahd_alloc_tstate - Target already allocated" , |
2706 | ahd_name(ahd)); |
2707 | tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT | M_ZERO); |
2708 | if (tstate == NULL) |
2709 | return (NULL); |
2710 | |
2711 | /* |
2712 | * If we have allocated a master tstate, copy user settings from |
2713 | * the master tstate (taken from SRAM or the EEPROM) for this |
2714 | * channel, but reset our current and goal settings to async/narrow |
2715 | * until an initiator talks to us. |
2716 | */ |
2717 | if (master_tstate != NULL) { |
2718 | memcpy(tstate, master_tstate, sizeof(*tstate)); |
2719 | memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); |
2720 | for (i = 0; i < 16; i++) { |
2721 | memset(&tstate->transinfo[i].curr, 0, |
2722 | sizeof(tstate->transinfo[i].curr)); |
2723 | memset(&tstate->transinfo[i].goal, 0, |
2724 | sizeof(tstate->transinfo[i].goal)); |
2725 | } |
2726 | } else |
2727 | memset(tstate, 0, sizeof(*tstate)); |
2728 | ahd->enabled_targets[scsi_id] = tstate; |
2729 | return (tstate); |
2730 | } |
2731 | |
2732 | #ifdef AHD_TARGET_MODE |
2733 | /* |
2734 | * Free per target mode instance (ID we respond to as a target) |
2735 | * transfer negotiation data structures. |
2736 | */ |
2737 | static void |
2738 | ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force) |
2739 | { |
2740 | struct ahd_tmode_tstate *tstate; |
2741 | |
2742 | /* |
2743 | * Don't clean up our "master" tstate. |
2744 | * It has our default user settings. |
2745 | */ |
2746 | if (scsi_id == ahd->our_id |
2747 | && force == FALSE) |
2748 | return; |
2749 | |
2750 | tstate = ahd->enabled_targets[scsi_id]; |
2751 | if (tstate != NULL) |
2752 | free(tstate, M_DEVBUF); |
2753 | ahd->enabled_targets[scsi_id] = NULL; |
2754 | } |
2755 | #endif |
2756 | |
2757 | /* |
2758 | * Called when we have an active connection to a target on the bus, |
2759 | * this function finds the nearest period to the input period limited |
2760 | * by the capabilities of the bus connectivity of and sync settings for |
2761 | * the target. |
2762 | */ |
2763 | void |
2764 | ahd_devlimited_syncrate(struct ahd_softc *ahd, |
2765 | struct ahd_initiator_tinfo *tinfo, |
2766 | u_int *period, u_int *ppr_options, role_t role) |
2767 | { |
2768 | struct ahd_transinfo *transinfo; |
2769 | u_int maxsync; |
2770 | |
2771 | if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0 |
2772 | && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) { |
2773 | maxsync = AHD_SYNCRATE_PACED; |
2774 | } else { |
2775 | maxsync = AHD_SYNCRATE_ULTRA; |
2776 | /* Can't do DT related options on an SE bus */ |
2777 | *ppr_options &= MSG_EXT_PPR_QAS_REQ; |
2778 | } |
2779 | /* |
2780 | * Never allow a value higher than our current goal |
2781 | * period otherwise we may allow a target initiated |
2782 | * negotiation to go above the limit as set by the |
2783 | * user. In the case of an initiator initiated |
2784 | * sync negotiation, we limit based on the user |
2785 | * setting. This allows the system to still accept |
2786 | * incoming negotiations even if target initiated |
2787 | * negotiation is not performed. |
2788 | */ |
2789 | if (role == ROLE_TARGET) |
2790 | transinfo = &tinfo->user; |
2791 | else |
2792 | transinfo = &tinfo->goal; |
2793 | *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN); |
2794 | if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { |
2795 | maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2); |
2796 | *ppr_options &= ~MSG_EXT_PPR_DT_REQ; |
2797 | } |
2798 | if (transinfo->period == 0) { |
2799 | *period = 0; |
2800 | *ppr_options = 0; |
2801 | } else { |
2802 | *period = MAX(*period, transinfo->period); |
2803 | ahd_find_syncrate(ahd, period, ppr_options, maxsync); |
2804 | } |
2805 | } |
2806 | |
2807 | /* |
2808 | * Look up the valid period to SCSIRATE conversion in our table. |
2809 | * Return the period and offset that should be sent to the target |
2810 | * if this was the beginning of an SDTR. |
2811 | */ |
2812 | void |
2813 | ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, |
2814 | u_int *ppr_options, u_int maxsync) |
2815 | { |
2816 | if (*period < maxsync) |
2817 | *period = maxsync; |
2818 | |
2819 | if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0 |
2820 | && *period > AHD_SYNCRATE_MIN_DT) |
2821 | *ppr_options &= ~MSG_EXT_PPR_DT_REQ; |
2822 | |
2823 | if (*period > AHD_SYNCRATE_MIN) |
2824 | *period = 0; |
2825 | |
2826 | /* Honor PPR option conformance rules. */ |
2827 | if (*period > AHD_SYNCRATE_PACED) |
2828 | *ppr_options &= ~MSG_EXT_PPR_RTI; |
2829 | |
2830 | if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0) |
2831 | *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ); |
2832 | |
2833 | if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0) |
2834 | *ppr_options &= MSG_EXT_PPR_QAS_REQ; |
2835 | |
2836 | /* Skip all PACED only entries if IU is not available */ |
2837 | if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0 |
2838 | && *period < AHD_SYNCRATE_DT) |
2839 | *period = AHD_SYNCRATE_DT; |
2840 | |
2841 | /* Skip all DT only entries if DT is not available */ |
2842 | if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 |
2843 | && *period < AHD_SYNCRATE_ULTRA2) |
2844 | *period = AHD_SYNCRATE_ULTRA2; |
2845 | } |
2846 | |
2847 | /* |
2848 | * Truncate the given synchronous offset to a value the |
2849 | * current adapter type and syncrate are capable of. |
2850 | */ |
2851 | void |
2852 | ahd_validate_offset(struct ahd_softc *ahd, |
2853 | struct ahd_initiator_tinfo *tinfo, |
2854 | u_int period, u_int *offset, int wide, |
2855 | role_t role) |
2856 | { |
2857 | u_int maxoffset; |
2858 | |
2859 | /* Limit offset to what we can do */ |
2860 | if (period == 0) |
2861 | maxoffset = 0; |
2862 | else if (period <= AHD_SYNCRATE_PACED) { |
2863 | if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) |
2864 | maxoffset = MAX_OFFSET_PACED_BUG; |
2865 | else |
2866 | maxoffset = MAX_OFFSET_PACED; |
2867 | } else |
2868 | maxoffset = MAX_OFFSET_NON_PACED; |
2869 | *offset = MIN(*offset, maxoffset); |
2870 | if (tinfo != NULL) { |
2871 | if (role == ROLE_TARGET) |
2872 | *offset = MIN(*offset, tinfo->user.offset); |
2873 | else |
2874 | *offset = MIN(*offset, tinfo->goal.offset); |
2875 | } |
2876 | } |
2877 | |
2878 | /* |
2879 | * Truncate the given transfer width parameter to a value the |
2880 | * current adapter type is capable of. |
2881 | */ |
2882 | void |
2883 | ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo, |
2884 | u_int *bus_width, role_t role) |
2885 | { |
2886 | switch (*bus_width) { |
2887 | default: |
2888 | if (ahd->features & AHD_WIDE) { |
2889 | /* Respond Wide */ |
2890 | *bus_width = MSG_EXT_WDTR_BUS_16_BIT; |
2891 | break; |
2892 | } |
2893 | /* FALLTHROUGH */ |
2894 | case MSG_EXT_WDTR_BUS_8_BIT: |
2895 | *bus_width = MSG_EXT_WDTR_BUS_8_BIT; |
2896 | break; |
2897 | } |
2898 | if (tinfo != NULL) { |
2899 | if (role == ROLE_TARGET) |
2900 | *bus_width = MIN(tinfo->user.width, *bus_width); |
2901 | else |
2902 | *bus_width = MIN(tinfo->goal.width, *bus_width); |
2903 | } |
2904 | } |
2905 | |
2906 | /* |
2907 | * Update the bitmask of targets for which the controller should |
2908 | * negotiate with at the next convenient opportunity. This currently |
2909 | * means the next time we send the initial identify messages for |
2910 | * a new transaction. |
2911 | */ |
2912 | int |
2913 | ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, |
2914 | struct ahd_tmode_tstate *tstate, |
2915 | struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type) |
2916 | { |
2917 | u_int auto_negotiate_orig; |
2918 | |
2919 | auto_negotiate_orig = tstate->auto_negotiate; |
2920 | if (neg_type == AHD_NEG_ALWAYS) { |
2921 | /* |
2922 | * Force our "current" settings to be |
2923 | * unknown so that unless a bus reset |
2924 | * occurs the need to renegotiate is |
2925 | * recorded persistently. |
2926 | */ |
2927 | if ((ahd->features & AHD_WIDE) != 0) |
2928 | tinfo->curr.width = AHD_WIDTH_UNKNOWN; |
2929 | tinfo->curr.period = AHD_PERIOD_UNKNOWN; |
2930 | tinfo->curr.offset = AHD_OFFSET_UNKNOWN; |
2931 | } |
2932 | if (tinfo->curr.period != tinfo->goal.period |
2933 | || tinfo->curr.width != tinfo->goal.width |
2934 | || tinfo->curr.offset != tinfo->goal.offset |
2935 | || tinfo->curr.ppr_options != tinfo->goal.ppr_options |
2936 | || (neg_type == AHD_NEG_IF_NON_ASYNC |
2937 | && (tinfo->goal.offset != 0 |
2938 | || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT |
2939 | || tinfo->goal.ppr_options != 0))) |
2940 | tstate->auto_negotiate |= devinfo->target_mask; |
2941 | else |
2942 | tstate->auto_negotiate &= ~devinfo->target_mask; |
2943 | |
2944 | return (auto_negotiate_orig != tstate->auto_negotiate); |
2945 | } |
2946 | |
2947 | /* |
2948 | * Update the user/goal/curr tables of synchronous negotiation |
2949 | * parameters as well as, in the case of a current or active update, |
2950 | * any data structures on the host controller. In the case of an |
2951 | * active update, the specified target is currently talking to us on |
2952 | * the bus, so the transfer parameter update must take effect |
2953 | * immediately. |
2954 | */ |
2955 | void |
2956 | ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, |
2957 | u_int period, u_int offset, u_int ppr_options, |
2958 | u_int type, int paused) |
2959 | { |
2960 | struct ahd_initiator_tinfo *tinfo; |
2961 | struct ahd_tmode_tstate *tstate; |
2962 | u_int old_period; |
2963 | u_int old_offset; |
2964 | u_int old_ppr; |
2965 | int active; |
2966 | int update_needed; |
2967 | |
2968 | active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; |
2969 | update_needed = 0; |
2970 | |
2971 | if (period == 0 || offset == 0) { |
2972 | period = 0; |
2973 | offset = 0; |
2974 | } |
2975 | |
2976 | tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, |
2977 | devinfo->target, &tstate); |
2978 | |
2979 | if ((type & AHD_TRANS_USER) != 0) { |
2980 | tinfo->user.period = period; |
2981 | tinfo->user.offset = offset; |
2982 | tinfo->user.ppr_options = ppr_options; |
2983 | } |
2984 | |
2985 | if ((type & AHD_TRANS_GOAL) != 0) { |
2986 | tinfo->goal.period = period; |
2987 | tinfo->goal.offset = offset; |
2988 | tinfo->goal.ppr_options = ppr_options; |
2989 | } |
2990 | |
2991 | old_period = tinfo->curr.period; |
2992 | old_offset = tinfo->curr.offset; |
2993 | old_ppr = tinfo->curr.ppr_options; |
2994 | |
2995 | if ((type & AHD_TRANS_CUR) != 0 |
2996 | && (old_period != period |
2997 | || old_offset != offset |
2998 | || old_ppr != ppr_options)) { |
2999 | |
3000 | update_needed++; |
3001 | |
3002 | tinfo->curr.period = period; |
3003 | tinfo->curr.offset = offset; |
3004 | tinfo->curr.ppr_options = ppr_options; |
3005 | |
3006 | ahd_send_async(ahd, devinfo->channel, devinfo->target, |
3007 | CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); |
3008 | |
3009 | if (bootverbose) { |
3010 | if (offset != 0) { |
3011 | int options; |
3012 | |
3013 | printf("%s: target %d synchronous with " |
3014 | "period = 0x%x, offset = 0x%x" , |
3015 | ahd_name(ahd), devinfo->target, |
3016 | period, offset); |
3017 | options = 0; |
3018 | if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) { |
3019 | printf("(RDSTRM" ); |
3020 | options++; |
3021 | } |
3022 | if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) { |
3023 | printf("%s" , options ? "|DT" : "(DT" ); |
3024 | options++; |
3025 | } |
3026 | if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) { |
3027 | printf("%s" , options ? "|IU" : "(IU" ); |
3028 | options++; |
3029 | } |
3030 | if ((ppr_options & MSG_EXT_PPR_RTI) != 0) { |
3031 | printf("%s" , options ? "|RTI" : "(RTI" ); |
3032 | options++; |
3033 | } |
3034 | if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) { |
3035 | printf("%s" , options ? "|QAS" : "(QAS" ); |
3036 | options++; |
3037 | } |
3038 | if (options != 0) |
3039 | printf(")\n" ); |
3040 | else |
3041 | printf("\n" ); |
3042 | } else { |
3043 | printf("%s: target %d using " |
3044 | "asynchronous transfers%s\n" , |
3045 | ahd_name(ahd), devinfo->target, |
3046 | (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0 |
3047 | ? "(QAS)" : "" ); |
3048 | } |
3049 | } |
3050 | } |
3051 | /* |
3052 | * Always refresh the neg-table to handle the case of the |
3053 | * sequencer setting the ENATNO bit for a MK_MESSAGE request. |
3054 | * We will always renegotiate in that case if this is a |
3055 | * packetized request. Also manage the busfree expected flag |
3056 | * from this common routine so that we catch changes due to |
3057 | * WDTR or SDTR messages. |
3058 | */ |
3059 | if ((type & AHD_TRANS_CUR) != 0) { |
3060 | if (!paused) |
3061 | ahd_pause(ahd); |
3062 | ahd_update_neg_table(ahd, devinfo, &tinfo->curr); |
3063 | if (!paused) |
3064 | ahd_unpause(ahd); |
3065 | if (ahd->msg_type != MSG_TYPE_NONE) { |
3066 | if ((old_ppr & MSG_EXT_PPR_IU_REQ) |
3067 | != (ppr_options & MSG_EXT_PPR_IU_REQ)) { |
3068 | #ifdef AHD_DEBUG |
3069 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { |
3070 | ahd_print_devinfo(ahd, devinfo); |
3071 | printf("Expecting IU Change busfree\n" ); |
3072 | } |
3073 | #endif |
3074 | ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE |
3075 | | MSG_FLAG_IU_REQ_CHANGED; |
3076 | } |
3077 | if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) { |
3078 | #ifdef AHD_DEBUG |
3079 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) |
3080 | printf("PPR with IU_REQ outstanding\n" ); |
3081 | #endif |
3082 | ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE; |
3083 | } |
3084 | } |
3085 | } |
3086 | |
3087 | update_needed += ahd_update_neg_request(ahd, devinfo, tstate, |
3088 | tinfo, AHD_NEG_TO_GOAL); |
3089 | |
3090 | if (update_needed && active) |
3091 | ahd_update_pending_scbs(ahd); |
3092 | } |
3093 | |
3094 | /* |
3095 | * Update the user/goal/curr tables of wide negotiation |
3096 | * parameters as well as, in the case of a current or active update, |
3097 | * any data structures on the host controller. In the case of an |
3098 | * active update, the specified target is currently talking to us on |
3099 | * the bus, so the transfer parameter update must take effect |
3100 | * immediately. |
3101 | */ |
3102 | void |
3103 | ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, |
3104 | u_int width, u_int type, int paused) |
3105 | { |
3106 | struct ahd_initiator_tinfo *tinfo; |
3107 | struct ahd_tmode_tstate *tstate; |
3108 | u_int oldwidth; |
3109 | int active; |
3110 | int update_needed; |
3111 | |
3112 | active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; |
3113 | update_needed = 0; |
3114 | tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, |
3115 | devinfo->target, &tstate); |
3116 | |
3117 | if ((type & AHD_TRANS_USER) != 0) |
3118 | tinfo->user.width = width; |
3119 | |
3120 | if ((type & AHD_TRANS_GOAL) != 0) |
3121 | tinfo->goal.width = width; |
3122 | |
3123 | oldwidth = tinfo->curr.width; |
3124 | if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) { |
3125 | |
3126 | update_needed++; |
3127 | |
3128 | tinfo->curr.width = width; |
3129 | ahd_send_async(ahd, devinfo->channel, devinfo->target, |
3130 | CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); |
3131 | |
3132 | if (bootverbose) { |
3133 | printf("%s: target %d using %dbit transfers\n" , |
3134 | ahd_name(ahd), devinfo->target, |
3135 | 8 * (0x01 << width)); |
3136 | } |
3137 | } |
3138 | |
3139 | if ((type & AHD_TRANS_CUR) != 0) { |
3140 | if (!paused) |
3141 | ahd_pause(ahd); |
3142 | ahd_update_neg_table(ahd, devinfo, &tinfo->curr); |
3143 | if (!paused) |
3144 | ahd_unpause(ahd); |
3145 | } |
3146 | |
3147 | update_needed += ahd_update_neg_request(ahd, devinfo, tstate, |
3148 | tinfo, AHD_NEG_TO_GOAL); |
3149 | if (update_needed && active) |
3150 | ahd_update_pending_scbs(ahd); |
3151 | |
3152 | } |
3153 | |
3154 | /* |
3155 | * Update the current state of tagged queuing for a given target. |
3156 | */ |
3157 | void |
3158 | ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, |
3159 | ahd_queue_alg alg) |
3160 | { |
3161 | ahd_platform_set_tags(ahd, devinfo, alg); |
3162 | ahd_send_async(ahd, devinfo->channel, devinfo->target, |
3163 | devinfo->lun, AC_TRANSFER_NEG, &alg); |
3164 | } |
3165 | |
3166 | static void |
3167 | ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, |
3168 | struct ahd_transinfo *tinfo) |
3169 | { |
3170 | ahd_mode_state saved_modes; |
3171 | u_int period; |
3172 | u_int ppr_opts; |
3173 | u_int con_opts; |
3174 | u_int offset; |
3175 | u_int saved_negoaddr; |
3176 | uint8_t iocell_opts[sizeof(ahd->iocell_opts)]; |
3177 | |
3178 | saved_modes = ahd_save_modes(ahd); |
3179 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
3180 | |
3181 | saved_negoaddr = ahd_inb(ahd, NEGOADDR); |
3182 | ahd_outb(ahd, NEGOADDR, devinfo->target); |
3183 | period = tinfo->period; |
3184 | offset = tinfo->offset; |
3185 | memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts)); |
3186 | ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ |
3187 | |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI); |
3188 | con_opts = 0; |
3189 | if (period == 0) |
3190 | period = AHD_SYNCRATE_ASYNC; |
3191 | if (period == AHD_SYNCRATE_160) { |
3192 | |
3193 | if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { |
3194 | /* |
3195 | * When the SPI4 spec was finalized, PACE transfers |
3196 | * was not made a configurable option in the PPR |
3197 | * message. Instead it is assumed to be enabled for |
3198 | * any syncrate faster than 80MHz. Nevertheless, |
3199 | * Harpoon2A4 allows this to be configurable. |
3200 | * |
3201 | * Harpoon2A4 also assumes at most 2 data bytes per |
3202 | * negotiated REQ/ACK offset. Paced transfers take |
3203 | * 4, so we must adjust our offset. |
3204 | */ |
3205 | ppr_opts |= PPROPT_PACE; |
3206 | offset *= 2; |
3207 | |
3208 | /* |
3209 | * Harpoon2A assumed that there would be a |
3210 | * fallback rate between 160 MHz and 80 MHz, |
3211 | * so 7 is used as the period factor rather |
3212 | * than 8 for 160MHz. |
3213 | */ |
3214 | period = AHD_SYNCRATE_REVA_160; |
3215 | } |
3216 | if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0) |
3217 | iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= |
3218 | ~AHD_PRECOMP_MASK; |
3219 | } else { |
3220 | /* |
3221 | * Precomp should be disabled for non-paced transfers. |
3222 | */ |
3223 | iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; |
3224 | |
3225 | if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0 |
3226 | && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0) { |
3227 | /* |
3228 | * Slow down our CRC interval to be |
3229 | * compatible with devices that can't |
3230 | * handle a CRC at full speed. |
3231 | */ |
3232 | con_opts |= ENSLOWCRC; |
3233 | } |
3234 | } |
3235 | |
3236 | ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW); |
3237 | ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]); |
3238 | ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE); |
3239 | ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]); |
3240 | |
3241 | ahd_outb(ahd, NEGPERIOD, period); |
3242 | ahd_outb(ahd, NEGPPROPTS, ppr_opts); |
3243 | ahd_outb(ahd, NEGOFFSET, offset); |
3244 | |
3245 | if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT) |
3246 | con_opts |= WIDEXFER; |
3247 | |
3248 | /* |
3249 | * During packetized transfers, the target will |
3250 | * give us the opportunity to send command packets |
3251 | * without us asserting attention. |
3252 | */ |
3253 | if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0) |
3254 | con_opts |= ENAUTOATNO; |
3255 | ahd_outb(ahd, NEGCONOPTS, con_opts); |
3256 | ahd_outb(ahd, NEGOADDR, saved_negoaddr); |
3257 | ahd_restore_modes(ahd, saved_modes); |
3258 | } |
3259 | |
3260 | /* |
3261 | * When the transfer settings for a connection change, setup for |
3262 | * negotiation in pending SCBs to effect the change as quickly as |
3263 | * possible. We also cancel any negotiations that are scheduled |
3264 | * for inflight SCBs that have not been started yet. |
3265 | */ |
3266 | static void |
3267 | ahd_update_pending_scbs(struct ahd_softc *ahd) |
3268 | { |
3269 | struct scb *pending_scb; |
3270 | int pending_scb_count; |
3271 | u_int scb_tag; |
3272 | int paused; |
3273 | u_int saved_scbptr; |
3274 | ahd_mode_state saved_modes; |
3275 | |
3276 | /* |
3277 | * Traverse the pending SCB list and ensure that all of the |
3278 | * SCBs there have the proper settings. We can only safely |
3279 | * clear the negotiation required flag (setting requires the |
3280 | * execution queue to be modified) and this is only possible |
3281 | * if we are not already attempting to select out for this |
3282 | * SCB. For this reason, all callers only call this routine |
3283 | * if we are changing the negotiation settings for the currently |
3284 | * active transaction on the bus. |
3285 | */ |
3286 | pending_scb_count = 0; |
3287 | LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { |
3288 | struct ahd_devinfo devinfo; |
3289 | struct hardware_scb *pending_hscb; |
3290 | struct ahd_tmode_tstate *tstate; |
3291 | |
3292 | ahd_scb_devinfo(ahd, &devinfo, pending_scb); |
3293 | (void)ahd_fetch_transinfo(ahd, devinfo.channel, |
3294 | devinfo.our_scsiid, |
3295 | devinfo.target, &tstate); |
3296 | pending_hscb = pending_scb->hscb; |
3297 | if ((tstate->auto_negotiate & devinfo.target_mask) == 0 |
3298 | && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { |
3299 | pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; |
3300 | pending_hscb->control &= ~MK_MESSAGE; |
3301 | } |
3302 | ahd_sync_scb(ahd, pending_scb, |
3303 | BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
3304 | pending_scb_count++; |
3305 | } |
3306 | |
3307 | if (pending_scb_count == 0) |
3308 | return; |
3309 | |
3310 | if (ahd_is_paused(ahd)) { |
3311 | paused = 1; |
3312 | } else { |
3313 | paused = 0; |
3314 | ahd_pause(ahd); |
3315 | } |
3316 | |
3317 | /* |
3318 | * Force the sequencer to reinitialize the selection for |
3319 | * the command at the head of the execution queue if it |
3320 | * has already been setup. The negotiation changes may |
3321 | * effect whether we select-out with ATN. |
3322 | */ |
3323 | saved_modes = ahd_save_modes(ahd); |
3324 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
3325 | ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); |
3326 | saved_scbptr = ahd_get_scbptr(ahd); |
3327 | /* Ensure that the hscbs down on the card match the new information */ |
3328 | for (scb_tag = 0; scb_tag < ahd->scb_data.maxhscbs; scb_tag++) { |
3329 | struct hardware_scb *pending_hscb; |
3330 | u_int control; |
3331 | |
3332 | pending_scb = ahd_lookup_scb(ahd, scb_tag); |
3333 | if (pending_scb == NULL) |
3334 | continue; |
3335 | ahd_set_scbptr(ahd, scb_tag); |
3336 | pending_hscb = pending_scb->hscb; |
3337 | control = ahd_inb_scbram(ahd, SCB_CONTROL); |
3338 | control &= ~MK_MESSAGE; |
3339 | control |= pending_hscb->control & MK_MESSAGE; |
3340 | ahd_outb(ahd, SCB_CONTROL, control); |
3341 | } |
3342 | ahd_set_scbptr(ahd, saved_scbptr); |
3343 | ahd_restore_modes(ahd, saved_modes); |
3344 | |
3345 | if (paused == 0) |
3346 | ahd_unpause(ahd); |
3347 | } |
3348 | |
3349 | /**************************** Pathing Information *****************************/ |
3350 | static void |
3351 | ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) |
3352 | { |
3353 | ahd_mode_state saved_modes; |
3354 | u_int saved_scsiid; |
3355 | role_t role; |
3356 | int our_id; |
3357 | |
3358 | saved_modes = ahd_save_modes(ahd); |
3359 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
3360 | |
3361 | if (ahd_inb(ahd, SSTAT0) & TARGET) |
3362 | role = ROLE_TARGET; |
3363 | else |
3364 | role = ROLE_INITIATOR; |
3365 | |
3366 | if (role == ROLE_TARGET |
3367 | && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { |
3368 | /* We were selected, so pull our id from TARGIDIN */ |
3369 | our_id = ahd_inb(ahd, TARGIDIN) & OID; |
3370 | } else if (role == ROLE_TARGET) |
3371 | our_id = ahd_inb(ahd, TOWNID); |
3372 | else |
3373 | our_id = ahd_inb(ahd, IOWNID); |
3374 | |
3375 | saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); |
3376 | ahd_compile_devinfo(devinfo, |
3377 | our_id, |
3378 | SCSIID_TARGET(ahd, saved_scsiid), |
3379 | ahd_inb(ahd, SAVED_LUN), |
3380 | SCSIID_CHANNEL(ahd, saved_scsiid), |
3381 | role); |
3382 | ahd_restore_modes(ahd, saved_modes); |
3383 | } |
3384 | |
3385 | void |
3386 | ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) |
3387 | { |
3388 | printf("%s:%c:%d:%d: (0x%x) " , ahd_name(ahd), 'A', |
3389 | devinfo->target, devinfo->lun, ahd_get_scbptr(ahd)); |
3390 | } |
3391 | |
3392 | struct ahd_phase_table_entry* |
3393 | ahd_lookup_phase_entry(int phase) |
3394 | { |
3395 | struct ahd_phase_table_entry *entry; |
3396 | struct ahd_phase_table_entry *last_entry; |
3397 | |
3398 | /* |
3399 | * num_phases doesn't include the default entry which |
3400 | * will be returned if the phase doesn't match. |
3401 | */ |
3402 | last_entry = &ahd_phase_table[num_phases]; |
3403 | for (entry = ahd_phase_table; entry < last_entry; entry++) { |
3404 | if (phase == entry->phase) |
3405 | break; |
3406 | } |
3407 | return (entry); |
3408 | } |
3409 | |
3410 | void |
3411 | ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target, |
3412 | u_int lun, char channel, role_t role) |
3413 | { |
3414 | devinfo->our_scsiid = our_id; |
3415 | devinfo->target = target; |
3416 | devinfo->lun = lun; |
3417 | devinfo->target_offset = target; |
3418 | devinfo->channel = channel; |
3419 | devinfo->role = role; |
3420 | if (channel == 'B') |
3421 | devinfo->target_offset += 8; |
3422 | devinfo->target_mask = (0x01 << devinfo->target_offset); |
3423 | } |
3424 | |
3425 | static void |
3426 | ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, |
3427 | struct scb *scb) |
3428 | { |
3429 | role_t role; |
3430 | int our_id; |
3431 | |
3432 | our_id = SCSIID_OUR_ID(scb->hscb->scsiid); |
3433 | role = ROLE_INITIATOR; |
3434 | if ((scb->hscb->control & TARGET_SCB) != 0) |
3435 | role = ROLE_TARGET; |
3436 | ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb), |
3437 | SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role); |
3438 | } |
3439 | |
3440 | |
3441 | /************************ Message Phase Processing ****************************/ |
3442 | /* |
3443 | * When an initiator transaction with the MK_MESSAGE flag either reconnects |
3444 | * or enters the initial message out phase, we are interrupted. Fill our |
3445 | * outgoing message buffer with the appropriate message and begin handing |
3446 | * the message phase(s) manually. |
3447 | */ |
3448 | static void |
3449 | ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, |
3450 | struct scb *scb) |
3451 | { |
3452 | /* |
3453 | * To facilitate adding multiple messages together, |
3454 | * each routine should increment the index and len |
3455 | * variables instead of setting them explicitly. |
3456 | */ |
3457 | ahd->msgout_index = 0; |
3458 | ahd->msgout_len = 0; |
3459 | |
3460 | if (ahd_currently_packetized(ahd)) |
3461 | ahd->msg_flags |= MSG_FLAG_PACKETIZED; |
3462 | |
3463 | if (ahd->send_msg_perror |
3464 | && ahd_inb(ahd, MSG_OUT) == HOST_MSG) { |
3465 | ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror; |
3466 | ahd->msgout_len++; |
3467 | ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; |
3468 | #ifdef AHD_DEBUG |
3469 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) |
3470 | printf("Setting up for Parity Error delivery\n" ); |
3471 | #endif |
3472 | return; |
3473 | } else if (scb == NULL) { |
3474 | printf("%s: WARNING. No pending message for " |
3475 | "I_T msgin. Issuing NO-OP\n" , ahd_name(ahd)); |
3476 | ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP; |
3477 | ahd->msgout_len++; |
3478 | ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; |
3479 | return; |
3480 | } |
3481 | |
3482 | if ((scb->flags & SCB_DEVICE_RESET) == 0 |
3483 | && (scb->flags & SCB_PACKETIZED) == 0 |
3484 | && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) { |
3485 | u_int identify_msg; |
3486 | |
3487 | identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); |
3488 | if ((scb->hscb->control & DISCENB) != 0) |
3489 | identify_msg |= MSG_IDENTIFY_DISCFLAG; |
3490 | ahd->msgout_buf[ahd->msgout_index++] = identify_msg; |
3491 | ahd->msgout_len++; |
3492 | |
3493 | if ((scb->hscb->control & TAG_ENB) != 0) { |
3494 | ahd->msgout_buf[ahd->msgout_index++] = |
3495 | scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); |
3496 | ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb); |
3497 | ahd->msgout_len += 2; |
3498 | } |
3499 | } |
3500 | |
3501 | if (scb->flags & SCB_DEVICE_RESET) { |
3502 | ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET; |
3503 | ahd->msgout_len++; |
3504 | ahd_print_path(ahd, scb); |
3505 | printf("Bus Device Reset Message Sent\n" ); |
3506 | /* |
3507 | * Clear our selection hardware in advance of |
3508 | * the busfree. We may have an entry in the waiting |
3509 | * Q for this target, and we don't want to go about |
3510 | * selecting while we handle the busfree and blow it |
3511 | * away. |
3512 | */ |
3513 | ahd_outb(ahd, SCSISEQ0, 0); |
3514 | } else if ((scb->flags & SCB_ABORT) != 0) { |
3515 | |
3516 | if ((scb->hscb->control & TAG_ENB) != 0) { |
3517 | ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG; |
3518 | } else { |
3519 | ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT; |
3520 | } |
3521 | ahd->msgout_len++; |
3522 | ahd_print_path(ahd, scb); |
3523 | printf("Abort%s Message Sent\n" , |
3524 | (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "" ); |
3525 | /* |
3526 | * Clear our selection hardware in advance of |
3527 | * the busfree. We may have an entry in the waiting |
3528 | * Q for this target, and we don't want to go about |
3529 | * selecting while we handle the busfree and blow it |
3530 | * away. |
3531 | */ |
3532 | ahd_outb(ahd, SCSISEQ0, 0); |
3533 | } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { |
3534 | ahd_build_transfer_msg(ahd, devinfo); |
3535 | /* |
3536 | * Clear our selection hardware in advance of potential |
3537 | * PPR IU status change busfree. We may have an entry in |
3538 | * the waiting Q for this target, and we don't want to go |
3539 | * about selecting while we handle the busfree and blow |
3540 | * it away. |
3541 | */ |
3542 | ahd_outb(ahd, SCSISEQ0, 0); |
3543 | } else { |
3544 | printf("ahd_intr: AWAITING_MSG for an SCB that " |
3545 | "does not have a waiting message\n" ); |
3546 | printf("SCSIID = %x, target_mask = %x\n" , scb->hscb->scsiid, |
3547 | devinfo->target_mask); |
3548 | panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x " |
3549 | "SCB flags = %x" , SCB_GET_TAG(scb), scb->hscb->control, |
3550 | ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT), |
3551 | scb->flags); |
3552 | } |
3553 | |
3554 | /* |
3555 | * Clear the MK_MESSAGE flag from the SCB so we aren't |
3556 | * asked to send this message again. |
3557 | */ |
3558 | ahd_outb(ahd, SCB_CONTROL, |
3559 | ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); |
3560 | scb->hscb->control &= ~MK_MESSAGE; |
3561 | ahd->msgout_index = 0; |
3562 | ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; |
3563 | } |
3564 | |
3565 | /* |
3566 | * Build an appropriate transfer negotiation message for the |
3567 | * currently active target. |
3568 | */ |
3569 | static void |
3570 | ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) |
3571 | { |
3572 | /* |
3573 | * We need to initiate transfer negotiations. |
3574 | * If our current and goal settings are identical, |
3575 | * we want to renegotiate due to a check condition. |
3576 | */ |
3577 | struct ahd_initiator_tinfo *tinfo; |
3578 | struct ahd_tmode_tstate *tstate; |
3579 | int dowide; |
3580 | int dosync; |
3581 | int doppr; |
3582 | u_int period; |
3583 | u_int ppr_options; |
3584 | u_int offset; |
3585 | |
3586 | tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, |
3587 | devinfo->target, &tstate); |
3588 | /* |
3589 | * Filter our period based on the current connection. |
3590 | * If we can't perform DT transfers on this segment (not in LVD |
3591 | * mode for instance), then our decision to issue a PPR message |
3592 | * may change. |
3593 | */ |
3594 | period = tinfo->goal.period; |
3595 | offset = tinfo->goal.offset; |
3596 | ppr_options = tinfo->goal.ppr_options; |
3597 | /* Target initiated PPR is not allowed in the SCSI spec */ |
3598 | if (devinfo->role == ROLE_TARGET) |
3599 | ppr_options = 0; |
3600 | ahd_devlimited_syncrate(ahd, tinfo, &period, |
3601 | &ppr_options, devinfo->role); |
3602 | dowide = tinfo->curr.width != tinfo->goal.width; |
3603 | dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; |
3604 | /* |
3605 | * Only use PPR if we have options that need it, even if the device |
3606 | * claims to support it. There might be an expander in the way |
3607 | * that doesn't. |
3608 | */ |
3609 | doppr = ppr_options != 0; |
3610 | |
3611 | if (!dowide && !dosync && !doppr) { |
3612 | dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; |
3613 | dosync = tinfo->goal.offset != 0; |
3614 | } |
3615 | |
3616 | if (!dowide && !dosync && !doppr) { |
3617 | /* |
3618 | * Force async with a WDTR message if we have a wide bus, |
3619 | * or just issue an SDTR with a 0 offset. |
3620 | */ |
3621 | if ((ahd->features & AHD_WIDE) != 0) |
3622 | dowide = 1; |
3623 | else |
3624 | dosync = 1; |
3625 | |
3626 | if (bootverbose) { |
3627 | ahd_print_devinfo(ahd, devinfo); |
3628 | printf("Ensuring async\n" ); |
3629 | } |
3630 | } |
3631 | /* Target initiated PPR is not allowed in the SCSI spec */ |
3632 | if (devinfo->role == ROLE_TARGET) |
3633 | doppr = 0; |
3634 | |
3635 | /* |
3636 | * Both the PPR message and SDTR message require the |
3637 | * goal syncrate to be limited to what the target device |
3638 | * is capable of handling (based on whether an LVD->SE |
3639 | * expander is on the bus), so combine these two cases. |
3640 | * Regardless, guarantee that if we are using WDTR and SDTR |
3641 | * messages that WDTR comes first. |
3642 | */ |
3643 | if (doppr || (dosync && !dowide)) { |
3644 | |
3645 | offset = tinfo->goal.offset; |
3646 | ahd_validate_offset(ahd, tinfo, period, &offset, |
3647 | doppr ? tinfo->goal.width |
3648 | : tinfo->curr.width, |
3649 | devinfo->role); |
3650 | if (doppr) { |
3651 | ahd_construct_ppr(ahd, devinfo, period, offset, |
3652 | tinfo->goal.width, ppr_options); |
3653 | } else { |
3654 | ahd_construct_sdtr(ahd, devinfo, period, offset); |
3655 | } |
3656 | } else { |
3657 | ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width); |
3658 | } |
3659 | } |
3660 | |
3661 | /* |
3662 | * Build a synchronous negotiation message in our message |
3663 | * buffer based on the input parameters. |
3664 | */ |
3665 | static void |
3666 | ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, |
3667 | u_int period, u_int offset) |
3668 | { |
3669 | if (offset == 0) |
3670 | period = AHD_ASYNC_XFER_PERIOD; |
3671 | ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; |
3672 | ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN; |
3673 | ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR; |
3674 | ahd->msgout_buf[ahd->msgout_index++] = period; |
3675 | ahd->msgout_buf[ahd->msgout_index++] = offset; |
3676 | ahd->msgout_len += 5; |
3677 | if (bootverbose) { |
3678 | printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n" , |
3679 | ahd_name(ahd), devinfo->channel, devinfo->target, |
3680 | devinfo->lun, period, offset); |
3681 | } |
3682 | } |
3683 | |
3684 | /* |
3685 | * Build a wide negotiation message in our message |
3686 | * buffer based on the input parameters. |
3687 | */ |
3688 | static void |
3689 | ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, |
3690 | u_int bus_width) |
3691 | { |
3692 | ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; |
3693 | ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN; |
3694 | ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR; |
3695 | ahd->msgout_buf[ahd->msgout_index++] = bus_width; |
3696 | ahd->msgout_len += 4; |
3697 | if (bootverbose) { |
3698 | printf("(%s:%c:%d:%d): Sending WDTR %x\n" , |
3699 | ahd_name(ahd), devinfo->channel, devinfo->target, |
3700 | devinfo->lun, bus_width); |
3701 | } |
3702 | } |
3703 | |
3704 | /* |
3705 | * Build a parallel protocol request message in our message |
3706 | * buffer based on the input parameters. |
3707 | */ |
3708 | static void |
3709 | ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, |
3710 | u_int period, u_int offset, u_int bus_width, |
3711 | u_int ppr_options) |
3712 | { |
3713 | /* |
3714 | * Always request precompensation from |
3715 | * the other target if we are running |
3716 | * at paced syncrates. |
3717 | */ |
3718 | if (period <= AHD_SYNCRATE_PACED) |
3719 | ppr_options |= MSG_EXT_PPR_PCOMP_EN; |
3720 | if (offset == 0) |
3721 | period = AHD_ASYNC_XFER_PERIOD; |
3722 | ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; |
3723 | ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN; |
3724 | ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR; |
3725 | ahd->msgout_buf[ahd->msgout_index++] = period; |
3726 | ahd->msgout_buf[ahd->msgout_index++] = 0; |
3727 | ahd->msgout_buf[ahd->msgout_index++] = offset; |
3728 | ahd->msgout_buf[ahd->msgout_index++] = bus_width; |
3729 | ahd->msgout_buf[ahd->msgout_index++] = ppr_options; |
3730 | ahd->msgout_len += 8; |
3731 | if (bootverbose) { |
3732 | printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period 0x%x, " |
3733 | "offset 0x%x, ppr_options 0x%x\n" , ahd_name(ahd), |
3734 | devinfo->channel, devinfo->target, devinfo->lun, |
3735 | bus_width, period, offset, ppr_options); |
3736 | } |
3737 | } |
3738 | |
3739 | /* |
3740 | * Clear any active message state. |
3741 | */ |
3742 | static void |
3743 | ahd_clear_msg_state(struct ahd_softc *ahd) |
3744 | { |
3745 | ahd_mode_state saved_modes; |
3746 | |
3747 | saved_modes = ahd_save_modes(ahd); |
3748 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
3749 | ahd->send_msg_perror = 0; |
3750 | ahd->msg_flags = MSG_FLAG_NONE; |
3751 | ahd->msgout_len = 0; |
3752 | ahd->msgin_index = 0; |
3753 | ahd->msg_type = MSG_TYPE_NONE; |
3754 | if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { |
3755 | /* |
3756 | * The target didn't care to respond to our |
3757 | * message request, so clear ATN. |
3758 | */ |
3759 | ahd_outb(ahd, CLRSINT1, CLRATNO); |
3760 | } |
3761 | ahd_outb(ahd, MSG_OUT, MSG_NOOP); |
3762 | ahd_outb(ahd, SEQ_FLAGS2, |
3763 | ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); |
3764 | ahd_restore_modes(ahd, saved_modes); |
3765 | } |
3766 | |
3767 | /* |
3768 | * Manual message loop handler. |
3769 | */ |
3770 | static void |
3771 | ahd_handle_message_phase(struct ahd_softc *ahd) |
3772 | { |
3773 | struct ahd_devinfo devinfo; |
3774 | u_int bus_phase; |
3775 | int end_session; |
3776 | |
3777 | ahd_fetch_devinfo(ahd, &devinfo); |
3778 | end_session = FALSE; |
3779 | bus_phase = ahd_inb(ahd, LASTPHASE); |
3780 | |
3781 | if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) { |
3782 | printf("LQIRETRY for LQIPHASE_OUTPKT\n" ); |
3783 | ahd_outb(ahd, LQCTL2, LQIRETRY); |
3784 | } |
3785 | reswitch: |
3786 | switch (ahd->msg_type) { |
3787 | case MSG_TYPE_INITIATOR_MSGOUT: |
3788 | { |
3789 | int lastbyte; |
3790 | int phasemis; |
3791 | int msgdone; |
3792 | |
3793 | if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0) |
3794 | panic("HOST_MSG_LOOP interrupt with no active message" ); |
3795 | |
3796 | #ifdef AHD_DEBUG |
3797 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { |
3798 | ahd_print_devinfo(ahd, &devinfo); |
3799 | printf("INITIATOR_MSG_OUT" ); |
3800 | } |
3801 | #endif |
3802 | phasemis = bus_phase != P_MESGOUT; |
3803 | if (phasemis) { |
3804 | #ifdef AHD_DEBUG |
3805 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { |
3806 | printf(" PHASEMIS %s\n" , |
3807 | ahd_lookup_phase_entry(bus_phase) |
3808 | ->phasemsg); |
3809 | } |
3810 | #endif |
3811 | if (bus_phase == P_MESGIN) { |
3812 | /* |
3813 | * Change gears and see if |
3814 | * this messages is of interest to |
3815 | * us or should be passed back to |
3816 | * the sequencer. |
3817 | */ |
3818 | ahd_outb(ahd, CLRSINT1, CLRATNO); |
3819 | ahd->send_msg_perror = 0; |
3820 | ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN; |
3821 | ahd->msgin_index = 0; |
3822 | goto reswitch; |
3823 | } |
3824 | end_session = TRUE; |
3825 | break; |
3826 | } |
3827 | |
3828 | if (ahd->send_msg_perror) { |
3829 | ahd_outb(ahd, CLRSINT1, CLRATNO); |
3830 | ahd_outb(ahd, CLRSINT1, CLRREQINIT); |
3831 | #ifdef AHD_DEBUG |
3832 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) |
3833 | printf(" byte 0x%x\n" , ahd->send_msg_perror); |
3834 | #endif |
3835 | /* |
3836 | * If we are notifying the target of a CRC error |
3837 | * during packetized operations, the target is |
3838 | * within its rights to acknowledge our message |
3839 | * with a busfree. |
3840 | */ |
3841 | if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0 |
3842 | && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR) |
3843 | ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE; |
3844 | |
3845 | ahd_outb(ahd, RETURN_2, ahd->send_msg_perror); |
3846 | ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); |
3847 | break; |
3848 | } |
3849 | |
3850 | msgdone = ahd->msgout_index == ahd->msgout_len; |
3851 | if (msgdone) { |
3852 | /* |
3853 | * The target has requested a retry. |
3854 | * Re-assert ATN, reset our message index to |
3855 | * 0, and try again. |
3856 | */ |
3857 | ahd->msgout_index = 0; |
3858 | ahd_assert_atn(ahd); |
3859 | } |
3860 | |
3861 | lastbyte = ahd->msgout_index == (ahd->msgout_len - 1); |
3862 | if (lastbyte) { |
3863 | /* Last byte is signified by dropping ATN */ |
3864 | ahd_outb(ahd, CLRSINT1, CLRATNO); |
3865 | } |
3866 | |
3867 | /* |
3868 | * Clear our interrupt status and present |
3869 | * the next byte on the bus. |
3870 | */ |
3871 | ahd_outb(ahd, CLRSINT1, CLRREQINIT); |
3872 | #ifdef AHD_DEBUG |
3873 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) |
3874 | printf(" byte 0x%x\n" , |
3875 | ahd->msgout_buf[ahd->msgout_index]); |
3876 | #endif |
3877 | ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]); |
3878 | ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); |
3879 | break; |
3880 | } |
3881 | case MSG_TYPE_INITIATOR_MSGIN: |
3882 | { |
3883 | int phasemis; |
3884 | int message_done; |
3885 | |
3886 | #ifdef AHD_DEBUG |
3887 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { |
3888 | ahd_print_devinfo(ahd, &devinfo); |
3889 | printf("INITIATOR_MSG_IN" ); |
3890 | } |
3891 | #endif |
3892 | phasemis = bus_phase != P_MESGIN; |
3893 | if (phasemis) { |
3894 | #ifdef AHD_DEBUG |
3895 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { |
3896 | printf(" PHASEMIS %s\n" , |
3897 | ahd_lookup_phase_entry(bus_phase) |
3898 | ->phasemsg); |
3899 | } |
3900 | #endif |
3901 | ahd->msgin_index = 0; |
3902 | if (bus_phase == P_MESGOUT |
3903 | && (ahd->send_msg_perror != 0 |
3904 | || (ahd->msgout_len != 0 |
3905 | && ahd->msgout_index == 0))) { |
3906 | ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; |
3907 | goto reswitch; |
3908 | } |
3909 | end_session = TRUE; |
3910 | break; |
3911 | } |
3912 | |
3913 | /* Pull the byte in without acking it */ |
3914 | ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS); |
3915 | #ifdef AHD_DEBUG |
3916 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) |
3917 | printf(" byte 0x%x\n" , |
3918 | ahd->msgin_buf[ahd->msgin_index]); |
3919 | #endif |
3920 | |
3921 | message_done = ahd_parse_msg(ahd, &devinfo); |
3922 | |
3923 | if (message_done) { |
3924 | /* |
3925 | * Clear our incoming message buffer in case there |
3926 | * is another message following this one. |
3927 | */ |
3928 | ahd->msgin_index = 0; |
3929 | |
3930 | /* |
3931 | * If this message illicited a response, |
3932 | * assert ATN so the target takes us to the |
3933 | * message out phase. |
3934 | */ |
3935 | if (ahd->msgout_len != 0) { |
3936 | #ifdef AHD_DEBUG |
3937 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { |
3938 | ahd_print_devinfo(ahd, &devinfo); |
3939 | printf("Asserting ATN for response\n" ); |
3940 | } |
3941 | #endif |
3942 | ahd_assert_atn(ahd); |
3943 | } |
3944 | } else |
3945 | ahd->msgin_index++; |
3946 | |
3947 | if (message_done == MSGLOOP_TERMINATED) { |
3948 | end_session = TRUE; |
3949 | } else { |
3950 | /* Ack the byte */ |
3951 | ahd_outb(ahd, CLRSINT1, CLRREQINIT); |
3952 | ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ); |
3953 | } |
3954 | break; |
3955 | } |
3956 | case MSG_TYPE_TARGET_MSGIN: |
3957 | { |
3958 | int msgdone; |
3959 | int msgout_request; |
3960 | |
3961 | /* |
3962 | * By default, the message loop will continue. |
3963 | */ |
3964 | ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); |
3965 | |
3966 | if (ahd->msgout_len == 0) |
3967 | panic("Target MSGIN with no active message" ); |
3968 | |
3969 | /* |
3970 | * If we interrupted a mesgout session, the initiator |
3971 | * will not know this until our first REQ. So, we |
3972 | * only honor mesgout requests after we've sent our |
3973 | * first byte. |
3974 | */ |
3975 | if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0 |
3976 | && ahd->msgout_index > 0) |
3977 | msgout_request = TRUE; |
3978 | else |
3979 | msgout_request = FALSE; |
3980 | |
3981 | if (msgout_request) { |
3982 | |
3983 | /* |
3984 | * Change gears and see if |
3985 | * this messages is of interest to |
3986 | * us or should be passed back to |
3987 | * the sequencer. |
3988 | */ |
3989 | ahd->msg_type = MSG_TYPE_TARGET_MSGOUT; |
3990 | ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO); |
3991 | ahd->msgin_index = 0; |
3992 | /* Dummy read to REQ for first byte */ |
3993 | ahd_inb(ahd, SCSIDAT); |
3994 | ahd_outb(ahd, SXFRCTL0, |
3995 | ahd_inb(ahd, SXFRCTL0) | SPIOEN); |
3996 | break; |
3997 | } |
3998 | |
3999 | msgdone = ahd->msgout_index == ahd->msgout_len; |
4000 | if (msgdone) { |
4001 | ahd_outb(ahd, SXFRCTL0, |
4002 | ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); |
4003 | end_session = TRUE; |
4004 | break; |
4005 | } |
4006 | |
4007 | /* |
4008 | * Present the next byte on the bus. |
4009 | */ |
4010 | ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN); |
4011 | ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]); |
4012 | break; |
4013 | } |
4014 | case MSG_TYPE_TARGET_MSGOUT: |
4015 | { |
4016 | int lastbyte; |
4017 | int msgdone; |
4018 | |
4019 | /* |
4020 | * By default, the message loop will continue. |
4021 | */ |
4022 | ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); |
4023 | |
4024 | /* |
4025 | * The initiator signals that this is |
4026 | * the last byte by dropping ATN. |
4027 | */ |
4028 | lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0; |
4029 | |
4030 | /* |
4031 | * Read the latched byte, but turn off SPIOEN first |
4032 | * so that we don't inadvertently cause a REQ for the |
4033 | * next byte. |
4034 | */ |
4035 | ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); |
4036 | ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT); |
4037 | msgdone = ahd_parse_msg(ahd, &devinfo); |
4038 | if (msgdone == MSGLOOP_TERMINATED) { |
4039 | /* |
4040 | * The message is *really* done in that it caused |
4041 | * us to go to bus free. The sequencer has already |
4042 | * been reset at this point, so pull the ejection |
4043 | * handle. |
4044 | */ |
4045 | return; |
4046 | } |
4047 | |
4048 | ahd->msgin_index++; |
4049 | |
4050 | /* |
4051 | * XXX Read spec about initiator dropping ATN too soon |
4052 | * and use msgdone to detect it. |
4053 | */ |
4054 | if (msgdone == MSGLOOP_MSGCOMPLETE) { |
4055 | ahd->msgin_index = 0; |
4056 | |
4057 | /* |
4058 | * If this message illicited a response, transition |
4059 | * to the Message in phase and send it. |
4060 | */ |
4061 | if (ahd->msgout_len != 0) { |
4062 | ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO); |
4063 | ahd_outb(ahd, SXFRCTL0, |
4064 | ahd_inb(ahd, SXFRCTL0) | SPIOEN); |
4065 | ahd->msg_type = MSG_TYPE_TARGET_MSGIN; |
4066 | ahd->msgin_index = 0; |
4067 | break; |
4068 | } |
4069 | } |
4070 | |
4071 | if (lastbyte) |
4072 | end_session = TRUE; |
4073 | else { |
4074 | /* Ask for the next byte. */ |
4075 | ahd_outb(ahd, SXFRCTL0, |
4076 | ahd_inb(ahd, SXFRCTL0) | SPIOEN); |
4077 | } |
4078 | |
4079 | break; |
4080 | } |
4081 | default: |
4082 | panic("Unknown REQINIT message type" ); |
4083 | } |
4084 | |
4085 | if (end_session) { |
4086 | if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) { |
4087 | printf("%s: Returning to Idle Loop\n" , |
4088 | ahd_name(ahd)); |
4089 | ahd_clear_msg_state(ahd); |
4090 | |
4091 | /* |
4092 | * Perform the equivalent of a clear_target_state. |
4093 | */ |
4094 | ahd_outb(ahd, LASTPHASE, P_BUSFREE); |
4095 | ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT); |
4096 | ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); |
4097 | } else { |
4098 | ahd_clear_msg_state(ahd); |
4099 | ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP); |
4100 | } |
4101 | } |
4102 | } |
4103 | |
4104 | /* |
4105 | * See if we sent a particular extended message to the target. |
4106 | * If "full" is true, return true only if the target saw the full |
4107 | * message. If "full" is false, return true if the target saw at |
4108 | * least the first byte of the message. |
4109 | */ |
4110 | static int |
4111 | ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full) |
4112 | { |
4113 | int found; |
4114 | u_int index; |
4115 | |
4116 | found = FALSE; |
4117 | index = 0; |
4118 | |
4119 | while (index < ahd->msgout_len) { |
4120 | if (ahd->msgout_buf[index] == MSG_EXTENDED) { |
4121 | u_int end_index; |
4122 | |
4123 | end_index = index + 1 + ahd->msgout_buf[index + 1]; |
4124 | if (ahd->msgout_buf[index+2] == msgval |
4125 | && type == AHDMSG_EXT) { |
4126 | |
4127 | if (full) { |
4128 | if (ahd->msgout_index > end_index) |
4129 | found = TRUE; |
4130 | } else if (ahd->msgout_index > index) |
4131 | found = TRUE; |
4132 | } |
4133 | index = end_index; |
4134 | } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK |
4135 | && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { |
4136 | |
4137 | /* Skip tag type and tag id or residue param*/ |
4138 | index += 2; |
4139 | } else { |
4140 | /* Single byte message */ |
4141 | if (type == AHDMSG_1B |
4142 | && ahd->msgout_index > index |
4143 | && (ahd->msgout_buf[index] == msgval |
4144 | || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 |
4145 | && msgval == MSG_IDENTIFYFLAG))) |
4146 | found = TRUE; |
4147 | index++; |
4148 | } |
4149 | |
4150 | if (found) |
4151 | break; |
4152 | } |
4153 | return (found); |
4154 | } |
4155 | |
4156 | /* |
4157 | * Wait for a complete incoming message, parse it, and respond accordingly. |
4158 | */ |
4159 | static int |
4160 | ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) |
4161 | { |
4162 | struct ahd_initiator_tinfo *tinfo; |
4163 | struct ahd_tmode_tstate *tstate; |
4164 | int reject; |
4165 | int done; |
4166 | int response; |
4167 | |
4168 | done = MSGLOOP_IN_PROG; |
4169 | response = FALSE; |
4170 | reject = FALSE; |
4171 | tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, |
4172 | devinfo->target, &tstate); |
4173 | |
4174 | /* |
4175 | * Parse as much of the message as is available, |
4176 | * rejecting it if we don't support it. When |
4177 | * the entire message is available and has been |
4178 | * handled, return MSGLOOP_MSGCOMPLETE, indicating |
4179 | * that we have parsed an entire message. |
4180 | * |
4181 | * In the case of extended messages, we accept the length |
4182 | * byte outright and perform more checking once we know the |
4183 | * extended message type. |
4184 | */ |
4185 | switch (ahd->msgin_buf[0]) { |
4186 | case MSG_DISCONNECT: |
4187 | case MSG_SAVEDATAPOINTER: |
4188 | case MSG_CMDCOMPLETE: |
4189 | case MSG_RESTOREPOINTERS: |
4190 | case MSG_IGN_WIDE_RESIDUE: |
4191 | /* |
4192 | * End our message loop as these are messages |
4193 | * the sequencer handles on its own. |
4194 | */ |
4195 | done = MSGLOOP_TERMINATED; |
4196 | break; |
4197 | case MSG_MESSAGE_REJECT: |
4198 | response = ahd_handle_msg_reject(ahd, devinfo); |
4199 | /* FALLTHROUGH */ |
4200 | case MSG_NOOP: |
4201 | done = MSGLOOP_MSGCOMPLETE; |
4202 | break; |
4203 | case MSG_EXTENDED: |
4204 | { |
4205 | /* Wait for enough of the message to begin validation */ |
4206 | if (ahd->msgin_index < 2) |
4207 | break; |
4208 | switch (ahd->msgin_buf[2]) { |
4209 | case MSG_EXT_SDTR: |
4210 | { |
4211 | u_int period; |
4212 | u_int ppr_options; |
4213 | u_int offset; |
4214 | u_int saved_offset; |
4215 | |
4216 | if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) { |
4217 | reject = TRUE; |
4218 | break; |
4219 | } |
4220 | |
4221 | /* |
4222 | * Wait until we have both args before validating |
4223 | * and acting on this message. |
4224 | * |
4225 | * Add one to MSG_EXT_SDTR_LEN to account for |
4226 | * the extended message preamble. |
4227 | */ |
4228 | if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1)) |
4229 | break; |
4230 | |
4231 | period = ahd->msgin_buf[3]; |
4232 | ppr_options = 0; |
4233 | saved_offset = offset = ahd->msgin_buf[4]; |
4234 | ahd_devlimited_syncrate(ahd, tinfo, &period, |
4235 | &ppr_options, devinfo->role); |
4236 | ahd_validate_offset(ahd, tinfo, period, &offset, |
4237 | tinfo->curr.width, devinfo->role); |
4238 | if (bootverbose) { |
4239 | printf("(%s:%c:%d:%d): Received " |
4240 | "SDTR period %x, offset %x\n\t" |
4241 | "Filtered to period %x, offset %x\n" , |
4242 | ahd_name(ahd), devinfo->channel, |
4243 | devinfo->target, devinfo->lun, |
4244 | ahd->msgin_buf[3], saved_offset, |
4245 | period, offset); |
4246 | } |
4247 | ahd_set_syncrate(ahd, devinfo, period, |
4248 | offset, ppr_options, |
4249 | AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, |
4250 | /*paused*/TRUE); |
4251 | |
4252 | /* |
4253 | * See if we initiated Sync Negotiation |
4254 | * and didn't have to fall down to async |
4255 | * transfers. |
4256 | */ |
4257 | if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) { |
4258 | /* We started it */ |
4259 | if (saved_offset != offset) { |
4260 | /* Went too low - force async */ |
4261 | reject = TRUE; |
4262 | } |
4263 | } else { |
4264 | /* |
4265 | * Send our own SDTR in reply |
4266 | */ |
4267 | if (bootverbose |
4268 | && devinfo->role == ROLE_INITIATOR) { |
4269 | printf("(%s:%c:%d:%d): Target " |
4270 | "Initiated SDTR\n" , |
4271 | ahd_name(ahd), devinfo->channel, |
4272 | devinfo->target, devinfo->lun); |
4273 | } |
4274 | ahd->msgout_index = 0; |
4275 | ahd->msgout_len = 0; |
4276 | ahd_construct_sdtr(ahd, devinfo, |
4277 | period, offset); |
4278 | ahd->msgout_index = 0; |
4279 | response = TRUE; |
4280 | } |
4281 | done = MSGLOOP_MSGCOMPLETE; |
4282 | break; |
4283 | } |
4284 | case MSG_EXT_WDTR: |
4285 | { |
4286 | u_int bus_width; |
4287 | u_int saved_width; |
4288 | u_int sending_reply; |
4289 | |
4290 | sending_reply = FALSE; |
4291 | if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) { |
4292 | reject = TRUE; |
4293 | break; |
4294 | } |
4295 | |
4296 | /* |
4297 | * Wait until we have our arg before validating |
4298 | * and acting on this message. |
4299 | * |
4300 | * Add one to MSG_EXT_WDTR_LEN to account for |
4301 | * the extended message preamble. |
4302 | */ |
4303 | if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1)) |
4304 | break; |
4305 | |
4306 | bus_width = ahd->msgin_buf[3]; |
4307 | saved_width = bus_width; |
4308 | ahd_validate_width(ahd, tinfo, &bus_width, |
4309 | devinfo->role); |
4310 | if (bootverbose) { |
4311 | printf("(%s:%c:%d:%d): Received WDTR " |
4312 | "%x filtered to %x\n" , |
4313 | ahd_name(ahd), devinfo->channel, |
4314 | devinfo->target, devinfo->lun, |
4315 | saved_width, bus_width); |
4316 | } |
4317 | |
4318 | if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) { |
4319 | /* |
4320 | * Don't send a WDTR back to the |
4321 | * target, since we asked first. |
4322 | * If the width went higher than our |
4323 | * request, reject it. |
4324 | */ |
4325 | if (saved_width > bus_width) { |
4326 | reject = TRUE; |
4327 | printf("(%s:%c:%d:%d): requested %dBit " |
4328 | "transfers. Rejecting...\n" , |
4329 | ahd_name(ahd), devinfo->channel, |
4330 | devinfo->target, devinfo->lun, |
4331 | 8 * (0x01 << bus_width)); |
4332 | bus_width = 0; |
4333 | } |
4334 | } else { |
4335 | /* |
4336 | * Send our own WDTR in reply |
4337 | */ |
4338 | if (bootverbose |
4339 | && devinfo->role == ROLE_INITIATOR) { |
4340 | printf("(%s:%c:%d:%d): Target " |
4341 | "Initiated WDTR\n" , |
4342 | ahd_name(ahd), devinfo->channel, |
4343 | devinfo->target, devinfo->lun); |
4344 | } |
4345 | ahd->msgout_index = 0; |
4346 | ahd->msgout_len = 0; |
4347 | ahd_construct_wdtr(ahd, devinfo, bus_width); |
4348 | ahd->msgout_index = 0; |
4349 | response = TRUE; |
4350 | sending_reply = TRUE; |
4351 | } |
4352 | /* |
4353 | * After a wide message, we are async, but |
4354 | * some devices don't seem to honor this portion |
4355 | * of the spec. Force a renegotiation of the |
4356 | * sync component of our transfer agreement even |
4357 | * if our goal is async. By updating our width |
4358 | * after forcing the negotiation, we avoid |
4359 | * renegotiating for width. |
4360 | */ |
4361 | ahd_update_neg_request(ahd, devinfo, tstate, |
4362 | tinfo, AHD_NEG_ALWAYS); |
4363 | ahd_set_width(ahd, devinfo, bus_width, |
4364 | AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, |
4365 | /*paused*/TRUE); |
4366 | if (sending_reply == FALSE && reject == FALSE) { |
4367 | |
4368 | /* |
4369 | * We will always have an SDTR to send. |
4370 | */ |
4371 | ahd->msgout_index = 0; |
4372 | ahd->msgout_len = 0; |
4373 | ahd_build_transfer_msg(ahd, devinfo); |
4374 | ahd->msgout_index = 0; |
4375 | response = TRUE; |
4376 | } |
4377 | done = MSGLOOP_MSGCOMPLETE; |
4378 | break; |
4379 | } |
4380 | case MSG_EXT_PPR: |
4381 | { |
4382 | u_int period; |
4383 | u_int offset; |
4384 | u_int bus_width; |
4385 | u_int ppr_options; |
4386 | u_int saved_width; |
4387 | u_int saved_offset; |
4388 | u_int saved_ppr_options; |
4389 | |
4390 | if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) { |
4391 | reject = TRUE; |
4392 | break; |
4393 | } |
4394 | |
4395 | /* |
4396 | * Wait until we have all args before validating |
4397 | * and acting on this message. |
4398 | * |
4399 | * Add one to MSG_EXT_PPR_LEN to account for |
4400 | * the extended message preamble. |
4401 | */ |
4402 | if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1)) |
4403 | break; |
4404 | |
4405 | period = ahd->msgin_buf[3]; |
4406 | offset = ahd->msgin_buf[5]; |
4407 | bus_width = ahd->msgin_buf[6]; |
4408 | saved_width = bus_width; |
4409 | ppr_options = ahd->msgin_buf[7]; |
4410 | /* |
4411 | * According to the spec, a DT only |
4412 | * period factor with no DT option |
4413 | * set implies async. |
4414 | */ |
4415 | if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 |
4416 | && period <= 9) |
4417 | offset = 0; |
4418 | saved_ppr_options = ppr_options; |
4419 | saved_offset = offset; |
4420 | |
4421 | /* |
4422 | * Transfer options are only available if we |
4423 | * are negotiating wide. |
4424 | */ |
4425 | if (bus_width == 0) |
4426 | ppr_options &= MSG_EXT_PPR_QAS_REQ; |
4427 | |
4428 | ahd_validate_width(ahd, tinfo, &bus_width, |
4429 | devinfo->role); |
4430 | ahd_devlimited_syncrate(ahd, tinfo, &period, |
4431 | &ppr_options, devinfo->role); |
4432 | ahd_validate_offset(ahd, tinfo, period, &offset, |
4433 | bus_width, devinfo->role); |
4434 | |
4435 | if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) { |
4436 | /* |
4437 | * If we are unable to do any of the |
4438 | * requested options (we went too low), |
4439 | * then we'll have to reject the message. |
4440 | */ |
4441 | if (saved_width > bus_width |
4442 | || saved_offset != offset |
4443 | || saved_ppr_options != ppr_options) { |
4444 | reject = TRUE; |
4445 | period = 0; |
4446 | offset = 0; |
4447 | bus_width = 0; |
4448 | ppr_options = 0; |
4449 | } |
4450 | } else { |
4451 | if (devinfo->role != ROLE_TARGET) |
4452 | printf("(%s:%c:%d:%d): Target " |
4453 | "Initiated PPR\n" , |
4454 | ahd_name(ahd), devinfo->channel, |
4455 | devinfo->target, devinfo->lun); |
4456 | else |
4457 | printf("(%s:%c:%d:%d): Initiator " |
4458 | "Initiated PPR\n" , |
4459 | ahd_name(ahd), devinfo->channel, |
4460 | devinfo->target, devinfo->lun); |
4461 | ahd->msgout_index = 0; |
4462 | ahd->msgout_len = 0; |
4463 | ahd_construct_ppr(ahd, devinfo, period, offset, |
4464 | bus_width, ppr_options); |
4465 | ahd->msgout_index = 0; |
4466 | response = TRUE; |
4467 | } |
4468 | if (bootverbose) { |
4469 | printf("(%s:%c:%d:%d): Received PPR width %x, " |
4470 | "period %x, offset %x,options %x\n" |
4471 | "\tFiltered to width %x, period %x, " |
4472 | "offset %x, options %x\n" , |
4473 | ahd_name(ahd), devinfo->channel, |
4474 | devinfo->target, devinfo->lun, |
4475 | saved_width, ahd->msgin_buf[3], |
4476 | saved_offset, saved_ppr_options, |
4477 | bus_width, period, offset, ppr_options); |
4478 | } |
4479 | ahd_set_width(ahd, devinfo, bus_width, |
4480 | AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, |
4481 | /*paused*/TRUE); |
4482 | ahd_set_syncrate(ahd, devinfo, period, |
4483 | offset, ppr_options, |
4484 | AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, |
4485 | /*paused*/TRUE); |
4486 | |
4487 | done = MSGLOOP_MSGCOMPLETE; |
4488 | break; |
4489 | } |
4490 | default: |
4491 | /* Unknown extended message. Reject it. */ |
4492 | reject = TRUE; |
4493 | break; |
4494 | } |
4495 | break; |
4496 | } |
4497 | #ifdef AHD_TARGET_MODE |
4498 | case MSG_BUS_DEV_RESET: |
4499 | ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD, |
4500 | CAM_BDR_SENT, |
4501 | "Bus Device Reset Received" , |
4502 | /*verbose_level*/0); |
4503 | ahd_restart(ahd); |
4504 | done = MSGLOOP_TERMINATED; |
4505 | break; |
4506 | case MSG_ABORT_TAG: |
4507 | case MSG_ABORT: |
4508 | case MSG_CLEAR_QUEUE: |
4509 | { |
4510 | int tag; |
4511 | |
4512 | /* Target mode messages */ |
4513 | if (devinfo->role != ROLE_TARGET) { |
4514 | reject = TRUE; |
4515 | break; |
4516 | } |
4517 | tag = SCB_LIST_NULL; |
4518 | if (ahd->msgin_buf[0] == MSG_ABORT_TAG) |
4519 | tag = ahd_inb(ahd, INITIATOR_TAG); |
4520 | ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, |
4521 | devinfo->lun, tag, ROLE_TARGET, |
4522 | CAM_REQ_ABORTED); |
4523 | |
4524 | tstate = ahd->enabled_targets[devinfo->our_scsiid]; |
4525 | if (tstate != NULL) { |
4526 | struct ahd_tmode_lstate* lstate; |
4527 | |
4528 | lstate = tstate->enabled_luns[devinfo->lun]; |
4529 | if (lstate != NULL) { |
4530 | ahd_queue_lstate_event(ahd, lstate, |
4531 | devinfo->our_scsiid, |
4532 | ahd->msgin_buf[0], |
4533 | /*arg*/tag); |
4534 | ahd_send_lstate_events(ahd, lstate); |
4535 | } |
4536 | } |
4537 | ahd_restart(ahd); |
4538 | done = MSGLOOP_TERMINATED; |
4539 | break; |
4540 | } |
4541 | #endif |
4542 | case MSG_QAS_REQUEST: |
4543 | #ifdef AHD_DEBUG |
4544 | if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) |
4545 | printf("%s: QAS request. SCSISIGI == 0x%x\n" , |
4546 | ahd_name(ahd), ahd_inb(ahd, SCSISIGI)); |
4547 | #endif |
4548 | ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE; |
4549 | /* FALLTHROUGH */ |
4550 | case MSG_TERM_IO_PROC: |
4551 | default: |
4552 | reject = TRUE; |
4553 | break; |
4554 | } |
4555 | |
4556 | if (reject) { |
4557 | /* |
4558 | * Setup to reject the message. |
4559 | */ |
4560 | ahd->msgout_index = 0; |
4561 | ahd->msgout_len = 1; |
4562 | ahd->msgout_buf[0] = MSG_MESSAGE_REJECT; |
4563 | done = MSGLOOP_MSGCOMPLETE; |
4564 | response = TRUE; |
4565 | } |
4566 | |
4567 | if (done != MSGLOOP_IN_PROG && !response) |
4568 | /* Clear the outgoing message buffer */ |
4569 | ahd->msgout_len = 0; |
4570 | |
4571 | return (done); |
4572 | } |
4573 | |
4574 | /* |
4575 | * Process a message reject message. |
4576 | */ |
4577 | static int |
4578 | ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) |
4579 | { |
4580 | /* |
4581 | * What we care about here is if we had an |
4582 | * outstanding SDTR or WDTR message for this |
4583 | * target. If we did, this is a signal that |
4584 | * the target is refusing negotiation. |
4585 | */ |
4586 | struct scb *scb; |
4587 | struct ahd_initiator_tinfo *tinfo; |
4588 | struct ahd_tmode_tstate *tstate; |
4589 | u_int scb_index; |
4590 | u_int last_msg; |
4591 | int response = 0; |
4592 | |
4593 | scb_index = ahd_get_scbptr(ahd); |
4594 | scb = ahd_lookup_scb(ahd, scb_index); |
4595 | tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, |
4596 | devinfo->our_scsiid, |
4597 | devinfo->target, &tstate); |
4598 | /* Might be necessary */ |
4599 | last_msg = ahd_inb(ahd, LAST_MSG); |
4600 | |
4601 | if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { |
4602 | if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE) |
4603 | && tinfo->goal.period <= AHD_SYNCRATE_PACED) { |
4604 | /* |
4605 | * Target may not like our SPI-4 PPR Options. |
4606 | * Attempt to negotiate 80MHz which will turn |
4607 | * off these options. |
4608 | */ |
4609 | if (bootverbose) { |
4610 | printf("(%s:%c:%d:%d): PPR Rejected. " |
4611 | "Trying simple U160 PPR\n" , |
4612 | ahd_name(ahd), devinfo->channel, |
4613 | devinfo->target, devinfo->lun); |
4614 | } |
4615 | tinfo->goal.period = AHD_SYNCRATE_DT; |
4616 | tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ |
4617 | | MSG_EXT_PPR_QAS_REQ |
4618 | | MSG_EXT_PPR_DT_REQ; |
4619 | } else { |
4620 | /* |
4621 | * Target does not support the PPR message. |
4622 | * Attempt to negotiate SPI-2 style. |
4623 | */ |
4624 | if (bootverbose) { |
4625 | printf("(%s:%c:%d:%d): PPR Rejected. " |
4626 | "Trying WDTR/SDTR\n" , |
4627 | ahd_name(ahd), devinfo->channel, |
4628 | devinfo->target, devinfo->lun); |
4629 | } |
4630 | tinfo->goal.ppr_options = 0; |
4631 | tinfo->curr.transport_version = 2; |
4632 | tinfo->goal.transport_version = 2; |
4633 | } |
4634 | ahd->msgout_index = 0; |
4635 | ahd->msgout_len = 0; |
4636 | ahd_build_transfer_msg(ahd, devinfo); |
4637 | ahd->msgout_index = 0; |
4638 | response = 1; |
4639 | } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { |
4640 | |
4641 | /* note 8bit xfers */ |
4642 | printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " |
4643 | "8bit transfers\n" , ahd_name(ahd), |
4644 | devinfo->channel, devinfo->target, devinfo->lun); |
4645 | ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, |
4646 | AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, |
4647 | /*paused*/TRUE); |
4648 | /* |
4649 | * No need to clear the sync rate. If the target |
4650 | * did not accept the command, our syncrate is |
4651 | * unaffected. If the target started the negotiation, |
4652 | * but rejected our response, we already cleared the |
4653 | * sync rate before sending our WDTR. |
4654 | */ |
4655 | if (tinfo->goal.offset != tinfo->curr.offset) { |
4656 | |
4657 | /* Start the sync negotiation */ |
4658 | ahd->msgout_index = 0; |
4659 | ahd->msgout_len = 0; |
4660 | ahd_build_transfer_msg(ahd, devinfo); |
4661 | ahd->msgout_index = 0; |
4662 | response = 1; |
4663 | } |
4664 | } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { |
4665 | /* note asynch xfers and clear flag */ |
4666 | ahd_set_syncrate(ahd, devinfo, /*period*/0, |
4667 | /*offset*/0, /*ppr_options*/0, |
4668 | AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, |
4669 | /*paused*/TRUE); |
4670 | printf("(%s:%c:%d:%d): refuses synchronous negotiation. " |
4671 | "Using asynchronous transfers\n" , |
4672 | ahd_name(ahd), devinfo->channel, |
4673 | devinfo->target, devinfo->lun); |
4674 | } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { |
4675 | int tag_type; |
4676 | int mask; |
4677 | |
4678 | tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); |
4679 | |
4680 | if (tag_type == MSG_SIMPLE_TASK) { |
4681 | printf("(%s:%c:%d:%d): refuses tagged commands. " |
4682 | "Performing non-tagged I/O\n" , ahd_name(ahd), |
4683 | devinfo->channel, devinfo->target, devinfo->lun); |
4684 | ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE); |
4685 | mask = ~0x23; |
4686 | } else { |
4687 | printf("(%s:%c:%d:%d): refuses %s tagged commands. " |
4688 | "Performing simple queue tagged I/O only\n" , |
4689 | ahd_name(ahd), devinfo->channel, devinfo->target, |
4690 | devinfo->lun, tag_type == MSG_ORDERED_Q_TAG |
4691 | ? "ordered" : "head of queue" ); |
4692 | ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC); |
4693 | mask = ~0x03; |
4694 | } |
4695 | |
4696 | /* |
4697 | * Resend the identify for this CCB as the target |
4698 | * may believe that the selection is invalid otherwise. |
4699 | */ |
4700 | ahd_outb(ahd, SCB_CONTROL, |
4701 | ahd_inb_scbram(ahd, SCB_CONTROL) & mask); |
4702 | scb->hscb->control &= mask; |
4703 | ahd_set_transaction_tag(scb, /*enabled*/FALSE, |
4704 | /*type*/MSG_SIMPLE_TASK); |
4705 | ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG); |
4706 | ahd_assert_atn(ahd); |
4707 | ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), |
4708 | SCB_GET_TAG(scb)); |
4709 | |
4710 | /* |
4711 | * Requeue all tagged commands for this target |
4712 | * currently in our possession so they can be |
4713 | * converted to untagged commands. |
4714 | */ |
4715 | ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), |
4716 | SCB_GET_CHANNEL(ahd, scb), |
4717 | SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, |
4718 | ROLE_INITIATOR, CAM_REQUEUE_REQ, |
4719 | SEARCH_COMPLETE); |
4720 | } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) { |
4721 | /* |
4722 | * Most likely the device believes that we had |
4723 | * previously negotiated packetized. |
4724 | */ |
4725 | ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE |
4726 | | MSG_FLAG_IU_REQ_CHANGED; |
4727 | |
4728 | ahd_force_renegotiation(ahd, devinfo); |
4729 | ahd->msgout_index = 0; |
4730 | ahd->msgout_len = 0; |
4731 | ahd_build_transfer_msg(ahd, devinfo); |
4732 | ahd->msgout_index = 0; |
4733 | response = 1; |
4734 | } else { |
4735 | /* |
4736 | * Otherwise, we ignore it. |
4737 | */ |
4738 | printf("%s:%c:%d: Message reject for %x -- ignored\n" , |
4739 | ahd_name(ahd), devinfo->channel, devinfo->target, |
4740 | last_msg); |
4741 | } |
4742 | return (response); |
4743 | } |
4744 | |
4745 | /* |
4746 | * Process an ignore wide residue message. |
4747 | */ |
4748 | static void |
4749 | ahd_handle_ign_wide_residue(struct ahd_softc *ahd, |
4750 | struct ahd_devinfo *devinfo) |
4751 | { |
4752 | u_int scb_index; |
4753 | struct scb *scb; |
4754 | |
4755 | printf("%s: ahd_handle_ign_wide_residue\n" , ahd_name(ahd)); |
4756 | |
4757 | scb_index = ahd_get_scbptr(ahd); |
4758 | scb = ahd_lookup_scb(ahd, scb_index); |
4759 | /* |
4760 | * XXX Actually check data direction in the sequencer? |
4761 | * Perhaps add datadir to some spare bits in the hscb? |
4762 | */ |
4763 | if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0 |
4764 | || ahd_get_transfer_dir(scb) != CAM_DIR_IN) { |
4765 | /* |
4766 | * Ignore the message if we haven't |
4767 | * seen an appropriate data phase yet. |
4768 | */ |
4769 | } else { |
4770 | /* |
4771 | * If the residual occurred on the last |
4772 | * transfer and the transfer request was |
4773 | * expected to end on an odd count, do |
4774 | * nothing. Otherwise, subtract a byte |
4775 | * and update the residual count accordingly. |
4776 | */ |
4777 | uint32_t sgptr; |
4778 | |
4779 | sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); |
4780 | if ((sgptr & SG_LIST_NULL) != 0 |
4781 | && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE) |
4782 | & SCB_XFERLEN_ODD) != 0) { |
4783 | /* |
4784 | * If the residual occurred on the last |
4785 | * transfer and the transfer request was |
4786 | * expected to end on an odd count, do |
4787 | * nothing. |
4788 | */ |
4789 | } else { |
4790 | uint32_t data_cnt; |
4791 | uint64_t data_addr; |
4792 | uint32_t sglen; |
4793 | |
4794 | /* Pull in the rest of the sgptr */ |
4795 | sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); |
4796 | data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT); |
4797 | if ((sgptr & SG_LIST_NULL) != 0) { |
4798 | /* |
4799 | * The residual data count is not updated |
4800 | * for the command run to completion case. |
4801 | * Explcitly zero the count. |
4802 | */ |
4803 | data_cnt &= ~AHD_SG_LEN_MASK; |
4804 | } |
4805 | data_addr = ahd_inq(ahd, SHADDR); |
4806 | data_cnt += 1; |
4807 | data_addr -= 1; |
4808 | sgptr &= SG_PTR_MASK; |
4809 | if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { |
4810 | struct ahd_dma64_seg *sg; |
4811 | |
4812 | sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); |
4813 | |
4814 | /* |
4815 | * The residual sg ptr points to the next S/G |
4816 | * to load so we must go back one. |
4817 | */ |
4818 | sg--; |
4819 | sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; |
4820 | if (sg != scb->sg_list |
4821 | && sglen < (data_cnt & AHD_SG_LEN_MASK)) { |
4822 | |
4823 | sg--; |
4824 | sglen = ahd_le32toh(sg->len); |
4825 | /* |
4826 | * Preserve High Address and SG_LIST |
4827 | * bits while setting the count to 1. |
4828 | */ |
4829 | data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); |
4830 | data_addr = ahd_le64toh(sg->addr) |
4831 | + (sglen & AHD_SG_LEN_MASK) |
4832 | - 1; |
4833 | |
4834 | /* |
4835 | * Increment sg so it points to the |
4836 | * "next" sg. |
4837 | */ |
4838 | sg++; |
4839 | sgptr = ahd_sg_virt_to_bus(ahd, scb, |
4840 | sg); |
4841 | } |
4842 | } else { |
4843 | struct ahd_dma_seg *sg; |
4844 | |
4845 | sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); |
4846 | |
4847 | /* |
4848 | * The residual sg ptr points to the next S/G |
4849 | * to load so we must go back one. |
4850 | */ |
4851 | sg--; |
4852 | sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; |
4853 | if (sg != scb->sg_list |
4854 | && sglen < (data_cnt & AHD_SG_LEN_MASK)) { |
4855 | |
4856 | sg--; |
4857 | sglen = ahd_le32toh(sg->len); |
4858 | /* |
4859 | * Preserve High Address and SG_LIST |
4860 | * bits while setting the count to 1. |
4861 | */ |
4862 | data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); |
4863 | data_addr = ahd_le32toh(sg->addr) |
4864 | + (sglen & AHD_SG_LEN_MASK) |
4865 | - 1; |
4866 | |
4867 | /* |
4868 | * Increment sg so it points to the |
4869 | * "next" sg. |
4870 | */ |
4871 | sg++; |
4872 | sgptr = ahd_sg_virt_to_bus(ahd, scb, |
4873 | sg); |
4874 | } |
4875 | } |
4876 | /* |
4877 | * Toggle the "oddness" of the transfer length |
4878 | * to handle this mid-transfer ignore wide |
4879 | * residue. This ensures that the oddness is |
4880 | * correct for subsequent data transfers. |
4881 | */ |
4882 | ahd_outb(ahd, SCB_TASK_ATTRIBUTE, |
4883 | ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE) |
4884 | ^ SCB_XFERLEN_ODD); |
4885 | |
4886 | ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); |
4887 | ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt); |
4888 | /* |
4889 | * The FIFO's pointers will be updated if/when the |
4890 | * sequencer re-enters a data phase. |
4891 | */ |
4892 | } |
4893 | } |
4894 | } |
4895 | |
4896 | |
4897 | /* |
4898 | * Reinitialize the data pointers for the active transfer |
4899 | * based on its current residual. |
4900 | */ |
4901 | static void |
4902 | ahd_reinitialize_dataptrs(struct ahd_softc *ahd) |
4903 | { |
4904 | struct scb *scb; |
4905 | ahd_mode_state saved_modes; |
4906 | u_int scb_index; |
4907 | u_int wait; |
4908 | uint32_t sgptr; |
4909 | uint32_t resid; |
4910 | uint64_t dataptr; |
4911 | |
4912 | AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK, |
4913 | AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK); |
4914 | |
4915 | scb_index = ahd_get_scbptr(ahd); |
4916 | scb = ahd_lookup_scb(ahd, scb_index); |
4917 | |
4918 | /* |
4919 | * Release and reacquire the FIFO so we |
4920 | * have a clean slate. |
4921 | */ |
4922 | ahd_outb(ahd, DFFSXFRCTL, CLRCHN); |
4923 | wait = 1000; |
4924 | while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE)) |
4925 | ahd_delay(100); |
4926 | if (wait == 0) { |
4927 | ahd_print_path(ahd, scb); |
4928 | printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n" ); |
4929 | ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); |
4930 | } |
4931 | saved_modes = ahd_save_modes(ahd); |
4932 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
4933 | ahd_outb(ahd, DFFSTAT, |
4934 | ahd_inb(ahd, DFFSTAT) |
4935 | | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0)); |
4936 | |
4937 | /* |
4938 | * Determine initial values for data_addr and data_cnt |
4939 | * for resuming the data phase. |
4940 | */ |
4941 | sgptr = (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24) |
4942 | | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16) |
4943 | | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8) |
4944 | | ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); |
4945 | sgptr &= SG_PTR_MASK; |
4946 | |
4947 | resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16) |
4948 | | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8) |
4949 | | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT); |
4950 | |
4951 | if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { |
4952 | struct ahd_dma64_seg *sg; |
4953 | |
4954 | sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); |
4955 | |
4956 | /* The residual sg_ptr always points to the next sg */ |
4957 | sg--; |
4958 | |
4959 | dataptr = ahd_le64toh(sg->addr) |
4960 | + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) |
4961 | - resid; |
4962 | ahd_outb(ahd, HADDR + 7, dataptr >> 56); |
4963 | ahd_outb(ahd, HADDR + 6, dataptr >> 48); |
4964 | ahd_outb(ahd, HADDR + 5, dataptr >> 40); |
4965 | ahd_outb(ahd, HADDR + 4, dataptr >> 32); |
4966 | } else { |
4967 | struct ahd_dma_seg *sg; |
4968 | |
4969 | sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); |
4970 | |
4971 | /* The residual sg_ptr always points to the next sg */ |
4972 | sg--; |
4973 | |
4974 | dataptr = ahd_le32toh(sg->addr) |
4975 | + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) |
4976 | - resid; |
4977 | ahd_outb(ahd, HADDR + 4, |
4978 | (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24); |
4979 | } |
4980 | ahd_outb(ahd, HADDR + 3, dataptr >> 24); |
4981 | ahd_outb(ahd, HADDR + 2, dataptr >> 16); |
4982 | ahd_outb(ahd, HADDR + 1, dataptr >> 8); |
4983 | ahd_outb(ahd, HADDR, dataptr); |
4984 | ahd_outb(ahd, HCNT + 2, resid >> 16); |
4985 | ahd_outb(ahd, HCNT + 1, resid >> 8); |
4986 | ahd_outb(ahd, HCNT, resid); |
4987 | } |
4988 | |
4989 | /* |
4990 | * Handle the effects of issuing a bus device reset message. |
4991 | */ |
4992 | static void |
4993 | ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, |
4994 | u_int lun, cam_status status, const char *message, |
4995 | int verbose_level) |
4996 | { |
4997 | #ifdef AHD_TARGET_MODE |
4998 | struct ahd_tmode_tstate* tstate; |
4999 | #endif |
5000 | int found; |
5001 | |
5002 | found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, |
5003 | lun, SCB_LIST_NULL, devinfo->role, |
5004 | status); |
5005 | |
5006 | #ifdef AHD_TARGET_MODE |
5007 | /* |
5008 | * Send an immediate notify ccb to all target mord peripheral |
5009 | * drivers affected by this action. |
5010 | */ |
5011 | tstate = ahd->enabled_targets[devinfo->our_scsiid]; |
5012 | if (tstate != NULL) { |
5013 | u_int cur_lun; |
5014 | u_int max_lun; |
5015 | |
5016 | if (lun != CAM_LUN_WILDCARD) { |
5017 | cur_lun = 0; |
5018 | max_lun = AHD_NUM_LUNS - 1; |
5019 | } else { |
5020 | cur_lun = lun; |
5021 | max_lun = lun; |
5022 | } |
5023 | for (cur_lun <= max_lun; cur_lun++) { |
5024 | struct ahd_tmode_lstate* lstate; |
5025 | |
5026 | lstate = tstate->enabled_luns[cur_lun]; |
5027 | if (lstate == NULL) |
5028 | continue; |
5029 | |
5030 | ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid, |
5031 | MSG_BUS_DEV_RESET, /*arg*/0); |
5032 | ahd_send_lstate_events(ahd, lstate); |
5033 | } |
5034 | } |
5035 | #endif |
5036 | |
5037 | /* |
5038 | * Go back to async/narrow transfers and renegotiate. |
5039 | */ |
5040 | ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, |
5041 | AHD_TRANS_CUR, /*paused*/TRUE); |
5042 | ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0, |
5043 | /*ppr_options*/0, AHD_TRANS_CUR, /*paused*/TRUE); |
5044 | |
5045 | ahd_send_async(ahd, devinfo->channel, devinfo->target, |
5046 | lun, AC_SENT_BDR, NULL); |
5047 | |
5048 | if (message != NULL |
5049 | && (verbose_level <= bootverbose)) |
5050 | printf("%s: %s on %c:%d. %d SCBs aborted\n" , ahd_name(ahd), |
5051 | message, devinfo->channel, devinfo->target, found); |
5052 | } |
5053 | |
5054 | #ifdef AHD_TARGET_MODE |
5055 | static void |
5056 | ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, |
5057 | struct scb *scb) |
5058 | { |
5059 | |
5060 | /* |
5061 | * To facilitate adding multiple messages together, |
5062 | * each routine should increment the index and len |
5063 | * variables instead of setting them explicitly. |
5064 | */ |
5065 | ahd->msgout_index = 0; |
5066 | ahd->msgout_len = 0; |
5067 | |
5068 | if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) |
5069 | ahd_build_transfer_msg(ahd, devinfo); |
5070 | else |
5071 | panic("ahd_intr: AWAITING target message with no message" ); |
5072 | |
5073 | ahd->msgout_index = 0; |
5074 | ahd->msg_type = MSG_TYPE_TARGET_MSGIN; |
5075 | } |
5076 | #endif |
5077 | /**************************** Initialization **********************************/ |
5078 | static u_int |
5079 | ahd_sglist_size(struct ahd_softc *ahd) |
5080 | { |
5081 | bus_size_t list_size; |
5082 | |
5083 | list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG; |
5084 | if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) |
5085 | list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG; |
5086 | return (list_size); |
5087 | } |
5088 | |
5089 | /* |
5090 | * Calculate the optimum S/G List allocation size. S/G elements used |
5091 | * for a given transaction must be physically contiguous. Assume the |
5092 | * OS will allocate full pages to us, so it doesn't make sense to request |
5093 | * less than a page. |
5094 | */ |
5095 | static u_int |
5096 | ahd_sglist_allocsize(struct ahd_softc *ahd) |
5097 | { |
5098 | bus_size_t sg_list_increment; |
5099 | bus_size_t sg_list_size; |
5100 | bus_size_t max_list_size; |
5101 | bus_size_t best_list_size; |
5102 | |
5103 | /* Start out with the minimum required for AHD_NSEG. */ |
5104 | sg_list_increment = ahd_sglist_size(ahd); |
5105 | sg_list_size = sg_list_increment; |
5106 | |
5107 | /* Get us as close as possible to a page in size. */ |
5108 | while ((sg_list_size + sg_list_increment) <= PAGE_SIZE) |
5109 | sg_list_size += sg_list_increment; |
5110 | |
5111 | /* |
5112 | * Try to reduce the amount of wastage by allocating |
5113 | * multiple pages. |
5114 | */ |
5115 | best_list_size = sg_list_size; |
5116 | max_list_size = roundup(sg_list_increment, PAGE_SIZE); |
5117 | if (max_list_size < 4 * PAGE_SIZE) |
5118 | max_list_size = 4 * PAGE_SIZE; |
5119 | if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment)) |
5120 | max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment); |
5121 | while ((sg_list_size + sg_list_increment) <= max_list_size |
5122 | && (sg_list_size % PAGE_SIZE) != 0) { |
5123 | bus_size_t new_mod; |
5124 | bus_size_t best_mod; |
5125 | |
5126 | sg_list_size += sg_list_increment; |
5127 | new_mod = sg_list_size % PAGE_SIZE; |
5128 | best_mod = best_list_size % PAGE_SIZE; |
5129 | if (new_mod > best_mod || new_mod == 0) { |
5130 | best_list_size = sg_list_size; |
5131 | } |
5132 | } |
5133 | return (best_list_size); |
5134 | } |
5135 | |
5136 | int |
5137 | ahd_softc_init(struct ahd_softc *ahd) |
5138 | { |
5139 | |
5140 | ahd->unpause = 0; |
5141 | ahd->pause = PAUSE; |
5142 | return (0); |
5143 | } |
5144 | |
5145 | void |
5146 | ahd_set_unit(struct ahd_softc *ahd, int unit) |
5147 | { |
5148 | ahd->unit = unit; |
5149 | } |
5150 | |
5151 | void |
5152 | ahd_set_name(struct ahd_softc *ahd, const char *name) |
5153 | { |
5154 | ahd->name = name; |
5155 | } |
5156 | |
5157 | void |
5158 | ahd_free(struct ahd_softc *ahd) |
5159 | { |
5160 | int i; |
5161 | |
5162 | switch (ahd->init_level) { |
5163 | default: |
5164 | case 2: |
5165 | ahd_shutdown(ahd); |
5166 | TAILQ_REMOVE(&ahd_tailq, ahd, links); |
5167 | /* FALLTHROUGH */ |
5168 | case 1: |
5169 | bus_dmamap_unload(ahd->parent_dmat, |
5170 | ahd->shared_data_map.dmamap); |
5171 | bus_dmamap_destroy(ahd->parent_dmat, |
5172 | ahd->shared_data_map.dmamap); |
5173 | bus_dmamem_unmap(ahd->parent_dmat, (void *)ahd->qoutfifo, |
5174 | ahd->shared_data_size); |
5175 | bus_dmamem_free(ahd->parent_dmat, |
5176 | &ahd->shared_data_map.dmasegs, ahd->shared_data_map.nseg); |
5177 | break; |
5178 | case 0: |
5179 | break; |
5180 | } |
5181 | |
5182 | ahd_platform_free(ahd); |
5183 | ahd_fini_scbdata(ahd); |
5184 | for (i = 0; i < AHD_NUM_TARGETS; i++) { |
5185 | struct ahd_tmode_tstate *tstate; |
5186 | |
5187 | tstate = ahd->enabled_targets[i]; |
5188 | if (tstate != NULL) { |
5189 | #if AHD_TARGET_MODE |
5190 | int j; |
5191 | |
5192 | for (j = 0; j < AHD_NUM_LUNS; j++) { |
5193 | struct ahd_tmode_lstate *lstate; |
5194 | |
5195 | lstate = tstate->enabled_luns[j]; |
5196 | if (lstate != NULL) { |
5197 | xpt_free_path(lstate->path); |
5198 | free(lstate, M_DEVBUF); |
5199 | } |
5200 | } |
5201 | #endif |
5202 | free(tstate, M_DEVBUF); |
5203 | } |
5204 | } |
5205 | #if AHD_TARGET_MODE |
5206 | if (ahd->black_hole != NULL) { |
5207 | xpt_free_path(ahd->black_hole->path); |
5208 | free(ahd->black_hole, M_DEVBUF); |
5209 | } |
5210 | #endif |
5211 | if (ahd->seep_config != NULL) |
5212 | free(ahd->seep_config, M_DEVBUF); |
5213 | if (ahd->saved_stack != NULL) |
5214 | free(ahd->saved_stack, M_DEVBUF); |
5215 | #ifndef __FreeBSD__ |
5216 | free(ahd, M_DEVBUF); |
5217 | #endif |
5218 | return; |
5219 | } |
5220 | |
5221 | void |
5222 | ahd_shutdown(void *arg) |
5223 | { |
5224 | struct ahd_softc *ahd; |
5225 | |
5226 | ahd = arg; |
5227 | |
5228 | #ifdef AHD_DEBUG |
5229 | printf("%s: ahd_shutdown\n" , ahd_name(ahd)); |
5230 | #endif |
5231 | /* |
5232 | * Stop periodic timer callbacks. |
5233 | */ |
5234 | ahd_timer_stop(&ahd->reset_timer); |
5235 | ahd_timer_stop(&ahd->stat_timer); |
5236 | |
5237 | /* This will reset most registers to 0, but not all */ |
5238 | ahd_reset(ahd, /*reinit*/FALSE); |
5239 | } |
5240 | |
5241 | /* |
5242 | * Reset the controller and record some information about it |
5243 | * that is only available just after a reset. If "reinit" is |
5244 | * non-zero, this reset occurred after initial configuration |
5245 | * and the caller requests that the chip be fully reinitialized |
5246 | * to a runable state. Chip interrupts are *not* enabled after |
5247 | * a reinitialization. The caller must enable interrupts via |
5248 | * ahd_intr_enable(). |
5249 | */ |
5250 | int |
5251 | ahd_reset(struct ahd_softc *ahd, int reinit) |
5252 | { |
5253 | u_int sxfrctl1; |
5254 | int wait; |
5255 | uint32_t cmd; |
5256 | struct ahd_pci_busdata *bd = ahd->bus_data; |
5257 | |
5258 | /* |
5259 | * Preserve the value of the SXFRCTL1 register for all channels. |
5260 | * It contains settings that affect termination and we don't want |
5261 | * to disturb the integrity of the bus. |
5262 | */ |
5263 | ahd_pause(ahd); |
5264 | ahd_update_modes(ahd); |
5265 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
5266 | sxfrctl1 = ahd_inb(ahd, SXFRCTL1); |
5267 | |
5268 | cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); |
5269 | |
5270 | if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { |
5271 | uint32_t mod_cmd; |
5272 | |
5273 | /* |
5274 | * A4 Razor #632 |
5275 | * During the assertion of CHIPRST, the chip |
5276 | * does not disable its parity logic prior to |
5277 | * the start of the reset. This may cause a |
5278 | * parity error to be detected and thus a |
5279 | * spurious SERR or PERR assertion. Disble |
5280 | * PERR and SERR responses during the CHIPRST. |
5281 | */ |
5282 | mod_cmd = cmd & |
5283 | ~(PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); |
5284 | pci_conf_write(bd->pc, bd->tag, |
5285 | PCI_COMMAND_STATUS_REG, mod_cmd); |
5286 | } |
5287 | ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause); |
5288 | |
5289 | /* |
5290 | * Ensure that the reset has finished. We delay 1000us |
5291 | * prior to reading the register to make sure the chip |
5292 | * has sufficiently completed its reset to handle register |
5293 | * accesses. |
5294 | */ |
5295 | wait = 1000; |
5296 | do { |
5297 | ahd_delay(1000); |
5298 | } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK)); |
5299 | |
5300 | if (wait == 0) { |
5301 | printf("%s: WARNING - Failed chip reset! " |
5302 | "Trying to initialize anyway.\n" , ahd_name(ahd)); |
5303 | } |
5304 | ahd_outb(ahd, HCNTRL, ahd->pause); |
5305 | |
5306 | if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { |
5307 | /* |
5308 | * Clear any latched PCI error status and restore |
5309 | * previous SERR and PERR response enables. |
5310 | */ |
5311 | pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd | |
5312 | (PCI_STATUS_PARITY_ERROR | PCI_STATUS_TARGET_TARGET_ABORT | |
5313 | PCI_STATUS_MASTER_TARGET_ABORT | PCI_STATUS_MASTER_ABORT | |
5314 | PCI_STATUS_SPECIAL_ERROR)); |
5315 | } |
5316 | |
5317 | /* |
5318 | * Mode should be SCSI after a chip reset, but lets |
5319 | * set it just to be safe. We touch the MODE_PTR |
5320 | * register directly so as to bypass the lazy update |
5321 | * ode in ahd_set_modes(). |
5322 | */ |
5323 | ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
5324 | ahd_outb(ahd, MODE_PTR, |
5325 | ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI)); |
5326 | |
5327 | /* |
5328 | * Restore SXFRCTL1. |
5329 | * |
5330 | * We must always initialize STPWEN to 1 before we |
5331 | * restore the saved values. STPWEN is initialized |
5332 | * to a tri-state condition which can only be cleared |
5333 | * by turning it on. |
5334 | */ |
5335 | ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); |
5336 | ahd_outb(ahd, SXFRCTL1, sxfrctl1); |
5337 | |
5338 | /* Determine chip configuration */ |
5339 | ahd->features &= ~AHD_WIDE; |
5340 | if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0) |
5341 | ahd->features |= AHD_WIDE; |
5342 | |
5343 | /* |
5344 | * If a recovery action has forced a chip reset, |
5345 | * re-initialize the chip to our liking. |
5346 | */ |
5347 | if (reinit != 0) |
5348 | ahd_chip_init(ahd); |
5349 | |
5350 | return (0); |
5351 | } |
5352 | |
5353 | /* |
5354 | * Determine the number of SCBs available on the controller |
5355 | */ |
5356 | int |
5357 | ahd_probe_scbs(struct ahd_softc *ahd) { |
5358 | int i; |
5359 | |
5360 | AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), |
5361 | ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); |
5362 | for (i = 0; i < AHD_SCB_MAX; i++) { |
5363 | int j; |
5364 | int ret; |
5365 | |
5366 | ahd_set_scbptr(ahd, i); |
5367 | ahd_outw(ahd, SCB_BASE, i); |
5368 | for (j = 2; j < 64; j++) |
5369 | ahd_outb(ahd, SCB_BASE+j, 0); |
5370 | /* Start out life as unallocated (needing an abort) */ |
5371 | ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE); |
5372 | ret = ahd_inw_scbram(ahd, SCB_BASE); |
5373 | if (ret != i) { |
5374 | printf("%s: ahd_probe_scbs (!=%d): returned 0x%x\n" , |
5375 | ahd_name(ahd), i, ret); |
5376 | break; |
5377 | } |
5378 | ahd_set_scbptr(ahd, 0); |
5379 | ret = ahd_inw_scbram(ahd, SCB_BASE); |
5380 | if (ret != 0) { |
5381 | printf("ahd_probe_scbs (non zero): returned 0x%x\n" , |
5382 | ret); |
5383 | break; |
5384 | } |
5385 | } |
5386 | return (i); |
5387 | } |
5388 | |
5389 | static void |
5390 | ahd_initialize_hscbs(struct ahd_softc *ahd) |
5391 | { |
5392 | int i; |
5393 | |
5394 | for (i = 0; i < ahd->scb_data.maxhscbs; i++) { |
5395 | ahd_set_scbptr(ahd, i); |
5396 | |
5397 | /* Clear the control byte. */ |
5398 | ahd_outb(ahd, SCB_CONTROL, 0); |
5399 | |
5400 | /* Set the next pointer */ |
5401 | ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL); |
5402 | } |
5403 | } |
5404 | |
5405 | static int |
5406 | ahd_init_scbdata(struct ahd_softc *ahd) |
5407 | { |
5408 | struct scb_data *scb_data; |
5409 | int i; |
5410 | |
5411 | scb_data = &ahd->scb_data; |
5412 | TAILQ_INIT(&scb_data->free_scbs); |
5413 | for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++) |
5414 | LIST_INIT(&scb_data->free_scb_lists[i]); |
5415 | LIST_INIT(&scb_data->any_dev_free_scb_list); |
5416 | SLIST_INIT(&scb_data->hscb_maps); |
5417 | SLIST_INIT(&scb_data->sg_maps); |
5418 | SLIST_INIT(&scb_data->sense_maps); |
5419 | |
5420 | /* Determine the number of hardware SCBs and initialize them */ |
5421 | scb_data->maxhscbs = ahd_probe_scbs(ahd); |
5422 | if (scb_data->maxhscbs == 0) { |
5423 | printf("%s: No SCB space found\n" , ahd_name(ahd)); |
5424 | return (ENXIO); |
5425 | } |
5426 | ahd_initialize_hscbs(ahd); |
5427 | |
5428 | /* |
5429 | * Create our DMA tags. These tags define the kinds of device |
5430 | * accessible memory allocations and memory mappings we will |
5431 | * need to perform during normal operation. |
5432 | * |
5433 | * Unless we need to further restrict the allocation, we rely |
5434 | * on the restrictions of the parent dmat, hence the common |
5435 | * use of MAXADDR and MAXSIZE. |
5436 | */ |
5437 | |
5438 | /* Perform initial CCB allocation */ |
5439 | ahd_alloc_scbs(ahd); |
5440 | |
5441 | if (scb_data->numscbs == 0) { |
5442 | printf("%s: ahd_init_scbdata - " |
5443 | "Unable to allocate initial scbs\n" , |
5444 | ahd_name(ahd)); |
5445 | goto error_exit; |
5446 | } |
5447 | |
5448 | /* |
5449 | * Note that we were successfull |
5450 | */ |
5451 | return (0); |
5452 | |
5453 | error_exit: |
5454 | |
5455 | return (ENOMEM); |
5456 | } |
5457 | |
5458 | static struct scb * |
5459 | ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag) |
5460 | { |
5461 | struct scb *scb; |
5462 | |
5463 | /* |
5464 | * Look on the pending list. |
5465 | */ |
5466 | LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { |
5467 | if (SCB_GET_TAG(scb) == tag) |
5468 | return (scb); |
5469 | } |
5470 | |
5471 | /* |
5472 | * Then on all of the collision free lists. |
5473 | */ |
5474 | TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { |
5475 | struct scb *list_scb; |
5476 | |
5477 | list_scb = scb; |
5478 | do { |
5479 | if (SCB_GET_TAG(list_scb) == tag) |
5480 | return (list_scb); |
5481 | list_scb = LIST_NEXT(list_scb, collision_links); |
5482 | } while (list_scb); |
5483 | } |
5484 | |
5485 | /* |
5486 | * And finally on the generic free list. |
5487 | */ |
5488 | LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { |
5489 | if (SCB_GET_TAG(scb) == tag) |
5490 | return (scb); |
5491 | } |
5492 | |
5493 | return (NULL); |
5494 | } |
5495 | |
5496 | static void |
5497 | ahd_fini_scbdata(struct ahd_softc *ahd) |
5498 | { |
5499 | struct scb_data *scb_data; |
5500 | |
5501 | scb_data = &ahd->scb_data; |
5502 | if (scb_data == NULL) |
5503 | return; |
5504 | |
5505 | switch (scb_data->init_level) { |
5506 | default: |
5507 | case 3: |
5508 | { |
5509 | struct map_node *sns_map; |
5510 | |
5511 | while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) { |
5512 | SLIST_REMOVE_HEAD(&scb_data->sense_maps, links); |
5513 | ahd_freedmamem(ahd->parent_dmat, PAGE_SIZE, |
5514 | sns_map->dmamap, (void *)sns_map->vaddr, |
5515 | &sns_map->dmasegs, sns_map->nseg); |
5516 | free(sns_map, M_DEVBUF); |
5517 | } |
5518 | /* FALLTHROUGH */ |
5519 | } |
5520 | case 2: |
5521 | { |
5522 | struct map_node *sg_map; |
5523 | |
5524 | while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) { |
5525 | SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); |
5526 | ahd_freedmamem(ahd->parent_dmat, |
5527 | ahd_sglist_allocsize(ahd), |
5528 | sg_map->dmamap, (void *)sg_map->vaddr, |
5529 | &sg_map->dmasegs, sg_map->nseg); |
5530 | free(sg_map, M_DEVBUF); |
5531 | } |
5532 | /* FALLTHROUGH */ |
5533 | } |
5534 | case 1: |
5535 | { |
5536 | struct map_node *hscb_map; |
5537 | |
5538 | while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) { |
5539 | SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links); |
5540 | ahd_freedmamem(ahd->parent_dmat, PAGE_SIZE, |
5541 | hscb_map->dmamap, |
5542 | (void *)hscb_map->vaddr, |
5543 | &hscb_map->dmasegs, hscb_map->nseg); |
5544 | free(hscb_map, M_DEVBUF); |
5545 | } |
5546 | /* FALLTHROUGH */ |
5547 | } |
5548 | case 0: |
5549 | break; |
5550 | } |
5551 | } |
5552 | |
5553 | /* |
5554 | * DSP filter Bypass must be enabled until the first selection |
5555 | * after a change in bus mode (Razor #491 and #493). |
5556 | */ |
5557 | static void |
5558 | ahd_setup_iocell_workaround(struct ahd_softc *ahd) |
5559 | { |
5560 | ahd_mode_state saved_modes; |
5561 | |
5562 | saved_modes = ahd_save_modes(ahd); |
5563 | ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); |
5564 | ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL) |
5565 | | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS); |
5566 | ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI)); |
5567 | #ifdef AHD_DEBUG |
5568 | if ((ahd_debug & AHD_SHOW_MISC) != 0) |
5569 | printf("%s: Setting up iocell workaround\n" , ahd_name(ahd)); |
5570 | #endif |
5571 | ahd_restore_modes(ahd, saved_modes); |
5572 | ahd->flags &= ~AHD_HAD_FIRST_SEL; |
5573 | } |
5574 | |
5575 | static void |
5576 | ahd_iocell_first_selection(struct ahd_softc *ahd) |
5577 | { |
5578 | ahd_mode_state saved_modes; |
5579 | u_int sblkctl; |
5580 | |
5581 | if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0) |
5582 | return; |
5583 | saved_modes = ahd_save_modes(ahd); |
5584 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
5585 | sblkctl = ahd_inb(ahd, SBLKCTL); |
5586 | ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); |
5587 | #ifdef AHD_DEBUG |
5588 | if ((ahd_debug & AHD_SHOW_MISC) != 0) |
5589 | printf("%s: iocell first selection\n" , ahd_name(ahd)); |
5590 | #endif |
5591 | if ((sblkctl & ENAB40) != 0) { |
5592 | ahd_outb(ahd, DSPDATACTL, |
5593 | ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB); |
5594 | #ifdef AHD_DEBUG |
5595 | if ((ahd_debug & AHD_SHOW_MISC) != 0) |
5596 | printf("%s: BYPASS now disabled\n" , ahd_name(ahd)); |
5597 | #endif |
5598 | } |
5599 | ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI)); |
5600 | ahd_outb(ahd, CLRINT, CLRSCSIINT); |
5601 | ahd_restore_modes(ahd, saved_modes); |
5602 | ahd->flags |= AHD_HAD_FIRST_SEL; |
5603 | } |
5604 | |
5605 | /*************************** SCB Management ***********************************/ |
5606 | static void |
5607 | ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx) |
5608 | { |
5609 | struct scb_list *free_list; |
5610 | struct scb_tailq *free_tailq; |
5611 | struct scb *first_scb; |
5612 | |
5613 | scb->flags |= SCB_ON_COL_LIST; |
5614 | AHD_SET_SCB_COL_IDX(scb, col_idx); |
5615 | free_list = &ahd->scb_data.free_scb_lists[col_idx]; |
5616 | free_tailq = &ahd->scb_data.free_scbs; |
5617 | first_scb = LIST_FIRST(free_list); |
5618 | if (first_scb != NULL) { |
5619 | LIST_INSERT_AFTER(first_scb, scb, collision_links); |
5620 | } else { |
5621 | LIST_INSERT_HEAD(free_list, scb, collision_links); |
5622 | TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe); |
5623 | } |
5624 | } |
5625 | |
5626 | static void |
5627 | ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb) |
5628 | { |
5629 | struct scb_list *free_list; |
5630 | struct scb_tailq *free_tailq; |
5631 | struct scb *first_scb; |
5632 | u_int col_idx; |
5633 | |
5634 | scb->flags &= ~SCB_ON_COL_LIST; |
5635 | col_idx = AHD_GET_SCB_COL_IDX(ahd, scb); |
5636 | free_list = &ahd->scb_data.free_scb_lists[col_idx]; |
5637 | free_tailq = &ahd->scb_data.free_scbs; |
5638 | first_scb = LIST_FIRST(free_list); |
5639 | if (first_scb == scb) { |
5640 | struct scb *next_scb; |
5641 | |
5642 | /* |
5643 | * Maintain order in the collision free |
5644 | * lists for fairness if this device has |
5645 | * other colliding tags active. |
5646 | */ |
5647 | next_scb = LIST_NEXT(scb, collision_links); |
5648 | if (next_scb != NULL) { |
5649 | TAILQ_INSERT_AFTER(free_tailq, scb, |
5650 | next_scb, links.tqe); |
5651 | } |
5652 | TAILQ_REMOVE(free_tailq, scb, links.tqe); |
5653 | } |
5654 | LIST_REMOVE(scb, collision_links); |
5655 | } |
5656 | |
5657 | /* |
5658 | * Get a free scb. If there are none, see if we can allocate a new SCB. |
5659 | */ |
5660 | struct scb * |
5661 | ahd_get_scb(struct ahd_softc *ahd, u_int col_idx) |
5662 | { |
5663 | struct scb *scb; |
5664 | TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { |
5665 | if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) { |
5666 | ahd_rem_col_list(ahd, scb); |
5667 | goto found; |
5668 | } |
5669 | } |
5670 | if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) |
5671 | return (NULL); |
5672 | LIST_REMOVE(scb, links.le); |
5673 | if (col_idx != AHD_NEVER_COL_IDX |
5674 | && (scb->col_scb != NULL) |
5675 | && (scb->col_scb->flags & SCB_ACTIVE) == 0) { |
5676 | LIST_REMOVE(scb->col_scb, links.le); |
5677 | ahd_add_col_list(ahd, scb->col_scb, col_idx); |
5678 | } |
5679 | found: |
5680 | scb->flags |= SCB_ACTIVE; |
5681 | return (scb); |
5682 | } |
5683 | |
5684 | /* |
5685 | * Return an SCB resource to the free list. |
5686 | */ |
5687 | void |
5688 | ahd_free_scb(struct ahd_softc *ahd, struct scb *scb) |
5689 | { |
5690 | |
5691 | /* Clean up for the next user */ |
5692 | scb->flags = SCB_FLAG_NONE; |
5693 | scb->hscb->control = 0; |
5694 | ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL; |
5695 | |
5696 | if (scb->col_scb == NULL) { |
5697 | |
5698 | /* |
5699 | * No collision possible. Just free normally. |
5700 | */ |
5701 | LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, |
5702 | scb, links.le); |
5703 | } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) { |
5704 | |
5705 | /* |
5706 | * The SCB we might have collided with is on |
5707 | * a free collision list. Put both SCBs on |
5708 | * the generic list. |
5709 | */ |
5710 | ahd_rem_col_list(ahd, scb->col_scb); |
5711 | LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, |
5712 | scb, links.le); |
5713 | LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, |
5714 | scb->col_scb, links.le); |
5715 | } else if ((scb->col_scb->flags |
5716 | & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE |
5717 | && (scb->col_scb->hscb->control & TAG_ENB) != 0) { |
5718 | |
5719 | /* |
5720 | * The SCB we might collide with on the next allocation |
5721 | * is still active in a non-packetized, tagged, context. |
5722 | * Put us on the SCB collision list. |
5723 | */ |
5724 | ahd_add_col_list(ahd, scb, |
5725 | AHD_GET_SCB_COL_IDX(ahd, scb->col_scb)); |
5726 | } else { |
5727 | /* |
5728 | * The SCB we might collide with on the next allocation |
5729 | * is either active in a packetized context, or free. |
5730 | * Since we can't collide, put this SCB on the generic |
5731 | * free list. |
5732 | */ |
5733 | LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, |
5734 | scb, links.le); |
5735 | } |
5736 | |
5737 | ahd_platform_scb_free(ahd, scb); |
5738 | } |
5739 | |
5740 | int |
5741 | ahd_alloc_scbs(struct ahd_softc *ahd) |
5742 | { |
5743 | struct scb_data *scb_data; |
5744 | struct scb *next_scb; |
5745 | struct hardware_scb *hscb; |
5746 | struct map_node *hscb_map; |
5747 | struct map_node *sg_map; |
5748 | struct map_node *sense_map; |
5749 | uint8_t *segs; |
5750 | uint8_t *sense_data; |
5751 | bus_addr_t hscb_busaddr; |
5752 | bus_addr_t sg_busaddr; |
5753 | bus_addr_t sense_busaddr; |
5754 | int newcount; |
5755 | int i; |
5756 | |
5757 | scb_data = &ahd->scb_data; |
5758 | if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC) |
5759 | /* Can't allocate any more */ |
5760 | return (0); |
5761 | |
5762 | KASSERT(scb_data->scbs_left >= 0); |
5763 | if (scb_data->scbs_left != 0) { |
5764 | int offset; |
5765 | |
5766 | offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left; |
5767 | hscb_map = SLIST_FIRST(&scb_data->hscb_maps); |
5768 | hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset]; |
5769 | hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb)); |
5770 | } else { |
5771 | hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_WAITOK); |
5772 | |
5773 | if (hscb_map == NULL) |
5774 | return (0); |
5775 | |
5776 | memset(hscb_map, 0, sizeof(*hscb_map)); |
5777 | |
5778 | /* Allocate the next batch of hardware SCBs */ |
5779 | if (ahd_createdmamem(ahd->parent_dmat, PAGE_SIZE, |
5780 | ahd->sc_dmaflags, |
5781 | &hscb_map->dmamap, |
5782 | (void **)&hscb_map->vaddr, |
5783 | &hscb_map->physaddr, &hscb_map->dmasegs, |
5784 | &hscb_map->nseg, ahd_name(ahd), |
5785 | "hardware SCB structures" ) < 0) { |
5786 | free(hscb_map, M_DEVBUF); |
5787 | return (0); |
5788 | } |
5789 | |
5790 | SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links); |
5791 | |
5792 | hscb = (struct hardware_scb *)hscb_map->vaddr; |
5793 | hscb_busaddr = hscb_map->physaddr; |
5794 | scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb); |
5795 | } |
5796 | |
5797 | scb_data->init_level++; |
5798 | |
5799 | if (scb_data->sgs_left != 0) { |
5800 | int offset; |
5801 | |
5802 | offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd)) |
5803 | - scb_data->sgs_left) * ahd_sglist_size(ahd); |
5804 | sg_map = SLIST_FIRST(&scb_data->sg_maps); |
5805 | segs = sg_map->vaddr + offset; |
5806 | sg_busaddr = sg_map->physaddr + offset; |
5807 | } else { |
5808 | sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_WAITOK); |
5809 | |
5810 | if (sg_map == NULL) |
5811 | return (0); |
5812 | |
5813 | memset(sg_map, 0, sizeof(*sg_map)); |
5814 | |
5815 | /* Allocate the next batch of S/G lists */ |
5816 | if (ahd_createdmamem(ahd->parent_dmat, |
5817 | ahd_sglist_allocsize(ahd), |
5818 | ahd->sc_dmaflags, |
5819 | &sg_map->dmamap, (void **)&sg_map->vaddr, |
5820 | &sg_map->physaddr, &sg_map->dmasegs, |
5821 | &sg_map->nseg, ahd_name(ahd), |
5822 | "SG data structures" ) < 0) { |
5823 | free(sg_map, M_DEVBUF); |
5824 | return (0); |
5825 | } |
5826 | |
5827 | SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); |
5828 | |
5829 | segs = sg_map->vaddr; |
5830 | sg_busaddr = sg_map->physaddr; |
5831 | scb_data->sgs_left = |
5832 | ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd); |
5833 | #ifdef AHD_DEBUG |
5834 | if (ahd_debug & AHD_SHOW_MEMORY) |
5835 | printf("%s: ahd_alloc_scbs - Mapped SG data\n" , |
5836 | ahd_name(ahd)); |
5837 | #endif |
5838 | } |
5839 | |
5840 | scb_data->init_level++; |
5841 | |
5842 | |
5843 | if (scb_data->sense_left != 0) { |
5844 | int offset; |
5845 | |
5846 | offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left); |
5847 | sense_map = SLIST_FIRST(&scb_data->sense_maps); |
5848 | sense_data = sense_map->vaddr + offset; |
5849 | sense_busaddr = sense_map->physaddr + offset; |
5850 | } else { |
5851 | sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_WAITOK); |
5852 | |
5853 | if (sense_map == NULL) |
5854 | return (0); |
5855 | |
5856 | memset(sense_map, 0, sizeof(*sense_map)); |
5857 | |
5858 | /* Allocate the next batch of sense buffers */ |
5859 | if (ahd_createdmamem(ahd->parent_dmat, PAGE_SIZE, |
5860 | ahd->sc_dmaflags, |
5861 | &sense_map->dmamap, |
5862 | (void **)&sense_map->vaddr, |
5863 | &sense_map->physaddr, &sense_map->dmasegs, |
5864 | &sense_map->nseg, ahd_name(ahd), |
5865 | "Sense Data structures" ) < 0) { |
5866 | free(sense_map, M_DEVBUF); |
5867 | return (0); |
5868 | } |
5869 | |
5870 | SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links); |
5871 | |
5872 | sense_data = sense_map->vaddr; |
5873 | sense_busaddr = sense_map->physaddr; |
5874 | scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE; |
5875 | #ifdef AHD_DEBUG |
5876 | if (ahd_debug & AHD_SHOW_MEMORY) |
5877 | printf("%s: ahd_alloc_scbs - Mapped sense data\n" , |
5878 | ahd_name(ahd)); |
5879 | #endif |
5880 | } |
5881 | |
5882 | scb_data->init_level++; |
5883 | |
5884 | newcount = MIN(scb_data->sense_left, scb_data->scbs_left); |
5885 | newcount = MIN(newcount, scb_data->sgs_left); |
5886 | newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs)); |
5887 | scb_data->sense_left -= newcount; |
5888 | scb_data->scbs_left -= newcount; |
5889 | scb_data->sgs_left -= newcount; |
5890 | |
5891 | for (i = 0; i < newcount; i++) { |
5892 | u_int col_tag; |
5893 | |
5894 | struct scb_platform_data *pdata; |
5895 | #ifndef __linux__ |
5896 | int error; |
5897 | #endif |
5898 | next_scb = malloc(sizeof(*next_scb), M_DEVBUF, M_WAITOK); |
5899 | if (next_scb == NULL) |
5900 | break; |
5901 | |
5902 | pdata = malloc(sizeof(*pdata), M_DEVBUF, M_WAITOK); |
5903 | if (pdata == NULL) { |
5904 | free(next_scb, M_DEVBUF); |
5905 | break; |
5906 | } |
5907 | next_scb->platform_data = pdata; |
5908 | next_scb->hscb_map = hscb_map; |
5909 | next_scb->sg_map = sg_map; |
5910 | next_scb->sense_map = sense_map; |
5911 | next_scb->sg_list = segs; |
5912 | next_scb->sense_data = sense_data; |
5913 | next_scb->sense_busaddr = sense_busaddr; |
5914 | memset(hscb, 0, sizeof(*hscb)); |
5915 | next_scb->hscb = hscb; |
5916 | hscb->hscb_busaddr = ahd_htole32(hscb_busaddr); |
5917 | KASSERT((vaddr_t)hscb >= (vaddr_t)hscb_map->vaddr && |
5918 | (vaddr_t)hscb < (vaddr_t)hscb_map->vaddr + PAGE_SIZE); |
5919 | |
5920 | /* |
5921 | * The sequencer always starts with the second entry. |
5922 | * The first entry is embedded in the scb. |
5923 | */ |
5924 | next_scb->sg_list_busaddr = sg_busaddr; |
5925 | if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) |
5926 | next_scb->sg_list_busaddr |
5927 | += sizeof(struct ahd_dma64_seg); |
5928 | else |
5929 | next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg); |
5930 | next_scb->ahd_softc = ahd; |
5931 | next_scb->flags = SCB_FLAG_NONE; |
5932 | |
5933 | error = bus_dmamap_create(ahd->parent_dmat, |
5934 | AHD_MAXTRANSFER_SIZE, AHD_NSEG, |
5935 | MAXBSIZE, 0, |
5936 | BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW| |
5937 | ahd->sc_dmaflags, |
5938 | &next_scb->dmamap); |
5939 | if (error != 0) { |
5940 | free(next_scb, M_DEVBUF); |
5941 | free(pdata, M_DEVBUF); |
5942 | break; |
5943 | } |
5944 | next_scb->hscb->tag = ahd_htole16(scb_data->numscbs); |
5945 | col_tag = scb_data->numscbs ^ 0x100; |
5946 | next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag); |
5947 | if (next_scb->col_scb != NULL) |
5948 | next_scb->col_scb->col_scb = next_scb; |
5949 | ahd_free_scb(ahd, next_scb); |
5950 | hscb++; |
5951 | hscb_busaddr += sizeof(*hscb); |
5952 | segs += ahd_sglist_size(ahd); |
5953 | sg_busaddr += ahd_sglist_size(ahd); |
5954 | sense_data += AHD_SENSE_BUFSIZE; |
5955 | sense_busaddr += AHD_SENSE_BUFSIZE; |
5956 | scb_data->numscbs++; |
5957 | } |
5958 | return (i); |
5959 | } |
5960 | |
5961 | void |
5962 | ahd_controller_info(struct ahd_softc *ahd, char *tbuf, size_t l) |
5963 | { |
5964 | const char *speed; |
5965 | const char *type; |
5966 | size_t len; |
5967 | |
5968 | len = snprintf(tbuf, l, "%s: " , |
5969 | ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]); |
5970 | if (len > l) |
5971 | return; |
5972 | speed = "Ultra320 " ; |
5973 | if ((ahd->features & AHD_WIDE) != 0) { |
5974 | type = "Wide " ; |
5975 | } else { |
5976 | type = "Single " ; |
5977 | } |
5978 | len += snprintf(tbuf + len, l - len, "%s%sChannel %c, SCSI Id=%d, " , |
5979 | speed, type, ahd->channel, ahd->our_id); |
5980 | if (len > l) |
5981 | return; |
5982 | snprintf(tbuf + len, l - len, "%s, %d SCBs" , ahd->bus_description, |
5983 | ahd->scb_data.maxhscbs); |
5984 | } |
5985 | |
5986 | static const char *channel_strings[] = { |
5987 | "Primary Low" , |
5988 | "Primary High" , |
5989 | "Secondary Low" , |
5990 | "Secondary High" |
5991 | }; |
5992 | |
5993 | static const char *termstat_strings[] = { |
5994 | "Terminated Correctly" , |
5995 | "Over Terminated" , |
5996 | "Under Terminated" , |
5997 | "Not Configured" |
5998 | }; |
5999 | |
6000 | /* |
6001 | * Start the board, ready for normal operation |
6002 | */ |
6003 | int |
6004 | ahd_init(struct ahd_softc *ahd) |
6005 | { |
6006 | uint8_t *next_vaddr; |
6007 | bus_addr_t next_baddr; |
6008 | size_t driver_data_size; |
6009 | int i; |
6010 | int error; |
6011 | u_int warn_user; |
6012 | uint8_t current_sensing; |
6013 | uint8_t fstat; |
6014 | |
6015 | AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); |
6016 | |
6017 | ahd->stack_size = ahd_probe_stack_size(ahd); |
6018 | ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t), |
6019 | M_DEVBUF, M_NOWAIT); |
6020 | if (ahd->saved_stack == NULL) |
6021 | return (ENOMEM); |
6022 | /* Zero the memory */ |
6023 | memset(ahd->saved_stack, 0, ahd->stack_size * sizeof(uint16_t)); |
6024 | |
6025 | /* |
6026 | * Verify that the compiler hasn't over-agressively |
6027 | * padded important structures. |
6028 | */ |
6029 | if (sizeof(struct hardware_scb) != 64) |
6030 | panic("Hardware SCB size is incorrect" ); |
6031 | |
6032 | #ifdef AHD_DEBUG |
6033 | if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0) |
6034 | ahd->flags |= AHD_SEQUENCER_DEBUG; |
6035 | #endif |
6036 | |
6037 | /* |
6038 | * Default to allowing initiator operations. |
6039 | */ |
6040 | ahd->flags |= AHD_INITIATORROLE; |
6041 | |
6042 | /* |
6043 | * Only allow target mode features if this unit has them enabled. |
6044 | */ |
6045 | if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0) |
6046 | ahd->features &= ~AHD_TARGETMODE; |
6047 | |
6048 | /* |
6049 | * DMA tag for our command fifos and other data in system memory |
6050 | * the card's sequencer must be able to access. For initiator |
6051 | * roles, we need to allocate space for the qoutfifo. When providing |
6052 | * for the target mode role, we must additionally provide space for |
6053 | * the incoming target command fifo. |
6054 | */ |
6055 | driver_data_size = AHD_SCB_MAX * sizeof(uint16_t) |
6056 | + sizeof(struct hardware_scb); |
6057 | if ((ahd->features & AHD_TARGETMODE) != 0) |
6058 | driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd); |
6059 | if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) |
6060 | driver_data_size += PKT_OVERRUN_BUFSIZE; |
6061 | ahd->shared_data_size = driver_data_size; |
6062 | |
6063 | memset(&ahd->shared_data_map, 0, sizeof(ahd->shared_data_map)); |
6064 | ahd->sc_dmaflags = BUS_DMA_NOWAIT; |
6065 | |
6066 | if (ahd_createdmamem(ahd->parent_dmat, ahd->shared_data_size, |
6067 | ahd->sc_dmaflags, |
6068 | &ahd->shared_data_map.dmamap, |
6069 | (void **)&ahd->shared_data_map.vaddr, |
6070 | &ahd->shared_data_map.physaddr, |
6071 | &ahd->shared_data_map.dmasegs, |
6072 | &ahd->shared_data_map.nseg, ahd_name(ahd), |
6073 | "shared data" ) < 0) |
6074 | return (ENOMEM); |
6075 | ahd->qoutfifo = (void *) ahd->shared_data_map.vaddr; |
6076 | |
6077 | ahd->init_level++; |
6078 | |
6079 | next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE]; |
6080 | next_baddr = ahd->shared_data_map.physaddr + |
6081 | AHD_QOUT_SIZE * sizeof(uint16_t); |
6082 | if ((ahd->features & AHD_TARGETMODE) != 0) { |
6083 | ahd->targetcmds = (struct target_cmd *)next_vaddr; |
6084 | next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); |
6085 | next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); |
6086 | } |
6087 | |
6088 | if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) { |
6089 | ahd->overrun_buf = next_vaddr; |
6090 | next_vaddr += PKT_OVERRUN_BUFSIZE; |
6091 | next_baddr += PKT_OVERRUN_BUFSIZE; |
6092 | } |
6093 | |
6094 | /* |
6095 | * We need one SCB to serve as the "next SCB". Since the |
6096 | * tag identifier in this SCB will never be used, there is |
6097 | * no point in using a valid HSCB tag from an SCB pulled from |
6098 | * the standard free pool. So, we allocate this "sentinel" |
6099 | * specially from the DMA safe memory chunk used for the QOUTFIFO. |
6100 | */ |
6101 | ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr; |
6102 | ahd->next_queued_hscb_map = &ahd->shared_data_map; |
6103 | ahd->next_queued_hscb->hscb_busaddr = ahd_htole32(next_baddr); |
6104 | |
6105 | memset(&ahd->scb_data, 0, sizeof(struct scb_data)); |
6106 | |
6107 | /* Allocate SCB data now that parent_dmat is initialized */ |
6108 | if (ahd_init_scbdata(ahd) != 0) |
6109 | return (ENOMEM); |
6110 | |
6111 | if ((ahd->flags & AHD_INITIATORROLE) == 0) |
6112 | ahd->flags &= ~AHD_RESET_BUS_A; |
6113 | |
6114 | /* |
6115 | * Before committing these settings to the chip, give |
6116 | * the OSM one last chance to modify our configuration. |
6117 | */ |
6118 | ahd_platform_init(ahd); |
6119 | |
6120 | /* Bring up the chip. */ |
6121 | ahd_chip_init(ahd); |
6122 | |
6123 | AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); |
6124 | |
6125 | if ((ahd->flags & AHD_CURRENT_SENSING) == 0) |
6126 | goto init_done; |
6127 | |
6128 | /* |
6129 | * Verify termination based on current draw and |
6130 | * warn user if the bus is over/under terminated. |
6131 | */ |
6132 | error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, |
6133 | CURSENSE_ENB); |
6134 | if (error != 0) { |
6135 | printf("%s: current sensing timeout 1\n" , ahd_name(ahd)); |
6136 | goto init_done; |
6137 | } |
6138 | for (i = 20, fstat = FLX_FSTAT_BUSY; |
6139 | (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) { |
6140 | error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat); |
6141 | if (error != 0) { |
6142 | printf("%s: current sensing timeout 2\n" , |
6143 | ahd_name(ahd)); |
6144 | goto init_done; |
6145 | } |
6146 | } |
6147 | if (i == 0) { |
6148 | printf("%s: Timedout during current-sensing test\n" , |
6149 | ahd_name(ahd)); |
6150 | goto init_done; |
6151 | } |
6152 | |
6153 | /* Latch Current Sensing status. */ |
6154 | error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing); |
6155 | if (error != 0) { |
6156 | printf("%s: current sensing timeout 3\n" , ahd_name(ahd)); |
6157 | goto init_done; |
6158 | } |
6159 | |
6160 | /* Diable current sensing. */ |
6161 | ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); |
6162 | |
6163 | #ifdef AHD_DEBUG |
6164 | if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) { |
6165 | printf("%s: current_sensing == 0x%x\n" , |
6166 | ahd_name(ahd), current_sensing); |
6167 | } |
6168 | #endif |
6169 | warn_user = 0; |
6170 | for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) { |
6171 | u_int term_stat; |
6172 | |
6173 | term_stat = (current_sensing & FLX_CSTAT_MASK); |
6174 | switch (term_stat) { |
6175 | case FLX_CSTAT_OVER: |
6176 | case FLX_CSTAT_UNDER: |
6177 | warn_user++; |
6178 | case FLX_CSTAT_INVALID: |
6179 | case FLX_CSTAT_OKAY: |
6180 | if (warn_user == 0 && bootverbose == 0) |
6181 | break; |
6182 | printf("%s: %s Channel %s\n" , ahd_name(ahd), |
6183 | channel_strings[i], termstat_strings[term_stat]); |
6184 | break; |
6185 | } |
6186 | } |
6187 | if (warn_user) { |
6188 | printf("%s: WARNING. Termination is not configured correctly.\n" |
6189 | "%s: WARNING. SCSI bus operations may FAIL.\n" , |
6190 | ahd_name(ahd), ahd_name(ahd)); |
6191 | } |
6192 | init_done: |
6193 | ahd_reset_current_bus(ahd); |
6194 | ahd_restart(ahd); |
6195 | ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, |
6196 | ahd_stat_timer, ahd); |
6197 | |
6198 | return (0); |
6199 | } |
6200 | |
6201 | /* |
6202 | * (Re)initialize chip state after a chip reset. |
6203 | */ |
6204 | static void |
6205 | ahd_chip_init(struct ahd_softc *ahd) |
6206 | { |
6207 | uint32_t busaddr; |
6208 | u_int sxfrctl1; |
6209 | u_int scsiseq_template; |
6210 | u_int wait; |
6211 | u_int i; |
6212 | u_int target; |
6213 | |
6214 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
6215 | /* |
6216 | * Take the LED out of diagnostic mode |
6217 | */ |
6218 | ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON)); |
6219 | |
6220 | /* |
6221 | * Return HS_MAILBOX to its default value. |
6222 | */ |
6223 | ahd->hs_mailbox = 0; |
6224 | ahd_outb(ahd, HS_MAILBOX, 0); |
6225 | |
6226 | /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */ |
6227 | ahd_outb(ahd, IOWNID, ahd->our_id); |
6228 | ahd_outb(ahd, TOWNID, ahd->our_id); |
6229 | sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0; |
6230 | sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0; |
6231 | if ((ahd->bugs & AHD_LONG_SETIMO_BUG) |
6232 | && (ahd->seltime != STIMESEL_MIN)) { |
6233 | /* |
6234 | * The selection timer duration is twice as long |
6235 | * as it should be. Halve it by adding "1" to |
6236 | * the user specified setting. |
6237 | */ |
6238 | sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ; |
6239 | } else { |
6240 | sxfrctl1 |= ahd->seltime; |
6241 | } |
6242 | |
6243 | ahd_outb(ahd, SXFRCTL0, DFON); |
6244 | ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN); |
6245 | ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); |
6246 | |
6247 | /* |
6248 | * Now that termination is set, wait for up |
6249 | * to 500ms for our transceivers to settle. If |
6250 | * the adapter does not have a cable attached, |
6251 | * the transceivers may never settle, so don't |
6252 | * complain if we fail here. |
6253 | */ |
6254 | for (wait = 10000; |
6255 | (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; |
6256 | wait--) |
6257 | ahd_delay(100); |
6258 | |
6259 | /* Clear any false bus resets due to the transceivers settling */ |
6260 | ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); |
6261 | ahd_outb(ahd, CLRINT, CLRSCSIINT); |
6262 | |
6263 | /* Initialize mode specific S/G state. */ |
6264 | for (i = 0; i < 2; i++) { |
6265 | ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); |
6266 | ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); |
6267 | ahd_outb(ahd, SG_STATE, 0); |
6268 | ahd_outb(ahd, CLRSEQINTSRC, 0xFF); |
6269 | ahd_outb(ahd, SEQIMODE, |
6270 | ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT |
6271 | |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD); |
6272 | } |
6273 | |
6274 | ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); |
6275 | ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN); |
6276 | ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); |
6277 | ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN); |
6278 | ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR); |
6279 | if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) { |
6280 | ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE); |
6281 | } else { |
6282 | ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE); |
6283 | } |
6284 | ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS); |
6285 | if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX) |
6286 | /* |
6287 | * Do not issue a target abort when a split completion |
6288 | * error occurs. Let our PCIX interrupt handler deal |
6289 | * with it instead. H2A4 Razor #625 |
6290 | */ |
6291 | ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS); |
6292 | |
6293 | if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0) |
6294 | ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER); |
6295 | |
6296 | /* |
6297 | * Tweak IOCELL settings. |
6298 | */ |
6299 | if ((ahd->flags & AHD_HP_BOARD) != 0) { |
6300 | for (i = 0; i < NUMDSPS; i++) { |
6301 | ahd_outb(ahd, DSPSELECT, i); |
6302 | ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT); |
6303 | } |
6304 | #ifdef AHD_DEBUG |
6305 | if ((ahd_debug & AHD_SHOW_MISC) != 0) |
6306 | printf("%s: WRTBIASCTL now 0x%x\n" , ahd_name(ahd), |
6307 | WRTBIASCTL_HP_DEFAULT); |
6308 | #endif |
6309 | } |
6310 | ahd_setup_iocell_workaround(ahd); |
6311 | |
6312 | /* |
6313 | * Enable LQI Manager interrupts. |
6314 | */ |
6315 | ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT |
6316 | | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI |
6317 | | ENLQIOVERI_LQ|ENLQIOVERI_NLQ); |
6318 | ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC); |
6319 | /* |
6320 | * An interrupt from LQOBUSFREE is made redundant by the |
6321 | * BUSFREE interrupt. We choose to have the sequencer catch |
6322 | * LQOPHCHGINPKT errors manually for the command phase at the |
6323 | * start of a packetized selection case. |
6324 | ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE|ENLQOPHACHGINPKT); |
6325 | */ |
6326 | ahd_outb(ahd, LQOMODE1, 0); |
6327 | |
6328 | /* |
6329 | * Setup sequencer interrupt handlers. |
6330 | */ |
6331 | ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr)); |
6332 | ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr)); |
6333 | |
6334 | /* |
6335 | * Setup SCB Offset registers. |
6336 | */ |
6337 | if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { |
6338 | ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, |
6339 | pkt_long_lun)); |
6340 | } else { |
6341 | ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun)); |
6342 | } |
6343 | ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len)); |
6344 | ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute)); |
6345 | ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management)); |
6346 | ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb, |
6347 | shared_data.idata.cdb)); |
6348 | ahd_outb(ahd, QNEXTPTR, |
6349 | offsetof(struct hardware_scb, next_hscb_busaddr)); |
6350 | ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET); |
6351 | ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control)); |
6352 | if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { |
6353 | ahd_outb(ahd, LUNLEN, |
6354 | sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1); |
6355 | } else { |
6356 | ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN); |
6357 | } |
6358 | ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1); |
6359 | ahd_outb(ahd, MAXCMD, 0xFF); |
6360 | ahd_outb(ahd, SCBAUTOPTR, |
6361 | AUSCBPTR_EN | offsetof(struct hardware_scb, tag)); |
6362 | |
6363 | /* We haven't been enabled for target mode yet. */ |
6364 | ahd_outb(ahd, MULTARGID, 0); |
6365 | ahd_outb(ahd, MULTARGID + 1, 0); |
6366 | |
6367 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
6368 | /* Initialize the negotiation table. */ |
6369 | if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) { |
6370 | /* |
6371 | * Clear the spare bytes in the neg table to avoid |
6372 | * spurious parity errors. |
6373 | */ |
6374 | for (target = 0; target < AHD_NUM_TARGETS; target++) { |
6375 | ahd_outb(ahd, NEGOADDR, target); |
6376 | ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0); |
6377 | for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++) |
6378 | ahd_outb(ahd, ANNEXDAT, 0); |
6379 | } |
6380 | } |
6381 | |
6382 | for (target = 0; target < AHD_NUM_TARGETS; target++) { |
6383 | struct ahd_devinfo devinfo; |
6384 | struct ahd_initiator_tinfo *tinfo; |
6385 | struct ahd_tmode_tstate *tstate; |
6386 | |
6387 | tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, |
6388 | target, &tstate); |
6389 | ahd_compile_devinfo(&devinfo, ahd->our_id, |
6390 | target, CAM_LUN_WILDCARD, |
6391 | 'A', ROLE_INITIATOR); |
6392 | ahd_update_neg_table(ahd, &devinfo, &tinfo->curr); |
6393 | } |
6394 | |
6395 | ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR); |
6396 | ahd_outb(ahd, CLRINT, CLRSCSIINT); |
6397 | |
6398 | #if NEEDS_MORE_TESTING |
6399 | /* |
6400 | * Always enable abort on incoming L_Qs if this feature is |
6401 | * supported. We use this to catch invalid SCB references. |
6402 | */ |
6403 | if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0) |
6404 | ahd_outb(ahd, LQCTL1, ABORTPENDING); |
6405 | else |
6406 | #endif |
6407 | ahd_outb(ahd, LQCTL1, 0); |
6408 | |
6409 | /* All of our queues are empty */ |
6410 | ahd->qoutfifonext = 0; |
6411 | ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID_LE; |
6412 | ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID >> 8); |
6413 | for (i = 0; i < AHD_QOUT_SIZE; i++) |
6414 | ahd->qoutfifo[i] = 0; |
6415 | ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD); |
6416 | |
6417 | ahd->qinfifonext = 0; |
6418 | for (i = 0; i < AHD_QIN_SIZE; i++) |
6419 | ahd->qinfifo[i] = SCB_LIST_NULL; |
6420 | |
6421 | if ((ahd->features & AHD_TARGETMODE) != 0) { |
6422 | /* All target command blocks start out invalid. */ |
6423 | for (i = 0; i < AHD_TMODE_CMDS; i++) |
6424 | ahd->targetcmds[i].cmd_valid = 0; |
6425 | ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD); |
6426 | ahd->tqinfifonext = 1; |
6427 | ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1); |
6428 | ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); |
6429 | } |
6430 | |
6431 | /* Initialize Scratch Ram. */ |
6432 | ahd_outb(ahd, SEQ_FLAGS, 0); |
6433 | ahd_outb(ahd, SEQ_FLAGS2, 0); |
6434 | |
6435 | /* We don't have any waiting selections */ |
6436 | ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL); |
6437 | ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL); |
6438 | for (i = 0; i < AHD_NUM_TARGETS; i++) { |
6439 | ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL); |
6440 | } |
6441 | |
6442 | /* |
6443 | * Nobody is waiting to be DMAed into the QOUTFIFO. |
6444 | */ |
6445 | ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); |
6446 | ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL); |
6447 | ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); |
6448 | |
6449 | /* |
6450 | * The Freeze Count is 0. |
6451 | */ |
6452 | ahd_outw(ahd, QFREEZE_COUNT, 0); |
6453 | |
6454 | /* |
6455 | * Tell the sequencer where it can find our arrays in memory. |
6456 | */ |
6457 | busaddr = ahd->shared_data_map.physaddr; |
6458 | ahd_outb(ahd, SHARED_DATA_ADDR, busaddr & 0xFF); |
6459 | ahd_outb(ahd, SHARED_DATA_ADDR + 1, (busaddr >> 8) & 0xFF); |
6460 | ahd_outb(ahd, SHARED_DATA_ADDR + 2, (busaddr >> 16) & 0xFF); |
6461 | ahd_outb(ahd, SHARED_DATA_ADDR + 3, (busaddr >> 24) & 0xFF); |
6462 | ahd_outb(ahd, QOUTFIFO_NEXT_ADDR, busaddr & 0xFF); |
6463 | ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 1, (busaddr >> 8) & 0xFF); |
6464 | ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 2, (busaddr >> 16) & 0xFF); |
6465 | ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 3, (busaddr >> 24) & 0xFF); |
6466 | /* |
6467 | * Setup the allowed SCSI Sequences based on operational mode. |
6468 | * If we are a target, we'll enable select in operations once |
6469 | * we've had a lun enabled. |
6470 | */ |
6471 | scsiseq_template = ENAUTOATNP; |
6472 | if ((ahd->flags & AHD_INITIATORROLE) != 0) |
6473 | scsiseq_template |= ENRSELI; |
6474 | ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template); |
6475 | |
6476 | /* There are no busy SCBs yet. */ |
6477 | for (target = 0; target < AHD_NUM_TARGETS; target++) { |
6478 | int lun; |
6479 | |
6480 | for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++) |
6481 | ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun)); |
6482 | } |
6483 | |
6484 | /* |
6485 | * Initialize the group code to command length table. |
6486 | * Vendor Unique codes are set to 0 so we only capture |
6487 | * the first byte of the cdb. These can be overridden |
6488 | * when target mode is enabled. |
6489 | */ |
6490 | ahd_outb(ahd, CMDSIZE_TABLE, 5); |
6491 | ahd_outb(ahd, CMDSIZE_TABLE + 1, 9); |
6492 | ahd_outb(ahd, CMDSIZE_TABLE + 2, 9); |
6493 | ahd_outb(ahd, CMDSIZE_TABLE + 3, 0); |
6494 | ahd_outb(ahd, CMDSIZE_TABLE + 4, 15); |
6495 | ahd_outb(ahd, CMDSIZE_TABLE + 5, 11); |
6496 | ahd_outb(ahd, CMDSIZE_TABLE + 6, 0); |
6497 | ahd_outb(ahd, CMDSIZE_TABLE + 7, 0); |
6498 | |
6499 | /* Tell the sequencer of our initial queue positions */ |
6500 | ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); |
6501 | ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512); |
6502 | ahd->qinfifonext = 0; |
6503 | ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); |
6504 | ahd_set_hescb_qoff(ahd, 0); |
6505 | ahd_set_snscb_qoff(ahd, 0); |
6506 | ahd_set_sescb_qoff(ahd, 0); |
6507 | ahd_set_sdscb_qoff(ahd, 0); |
6508 | |
6509 | /* |
6510 | * Tell the sequencer which SCB will be the next one it receives. |
6511 | */ |
6512 | busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); |
6513 | ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); |
6514 | ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); |
6515 | ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); |
6516 | ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); |
6517 | |
6518 | /* |
6519 | * Default to coalescing disabled. |
6520 | */ |
6521 | ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0); |
6522 | ahd_outw(ahd, CMDS_PENDING, 0); |
6523 | ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer, |
6524 | ahd->int_coalescing_maxcmds, |
6525 | ahd->int_coalescing_mincmds); |
6526 | ahd_enable_coalescing(ahd, FALSE); |
6527 | |
6528 | ahd_loadseq(ahd); |
6529 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
6530 | } |
6531 | |
6532 | /* |
6533 | * Setup default device and controller settings. |
6534 | * This should only be called if our probe has |
6535 | * determined that no configuration data is available. |
6536 | */ |
6537 | int |
6538 | ahd_default_config(struct ahd_softc *ahd) |
6539 | { |
6540 | int targ; |
6541 | |
6542 | ahd->our_id = 7; |
6543 | |
6544 | /* |
6545 | * Allocate a tstate to house information for our |
6546 | * initiator presence on the bus as well as the user |
6547 | * data for any target mode initiator. |
6548 | */ |
6549 | if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { |
6550 | printf("%s: unable to allocate ahd_tmode_tstate. " |
6551 | "Failing attach\n" , ahd_name(ahd)); |
6552 | return (ENOMEM); |
6553 | } |
6554 | |
6555 | for (targ = 0; targ < AHD_NUM_TARGETS; targ++) { |
6556 | struct ahd_devinfo devinfo; |
6557 | struct ahd_initiator_tinfo *tinfo; |
6558 | struct ahd_tmode_tstate *tstate; |
6559 | uint16_t target_mask; |
6560 | |
6561 | tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, |
6562 | targ, &tstate); |
6563 | /* |
6564 | * We support SPC2 and SPI4. |
6565 | */ |
6566 | tinfo->user.protocol_version = 4; |
6567 | tinfo->user.transport_version = 4; |
6568 | |
6569 | target_mask = 0x01 << targ; |
6570 | ahd->user_discenable |= target_mask; |
6571 | tstate->discenable |= target_mask; |
6572 | ahd->user_tagenable |= target_mask; |
6573 | #ifdef AHD_FORCE_160 |
6574 | tinfo->user.period = AHD_SYNCRATE_DT; |
6575 | #else |
6576 | tinfo->user.period = AHD_SYNCRATE_160; |
6577 | #endif |
6578 | tinfo->user.offset= MAX_OFFSET; |
6579 | tinfo->user.ppr_options = MSG_EXT_PPR_RDSTRM |
6580 | | MSG_EXT_PPR_WRFLOW |
6581 | | MSG_EXT_PPR_HOLDMCS |
6582 | | MSG_EXT_PPR_IU_REQ |
6583 | | MSG_EXT_PPR_QAS_REQ |
6584 | | MSG_EXT_PPR_DT_REQ; |
6585 | if ((ahd->features & AHD_RTI) != 0) |
6586 | tinfo->user.ppr_options |= MSG_EXT_PPR_RTI; |
6587 | |
6588 | tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; |
6589 | |
6590 | /* |
6591 | * Start out Async/Narrow/Untagged and with |
6592 | * conservative protocol support. |
6593 | */ |
6594 | tinfo->goal.protocol_version = 2; |
6595 | tinfo->goal.transport_version = 2; |
6596 | tinfo->curr.protocol_version = 2; |
6597 | tinfo->curr.transport_version = 2; |
6598 | ahd_compile_devinfo(&devinfo, ahd->our_id, |
6599 | targ, CAM_LUN_WILDCARD, |
6600 | 'A', ROLE_INITIATOR); |
6601 | tstate->tagenable &= ~target_mask; |
6602 | ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, |
6603 | AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); |
6604 | ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, |
6605 | /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, |
6606 | /*paused*/TRUE); |
6607 | } |
6608 | return (0); |
6609 | } |
6610 | |
6611 | /* |
6612 | * Parse device configuration information. |
6613 | */ |
6614 | int |
6615 | ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc) |
6616 | { |
6617 | int targ; |
6618 | int max_targ; |
6619 | |
6620 | max_targ = sc->max_targets & CFMAXTARG; |
6621 | ahd->our_id = sc->brtime_id & CFSCSIID; |
6622 | |
6623 | /* |
6624 | * Allocate a tstate to house information for our |
6625 | * initiator presence on the bus as well as the user |
6626 | * data for any target mode initiator. |
6627 | */ |
6628 | if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { |
6629 | printf("%s: unable to allocate ahd_tmode_tstate. " |
6630 | "Failing attach\n" , ahd_name(ahd)); |
6631 | return (ENOMEM); |
6632 | } |
6633 | |
6634 | for (targ = 0; targ < max_targ; targ++) { |
6635 | struct ahd_devinfo devinfo; |
6636 | struct ahd_initiator_tinfo *tinfo; |
6637 | struct ahd_transinfo *user_tinfo; |
6638 | struct ahd_tmode_tstate *tstate; |
6639 | uint16_t target_mask; |
6640 | |
6641 | tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, |
6642 | targ, &tstate); |
6643 | user_tinfo = &tinfo->user; |
6644 | |
6645 | /* |
6646 | * We support SPC2 and SPI4. |
6647 | */ |
6648 | tinfo->user.protocol_version = 4; |
6649 | tinfo->user.transport_version = 4; |
6650 | |
6651 | target_mask = 0x01 << targ; |
6652 | ahd->user_discenable &= ~target_mask; |
6653 | tstate->discenable &= ~target_mask; |
6654 | ahd->user_tagenable &= ~target_mask; |
6655 | if (sc->device_flags[targ] & CFDISC) { |
6656 | tstate->discenable |= target_mask; |
6657 | ahd->user_discenable |= target_mask; |
6658 | ahd->user_tagenable |= target_mask; |
6659 | } else { |
6660 | /* |
6661 | * Cannot be packetized without disconnection. |
6662 | */ |
6663 | sc->device_flags[targ] &= ~CFPACKETIZED; |
6664 | } |
6665 | |
6666 | user_tinfo->ppr_options = 0; |
6667 | user_tinfo->period = (sc->device_flags[targ] & CFXFER); |
6668 | if (user_tinfo->period < CFXFER_ASYNC) { |
6669 | if (user_tinfo->period <= AHD_PERIOD_10MHz) |
6670 | user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ; |
6671 | user_tinfo->offset = MAX_OFFSET; |
6672 | } else { |
6673 | user_tinfo->offset = 0; |
6674 | user_tinfo->period = AHD_ASYNC_XFER_PERIOD; |
6675 | } |
6676 | #ifdef AHD_FORCE_160 |
6677 | if (user_tinfo->period <= AHD_SYNCRATE_160) |
6678 | user_tinfo->period = AHD_SYNCRATE_DT; |
6679 | #endif |
6680 | |
6681 | if ((sc->device_flags[targ] & CFPACKETIZED) != 0) { |
6682 | user_tinfo->ppr_options |= MSG_EXT_PPR_RDSTRM |
6683 | | MSG_EXT_PPR_WRFLOW |
6684 | | MSG_EXT_PPR_HOLDMCS |
6685 | | MSG_EXT_PPR_IU_REQ; |
6686 | if ((ahd->features & AHD_RTI) != 0) |
6687 | user_tinfo->ppr_options |= MSG_EXT_PPR_RTI; |
6688 | } |
6689 | |
6690 | if ((sc->device_flags[targ] & CFQAS) != 0) |
6691 | user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ; |
6692 | |
6693 | if ((sc->device_flags[targ] & CFWIDEB) != 0) |
6694 | user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT; |
6695 | else |
6696 | user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT; |
6697 | #ifdef AHD_DEBUG |
6698 | if ((ahd_debug & AHD_SHOW_MISC) != 0) |
6699 | printf("(%d): %x:%x:%x:%x\n" , targ, user_tinfo->width, |
6700 | user_tinfo->period, user_tinfo->offset, |
6701 | user_tinfo->ppr_options); |
6702 | #endif |
6703 | /* |
6704 | * Start out Async/Narrow/Untagged and with |
6705 | * conservative protocol support. |
6706 | */ |
6707 | tstate->tagenable &= ~target_mask; |
6708 | tinfo->goal.protocol_version = 2; |
6709 | tinfo->goal.transport_version = 2; |
6710 | tinfo->curr.protocol_version = 2; |
6711 | tinfo->curr.transport_version = 2; |
6712 | ahd_compile_devinfo(&devinfo, ahd->our_id, |
6713 | targ, CAM_LUN_WILDCARD, |
6714 | 'A', ROLE_INITIATOR); |
6715 | ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, |
6716 | AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); |
6717 | ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, |
6718 | /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, |
6719 | /*paused*/TRUE); |
6720 | } |
6721 | |
6722 | ahd->flags &= ~AHD_SPCHK_ENB_A; |
6723 | if (sc->bios_control & CFSPARITY) |
6724 | ahd->flags |= AHD_SPCHK_ENB_A; |
6725 | |
6726 | ahd->flags &= ~AHD_RESET_BUS_A; |
6727 | if (sc->bios_control & CFRESETB) |
6728 | ahd->flags |= AHD_RESET_BUS_A; |
6729 | |
6730 | ahd->flags &= ~AHD_EXTENDED_TRANS_A; |
6731 | if (sc->bios_control & CFEXTEND) |
6732 | ahd->flags |= AHD_EXTENDED_TRANS_A; |
6733 | |
6734 | ahd->flags &= ~AHD_BIOS_ENABLED; |
6735 | if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED) |
6736 | ahd->flags |= AHD_BIOS_ENABLED; |
6737 | |
6738 | ahd->flags &= ~AHD_STPWLEVEL_A; |
6739 | if ((sc->adapter_control & CFSTPWLEVEL) != 0) |
6740 | ahd->flags |= AHD_STPWLEVEL_A; |
6741 | |
6742 | return (0); |
6743 | } |
6744 | |
6745 | /* |
6746 | * Parse device configuration information. |
6747 | */ |
6748 | int |
6749 | ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd) |
6750 | { |
6751 | int error; |
6752 | |
6753 | error = ahd_verify_vpd_cksum(vpd); |
6754 | if (error == 0) |
6755 | return (EINVAL); |
6756 | if ((vpd->bios_flags & VPDBOOTHOST) != 0) |
6757 | ahd->flags |= AHD_BOOT_CHANNEL; |
6758 | return (0); |
6759 | } |
6760 | |
6761 | void |
6762 | ahd_intr_enable(struct ahd_softc *ahd, int enable) |
6763 | { |
6764 | u_int hcntrl; |
6765 | |
6766 | hcntrl = ahd_inb(ahd, HCNTRL); |
6767 | hcntrl &= ~INTEN; |
6768 | ahd->pause &= ~INTEN; |
6769 | ahd->unpause &= ~INTEN; |
6770 | if (enable) { |
6771 | hcntrl |= INTEN; |
6772 | ahd->pause |= INTEN; |
6773 | ahd->unpause |= INTEN; |
6774 | } |
6775 | ahd_outb(ahd, HCNTRL, hcntrl); |
6776 | } |
6777 | |
6778 | void |
6779 | ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds, |
6780 | u_int mincmds) |
6781 | { |
6782 | if (timer > AHD_TIMER_MAX_US) |
6783 | timer = AHD_TIMER_MAX_US; |
6784 | ahd->int_coalescing_timer = timer; |
6785 | |
6786 | if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX) |
6787 | maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX; |
6788 | if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX) |
6789 | mincmds = AHD_INT_COALESCING_MINCMDS_MAX; |
6790 | ahd->int_coalescing_maxcmds = maxcmds; |
6791 | ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK); |
6792 | ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds); |
6793 | ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds); |
6794 | } |
6795 | |
6796 | void |
6797 | ahd_enable_coalescing(struct ahd_softc *ahd, int enable) |
6798 | { |
6799 | |
6800 | ahd->hs_mailbox &= ~ENINT_COALESCE; |
6801 | if (enable) |
6802 | ahd->hs_mailbox |= ENINT_COALESCE; |
6803 | ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox); |
6804 | ahd_flush_device_writes(ahd); |
6805 | ahd_run_qoutfifo(ahd); |
6806 | } |
6807 | |
6808 | /* |
6809 | * Ensure that the card is paused in a location |
6810 | * outside of all critical sections and that all |
6811 | * pending work is completed prior to returning. |
6812 | * This routine should only be called from outside |
6813 | * an interrupt context. |
6814 | */ |
6815 | void |
6816 | ahd_pause_and_flushwork(struct ahd_softc *ahd) |
6817 | { |
6818 | u_int intstat; |
6819 | u_int maxloops; |
6820 | u_int qfreeze_cnt; |
6821 | |
6822 | maxloops = 1000; |
6823 | ahd->flags |= AHD_ALL_INTERRUPTS; |
6824 | ahd_pause(ahd); |
6825 | /* |
6826 | * Increment the QFreeze Count so that the sequencer |
6827 | * will not start new selections. We do this only |
6828 | * until we are safely paused without further selections |
6829 | * pending. |
6830 | */ |
6831 | ahd_outw(ahd, QFREEZE_COUNT, ahd_inw(ahd, QFREEZE_COUNT) + 1); |
6832 | ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN); |
6833 | do { |
6834 | struct scb *waiting_scb; |
6835 | |
6836 | ahd_unpause(ahd); |
6837 | ahd_intr(ahd); |
6838 | ahd_pause(ahd); |
6839 | ahd_clear_critical_section(ahd); |
6840 | intstat = ahd_inb(ahd, INTSTAT); |
6841 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
6842 | if ((ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0) |
6843 | ahd_outb(ahd, SCSISEQ0, |
6844 | ahd_inb(ahd, SCSISEQ0) & ~ENSELO); |
6845 | /* |
6846 | * In the non-packetized case, the sequencer (for Rev A), |
6847 | * relies on ENSELO remaining set after SELDO. The hardware |
6848 | * auto-clears ENSELO in the packetized case. |
6849 | */ |
6850 | waiting_scb = ahd_lookup_scb(ahd, |
6851 | ahd_inw(ahd, WAITING_TID_HEAD)); |
6852 | if (waiting_scb != NULL |
6853 | && (waiting_scb->flags & SCB_PACKETIZED) == 0 |
6854 | && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0) |
6855 | ahd_outb(ahd, SCSISEQ0, |
6856 | ahd_inb(ahd, SCSISEQ0) | ENSELO); |
6857 | } while (--maxloops |
6858 | && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0) |
6859 | && ((intstat & INT_PEND) != 0 |
6860 | || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 |
6861 | || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0)); |
6862 | if (maxloops == 0) { |
6863 | printf("Infinite interrupt loop, INTSTAT = %x" , |
6864 | ahd_inb(ahd, INTSTAT)); |
6865 | } |
6866 | qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); |
6867 | if (qfreeze_cnt == 0) { |
6868 | printf("%s: ahd_pause_and_flushwork with 0 qfreeze count!\n" , |
6869 | ahd_name(ahd)); |
6870 | } else { |
6871 | qfreeze_cnt--; |
6872 | } |
6873 | ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); |
6874 | if (qfreeze_cnt == 0) |
6875 | ahd_outb(ahd, SEQ_FLAGS2, |
6876 | ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); |
6877 | |
6878 | ahd_flush_qoutfifo(ahd); |
6879 | |
6880 | ahd_platform_flushwork(ahd); |
6881 | ahd->flags &= ~AHD_ALL_INTERRUPTS; |
6882 | } |
6883 | |
6884 | int |
6885 | ahd_suspend(struct ahd_softc *ahd) |
6886 | { |
6887 | |
6888 | ahd_pause_and_flushwork(ahd); |
6889 | |
6890 | if (LIST_FIRST(&ahd->pending_scbs) != NULL) { |
6891 | ahd_unpause(ahd); |
6892 | return (EBUSY); |
6893 | } |
6894 | ahd_shutdown(ahd); |
6895 | return (0); |
6896 | } |
6897 | |
6898 | int |
6899 | ahd_resume(struct ahd_softc *ahd) |
6900 | { |
6901 | |
6902 | ahd_reset(ahd, /*reinit*/TRUE); |
6903 | ahd_intr_enable(ahd, TRUE); |
6904 | ahd_restart(ahd); |
6905 | return (0); |
6906 | } |
6907 | |
6908 | /************************** Busy Target Table *********************************/ |
6909 | /* |
6910 | * Set SCBPTR to the SCB that contains the busy |
6911 | * table entry for TCL. Return the offset into |
6912 | * the SCB that contains the entry for TCL. |
6913 | * saved_scbid is dereferenced and set to the |
6914 | * scbid that should be restored once manipualtion |
6915 | * of the TCL entry is complete. |
6916 | */ |
6917 | static inline u_int |
6918 | ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl) |
6919 | { |
6920 | /* |
6921 | * Index to the SCB that contains the busy entry. |
6922 | */ |
6923 | AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); |
6924 | *saved_scbid = ahd_get_scbptr(ahd); |
6925 | ahd_set_scbptr(ahd, TCL_LUN(tcl) |
6926 | | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4)); |
6927 | |
6928 | /* |
6929 | * And now calculate the SCB offset to the entry. |
6930 | * Each entry is 2 bytes wide, hence the |
6931 | * multiplication by 2. |
6932 | */ |
6933 | return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS); |
6934 | } |
6935 | |
6936 | /* |
6937 | * Return the untagged transaction id for a given target/channel lun. |
6938 | */ |
6939 | u_int |
6940 | ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl) |
6941 | { |
6942 | u_int scbid; |
6943 | u_int scb_offset; |
6944 | u_int saved_scbptr; |
6945 | |
6946 | scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); |
6947 | scbid = ahd_inw_scbram(ahd, scb_offset); |
6948 | ahd_set_scbptr(ahd, saved_scbptr); |
6949 | return (scbid); |
6950 | } |
6951 | |
6952 | void |
6953 | ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid) |
6954 | { |
6955 | u_int scb_offset; |
6956 | u_int saved_scbptr; |
6957 | |
6958 | scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); |
6959 | ahd_outw(ahd, scb_offset, scbid); |
6960 | ahd_set_scbptr(ahd, saved_scbptr); |
6961 | } |
6962 | |
6963 | /************************** SCB and SCB queue management **********************/ |
6964 | int |
6965 | ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target, |
6966 | char channel, int lun, u_int tag, role_t role) |
6967 | { |
6968 | int targ = SCB_GET_TARGET(ahd, scb); |
6969 | char chan = SCB_GET_CHANNEL(ahd, scb); |
6970 | int slun = SCB_GET_LUN(scb); |
6971 | int match; |
6972 | |
6973 | match = ((chan == channel) || (channel == ALL_CHANNELS)); |
6974 | if (match != 0) |
6975 | match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); |
6976 | if (match != 0) |
6977 | match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); |
6978 | if (match != 0) { |
6979 | #if AHD_TARGET_MODE |
6980 | int group; |
6981 | |
6982 | group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); |
6983 | if (role == ROLE_INITIATOR) { |
6984 | match = (group != XPT_FC_GROUP_TMODE) |
6985 | && ((tag == SCB_GET_TAG(scb)) |
6986 | || (tag == SCB_LIST_NULL)); |
6987 | } else if (role == ROLE_TARGET) { |
6988 | match = (group == XPT_FC_GROUP_TMODE) |
6989 | && ((tag == scb->io_ctx->csio.tag_id) |
6990 | || (tag == SCB_LIST_NULL)); |
6991 | } |
6992 | #else /* !AHD_TARGET_MODE */ |
6993 | match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL)); |
6994 | #endif /* AHD_TARGET_MODE */ |
6995 | } |
6996 | |
6997 | return match; |
6998 | } |
6999 | |
7000 | void |
7001 | ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb) |
7002 | { |
7003 | int target; |
7004 | char channel; |
7005 | int lun; |
7006 | |
7007 | target = SCB_GET_TARGET(ahd, scb); |
7008 | lun = SCB_GET_LUN(scb); |
7009 | channel = SCB_GET_CHANNEL(ahd, scb); |
7010 | |
7011 | ahd_search_qinfifo(ahd, target, channel, lun, |
7012 | /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, |
7013 | CAM_REQUEUE_REQ, SEARCH_COMPLETE); |
7014 | |
7015 | ahd_platform_freeze_devq(ahd, scb); |
7016 | } |
7017 | |
7018 | void |
7019 | ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb) |
7020 | { |
7021 | struct scb *prev_scb; |
7022 | ahd_mode_state saved_modes; |
7023 | |
7024 | saved_modes = ahd_save_modes(ahd); |
7025 | ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); |
7026 | prev_scb = NULL; |
7027 | if (ahd_qinfifo_count(ahd) != 0) { |
7028 | u_int prev_tag; |
7029 | u_int prev_pos; |
7030 | |
7031 | prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1); |
7032 | prev_tag = ahd->qinfifo[prev_pos]; |
7033 | prev_scb = ahd_lookup_scb(ahd, prev_tag); |
7034 | } |
7035 | ahd_qinfifo_requeue(ahd, prev_scb, scb); |
7036 | ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); |
7037 | ahd_restore_modes(ahd, saved_modes); |
7038 | } |
7039 | |
7040 | static void |
7041 | ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb, |
7042 | struct scb *scb) |
7043 | { |
7044 | if (prev_scb == NULL) { |
7045 | uint32_t busaddr; |
7046 | |
7047 | busaddr = ahd_le32toh(scb->hscb->hscb_busaddr); |
7048 | ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); |
7049 | ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); |
7050 | ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); |
7051 | ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); |
7052 | } else { |
7053 | prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; |
7054 | ahd_sync_scb(ahd, prev_scb, |
7055 | BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
7056 | } |
7057 | ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); |
7058 | ahd->qinfifonext++; |
7059 | scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr; |
7060 | ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); |
7061 | } |
7062 | |
7063 | static int |
7064 | ahd_qinfifo_count(struct ahd_softc *ahd) |
7065 | { |
7066 | u_int qinpos; |
7067 | u_int wrap_qinpos; |
7068 | u_int wrap_qinfifonext; |
7069 | |
7070 | AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); |
7071 | qinpos = ahd_get_snscb_qoff(ahd); |
7072 | wrap_qinpos = AHD_QIN_WRAP(qinpos); |
7073 | wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext); |
7074 | if (wrap_qinfifonext >= wrap_qinpos) |
7075 | return (wrap_qinfifonext - wrap_qinpos); |
7076 | else |
7077 | return (wrap_qinfifonext |
7078 | + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos); |
7079 | } |
7080 | |
7081 | void |
7082 | ahd_reset_cmds_pending(struct ahd_softc *ahd) |
7083 | { |
7084 | struct scb *scb; |
7085 | ahd_mode_state saved_modes; |
7086 | u_int pending_cmds; |
7087 | |
7088 | saved_modes = ahd_save_modes(ahd); |
7089 | ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); |
7090 | |
7091 | /* |
7092 | * Don't count any commands as outstanding that the |
7093 | * sequencer has already marked for completion. |
7094 | */ |
7095 | ahd_flush_qoutfifo(ahd); |
7096 | |
7097 | pending_cmds = 0; |
7098 | LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { |
7099 | pending_cmds++; |
7100 | } |
7101 | ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd)); |
7102 | ahd_restore_modes(ahd, saved_modes); |
7103 | ahd->flags &= ~AHD_UPDATE_PEND_CMDS; |
7104 | } |
7105 | |
7106 | int |
7107 | ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel, |
7108 | int lun, u_int tag, role_t role, uint32_t status, |
7109 | ahd_search_action action) |
7110 | { |
7111 | struct scb *scb; |
7112 | struct scb *prev_scb; |
7113 | ahd_mode_state saved_modes; |
7114 | u_int qinstart; |
7115 | u_int qinpos; |
7116 | u_int qintail; |
7117 | u_int tid_next; |
7118 | u_int tid_prev; |
7119 | u_int scbid; |
7120 | u_int savedscbptr; |
7121 | uint32_t busaddr; |
7122 | int found; |
7123 | int targets; |
7124 | int pending_cmds; |
7125 | |
7126 | /* Must be in CCHAN mode */ |
7127 | saved_modes = ahd_save_modes(ahd); |
7128 | ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); |
7129 | |
7130 | /* |
7131 | * Halt any pending SCB DMA. The sequencer will reinitiate |
7132 | * this DMA if the qinfifo is not empty once we unpause. |
7133 | */ |
7134 | if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR)) |
7135 | == (CCARREN|CCSCBEN|CCSCBDIR)) { |
7136 | ahd_outb(ahd, CCSCBCTL, |
7137 | ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN)); |
7138 | while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) |
7139 | ; |
7140 | } |
7141 | /* Determine sequencer's position in the qinfifo. */ |
7142 | qintail = AHD_QIN_WRAP(ahd->qinfifonext); |
7143 | qinstart = ahd_get_snscb_qoff(ahd); |
7144 | qinpos = AHD_QIN_WRAP(qinstart); |
7145 | found = 0; |
7146 | prev_scb = NULL; |
7147 | |
7148 | pending_cmds = 0; |
7149 | LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { |
7150 | pending_cmds++; |
7151 | } |
7152 | (void)ahd_qinfifo_count(ahd); |
7153 | |
7154 | if (action == SEARCH_PRINT) { |
7155 | printf("qinstart = 0x%x qinfifonext = 0x%x\n" , |
7156 | qinstart, ahd->qinfifonext); |
7157 | } |
7158 | |
7159 | /* |
7160 | * Start with an empty queue. Entries that are not chosen |
7161 | * for removal will be re-added to the queue as we go. |
7162 | */ |
7163 | ahd->qinfifonext = qinstart; |
7164 | busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); |
7165 | ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); |
7166 | ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); |
7167 | ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); |
7168 | ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); |
7169 | |
7170 | while (qinpos != qintail) { |
7171 | scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]); |
7172 | if (scb == NULL) { |
7173 | panic("Loop 1\n" ); |
7174 | } |
7175 | |
7176 | if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) { |
7177 | /* |
7178 | * We found an scb that needs to be acted on. |
7179 | */ |
7180 | found++; |
7181 | switch (action) { |
7182 | case SEARCH_COMPLETE: |
7183 | { |
7184 | cam_status ostat; |
7185 | cam_status cstat; |
7186 | |
7187 | ostat = ahd_get_scsi_status(scb); |
7188 | if (ostat == CAM_REQ_INPROG) |
7189 | ahd_set_scsi_status(scb, status); |
7190 | cstat = ahd_get_transaction_status(scb); |
7191 | if (cstat != CAM_REQ_CMP) |
7192 | ahd_freeze_scb(scb); |
7193 | if ((scb->flags & SCB_ACTIVE) == 0) |
7194 | printf("Inactive SCB in qinfifo\n" ); |
7195 | if ((cam_status)scb->xs->error != CAM_REQ_CMP) |
7196 | printf("SEARCH_COMPLETE(0x%x):" |
7197 | " ostat 0x%x, cstat 0x%x, " |
7198 | "xs_error 0x%x\n" , |
7199 | SCB_GET_TAG(scb), ostat, cstat, |
7200 | scb->xs->error); |
7201 | ahd_done(ahd, scb); |
7202 | |
7203 | /* FALLTHROUGH */ |
7204 | } |
7205 | case SEARCH_REMOVE: |
7206 | break; |
7207 | case SEARCH_PRINT: |
7208 | printf(" 0x%x" , ahd->qinfifo[qinpos]); |
7209 | /* FALLTHROUGH */ |
7210 | case SEARCH_COUNT: |
7211 | ahd_qinfifo_requeue(ahd, prev_scb, scb); |
7212 | prev_scb = scb; |
7213 | break; |
7214 | } |
7215 | } else { |
7216 | ahd_qinfifo_requeue(ahd, prev_scb, scb); |
7217 | prev_scb = scb; |
7218 | } |
7219 | qinpos = AHD_QIN_WRAP(qinpos+1); |
7220 | } |
7221 | |
7222 | ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); |
7223 | |
7224 | if (action == SEARCH_PRINT) |
7225 | printf("\nWAITING_TID_QUEUES:\n" ); |
7226 | |
7227 | /* |
7228 | * Search waiting for selection lists. We traverse the |
7229 | * list of "their ids" waiting for selection and, if |
7230 | * appropriate, traverse the SCBs of each "their id" |
7231 | * looking for matches. |
7232 | */ |
7233 | savedscbptr = ahd_get_scbptr(ahd); |
7234 | tid_next = ahd_inw(ahd, WAITING_TID_HEAD); |
7235 | tid_prev = SCB_LIST_NULL; |
7236 | targets = 0; |
7237 | for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) { |
7238 | u_int tid_head; |
7239 | |
7240 | /* |
7241 | * We limit based on the number of SCBs since |
7242 | * MK_MESSAGE SCBs are not in the per-tid lists. |
7243 | */ |
7244 | targets++; |
7245 | if (targets > AHD_SCB_MAX) { |
7246 | panic("TID LIST LOOP" ); |
7247 | } |
7248 | if (scbid >= ahd->scb_data.numscbs) { |
7249 | printf("%s: Waiting TID List inconsistency. " |
7250 | "SCB index == 0x%x, yet numscbs == 0x%x." , |
7251 | ahd_name(ahd), scbid, ahd->scb_data.numscbs); |
7252 | ahd_dump_card_state(ahd); |
7253 | panic("for safety" ); |
7254 | } |
7255 | scb = ahd_lookup_scb(ahd, scbid); |
7256 | if (scb == NULL) { |
7257 | printf("%s: SCB = 0x%x Not Active!\n" , |
7258 | ahd_name(ahd), scbid); |
7259 | panic("Waiting TID List traversal\n" ); |
7260 | break; |
7261 | } |
7262 | ahd_set_scbptr(ahd, scbid); |
7263 | tid_next = ahd_inw_scbram(ahd, SCB_NEXT2); |
7264 | if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, |
7265 | SCB_LIST_NULL, ROLE_UNKNOWN) == 0) { |
7266 | tid_prev = scbid; |
7267 | continue; |
7268 | } |
7269 | |
7270 | /* |
7271 | * We found a list of scbs that needs to be searched. |
7272 | */ |
7273 | if (action == SEARCH_PRINT) |
7274 | printf(" %d ( " , SCB_GET_TARGET(ahd, scb)); |
7275 | tid_head = scbid; |
7276 | found += ahd_search_scb_list(ahd, target, channel, |
7277 | lun, tag, role, status, |
7278 | action, &tid_head, |
7279 | SCB_GET_TARGET(ahd, scb)); |
7280 | if (tid_head != scbid) |
7281 | ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next); |
7282 | if (!SCBID_IS_NULL(tid_head)) |
7283 | tid_prev = tid_head; |
7284 | if (action == SEARCH_PRINT) |
7285 | printf(")\n" ); |
7286 | } |
7287 | ahd_set_scbptr(ahd, savedscbptr); |
7288 | ahd_restore_modes(ahd, saved_modes); |
7289 | return (found); |
7290 | } |
7291 | |
7292 | static int |
7293 | ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel, |
7294 | int lun, u_int tag, role_t role, uint32_t status, |
7295 | ahd_search_action action, u_int *list_head, u_int tid) |
7296 | { |
7297 | struct scb *scb; |
7298 | u_int scbid; |
7299 | u_int next; |
7300 | u_int prev; |
7301 | int found; |
7302 | |
7303 | AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); |
7304 | found = 0; |
7305 | prev = SCB_LIST_NULL; |
7306 | next = *list_head; |
7307 | for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) { |
7308 | if (scbid >= ahd->scb_data.numscbs) { |
7309 | printf("%s:SCB List inconsistency. " |
7310 | "SCB == 0x%x, yet numscbs == 0x%x." , |
7311 | ahd_name(ahd), scbid, ahd->scb_data.numscbs); |
7312 | ahd_dump_card_state(ahd); |
7313 | panic("for safety" ); |
7314 | } |
7315 | scb = ahd_lookup_scb(ahd, scbid); |
7316 | if (scb == NULL) { |
7317 | printf("%s: SCB = %d Not Active!\n" , |
7318 | ahd_name(ahd), scbid); |
7319 | panic("Waiting List traversal\n" ); |
7320 | } |
7321 | ahd_set_scbptr(ahd, scbid); |
7322 | next = ahd_inw_scbram(ahd, SCB_NEXT); |
7323 | if (ahd_match_scb(ahd, scb, target, channel, |
7324 | lun, SCB_LIST_NULL, role) == 0) { |
7325 | prev = scbid; |
7326 | continue; |
7327 | } |
7328 | found++; |
7329 | switch (action) { |
7330 | case SEARCH_COMPLETE: |
7331 | { |
7332 | cam_status ostat; |
7333 | cam_status cstat; |
7334 | |
7335 | ostat = ahd_get_scsi_status(scb); |
7336 | if (ostat == CAM_REQ_INPROG) |
7337 | ahd_set_scsi_status(scb, status); |
7338 | cstat = ahd_get_transaction_status(scb); |
7339 | if (cstat != CAM_REQ_CMP) |
7340 | ahd_freeze_scb(scb); |
7341 | if ((scb->flags & SCB_ACTIVE) == 0) |
7342 | printf("Inactive SCB in Waiting List\n" ); |
7343 | ahd_done(ahd, scb); |
7344 | /* FALLTHROUGH */ |
7345 | } |
7346 | case SEARCH_REMOVE: |
7347 | ahd_rem_wscb(ahd, scbid, prev, next, tid); |
7348 | if (prev == SCB_LIST_NULL) |
7349 | *list_head = next; |
7350 | break; |
7351 | case SEARCH_PRINT: |
7352 | printf("0x%x " , scbid); |
7353 | case SEARCH_COUNT: |
7354 | prev = scbid; |
7355 | break; |
7356 | } |
7357 | if (found > AHD_SCB_MAX) |
7358 | panic("SCB LIST LOOP" ); |
7359 | } |
7360 | if (action == SEARCH_COMPLETE |
7361 | || action == SEARCH_REMOVE) |
7362 | ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found); |
7363 | return (found); |
7364 | } |
7365 | |
7366 | static void |
7367 | ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev, |
7368 | u_int tid_cur, u_int tid_next) |
7369 | { |
7370 | AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); |
7371 | |
7372 | if (SCBID_IS_NULL(tid_cur)) { |
7373 | |
7374 | /* Bypass current TID list */ |
7375 | if (SCBID_IS_NULL(tid_prev)) { |
7376 | ahd_outw(ahd, WAITING_TID_HEAD, tid_next); |
7377 | } else { |
7378 | ahd_set_scbptr(ahd, tid_prev); |
7379 | ahd_outw(ahd, SCB_NEXT2, tid_next); |
7380 | } |
7381 | if (SCBID_IS_NULL(tid_next)) |
7382 | ahd_outw(ahd, WAITING_TID_TAIL, tid_prev); |
7383 | } else { |
7384 | |
7385 | /* Stitch through tid_cur */ |
7386 | if (SCBID_IS_NULL(tid_prev)) { |
7387 | ahd_outw(ahd, WAITING_TID_HEAD, tid_cur); |
7388 | } else { |
7389 | ahd_set_scbptr(ahd, tid_prev); |
7390 | ahd_outw(ahd, SCB_NEXT2, tid_cur); |
7391 | } |
7392 | ahd_set_scbptr(ahd, tid_cur); |
7393 | ahd_outw(ahd, SCB_NEXT2, tid_next); |
7394 | |
7395 | if (SCBID_IS_NULL(tid_next)) |
7396 | ahd_outw(ahd, WAITING_TID_TAIL, tid_cur); |
7397 | } |
7398 | } |
7399 | |
7400 | /* |
7401 | * Manipulate the waiting for selection list and return the |
7402 | * scb that follows the one that we remove. |
7403 | */ |
7404 | static u_int |
7405 | ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, |
7406 | u_int prev, u_int next, u_int tid) |
7407 | { |
7408 | u_int tail_offset; |
7409 | |
7410 | AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); |
7411 | if (!SCBID_IS_NULL(prev)) { |
7412 | ahd_set_scbptr(ahd, prev); |
7413 | ahd_outw(ahd, SCB_NEXT, next); |
7414 | } |
7415 | |
7416 | /* |
7417 | * SCBs that had MK_MESSAGE set in them will not |
7418 | * be queued to the per-target lists, so don't |
7419 | * blindly clear the tail pointer. |
7420 | */ |
7421 | tail_offset = WAITING_SCB_TAILS + (2 * tid); |
7422 | if (SCBID_IS_NULL(next) |
7423 | && ahd_inw(ahd, tail_offset) == scbid) |
7424 | ahd_outw(ahd, tail_offset, prev); |
7425 | ahd_add_scb_to_free_list(ahd, scbid); |
7426 | return (next); |
7427 | } |
7428 | |
7429 | /* |
7430 | * Add the SCB as selected by SCBPTR onto the on chip list of |
7431 | * free hardware SCBs. This list is empty/unused if we are not |
7432 | * performing SCB paging. |
7433 | */ |
7434 | static void |
7435 | ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid) |
7436 | { |
7437 | #ifdef notdef |
7438 | /* XXX Need some other mechanism to designate "free". */ |
7439 | /* |
7440 | * Invalidate the tag so that our abort |
7441 | * routines don't think it's active. |
7442 | */ |
7443 | ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL); |
7444 | #endif |
7445 | } |
7446 | |
7447 | /******************************** Error Handling ******************************/ |
7448 | /* |
7449 | * Abort all SCBs that match the given description (target/channel/lun/tag), |
7450 | * setting their status to the passed in status if the status has not already |
7451 | * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer |
7452 | * is paused before it is called. |
7453 | */ |
7454 | int |
7455 | ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel, |
7456 | int lun, u_int tag, role_t role, uint32_t status) |
7457 | { |
7458 | struct scb *scbp; |
7459 | struct scb *scbp_next; |
7460 | u_int i, j; |
7461 | u_int maxtarget; |
7462 | u_int minlun; |
7463 | u_int maxlun; |
7464 | int found; |
7465 | ahd_mode_state saved_modes; |
7466 | |
7467 | /* restore this when we're done */ |
7468 | saved_modes = ahd_save_modes(ahd); |
7469 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
7470 | |
7471 | found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL, |
7472 | role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); |
7473 | |
7474 | /* |
7475 | * Clean out the busy target table for any untagged commands. |
7476 | */ |
7477 | i = 0; |
7478 | maxtarget = 16; |
7479 | if (target != CAM_TARGET_WILDCARD) { |
7480 | i = target; |
7481 | if (channel == 'B') |
7482 | i += 8; |
7483 | maxtarget = i + 1; |
7484 | } |
7485 | |
7486 | if (lun == CAM_LUN_WILDCARD) { |
7487 | minlun = 0; |
7488 | maxlun = AHD_NUM_LUNS_NONPKT; |
7489 | } else if (lun >= AHD_NUM_LUNS_NONPKT) { |
7490 | minlun = maxlun = 0; |
7491 | } else { |
7492 | minlun = lun; |
7493 | maxlun = lun + 1; |
7494 | } |
7495 | |
7496 | if (role != ROLE_TARGET) { |
7497 | for (;i < maxtarget; i++) { |
7498 | for (j = minlun;j < maxlun; j++) { |
7499 | u_int scbid; |
7500 | u_int tcl; |
7501 | |
7502 | tcl = BUILD_TCL_RAW(i, 'A', j); |
7503 | scbid = ahd_find_busy_tcl(ahd, tcl); |
7504 | scbp = ahd_lookup_scb(ahd, scbid); |
7505 | if (scbp == NULL |
7506 | || ahd_match_scb(ahd, scbp, target, channel, |
7507 | lun, tag, role) == 0) |
7508 | continue; |
7509 | ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j)); |
7510 | } |
7511 | } |
7512 | } |
7513 | |
7514 | /* |
7515 | * Don't abort commands that have already completed, |
7516 | * but haven't quite made it up to the host yet. |
7517 | */ |
7518 | ahd_flush_qoutfifo(ahd); |
7519 | |
7520 | /* |
7521 | * Go through the pending CCB list and look for |
7522 | * commands for this target that are still active. |
7523 | * These are other tagged commands that were |
7524 | * disconnected when the reset occurred. |
7525 | */ |
7526 | scbp_next = LIST_FIRST(&ahd->pending_scbs); |
7527 | while (scbp_next != NULL) { |
7528 | scbp = scbp_next; |
7529 | scbp_next = LIST_NEXT(scbp, pending_links); |
7530 | if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) { |
7531 | cam_status ostat; |
7532 | |
7533 | ostat = ahd_get_scsi_status(scbp); |
7534 | if (ostat == CAM_REQ_INPROG) |
7535 | ahd_set_scsi_status(scbp, status); |
7536 | if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP) |
7537 | ahd_freeze_scb(scbp); |
7538 | if ((scbp->flags & SCB_ACTIVE) == 0) |
7539 | printf("Inactive SCB on pending list\n" ); |
7540 | ahd_done(ahd, scbp); |
7541 | found++; |
7542 | } |
7543 | } |
7544 | ahd_restore_modes(ahd, saved_modes); |
7545 | ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status); |
7546 | ahd->flags |= AHD_UPDATE_PEND_CMDS; |
7547 | return found; |
7548 | } |
7549 | |
7550 | static void |
7551 | ahd_reset_current_bus(struct ahd_softc *ahd) |
7552 | { |
7553 | uint8_t scsiseq; |
7554 | |
7555 | AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); |
7556 | ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST); |
7557 | scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO); |
7558 | ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO); |
7559 | ahd_flush_device_writes(ahd); |
7560 | ahd_delay(AHD_BUSRESET_DELAY); |
7561 | /* Turn off the bus reset */ |
7562 | ahd_outb(ahd, SCSISEQ0, scsiseq); |
7563 | ahd_flush_device_writes(ahd); |
7564 | ahd_delay(AHD_BUSRESET_DELAY); |
7565 | if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) { |
7566 | /* |
7567 | * 2A Razor #474 |
7568 | * Certain chip state is not cleared for |
7569 | * SCSI bus resets that we initiate, so |
7570 | * we must reset the chip. |
7571 | */ |
7572 | ahd_reset(ahd, /*reinit*/TRUE); |
7573 | ahd_intr_enable(ahd, /*enable*/TRUE); |
7574 | AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); |
7575 | } |
7576 | |
7577 | ahd_clear_intstat(ahd); |
7578 | } |
7579 | |
7580 | int |
7581 | ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) |
7582 | { |
7583 | struct ahd_devinfo devinfo; |
7584 | u_int initiator; |
7585 | u_int target; |
7586 | u_int max_scsiid; |
7587 | int found; |
7588 | u_int fifo; |
7589 | u_int next_fifo; |
7590 | |
7591 | |
7592 | ahd->pending_device = NULL; |
7593 | |
7594 | ahd_compile_devinfo(&devinfo, |
7595 | CAM_TARGET_WILDCARD, |
7596 | CAM_TARGET_WILDCARD, |
7597 | CAM_LUN_WILDCARD, |
7598 | channel, ROLE_UNKNOWN); |
7599 | ahd_pause(ahd); |
7600 | |
7601 | /* Make sure the sequencer is in a safe location. */ |
7602 | ahd_clear_critical_section(ahd); |
7603 | |
7604 | #if AHD_TARGET_MODE |
7605 | if ((ahd->flags & AHD_TARGETROLE) != 0) { |
7606 | ahd_run_tqinfifo(ahd, /*paused*/TRUE); |
7607 | } |
7608 | #endif |
7609 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
7610 | |
7611 | /* |
7612 | * Disable selections so no automatic hardware |
7613 | * functions will modify chip state. |
7614 | */ |
7615 | ahd_outb(ahd, SCSISEQ0, 0); |
7616 | ahd_outb(ahd, SCSISEQ1, 0); |
7617 | |
7618 | /* |
7619 | * Safely shut down our DMA engines. Always start with |
7620 | * the FIFO that is not currently active (if any are |
7621 | * actively connected). |
7622 | */ |
7623 | next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; |
7624 | if (next_fifo > CURRFIFO_1) |
7625 | /* If disconneced, arbitrarily start with FIFO1. */ |
7626 | next_fifo = fifo = 0; |
7627 | do { |
7628 | next_fifo ^= CURRFIFO_1; |
7629 | ahd_set_modes(ahd, next_fifo, next_fifo); |
7630 | ahd_outb(ahd, DFCNTRL, |
7631 | ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN)); |
7632 | while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) |
7633 | ahd_delay(10); |
7634 | /* |
7635 | * Set CURRFIFO to the now inactive channel. |
7636 | */ |
7637 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
7638 | ahd_outb(ahd, DFFSTAT, next_fifo); |
7639 | } while (next_fifo != fifo); |
7640 | |
7641 | /* |
7642 | * Reset the bus if we are initiating this reset |
7643 | */ |
7644 | ahd_clear_msg_state(ahd); |
7645 | ahd_outb(ahd, SIMODE1, |
7646 | ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST|ENBUSFREE)); |
7647 | |
7648 | if (initiate_reset) |
7649 | ahd_reset_current_bus(ahd); |
7650 | |
7651 | ahd_clear_intstat(ahd); |
7652 | |
7653 | /* |
7654 | * Clean up all the state information for the |
7655 | * pending transactions on this bus. |
7656 | */ |
7657 | found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel, |
7658 | CAM_LUN_WILDCARD, SCB_LIST_NULL, |
7659 | ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); |
7660 | |
7661 | /* |
7662 | * Cleanup anything left in the FIFOs. |
7663 | */ |
7664 | ahd_clear_fifo(ahd, 0); |
7665 | ahd_clear_fifo(ahd, 1); |
7666 | |
7667 | /* |
7668 | * Revert to async/narrow transfers until we renegotiate. |
7669 | */ |
7670 | max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; |
7671 | for (target = 0; target <= max_scsiid; target++) { |
7672 | |
7673 | if (ahd->enabled_targets[target] == NULL) |
7674 | continue; |
7675 | for (initiator = 0; initiator <= max_scsiid; initiator++) { |
7676 | struct ahd_devinfo dinfo; |
7677 | |
7678 | ahd_compile_devinfo(&dinfo, target, initiator, |
7679 | CAM_LUN_WILDCARD, |
7680 | 'A', ROLE_UNKNOWN); |
7681 | ahd_set_width(ahd, &dinfo, MSG_EXT_WDTR_BUS_8_BIT, |
7682 | AHD_TRANS_CUR, /*paused*/TRUE); |
7683 | ahd_set_syncrate(ahd, &dinfo, /*period*/0, |
7684 | /*offset*/0, /*ppr_options*/0, |
7685 | AHD_TRANS_CUR, /*paused*/TRUE); |
7686 | } |
7687 | } |
7688 | |
7689 | #ifdef AHD_TARGET_MODE |
7690 | max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; |
7691 | |
7692 | /* |
7693 | * Send an immediate notify ccb to all target more peripheral |
7694 | * drivers affected by this action. |
7695 | */ |
7696 | for (target = 0; target <= max_scsiid; target++) { |
7697 | struct ahd_tmode_tstate* tstate; |
7698 | u_int lun; |
7699 | |
7700 | tstate = ahd->enabled_targets[target]; |
7701 | if (tstate == NULL) |
7702 | continue; |
7703 | for (lun = 0; lun < AHD_NUM_LUNS; lun++) { |
7704 | struct ahd_tmode_lstate* lstate; |
7705 | |
7706 | lstate = tstate->enabled_luns[lun]; |
7707 | if (lstate == NULL) |
7708 | continue; |
7709 | |
7710 | ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD, |
7711 | EVENT_TYPE_BUS_RESET, /*arg*/0); |
7712 | ahd_send_lstate_events(ahd, lstate); |
7713 | } |
7714 | } |
7715 | #endif |
7716 | |
7717 | /* Notify the XPT that a bus reset occurred */ |
7718 | ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD, |
7719 | CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); |
7720 | ahd_restart(ahd); |
7721 | |
7722 | /* |
7723 | * Freeze the SIMQ until our poller can determine that |
7724 | * the bus reset has really gone away. We set the initial |
7725 | * timer to 0 to have the check performed as soon as possible |
7726 | * from the timer context. |
7727 | */ |
7728 | if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) { |
7729 | ahd->flags |= AHD_RESET_POLL_ACTIVE; |
7730 | ahd_freeze_simq(ahd); |
7731 | ahd_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd); |
7732 | } |
7733 | return (found); |
7734 | } |
7735 | |
7736 | |
7737 | #define AHD_RESET_POLL_US 1000 |
7738 | static void |
7739 | ahd_reset_poll(void *arg) |
7740 | { |
7741 | struct ahd_softc *ahd; |
7742 | u_int scsiseq1; |
7743 | u_long l; |
7744 | int s; |
7745 | |
7746 | ahd_list_lock(&l); |
7747 | ahd = arg; |
7748 | if (ahd == NULL) { |
7749 | printf("ahd_reset_poll: Instance %p no longer exists\n" , arg); |
7750 | ahd_list_unlock(&l); |
7751 | return; |
7752 | } |
7753 | ahd_lock(ahd, &s); |
7754 | ahd_pause(ahd); |
7755 | ahd_update_modes(ahd); |
7756 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
7757 | ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); |
7758 | if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) { |
7759 | ahd_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US, |
7760 | ahd_reset_poll, ahd); |
7761 | ahd_unpause(ahd); |
7762 | ahd_unlock(ahd, &s); |
7763 | ahd_list_unlock(&l); |
7764 | return; |
7765 | } |
7766 | |
7767 | /* Reset is now low. Complete chip reinitialization. */ |
7768 | ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST); |
7769 | scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); |
7770 | ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP)); |
7771 | ahd_unpause(ahd); |
7772 | ahd->flags &= ~AHD_RESET_POLL_ACTIVE; |
7773 | ahd_unlock(ahd, &s); |
7774 | ahd_release_simq(ahd); |
7775 | ahd_list_unlock(&l); |
7776 | } |
7777 | |
7778 | /**************************** Statistics Processing ***************************/ |
7779 | static void |
7780 | ahd_stat_timer(void *arg) |
7781 | { |
7782 | struct ahd_softc *ahd; |
7783 | u_long l; |
7784 | int s; |
7785 | int enint_coal; |
7786 | |
7787 | ahd_list_lock(&l); |
7788 | ahd = arg; |
7789 | if (ahd == NULL) { |
7790 | printf("ahd_stat_timer: Instance %p no longer exists\n" , arg); |
7791 | ahd_list_unlock(&l); |
7792 | return; |
7793 | } |
7794 | ahd_lock(ahd, &s); |
7795 | |
7796 | enint_coal = ahd->hs_mailbox & ENINT_COALESCE; |
7797 | if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold) |
7798 | enint_coal |= ENINT_COALESCE; |
7799 | else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold) |
7800 | enint_coal &= ~ENINT_COALESCE; |
7801 | |
7802 | if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) { |
7803 | ahd_enable_coalescing(ahd, enint_coal); |
7804 | #ifdef AHD_DEBUG |
7805 | if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0) |
7806 | printf("%s: Interrupt coalescing " |
7807 | "now %sabled. Cmds %d\n" , |
7808 | ahd_name(ahd), |
7809 | (enint_coal & ENINT_COALESCE) ? "en" : "dis" , |
7810 | ahd->cmdcmplt_total); |
7811 | #endif |
7812 | } |
7813 | |
7814 | ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1); |
7815 | ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]; |
7816 | ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0; |
7817 | ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, |
7818 | ahd_stat_timer, ahd); |
7819 | ahd_unlock(ahd, &s); |
7820 | ahd_list_unlock(&l); |
7821 | } |
7822 | |
7823 | /****************************** Status Processing *****************************/ |
7824 | void |
7825 | ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb) |
7826 | { |
7827 | if (scb->hscb->shared_data.istatus.scsi_status != 0) { |
7828 | ahd_handle_scsi_status(ahd, scb); |
7829 | } else { |
7830 | ahd_calc_residual(ahd, scb); |
7831 | ahd_done(ahd, scb); |
7832 | } |
7833 | } |
7834 | |
7835 | void |
7836 | ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb) |
7837 | { |
7838 | struct hardware_scb *hscb; |
7839 | u_int qfreeze_cnt; |
7840 | |
7841 | /* |
7842 | * The sequencer freezes its select-out queue |
7843 | * anytime a SCSI status error occurs. We must |
7844 | * handle the error and decrement the QFREEZE count |
7845 | * to allow the sequencer to continue. |
7846 | */ |
7847 | hscb = scb->hscb; |
7848 | |
7849 | /* Freeze the queue until the client sees the error. */ |
7850 | ahd_freeze_devq(ahd, scb); |
7851 | ahd_freeze_scb(scb); |
7852 | qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); |
7853 | if (qfreeze_cnt == 0) { |
7854 | printf("%s: Bad status with 0 qfreeze count!\n" , ahd_name(ahd)); |
7855 | } else { |
7856 | qfreeze_cnt--; |
7857 | ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); |
7858 | } |
7859 | if (qfreeze_cnt == 0) |
7860 | ahd_outb(ahd, SEQ_FLAGS2, |
7861 | ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); |
7862 | |
7863 | /* Don't want to clobber the original sense code */ |
7864 | if ((scb->flags & SCB_SENSE) != 0) { |
7865 | /* |
7866 | * Clear the SCB_SENSE Flag and perform |
7867 | * a normal command completion. |
7868 | */ |
7869 | scb->flags &= ~SCB_SENSE; |
7870 | ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); |
7871 | ahd_done(ahd, scb); |
7872 | return; |
7873 | } |
7874 | ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status); |
7875 | ahd_set_xfer_status(scb, hscb->shared_data.istatus.scsi_status); |
7876 | switch (hscb->shared_data.istatus.scsi_status) { |
7877 | case STATUS_PKT_SENSE: |
7878 | { |
7879 | struct scsi_status_iu_header *siu; |
7880 | |
7881 | ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD); |
7882 | siu = (struct scsi_status_iu_header *)scb->sense_data; |
7883 | ahd_set_scsi_status(scb, siu->status); |
7884 | #ifdef AHD_DEBUG |
7885 | if ((ahd_debug & AHD_SHOW_SENSE) != 0) { |
7886 | ahd_print_path(ahd, scb); |
7887 | printf("SCB 0x%x Received PKT Status of 0x%x\n" , |
7888 | SCB_GET_TAG(scb), siu->status); |
7889 | } |
7890 | #endif |
7891 | if ((siu->flags & SIU_RSPVALID) != 0) { |
7892 | scsipi_printaddr(scb->xs->xs_periph); |
7893 | if (scsi_4btoul(siu->pkt_failures_length) < 4) { |
7894 | printf("Unable to parse pkt_failures\n" ); |
7895 | } else { |
7896 | |
7897 | switch (SIU_PKTFAIL_CODE(siu)) { |
7898 | case SIU_PFC_NONE: |
7899 | printf("No packet failure found\n" ); |
7900 | break; |
7901 | case SIU_PFC_CIU_FIELDS_INVALID: |
7902 | printf("Invalid Command IU Field\n" ); |
7903 | break; |
7904 | case SIU_PFC_TMF_NOT_SUPPORTED: |
7905 | printf("TMF not supportd\n" ); |
7906 | break; |
7907 | case SIU_PFC_TMF_FAILED: |
7908 | printf("TMF failed\n" ); |
7909 | break; |
7910 | case SIU_PFC_INVALID_TYPE_CODE: |
7911 | printf("Invalid L_Q Type code\n" ); |
7912 | break; |
7913 | case SIU_PFC_ILLEGAL_REQUEST: |
7914 | printf("Illegal request\n" ); |
7915 | default: |
7916 | break; |
7917 | } |
7918 | } |
7919 | if (siu->status == SCSI_STATUS_OK) |
7920 | ahd_set_transaction_status(scb, |
7921 | CAM_REQ_CMP_ERR); |
7922 | } |
7923 | if ((siu->flags & SIU_SNSVALID) != 0) { |
7924 | scb->flags |= SCB_PKT_SENSE; |
7925 | #ifdef AHD_DEBUG |
7926 | if ((ahd_debug & AHD_SHOW_SENSE) != 0) { |
7927 | printf("Sense data available (%d)\n" , |
7928 | siu->sense_length[0]); |
7929 | printf("SK 0x%x ASC 0x%x ASCQ 0x%x\n" , |
7930 | ((uint8_t)scb->sense_data[ |
7931 | SIU_SENSE_OFFSET(siu)+2]) & 0x0F, |
7932 | ((uint8_t)scb->sense_data[ |
7933 | SIU_SENSE_OFFSET(siu)+12]), |
7934 | ((uint8_t)scb->sense_data[ |
7935 | SIU_SENSE_OFFSET(siu)+13])); |
7936 | } |
7937 | #endif |
7938 | } |
7939 | ahd_done(ahd, scb); |
7940 | break; |
7941 | } |
7942 | case SCSI_STATUS_CMD_TERMINATED: |
7943 | case SCSI_STATUS_CHECK_COND: |
7944 | { |
7945 | struct ahd_devinfo devinfo; |
7946 | struct ahd_dma_seg *sg; |
7947 | struct scsi_request_sense *sc; |
7948 | struct ahd_initiator_tinfo *targ_info; |
7949 | struct ahd_tmode_tstate *tstate; |
7950 | #ifdef AHD_DEBUG |
7951 | if (ahd_debug & AHD_SHOW_SENSE) { |
7952 | ahd_print_path(ahd, scb); |
7953 | printf("SCB %d: requests Check Status\n" , |
7954 | SCB_GET_TAG(scb)); |
7955 | } |
7956 | #endif |
7957 | |
7958 | if (ahd_perform_autosense(scb) == 0) |
7959 | break; |
7960 | |
7961 | ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), |
7962 | SCB_GET_TARGET(ahd, scb), |
7963 | SCB_GET_LUN(scb), |
7964 | SCB_GET_CHANNEL(ahd, scb), |
7965 | ROLE_INITIATOR); |
7966 | targ_info = ahd_fetch_transinfo(ahd, |
7967 | devinfo.channel, |
7968 | devinfo.our_scsiid, |
7969 | devinfo.target, |
7970 | &tstate); |
7971 | sg = scb->sg_list; |
7972 | sc = (struct scsi_request_sense *)hscb->shared_data.idata.cdb; |
7973 | /* |
7974 | * Save off the residual if there is one. |
7975 | */ |
7976 | ahd_update_residual(ahd, scb); |
7977 | #ifdef AHD_DEBUG |
7978 | if (ahd_debug & AHD_SHOW_SENSE) { |
7979 | ahd_print_path(ahd, scb); |
7980 | printf("Sending Sense\n" ); |
7981 | } |
7982 | #endif |
7983 | scb->sg_count = 0; |
7984 | sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb), |
7985 | ahd_get_sense_bufsize(ahd, scb), |
7986 | /*last*/TRUE); |
7987 | memset(sc, 0, sizeof(*sc)); |
7988 | sc->opcode = SCSI_REQUEST_SENSE; |
7989 | sc->length = ahd_get_sense_bufsize(ahd, scb); |
7990 | |
7991 | /* |
7992 | * We can't allow the target to disconnect. |
7993 | * This will be an untagged transaction and |
7994 | * having the target disconnect will make this |
7995 | * transaction indistinguishable from outstanding |
7996 | * tagged transactions. |
7997 | */ |
7998 | hscb->control = 0; |
7999 | |
8000 | /* |
8001 | * This request sense could be because the |
8002 | * the device lost power or in some other |
8003 | * way has lost our transfer negotiations. |
8004 | * Renegotiate if appropriate. Unit attention |
8005 | * errors will be reported before any data |
8006 | * phases occur. |
8007 | */ |
8008 | if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) { |
8009 | ahd_update_neg_request(ahd, &devinfo, |
8010 | tstate, targ_info, |
8011 | AHD_NEG_IF_NON_ASYNC); |
8012 | } |
8013 | if (tstate->auto_negotiate & devinfo.target_mask) { |
8014 | hscb->control |= MK_MESSAGE; |
8015 | scb->flags &= |
8016 | ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET); |
8017 | scb->flags |= SCB_AUTO_NEGOTIATE; |
8018 | } |
8019 | hscb->cdb_len = sizeof(*sc); |
8020 | ahd_setup_data_scb(ahd, scb); |
8021 | scb->flags |= SCB_SENSE; |
8022 | ahd_queue_scb(ahd, scb); |
8023 | /* |
8024 | * Ensure we have enough time to actually |
8025 | * retrieve the sense. |
8026 | */ |
8027 | ahd_scb_timer_reset(scb, 5 * 1000000); |
8028 | break; |
8029 | } |
8030 | case SCSI_STATUS_OK: |
8031 | printf("%s: Interrupted for status of 0? (SCB 0x%x)\n" , |
8032 | ahd_name(ahd), SCB_GET_TAG(scb)); |
8033 | /* FALLTHROUGH */ |
8034 | default: |
8035 | ahd_done(ahd, scb); |
8036 | break; |
8037 | } |
8038 | } |
8039 | |
8040 | /* |
8041 | * Calculate the residual for a just completed SCB. |
8042 | */ |
8043 | void |
8044 | ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb) |
8045 | { |
8046 | struct hardware_scb *hscb; |
8047 | struct initiator_status *spkt; |
8048 | uint32_t sgptr; |
8049 | uint32_t resid_sgptr; |
8050 | uint32_t resid; |
8051 | |
8052 | /* |
8053 | * 5 cases. |
8054 | * 1) No residual. |
8055 | * SG_STATUS_VALID clear in sgptr. |
8056 | * 2) Transferless command |
8057 | * 3) Never performed any transfers. |
8058 | * sgptr has SG_FULL_RESID set. |
8059 | * 4) No residual but target did not |
8060 | * save data pointers after the |
8061 | * last transfer, so sgptr was |
8062 | * never updated. |
8063 | * 5) We have a partial residual. |
8064 | * Use residual_sgptr to determine |
8065 | * where we are. |
8066 | */ |
8067 | |
8068 | hscb = scb->hscb; |
8069 | sgptr = ahd_le32toh(hscb->sgptr); |
8070 | if ((sgptr & SG_STATUS_VALID) == 0) |
8071 | /* Case 1 */ |
8072 | return; |
8073 | sgptr &= ~SG_STATUS_VALID; |
8074 | |
8075 | if ((sgptr & SG_LIST_NULL) != 0) |
8076 | /* Case 2 */ |
8077 | return; |
8078 | |
8079 | /* |
8080 | * Residual fields are the same in both |
8081 | * target and initiator status packets, |
8082 | * so we can always use the initiator fields |
8083 | * regardless of the role for this SCB. |
8084 | */ |
8085 | spkt = &hscb->shared_data.istatus; |
8086 | resid_sgptr = ahd_le32toh(spkt->residual_sgptr); |
8087 | if ((sgptr & SG_FULL_RESID) != 0) { |
8088 | /* Case 3 */ |
8089 | resid = ahd_get_transfer_length(scb); |
8090 | } else if ((resid_sgptr & SG_LIST_NULL) != 0) { |
8091 | /* Case 4 */ |
8092 | return; |
8093 | } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) { |
8094 | ahd_print_path(ahd, scb); |
8095 | printf("data overrun detected Tag == 0x%x.\n" , |
8096 | SCB_GET_TAG(scb)); |
8097 | ahd_freeze_devq(ahd, scb); |
8098 | ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); |
8099 | ahd_freeze_scb(scb); |
8100 | return; |
8101 | } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { |
8102 | panic("Bogus resid sgptr value 0x%x\n" , resid_sgptr); |
8103 | /* NOTREACHED */ |
8104 | } else { |
8105 | struct ahd_dma_seg *sg; |
8106 | |
8107 | /* |
8108 | * Remainder of the SG where the transfer |
8109 | * stopped. |
8110 | */ |
8111 | resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK; |
8112 | sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK); |
8113 | |
8114 | /* The residual sg_ptr always points to the next sg */ |
8115 | sg--; |
8116 | |
8117 | /* |
8118 | * Add up the contents of all residual |
8119 | * SG segments that are after the SG where |
8120 | * the transfer stopped. |
8121 | */ |
8122 | while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) { |
8123 | sg++; |
8124 | resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; |
8125 | } |
8126 | } |
8127 | |
8128 | if ((scb->flags & SCB_SENSE) == 0) |
8129 | ahd_set_residual(scb, resid); |
8130 | /*else |
8131 | ahd_set_sense_residual(scb, resid);*/ |
8132 | |
8133 | #ifdef AHD_DEBUG |
8134 | if ((ahd_debug & AHD_SHOW_MISC) != 0) { |
8135 | ahd_print_path(ahd, scb); |
8136 | printf("Handled %sResidual of %d bytes\n" , |
8137 | (scb->flags & SCB_SENSE) ? "Sense " : "" , resid); |
8138 | } |
8139 | #endif |
8140 | } |
8141 | |
8142 | /******************************* Target Mode **********************************/ |
8143 | #ifdef AHD_TARGET_MODE |
8144 | /* |
8145 | * Add a target mode event to this lun's queue |
8146 | */ |
8147 | static void |
8148 | ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate, |
8149 | u_int initiator_id, u_int event_type, u_int event_arg) |
8150 | { |
8151 | struct ahd_tmode_event *event; |
8152 | int pending; |
8153 | |
8154 | xpt_freeze_devq(lstate->path, /*count*/1); |
8155 | if (lstate->event_w_idx >= lstate->event_r_idx) |
8156 | pending = lstate->event_w_idx - lstate->event_r_idx; |
8157 | else |
8158 | pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1 |
8159 | - (lstate->event_r_idx - lstate->event_w_idx); |
8160 | |
8161 | if (event_type == EVENT_TYPE_BUS_RESET |
8162 | || event_type == MSG_BUS_DEV_RESET) { |
8163 | /* |
8164 | * Any earlier events are irrelevant, so reset our buffer. |
8165 | * This has the effect of allowing us to deal with reset |
8166 | * floods (an external device holding down the reset line) |
8167 | * without losing the event that is really interesting. |
8168 | */ |
8169 | lstate->event_r_idx = 0; |
8170 | lstate->event_w_idx = 0; |
8171 | xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); |
8172 | } |
8173 | |
8174 | if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) { |
8175 | xpt_print_path(lstate->path); |
8176 | printf("immediate event %x:%x lost\n" , |
8177 | lstate->event_buffer[lstate->event_r_idx].event_type, |
8178 | lstate->event_buffer[lstate->event_r_idx].event_arg); |
8179 | lstate->event_r_idx++; |
8180 | if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) |
8181 | lstate->event_r_idx = 0; |
8182 | xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); |
8183 | } |
8184 | |
8185 | event = &lstate->event_buffer[lstate->event_w_idx]; |
8186 | event->initiator_id = initiator_id; |
8187 | event->event_type = event_type; |
8188 | event->event_arg = event_arg; |
8189 | lstate->event_w_idx++; |
8190 | if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE) |
8191 | lstate->event_w_idx = 0; |
8192 | } |
8193 | |
8194 | /* |
8195 | * Send any target mode events queued up waiting |
8196 | * for immediate notify resources. |
8197 | */ |
8198 | void |
8199 | ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate) |
8200 | { |
8201 | struct ccb_hdr *ccbh; |
8202 | struct ccb_immed_notify *inot; |
8203 | |
8204 | while (lstate->event_r_idx != lstate->event_w_idx |
8205 | && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { |
8206 | struct ahd_tmode_event *event; |
8207 | |
8208 | event = &lstate->event_buffer[lstate->event_r_idx]; |
8209 | SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); |
8210 | inot = (struct ccb_immed_notify *)ccbh; |
8211 | switch (event->event_type) { |
8212 | case EVENT_TYPE_BUS_RESET: |
8213 | ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; |
8214 | break; |
8215 | default: |
8216 | ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; |
8217 | inot->message_args[0] = event->event_type; |
8218 | inot->message_args[1] = event->event_arg; |
8219 | break; |
8220 | } |
8221 | inot->initiator_id = event->initiator_id; |
8222 | inot->sense_len = 0; |
8223 | xpt_done((union ccb *)inot); |
8224 | lstate->event_r_idx++; |
8225 | if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) |
8226 | lstate->event_r_idx = 0; |
8227 | } |
8228 | } |
8229 | #endif |
8230 | |
8231 | /******************** Sequencer Program Patching/Download *********************/ |
8232 | |
8233 | #ifdef AHD_DUMP_SEQ |
8234 | void |
8235 | ahd_dumpseq(struct ahd_softc* ahd) |
8236 | { |
8237 | int i; |
8238 | int max_prog; |
8239 | |
8240 | max_prog = 2048; |
8241 | |
8242 | ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); |
8243 | ahd_outb(ahd, PRGMCNT, 0); |
8244 | ahd_outb(ahd, PRGMCNT+1, 0); |
8245 | for (i = 0; i < max_prog; i++) { |
8246 | uint8_t ins_bytes[4]; |
8247 | |
8248 | ahd_insb(ahd, SEQRAM, ins_bytes, 4); |
8249 | printf("0x%08x\n" , ins_bytes[0] << 24 |
8250 | | ins_bytes[1] << 16 |
8251 | | ins_bytes[2] << 8 |
8252 | | ins_bytes[3]); |
8253 | } |
8254 | } |
8255 | #endif |
8256 | |
8257 | static void |
8258 | ahd_loadseq(struct ahd_softc *ahd) |
8259 | { |
8260 | struct cs cs_table[num_critical_sections]; |
8261 | u_int begin_set[num_critical_sections]; |
8262 | u_int end_set[num_critical_sections]; |
8263 | struct patch *cur_patch; |
8264 | u_int cs_count; |
8265 | u_int cur_cs; |
8266 | u_int i; |
8267 | int downloaded; |
8268 | u_int skip_addr; |
8269 | u_int sg_prefetch_cnt; |
8270 | u_int sg_prefetch_cnt_limit; |
8271 | u_int sg_prefetch_align; |
8272 | u_int sg_size; |
8273 | uint8_t download_consts[DOWNLOAD_CONST_COUNT]; |
8274 | |
8275 | if (bootverbose) |
8276 | printf("%s: Downloading Sequencer Program..." , |
8277 | ahd_name(ahd)); |
8278 | |
8279 | #if DOWNLOAD_CONST_COUNT != 7 |
8280 | #error "Download Const Mismatch" |
8281 | #endif |
8282 | /* |
8283 | * Start out with 0 critical sections |
8284 | * that apply to this firmware load. |
8285 | */ |
8286 | cs_count = 0; |
8287 | cur_cs = 0; |
8288 | memset(begin_set, 0, sizeof(begin_set)); |
8289 | memset(end_set, 0, sizeof(end_set)); |
8290 | |
8291 | /* |
8292 | * Setup downloadable constant table. |
8293 | * |
8294 | * The computation for the S/G prefetch variables is |
8295 | * a bit complicated. We would like to always fetch |
8296 | * in terms of cachelined sized increments. However, |
8297 | * if the cacheline is not an even multiple of the |
8298 | * SG element size or is larger than our SG RAM, using |
8299 | * just the cache size might leave us with only a portion |
8300 | * of an SG element at the tail of a prefetch. If the |
8301 | * cacheline is larger than our S/G prefetch buffer less |
8302 | * the size of an SG element, we may round down to a cacheline |
8303 | * that doesn't contain any or all of the S/G of interest |
8304 | * within the bounds of our S/G ram. Provide variables to |
8305 | * the sequencer that will allow it to handle these edge |
8306 | * cases. |
8307 | */ |
8308 | /* Start by aligning to the nearest cacheline. */ |
8309 | sg_prefetch_align = ahd->pci_cachesize; |
8310 | if (sg_prefetch_align == 0) |
8311 | sg_prefetch_align = 8; |
8312 | /* Round down to the nearest power of 2. */ |
8313 | while (powerof2(sg_prefetch_align) == 0) |
8314 | sg_prefetch_align--; |
8315 | /* |
8316 | * If the cacheline boundary is greater than half our prefetch RAM |
8317 | * we risk not being able to fetch even a single complete S/G |
8318 | * segment if we align to that boundary. |
8319 | */ |
8320 | if (sg_prefetch_align > CCSGADDR_MAX/2) |
8321 | sg_prefetch_align = CCSGADDR_MAX/2; |
8322 | /* Start by fetching a single cacheline. */ |
8323 | sg_prefetch_cnt = sg_prefetch_align; |
8324 | /* |
8325 | * Increment the prefetch count by cachelines until |
8326 | * at least one S/G element will fit. |
8327 | */ |
8328 | sg_size = sizeof(struct ahd_dma_seg); |
8329 | if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) |
8330 | sg_size = sizeof(struct ahd_dma64_seg); |
8331 | while (sg_prefetch_cnt < sg_size) |
8332 | sg_prefetch_cnt += sg_prefetch_align; |
8333 | /* |
8334 | * If the cacheline is not an even multiple of |
8335 | * the S/G size, we may only get a partial S/G when |
8336 | * we align. Add a cacheline if this is the case. |
8337 | */ |
8338 | if ((sg_prefetch_align % sg_size) != 0 |
8339 | && (sg_prefetch_cnt < CCSGADDR_MAX)) |
8340 | sg_prefetch_cnt += sg_prefetch_align; |
8341 | /* |
8342 | * Lastly, compute a value that the sequencer can use |
8343 | * to determine if the remainder of the CCSGRAM buffer |
8344 | * has a full S/G element in it. |
8345 | */ |
8346 | sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1); |
8347 | download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; |
8348 | download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit; |
8349 | download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1); |
8350 | download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1); |
8351 | download_consts[SG_SIZEOF] = sg_size; |
8352 | download_consts[PKT_OVERRUN_BUFOFFSET] = |
8353 | (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256; |
8354 | download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN; |
8355 | cur_patch = patches; |
8356 | downloaded = 0; |
8357 | skip_addr = 0; |
8358 | ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); |
8359 | ahd_outb(ahd, PRGMCNT, 0); |
8360 | ahd_outb(ahd, PRGMCNT+1, 0); |
8361 | |
8362 | for (i = 0; i < sizeof(seqprog)/4; i++) { |
8363 | if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) { |
8364 | /* |
8365 | * Don't download this instruction as it |
8366 | * is in a patch that was removed. |
8367 | */ |
8368 | continue; |
8369 | } |
8370 | /* |
8371 | * Move through the CS table until we find a CS |
8372 | * that might apply to this instruction. |
8373 | */ |
8374 | for (; cur_cs < num_critical_sections; cur_cs++) { |
8375 | if (critical_sections[cur_cs].end <= i) { |
8376 | if (begin_set[cs_count] == TRUE |
8377 | && end_set[cs_count] == FALSE) { |
8378 | cs_table[cs_count].end = downloaded; |
8379 | end_set[cs_count] = TRUE; |
8380 | cs_count++; |
8381 | } |
8382 | continue; |
8383 | } |
8384 | if (critical_sections[cur_cs].begin <= i |
8385 | && begin_set[cs_count] == FALSE) { |
8386 | cs_table[cs_count].begin = downloaded; |
8387 | begin_set[cs_count] = TRUE; |
8388 | } |
8389 | break; |
8390 | } |
8391 | ahd_download_instr(ahd, i, download_consts); |
8392 | downloaded++; |
8393 | } |
8394 | |
8395 | ahd->num_critical_sections = cs_count; |
8396 | if (cs_count != 0) { |
8397 | |
8398 | cs_count *= sizeof(struct cs); |
8399 | ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); |
8400 | if (ahd->critical_sections == NULL) |
8401 | panic("ahd_loadseq: Could not malloc" ); |
8402 | memcpy(ahd->critical_sections, cs_table, cs_count); |
8403 | } |
8404 | ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE); |
8405 | |
8406 | if (bootverbose) { |
8407 | printf(" %d instructions downloaded\n" , downloaded); |
8408 | printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n" , |
8409 | ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags); |
8410 | } |
8411 | } |
8412 | |
8413 | static int |
8414 | ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch, |
8415 | u_int start_instr, u_int *skip_addr) |
8416 | { |
8417 | struct patch *cur_patch; |
8418 | struct patch *last_patch; |
8419 | u_int num_patches; |
8420 | |
8421 | num_patches = sizeof(patches)/sizeof(struct patch); |
8422 | last_patch = &patches[num_patches]; |
8423 | cur_patch = *start_patch; |
8424 | |
8425 | while (cur_patch < last_patch && start_instr == cur_patch->begin) { |
8426 | |
8427 | if (cur_patch->patch_func(ahd) == 0) { |
8428 | |
8429 | /* Start rejecting code */ |
8430 | *skip_addr = start_instr + cur_patch->skip_instr; |
8431 | cur_patch += cur_patch->skip_patch; |
8432 | } else { |
8433 | /* Accepted this patch. Advance to the next |
8434 | * one and wait for our intruction pointer to |
8435 | * hit this point. |
8436 | */ |
8437 | cur_patch++; |
8438 | } |
8439 | } |
8440 | |
8441 | *start_patch = cur_patch; |
8442 | if (start_instr < *skip_addr) |
8443 | /* Still skipping */ |
8444 | return (0); |
8445 | |
8446 | return (1); |
8447 | } |
8448 | |
8449 | static u_int |
8450 | ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address) |
8451 | { |
8452 | struct patch *cur_patch; |
8453 | int address_offset; |
8454 | u_int skip_addr; |
8455 | u_int i; |
8456 | |
8457 | address_offset = 0; |
8458 | cur_patch = patches; |
8459 | skip_addr = 0; |
8460 | |
8461 | for (i = 0; i < address;) { |
8462 | |
8463 | ahd_check_patch(ahd, &cur_patch, i, &skip_addr); |
8464 | |
8465 | if (skip_addr > i) { |
8466 | int end_addr; |
8467 | |
8468 | end_addr = MIN(address, skip_addr); |
8469 | address_offset += end_addr - i; |
8470 | i = skip_addr; |
8471 | } else { |
8472 | i++; |
8473 | } |
8474 | } |
8475 | return (address - address_offset); |
8476 | } |
8477 | |
8478 | static void |
8479 | ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts) |
8480 | { |
8481 | union ins_formats instr; |
8482 | struct ins_format1 *fmt1_ins; |
8483 | struct ins_format3 *fmt3_ins; |
8484 | u_int opcode; |
8485 | |
8486 | /* |
8487 | * The firmware is always compiled into a little endian format. |
8488 | */ |
8489 | instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); |
8490 | |
8491 | fmt1_ins = &instr.format1; |
8492 | fmt3_ins = NULL; |
8493 | |
8494 | /* Pull the opcode */ |
8495 | opcode = instr.format1.opcode; |
8496 | switch (opcode) { |
8497 | case AIC_OP_JMP: |
8498 | case AIC_OP_JC: |
8499 | case AIC_OP_JNC: |
8500 | case AIC_OP_CALL: |
8501 | case AIC_OP_JNE: |
8502 | case AIC_OP_JNZ: |
8503 | case AIC_OP_JE: |
8504 | case AIC_OP_JZ: |
8505 | { |
8506 | fmt3_ins = &instr.format3; |
8507 | fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address); |
8508 | /* FALLTHROUGH */ |
8509 | } |
8510 | case AIC_OP_OR: |
8511 | case AIC_OP_AND: |
8512 | case AIC_OP_XOR: |
8513 | case AIC_OP_ADD: |
8514 | case AIC_OP_ADC: |
8515 | case AIC_OP_BMOV: |
8516 | if (fmt1_ins->parity != 0) { |
8517 | fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; |
8518 | } |
8519 | fmt1_ins->parity = 0; |
8520 | /* FALLTHROUGH */ |
8521 | case AIC_OP_ROL: |
8522 | { |
8523 | int i, count; |
8524 | |
8525 | /* Calculate odd parity for the instruction */ |
8526 | for (i = 0, count = 0; i < 31; i++) { |
8527 | uint32_t mask; |
8528 | |
8529 | mask = 0x01 << i; |
8530 | if ((instr.integer & mask) != 0) |
8531 | count++; |
8532 | } |
8533 | if ((count & 0x01) == 0) |
8534 | instr.format1.parity = 1; |
8535 | |
8536 | /* The sequencer is a little endian CPU */ |
8537 | instr.integer = ahd_htole32(instr.integer); |
8538 | ahd_outsb(ahd, SEQRAM, instr.bytes, 4); |
8539 | break; |
8540 | } |
8541 | default: |
8542 | panic("Unknown opcode encountered in seq program" ); |
8543 | break; |
8544 | } |
8545 | } |
8546 | |
8547 | static int |
8548 | ahd_probe_stack_size(struct ahd_softc *ahd) |
8549 | { |
8550 | int last_probe; |
8551 | |
8552 | last_probe = 0; |
8553 | while (1) { |
8554 | int i; |
8555 | |
8556 | /* |
8557 | * We avoid using 0 as a pattern to avoid |
8558 | * confusion if the stack implementation |
8559 | * "back-fills" with zeros when "poping' |
8560 | * entries. |
8561 | */ |
8562 | for (i = 1; i <= last_probe+1; i++) { |
8563 | ahd_outb(ahd, STACK, i & 0xFF); |
8564 | ahd_outb(ahd, STACK, (i >> 8) & 0xFF); |
8565 | } |
8566 | |
8567 | /* Verify */ |
8568 | for (i = last_probe+1; i > 0; i--) { |
8569 | u_int stack_entry; |
8570 | |
8571 | stack_entry = ahd_inb(ahd, STACK) |
8572 | |(ahd_inb(ahd, STACK) << 8); |
8573 | if (stack_entry != i) |
8574 | goto sized; |
8575 | } |
8576 | last_probe++; |
8577 | } |
8578 | sized: |
8579 | return (last_probe); |
8580 | } |
8581 | |
8582 | void |
8583 | ahd_dump_all_cards_state(void) |
8584 | { |
8585 | struct ahd_softc *list_ahd; |
8586 | |
8587 | TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { |
8588 | ahd_dump_card_state(list_ahd); |
8589 | } |
8590 | } |
8591 | |
8592 | int |
8593 | ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries, |
8594 | const char *name, u_int address, u_int value, |
8595 | u_int *cur_column, u_int wrap_point) |
8596 | { |
8597 | size_t printed; |
8598 | u_int printed_mask; |
8599 | char line[1024]; |
8600 | |
8601 | line[0] = 0; |
8602 | |
8603 | if (cur_column != NULL && *cur_column >= wrap_point) { |
8604 | printf("\n" ); |
8605 | *cur_column = 0; |
8606 | } |
8607 | printed = snprintf(line, sizeof(line), "%s[0x%x]" , name, value); |
8608 | printed = sizeof(line); |
8609 | if (table == NULL) { |
8610 | if (printed < sizeof(line)) |
8611 | printed += snprintf(&line[printed], |
8612 | (sizeof line) - printed, " " ); |
8613 | printf("%s" , line); |
8614 | if (cur_column != NULL) |
8615 | *cur_column += printed; |
8616 | return (printed); |
8617 | } |
8618 | printed_mask = 0; |
8619 | while (printed_mask != 0xFF) { |
8620 | int entry; |
8621 | |
8622 | for (entry = 0; entry < num_entries; entry++) { |
8623 | if (((value & table[entry].mask) |
8624 | != table[entry].value) |
8625 | || ((printed_mask & table[entry].mask) |
8626 | == table[entry].mask)) |
8627 | continue; |
8628 | if (printed < sizeof(line)) |
8629 | printed += snprintf(&line[printed], |
8630 | (sizeof line) - printed, "%s%s" , |
8631 | printed_mask == 0 ? ":(" : "|" , |
8632 | table[entry].name); |
8633 | printed_mask |= table[entry].mask; |
8634 | |
8635 | break; |
8636 | } |
8637 | if (entry >= num_entries) |
8638 | break; |
8639 | } |
8640 | if (printed < sizeof(line)) { |
8641 | if (printed_mask != 0) |
8642 | printed += snprintf(&line[printed], |
8643 | (sizeof line) - printed, ") " ); |
8644 | else |
8645 | printed += snprintf(&line[printed], |
8646 | (sizeof line) - printed, " " ); |
8647 | } |
8648 | if (cur_column != NULL) |
8649 | *cur_column += printed; |
8650 | printf("%s" , line); |
8651 | |
8652 | return (printed); |
8653 | } |
8654 | |
8655 | void |
8656 | ahd_dump_card_state(struct ahd_softc *ahd) |
8657 | { |
8658 | struct scb *scb; |
8659 | ahd_mode_state saved_modes; |
8660 | u_int dffstat; |
8661 | int paused; |
8662 | u_int scb_index; |
8663 | u_int saved_scb_index; |
8664 | u_int cur_col; |
8665 | int i; |
8666 | |
8667 | if (ahd_is_paused(ahd)) { |
8668 | paused = 1; |
8669 | } else { |
8670 | paused = 0; |
8671 | ahd_pause(ahd); |
8672 | } |
8673 | saved_modes = ahd_save_modes(ahd); |
8674 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
8675 | printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" |
8676 | "%s: Dumping Card State at program address 0x%x Mode 0x%x\n" , |
8677 | ahd_name(ahd), |
8678 | ahd_inb(ahd, CURADDR) | (ahd_inb(ahd, CURADDR+1) << 8), |
8679 | ahd_build_mode_state(ahd, ahd->saved_src_mode, |
8680 | ahd->saved_dst_mode)); |
8681 | if (paused) |
8682 | printf("Card was paused\n" ); |
8683 | |
8684 | if (ahd_check_cmdcmpltqueues(ahd)) |
8685 | printf("Completions are pending\n" ); |
8686 | /* |
8687 | * Mode independent registers. |
8688 | */ |
8689 | cur_col = 0; |
8690 | ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50); |
8691 | ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50); |
8692 | ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50); |
8693 | ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50); |
8694 | ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50); |
8695 | ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50); |
8696 | ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50); |
8697 | ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50); |
8698 | ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50); |
8699 | ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50); |
8700 | ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50); |
8701 | ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50); |
8702 | ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50); |
8703 | ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50); |
8704 | ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50); |
8705 | ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50); |
8706 | ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50); |
8707 | ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50); |
8708 | ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50); |
8709 | ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50); |
8710 | ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50); |
8711 | ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50); |
8712 | ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50); |
8713 | ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50); |
8714 | ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50); |
8715 | ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50); |
8716 | ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50); |
8717 | printf("\n" ); |
8718 | printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x " |
8719 | "CURRSCB 0x%x NEXTSCB 0x%x\n" , |
8720 | ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING), |
8721 | ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB), |
8722 | ahd_inw(ahd, NEXTSCB)); |
8723 | cur_col = 0; |
8724 | /* QINFIFO */ |
8725 | ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, |
8726 | CAM_LUN_WILDCARD, SCB_LIST_NULL, |
8727 | ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT); |
8728 | saved_scb_index = ahd_get_scbptr(ahd); |
8729 | printf("Pending list:" ); |
8730 | i = 0; |
8731 | LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { |
8732 | if (i++ > AHD_SCB_MAX) |
8733 | break; |
8734 | /*cur_col =*/ printf("\n%3d FIFO_USE[0x%x] " , SCB_GET_TAG(scb), |
8735 | ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT)); |
8736 | ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); |
8737 | ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL), |
8738 | &cur_col, 60); |
8739 | ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID), |
8740 | &cur_col, 60); |
8741 | } |
8742 | printf("\nTotal %d\n" , i); |
8743 | |
8744 | printf("Kernel Free SCB list: " ); |
8745 | i = 0; |
8746 | TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { |
8747 | struct scb *list_scb; |
8748 | |
8749 | list_scb = scb; |
8750 | do { |
8751 | printf("%d " , SCB_GET_TAG(list_scb)); |
8752 | list_scb = LIST_NEXT(list_scb, collision_links); |
8753 | } while (list_scb && i++ < AHD_SCB_MAX); |
8754 | } |
8755 | |
8756 | LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { |
8757 | if (i++ > AHD_SCB_MAX) |
8758 | break; |
8759 | printf("%d " , SCB_GET_TAG(scb)); |
8760 | } |
8761 | printf("\n" ); |
8762 | |
8763 | printf("Sequencer Complete DMA-inprog list: " ); |
8764 | scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD); |
8765 | i = 0; |
8766 | while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { |
8767 | ahd_set_scbptr(ahd, scb_index); |
8768 | printf("%d " , scb_index); |
8769 | scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); |
8770 | } |
8771 | printf("\n" ); |
8772 | |
8773 | printf("Sequencer Complete list: " ); |
8774 | scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD); |
8775 | i = 0; |
8776 | while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { |
8777 | ahd_set_scbptr(ahd, scb_index); |
8778 | printf("%d " , scb_index); |
8779 | scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); |
8780 | } |
8781 | printf("\n" ); |
8782 | |
8783 | |
8784 | printf("Sequencer DMA-Up and Complete list: " ); |
8785 | scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); |
8786 | i = 0; |
8787 | while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { |
8788 | ahd_set_scbptr(ahd, scb_index); |
8789 | printf("%d " , scb_index); |
8790 | scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); |
8791 | } |
8792 | printf("\n" ); |
8793 | ahd_set_scbptr(ahd, saved_scb_index); |
8794 | dffstat = ahd_inb(ahd, DFFSTAT); |
8795 | for (i = 0; i < 2; i++) { |
8796 | #ifdef AHD_DEBUG |
8797 | struct scb *fifo_scb; |
8798 | #endif |
8799 | u_int fifo_scbptr; |
8800 | |
8801 | ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); |
8802 | fifo_scbptr = ahd_get_scbptr(ahd); |
8803 | printf("\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n" , |
8804 | ahd_name(ahd), i, |
8805 | (dffstat & (FIFO0FREE << i)) ? "Free" : "Active" , |
8806 | ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr); |
8807 | cur_col = 0; |
8808 | ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50); |
8809 | ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50); |
8810 | ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50); |
8811 | ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50); |
8812 | ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW), |
8813 | &cur_col, 50); |
8814 | ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50); |
8815 | ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50); |
8816 | ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50); |
8817 | ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50); |
8818 | if (cur_col > 50) { |
8819 | printf("\n" ); |
8820 | cur_col = 0; |
8821 | } |
8822 | printf("\nSHADDR = 0x%x%x, SHCNT = 0x%x " , |
8823 | ahd_inl(ahd, SHADDR+4), |
8824 | ahd_inl(ahd, SHADDR), |
8825 | (ahd_inb(ahd, SHCNT) |
8826 | | (ahd_inb(ahd, SHCNT + 1) << 8) |
8827 | | (ahd_inb(ahd, SHCNT + 2) << 16))); |
8828 | printf("HADDR = 0x%x%x, HCNT = 0x%x \n" , |
8829 | ahd_inl(ahd, HADDR+4), |
8830 | ahd_inl(ahd, HADDR), |
8831 | (ahd_inb(ahd, HCNT) |
8832 | | (ahd_inb(ahd, HCNT + 1) << 8) |
8833 | | (ahd_inb(ahd, HCNT + 2) << 16))); |
8834 | ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50); |
8835 | #ifdef AHD_DEBUG |
8836 | if ((ahd_debug & AHD_SHOW_SG) != 0) { |
8837 | fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr); |
8838 | if (fifo_scb != NULL) |
8839 | ahd_dump_sglist(fifo_scb); |
8840 | } |
8841 | #endif |
8842 | } |
8843 | printf("\nLQIN: " ); |
8844 | for (i = 0; i < 20; i++) |
8845 | printf("0x%x " , ahd_inb(ahd, LQIN + i)); |
8846 | printf("\n" ); |
8847 | ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); |
8848 | printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n" , |
8849 | ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE), |
8850 | ahd_inb(ahd, OPTIONMODE)); |
8851 | printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n" , |
8852 | ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT), |
8853 | ahd_inb(ahd, MAXCMDCNT)); |
8854 | ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50); |
8855 | printf("\n" ); |
8856 | ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); |
8857 | cur_col = 0; |
8858 | ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); |
8859 | printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n" , |
8860 | ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX), |
8861 | ahd_inw(ahd, DINDEX)); |
8862 | printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n" , |
8863 | ahd_name(ahd), ahd_get_scbptr(ahd), |
8864 | ahd_inw_scbram(ahd, SCB_NEXT), |
8865 | ahd_inw_scbram(ahd, SCB_NEXT2)); |
8866 | printf("CDB %x %x %x %x %x %x\n" , |
8867 | ahd_inb_scbram(ahd, SCB_CDB_STORE), |
8868 | ahd_inb_scbram(ahd, SCB_CDB_STORE+1), |
8869 | ahd_inb_scbram(ahd, SCB_CDB_STORE+2), |
8870 | ahd_inb_scbram(ahd, SCB_CDB_STORE+3), |
8871 | ahd_inb_scbram(ahd, SCB_CDB_STORE+4), |
8872 | ahd_inb_scbram(ahd, SCB_CDB_STORE+5)); |
8873 | printf("STACK:" ); |
8874 | for (i = 0; i < ahd->stack_size; i++) { |
8875 | ahd->saved_stack[i] = |
8876 | ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8); |
8877 | printf(" 0x%x" , ahd->saved_stack[i]); |
8878 | } |
8879 | for (i = ahd->stack_size-1; i >= 0; i--) { |
8880 | ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF); |
8881 | ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF); |
8882 | } |
8883 | printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n" ); |
8884 | ahd_platform_dump_card_state(ahd); |
8885 | ahd_restore_modes(ahd, saved_modes); |
8886 | if (paused == 0) |
8887 | ahd_unpause(ahd); |
8888 | } |
8889 | |
8890 | void |
8891 | ahd_dump_scbs(struct ahd_softc *ahd) |
8892 | { |
8893 | ahd_mode_state saved_modes; |
8894 | u_int saved_scb_index; |
8895 | int i; |
8896 | |
8897 | saved_modes = ahd_save_modes(ahd); |
8898 | ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); |
8899 | saved_scb_index = ahd_get_scbptr(ahd); |
8900 | for (i = 0; i < AHD_SCB_MAX; i++) { |
8901 | ahd_set_scbptr(ahd, i); |
8902 | printf("%3d" , i); |
8903 | printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n" , |
8904 | ahd_inb_scbram(ahd, SCB_CONTROL), |
8905 | ahd_inb_scbram(ahd, SCB_SCSIID), |
8906 | ahd_inw_scbram(ahd, SCB_NEXT), |
8907 | ahd_inw_scbram(ahd, SCB_NEXT2), |
8908 | ahd_inl_scbram(ahd, SCB_SGPTR), |
8909 | ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR)); |
8910 | } |
8911 | printf("\n" ); |
8912 | ahd_set_scbptr(ahd, saved_scb_index); |
8913 | ahd_restore_modes(ahd, saved_modes); |
8914 | } |
8915 | |
8916 | /**************************** Flexport Logic **********************************/ |
8917 | /* |
8918 | * Read count 16bit words from 16bit word address start_addr from the |
8919 | * SEEPROM attached to the controller, into tbuf, using the controller's |
8920 | * SEEPROM reading state machine. Optionally treat the data as a byte |
8921 | * stream in terms of byte order. |
8922 | */ |
8923 | int |
8924 | ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *tbuf, |
8925 | u_int start_addr, u_int count, int bytestream) |
8926 | { |
8927 | u_int cur_addr; |
8928 | u_int end_addr; |
8929 | int error; |
8930 | |
8931 | /* |
8932 | * If we never make it through the loop even once, |
8933 | * we were passed invalid arguments. |
8934 | */ |
8935 | error = EINVAL; |
8936 | AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); |
8937 | end_addr = start_addr + count; |
8938 | for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { |
8939 | |
8940 | ahd_outb(ahd, SEEADR, cur_addr); |
8941 | ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART); |
8942 | |
8943 | error = ahd_wait_seeprom(ahd); |
8944 | if (error) { |
8945 | printf("%s: ahd_wait_seeprom timed out\n" , |
8946 | ahd_name(ahd)); |
8947 | break; |
8948 | } |
8949 | if (bytestream != 0) { |
8950 | uint8_t *bytestream_ptr; |
8951 | |
8952 | bytestream_ptr = (uint8_t *)tbuf; |
8953 | *bytestream_ptr++ = ahd_inb(ahd, SEEDAT); |
8954 | *bytestream_ptr = ahd_inb(ahd, SEEDAT+1); |
8955 | } else { |
8956 | /* |
8957 | * ahd_inw() already handles machine byte order. |
8958 | */ |
8959 | *tbuf = ahd_inw(ahd, SEEDAT); |
8960 | } |
8961 | tbuf++; |
8962 | } |
8963 | return (error); |
8964 | } |
8965 | |
8966 | /* |
8967 | * Write count 16bit words from tbuf, into SEEPROM attache to the |
8968 | * controller starting at 16bit word address start_addr, using the |
8969 | * controller's SEEPROM writing state machine. |
8970 | */ |
8971 | int |
8972 | ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *tbuf, |
8973 | u_int start_addr, u_int count) |
8974 | { |
8975 | u_int cur_addr; |
8976 | u_int end_addr; |
8977 | int error; |
8978 | int retval; |
8979 | |
8980 | AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); |
8981 | error = ENOENT; |
8982 | |
8983 | /* Place the chip into write-enable mode */ |
8984 | ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR); |
8985 | ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART); |
8986 | error = ahd_wait_seeprom(ahd); |
8987 | if (error) |
8988 | return (error); |
8989 | |
8990 | /* |
8991 | * Write the data. If we don't get throught the loop at |
8992 | * least once, the arguments were invalid. |
8993 | */ |
8994 | retval = EINVAL; |
8995 | end_addr = start_addr + count; |
8996 | for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { |
8997 | ahd_outw(ahd, SEEDAT, *tbuf++); |
8998 | ahd_outb(ahd, SEEADR, cur_addr); |
8999 | ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART); |
9000 | |
9001 | retval = ahd_wait_seeprom(ahd); |
9002 | if (retval) |
9003 | break; |
9004 | } |
9005 | |
9006 | /* |
9007 | * Disable writes. |
9008 | */ |
9009 | ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR); |
9010 | ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART); |
9011 | error = ahd_wait_seeprom(ahd); |
9012 | if (error) |
9013 | return (error); |
9014 | return (retval); |
9015 | } |
9016 | |
9017 | /* |
9018 | * Wait ~100us for the serial eeprom to satisfy our request. |
9019 | */ |
9020 | int |
9021 | ahd_wait_seeprom(struct ahd_softc *ahd) |
9022 | { |
9023 | int cnt; |
9024 | |
9025 | cnt = 2000; |
9026 | while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt) |
9027 | ahd_delay(5); |
9028 | |
9029 | if (cnt == 0) |
9030 | return (ETIMEDOUT); |
9031 | return (0); |
9032 | } |
9033 | |
9034 | /* |
9035 | * Validate the two checksums in the per_channel |
9036 | * vital product data struct. |
9037 | */ |
9038 | int |
9039 | ahd_verify_vpd_cksum(struct vpd_config *vpd) |
9040 | { |
9041 | int i; |
9042 | int maxaddr; |
9043 | uint32_t checksum; |
9044 | uint8_t *vpdarray; |
9045 | |
9046 | vpdarray = (uint8_t *)vpd; |
9047 | maxaddr = offsetof(struct vpd_config, vpd_checksum); |
9048 | checksum = 0; |
9049 | for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++) |
9050 | checksum = checksum + vpdarray[i]; |
9051 | if (checksum == 0 |
9052 | || (-checksum & 0xFF) != vpd->vpd_checksum) |
9053 | return (0); |
9054 | |
9055 | checksum = 0; |
9056 | maxaddr = offsetof(struct vpd_config, checksum); |
9057 | for (i = offsetof(struct vpd_config, default_target_flags); |
9058 | i < maxaddr; i++) |
9059 | checksum = checksum + vpdarray[i]; |
9060 | if (checksum == 0 |
9061 | || (-checksum & 0xFF) != vpd->checksum) |
9062 | return (0); |
9063 | return (1); |
9064 | } |
9065 | |
9066 | int |
9067 | ahd_verify_cksum(struct seeprom_config *sc) |
9068 | { |
9069 | int i; |
9070 | int maxaddr; |
9071 | uint32_t checksum; |
9072 | uint16_t *scarray; |
9073 | |
9074 | maxaddr = (sizeof(*sc)/2) - 1; |
9075 | checksum = 0; |
9076 | scarray = (uint16_t *)sc; |
9077 | |
9078 | for (i = 0; i < maxaddr; i++) |
9079 | checksum = checksum + scarray[i]; |
9080 | if (checksum == 0 |
9081 | || (checksum & 0xFFFF) != sc->checksum) { |
9082 | return (0); |
9083 | } else { |
9084 | return (1); |
9085 | } |
9086 | } |
9087 | |
9088 | int |
9089 | ahd_acquire_seeprom(struct ahd_softc *ahd) |
9090 | { |
9091 | /* |
9092 | * We should be able to determine the SEEPROM type |
9093 | * from the flexport logic, but unfortunately not |
9094 | * all implementations have this logic and there is |
9095 | * no programatic method for determining if the logic |
9096 | * is present. |
9097 | */ |
9098 | |
9099 | return (1); |
9100 | #if 0 |
9101 | uint8_t seetype; |
9102 | int error; |
9103 | |
9104 | error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype); |
9105 | if (error != 0 |
9106 | || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE)) |
9107 | return (0); |
9108 | return (1); |
9109 | #endif |
9110 | } |
9111 | |
9112 | void |
9113 | ahd_release_seeprom(struct ahd_softc *ahd) |
9114 | { |
9115 | /* Currently a no-op */ |
9116 | } |
9117 | |
9118 | int |
9119 | ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value) |
9120 | { |
9121 | int error; |
9122 | |
9123 | AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); |
9124 | if (addr > 7) |
9125 | panic("ahd_write_flexport: address out of range" ); |
9126 | ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); |
9127 | error = ahd_wait_flexport(ahd); |
9128 | if (error != 0) |
9129 | return (error); |
9130 | ahd_outb(ahd, BRDDAT, value); |
9131 | ahd_flush_device_writes(ahd); |
9132 | ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3)); |
9133 | ahd_flush_device_writes(ahd); |
9134 | ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); |
9135 | ahd_flush_device_writes(ahd); |
9136 | ahd_outb(ahd, BRDCTL, 0); |
9137 | ahd_flush_device_writes(ahd); |
9138 | return (0); |
9139 | } |
9140 | |
9141 | int |
9142 | ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value) |
9143 | { |
9144 | int error; |
9145 | |
9146 | AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); |
9147 | if (addr > 7) |
9148 | panic("ahd_read_flexport: address out of range" ); |
9149 | ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3)); |
9150 | error = ahd_wait_flexport(ahd); |
9151 | if (error != 0) |
9152 | return (error); |
9153 | *value = ahd_inb(ahd, BRDDAT); |
9154 | ahd_outb(ahd, BRDCTL, 0); |
9155 | ahd_flush_device_writes(ahd); |
9156 | return (0); |
9157 | } |
9158 | |
9159 | /* |
9160 | * Wait at most 2 seconds for flexport arbitration to succeed. |
9161 | */ |
9162 | int |
9163 | ahd_wait_flexport(struct ahd_softc *ahd) |
9164 | { |
9165 | int cnt; |
9166 | |
9167 | AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); |
9168 | cnt = 1000000 * 2 / 5; |
9169 | while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt) |
9170 | ahd_delay(5); |
9171 | |
9172 | if (cnt == 0) |
9173 | return (ETIMEDOUT); |
9174 | return (0); |
9175 | } |
9176 | |
9177 | /************************* Target Mode ****************************************/ |
9178 | #ifdef AHD_TARGET_MODE |
9179 | cam_status |
9180 | ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb, |
9181 | struct ahd_tmode_tstate **tstate, |
9182 | struct ahd_tmode_lstate **lstate, |
9183 | int notfound_failure) |
9184 | { |
9185 | |
9186 | if ((ahd->features & AHD_TARGETMODE) == 0) |
9187 | return (CAM_REQ_INVALID); |
9188 | |
9189 | /* |
9190 | * Handle the 'black hole' device that sucks up |
9191 | * requests to unattached luns on enabled targets. |
9192 | */ |
9193 | if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD |
9194 | && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { |
9195 | *tstate = NULL; |
9196 | *lstate = ahd->black_hole; |
9197 | } else { |
9198 | u_int max_id; |
9199 | |
9200 | max_id = (ahd->features & AHD_WIDE) ? 15 : 7; |
9201 | if (ccb->ccb_h.target_id > max_id) |
9202 | return (CAM_TID_INVALID); |
9203 | |
9204 | if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS) |
9205 | return (CAM_LUN_INVALID); |
9206 | |
9207 | *tstate = ahd->enabled_targets[ccb->ccb_h.target_id]; |
9208 | *lstate = NULL; |
9209 | if (*tstate != NULL) |
9210 | *lstate = |
9211 | (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; |
9212 | } |
9213 | |
9214 | if (notfound_failure != 0 && *lstate == NULL) |
9215 | return (CAM_PATH_INVALID); |
9216 | |
9217 | return (CAM_REQ_CMP); |
9218 | } |
9219 | |
9220 | void |
9221 | ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb) |
9222 | { |
9223 | #if NOT_YET |
9224 | struct ahd_tmode_tstate *tstate; |
9225 | struct ahd_tmode_lstate *lstate; |
9226 | struct ccb_en_lun *cel; |
9227 | cam_status status; |
9228 | u_int target; |
9229 | u_int lun; |
9230 | u_int target_mask; |
9231 | u_long s; |
9232 | char channel; |
9233 | |
9234 | status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate, |
9235 | /*notfound_failure*/FALSE); |
9236 | |
9237 | if (status != CAM_REQ_CMP) { |
9238 | ccb->ccb_h.status = status; |
9239 | return; |
9240 | } |
9241 | |
9242 | if ((ahd->features & AHD_MULTIROLE) != 0) { |
9243 | u_int our_id; |
9244 | |
9245 | our_id = ahd->our_id; |
9246 | if (ccb->ccb_h.target_id != our_id) { |
9247 | if ((ahd->features & AHD_MULTI_TID) != 0 |
9248 | && (ahd->flags & AHD_INITIATORROLE) != 0) { |
9249 | /* |
9250 | * Only allow additional targets if |
9251 | * the initiator role is disabled. |
9252 | * The hardware cannot handle a re-select-in |
9253 | * on the initiator id during a re-select-out |
9254 | * on a different target id. |
9255 | */ |
9256 | status = CAM_TID_INVALID; |
9257 | } else if ((ahd->flags & AHD_INITIATORROLE) != 0 |
9258 | || ahd->enabled_luns > 0) { |
9259 | /* |
9260 | * Only allow our target id to change |
9261 | * if the initiator role is not configured |
9262 | * and there are no enabled luns which |
9263 | * are attached to the currently registered |
9264 | * scsi id. |
9265 | */ |
9266 | status = CAM_TID_INVALID; |
9267 | } |
9268 | } |
9269 | } |
9270 | |
9271 | if (status != CAM_REQ_CMP) { |
9272 | ccb->ccb_h.status = status; |
9273 | return; |
9274 | } |
9275 | |
9276 | /* |
9277 | * We now have an id that is valid. |
9278 | * If we aren't in target mode, switch modes. |
9279 | */ |
9280 | if ((ahd->flags & AHD_TARGETROLE) == 0 |
9281 | && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { |
9282 | u_long s; |
9283 | |
9284 | printf("Configuring Target Mode\n" ); |
9285 | ahd_lock(ahd, &s); |
9286 | if (LIST_FIRST(&ahd->pending_scbs) != NULL) { |
9287 | ccb->ccb_h.status = CAM_BUSY; |
9288 | ahd_unlock(ahd, &s); |
9289 | return; |
9290 | } |
9291 | ahd->flags |= AHD_TARGETROLE; |
9292 | if ((ahd->features & AHD_MULTIROLE) == 0) |
9293 | ahd->flags &= ~AHD_INITIATORROLE; |
9294 | ahd_pause(ahd); |
9295 | ahd_loadseq(ahd); |
9296 | ahd_restart(ahd); |
9297 | ahd_unlock(ahd, &s); |
9298 | } |
9299 | cel = &ccb->cel; |
9300 | target = ccb->ccb_h.target_id; |
9301 | lun = ccb->ccb_h.target_lun; |
9302 | channel = SIM_CHANNEL(ahd, sim); |
9303 | target_mask = 0x01 << target; |
9304 | if (channel == 'B') |
9305 | target_mask <<= 8; |
9306 | |
9307 | if (cel->enable != 0) { |
9308 | u_int scsiseq1; |
9309 | |
9310 | /* Are we already enabled?? */ |
9311 | if (lstate != NULL) { |
9312 | xpt_print_path(ccb->ccb_h.path); |
9313 | printf("Lun already enabled\n" ); |
9314 | ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; |
9315 | return; |
9316 | } |
9317 | |
9318 | if (cel->grp6_len != 0 |
9319 | || cel->grp7_len != 0) { |
9320 | /* |
9321 | * Don't (yet?) support vendor |
9322 | * specific commands. |
9323 | */ |
9324 | ccb->ccb_h.status = CAM_REQ_INVALID; |
9325 | printf("Non-zero Group Codes\n" ); |
9326 | return; |
9327 | } |
9328 | |
9329 | /* |
9330 | * Seems to be okay. |
9331 | * Setup our data structures. |
9332 | */ |
9333 | if (target != CAM_TARGET_WILDCARD && tstate == NULL) { |
9334 | tstate = ahd_alloc_tstate(ahd, target, channel); |
9335 | if (tstate == NULL) { |
9336 | xpt_print_path(ccb->ccb_h.path); |
9337 | printf("Couldn't allocate tstate\n" ); |
9338 | ccb->ccb_h.status = CAM_RESRC_UNAVAIL; |
9339 | return; |
9340 | } |
9341 | } |
9342 | lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); |
9343 | if (lstate == NULL) { |
9344 | xpt_print_path(ccb->ccb_h.path); |
9345 | printf("Couldn't allocate lstate\n" ); |
9346 | ccb->ccb_h.status = CAM_RESRC_UNAVAIL; |
9347 | return; |
9348 | } |
9349 | memset(lstate, 0, sizeof(*lstate)); |
9350 | status = xpt_create_path(&lstate->path, /*periph*/NULL, |
9351 | xpt_path_path_id(ccb->ccb_h.path), |
9352 | xpt_path_target_id(ccb->ccb_h.path), |
9353 | xpt_path_lun_id(ccb->ccb_h.path)); |
9354 | if (status != CAM_REQ_CMP) { |
9355 | free(lstate, M_DEVBUF); |
9356 | xpt_print_path(ccb->ccb_h.path); |
9357 | printf("Couldn't allocate path\n" ); |
9358 | ccb->ccb_h.status = CAM_RESRC_UNAVAIL; |
9359 | return; |
9360 | } |
9361 | SLIST_INIT(&lstate->accept_tios); |
9362 | SLIST_INIT(&lstate->immed_notifies); |
9363 | ahd_lock(ahd, &s); |
9364 | ahd_pause(ahd); |
9365 | if (target != CAM_TARGET_WILDCARD) { |
9366 | tstate->enabled_luns[lun] = lstate; |
9367 | ahd->enabled_luns++; |
9368 | |
9369 | if ((ahd->features & AHD_MULTI_TID) != 0) { |
9370 | u_int targid_mask; |
9371 | |
9372 | targid_mask = ahd_inb(ahd, TARGID) |
9373 | | (ahd_inb(ahd, TARGID + 1) << 8); |
9374 | |
9375 | targid_mask |= target_mask; |
9376 | ahd_outb(ahd, TARGID, targid_mask); |
9377 | ahd_outb(ahd, TARGID+1, (targid_mask >> 8)); |
9378 | |
9379 | ahd_update_scsiid(ahd, targid_mask); |
9380 | } else { |
9381 | u_int our_id; |
9382 | char channel; |
9383 | |
9384 | channel = SIM_CHANNEL(ahd, sim); |
9385 | our_id = SIM_SCSI_ID(ahd, sim); |
9386 | |
9387 | /* |
9388 | * This can only happen if selections |
9389 | * are not enabled |
9390 | */ |
9391 | if (target != our_id) { |
9392 | u_int sblkctl; |
9393 | char cur_channel; |
9394 | int swap; |
9395 | |
9396 | sblkctl = ahd_inb(ahd, SBLKCTL); |
9397 | cur_channel = (sblkctl & SELBUSB) |
9398 | ? 'B' : 'A'; |
9399 | if ((ahd->features & AHD_TWIN) == 0) |
9400 | cur_channel = 'A'; |
9401 | swap = cur_channel != channel; |
9402 | ahd->our_id = target; |
9403 | |
9404 | if (swap) |
9405 | ahd_outb(ahd, SBLKCTL, |
9406 | sblkctl ^ SELBUSB); |
9407 | |
9408 | ahd_outb(ahd, SCSIID, target); |
9409 | |
9410 | if (swap) |
9411 | ahd_outb(ahd, SBLKCTL, sblkctl); |
9412 | } |
9413 | } |
9414 | } else |
9415 | ahd->black_hole = lstate; |
9416 | /* Allow select-in operations */ |
9417 | if (ahd->black_hole != NULL && ahd->enabled_luns > 0) { |
9418 | scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); |
9419 | scsiseq1 |= ENSELI; |
9420 | ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); |
9421 | scsiseq1 = ahd_inb(ahd, SCSISEQ1); |
9422 | scsiseq1 |= ENSELI; |
9423 | ahd_outb(ahd, SCSISEQ1, scsiseq1); |
9424 | } |
9425 | ahd_unpause(ahd); |
9426 | ahd_unlock(ahd, &s); |
9427 | ccb->ccb_h.status = CAM_REQ_CMP; |
9428 | xpt_print_path(ccb->ccb_h.path); |
9429 | printf("Lun now enabled for target mode\n" ); |
9430 | } else { |
9431 | struct scb *scb; |
9432 | int i, empty; |
9433 | |
9434 | if (lstate == NULL) { |
9435 | ccb->ccb_h.status = CAM_LUN_INVALID; |
9436 | return; |
9437 | } |
9438 | |
9439 | ahd_lock(ahd, &s); |
9440 | |
9441 | ccb->ccb_h.status = CAM_REQ_CMP; |
9442 | LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { |
9443 | struct ccb_hdr *ccbh; |
9444 | |
9445 | ccbh = &scb->io_ctx->ccb_h; |
9446 | if (ccbh->func_code == XPT_CONT_TARGET_IO |
9447 | && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ |
9448 | printf("CTIO pending\n" ); |
9449 | ccb->ccb_h.status = CAM_REQ_INVALID; |
9450 | ahd_unlock(ahd, &s); |
9451 | return; |
9452 | } |
9453 | } |
9454 | |
9455 | if (SLIST_FIRST(&lstate->accept_tios) != NULL) { |
9456 | printf("ATIOs pending\n" ); |
9457 | ccb->ccb_h.status = CAM_REQ_INVALID; |
9458 | } |
9459 | |
9460 | if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { |
9461 | printf("INOTs pending\n" ); |
9462 | ccb->ccb_h.status = CAM_REQ_INVALID; |
9463 | } |
9464 | |
9465 | if (ccb->ccb_h.status != CAM_REQ_CMP) { |
9466 | ahd_unlock(ahd, &s); |
9467 | return; |
9468 | } |
9469 | |
9470 | xpt_print_path(ccb->ccb_h.path); |
9471 | printf("Target mode disabled\n" ); |
9472 | xpt_free_path(lstate->path); |
9473 | free(lstate, M_DEVBUF); |
9474 | |
9475 | ahd_pause(ahd); |
9476 | /* Can we clean up the target too? */ |
9477 | if (target != CAM_TARGET_WILDCARD) { |
9478 | tstate->enabled_luns[lun] = NULL; |
9479 | ahd->enabled_luns--; |
9480 | for (empty = 1, i = 0; i < 8; i++) |
9481 | if (tstate->enabled_luns[i] != NULL) { |
9482 | empty = 0; |
9483 | break; |
9484 | } |
9485 | |
9486 | if (empty) { |
9487 | ahd_free_tstate(ahd, target, channel, |
9488 | /*force*/FALSE); |
9489 | if (ahd->features & AHD_MULTI_TID) { |
9490 | u_int targid_mask; |
9491 | |
9492 | targid_mask = ahd_inb(ahd, TARGID) |
9493 | | (ahd_inb(ahd, TARGID + 1) |
9494 | << 8); |
9495 | |
9496 | targid_mask &= ~target_mask; |
9497 | ahd_outb(ahd, TARGID, targid_mask); |
9498 | ahd_outb(ahd, TARGID+1, |
9499 | (targid_mask >> 8)); |
9500 | ahd_update_scsiid(ahd, targid_mask); |
9501 | } |
9502 | } |
9503 | } else { |
9504 | |
9505 | ahd->black_hole = NULL; |
9506 | |
9507 | /* |
9508 | * We can't allow selections without |
9509 | * our black hole device. |
9510 | */ |
9511 | empty = TRUE; |
9512 | } |
9513 | if (ahd->enabled_luns == 0) { |
9514 | /* Disallow select-in */ |
9515 | u_int scsiseq1; |
9516 | |
9517 | scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); |
9518 | scsiseq1 &= ~ENSELI; |
9519 | ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); |
9520 | scsiseq1 = ahd_inb(ahd, SCSISEQ1); |
9521 | scsiseq1 &= ~ENSELI; |
9522 | ahd_outb(ahd, SCSISEQ1, scsiseq1); |
9523 | |
9524 | if ((ahd->features & AHD_MULTIROLE) == 0) { |
9525 | printf("Configuring Initiator Mode\n" ); |
9526 | ahd->flags &= ~AHD_TARGETROLE; |
9527 | ahd->flags |= AHD_INITIATORROLE; |
9528 | ahd_pause(ahd); |
9529 | ahd_loadseq(ahd); |
9530 | ahd_restart(ahd); |
9531 | /* |
9532 | * Unpaused. The extra unpause |
9533 | * that follows is harmless. |
9534 | */ |
9535 | } |
9536 | } |
9537 | ahd_unpause(ahd); |
9538 | ahd_unlock(ahd, &s); |
9539 | } |
9540 | #endif |
9541 | } |
9542 | |
9543 | static void |
9544 | ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask) |
9545 | { |
9546 | #if NOT_YET |
9547 | u_int scsiid_mask; |
9548 | u_int scsiid; |
9549 | |
9550 | if ((ahd->features & AHD_MULTI_TID) == 0) |
9551 | panic("ahd_update_scsiid called on non-multitid unit\n" ); |
9552 | |
9553 | /* |
9554 | * Since we will rely on the TARGID mask |
9555 | * for selection enables, ensure that OID |
9556 | * in SCSIID is not set to some other ID |
9557 | * that we don't want to allow selections on. |
9558 | */ |
9559 | if ((ahd->features & AHD_ULTRA2) != 0) |
9560 | scsiid = ahd_inb(ahd, SCSIID_ULTRA2); |
9561 | else |
9562 | scsiid = ahd_inb(ahd, SCSIID); |
9563 | scsiid_mask = 0x1 << (scsiid & OID); |
9564 | if ((targid_mask & scsiid_mask) == 0) { |
9565 | u_int our_id; |
9566 | |
9567 | /* ffs counts from 1 */ |
9568 | our_id = ffs(targid_mask); |
9569 | if (our_id == 0) |
9570 | our_id = ahd->our_id; |
9571 | else |
9572 | our_id--; |
9573 | scsiid &= TID; |
9574 | scsiid |= our_id; |
9575 | } |
9576 | if ((ahd->features & AHD_ULTRA2) != 0) |
9577 | ahd_outb(ahd, SCSIID_ULTRA2, scsiid); |
9578 | else |
9579 | ahd_outb(ahd, SCSIID, scsiid); |
9580 | #endif |
9581 | } |
9582 | |
9583 | #ifdef AHD_TARGET_MODE |
9584 | void |
9585 | ahd_run_tqinfifo(struct ahd_softc *ahd, int paused) |
9586 | { |
9587 | struct target_cmd *cmd; |
9588 | |
9589 | ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD); |
9590 | while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) { |
9591 | |
9592 | /* |
9593 | * Only advance through the queue if we |
9594 | * have the resources to process the command. |
9595 | */ |
9596 | if (ahd_handle_target_cmd(ahd, cmd) != 0) |
9597 | break; |
9598 | |
9599 | cmd->cmd_valid = 0; |
9600 | ahd_dmamap_sync(ahd, ahd->parent_dmat /*shared_data_dmat*/, |
9601 | ahd->shared_data_map.dmamap, |
9602 | ahd_targetcmd_offset(ahd, ahd->tqinfifonext), |
9603 | sizeof(struct target_cmd), |
9604 | BUS_DMASYNC_PREREAD); |
9605 | ahd->tqinfifonext++; |
9606 | |
9607 | /* |
9608 | * Lazily update our position in the target mode incoming |
9609 | * command queue as seen by the sequencer. |
9610 | */ |
9611 | if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { |
9612 | u_int hs_mailbox; |
9613 | |
9614 | hs_mailbox = ahd_inb(ahd, HS_MAILBOX); |
9615 | hs_mailbox &= ~HOST_TQINPOS; |
9616 | hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS; |
9617 | ahd_outb(ahd, HS_MAILBOX, hs_mailbox); |
9618 | } |
9619 | } |
9620 | } |
9621 | #endif |
9622 | |
9623 | static int |
9624 | ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd) |
9625 | { |
9626 | struct ahd_tmode_tstate *tstate; |
9627 | struct ahd_tmode_lstate *lstate; |
9628 | struct ccb_accept_tio *atio; |
9629 | uint8_t *byte; |
9630 | int initiator; |
9631 | int target; |
9632 | int lun; |
9633 | |
9634 | initiator = SCSIID_TARGET(ahd, cmd->scsiid); |
9635 | target = SCSIID_OUR_ID(cmd->scsiid); |
9636 | lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); |
9637 | |
9638 | byte = cmd->bytes; |
9639 | tstate = ahd->enabled_targets[target]; |
9640 | lstate = NULL; |
9641 | if (tstate != NULL) |
9642 | lstate = tstate->enabled_luns[lun]; |
9643 | |
9644 | /* |
9645 | * Commands for disabled luns go to the black hole driver. |
9646 | */ |
9647 | if (lstate == NULL) |
9648 | lstate = ahd->black_hole; |
9649 | |
9650 | atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); |
9651 | if (atio == NULL) { |
9652 | ahd->flags |= AHD_TQINFIFO_BLOCKED; |
9653 | /* |
9654 | * Wait for more ATIOs from the peripheral driver for this lun. |
9655 | */ |
9656 | return (1); |
9657 | } else |
9658 | ahd->flags &= ~AHD_TQINFIFO_BLOCKED; |
9659 | #ifdef AHD_DEBUG |
9660 | if ((ahd_debug & AHD_SHOW_TQIN) != 0) |
9661 | printf("%s: incoming command from %d for %d:%d%s\n" , |
9662 | ahd_name(ahd), |
9663 | initiator, target, lun, |
9664 | lstate == ahd->black_hole ? "(Black Holed)" : "" ); |
9665 | #endif |
9666 | SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); |
9667 | |
9668 | if (lstate == ahd->black_hole) { |
9669 | /* Fill in the wildcards */ |
9670 | atio->ccb_h.target_id = target; |
9671 | atio->ccb_h.target_lun = lun; |
9672 | } |
9673 | |
9674 | /* |
9675 | * Package it up and send it off to |
9676 | * whomever has this lun enabled. |
9677 | */ |
9678 | atio->sense_len = 0; |
9679 | atio->init_id = initiator; |
9680 | if (byte[0] != 0xFF) { |
9681 | /* Tag was included */ |
9682 | atio->tag_action = *byte++; |
9683 | atio->tag_id = *byte++; |
9684 | atio->ccb_h.flags = CAM_TAG_ACTION_VALID; |
9685 | } else { |
9686 | atio->ccb_h.flags = 0; |
9687 | } |
9688 | byte++; |
9689 | |
9690 | /* Okay. Now determine the cdb size based on the command code */ |
9691 | switch (*byte >> CMD_GROUP_CODE_SHIFT) { |
9692 | case 0: |
9693 | atio->cdb_len = 6; |
9694 | break; |
9695 | case 1: |
9696 | case 2: |
9697 | atio->cdb_len = 10; |
9698 | break; |
9699 | case 4: |
9700 | atio->cdb_len = 16; |
9701 | break; |
9702 | case 5: |
9703 | atio->cdb_len = 12; |
9704 | break; |
9705 | case 3: |
9706 | default: |
9707 | /* Only copy the opcode. */ |
9708 | atio->cdb_len = 1; |
9709 | printf("Reserved or VU command code type encountered\n" ); |
9710 | break; |
9711 | } |
9712 | |
9713 | memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); |
9714 | |
9715 | atio->ccb_h.status |= CAM_CDB_RECVD; |
9716 | |
9717 | if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { |
9718 | /* |
9719 | * We weren't allowed to disconnect. |
9720 | * We're hanging on the bus until a |
9721 | * continue target I/O comes in response |
9722 | * to this accept tio. |
9723 | */ |
9724 | #ifdef AHD_DEBUG |
9725 | if ((ahd_debug & AHD_SHOW_TQIN) != 0) |
9726 | printf("Received Immediate Command %d:%d:%d - %p\n" , |
9727 | initiator, target, lun, ahd->pending_device); |
9728 | #endif |
9729 | ahd->pending_device = lstate; |
9730 | ahd_freeze_ccb((union ccb *)atio); |
9731 | atio->ccb_h.flags |= CAM_DIS_DISCONNECT; |
9732 | } |
9733 | xpt_done((union ccb*)atio); |
9734 | return (0); |
9735 | } |
9736 | |
9737 | #endif |
9738 | |
9739 | static int |
9740 | ahd_createdmamem(bus_dma_tag_t tag, int size, int flags, bus_dmamap_t *mapp, |
9741 | void **vaddr, bus_addr_t *baddr, bus_dma_segment_t *seg, int *nseg, |
9742 | const char *myname, const char *what) |
9743 | { |
9744 | int error, level = 0; |
9745 | |
9746 | if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, |
9747 | seg, 1, nseg, BUS_DMA_WAITOK)) != 0) { |
9748 | printf("%s: failed to allocate DMA mem for %s, error = %d\n" , |
9749 | myname, what, error); |
9750 | goto out; |
9751 | } |
9752 | level++; |
9753 | |
9754 | if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, |
9755 | BUS_DMA_WAITOK|BUS_DMA_COHERENT)) != 0) { |
9756 | printf("%s: failed to map DMA mem for %s, error = %d\n" , |
9757 | myname, what, error); |
9758 | goto out; |
9759 | } |
9760 | level++; |
9761 | |
9762 | if ((error = bus_dmamap_create(tag, size, 1, size, 0, |
9763 | BUS_DMA_WAITOK | flags, mapp)) != 0) { |
9764 | printf("%s: failed to create DMA map for %s, error = %d\n" , |
9765 | myname, what, error); |
9766 | goto out; |
9767 | } |
9768 | level++; |
9769 | |
9770 | |
9771 | if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, |
9772 | BUS_DMA_WAITOK)) != 0) { |
9773 | printf("%s: failed to load DMA map for %s, error = %d\n" , |
9774 | myname, what, error); |
9775 | goto out; |
9776 | } |
9777 | |
9778 | *baddr = (*mapp)->dm_segs[0].ds_addr; |
9779 | |
9780 | return 0; |
9781 | out: |
9782 | printf("ahd_createdmamem error (%d)\n" , level); |
9783 | switch (level) { |
9784 | case 3: |
9785 | bus_dmamap_destroy(tag, *mapp); |
9786 | /* FALLTHROUGH */ |
9787 | case 2: |
9788 | bus_dmamem_unmap(tag, *vaddr, size); |
9789 | /* FALLTHROUGH */ |
9790 | case 1: |
9791 | bus_dmamem_free(tag, seg, *nseg); |
9792 | break; |
9793 | default: |
9794 | break; |
9795 | } |
9796 | |
9797 | return error; |
9798 | } |
9799 | |
9800 | static void |
9801 | ahd_freedmamem(bus_dma_tag_t tag, int size, bus_dmamap_t map, void *vaddr, |
9802 | bus_dma_segment_t *seg, int nseg) |
9803 | { |
9804 | |
9805 | bus_dmamap_unload(tag, map); |
9806 | bus_dmamap_destroy(tag, map); |
9807 | bus_dmamem_unmap(tag, vaddr, size); |
9808 | bus_dmamem_free(tag, seg, nseg); |
9809 | } |
9810 | |