1 | /* $NetBSD: nouveau_engine_disp_nv84.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_disp_nv84.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $" ); |
29 | |
30 | #include <engine/software.h> |
31 | #include <engine/disp.h> |
32 | |
33 | #include <core/class.h> |
34 | |
35 | #include "nv50.h" |
36 | |
37 | /******************************************************************************* |
38 | * EVO master channel object |
39 | ******************************************************************************/ |
40 | |
41 | const struct nv50_disp_mthd_list |
42 | nv84_disp_mast_mthd_dac = { |
43 | .mthd = 0x0080, |
44 | .addr = 0x000008, |
45 | .data = { |
46 | { 0x0400, 0x610b58 }, |
47 | { 0x0404, 0x610bdc }, |
48 | { 0x0420, 0x610bc4 }, |
49 | {} |
50 | } |
51 | }; |
52 | |
53 | const struct nv50_disp_mthd_list |
54 | nv84_disp_mast_mthd_head = { |
55 | .mthd = 0x0400, |
56 | .addr = 0x000540, |
57 | .data = { |
58 | { 0x0800, 0x610ad8 }, |
59 | { 0x0804, 0x610ad0 }, |
60 | { 0x0808, 0x610a48 }, |
61 | { 0x080c, 0x610a78 }, |
62 | { 0x0810, 0x610ac0 }, |
63 | { 0x0814, 0x610af8 }, |
64 | { 0x0818, 0x610b00 }, |
65 | { 0x081c, 0x610ae8 }, |
66 | { 0x0820, 0x610af0 }, |
67 | { 0x0824, 0x610b08 }, |
68 | { 0x0828, 0x610b10 }, |
69 | { 0x082c, 0x610a68 }, |
70 | { 0x0830, 0x610a60 }, |
71 | { 0x0834, 0x000000 }, |
72 | { 0x0838, 0x610a40 }, |
73 | { 0x0840, 0x610a24 }, |
74 | { 0x0844, 0x610a2c }, |
75 | { 0x0848, 0x610aa8 }, |
76 | { 0x084c, 0x610ab0 }, |
77 | { 0x085c, 0x610c5c }, |
78 | { 0x0860, 0x610a84 }, |
79 | { 0x0864, 0x610a90 }, |
80 | { 0x0868, 0x610b18 }, |
81 | { 0x086c, 0x610b20 }, |
82 | { 0x0870, 0x610ac8 }, |
83 | { 0x0874, 0x610a38 }, |
84 | { 0x0878, 0x610c50 }, |
85 | { 0x0880, 0x610a58 }, |
86 | { 0x0884, 0x610a9c }, |
87 | { 0x089c, 0x610c68 }, |
88 | { 0x08a0, 0x610a70 }, |
89 | { 0x08a4, 0x610a50 }, |
90 | { 0x08a8, 0x610ae0 }, |
91 | { 0x08c0, 0x610b28 }, |
92 | { 0x08c4, 0x610b30 }, |
93 | { 0x08c8, 0x610b40 }, |
94 | { 0x08d4, 0x610b38 }, |
95 | { 0x08d8, 0x610b48 }, |
96 | { 0x08dc, 0x610b50 }, |
97 | { 0x0900, 0x610a18 }, |
98 | { 0x0904, 0x610ab8 }, |
99 | { 0x0910, 0x610c70 }, |
100 | { 0x0914, 0x610c78 }, |
101 | {} |
102 | } |
103 | }; |
104 | |
105 | const struct nv50_disp_mthd_chan |
106 | nv84_disp_mast_mthd_chan = { |
107 | .name = "Core" , |
108 | .addr = 0x000000, |
109 | .data = { |
110 | { "Global" , 1, &nv50_disp_mast_mthd_base }, |
111 | { "DAC" , 3, &nv84_disp_mast_mthd_dac }, |
112 | { "SOR" , 2, &nv50_disp_mast_mthd_sor }, |
113 | { "PIOR" , 3, &nv50_disp_mast_mthd_pior }, |
114 | { "HEAD" , 2, &nv84_disp_mast_mthd_head }, |
115 | {} |
116 | } |
117 | }; |
118 | |
119 | /******************************************************************************* |
120 | * EVO sync channel objects |
121 | ******************************************************************************/ |
122 | |
123 | static const struct nv50_disp_mthd_list |
124 | nv84_disp_sync_mthd_base = { |
125 | .mthd = 0x0000, |
126 | .addr = 0x000000, |
127 | .data = { |
128 | { 0x0080, 0x000000 }, |
129 | { 0x0084, 0x0008c4 }, |
130 | { 0x0088, 0x0008d0 }, |
131 | { 0x008c, 0x0008dc }, |
132 | { 0x0090, 0x0008e4 }, |
133 | { 0x0094, 0x610884 }, |
134 | { 0x00a0, 0x6108a0 }, |
135 | { 0x00a4, 0x610878 }, |
136 | { 0x00c0, 0x61086c }, |
137 | { 0x00c4, 0x610800 }, |
138 | { 0x00c8, 0x61080c }, |
139 | { 0x00cc, 0x610818 }, |
140 | { 0x00e0, 0x610858 }, |
141 | { 0x00e4, 0x610860 }, |
142 | { 0x00e8, 0x6108ac }, |
143 | { 0x00ec, 0x6108b4 }, |
144 | { 0x00fc, 0x610824 }, |
145 | { 0x0100, 0x610894 }, |
146 | { 0x0104, 0x61082c }, |
147 | { 0x0110, 0x6108bc }, |
148 | { 0x0114, 0x61088c }, |
149 | {} |
150 | } |
151 | }; |
152 | |
153 | const struct nv50_disp_mthd_chan |
154 | nv84_disp_sync_mthd_chan = { |
155 | .name = "Base" , |
156 | .addr = 0x000540, |
157 | .data = { |
158 | { "Global" , 1, &nv84_disp_sync_mthd_base }, |
159 | { "Image" , 2, &nv50_disp_sync_mthd_image }, |
160 | {} |
161 | } |
162 | }; |
163 | |
164 | /******************************************************************************* |
165 | * EVO overlay channel objects |
166 | ******************************************************************************/ |
167 | |
168 | static const struct nv50_disp_mthd_list |
169 | nv84_disp_ovly_mthd_base = { |
170 | .mthd = 0x0000, |
171 | .addr = 0x000000, |
172 | .data = { |
173 | { 0x0080, 0x000000 }, |
174 | { 0x0084, 0x6109a0 }, |
175 | { 0x0088, 0x6109c0 }, |
176 | { 0x008c, 0x6109c8 }, |
177 | { 0x0090, 0x6109b4 }, |
178 | { 0x0094, 0x610970 }, |
179 | { 0x00a0, 0x610998 }, |
180 | { 0x00a4, 0x610964 }, |
181 | { 0x00c0, 0x610958 }, |
182 | { 0x00e0, 0x6109a8 }, |
183 | { 0x00e4, 0x6109d0 }, |
184 | { 0x00e8, 0x6109d8 }, |
185 | { 0x0100, 0x61094c }, |
186 | { 0x0104, 0x610984 }, |
187 | { 0x0108, 0x61098c }, |
188 | { 0x0800, 0x6109f8 }, |
189 | { 0x0808, 0x610a08 }, |
190 | { 0x080c, 0x610a10 }, |
191 | { 0x0810, 0x610a00 }, |
192 | {} |
193 | } |
194 | }; |
195 | |
196 | const struct nv50_disp_mthd_chan |
197 | nv84_disp_ovly_mthd_chan = { |
198 | .name = "Overlay" , |
199 | .addr = 0x000540, |
200 | .data = { |
201 | { "Global" , 1, &nv84_disp_ovly_mthd_base }, |
202 | {} |
203 | } |
204 | }; |
205 | |
206 | /******************************************************************************* |
207 | * Base display object |
208 | ******************************************************************************/ |
209 | |
210 | static struct nouveau_oclass |
211 | nv84_disp_sclass[] = { |
212 | { NV84_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, |
213 | { NV84_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs }, |
214 | { NV84_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs }, |
215 | { NV84_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs }, |
216 | { NV84_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs }, |
217 | {} |
218 | }; |
219 | |
220 | struct nouveau_omthds |
221 | nv84_disp_base_omthds[] = { |
222 | { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos }, |
223 | { SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd }, |
224 | { SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd }, |
225 | { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd }, |
226 | { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd }, |
227 | { DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd }, |
228 | { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, |
229 | { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, |
230 | { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd }, |
231 | {}, |
232 | }; |
233 | |
234 | static struct nouveau_oclass |
235 | nv84_disp_base_oclass[] = { |
236 | { NV84_DISP_CLASS, &nv50_disp_base_ofuncs, nv84_disp_base_omthds }, |
237 | {} |
238 | }; |
239 | |
240 | /******************************************************************************* |
241 | * Display engine implementation |
242 | ******************************************************************************/ |
243 | |
244 | static int |
245 | nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
246 | struct nouveau_oclass *oclass, void *data, u32 size, |
247 | struct nouveau_object **pobject) |
248 | { |
249 | struct nv50_disp_priv *priv; |
250 | int ret; |
251 | |
252 | ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP" , |
253 | "display" , &priv); |
254 | *pobject = nv_object(priv); |
255 | if (ret) |
256 | return ret; |
257 | |
258 | nv_engine(priv)->sclass = nv84_disp_base_oclass; |
259 | nv_engine(priv)->cclass = &nv50_disp_cclass; |
260 | nv_subdev(priv)->intr = nv50_disp_intr; |
261 | INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); |
262 | priv->sclass = nv84_disp_sclass; |
263 | priv->head.nr = 2; |
264 | priv->dac.nr = 3; |
265 | priv->sor.nr = 2; |
266 | priv->pior.nr = 3; |
267 | priv->dac.power = nv50_dac_power; |
268 | priv->dac.sense = nv50_dac_sense; |
269 | priv->sor.power = nv50_sor_power; |
270 | priv->sor.hdmi = nv84_hdmi_ctrl; |
271 | priv->pior.power = nv50_pior_power; |
272 | priv->pior.dp = &nv50_pior_dp_func; |
273 | return 0; |
274 | } |
275 | |
276 | struct nouveau_oclass * |
277 | nv84_disp_oclass = &(struct nv50_disp_impl) { |
278 | .base.base.handle = NV_ENGINE(DISP, 0x82), |
279 | .base.base.ofuncs = &(struct nouveau_ofuncs) { |
280 | .ctor = nv84_disp_ctor, |
281 | .dtor = _nouveau_disp_dtor, |
282 | .init = _nouveau_disp_init, |
283 | .fini = _nouveau_disp_fini, |
284 | }, |
285 | .mthd.core = &nv84_disp_mast_mthd_chan, |
286 | .mthd.base = &nv84_disp_sync_mthd_chan, |
287 | .mthd.ovly = &nv84_disp_ovly_mthd_chan, |
288 | .mthd.prev = 0x000004, |
289 | }.base.base; |
290 | |