1 | /* $NetBSD: athn.c,v 1.13 2016/05/26 05:01:12 ozaki-r Exp $ */ |
2 | /* $OpenBSD: athn.c,v 1.83 2014/07/22 13:12:11 mpi Exp $ */ |
3 | |
4 | /*- |
5 | * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> |
6 | * Copyright (c) 2008-2010 Atheros Communications Inc. |
7 | * |
8 | * Permission to use, copy, modify, and/or distribute this software for any |
9 | * purpose with or without fee is hereby granted, provided that the above |
10 | * copyright notice and this permission notice appear in all copies. |
11 | * |
12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
19 | */ |
20 | |
21 | /* |
22 | * Driver for Atheros 802.11a/g/n chipsets. |
23 | */ |
24 | |
25 | #include <sys/cdefs.h> |
26 | __KERNEL_RCSID(0, "$NetBSD: athn.c,v 1.13 2016/05/26 05:01:12 ozaki-r Exp $" ); |
27 | |
28 | #ifndef _MODULE |
29 | #include "athn_usb.h" /* for NATHN_USB */ |
30 | #endif |
31 | |
32 | #include <sys/param.h> |
33 | #include <sys/sockio.h> |
34 | #include <sys/mbuf.h> |
35 | #include <sys/kernel.h> |
36 | #include <sys/socket.h> |
37 | #include <sys/systm.h> |
38 | #include <sys/malloc.h> |
39 | #include <sys/queue.h> |
40 | #include <sys/callout.h> |
41 | #include <sys/conf.h> |
42 | #include <sys/cpu.h> |
43 | #include <sys/device.h> |
44 | |
45 | #include <sys/bus.h> |
46 | #include <sys/endian.h> |
47 | #include <sys/intr.h> |
48 | |
49 | #include <net/bpf.h> |
50 | #include <net/if.h> |
51 | #include <net/if_arp.h> |
52 | #include <net/if_dl.h> |
53 | #include <net/if_ether.h> |
54 | #include <net/if_media.h> |
55 | #include <net/if_types.h> |
56 | |
57 | #include <netinet/in.h> |
58 | #include <netinet/in_systm.h> |
59 | #include <netinet/in_var.h> |
60 | #include <netinet/ip.h> |
61 | |
62 | #include <net80211/ieee80211_var.h> |
63 | #include <net80211/ieee80211_amrr.h> |
64 | #include <net80211/ieee80211_radiotap.h> |
65 | |
66 | #include <dev/ic/athnreg.h> |
67 | #include <dev/ic/athnvar.h> |
68 | #include <dev/ic/arn5008.h> |
69 | #include <dev/ic/arn5416.h> |
70 | #include <dev/ic/arn9003.h> |
71 | #include <dev/ic/arn9280.h> |
72 | #include <dev/ic/arn9285.h> |
73 | #include <dev/ic/arn9287.h> |
74 | #include <dev/ic/arn9380.h> |
75 | |
76 | #define Static static |
77 | |
78 | #define IS_UP_AND_RUNNING(ifp) \ |
79 | (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) |
80 | |
81 | #ifdef ATHN_DEBUG |
82 | int athn_debug = 0; |
83 | #endif |
84 | |
85 | Static int athn_clock_rate(struct athn_softc *); |
86 | Static const char * |
87 | athn_get_mac_name(struct athn_softc *); |
88 | Static const char * |
89 | athn_get_rf_name(struct athn_softc *); |
90 | Static int athn_init(struct ifnet *); |
91 | Static int athn_init_calib(struct athn_softc *, |
92 | struct ieee80211_channel *, struct ieee80211_channel *); |
93 | Static int athn_ioctl(struct ifnet *, u_long, void *); |
94 | Static int athn_media_change(struct ifnet *); |
95 | Static int athn_newstate(struct ieee80211com *, enum ieee80211_state, |
96 | int); |
97 | Static struct ieee80211_node * |
98 | athn_node_alloc(struct ieee80211_node_table *); |
99 | Static int athn_reset_power_on(struct athn_softc *); |
100 | Static int athn_stop_rx_dma(struct athn_softc *); |
101 | Static int athn_switch_chan(struct athn_softc *, |
102 | struct ieee80211_channel *, struct ieee80211_channel *); |
103 | Static void athn_calib_to(void *); |
104 | Static void athn_disable_interrupts(struct athn_softc *); |
105 | Static void athn_enable_interrupts(struct athn_softc *); |
106 | Static void athn_get_chanlist(struct athn_softc *); |
107 | Static void athn_get_chipid(struct athn_softc *); |
108 | Static void athn_init_dma(struct athn_softc *); |
109 | Static void athn_init_qos(struct athn_softc *); |
110 | Static void athn_init_tx_queues(struct athn_softc *); |
111 | Static void athn_iter_func(void *, struct ieee80211_node *); |
112 | Static void athn_newassoc(struct ieee80211_node *, int); |
113 | Static void athn_next_scan(void *); |
114 | Static void athn_pmf_wlan_off(device_t self); |
115 | Static void athn_radiotap_attach(struct athn_softc *); |
116 | Static void athn_start(struct ifnet *); |
117 | Static void athn_tx_reclaim(struct athn_softc *, int); |
118 | Static void athn_watchdog(struct ifnet *); |
119 | Static void athn_write_serdes(struct athn_softc *, |
120 | const struct athn_serdes *); |
121 | |
122 | #ifdef ATHN_BT_COEXISTENCE |
123 | Static void athn_btcoex_disable(struct athn_softc *); |
124 | Static void athn_btcoex_enable(struct athn_softc *); |
125 | #endif |
126 | |
127 | #ifdef unused |
128 | Static int32_t athn_ani_get_rssi(struct athn_softc *); |
129 | Static int athn_rx_abort(struct athn_softc *); |
130 | #endif |
131 | |
132 | #ifdef notyet |
133 | Static void athn_ani_cck_err_trigger(struct athn_softc *); |
134 | Static void athn_ani_lower_immunity(struct athn_softc *); |
135 | Static void athn_ani_monitor(struct athn_softc *); |
136 | Static void athn_ani_ofdm_err_trigger(struct athn_softc *); |
137 | Static void athn_ani_restart(struct athn_softc *); |
138 | Static void athn_set_multi(struct athn_softc *); |
139 | #endif /* notyet */ |
140 | |
141 | PUBLIC int |
142 | athn_attach(struct athn_softc *sc) |
143 | { |
144 | struct ieee80211com *ic = &sc->sc_ic; |
145 | struct ifnet *ifp = &sc->sc_if; |
146 | size_t max_nnodes; |
147 | int error; |
148 | |
149 | /* Read hardware revision. */ |
150 | athn_get_chipid(sc); |
151 | |
152 | if ((error = athn_reset_power_on(sc)) != 0) { |
153 | aprint_error_dev(sc->sc_dev, "could not reset chip\n" ); |
154 | return error; |
155 | } |
156 | |
157 | if ((error = athn_set_power_awake(sc)) != 0) { |
158 | aprint_error_dev(sc->sc_dev, "could not wakeup chip\n" ); |
159 | return error; |
160 | } |
161 | |
162 | if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) |
163 | error = ar5416_attach(sc); |
164 | else if (AR_SREV_9280(sc)) |
165 | error = ar9280_attach(sc); |
166 | else if (AR_SREV_9285(sc)) |
167 | error = ar9285_attach(sc); |
168 | #if NATHN_USB > 0 |
169 | else if (AR_SREV_9271(sc)) |
170 | error = ar9285_attach(sc); |
171 | #endif |
172 | else if (AR_SREV_9287(sc)) |
173 | error = ar9287_attach(sc); |
174 | else if (AR_SREV_9380(sc) || AR_SREV_9485(sc)) |
175 | error = ar9380_attach(sc); |
176 | else |
177 | error = ENOTSUP; |
178 | if (error != 0) { |
179 | aprint_error_dev(sc->sc_dev, "could not attach chip\n" ); |
180 | return error; |
181 | } |
182 | |
183 | pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); |
184 | pmf_event_register(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, |
185 | false); |
186 | |
187 | /* We can put the chip in sleep state now. */ |
188 | athn_set_power_sleep(sc); |
189 | |
190 | if (!(sc->sc_flags & ATHN_FLAG_USB)) { |
191 | error = sc->sc_ops.dma_alloc(sc); |
192 | if (error != 0) { |
193 | aprint_error_dev(sc->sc_dev, |
194 | "could not allocate DMA resources\n" ); |
195 | return error; |
196 | } |
197 | /* Steal one Tx buffer for beacons. */ |
198 | sc->sc_bcnbuf = SIMPLEQ_FIRST(&sc->sc_txbufs); |
199 | SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); |
200 | } |
201 | |
202 | if (sc->sc_flags & ATHN_FLAG_RFSILENT) { |
203 | DPRINTFN(DBG_INIT, sc, |
204 | "found RF switch connected to GPIO pin %d\n" , |
205 | sc->sc_rfsilent_pin); |
206 | } |
207 | DPRINTFN(DBG_INIT, sc, "%zd key cache entries\n" , sc->sc_kc_entries); |
208 | |
209 | /* |
210 | * In HostAP mode, the number of STAs that we can handle is |
211 | * limited by the number of entries in the HW key cache. |
212 | * TKIP keys consume 2 entries in the cache. |
213 | */ |
214 | KASSERT(sc->sc_kc_entries / 2 > IEEE80211_WEP_NKID); |
215 | max_nnodes = (sc->sc_kc_entries / 2) - IEEE80211_WEP_NKID; |
216 | if (sc->sc_max_aid != 0) /* we have an override */ |
217 | ic->ic_max_aid = sc->sc_max_aid; |
218 | if (ic->ic_max_aid > max_nnodes) |
219 | ic->ic_max_aid = max_nnodes; |
220 | |
221 | DPRINTFN(DBG_INIT, sc, "using %s loop power control\n" , |
222 | (sc->sc_flags & ATHN_FLAG_OLPC) ? "open" : "closed" ); |
223 | DPRINTFN(DBG_INIT, sc, "txchainmask=0x%x rxchainmask=0x%x\n" , |
224 | sc->sc_txchainmask, sc->sc_rxchainmask); |
225 | |
226 | /* Count the number of bits set (in lowest 3 bits). */ |
227 | sc->sc_ntxchains = |
228 | ((sc->sc_txchainmask >> 2) & 1) + |
229 | ((sc->sc_txchainmask >> 1) & 1) + |
230 | ((sc->sc_txchainmask >> 0) & 1); |
231 | sc->sc_nrxchains = |
232 | ((sc->sc_rxchainmask >> 2) & 1) + |
233 | ((sc->sc_rxchainmask >> 1) & 1) + |
234 | ((sc->sc_rxchainmask >> 0) & 1); |
235 | |
236 | if (AR_SINGLE_CHIP(sc)) { |
237 | aprint_normal(": Atheros %s\n" , athn_get_mac_name(sc)); |
238 | aprint_verbose_dev(sc->sc_dev, |
239 | "rev %d (%dT%dR), ROM rev %d, address %s\n" , |
240 | sc->sc_mac_rev, |
241 | sc->sc_ntxchains, sc->sc_nrxchains, sc->sc_eep_rev, |
242 | ether_sprintf(ic->ic_myaddr)); |
243 | } |
244 | else { |
245 | aprint_normal(": Atheros %s, RF %s\n" , athn_get_mac_name(sc), |
246 | athn_get_rf_name(sc)); |
247 | aprint_verbose_dev(sc->sc_dev, |
248 | "rev %d (%dT%dR), ROM rev %d, address %s\n" , |
249 | sc->sc_mac_rev, |
250 | sc->sc_ntxchains, sc->sc_nrxchains, |
251 | sc->sc_eep_rev, ether_sprintf(ic->ic_myaddr)); |
252 | } |
253 | |
254 | callout_init(&sc->sc_scan_to, 0); |
255 | callout_setfunc(&sc->sc_scan_to, athn_next_scan, sc); |
256 | callout_init(&sc->sc_calib_to, 0); |
257 | callout_setfunc(&sc->sc_calib_to, athn_calib_to, sc); |
258 | |
259 | sc->sc_amrr.amrr_min_success_threshold = 1; |
260 | sc->sc_amrr.amrr_max_success_threshold = 15; |
261 | |
262 | ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ |
263 | ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ |
264 | ic->ic_state = IEEE80211_S_INIT; |
265 | |
266 | /* Set device capabilities. */ |
267 | ic->ic_caps = |
268 | IEEE80211_C_WPA | /* 802.11i */ |
269 | #ifndef IEEE80211_STA_ONLY |
270 | IEEE80211_C_HOSTAP | /* Host AP mode supported. */ |
271 | // XXX? IEEE80211_C_APPMGT | /* Host AP power saving supported. */ |
272 | #endif |
273 | IEEE80211_C_MONITOR | /* Monitor mode supported. */ |
274 | IEEE80211_C_SHSLOT | /* Short slot time supported. */ |
275 | IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ |
276 | IEEE80211_C_PMGT; /* Power saving supported. */ |
277 | |
278 | #ifndef IEEE80211_NO_HT |
279 | if (sc->sc_flags & ATHN_FLAG_11N) { |
280 | int i, ntxstreams, nrxstreams; |
281 | |
282 | /* Set HT capabilities. */ |
283 | ic->ic_htcaps = |
284 | IEEE80211_HTCAP_SMPS_DIS | |
285 | IEEE80211_HTCAP_CBW20_40 | |
286 | IEEE80211_HTCAP_SGI40 | |
287 | IEEE80211_HTCAP_DSSSCCK40; |
288 | if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc)) |
289 | ic->ic_htcaps |= IEEE80211_HTCAP_SGI20; |
290 | if (AR_SREV_9380_10_OR_LATER(sc)) |
291 | ic->ic_htcaps |= IEEE80211_HTCAP_LDPC; |
292 | if (AR_SREV_9280_10_OR_LATER(sc)) { |
293 | ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; |
294 | ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT; |
295 | } |
296 | ntxstreams = sc->sc_ntxchains; |
297 | nrxstreams = sc->sc_nrxchains; |
298 | if (!AR_SREV_9380_10_OR_LATER(sc)) { |
299 | ntxstreams = MIN(ntxstreams, 2); |
300 | nrxstreams = MIN(nrxstreams, 2); |
301 | } |
302 | /* Set supported HT rates. */ |
303 | for (i = 0; i < nrxstreams; i++) |
304 | ic->ic_sup_mcs[i] = 0xff; |
305 | /* Set the "Tx MCS Set Defined" bit. */ |
306 | ic->ic_sup_mcs[12] |= 0x01; |
307 | if (ntxstreams != nrxstreams) { |
308 | /* Set "Tx Rx MCS Set Not Equal" bit. */ |
309 | ic->ic_sup_mcs[12] |= 0x02; |
310 | ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2; |
311 | } |
312 | } |
313 | #endif |
314 | |
315 | /* Set supported rates. */ |
316 | if (sc->sc_flags & ATHN_FLAG_11G) { |
317 | ic->ic_sup_rates[IEEE80211_MODE_11B] = |
318 | ieee80211_std_rateset_11b; |
319 | ic->ic_sup_rates[IEEE80211_MODE_11G] = |
320 | ieee80211_std_rateset_11g; |
321 | } |
322 | if (sc->sc_flags & ATHN_FLAG_11A) { |
323 | ic->ic_sup_rates[IEEE80211_MODE_11A] = |
324 | ieee80211_std_rateset_11a; |
325 | } |
326 | |
327 | /* Get the list of authorized/supported channels. */ |
328 | athn_get_chanlist(sc); |
329 | |
330 | ifp->if_softc = sc; |
331 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; |
332 | ifp->if_init = athn_init; |
333 | ifp->if_ioctl = athn_ioctl; |
334 | ifp->if_start = athn_start; |
335 | ifp->if_watchdog = athn_watchdog; |
336 | IFQ_SET_READY(&ifp->if_snd); |
337 | memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); |
338 | |
339 | if_attach(ifp); |
340 | ieee80211_ifattach(ic); |
341 | |
342 | ic->ic_node_alloc = athn_node_alloc; |
343 | ic->ic_newassoc = athn_newassoc; |
344 | if (ic->ic_updateslot == NULL) |
345 | ic->ic_updateslot = athn_updateslot; |
346 | #ifdef notyet_edca |
347 | ic->ic_updateedca = athn_updateedca; |
348 | #endif |
349 | #ifdef notyet |
350 | ic->ic_set_key = athn_set_key; |
351 | ic->ic_delete_key = athn_delete_key; |
352 | #endif |
353 | |
354 | /* Override 802.11 state transition machine. */ |
355 | sc->sc_newstate = ic->ic_newstate; |
356 | ic->ic_newstate = athn_newstate; |
357 | |
358 | if (sc->sc_media_change == NULL) |
359 | sc->sc_media_change = athn_media_change; |
360 | ieee80211_media_init(ic, sc->sc_media_change, ieee80211_media_status); |
361 | |
362 | athn_radiotap_attach(sc); |
363 | return 0; |
364 | } |
365 | |
366 | PUBLIC void |
367 | athn_detach(struct athn_softc *sc) |
368 | { |
369 | struct ifnet *ifp = &sc->sc_if; |
370 | int qid; |
371 | |
372 | callout_halt(&sc->sc_scan_to, NULL); |
373 | callout_halt(&sc->sc_calib_to, NULL); |
374 | |
375 | if (!(sc->sc_flags & ATHN_FLAG_USB)) { |
376 | for (qid = 0; qid < ATHN_QID_COUNT; qid++) |
377 | athn_tx_reclaim(sc, qid); |
378 | |
379 | /* Free Tx/Rx DMA resources. */ |
380 | sc->sc_ops.dma_free(sc); |
381 | } |
382 | /* Free ROM copy. */ |
383 | if (sc->sc_eep != NULL) { |
384 | free(sc->sc_eep, M_DEVBUF); |
385 | sc->sc_eep = NULL; |
386 | } |
387 | |
388 | bpf_detach(ifp); |
389 | ieee80211_ifdetach(&sc->sc_ic); |
390 | if_detach(ifp); |
391 | |
392 | callout_destroy(&sc->sc_scan_to); |
393 | callout_destroy(&sc->sc_calib_to); |
394 | } |
395 | |
396 | /* |
397 | * Attach the interface to 802.11 radiotap. |
398 | */ |
399 | Static void |
400 | athn_radiotap_attach(struct athn_softc *sc) |
401 | { |
402 | |
403 | bpf_attach2(&sc->sc_if, DLT_IEEE802_11_RADIO, |
404 | sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, |
405 | &sc->sc_drvbpf); |
406 | |
407 | sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); |
408 | sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); |
409 | sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); |
410 | |
411 | sc->sc_txtap_len = sizeof(sc->sc_txtapu); |
412 | sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); |
413 | sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); |
414 | } |
415 | |
416 | Static void |
417 | athn_get_chanlist(struct athn_softc *sc) |
418 | { |
419 | struct ieee80211com *ic = &sc->sc_ic; |
420 | uint8_t chan; |
421 | size_t i; |
422 | |
423 | if (sc->sc_flags & ATHN_FLAG_11G) { |
424 | for (i = 1; i <= 14; i++) { |
425 | chan = i; |
426 | ic->ic_channels[chan].ic_freq = |
427 | ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); |
428 | ic->ic_channels[chan].ic_flags = |
429 | IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | |
430 | IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; |
431 | } |
432 | } |
433 | if (sc->sc_flags & ATHN_FLAG_11A) { |
434 | for (i = 0; i < __arraycount(athn_5ghz_chans); i++) { |
435 | chan = athn_5ghz_chans[i]; |
436 | ic->ic_channels[chan].ic_freq = |
437 | ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); |
438 | ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; |
439 | } |
440 | } |
441 | } |
442 | |
443 | PUBLIC void |
444 | athn_rx_start(struct athn_softc *sc) |
445 | { |
446 | struct ieee80211com *ic = &sc->sc_ic; |
447 | uint32_t rfilt; |
448 | |
449 | /* Setup Rx DMA descriptors. */ |
450 | sc->sc_ops.rx_enable(sc); |
451 | |
452 | /* Set Rx filter. */ |
453 | rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST; |
454 | #ifndef IEEE80211_NO_HT |
455 | /* Want Compressed Block Ack Requests. */ |
456 | rfilt |= AR_RX_FILTER_COMPR_BAR; |
457 | #endif |
458 | rfilt |= AR_RX_FILTER_BEACON; |
459 | if (ic->ic_opmode != IEEE80211_M_STA) { |
460 | rfilt |= AR_RX_FILTER_PROBEREQ; |
461 | if (ic->ic_opmode == IEEE80211_M_MONITOR) |
462 | rfilt |= AR_RX_FILTER_PROM; |
463 | #ifndef IEEE80211_STA_ONLY |
464 | if (AR_SREV_9280_10_OR_LATER(sc) && |
465 | ic->ic_opmode == IEEE80211_M_HOSTAP) |
466 | rfilt |= AR_RX_FILTER_PSPOLL; |
467 | #endif |
468 | } |
469 | athn_set_rxfilter(sc, rfilt); |
470 | |
471 | /* Set BSSID mask. */ |
472 | AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); |
473 | AR_WRITE(sc, AR_BSSMSKU, 0xffff); |
474 | |
475 | athn_set_opmode(sc); |
476 | |
477 | /* Set multicast filter. */ |
478 | AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); |
479 | AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); |
480 | |
481 | AR_WRITE(sc, AR_FILT_OFDM, 0); |
482 | AR_WRITE(sc, AR_FILT_CCK, 0); |
483 | AR_WRITE(sc, AR_MIBC, 0); |
484 | AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); |
485 | AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); |
486 | |
487 | /* XXX ANI. */ |
488 | AR_WRITE(sc, AR_PHY_ERR_1, 0); |
489 | AR_WRITE(sc, AR_PHY_ERR_2, 0); |
490 | |
491 | /* Disable HW crypto for now. */ |
492 | AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); |
493 | |
494 | /* Start PCU Rx. */ |
495 | AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); |
496 | AR_WRITE_BARRIER(sc); |
497 | } |
498 | |
499 | PUBLIC void |
500 | athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) |
501 | { |
502 | |
503 | AR_WRITE(sc, AR_RX_FILTER, rfilt); |
504 | #ifdef notyet |
505 | reg = AR_READ(sc, AR_PHY_ERR); |
506 | reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING | |
507 | AR_PHY_ERR_CCK_TIMING); |
508 | AR_WRITE(sc, AR_PHY_ERR, reg); |
509 | if (reg != 0) |
510 | AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); |
511 | else |
512 | AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); |
513 | #else |
514 | AR_WRITE(sc, AR_PHY_ERR, 0); |
515 | AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); |
516 | #endif |
517 | AR_WRITE_BARRIER(sc); |
518 | } |
519 | |
520 | PUBLIC int |
521 | athn_intr(void *xsc) |
522 | { |
523 | struct athn_softc *sc = xsc; |
524 | struct ifnet *ifp = &sc->sc_if; |
525 | |
526 | if (!IS_UP_AND_RUNNING(ifp)) |
527 | return 0; |
528 | |
529 | if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) |
530 | /* |
531 | * The hardware is not ready/present, don't touch anything. |
532 | * Note this can happen early on if the IRQ is shared. |
533 | */ |
534 | return 0; |
535 | |
536 | return sc->sc_ops.intr(sc); |
537 | } |
538 | |
539 | Static void |
540 | athn_get_chipid(struct athn_softc *sc) |
541 | { |
542 | uint32_t reg; |
543 | |
544 | reg = AR_READ(sc, AR_SREV); |
545 | if (MS(reg, AR_SREV_ID) == 0xff) { |
546 | sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2); |
547 | sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2); |
548 | if (!(reg & AR_SREV_TYPE2_HOST_MODE)) |
549 | sc->sc_flags |= ATHN_FLAG_PCIE; |
550 | } |
551 | else { |
552 | sc->sc_mac_ver = MS(reg, AR_SREV_VERSION); |
553 | sc->sc_mac_rev = MS(reg, AR_SREV_REVISION); |
554 | if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCIE) |
555 | sc->sc_flags |= ATHN_FLAG_PCIE; |
556 | } |
557 | } |
558 | |
559 | Static const char * |
560 | athn_get_mac_name(struct athn_softc *sc) |
561 | { |
562 | |
563 | switch (sc->sc_mac_ver) { |
564 | case AR_SREV_VERSION_5416_PCI: |
565 | return "AR5416" ; |
566 | case AR_SREV_VERSION_5416_PCIE: |
567 | return "AR5418" ; |
568 | case AR_SREV_VERSION_9160: |
569 | return "AR9160" ; |
570 | case AR_SREV_VERSION_9280: |
571 | return "AR9280" ; |
572 | case AR_SREV_VERSION_9285: |
573 | return "AR9285" ; |
574 | case AR_SREV_VERSION_9271: |
575 | return "AR9271" ; |
576 | case AR_SREV_VERSION_9287: |
577 | return "AR9287" ; |
578 | case AR_SREV_VERSION_9380: |
579 | return "AR9380" ; |
580 | case AR_SREV_VERSION_9485: |
581 | return "AR9485" ; |
582 | default: |
583 | return "unknown" ; |
584 | } |
585 | } |
586 | |
587 | /* |
588 | * Return RF chip name (not for single-chip solutions). |
589 | */ |
590 | Static const char * |
591 | athn_get_rf_name(struct athn_softc *sc) |
592 | { |
593 | |
594 | KASSERT(!AR_SINGLE_CHIP(sc)); |
595 | |
596 | switch (sc->sc_rf_rev) { |
597 | case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */ |
598 | return "AR5133" ; |
599 | case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */ |
600 | return "AR2133" ; |
601 | case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */ |
602 | return "AR5122" ; |
603 | case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */ |
604 | return "AR2122" ; |
605 | default: |
606 | return "unknown" ; |
607 | } |
608 | } |
609 | |
610 | PUBLIC int |
611 | athn_reset_power_on(struct athn_softc *sc) |
612 | { |
613 | int ntries; |
614 | |
615 | /* Set force wake. */ |
616 | AR_WRITE(sc, AR_RTC_FORCE_WAKE, |
617 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); |
618 | |
619 | if (!AR_SREV_9380_10_OR_LATER(sc)) { |
620 | /* Make sure no DMA is active by doing an AHB reset. */ |
621 | AR_WRITE(sc, AR_RC, AR_RC_AHB); |
622 | } |
623 | /* RTC reset and clear. */ |
624 | AR_WRITE(sc, AR_RTC_RESET, 0); |
625 | AR_WRITE_BARRIER(sc); |
626 | DELAY(2); |
627 | if (!AR_SREV_9380_10_OR_LATER(sc)) |
628 | AR_WRITE(sc, AR_RC, 0); |
629 | AR_WRITE(sc, AR_RTC_RESET, 1); |
630 | |
631 | /* Poll until RTC is ON. */ |
632 | for (ntries = 0; ntries < 1000; ntries++) { |
633 | if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == |
634 | AR_RTC_STATUS_ON) |
635 | break; |
636 | DELAY(10); |
637 | } |
638 | if (ntries == 1000) { |
639 | DPRINTFN(DBG_INIT, sc, "RTC not waking up\n" ); |
640 | return ETIMEDOUT; |
641 | } |
642 | return athn_reset(sc, 0); |
643 | } |
644 | |
645 | PUBLIC int |
646 | athn_reset(struct athn_softc *sc, int cold_reset) |
647 | { |
648 | int ntries; |
649 | |
650 | /* Set force wake. */ |
651 | AR_WRITE(sc, AR_RTC_FORCE_WAKE, |
652 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); |
653 | |
654 | if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & |
655 | (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { |
656 | AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); |
657 | AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | |
658 | (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); |
659 | } |
660 | else if (!AR_SREV_9380_10_OR_LATER(sc)) |
661 | AR_WRITE(sc, AR_RC, AR_RC_AHB); |
662 | |
663 | AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | |
664 | (cold_reset ? AR_RTC_RC_MAC_COLD : 0)); |
665 | AR_WRITE_BARRIER(sc); |
666 | DELAY(50); |
667 | AR_WRITE(sc, AR_RTC_RC, 0); |
668 | for (ntries = 0; ntries < 1000; ntries++) { |
669 | if (!(AR_READ(sc, AR_RTC_RC) & |
670 | (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD))) |
671 | break; |
672 | DELAY(10); |
673 | } |
674 | if (ntries == 1000) { |
675 | DPRINTFN(DBG_INIT, sc, "RTC stuck in MAC reset\n" ); |
676 | return ETIMEDOUT; |
677 | } |
678 | AR_WRITE(sc, AR_RC, 0); |
679 | AR_WRITE_BARRIER(sc); |
680 | return 0; |
681 | } |
682 | |
683 | PUBLIC int |
684 | athn_set_power_awake(struct athn_softc *sc) |
685 | { |
686 | int ntries, error; |
687 | |
688 | /* Do a Power-On-Reset if shutdown. */ |
689 | if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == |
690 | AR_RTC_STATUS_SHUTDOWN) { |
691 | if ((error = athn_reset_power_on(sc)) != 0) |
692 | return error; |
693 | if (!AR_SREV_9380_10_OR_LATER(sc)) |
694 | athn_init_pll(sc, NULL); |
695 | } |
696 | AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); |
697 | AR_WRITE_BARRIER(sc); |
698 | DELAY(50); /* Give chip the chance to awake. */ |
699 | |
700 | /* Poll until RTC is ON. */ |
701 | for (ntries = 0; ntries < 4000; ntries++) { |
702 | if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == |
703 | AR_RTC_STATUS_ON) |
704 | break; |
705 | DELAY(50); |
706 | AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); |
707 | } |
708 | if (ntries == 4000) { |
709 | DPRINTFN(DBG_INIT, sc, "RTC not waking up\n" ); |
710 | return ETIMEDOUT; |
711 | } |
712 | |
713 | AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
714 | AR_WRITE_BARRIER(sc); |
715 | return 0; |
716 | } |
717 | |
718 | PUBLIC void |
719 | athn_set_power_sleep(struct athn_softc *sc) |
720 | { |
721 | |
722 | AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
723 | /* Allow the MAC to go to sleep. */ |
724 | AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); |
725 | if (!AR_SREV_9380_10_OR_LATER(sc)) |
726 | AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); |
727 | /* |
728 | * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode |
729 | * results in high power consumption on AR5416 chipsets. |
730 | */ |
731 | if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc)) |
732 | AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); |
733 | AR_WRITE_BARRIER(sc); |
734 | } |
735 | |
736 | PUBLIC void |
737 | athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) |
738 | { |
739 | uint32_t pll; |
740 | |
741 | if (AR_SREV_9380_10_OR_LATER(sc)) { |
742 | if (AR_SREV_9485(sc)) |
743 | AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666); |
744 | pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5); |
745 | pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); |
746 | } |
747 | else if (AR_SREV_9280_10_OR_LATER(sc)) { |
748 | pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); |
749 | if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) { |
750 | if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) |
751 | pll = 0x142c; |
752 | else if (AR_SREV_9280_20(sc)) |
753 | pll = 0x2850; |
754 | else |
755 | pll |= SM(AR_RTC_9160_PLL_DIV, 0x28); |
756 | } |
757 | else |
758 | pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); |
759 | } |
760 | else if (AR_SREV_9160_10_OR_LATER(sc)) { |
761 | pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); |
762 | if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) |
763 | pll |= SM(AR_RTC_9160_PLL_DIV, 0x50); |
764 | else |
765 | pll |= SM(AR_RTC_9160_PLL_DIV, 0x58); |
766 | } |
767 | else { |
768 | pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; |
769 | if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) |
770 | pll |= SM(AR_RTC_PLL_DIV, 0x0a); |
771 | else |
772 | pll |= SM(AR_RTC_PLL_DIV, 0x0b); |
773 | } |
774 | DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n" , pll); |
775 | AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); |
776 | if (AR_SREV_9271(sc)) { |
777 | /* Switch core clock to 117MHz. */ |
778 | AR_WRITE_BARRIER(sc); |
779 | DELAY(500); |
780 | AR_WRITE(sc, 0x50050, 0x304); |
781 | } |
782 | AR_WRITE_BARRIER(sc); |
783 | DELAY(100); |
784 | AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); |
785 | AR_WRITE_BARRIER(sc); |
786 | } |
787 | |
788 | Static void |
789 | athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes) |
790 | { |
791 | int i; |
792 | |
793 | /* Write sequence to Serializer/Deserializer. */ |
794 | for (i = 0; i < serdes->nvals; i++) |
795 | AR_WRITE(sc, serdes->regs[i], serdes->vals[i]); |
796 | AR_WRITE_BARRIER(sc); |
797 | } |
798 | |
799 | PUBLIC void |
800 | athn_config_pcie(struct athn_softc *sc) |
801 | { |
802 | |
803 | /* Disable PLL when in L0s as well as receiver clock when in L1. */ |
804 | athn_write_serdes(sc, sc->sc_serdes); |
805 | |
806 | DELAY(1000); |
807 | /* Allow forcing of PCIe core into L1 state. */ |
808 | AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
809 | |
810 | #ifndef ATHN_PCIE_WAEN |
811 | AR_WRITE(sc, AR_WA, sc->sc_workaround); |
812 | #else |
813 | AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); |
814 | #endif |
815 | AR_WRITE_BARRIER(sc); |
816 | } |
817 | |
818 | /* |
819 | * Serializer/Deserializer programming for non-PCIe devices. |
820 | */ |
821 | static const uint32_t ar_nonpcie_serdes_regs[] = { |
822 | AR_PCIE_SERDES, |
823 | AR_PCIE_SERDES, |
824 | AR_PCIE_SERDES, |
825 | AR_PCIE_SERDES, |
826 | AR_PCIE_SERDES, |
827 | AR_PCIE_SERDES, |
828 | AR_PCIE_SERDES, |
829 | AR_PCIE_SERDES, |
830 | AR_PCIE_SERDES, |
831 | AR_PCIE_SERDES2, |
832 | }; |
833 | |
834 | static const uint32_t ar_nonpcie_serdes_vals[] = { |
835 | 0x9248fc00, |
836 | 0x24924924, |
837 | 0x28000029, |
838 | 0x57160824, |
839 | 0x25980579, |
840 | 0x00000000, |
841 | 0x1aaabe40, |
842 | 0xbe105554, |
843 | 0x000e1007, |
844 | 0x00000000 |
845 | }; |
846 | |
847 | static const struct athn_serdes ar_nonpcie_serdes = { |
848 | __arraycount(ar_nonpcie_serdes_vals), |
849 | ar_nonpcie_serdes_regs, |
850 | ar_nonpcie_serdes_vals |
851 | }; |
852 | |
853 | PUBLIC void |
854 | athn_config_nonpcie(struct athn_softc *sc) |
855 | { |
856 | |
857 | athn_write_serdes(sc, &ar_nonpcie_serdes); |
858 | } |
859 | |
860 | PUBLIC int |
861 | athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, |
862 | struct ieee80211_channel *extchan) |
863 | { |
864 | struct athn_ops *ops = &sc->sc_ops; |
865 | int error, qid; |
866 | |
867 | /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ |
868 | for (qid = 0; qid < ATHN_QID_COUNT; qid++) |
869 | if (athn_tx_pending(sc, qid)) |
870 | return EBUSY; |
871 | |
872 | /* Request RF Bus grant. */ |
873 | if ((error = ops->rf_bus_request(sc)) != 0) |
874 | return error; |
875 | |
876 | ops->set_phy(sc, curchan, extchan); |
877 | |
878 | /* Change the synthesizer. */ |
879 | if ((error = ops->set_synth(sc, curchan, extchan)) != 0) |
880 | return error; |
881 | |
882 | sc->sc_curchan = curchan; |
883 | sc->sc_curchanext = extchan; |
884 | |
885 | /* Set transmit power values for new channel. */ |
886 | ops->set_txpower(sc, curchan, extchan); |
887 | |
888 | /* Release the RF Bus grant. */ |
889 | ops->rf_bus_release(sc); |
890 | |
891 | /* Write delta slope coeffs for modes where OFDM may be used. */ |
892 | if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) |
893 | ops->set_delta_slope(sc, curchan, extchan); |
894 | |
895 | ops->spur_mitigate(sc, curchan, extchan); |
896 | /* XXX Load noisefloor values and start calibration. */ |
897 | |
898 | return 0; |
899 | } |
900 | |
901 | Static int |
902 | athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, |
903 | struct ieee80211_channel *extchan) |
904 | { |
905 | int error, qid; |
906 | |
907 | /* Disable interrupts. */ |
908 | athn_disable_interrupts(sc); |
909 | |
910 | /* Stop all Tx queues. */ |
911 | for (qid = 0; qid < ATHN_QID_COUNT; qid++) |
912 | athn_stop_tx_dma(sc, qid); |
913 | for (qid = 0; qid < ATHN_QID_COUNT; qid++) |
914 | athn_tx_reclaim(sc, qid); |
915 | |
916 | /* Stop Rx. */ |
917 | AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); |
918 | AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); |
919 | AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); |
920 | AR_WRITE(sc, AR_FILT_OFDM, 0); |
921 | AR_WRITE(sc, AR_FILT_CCK, 0); |
922 | athn_set_rxfilter(sc, 0); |
923 | error = athn_stop_rx_dma(sc); |
924 | if (error != 0) |
925 | goto reset; |
926 | |
927 | #ifdef notyet |
928 | /* AR9280 needs a full reset. */ |
929 | if (AR_SREV_9280(sc)) |
930 | #endif |
931 | goto reset; |
932 | |
933 | /* If band or bandwidth changes, we need to do a full reset. */ |
934 | if (curchan->ic_flags != sc->sc_curchan->ic_flags || |
935 | ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) { |
936 | DPRINTFN(DBG_RF, sc, "channel band switch\n" ); |
937 | goto reset; |
938 | } |
939 | error = athn_set_power_awake(sc); |
940 | if (error != 0) |
941 | goto reset; |
942 | |
943 | error = athn_set_chan(sc, curchan, extchan); |
944 | if (error != 0) { |
945 | reset: /* Error found, try a full reset. */ |
946 | DPRINTFN(DBG_RF, sc, "needs a full reset\n" ); |
947 | error = athn_hw_reset(sc, curchan, extchan, 0); |
948 | if (error != 0) /* Hopeless case. */ |
949 | return error; |
950 | } |
951 | athn_rx_start(sc); |
952 | |
953 | /* Re-enable interrupts. */ |
954 | athn_enable_interrupts(sc); |
955 | return 0; |
956 | } |
957 | |
958 | PUBLIC void |
959 | athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) |
960 | { |
961 | #define COEFF_SCALE_SHIFT 24 |
962 | uint32_t exp, man; |
963 | |
964 | /* exponent = 14 - floor(log2(coeff)) */ |
965 | for (exp = 31; exp > 0; exp--) |
966 | if (coeff & (1 << exp)) |
967 | break; |
968 | exp = 14 - (exp - COEFF_SCALE_SHIFT); |
969 | |
970 | /* mantissa = floor(coeff * 2^exponent + 0.5) */ |
971 | man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); |
972 | |
973 | *mantissa = man >> (COEFF_SCALE_SHIFT - exp); |
974 | *exponent = exp - 16; |
975 | #undef COEFF_SCALE_SHIFT |
976 | } |
977 | |
978 | PUBLIC void |
979 | athn_reset_key(struct athn_softc *sc, int entry) |
980 | { |
981 | |
982 | /* |
983 | * NB: Key cache registers access special memory area that requires |
984 | * two 32-bit writes to actually update the values in the internal |
985 | * memory. Consequently, writes must be grouped by pair. |
986 | */ |
987 | AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); |
988 | AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); |
989 | |
990 | AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); |
991 | AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); |
992 | |
993 | AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); |
994 | AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); |
995 | |
996 | AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); |
997 | AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); |
998 | |
999 | AR_WRITE_BARRIER(sc); |
1000 | } |
1001 | |
1002 | #ifdef notyet |
1003 | Static int |
1004 | athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, |
1005 | struct ieee80211_key *k) |
1006 | { |
1007 | struct athn_softc *sc = ic->ic_ifp->if_softc; |
1008 | const uint8_t *txmic, *rxmic, *key, *addr; |
1009 | uintptr_t entry, micentry; |
1010 | uint32_t type, lo, hi; |
1011 | |
1012 | switch (k->k_cipher) { |
1013 | case IEEE80211_CIPHER_WEP40: |
1014 | type = AR_KEYTABLE_TYPE_40; |
1015 | break; |
1016 | case IEEE80211_CIPHER_WEP104: |
1017 | type = AR_KEYTABLE_TYPE_104; |
1018 | break; |
1019 | case IEEE80211_CIPHER_TKIP: |
1020 | type = AR_KEYTABLE_TYPE_TKIP; |
1021 | break; |
1022 | case IEEE80211_CIPHER_CCMP: |
1023 | type = AR_KEYTABLE_TYPE_CCM; |
1024 | break; |
1025 | default: |
1026 | /* Fallback to software crypto for other ciphers. */ |
1027 | return ieee80211_set_key(ic, ni, k); |
1028 | } |
1029 | |
1030 | if (!(k->k_flags & IEEE80211_KEY_GROUP)) |
1031 | entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd); |
1032 | else |
1033 | entry = k->k_id; |
1034 | k->k_priv = (void *)entry; |
1035 | |
1036 | /* NB: See note about key cache registers access above. */ |
1037 | key = k->k_key; |
1038 | if (type == AR_KEYTABLE_TYPE_TKIP) { |
1039 | #ifndef IEEE80211_STA_ONLY |
1040 | if (ic->ic_opmode == IEEE80211_M_HOSTAP) { |
1041 | txmic = &key[16]; |
1042 | rxmic = &key[24]; |
1043 | } |
1044 | else |
1045 | #endif |
1046 | { |
1047 | rxmic = &key[16]; |
1048 | txmic = &key[24]; |
1049 | } |
1050 | /* Tx+Rx MIC key is at entry + 64. */ |
1051 | micentry = entry + 64; |
1052 | AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0])); |
1053 | AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2])); |
1054 | |
1055 | AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4])); |
1056 | AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0])); |
1057 | |
1058 | AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4])); |
1059 | AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); |
1060 | } |
1061 | AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0])); |
1062 | AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4])); |
1063 | |
1064 | AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6])); |
1065 | AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10])); |
1066 | |
1067 | AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12])); |
1068 | AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); |
1069 | |
1070 | if (!(k->k_flags & IEEE80211_KEY_GROUP)) { |
1071 | addr = ni->ni_macaddr; |
1072 | lo = LE_READ_4(&addr[0]); |
1073 | hi = LE_READ_2(&addr[4]); |
1074 | lo = lo >> 1 | hi << 31; |
1075 | hi = hi >> 1; |
1076 | } |
1077 | else |
1078 | lo = hi = 0; |
1079 | AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); |
1080 | AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); |
1081 | AR_WRITE_BARRIER(sc); |
1082 | return 0; |
1083 | } |
1084 | |
1085 | Static void |
1086 | athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, |
1087 | struct ieee80211_key *k) |
1088 | { |
1089 | struct athn_softc *sc = ic->ic_ifp->if_softc; |
1090 | uintptr_t entry; |
1091 | |
1092 | switch (k->k_cipher) { |
1093 | case IEEE80211_CIPHER_WEP40: |
1094 | case IEEE80211_CIPHER_WEP104: |
1095 | case IEEE80211_CIPHER_CCMP: |
1096 | entry = (uintptr_t)k->k_priv; |
1097 | athn_reset_key(sc, entry); |
1098 | break; |
1099 | case IEEE80211_CIPHER_TKIP: |
1100 | entry = (uintptr_t)k->k_priv; |
1101 | athn_reset_key(sc, entry); |
1102 | athn_reset_key(sc, entry + 64); |
1103 | break; |
1104 | default: |
1105 | /* Fallback to software crypto for other ciphers. */ |
1106 | ieee80211_delete_key(ic, ni, k); |
1107 | } |
1108 | } |
1109 | #endif /* notyet */ |
1110 | |
1111 | PUBLIC void |
1112 | athn_led_init(struct athn_softc *sc) |
1113 | { |
1114 | struct athn_ops *ops = &sc->sc_ops; |
1115 | |
1116 | ops->gpio_config_output(sc, sc->sc_led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
1117 | /* LED off, active low. */ |
1118 | athn_set_led(sc, 0); |
1119 | } |
1120 | |
1121 | PUBLIC void |
1122 | athn_set_led(struct athn_softc *sc, int on) |
1123 | { |
1124 | struct athn_ops *ops = &sc->sc_ops; |
1125 | |
1126 | sc->sc_led_state = on; |
1127 | ops->gpio_write(sc, sc->sc_led_pin, !sc->sc_led_state); |
1128 | } |
1129 | |
1130 | #ifdef ATHN_BT_COEXISTENCE |
1131 | Static void |
1132 | athn_btcoex_init(struct athn_softc *sc) |
1133 | { |
1134 | struct athn_ops *ops = &sc->sc_ops; |
1135 | uint32_t reg; |
1136 | |
1137 | if (sc->sc_flags & ATHN_FLAG_BTCOEX2WIRE) { |
1138 | /* Connect bt_active to baseband. */ |
1139 | AR_CLRBITS(sc, sc->sc_gpio_input_en_off, |
1140 | AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | |
1141 | AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF); |
1142 | AR_SETBITS(sc, sc->sc_gpio_input_en_off, |
1143 | AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); |
1144 | |
1145 | reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); |
1146 | reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, |
1147 | AR_GPIO_BTACTIVE_PIN); |
1148 | AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); |
1149 | AR_WRITE_BARRIER(sc); |
1150 | |
1151 | ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); |
1152 | } |
1153 | else { /* 3-wire. */ |
1154 | AR_SETBITS(sc, sc->sc_gpio_input_en_off, |
1155 | AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | |
1156 | AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); |
1157 | |
1158 | reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); |
1159 | reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, |
1160 | AR_GPIO_BTACTIVE_PIN); |
1161 | reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY, |
1162 | AR_GPIO_BTPRIORITY_PIN); |
1163 | AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); |
1164 | AR_WRITE_BARRIER(sc); |
1165 | |
1166 | ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); |
1167 | ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); |
1168 | } |
1169 | } |
1170 | |
1171 | Static void |
1172 | athn_btcoex_enable(struct athn_softc *sc) |
1173 | { |
1174 | struct athn_ops *ops = &sc->sc_ops; |
1175 | uint32_t reg; |
1176 | |
1177 | if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { |
1178 | AR_WRITE(sc, AR_BT_COEX_MODE, |
1179 | SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) | |
1180 | SM(AR_BT_PRIORITY_TIME, 2) | |
1181 | SM(AR_BT_FIRST_SLOT_TIME, 5) | |
1182 | SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) | |
1183 | AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND | |
1184 | AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY); |
1185 | AR_WRITE(sc, AR_BT_COEX_WEIGHT, |
1186 | SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) | |
1187 | SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT)); |
1188 | AR_WRITE(sc, AR_BT_COEX_MODE2, |
1189 | SM(AR_BT_BCN_MISS_THRESH, 50) | |
1190 | AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT); |
1191 | |
1192 | AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); |
1193 | AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); |
1194 | AR_WRITE_BARRIER(sc); |
1195 | |
1196 | ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, |
1197 | AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); |
1198 | |
1199 | } |
1200 | else { /* 2-wire. */ |
1201 | ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, |
1202 | AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); |
1203 | } |
1204 | reg = AR_READ(sc, AR_GPIO_PDPU); |
1205 | reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2)); |
1206 | reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2); |
1207 | AR_WRITE(sc, AR_GPIO_PDPU, reg); |
1208 | AR_WRITE_BARRIER(sc); |
1209 | |
1210 | /* Disable PCIe Active State Power Management (ASPM). */ |
1211 | if (sc->sc_disable_aspm != NULL) |
1212 | sc->sc_disable_aspm(sc); |
1213 | |
1214 | /* XXX Start periodic timer. */ |
1215 | } |
1216 | |
1217 | Static void |
1218 | athn_btcoex_disable(struct athn_softc *sc) |
1219 | { |
1220 | struct athn_ops *ops = &sc->sc_ops; |
1221 | |
1222 | ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); |
1223 | |
1224 | ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, |
1225 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
1226 | |
1227 | if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { |
1228 | AR_WRITE(sc, AR_BT_COEX_MODE, |
1229 | SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET); |
1230 | AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); |
1231 | AR_WRITE(sc, AR_BT_COEX_MODE2, 0); |
1232 | /* XXX Stop periodic timer. */ |
1233 | } |
1234 | AR_WRITE_BARRIER(sc); |
1235 | /* XXX Restore ASPM setting? */ |
1236 | } |
1237 | #endif |
1238 | |
1239 | Static void |
1240 | athn_iter_func(void *arg, struct ieee80211_node *ni) |
1241 | { |
1242 | struct athn_softc *sc = arg; |
1243 | struct athn_node *an = (struct athn_node *)ni; |
1244 | |
1245 | ieee80211_amrr_choose(&sc->sc_amrr, ni, &an->amn); |
1246 | } |
1247 | |
1248 | Static void |
1249 | athn_calib_to(void *arg) |
1250 | { |
1251 | extern int ticks; |
1252 | struct athn_softc *sc = arg; |
1253 | struct athn_ops *ops = &sc->sc_ops; |
1254 | struct ieee80211com *ic = &sc->sc_ic; |
1255 | int s; |
1256 | |
1257 | s = splnet(); |
1258 | |
1259 | /* Do periodic (every 4 minutes) PA calibration. */ |
1260 | if (AR_SREV_9285_11_OR_LATER(sc) && |
1261 | !AR_SREV_9380_10_OR_LATER(sc) && |
1262 | (ticks - (sc->sc_pa_calib_ticks + 240 * hz)) >= 0) { |
1263 | sc->sc_pa_calib_ticks = ticks; |
1264 | if (AR_SREV_9271(sc)) |
1265 | ar9271_pa_calib(sc); |
1266 | else |
1267 | ar9285_pa_calib(sc); |
1268 | } |
1269 | |
1270 | /* Do periodic (every 30 seconds) temperature compensation. */ |
1271 | if ((sc->sc_flags & ATHN_FLAG_OLPC) && |
1272 | ticks >= sc->sc_olpc_ticks + 30 * hz) { |
1273 | sc->sc_olpc_ticks = ticks; |
1274 | ops->olpc_temp_compensation(sc); |
1275 | } |
1276 | |
1277 | #ifdef notyet |
1278 | /* XXX ANI. */ |
1279 | athn_ani_monitor(sc); |
1280 | |
1281 | ops->next_calib(sc); |
1282 | #endif |
1283 | if (ic->ic_fixed_rate == -1) { |
1284 | if (ic->ic_opmode == IEEE80211_M_STA) |
1285 | athn_iter_func(sc, ic->ic_bss); |
1286 | else |
1287 | ieee80211_iterate_nodes(&ic->ic_sta, athn_iter_func, sc); |
1288 | } |
1289 | callout_schedule(&sc->sc_calib_to, hz / 2); |
1290 | splx(s); |
1291 | } |
1292 | |
1293 | Static int |
1294 | athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan, |
1295 | struct ieee80211_channel *extchan) |
1296 | { |
1297 | struct athn_ops *ops = &sc->sc_ops; |
1298 | int error; |
1299 | |
1300 | if (AR_SREV_9380_10_OR_LATER(sc)) |
1301 | error = ar9003_init_calib(sc); |
1302 | else if (AR_SREV_9285_10_OR_LATER(sc)) |
1303 | error = ar9285_init_calib(sc, curchan, extchan); |
1304 | else |
1305 | error = ar5416_init_calib(sc, curchan, extchan); |
1306 | if (error != 0) |
1307 | return error; |
1308 | |
1309 | if (!AR_SREV_9380_10_OR_LATER(sc)) { |
1310 | /* Do PA calibration. */ |
1311 | if (AR_SREV_9285_11_OR_LATER(sc)) { |
1312 | extern int ticks; |
1313 | sc->sc_pa_calib_ticks = ticks; |
1314 | if (AR_SREV_9271(sc)) |
1315 | ar9271_pa_calib(sc); |
1316 | else |
1317 | ar9285_pa_calib(sc); |
1318 | } |
1319 | /* Do noisefloor calibration. */ |
1320 | ops->noisefloor_calib(sc); |
1321 | } |
1322 | if (AR_SREV_9160_10_OR_LATER(sc)) { |
1323 | /* Support IQ calibration. */ |
1324 | sc->sc_sup_calib_mask = ATHN_CAL_IQ; |
1325 | if (AR_SREV_9380_10_OR_LATER(sc)) { |
1326 | /* Support temperature compensation calibration. */ |
1327 | sc->sc_sup_calib_mask |= ATHN_CAL_TEMP; |
1328 | } |
1329 | else if (IEEE80211_IS_CHAN_5GHZ(curchan) || extchan != NULL) { |
1330 | /* |
1331 | * ADC gain calibration causes uplink throughput |
1332 | * drops in HT40 mode on AR9287. |
1333 | */ |
1334 | if (!AR_SREV_9287(sc)) { |
1335 | /* Support ADC gain calibration. */ |
1336 | sc->sc_sup_calib_mask |= ATHN_CAL_ADC_GAIN; |
1337 | } |
1338 | /* Support ADC DC offset calibration. */ |
1339 | sc->sc_sup_calib_mask |= ATHN_CAL_ADC_DC; |
1340 | } |
1341 | } |
1342 | return 0; |
1343 | } |
1344 | |
1345 | /* |
1346 | * Adaptive noise immunity. |
1347 | */ |
1348 | #ifdef notyet |
1349 | Static int32_t |
1350 | athn_ani_get_rssi(struct athn_softc *sc) |
1351 | { |
1352 | |
1353 | return 0; /* XXX */ |
1354 | } |
1355 | #endif /* notyet */ |
1356 | |
1357 | #ifdef notyet |
1358 | Static void |
1359 | athn_ani_ofdm_err_trigger(struct athn_softc *sc) |
1360 | { |
1361 | struct athn_ani *ani = &sc->sc_ani; |
1362 | struct athn_ops *ops = &sc->sc_ops; |
1363 | int32_t rssi; |
1364 | |
1365 | /* First, raise noise immunity level, up to max. */ |
1366 | if (ani->noise_immunity_level < 4) { |
1367 | ani->noise_immunity_level++; |
1368 | ops->set_noise_immunity_level(sc, ani->noise_immunity_level); |
1369 | return; |
1370 | } |
1371 | |
1372 | /* Then, raise our spur immunity level, up to max. */ |
1373 | if (ani->spur_immunity_level < 7) { |
1374 | ani->spur_immunity_level++; |
1375 | ops->set_spur_immunity_level(sc, ani->spur_immunity_level); |
1376 | return; |
1377 | } |
1378 | |
1379 | #ifndef IEEE80211_STA_ONLY |
1380 | if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { |
1381 | if (ani->firstep_level < 2) { |
1382 | ani->firstep_level++; |
1383 | ops->set_firstep_level(sc, ani->firstep_level); |
1384 | } |
1385 | return; |
1386 | } |
1387 | #endif |
1388 | rssi = athn_ani_get_rssi(sc); |
1389 | if (rssi > ATHN_ANI_RSSI_THR_HIGH) { |
1390 | /* |
1391 | * Beacon RSSI is high, turn off OFDM weak signal detection |
1392 | * or raise first step level as last resort. |
1393 | */ |
1394 | if (ani->ofdm_weak_signal) { |
1395 | ani->ofdm_weak_signal = 0; |
1396 | ops->disable_ofdm_weak_signal(sc); |
1397 | ani->spur_immunity_level = 0; |
1398 | ops->set_spur_immunity_level(sc, 0); |
1399 | } |
1400 | else if (ani->firstep_level < 2) { |
1401 | ani->firstep_level++; |
1402 | ops->set_firstep_level(sc, ani->firstep_level); |
1403 | } |
1404 | } |
1405 | else if (rssi > ATHN_ANI_RSSI_THR_LOW) { |
1406 | /* |
1407 | * Beacon RSSI is in mid range, we need OFDM weak signal |
1408 | * detection but we can raise first step level. |
1409 | */ |
1410 | if (!ani->ofdm_weak_signal) { |
1411 | ani->ofdm_weak_signal = 1; |
1412 | ops->enable_ofdm_weak_signal(sc); |
1413 | } |
1414 | if (ani->firstep_level < 2) { |
1415 | ani->firstep_level++; |
1416 | ops->set_firstep_level(sc, ani->firstep_level); |
1417 | } |
1418 | } |
1419 | else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { |
1420 | /* |
1421 | * Beacon RSSI is low, if in b/g mode, turn off OFDM weak |
1422 | * signal detection and zero first step level to maximize |
1423 | * CCK sensitivity. |
1424 | */ |
1425 | if (ani->ofdm_weak_signal) { |
1426 | ani->ofdm_weak_signal = 0; |
1427 | ops->disable_ofdm_weak_signal(sc); |
1428 | } |
1429 | if (ani->firstep_level > 0) { |
1430 | ani->firstep_level = 0; |
1431 | ops->set_firstep_level(sc, 0); |
1432 | } |
1433 | } |
1434 | } |
1435 | #endif /* notyet */ |
1436 | |
1437 | #ifdef notyet |
1438 | Static void |
1439 | athn_ani_cck_err_trigger(struct athn_softc *sc) |
1440 | { |
1441 | struct athn_ani *ani = &sc->sc_ani; |
1442 | struct athn_ops *ops = &sc->sc_ops; |
1443 | int32_t rssi; |
1444 | |
1445 | /* Raise noise immunity level, up to max. */ |
1446 | if (ani->noise_immunity_level < 4) { |
1447 | ani->noise_immunity_level++; |
1448 | ops->set_noise_immunity_level(sc, ani->noise_immunity_level); |
1449 | return; |
1450 | } |
1451 | |
1452 | #ifndef IEEE80211_STA_ONLY |
1453 | if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { |
1454 | if (ani->firstep_level < 2) { |
1455 | ani->firstep_level++; |
1456 | ops->set_firstep_level(sc, ani->firstep_level); |
1457 | } |
1458 | return; |
1459 | } |
1460 | #endif |
1461 | rssi = athn_ani_get_rssi(sc); |
1462 | if (rssi > ATHN_ANI_RSSI_THR_LOW) { |
1463 | /* |
1464 | * Beacon RSSI is in mid or high range, raise first step |
1465 | * level. |
1466 | */ |
1467 | if (ani->firstep_level < 2) { |
1468 | ani->firstep_level++; |
1469 | ops->set_firstep_level(sc, ani->firstep_level); |
1470 | } |
1471 | } |
1472 | else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { |
1473 | /* |
1474 | * Beacon RSSI is low, zero first step level to maximize |
1475 | * CCK sensitivity. |
1476 | */ |
1477 | if (ani->firstep_level > 0) { |
1478 | ani->firstep_level = 0; |
1479 | ops->set_firstep_level(sc, 0); |
1480 | } |
1481 | } |
1482 | } |
1483 | #endif /* notyet */ |
1484 | |
1485 | #ifdef notyet |
1486 | Static void |
1487 | athn_ani_lower_immunity(struct athn_softc *sc) |
1488 | { |
1489 | struct athn_ani *ani = &sc->sc_ani; |
1490 | struct athn_ops *ops = &sc->sc_ops; |
1491 | int32_t rssi; |
1492 | |
1493 | #ifndef IEEE80211_STA_ONLY |
1494 | if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { |
1495 | if (ani->firstep_level > 0) { |
1496 | ani->firstep_level--; |
1497 | ops->set_firstep_level(sc, ani->firstep_level); |
1498 | } |
1499 | return; |
1500 | } |
1501 | #endif |
1502 | rssi = athn_ani_get_rssi(sc); |
1503 | if (rssi > ATHN_ANI_RSSI_THR_HIGH) { |
1504 | /* |
1505 | * Beacon RSSI is high, leave OFDM weak signal detection |
1506 | * off or it may oscillate. |
1507 | */ |
1508 | } |
1509 | else if (rssi > ATHN_ANI_RSSI_THR_LOW) { |
1510 | /* |
1511 | * Beacon RSSI is in mid range, turn on OFDM weak signal |
1512 | * detection or lower first step level. |
1513 | */ |
1514 | if (!ani->ofdm_weak_signal) { |
1515 | ani->ofdm_weak_signal = 1; |
1516 | ops->enable_ofdm_weak_signal(sc); |
1517 | return; |
1518 | } |
1519 | if (ani->firstep_level > 0) { |
1520 | ani->firstep_level--; |
1521 | ops->set_firstep_level(sc, ani->firstep_level); |
1522 | return; |
1523 | } |
1524 | } |
1525 | else { |
1526 | /* Beacon RSSI is low, lower first step level. */ |
1527 | if (ani->firstep_level > 0) { |
1528 | ani->firstep_level--; |
1529 | ops->set_firstep_level(sc, ani->firstep_level); |
1530 | return; |
1531 | } |
1532 | } |
1533 | /* |
1534 | * Lower spur immunity level down to zero, or if all else fails, |
1535 | * lower noise immunity level down to zero. |
1536 | */ |
1537 | if (ani->spur_immunity_level > 0) { |
1538 | ani->spur_immunity_level--; |
1539 | ops->set_spur_immunity_level(sc, ani->spur_immunity_level); |
1540 | } |
1541 | else if (ani->noise_immunity_level > 0) { |
1542 | ani->noise_immunity_level--; |
1543 | ops->set_noise_immunity_level(sc, ani->noise_immunity_level); |
1544 | } |
1545 | } |
1546 | #endif /* notyet */ |
1547 | |
1548 | #ifdef notyet |
1549 | Static void |
1550 | athn_ani_restart(struct athn_softc *sc) |
1551 | { |
1552 | struct athn_ani *ani = &sc->sc_ani; |
1553 | |
1554 | AR_WRITE(sc, AR_PHY_ERR_1, 0); |
1555 | AR_WRITE(sc, AR_PHY_ERR_2, 0); |
1556 | AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); |
1557 | AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); |
1558 | AR_WRITE_BARRIER(sc); |
1559 | |
1560 | ani->listen_time = 0; |
1561 | ani->ofdm_phy_err_count = 0; |
1562 | ani->cck_phy_err_count = 0; |
1563 | } |
1564 | #endif /* notyet */ |
1565 | |
1566 | #ifdef notyet |
1567 | Static void |
1568 | athn_ani_monitor(struct athn_softc *sc) |
1569 | { |
1570 | struct athn_ani *ani = &sc->sc_ani; |
1571 | uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; |
1572 | int32_t cycdelta, txfdelta, rxfdelta; |
1573 | int32_t listen_time; |
1574 | |
1575 | txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ |
1576 | rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ |
1577 | cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ |
1578 | |
1579 | if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { |
1580 | cycdelta = cyccnt - ani->cyccnt; |
1581 | txfdelta = txfcnt - ani->txfcnt; |
1582 | rxfdelta = rxfcnt - ani->rxfcnt; |
1583 | |
1584 | listen_time = (cycdelta - txfdelta - rxfdelta) / |
1585 | (athn_clock_rate(sc) * 1000); |
1586 | } |
1587 | else |
1588 | listen_time = 0; |
1589 | |
1590 | ani->cyccnt = cyccnt; |
1591 | ani->txfcnt = txfcnt; |
1592 | ani->rxfcnt = rxfcnt; |
1593 | |
1594 | if (listen_time < 0) { |
1595 | athn_ani_restart(sc); |
1596 | return; |
1597 | } |
1598 | ani->listen_time += listen_time; |
1599 | |
1600 | phy1 = AR_READ(sc, AR_PHY_ERR_1); |
1601 | phy2 = AR_READ(sc, AR_PHY_ERR_2); |
1602 | |
1603 | if (phy1 < ani->ofdm_phy_err_base) { |
1604 | AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); |
1605 | AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); |
1606 | } |
1607 | if (phy2 < ani->cck_phy_err_base) { |
1608 | AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); |
1609 | AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); |
1610 | } |
1611 | if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) { |
1612 | AR_WRITE_BARRIER(sc); |
1613 | return; |
1614 | } |
1615 | ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; |
1616 | ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; |
1617 | |
1618 | if (ani->listen_time > 5 * ATHN_ANI_PERIOD) { |
1619 | /* Check to see if we need to lower immunity. */ |
1620 | if (ani->ofdm_phy_err_count <= |
1621 | ani->listen_time * ani->ofdm_trig_low / 1000 && |
1622 | ani->cck_phy_err_count <= |
1623 | ani->listen_time * ani->cck_trig_low / 1000) |
1624 | athn_ani_lower_immunity(sc); |
1625 | athn_ani_restart(sc); |
1626 | |
1627 | } |
1628 | else if (ani->listen_time > ATHN_ANI_PERIOD) { |
1629 | /* Check to see if we need to raise immunity. */ |
1630 | if (ani->ofdm_phy_err_count > |
1631 | ani->listen_time * ani->ofdm_trig_high / 1000) { |
1632 | athn_ani_ofdm_err_trigger(sc); |
1633 | athn_ani_restart(sc); |
1634 | } |
1635 | else if (ani->cck_phy_err_count > |
1636 | ani->listen_time * ani->cck_trig_high / 1000) { |
1637 | athn_ani_cck_err_trigger(sc); |
1638 | athn_ani_restart(sc); |
1639 | } |
1640 | } |
1641 | } |
1642 | #endif /* notyet */ |
1643 | |
1644 | PUBLIC uint8_t |
1645 | athn_chan2fbin(struct ieee80211_channel *c) |
1646 | { |
1647 | |
1648 | if (IEEE80211_IS_CHAN_2GHZ(c)) |
1649 | return c->ic_freq - 2300; |
1650 | else |
1651 | return (c->ic_freq - 4800) / 5; |
1652 | } |
1653 | |
1654 | PUBLIC int |
1655 | athn_interpolate(int x, int x1, int y1, int x2, int y2) |
1656 | { |
1657 | |
1658 | if (x1 == x2) /* Prevents division by zero. */ |
1659 | return y1; |
1660 | /* Linear interpolation. */ |
1661 | return y1 + ((x - x1) * (y2 - y1)) / (x2 - x1); |
1662 | } |
1663 | |
1664 | PUBLIC void |
1665 | athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, |
1666 | int *lo, int *hi) |
1667 | { |
1668 | int i; |
1669 | |
1670 | for (i = 0; i < npiers; i++) |
1671 | if (pierfreq[i] == AR_BCHAN_UNUSED || |
1672 | pierfreq[i] > fbin) |
1673 | break; |
1674 | *hi = i; |
1675 | *lo = *hi - 1; |
1676 | if (*lo == -1) |
1677 | *lo = *hi; |
1678 | else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED) |
1679 | *hi = *lo; |
1680 | } |
1681 | |
1682 | Static void |
1683 | athn_init_dma(struct athn_softc *sc) |
1684 | { |
1685 | uint32_t reg; |
1686 | |
1687 | if (!AR_SREV_9380_10_OR_LATER(sc)) { |
1688 | /* Set AHB not to do cacheline prefetches. */ |
1689 | AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); |
1690 | } |
1691 | reg = AR_READ(sc, AR_TXCFG); |
1692 | /* Let MAC DMA reads be in 128-byte chunks. */ |
1693 | reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B); |
1694 | |
1695 | /* Set initial Tx trigger level. */ |
1696 | if (AR_SREV_9285(sc) || AR_SREV_9271(sc)) |
1697 | reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B); |
1698 | else if (!AR_SREV_9380_10_OR_LATER(sc)) |
1699 | reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B); |
1700 | AR_WRITE(sc, AR_TXCFG, reg); |
1701 | |
1702 | /* Let MAC DMA writes be in 128-byte chunks. */ |
1703 | reg = AR_READ(sc, AR_RXCFG); |
1704 | reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B); |
1705 | AR_WRITE(sc, AR_RXCFG, reg); |
1706 | |
1707 | /* Setup Rx FIFO threshold to hold off Tx activities. */ |
1708 | AR_WRITE(sc, AR_RXFIFO_CFG, 512); |
1709 | |
1710 | /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ |
1711 | if (AR_SREV_9285(sc)) { |
1712 | AR_WRITE(sc, AR_PCU_TXBUF_CTRL, |
1713 | AR9285_PCU_TXBUF_CTRL_USABLE_SIZE); |
1714 | } |
1715 | else if (!AR_SREV_9271(sc)) { |
1716 | AR_WRITE(sc, AR_PCU_TXBUF_CTRL, |
1717 | AR_PCU_TXBUF_CTRL_USABLE_SIZE); |
1718 | } |
1719 | AR_WRITE_BARRIER(sc); |
1720 | |
1721 | /* Reset Tx status ring. */ |
1722 | if (AR_SREV_9380_10_OR_LATER(sc)) |
1723 | ar9003_reset_txsring(sc); |
1724 | } |
1725 | |
1726 | PUBLIC void |
1727 | athn_inc_tx_trigger_level(struct athn_softc *sc) |
1728 | { |
1729 | uint32_t reg, ftrig; |
1730 | |
1731 | reg = AR_READ(sc, AR_TXCFG); |
1732 | ftrig = MS(reg, AR_TXCFG_FTRIG); |
1733 | /* |
1734 | * NB: The AR9285 and all single-stream parts have an issue that |
1735 | * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. |
1736 | */ |
1737 | if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f)) |
1738 | return; /* Already at max. */ |
1739 | reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1); |
1740 | AR_WRITE(sc, AR_TXCFG, reg); |
1741 | AR_WRITE_BARRIER(sc); |
1742 | } |
1743 | |
1744 | PUBLIC int |
1745 | athn_stop_rx_dma(struct athn_softc *sc) |
1746 | { |
1747 | int ntries; |
1748 | |
1749 | AR_WRITE(sc, AR_CR, AR_CR_RXD); |
1750 | /* Wait for Rx enable bit to go low. */ |
1751 | for (ntries = 0; ntries < 100; ntries++) { |
1752 | if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) |
1753 | return 0; |
1754 | DELAY(100); |
1755 | } |
1756 | DPRINTFN(DBG_RX, sc, "Rx DMA failed to stop\n" ); |
1757 | return ETIMEDOUT; |
1758 | } |
1759 | |
1760 | #ifdef unused |
1761 | Static int |
1762 | athn_rx_abort(struct athn_softc *sc) |
1763 | { |
1764 | int ntries; |
1765 | |
1766 | AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); |
1767 | for (ntries = 0; ntries < 1000; ntries++) { |
1768 | if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) |
1769 | return 0; |
1770 | DELAY(10); |
1771 | } |
1772 | DPRINTFN(DBG_RX, sc, "Rx failed to go idle in 10ms\n" ); |
1773 | AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); |
1774 | AR_WRITE_BARRIER(sc); |
1775 | return ETIMEDOUT; |
1776 | } |
1777 | #endif /* unused */ |
1778 | |
1779 | Static void |
1780 | athn_tx_reclaim(struct athn_softc *sc, int qid) |
1781 | { |
1782 | struct athn_txq *txq = &sc->sc_txq[qid]; |
1783 | struct athn_tx_buf *bf; |
1784 | |
1785 | /* Reclaim all buffers queued in the specified Tx queue. */ |
1786 | /* NB: Tx DMA must be stopped. */ |
1787 | while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) { |
1788 | SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); |
1789 | |
1790 | bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, |
1791 | bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); |
1792 | bus_dmamap_unload(sc->sc_dmat, bf->bf_map); |
1793 | m_freem(bf->bf_m); |
1794 | bf->bf_m = NULL; |
1795 | bf->bf_ni = NULL; /* Nodes already freed! */ |
1796 | |
1797 | /* Link Tx buffer back to global free list. */ |
1798 | SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); |
1799 | } |
1800 | } |
1801 | |
1802 | PUBLIC int |
1803 | athn_tx_pending(struct athn_softc *sc, int qid) |
1804 | { |
1805 | |
1806 | return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || |
1807 | (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0; |
1808 | } |
1809 | |
1810 | PUBLIC void |
1811 | athn_stop_tx_dma(struct athn_softc *sc, int qid) |
1812 | { |
1813 | uint32_t tsflo; |
1814 | int ntries, i; |
1815 | |
1816 | AR_WRITE(sc, AR_Q_TXD, 1 << qid); |
1817 | for (ntries = 0; ntries < 40; ntries++) { |
1818 | if (!athn_tx_pending(sc, qid)) |
1819 | break; |
1820 | DELAY(100); |
1821 | } |
1822 | if (ntries == 40) { |
1823 | for (i = 0; i < 2; i++) { |
1824 | tsflo = AR_READ(sc, AR_TSF_L32) / 1024; |
1825 | AR_WRITE(sc, AR_QUIET2, |
1826 | SM(AR_QUIET2_QUIET_DUR, 10)); |
1827 | AR_WRITE(sc, AR_QUIET_PERIOD, 100); |
1828 | AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); |
1829 | AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); |
1830 | if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) |
1831 | break; |
1832 | } |
1833 | AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); |
1834 | AR_WRITE_BARRIER(sc); |
1835 | DELAY(200); |
1836 | AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); |
1837 | AR_WRITE_BARRIER(sc); |
1838 | |
1839 | for (ntries = 0; ntries < 40; ntries++) { |
1840 | if (!athn_tx_pending(sc, qid)) |
1841 | break; |
1842 | DELAY(100); |
1843 | } |
1844 | |
1845 | AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); |
1846 | } |
1847 | AR_WRITE(sc, AR_Q_TXD, 0); |
1848 | AR_WRITE_BARRIER(sc); |
1849 | } |
1850 | |
1851 | PUBLIC int |
1852 | athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) |
1853 | { |
1854 | #define divround(a, b) (((a) + (b) - 1) / (b)) |
1855 | int txtime; |
1856 | |
1857 | /* XXX HT. */ |
1858 | if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { |
1859 | txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); |
1860 | /* SIFS is 10us for 11g but Signal Extension adds 6us. */ |
1861 | txtime = 16 + 4 + 4 * txtime + 16; |
1862 | } |
1863 | else { |
1864 | txtime = divround(16 * len, athn_rates[ridx].rate); |
1865 | if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE)) |
1866 | txtime += 72 + 24; |
1867 | else |
1868 | txtime += 144 + 48; |
1869 | txtime += 10; /* 10us SIFS. */ |
1870 | } |
1871 | return txtime; |
1872 | #undef divround |
1873 | } |
1874 | |
1875 | PUBLIC void |
1876 | athn_init_tx_queues(struct athn_softc *sc) |
1877 | { |
1878 | int qid; |
1879 | |
1880 | for (qid = 0; qid < ATHN_QID_COUNT; qid++) { |
1881 | SIMPLEQ_INIT(&sc->sc_txq[qid].head); |
1882 | sc->sc_txq[qid].lastds = NULL; |
1883 | sc->sc_txq[qid].wait = NULL; |
1884 | sc->sc_txq[qid].queued = 0; |
1885 | |
1886 | AR_WRITE(sc, AR_DRETRY_LIMIT(qid), |
1887 | SM(AR_D_RETRY_LIMIT_STA_SH, 32) | |
1888 | SM(AR_D_RETRY_LIMIT_STA_LG, 32) | |
1889 | SM(AR_D_RETRY_LIMIT_FR_SH, 10)); |
1890 | AR_WRITE(sc, AR_QMISC(qid), |
1891 | AR_Q_MISC_DCU_EARLY_TERM_REQ); |
1892 | AR_WRITE(sc, AR_DMISC(qid), |
1893 | SM(AR_D_MISC_BKOFF_THRESH, 2) | |
1894 | AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN); |
1895 | } |
1896 | |
1897 | /* Init beacon queue. */ |
1898 | AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), |
1899 | AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | |
1900 | AR_Q_MISC_CBR_INCR_DIS1); |
1901 | AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), |
1902 | SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, |
1903 | AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) | |
1904 | AR_D_MISC_BEACON_USE | |
1905 | AR_D_MISC_POST_FR_BKOFF_DIS); |
1906 | AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), |
1907 | SM(AR_D_LCL_IFS_CWMIN, 0) | |
1908 | SM(AR_D_LCL_IFS_CWMAX, 0) | |
1909 | SM(AR_D_LCL_IFS_AIFS, 1)); |
1910 | |
1911 | /* Init CAB (Content After Beacon) queue. */ |
1912 | AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), |
1913 | AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | |
1914 | AR_Q_MISC_CBR_INCR_DIS0); |
1915 | AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), |
1916 | SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, |
1917 | AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL)); |
1918 | |
1919 | /* Init PS-Poll queue. */ |
1920 | AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), |
1921 | AR_Q_MISC_CBR_INCR_DIS1); |
1922 | |
1923 | /* Init UAPSD queue. */ |
1924 | AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), |
1925 | AR_D_MISC_POST_FR_BKOFF_DIS); |
1926 | |
1927 | if (AR_SREV_9380_10_OR_LATER(sc)) { |
1928 | /* Enable MAC descriptor CRC check. */ |
1929 | AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); |
1930 | } |
1931 | /* Enable DESC interrupts for all Tx queues. */ |
1932 | AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); |
1933 | /* Enable EOL interrupts for all Tx queues except UAPSD. */ |
1934 | AR_WRITE(sc, AR_IMR_S1, 0x00df0000); |
1935 | AR_WRITE_BARRIER(sc); |
1936 | } |
1937 | |
1938 | PUBLIC void |
1939 | athn_set_sta_timers(struct athn_softc *sc) |
1940 | { |
1941 | struct ieee80211com *ic = &sc->sc_ic; |
1942 | uint32_t tsfhi, tsflo, tsftu, reg; |
1943 | uint32_t intval, next_tbtt, next_dtim; |
1944 | int dtim_period, rem_dtim_count; |
1945 | |
1946 | tsfhi = AR_READ(sc, AR_TSF_U32); |
1947 | tsflo = AR_READ(sc, AR_TSF_L32); |
1948 | tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE; |
1949 | |
1950 | /* Beacon interval in TU. */ |
1951 | intval = ic->ic_bss->ni_intval; |
1952 | |
1953 | next_tbtt = roundup(tsftu, intval); |
1954 | #ifdef notyet |
1955 | dtim_period = ic->ic_dtim_period; |
1956 | if (dtim_period <= 0) |
1957 | #endif |
1958 | dtim_period = 1; /* Assume all TIMs are DTIMs. */ |
1959 | |
1960 | #ifdef notyet |
1961 | int dtim_count = ic->ic_dtim_count; |
1962 | if (dtim_count >= dtim_period) /* Should not happen. */ |
1963 | dtim_count = 0; /* Assume last TIM was a DTIM. */ |
1964 | #endif |
1965 | |
1966 | /* Compute number of remaining TIMs until next DTIM. */ |
1967 | rem_dtim_count = 0; /* XXX */ |
1968 | next_dtim = next_tbtt + rem_dtim_count * intval; |
1969 | |
1970 | AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); |
1971 | AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); |
1972 | AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); |
1973 | |
1974 | /* |
1975 | * Set the number of consecutive beacons to miss before raising |
1976 | * a BMISS interrupt to 10. |
1977 | */ |
1978 | reg = AR_READ(sc, AR_RSSI_THR); |
1979 | reg = RW(reg, AR_RSSI_THR_BM_THR, 10); |
1980 | AR_WRITE(sc, AR_RSSI_THR, reg); |
1981 | |
1982 | AR_WRITE(sc, AR_NEXT_DTIM, |
1983 | (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); |
1984 | AR_WRITE(sc, AR_NEXT_TIM, |
1985 | (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); |
1986 | |
1987 | /* CAB timeout is in 1/8 TU. */ |
1988 | AR_WRITE(sc, AR_SLEEP1, |
1989 | SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) | |
1990 | AR_SLEEP1_ASSUME_DTIM); |
1991 | AR_WRITE(sc, AR_SLEEP2, |
1992 | SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL)); |
1993 | |
1994 | AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); |
1995 | AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); |
1996 | |
1997 | AR_SETBITS(sc, AR_TIMER_MODE, |
1998 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN); |
1999 | |
2000 | /* Set TSF out-of-range threshold (fixed at 16k us). */ |
2001 | AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); |
2002 | |
2003 | AR_WRITE_BARRIER(sc); |
2004 | } |
2005 | |
2006 | #ifndef IEEE80211_STA_ONLY |
2007 | PUBLIC void |
2008 | athn_set_hostap_timers(struct athn_softc *sc) |
2009 | { |
2010 | struct ieee80211com *ic = &sc->sc_ic; |
2011 | uint32_t intval, next_tbtt; |
2012 | |
2013 | /* Beacon interval in TU. */ |
2014 | intval = ic->ic_bss->ni_intval; |
2015 | next_tbtt = intval; |
2016 | |
2017 | AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); |
2018 | AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT, |
2019 | (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU); |
2020 | AR_WRITE(sc, AR_NEXT_CFP, |
2021 | (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU); |
2022 | |
2023 | AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); |
2024 | AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); |
2025 | AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU); |
2026 | AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU); |
2027 | |
2028 | AR_WRITE(sc, AR_TIMER_MODE, |
2029 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); |
2030 | |
2031 | AR_WRITE_BARRIER(sc); |
2032 | } |
2033 | #endif |
2034 | |
2035 | PUBLIC void |
2036 | athn_set_opmode(struct athn_softc *sc) |
2037 | { |
2038 | uint32_t reg; |
2039 | |
2040 | switch (sc->sc_ic.ic_opmode) { |
2041 | #ifndef IEEE80211_STA_ONLY |
2042 | case IEEE80211_M_HOSTAP: |
2043 | reg = AR_READ(sc, AR_STA_ID1); |
2044 | reg &= ~AR_STA_ID1_ADHOC; |
2045 | reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE; |
2046 | AR_WRITE(sc, AR_STA_ID1, reg); |
2047 | |
2048 | AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
2049 | break; |
2050 | case IEEE80211_M_IBSS: |
2051 | case IEEE80211_M_AHDEMO: |
2052 | reg = AR_READ(sc, AR_STA_ID1); |
2053 | reg &= ~AR_STA_ID1_STA_AP; |
2054 | reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE; |
2055 | AR_WRITE(sc, AR_STA_ID1, reg); |
2056 | |
2057 | AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
2058 | break; |
2059 | #endif |
2060 | default: |
2061 | reg = AR_READ(sc, AR_STA_ID1); |
2062 | reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP); |
2063 | reg |= AR_STA_ID1_KSRCH_MODE; |
2064 | AR_WRITE(sc, AR_STA_ID1, reg); |
2065 | break; |
2066 | } |
2067 | AR_WRITE_BARRIER(sc); |
2068 | } |
2069 | |
2070 | PUBLIC void |
2071 | athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) |
2072 | { |
2073 | const uint8_t *bssid = ni->ni_bssid; |
2074 | |
2075 | AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0])); |
2076 | AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) | |
2077 | SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd))); |
2078 | AR_WRITE_BARRIER(sc); |
2079 | } |
2080 | |
2081 | Static void |
2082 | athn_enable_interrupts(struct athn_softc *sc) |
2083 | { |
2084 | uint32_t mask2; |
2085 | |
2086 | athn_disable_interrupts(sc); /* XXX */ |
2087 | |
2088 | AR_WRITE(sc, AR_IMR, sc->sc_imask); |
2089 | |
2090 | mask2 = AR_READ(sc, AR_IMR_S2); |
2091 | mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | |
2092 | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); |
2093 | mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; |
2094 | AR_WRITE(sc, AR_IMR_S2, mask2); |
2095 | |
2096 | AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); |
2097 | |
2098 | AR_WRITE(sc, AR_IER, AR_IER_ENABLE); |
2099 | |
2100 | AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); |
2101 | AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); |
2102 | |
2103 | AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); |
2104 | AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); |
2105 | AR_WRITE_BARRIER(sc); |
2106 | } |
2107 | |
2108 | Static void |
2109 | athn_disable_interrupts(struct athn_softc *sc) |
2110 | { |
2111 | |
2112 | AR_WRITE(sc, AR_IER, 0); |
2113 | (void)AR_READ(sc, AR_IER); |
2114 | |
2115 | AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); |
2116 | (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); |
2117 | |
2118 | AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); |
2119 | (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); |
2120 | |
2121 | AR_WRITE(sc, AR_IMR, 0); |
2122 | |
2123 | AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | |
2124 | AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | |
2125 | AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); |
2126 | |
2127 | AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); |
2128 | AR_WRITE_BARRIER(sc); |
2129 | } |
2130 | |
2131 | Static void |
2132 | athn_init_qos(struct athn_softc *sc) |
2133 | { |
2134 | |
2135 | /* Initialize QoS settings. */ |
2136 | AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); |
2137 | AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); |
2138 | AR_WRITE(sc, AR_QOS_NO_ACK, |
2139 | SM(AR_QOS_NO_ACK_TWO_BIT, 2) | |
2140 | SM(AR_QOS_NO_ACK_BIT_OFF, 5) | |
2141 | SM(AR_QOS_NO_ACK_BYTE_OFF, 0)); |
2142 | AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); |
2143 | /* Initialize TXOP for all TIDs. */ |
2144 | AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); |
2145 | AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); |
2146 | AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); |
2147 | AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); |
2148 | AR_WRITE_BARRIER(sc); |
2149 | } |
2150 | |
2151 | PUBLIC int |
2152 | athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan, |
2153 | struct ieee80211_channel *extchan, int init) |
2154 | { |
2155 | struct ieee80211com *ic = &sc->sc_ic; |
2156 | struct athn_ops *ops = &sc->sc_ops; |
2157 | uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; |
2158 | int i, error; |
2159 | |
2160 | /* XXX not if already awake */ |
2161 | if ((error = athn_set_power_awake(sc)) != 0) { |
2162 | aprint_error_dev(sc->sc_dev, "could not wakeup chip\n" ); |
2163 | return error; |
2164 | } |
2165 | |
2166 | /* Preserve the antenna on a channel switch. */ |
2167 | if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) |
2168 | def_ant = 1; |
2169 | /* Preserve other registers. */ |
2170 | sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; |
2171 | cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | |
2172 | AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M | |
2173 | AR_CFG_LED_BLINK_SLOW); |
2174 | |
2175 | /* Mark PHY as inactive. */ |
2176 | ops->disable_phy(sc); |
2177 | |
2178 | if (init && AR_SREV_9271(sc)) { |
2179 | AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, |
2180 | AR9271_RADIO_RF_RST); |
2181 | DELAY(50); |
2182 | } |
2183 | if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { |
2184 | /* Save TSF before it gets cleared. */ |
2185 | tsfhi = AR_READ(sc, AR_TSF_U32); |
2186 | tsflo = AR_READ(sc, AR_TSF_L32); |
2187 | |
2188 | /* NB: RTC reset clears TSF. */ |
2189 | error = athn_reset_power_on(sc); |
2190 | } |
2191 | else { |
2192 | tsfhi = tsflo = 0; /* XXX: gcc */ |
2193 | error = athn_reset(sc, 0); |
2194 | } |
2195 | if (error != 0) { |
2196 | aprint_error_dev(sc->sc_dev, |
2197 | "could not reset chip (error=%d)\n" , error); |
2198 | return error; |
2199 | } |
2200 | |
2201 | /* XXX not if already awake */ |
2202 | if ((error = athn_set_power_awake(sc)) != 0) { |
2203 | aprint_error_dev(sc->sc_dev, "could not wakeup chip\n" ); |
2204 | return error; |
2205 | } |
2206 | |
2207 | athn_init_pll(sc, curchan); |
2208 | ops->set_rf_mode(sc, curchan); |
2209 | |
2210 | if (sc->sc_flags & ATHN_FLAG_RFSILENT) { |
2211 | /* Check that the radio is not disabled by hardware switch. */ |
2212 | reg = ops->gpio_read(sc, sc->sc_rfsilent_pin); |
2213 | if (sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED) |
2214 | reg = !reg; |
2215 | if (!reg) { |
2216 | aprint_error_dev(sc->sc_dev, |
2217 | "radio is disabled by hardware switch\n" ); |
2218 | return EPERM; |
2219 | } |
2220 | } |
2221 | if (init && AR_SREV_9271(sc)) { |
2222 | AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, |
2223 | AR9271_GATE_MAC_CTL); |
2224 | DELAY(50); |
2225 | } |
2226 | if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { |
2227 | /* Restore TSF if it got cleared. */ |
2228 | AR_WRITE(sc, AR_TSF_L32, tsflo); |
2229 | AR_WRITE(sc, AR_TSF_U32, tsfhi); |
2230 | } |
2231 | |
2232 | if (AR_SREV_9280_10_OR_LATER(sc)) |
2233 | AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE); |
2234 | |
2235 | if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) |
2236 | ar9287_1_3_enable_async_fifo(sc); |
2237 | |
2238 | /* Write init values to hardware. */ |
2239 | ops->hw_init(sc, curchan, extchan); |
2240 | |
2241 | /* |
2242 | * Only >=AR9280 2.0 parts are capable of encrypting unicast |
2243 | * management frames using CCMP. |
2244 | */ |
2245 | if (AR_SREV_9280_20_OR_LATER(sc)) { |
2246 | reg = AR_READ(sc, AR_AES_MUTE_MASK1); |
2247 | /* Do not mask the subtype field in management frames. */ |
2248 | reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff); |
2249 | reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT, |
2250 | (uint32_t)~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT | |
2251 | IEEE80211_FC1_MORE_DATA)); |
2252 | AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); |
2253 | } |
2254 | else if (AR_SREV_9160_10_OR_LATER(sc)) { |
2255 | /* Disable hardware crypto for management frames. */ |
2256 | AR_CLRBITS(sc, AR_PCU_MISC_MODE2, |
2257 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); |
2258 | AR_SETBITS(sc, AR_PCU_MISC_MODE2, |
2259 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); |
2260 | } |
2261 | |
2262 | if (ic->ic_curmode != IEEE80211_MODE_11B) |
2263 | ops->set_delta_slope(sc, curchan, extchan); |
2264 | |
2265 | ops->spur_mitigate(sc, curchan, extchan); |
2266 | ops->init_from_rom(sc, curchan, extchan); |
2267 | |
2268 | /* XXX */ |
2269 | AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0])); |
2270 | AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) | |
2271 | sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE); |
2272 | |
2273 | athn_set_opmode(sc); |
2274 | |
2275 | AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); |
2276 | AR_WRITE(sc, AR_BSSMSKU, 0xffff); |
2277 | |
2278 | /* Restore previous antenna. */ |
2279 | AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); |
2280 | |
2281 | AR_WRITE(sc, AR_BSS_ID0, 0); |
2282 | AR_WRITE(sc, AR_BSS_ID1, 0); |
2283 | |
2284 | AR_WRITE(sc, AR_ISR, 0xffffffff); |
2285 | |
2286 | AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); |
2287 | |
2288 | if ((error = ops->set_synth(sc, curchan, extchan)) != 0) { |
2289 | aprint_error_dev(sc->sc_dev, "could not set channel\n" ); |
2290 | return error; |
2291 | } |
2292 | sc->sc_curchan = curchan; |
2293 | sc->sc_curchanext = extchan; |
2294 | |
2295 | for (i = 0; i < AR_NUM_DCU; i++) |
2296 | AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); |
2297 | |
2298 | athn_init_tx_queues(sc); |
2299 | |
2300 | /* Initialize interrupt mask. */ |
2301 | sc->sc_imask = |
2302 | AR_IMR_TXDESC | AR_IMR_TXEOL | |
2303 | AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN | |
2304 | AR_IMR_RXMINTR | AR_IMR_RXINTM | |
2305 | AR_IMR_GENTMR | AR_IMR_BCNMISC; |
2306 | if (AR_SREV_9380_10_OR_LATER(sc)) |
2307 | sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; |
2308 | #ifndef IEEE80211_STA_ONLY |
2309 | if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP) |
2310 | sc->sc_imask |= AR_IMR_MIB; |
2311 | #endif |
2312 | AR_WRITE(sc, AR_IMR, sc->sc_imask); |
2313 | AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); |
2314 | AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); |
2315 | sc->sc_isync = AR_INTR_SYNC_DEFAULT; |
2316 | if (sc->sc_flags & ATHN_FLAG_RFSILENT) |
2317 | sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin); |
2318 | AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); |
2319 | AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); |
2320 | if (AR_SREV_9380_10_OR_LATER(sc)) { |
2321 | AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); |
2322 | AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); |
2323 | AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); |
2324 | AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); |
2325 | } |
2326 | |
2327 | athn_init_qos(sc); |
2328 | |
2329 | AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); |
2330 | |
2331 | if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) |
2332 | ar9287_1_3_setup_async_fifo(sc); |
2333 | |
2334 | /* Disable sequence number generation in hardware. */ |
2335 | AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); |
2336 | |
2337 | athn_init_dma(sc); |
2338 | |
2339 | /* Program observation bus to see MAC interrupts. */ |
2340 | AR_WRITE(sc, sc->sc_obs_off, 8); |
2341 | |
2342 | /* Setup Rx interrupt mitigation. */ |
2343 | AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); |
2344 | |
2345 | ops->init_baseband(sc); |
2346 | |
2347 | if ((error = athn_init_calib(sc, curchan, extchan)) != 0) { |
2348 | aprint_error_dev(sc->sc_dev, |
2349 | "could not initialize calibration\n" ); |
2350 | return error; |
2351 | } |
2352 | |
2353 | ops->set_rxchains(sc); |
2354 | |
2355 | AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); |
2356 | |
2357 | if (sc->sc_flags & ATHN_FLAG_USB) { |
2358 | if (AR_SREV_9271(sc)) |
2359 | AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); |
2360 | else |
2361 | AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); |
2362 | } |
2363 | #if BYTE_ORDER == BIG_ENDIAN |
2364 | else { |
2365 | /* Default is LE, turn on swapping for BE. */ |
2366 | AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); |
2367 | } |
2368 | #endif |
2369 | AR_WRITE_BARRIER(sc); |
2370 | |
2371 | return 0; |
2372 | } |
2373 | |
2374 | Static struct ieee80211_node * |
2375 | athn_node_alloc(struct ieee80211_node_table *ntp) |
2376 | { |
2377 | |
2378 | return malloc(sizeof(struct athn_node), M_DEVBUF, |
2379 | M_NOWAIT | M_ZERO); |
2380 | } |
2381 | |
2382 | Static void |
2383 | athn_newassoc(struct ieee80211_node *ni, int isnew) |
2384 | { |
2385 | struct ieee80211com *ic = ni->ni_ic; |
2386 | struct athn_softc *sc = ic->ic_ifp->if_softc; |
2387 | struct athn_node *an = (void *)ni; |
2388 | struct ieee80211_rateset *rs = &ni->ni_rates; |
2389 | uint8_t rate; |
2390 | int ridx, i, j; |
2391 | |
2392 | ieee80211_amrr_node_init(&sc->sc_amrr, &an->amn); |
2393 | /* Start at lowest available bit-rate, AMRR will raise. */ |
2394 | ni->ni_txrate = 0; |
2395 | |
2396 | for (i = 0; i < rs->rs_nrates; i++) { |
2397 | rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; |
2398 | |
2399 | /* Map 802.11 rate to HW rate index. */ |
2400 | for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) |
2401 | if (athn_rates[ridx].rate == rate) |
2402 | break; |
2403 | an->ridx[i] = ridx; |
2404 | DPRINTFN(DBG_STM, sc, "rate %d index %d\n" , rate, ridx); |
2405 | |
2406 | /* Compute fallback rate for retries. */ |
2407 | an->fallback[i] = i; |
2408 | for (j = i - 1; j >= 0; j--) { |
2409 | if (athn_rates[an->ridx[j]].phy == |
2410 | athn_rates[an->ridx[i]].phy) { |
2411 | an->fallback[i] = j; |
2412 | break; |
2413 | } |
2414 | } |
2415 | DPRINTFN(DBG_STM, sc, "%d fallbacks to %d\n" , |
2416 | i, an->fallback[i]); |
2417 | } |
2418 | } |
2419 | |
2420 | Static int |
2421 | athn_media_change(struct ifnet *ifp) |
2422 | { |
2423 | struct athn_softc *sc = ifp->if_softc; |
2424 | struct ieee80211com *ic = &sc->sc_ic; |
2425 | uint8_t rate, ridx; |
2426 | int error; |
2427 | |
2428 | error = ieee80211_media_change(ifp); |
2429 | if (error != ENETRESET) |
2430 | return error; |
2431 | |
2432 | if (ic->ic_fixed_rate != -1) { |
2433 | rate = ic->ic_sup_rates[ic->ic_curmode]. |
2434 | rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; |
2435 | /* Map 802.11 rate to HW rate index. */ |
2436 | for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) |
2437 | if (athn_rates[ridx].rate == rate) |
2438 | break; |
2439 | sc->sc_fixed_ridx = ridx; |
2440 | } |
2441 | if (IS_UP_AND_RUNNING(ifp)) { |
2442 | athn_stop(ifp, 0); |
2443 | error = athn_init(ifp); |
2444 | } |
2445 | return error; |
2446 | } |
2447 | |
2448 | Static void |
2449 | athn_next_scan(void *arg) |
2450 | { |
2451 | struct athn_softc *sc = arg; |
2452 | struct ieee80211com *ic = &sc->sc_ic; |
2453 | int s; |
2454 | |
2455 | s = splnet(); |
2456 | if (ic->ic_state == IEEE80211_S_SCAN) |
2457 | ieee80211_next_scan(ic); |
2458 | splx(s); |
2459 | } |
2460 | |
2461 | Static int |
2462 | athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) |
2463 | { |
2464 | struct ifnet *ifp = ic->ic_ifp; |
2465 | struct athn_softc *sc = ifp->if_softc; |
2466 | uint32_t reg; |
2467 | int error; |
2468 | |
2469 | callout_stop(&sc->sc_calib_to); |
2470 | |
2471 | switch (nstate) { |
2472 | case IEEE80211_S_INIT: |
2473 | athn_set_led(sc, 0); |
2474 | break; |
2475 | case IEEE80211_S_SCAN: |
2476 | /* Make the LED blink while scanning. */ |
2477 | athn_set_led(sc, !sc->sc_led_state); |
2478 | error = athn_switch_chan(sc, ic->ic_curchan, NULL); |
2479 | if (error != 0) |
2480 | return error; |
2481 | callout_schedule(&sc->sc_scan_to, hz / 5); |
2482 | break; |
2483 | case IEEE80211_S_AUTH: |
2484 | athn_set_led(sc, 0); |
2485 | error = athn_switch_chan(sc, ic->ic_curchan, NULL); |
2486 | if (error != 0) |
2487 | return error; |
2488 | break; |
2489 | case IEEE80211_S_ASSOC: |
2490 | break; |
2491 | case IEEE80211_S_RUN: |
2492 | athn_set_led(sc, 1); |
2493 | |
2494 | if (ic->ic_opmode == IEEE80211_M_MONITOR) |
2495 | break; |
2496 | |
2497 | /* Fake a join to initialize the Tx rate. */ |
2498 | athn_newassoc(ic->ic_bss, 1); |
2499 | |
2500 | athn_set_bss(sc, ic->ic_bss); |
2501 | athn_disable_interrupts(sc); |
2502 | #ifndef IEEE80211_STA_ONLY |
2503 | if (ic->ic_opmode == IEEE80211_M_HOSTAP) { |
2504 | athn_set_hostap_timers(sc); |
2505 | /* Enable software beacon alert interrupts. */ |
2506 | sc->sc_imask |= AR_IMR_SWBA; |
2507 | } |
2508 | else |
2509 | #endif |
2510 | { |
2511 | athn_set_sta_timers(sc); |
2512 | /* Enable beacon miss interrupts. */ |
2513 | sc->sc_imask |= AR_IMR_BMISS; |
2514 | |
2515 | /* Stop receiving beacons from other BSS. */ |
2516 | reg = AR_READ(sc, AR_RX_FILTER); |
2517 | reg = (reg & ~AR_RX_FILTER_BEACON) | |
2518 | AR_RX_FILTER_MYBEACON; |
2519 | AR_WRITE(sc, AR_RX_FILTER, reg); |
2520 | AR_WRITE_BARRIER(sc); |
2521 | } |
2522 | athn_enable_interrupts(sc); |
2523 | |
2524 | if (sc->sc_sup_calib_mask != 0) { |
2525 | memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); |
2526 | sc->sc_cur_calib_mask = sc->sc_sup_calib_mask; |
2527 | /* ops->do_calib(sc); */ |
2528 | } |
2529 | /* XXX Start ANI. */ |
2530 | |
2531 | callout_schedule(&sc->sc_calib_to, hz / 2); |
2532 | break; |
2533 | } |
2534 | |
2535 | return sc->sc_newstate(ic, nstate, arg); |
2536 | } |
2537 | |
2538 | #ifdef notyet_edca |
2539 | PUBLIC void |
2540 | athn_updateedca(struct ieee80211com *ic) |
2541 | { |
2542 | #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ |
2543 | struct athn_softc *sc = ic->ic_ifp->if_softc; |
2544 | const struct ieee80211_edca_ac_params *ac; |
2545 | int aci, qid; |
2546 | |
2547 | for (aci = 0; aci < EDCA_NUM_AC; aci++) { |
2548 | ac = &ic->ic_edca_ac[aci]; |
2549 | qid = athn_ac2qid[aci]; |
2550 | |
2551 | AR_WRITE(sc, AR_DLCL_IFS(qid), |
2552 | SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) | |
2553 | SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) | |
2554 | SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn)); |
2555 | if (ac->ac_txoplimit != 0) { |
2556 | AR_WRITE(sc, AR_DCHNTIME(qid), |
2557 | SM(AR_D_CHNTIME_DUR, |
2558 | IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) | |
2559 | AR_D_CHNTIME_EN); |
2560 | } |
2561 | else |
2562 | AR_WRITE(sc, AR_DCHNTIME(qid), 0); |
2563 | } |
2564 | AR_WRITE_BARRIER(sc); |
2565 | #undef ATHN_EXP2 |
2566 | } |
2567 | #endif /* notyet_edca */ |
2568 | |
2569 | Static int |
2570 | athn_clock_rate(struct athn_softc *sc) |
2571 | { |
2572 | struct ieee80211com *ic = &sc->sc_ic; |
2573 | int clockrate; /* MHz. */ |
2574 | |
2575 | if (ic->ic_curmode == IEEE80211_MODE_11A) { |
2576 | if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) |
2577 | clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM; |
2578 | else |
2579 | clockrate = AR_CLOCK_RATE_5GHZ_OFDM; |
2580 | } |
2581 | else if (ic->ic_curmode == IEEE80211_MODE_11B) { |
2582 | clockrate = AR_CLOCK_RATE_CCK; |
2583 | } |
2584 | else |
2585 | clockrate = AR_CLOCK_RATE_2GHZ_OFDM; |
2586 | #ifndef IEEE80211_NO_HT |
2587 | if (sc->sc_curchanext != NULL) |
2588 | clockrate *= 2; |
2589 | #endif |
2590 | return clockrate; |
2591 | } |
2592 | |
2593 | PUBLIC void |
2594 | athn_updateslot(struct ifnet *ifp) |
2595 | { |
2596 | struct athn_softc *sc = ifp->if_softc; |
2597 | struct ieee80211com *ic = &sc->sc_ic; |
2598 | int slot; |
2599 | |
2600 | slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; |
2601 | AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc)); |
2602 | AR_WRITE_BARRIER(sc); |
2603 | } |
2604 | |
2605 | Static void |
2606 | athn_start(struct ifnet *ifp) |
2607 | { |
2608 | struct athn_softc *sc = ifp->if_softc; |
2609 | struct ieee80211com *ic = &sc->sc_ic; |
2610 | struct ether_header *eh; |
2611 | struct ieee80211_node *ni; |
2612 | struct mbuf *m; |
2613 | |
2614 | if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING |
2615 | || !device_is_active(sc->sc_dev)) |
2616 | return; |
2617 | |
2618 | for (;;) { |
2619 | if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) { |
2620 | ifp->if_flags |= IFF_OACTIVE; |
2621 | break; |
2622 | } |
2623 | /* Send pending management frames first. */ |
2624 | IF_DEQUEUE(&ic->ic_mgtq, m); |
2625 | if (m != NULL) { |
2626 | ni = M_GETCTX(m, struct ieee80211_node *); |
2627 | goto sendit; |
2628 | } |
2629 | if (ic->ic_state != IEEE80211_S_RUN) |
2630 | break; |
2631 | |
2632 | /* Encapsulate and send data frames. */ |
2633 | IFQ_DEQUEUE(&ifp->if_snd, m); |
2634 | if (m == NULL) |
2635 | break; |
2636 | |
2637 | if (m->m_len < (int)sizeof(*eh) && |
2638 | (m = m_pullup(m, sizeof(*eh))) == NULL) { |
2639 | ifp->if_oerrors++; |
2640 | continue; |
2641 | } |
2642 | eh = mtod(m, struct ether_header *); |
2643 | ni = ieee80211_find_txnode(ic, eh->ether_dhost); |
2644 | if (ni == NULL) { |
2645 | m_freem(m); |
2646 | ifp->if_oerrors++; |
2647 | continue; |
2648 | } |
2649 | |
2650 | bpf_mtap(ifp, m); |
2651 | |
2652 | if ((m = ieee80211_encap(ic, m, ni)) == NULL) |
2653 | continue; |
2654 | sendit: |
2655 | bpf_mtap3(ic->ic_rawbpf, m); |
2656 | |
2657 | if (sc->sc_ops.tx(sc, m, ni, 0) != 0) { |
2658 | ieee80211_free_node(ni); |
2659 | ifp->if_oerrors++; |
2660 | continue; |
2661 | } |
2662 | |
2663 | sc->sc_tx_timer = 5; |
2664 | ifp->if_timer = 1; |
2665 | } |
2666 | } |
2667 | |
2668 | Static void |
2669 | athn_watchdog(struct ifnet *ifp) |
2670 | { |
2671 | struct athn_softc *sc = ifp->if_softc; |
2672 | |
2673 | ifp->if_timer = 0; |
2674 | |
2675 | if (sc->sc_tx_timer > 0) { |
2676 | if (--sc->sc_tx_timer == 0) { |
2677 | aprint_error_dev(sc->sc_dev, "device timeout\n" ); |
2678 | /* see athn_init, no need to call athn_stop here */ |
2679 | /* athn_stop(ifp, 0); */ |
2680 | (void)athn_init(ifp); |
2681 | ifp->if_oerrors++; |
2682 | return; |
2683 | } |
2684 | ifp->if_timer = 1; |
2685 | } |
2686 | ieee80211_watchdog(&sc->sc_ic); |
2687 | } |
2688 | |
2689 | #ifdef notyet |
2690 | Static void |
2691 | athn_set_multi(struct athn_softc *sc) |
2692 | { |
2693 | struct arpcom *ac = &sc->sc_ic.ic_ac; |
2694 | struct ifnet *ifp = &ac->ac_if; |
2695 | struct ether_multi *enm; |
2696 | struct ether_multistep step; |
2697 | const uint8_t *addr; |
2698 | uint32_t val, lo, hi; |
2699 | uint8_t bit; |
2700 | |
2701 | if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { |
2702 | lo = hi = 0xffffffff; |
2703 | goto done; |
2704 | } |
2705 | lo = hi = 0; |
2706 | ETHER_FIRST_MULTI(step, ac, enm); |
2707 | while (enm != NULL) { |
2708 | if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { |
2709 | ifp->if_flags |= IFF_ALLMULTI; |
2710 | lo = hi = 0xffffffff; |
2711 | goto done; |
2712 | } |
2713 | addr = enm->enm_addrlo; |
2714 | /* Calculate the XOR value of all eight 6-bit words. */ |
2715 | val = addr[0] | addr[1] << 8 | addr[2] << 16; |
2716 | bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; |
2717 | val = addr[3] | addr[4] << 8 | addr[5] << 16; |
2718 | bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; |
2719 | bit &= 0x3f; |
2720 | if (bit < 32) |
2721 | lo |= 1 << bit; |
2722 | else |
2723 | hi |= 1 << (bit - 32); |
2724 | ETHER_NEXT_MULTI(step, enm); |
2725 | } |
2726 | done: |
2727 | AR_WRITE(sc, AR_MCAST_FIL0, lo); |
2728 | AR_WRITE(sc, AR_MCAST_FIL1, hi); |
2729 | AR_WRITE_BARRIER(sc); |
2730 | } |
2731 | #endif /* notyet */ |
2732 | |
2733 | Static int |
2734 | athn_ioctl(struct ifnet *ifp, u_long cmd, void *data) |
2735 | { |
2736 | struct athn_softc *sc = ifp->if_softc; |
2737 | struct ieee80211com *ic = &sc->sc_ic; |
2738 | int s, error = 0; |
2739 | |
2740 | s = splnet(); |
2741 | |
2742 | switch (cmd) { |
2743 | case SIOCSIFFLAGS: |
2744 | if ((error = ifioctl_common(ifp, cmd, data)) != 0) |
2745 | break; |
2746 | |
2747 | switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { |
2748 | case IFF_UP | IFF_RUNNING: |
2749 | #ifdef notyet |
2750 | if (((ifp->if_flags ^ sc->sc_if_flags) & |
2751 | (IFF_ALLMULTI | IFF_PROMISC)) != 0) |
2752 | /* XXX: setup multi */ |
2753 | #endif |
2754 | break; |
2755 | case IFF_UP: |
2756 | athn_init(ifp); |
2757 | break; |
2758 | |
2759 | case IFF_RUNNING: |
2760 | athn_stop(ifp, 1); |
2761 | break; |
2762 | case 0: |
2763 | default: |
2764 | break; |
2765 | } |
2766 | sc->sc_if_flags = ifp->if_flags; |
2767 | break; |
2768 | |
2769 | case SIOCADDMULTI: |
2770 | case SIOCDELMULTI: |
2771 | if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { |
2772 | /* setup multicast filter, etc */ |
2773 | #ifdef notyet |
2774 | athn_set_multi(sc); |
2775 | #endif |
2776 | error = 0; |
2777 | } |
2778 | break; |
2779 | |
2780 | case SIOCS80211CHANNEL: |
2781 | error = ieee80211_ioctl(ic, cmd, data); |
2782 | if (error == ENETRESET && |
2783 | ic->ic_opmode == IEEE80211_M_MONITOR) { |
2784 | if (IS_UP_AND_RUNNING(ifp)) |
2785 | athn_switch_chan(sc, ic->ic_curchan, NULL); |
2786 | error = 0; |
2787 | } |
2788 | break; |
2789 | |
2790 | default: |
2791 | error = ieee80211_ioctl(ic, cmd, data); |
2792 | } |
2793 | |
2794 | if (error == ENETRESET) { |
2795 | error = 0; |
2796 | if (IS_UP_AND_RUNNING(ifp) && |
2797 | ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { |
2798 | athn_stop(ifp, 0); |
2799 | error = athn_init(ifp); |
2800 | } |
2801 | } |
2802 | |
2803 | splx(s); |
2804 | return error; |
2805 | } |
2806 | |
2807 | Static int |
2808 | athn_init(struct ifnet *ifp) |
2809 | { |
2810 | struct athn_softc *sc = ifp->if_softc; |
2811 | struct athn_ops *ops = &sc->sc_ops; |
2812 | struct ieee80211com *ic = &sc->sc_ic; |
2813 | struct ieee80211_channel *curchan, *extchan; |
2814 | size_t i; |
2815 | int error; |
2816 | |
2817 | KASSERT(!cpu_intr_p()); |
2818 | |
2819 | if (device_is_active(sc->sc_dev)) { |
2820 | athn_stop(ifp, 0); /* see athn_watchdog() */ |
2821 | } else { |
2822 | short flags = ifp->if_flags; |
2823 | ifp->if_flags &= ~IFF_UP; |
2824 | /* avoid recursion in athn_resume */ |
2825 | if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || |
2826 | !device_is_active(sc->sc_dev)) { |
2827 | printf("%s: failed to power up device\n" , |
2828 | device_xname(sc->sc_dev)); |
2829 | return 0; |
2830 | } |
2831 | ifp->if_flags = flags; |
2832 | } |
2833 | |
2834 | curchan = ic->ic_curchan; |
2835 | extchan = NULL; |
2836 | |
2837 | /* In case a new MAC address has been configured. */ |
2838 | IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); |
2839 | |
2840 | #ifdef openbsd_power_management |
2841 | /* For CardBus, power on the socket. */ |
2842 | if (sc->sc_enable != NULL) { |
2843 | if ((error = sc->sc_enable(sc)) != 0) { |
2844 | aprint_error_dev(sc->sc_dev, |
2845 | "could not enable device\n" ); |
2846 | goto fail; |
2847 | } |
2848 | if ((error = athn_reset_power_on(sc)) != 0) { |
2849 | aprint_error_dev(sc->sc_dev, |
2850 | "could not power on device\n" ); |
2851 | goto fail; |
2852 | } |
2853 | } |
2854 | #endif |
2855 | if (!(sc->sc_flags & ATHN_FLAG_PCIE)) |
2856 | athn_config_nonpcie(sc); |
2857 | else |
2858 | athn_config_pcie(sc); |
2859 | |
2860 | /* Reset HW key cache entries. */ |
2861 | for (i = 0; i < sc->sc_kc_entries; i++) |
2862 | athn_reset_key(sc, i); |
2863 | |
2864 | ops->enable_antenna_diversity(sc); |
2865 | |
2866 | #ifdef ATHN_BT_COEXISTENCE |
2867 | /* Configure bluetooth coexistence for combo chips. */ |
2868 | if (sc->sc_flags & ATHN_FLAG_BTCOEX) |
2869 | athn_btcoex_init(sc); |
2870 | #endif |
2871 | |
2872 | /* Configure LED. */ |
2873 | athn_led_init(sc); |
2874 | |
2875 | /* Configure hardware radio switch. */ |
2876 | if (sc->sc_flags & ATHN_FLAG_RFSILENT) |
2877 | ops->rfsilent_init(sc); |
2878 | |
2879 | if ((error = athn_hw_reset(sc, curchan, extchan, 1)) != 0) { |
2880 | aprint_error_dev(sc->sc_dev, |
2881 | "unable to reset hardware; reset status %d\n" , error); |
2882 | goto fail; |
2883 | } |
2884 | |
2885 | /* Enable Rx. */ |
2886 | athn_rx_start(sc); |
2887 | |
2888 | /* Enable interrupts. */ |
2889 | athn_enable_interrupts(sc); |
2890 | |
2891 | #ifdef ATHN_BT_COEXISTENCE |
2892 | /* Enable bluetooth coexistence for combo chips. */ |
2893 | if (sc->sc_flags & ATHN_FLAG_BTCOEX) |
2894 | athn_btcoex_enable(sc); |
2895 | #endif |
2896 | |
2897 | ifp->if_flags &= ~IFF_OACTIVE; |
2898 | ifp->if_flags |= IFF_RUNNING; |
2899 | |
2900 | #ifdef notyet |
2901 | if (ic->ic_flags & IEEE80211_F_WEPON) { |
2902 | /* Configure WEP keys. */ |
2903 | for (i = 0; i < IEEE80211_WEP_NKID; i++) |
2904 | athn_set_key(ic, NULL, &ic->ic_nw_keys[i]); |
2905 | } |
2906 | #endif |
2907 | if (ic->ic_opmode == IEEE80211_M_MONITOR) |
2908 | ieee80211_new_state(ic, IEEE80211_S_RUN, -1); |
2909 | else |
2910 | ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); |
2911 | |
2912 | return 0; |
2913 | fail: |
2914 | athn_stop(ifp, 1); |
2915 | return error; |
2916 | } |
2917 | |
2918 | PUBLIC void |
2919 | athn_stop(struct ifnet *ifp, int disable) |
2920 | { |
2921 | struct athn_softc *sc = ifp->if_softc; |
2922 | struct ieee80211com *ic = &sc->sc_ic; |
2923 | int qid; |
2924 | |
2925 | ifp->if_timer = sc->sc_tx_timer = 0; |
2926 | ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); |
2927 | |
2928 | callout_stop(&sc->sc_scan_to); |
2929 | /* In case we were scanning, release the scan "lock". */ |
2930 | // ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; /* XXX:??? */ |
2931 | |
2932 | ieee80211_new_state(ic, IEEE80211_S_INIT, -1); |
2933 | |
2934 | #ifdef ATHN_BT_COEXISTENCE |
2935 | /* Disable bluetooth coexistence for combo chips. */ |
2936 | if (sc->sc_flags & ATHN_FLAG_BTCOEX) |
2937 | athn_btcoex_disable(sc); |
2938 | #endif |
2939 | |
2940 | /* Disable interrupts. */ |
2941 | athn_disable_interrupts(sc); |
2942 | /* Acknowledge interrupts (avoids interrupt storms). */ |
2943 | AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); |
2944 | AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); |
2945 | |
2946 | for (qid = 0; qid < ATHN_QID_COUNT; qid++) |
2947 | athn_stop_tx_dma(sc, qid); |
2948 | /* XXX call athn_hw_reset if Tx still pending? */ |
2949 | for (qid = 0; qid < ATHN_QID_COUNT; qid++) |
2950 | athn_tx_reclaim(sc, qid); |
2951 | |
2952 | /* Stop Rx. */ |
2953 | AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); |
2954 | AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); |
2955 | AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); |
2956 | AR_WRITE(sc, AR_FILT_OFDM, 0); |
2957 | AR_WRITE(sc, AR_FILT_CCK, 0); |
2958 | AR_WRITE_BARRIER(sc); |
2959 | athn_set_rxfilter(sc, 0); |
2960 | athn_stop_rx_dma(sc); |
2961 | |
2962 | athn_reset(sc, 0); |
2963 | athn_init_pll(sc, NULL); |
2964 | athn_set_power_awake(sc); |
2965 | athn_reset(sc, 1); |
2966 | athn_init_pll(sc, NULL); |
2967 | |
2968 | athn_set_power_sleep(sc); |
2969 | |
2970 | #if 0 /* XXX: shouldn't the pmf stuff take care of this? */ |
2971 | /* For CardBus, power down the socket. */ |
2972 | if (disable && sc->sc_disable != NULL) |
2973 | sc->sc_disable(sc); |
2974 | #endif |
2975 | if (disable) |
2976 | pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); |
2977 | } |
2978 | |
2979 | Static void |
2980 | athn_pmf_wlan_off(device_t self) |
2981 | { |
2982 | struct athn_softc *sc = device_private(self); |
2983 | struct ifnet *ifp = &sc->sc_if; |
2984 | |
2985 | /* Turn the interface down. */ |
2986 | ifp->if_flags &= ~IFF_UP; |
2987 | athn_stop(ifp, 1); |
2988 | } |
2989 | |
2990 | PUBLIC void |
2991 | athn_suspend(struct athn_softc *sc) |
2992 | { |
2993 | struct ifnet *ifp = &sc->sc_if; |
2994 | |
2995 | if (ifp->if_flags & IFF_RUNNING) |
2996 | athn_stop(ifp, 1); |
2997 | } |
2998 | |
2999 | PUBLIC bool |
3000 | athn_resume(struct athn_softc *sc) |
3001 | { |
3002 | struct ifnet *ifp = &sc->sc_if; |
3003 | |
3004 | if (ifp->if_flags & IFF_UP) |
3005 | athn_init(ifp); |
3006 | |
3007 | return true; |
3008 | } |
3009 | |