1 | /* $NetBSD: if_rtwnreg.h,v 1.2 2015/11/06 14:22:17 nonaka Exp $ */ |
2 | /* $OpenBSD: if_rtwnreg.h,v 1.3 2015/06/14 08:02:47 stsp Exp $ */ |
3 | |
4 | /*- |
5 | * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> |
6 | * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> |
7 | * |
8 | * Permission to use, copy, modify, and distribute this software for any |
9 | * purpose with or without fee is hereby granted, provided that the above |
10 | * copyright notice and this permission notice appear in all copies. |
11 | * |
12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
19 | */ |
20 | |
21 | #define R92C_MAX_CHAINS 2 |
22 | |
23 | /* Maximum number of output pipes is 3. */ |
24 | #define R92C_MAX_EPOUT 3 |
25 | |
26 | #define R92C_MAX_TX_PWR 0x3f |
27 | |
28 | #define R92C_PUBQ_NPAGES 176 |
29 | #define R92C_HPQ_NPAGES 41 |
30 | #define R92C_LPQ_NPAGES 28 |
31 | #define R92C_TXPKTBUF_COUNT 256 |
32 | #define R92C_TX_PAGE_COUNT \ |
33 | (R92C_PUBQ_NPAGES + R92C_HPQ_NPAGES + R92C_LPQ_NPAGES) |
34 | #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) |
35 | |
36 | #define R92C_H2C_NBOX 4 |
37 | |
38 | /* USB Requests. */ |
39 | #define R92C_REQ_REGS 0x05 |
40 | |
41 | /* |
42 | * MAC registers. |
43 | */ |
44 | /* System Configuration. */ |
45 | #define R92C_SYS_ISO_CTRL 0x000 |
46 | #define R92C_SYS_FUNC_EN 0x002 |
47 | #define R92C_APS_FSMCO 0x004 |
48 | #define R92C_SYS_CLKR 0x008 |
49 | #define R92C_AFE_MISC 0x010 |
50 | #define R92C_SPS0_CTRL 0x011 |
51 | #define R92C_SPS_OCP_CFG 0x018 |
52 | #define R92C_RSV_CTRL 0x01c |
53 | #define R92C_RF_CTRL 0x01f |
54 | #define R92C_LDOA15_CTRL 0x020 |
55 | #define R92C_LDOV12D_CTRL 0x021 |
56 | #define R92C_LDOHCI12_CTRL 0x022 |
57 | #define R92C_LPLDO_CTRL 0x023 |
58 | #define R92C_AFE_XTAL_CTRL 0x024 |
59 | #define R92C_AFE_PLL_CTRL 0x028 |
60 | #define R92C_EFUSE_CTRL 0x030 |
61 | #define R92C_EFUSE_TEST 0x034 |
62 | #define R92C_PWR_DATA 0x038 |
63 | #define R92C_CAL_TIMER 0x03c |
64 | #define R92C_ACLK_MON 0x03e |
65 | #define R92C_GPIO_MUXCFG 0x040 |
66 | #define R92C_GPIO_IO_SEL 0x042 |
67 | #define R92C_MAC_PINMUX_CFG 0x043 |
68 | #define R92C_GPIO_PIN_CTRL 0x044 |
69 | #define R92C_GPIO_INTM 0x048 |
70 | #define R92C_LEDCFG0 0x04c |
71 | #define R92C_LEDCFG1 0x04d |
72 | #define R92C_LEDCFG2 0x04e |
73 | #define R92C_LEDCFG3 0x04f |
74 | #define R92C_FSIMR 0x050 |
75 | #define R92C_FSISR 0x054 |
76 | #define R92C_HSIMR 0x058 |
77 | #define R92C_HSISR 0x05c |
78 | #define R92C_MCUFWDL 0x080 |
79 | #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) |
80 | #define R92C_BIST_SCAN 0x0d0 |
81 | #define R92C_BIST_RPT 0x0d4 |
82 | #define R92C_BIST_ROM_RPT 0x0d8 |
83 | #define R92C_USB_SIE_INTF 0x0e0 |
84 | #define R92C_PCIE_MIO_INTF 0x0e4 |
85 | #define R92C_PCIE_MIO_INTD 0x0e8 |
86 | #define R92C_HPON_FSM 0x0ec |
87 | #define R92C_SYS_CFG 0x0f0 |
88 | /* MAC General Configuration. */ |
89 | #define R92C_CR 0x100 |
90 | #define R92C_PBP 0x104 |
91 | #define R92C_TRXDMA_CTRL 0x10c |
92 | #define R92C_TRXFF_BNDY 0x114 |
93 | #define R92C_TRXFF_STATUS 0x118 |
94 | #define R92C_RXFF_PTR 0x11c |
95 | #define R92C_HIMR 0x120 |
96 | #define R92C_HISR 0x124 |
97 | #define R92C_HIMRE 0x128 |
98 | #define R92C_HISRE 0x12c |
99 | #define R92C_CPWM 0x12f |
100 | #define R92C_FWIMR 0x130 |
101 | #define R92C_FWISR 0x134 |
102 | #define R92C_PKTBUF_DBG_CTRL 0x140 |
103 | #define R92C_PKTBUF_DBG_DATA_L 0x144 |
104 | #define R92C_PKTBUF_DBG_DATA_H 0x148 |
105 | #define R92C_TC0_CTRL(i) (0x150 + (i) * 4) |
106 | #define R92C_TCUNIT_BASE 0x164 |
107 | #define R92C_MBIST_START 0x174 |
108 | #define R92C_MBIST_DONE 0x178 |
109 | #define R92C_MBIST_FAIL 0x17c |
110 | #define R92C_C2HEVT_MSG_NORMAL 0x1a0 |
111 | #define R92C_C2HEVT_MSG_TEST 0x1b8 |
112 | #define R92C_C2HEVT_CLEAR 0x1bf |
113 | #define R92C_MCUTST_1 0x1c0 |
114 | #define R92C_FMETHR 0x1c8 |
115 | #define R92C_HMETFR 0x1cc |
116 | #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) |
117 | #define R92C_LLT_INIT 0x1e0 |
118 | #define R92C_BB_ACCESS_CTRL 0x1e8 |
119 | #define R92C_BB_ACCESS_DATA 0x1ec |
120 | /* Tx DMA Configuration. */ |
121 | #define R92C_RQPN 0x200 |
122 | #define R92C_FIFOPAGE 0x204 |
123 | #define R92C_TDECTRL 0x208 |
124 | #define R92C_TXDMA_OFFSET_CHK 0x20c |
125 | #define R92C_TXDMA_STATUS 0x210 |
126 | #define R92C_RQPN_NPQ 0x214 |
127 | /* Rx DMA Configuration. */ |
128 | #define R92C_RXDMA_AGG_PG_TH 0x280 |
129 | #define R92C_RXPKT_NUM 0x284 |
130 | #define R92C_RXDMA_STATUS 0x288 |
131 | |
132 | #define R92C_PCIE_CTRL_REG 0x300 |
133 | #define R92C_INT_MIG 0x304 |
134 | #define R92C_BCNQ_DESA 0x308 |
135 | #define R92C_HQ_DESA 0x310 |
136 | #define R92C_MGQ_DESA 0x318 |
137 | #define R92C_VOQ_DESA 0x320 |
138 | #define R92C_VIQ_DESA 0x328 |
139 | #define R92C_BEQ_DESA 0x330 |
140 | #define R92C_BKQ_DESA 0x338 |
141 | #define R92C_RX_DESA 0x340 |
142 | #define R92C_DBI 0x348 |
143 | #define R92C_MDIO 0x354 |
144 | #define R92C_DBG_SEL 0x360 |
145 | #define R92C_PCIE_HRPWM 0x361 |
146 | #define R92C_PCIE_HCPWM 0x363 |
147 | #define R92C_UART_CTRL 0x364 |
148 | #define R92C_UART_TX_DES 0x370 |
149 | #define R92C_UART_RX_DES 0x378 |
150 | |
151 | #define R92C_VOQ_INFORMATION 0x0400 |
152 | #define R92C_VIQ_INFORMATION 0x0404 |
153 | #define R92C_BEQ_INFORMATION 0x0408 |
154 | #define R92C_BKQ_INFORMATION 0x040C |
155 | #define R92C_MGQ_INFORMATION 0x0410 |
156 | #define R92C_HGQ_INFORMATION 0x0414 |
157 | #define R92C_BCNQ_INFORMATION 0x0418 |
158 | #define R92C_CPU_MGQ_INFORMATION 0x041C |
159 | |
160 | /* Protocol Configuration. */ |
161 | #define R92C_FWHW_TXQ_CTRL 0x420 |
162 | #define R92C_HWSEQ_CTRL 0x423 |
163 | #define R92C_TXPKTBUF_BCNQ_BDNY 0x424 |
164 | #define R92C_TXPKTBUF_MGQ_BDNY 0x425 |
165 | #define R92C_SPEC_SIFS 0x428 |
166 | #define R92C_RL 0x42a |
167 | #define R92C_DARFRC 0x430 |
168 | #define R92C_RARFRC 0x438 |
169 | #define R92C_RRSR 0x440 |
170 | #define R92C_ARFR(i) (0x444 + (i) * 4) |
171 | #define R92C_AGGLEN_LMT 0x458 |
172 | #define R92C_AMPDU_MIN_SPACE 0x45c |
173 | #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d |
174 | #define R92C_FAST_EDCA_CTRL 0x460 |
175 | #define R92C_RD_RESP_PKT_TH 0x463 |
176 | #define R92C_INIRTS_RATE_SEL 0x480 |
177 | #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) |
178 | /* EDCA Configuration. */ |
179 | #define R92C_EDCA_VO_PARAM 0x500 |
180 | #define R92C_EDCA_VI_PARAM 0x504 |
181 | #define R92C_EDCA_BE_PARAM 0x508 |
182 | #define R92C_EDCA_BK_PARAM 0x50c |
183 | #define R92C_BCNTCFG 0x510 |
184 | #define R92C_PIFS 0x512 |
185 | #define R92C_RDG_PIFS 0x513 |
186 | #define R92C_SIFS_CCK 0x514 |
187 | #define R92C_SIFS_OFDM 0x516 |
188 | #define R92C_AGGR_BREAK_TIME 0x51a |
189 | #define R92C_SLOT 0x51b |
190 | #define R92C_TX_PTCL_CTRL 0x520 |
191 | #define R92C_TXPAUSE 0x522 |
192 | #define R92C_DIS_TXREQ_CLR 0x523 |
193 | #define R92C_RD_CTRL 0x524 |
194 | #define R92C_TBTT_PROHIBIT 0x540 |
195 | #define R92C_RD_NAV_NXT 0x544 |
196 | #define R92C_NAV_PROT_LEN 0x546 |
197 | #define R92C_BCN_CTRL 0x550 |
198 | #define R92C_USTIME_TSF 0x551 |
199 | #define R92C_MBID_NUM 0x552 |
200 | #define R92C_DUAL_TSF_RST 0x553 |
201 | #define R92C_BCN_INTERVAL 0x554 |
202 | #define R92C_DRVERLYINT 0x558 |
203 | #define R92C_BCNDMATIM 0x559 |
204 | #define R92C_ATIMWND 0x55a |
205 | #define R92C_BCN_MAX_ERR 0x55d |
206 | #define R92C_RXTSF_OFFSET_CCK 0x55e |
207 | #define R92C_RXTSF_OFFSET_OFDM 0x55f |
208 | #define R92C_TSFTR 0x560 |
209 | #define R92C_INIT_TSFTR 0x564 |
210 | #define R92C_PSTIMER 0x580 |
211 | #define R92C_TIMER0 0x584 |
212 | #define R92C_TIMER1 0x588 |
213 | #define R92C_ACMHWCTRL 0x5c0 |
214 | #define R92C_ACMRSTCTRL 0x5c1 |
215 | #define R92C_ACMAVG 0x5c2 |
216 | #define R92C_VO_ADMTIME 0x5c4 |
217 | #define R92C_VI_ADMTIME 0x5c6 |
218 | #define R92C_BE_ADMTIME 0x5c8 |
219 | #define R92C_EDCA_RANDOM_GEN 0x5cc |
220 | #define R92C_SCH_TXCMD 0x5d0 |
221 | /* WMAC Configuration. */ |
222 | #define R92C_APSD_CTRL 0x600 |
223 | #define R92C_BWOPMODE 0x603 |
224 | #define R92C_TCR 0x604 |
225 | #define R92C_RCR 0x608 |
226 | #define R92C_RX_DRVINFO_SZ 0x60f |
227 | #define R92C_MACID 0x610 |
228 | #define R92C_BSSID 0x618 |
229 | #define R92C_MAR 0x620 |
230 | #define R92C_MAC_SPEC_SIFS 0x63a |
231 | #define R92C_R2T_SIFS 0x63c |
232 | #define R92C_T2T_SIFS 0x63e |
233 | #define R92C_ACKTO 0x640 |
234 | #define R92C_CAMCMD 0x670 |
235 | #define R92C_CAMWRITE 0x674 |
236 | #define R92C_CAMREAD 0x678 |
237 | #define R92C_CAMDBG 0x67c |
238 | #define R92C_SECCFG 0x680 |
239 | #define R92C_RXFLTMAP0 0x6a0 |
240 | #define R92C_RXFLTMAP1 0x6a2 |
241 | #define R92C_RXFLTMAP2 0x6a4 |
242 | |
243 | /* Bits for R92C_SYS_ISO_CTRL. */ |
244 | #define R92C_SYS_ISO_CTRL_MD2PP 0x0001 |
245 | #define R92C_SYS_ISO_CTRL_UA2USB 0x0002 |
246 | #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 |
247 | #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 |
248 | #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 |
249 | #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 |
250 | #define R92C_SYS_ISO_CTRL_DIOP 0x0040 |
251 | #define R92C_SYS_ISO_CTRL_DIOE 0x0080 |
252 | #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 |
253 | #define R92C_SYS_ISO_CTRL_DIOR 0x0200 |
254 | #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 |
255 | #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 |
256 | |
257 | /* Bits for R92C_SYS_FUNC_EN. */ |
258 | #define R92C_SYS_FUNC_EN_BBRSTB 0x0001 |
259 | #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 |
260 | #define R92C_SYS_FUNC_EN_USBA 0x0004 |
261 | #define R92C_SYS_FUNC_EN_UPLL 0x0008 |
262 | #define R92C_SYS_FUNC_EN_USBD 0x0010 |
263 | #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 |
264 | #define R92C_SYS_FUNC_EN_PCIEA 0x0040 |
265 | #define R92C_SYS_FUNC_EN_PPLL 0x0080 |
266 | #define R92C_SYS_FUNC_EN_PCIED 0x0100 |
267 | #define R92C_SYS_FUNC_EN_DIOE 0x0200 |
268 | #define R92C_SYS_FUNC_EN_CPUEN 0x0400 |
269 | #define R92C_SYS_FUNC_EN_DCORE 0x0800 |
270 | #define R92C_SYS_FUNC_EN_ELDR 0x1000 |
271 | #define R92C_SYS_FUNC_EN_DIO_RF 0x2000 |
272 | #define R92C_SYS_FUNC_EN_HWPDN 0x4000 |
273 | #define R92C_SYS_FUNC_EN_MREGEN 0x8000 |
274 | |
275 | /* Bits for R92C_APS_FSMCO. */ |
276 | #define R92C_APS_FSMCO_PFM_LDALL 0x00000001 |
277 | #define R92C_APS_FSMCO_PFM_ALDN 0x00000002 |
278 | #define R92C_APS_FSMCO_PFM_LDKP 0x00000004 |
279 | #define R92C_APS_FSMCO_PFM_WOWL 0x00000008 |
280 | #define R92C_APS_FSMCO_PDN_EN 0x00000010 |
281 | #define R92C_APS_FSMCO_PDN_PL 0x00000020 |
282 | #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 |
283 | #define R92C_APS_FSMCO_APFM_OFF 0x00000200 |
284 | #define R92C_APS_FSMCO_APFM_RSM 0x00000400 |
285 | #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 |
286 | #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 |
287 | #define R92C_APS_FSMCO_APDM_MAC 0x00002000 |
288 | #define R92C_APS_FSMCO_APDM_HOST 0x00004000 |
289 | #define R92C_APS_FSMCO_APDM_HPDN 0x00008000 |
290 | #define R92C_APS_FSMCO_RDY_MACON 0x00010000 |
291 | #define R92C_APS_FSMCO_SUS_HOST 0x00020000 |
292 | #define R92C_APS_FSMCO_ROP_ALD 0x00100000 |
293 | #define R92C_APS_FSMCO_ROP_PWR 0x00200000 |
294 | #define R92C_APS_FSMCO_ROP_SPS 0x00400000 |
295 | #define R92C_APS_FSMCO_SOP_MRST 0x02000000 |
296 | #define R92C_APS_FSMCO_SOP_FUSE 0x04000000 |
297 | #define R92C_APS_FSMCO_SOP_ABG 0x08000000 |
298 | #define R92C_APS_FSMCO_SOP_AMB 0x10000000 |
299 | #define R92C_APS_FSMCO_SOP_RCK 0x20000000 |
300 | #define R92C_APS_FSMCO_SOP_A8M 0x40000000 |
301 | #define R92C_APS_FSMCO_XOP_BTCK 0x80000000 |
302 | |
303 | /* Bits for R92C_SYS_CLKR. */ |
304 | #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 |
305 | #define R92C_SYS_CLKR_ANA8M 0x00000002 |
306 | #define R92C_SYS_CLKR_MACSLP 0x00000010 |
307 | #define R92C_SYS_CLKR_LOADER_EN 0x00000020 |
308 | #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 |
309 | #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 |
310 | #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 |
311 | #define R92C_SYS_CLKR_SEC_EN 0x00000400 |
312 | #define R92C_SYS_CLKR_MAC_EN 0x00000800 |
313 | #define R92C_SYS_CLKR_SYS_EN 0x00001000 |
314 | #define R92C_SYS_CLKR_RING_EN 0x00002000 |
315 | |
316 | /* Bits for R92C_RF_CTRL. */ |
317 | #define R92C_RF_CTRL_EN 0x01 |
318 | #define R92C_RF_CTRL_RSTB 0x02 |
319 | #define R92C_RF_CTRL_SDMRSTB 0x04 |
320 | |
321 | /* Bits for R92C_LDOV12D_CTRL. */ |
322 | #define R92C_LDOV12D_CTRL_LDV12_EN 0x01 |
323 | |
324 | /* Bits for R92C_EFUSE_CTRL. */ |
325 | #define R92C_EFUSE_CTRL_DATA_M 0x000000ff |
326 | #define R92C_EFUSE_CTRL_DATA_S 0 |
327 | #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 |
328 | #define R92C_EFUSE_CTRL_ADDR_S 8 |
329 | #define R92C_EFUSE_CTRL_VALID 0x80000000 |
330 | |
331 | /* Bits for R92C_GPIO_MUXCFG. */ |
332 | #define R92C_GPIO_MUXCFG_RFKILL 0x0008 |
333 | #define R92C_GPIO_MUXCFG_ENBT 0x0020 |
334 | |
335 | /* Bits for R92C_GPIO_IO_SEL. */ |
336 | #define R92C_GPIO_IO_SEL_RFKILL 0x0008 |
337 | |
338 | /* Bits for R92C_LEDCFG0. */ |
339 | #define R92C_LEDCFG0_DIS 0x08 |
340 | |
341 | /* Bits for R92C_LEDCFG2. */ |
342 | #define R92C_LEDCFG2_EN 0x60 |
343 | #define R92C_LEDCFG2_DIS 0x68 |
344 | |
345 | /* Bits for R92C_MCUFWDL. */ |
346 | #define R92C_MCUFWDL_EN 0x00000001 |
347 | #define R92C_MCUFWDL_RDY 0x00000002 |
348 | #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 |
349 | #define R92C_MCUFWDL_MACINI_RDY 0x00000008 |
350 | #define R92C_MCUFWDL_BBINI_RDY 0x00000010 |
351 | #define R92C_MCUFWDL_RFINI_RDY 0x00000020 |
352 | #define R92C_MCUFWDL_WINTINI_RDY 0x00000040 |
353 | #define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 /* 1: RAM, 0: ROM */ |
354 | #define R92C_MCUFWDL_PAGE_M 0x00070000 |
355 | #define R92C_MCUFWDL_PAGE_S 16 |
356 | #define R92C_MCUFWDL_CPRST 0x00800000 |
357 | |
358 | /* Bits for R92C_HPON_FSM. */ |
359 | #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 |
360 | #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 |
361 | #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 |
362 | |
363 | /* Bits for R92C_SYS_CFG. */ |
364 | #define R92C_SYS_CFG_XCLK_VLD 0x00000001 |
365 | #define R92C_SYS_CFG_ACLK_VLD 0x00000002 |
366 | #define R92C_SYS_CFG_UCLK_VLD 0x00000004 |
367 | #define R92C_SYS_CFG_PCLK_VLD 0x00000008 |
368 | #define R92C_SYS_CFG_PCIRSTB 0x00000010 |
369 | #define R92C_SYS_CFG_V15_VLD 0x00000020 |
370 | #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 |
371 | #define R92C_SYS_CFG_SIC_IDLE 0x00000100 |
372 | #define R92C_SYS_CFG_BD_MAC2 0x00000200 |
373 | #define R92C_SYS_CFG_BD_MAC1 0x00000400 |
374 | #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 |
375 | #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 |
376 | #define R92C_SYS_CFG_CHIP_VER_RTL_S 12 |
377 | #define R92C_SYS_CFG_BT_FUNC 0x00010000 |
378 | #define R92C_SYS_CFG_VENDOR_UMC 0x00080000 |
379 | #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 |
380 | #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 |
381 | #define R92C_SYS_CFG_TRP_BT_EN 0x01000000 |
382 | #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 |
383 | #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 |
384 | #define R92C_SYS_CFG_TYPE_92C 0x08000000 |
385 | |
386 | /* Bits for R92C_CR. */ |
387 | #define R92C_CR_HCI_TXDMA_EN 0x00000001 |
388 | #define R92C_CR_HCI_RXDMA_EN 0x00000002 |
389 | #define R92C_CR_TXDMA_EN 0x00000004 |
390 | #define R92C_CR_RXDMA_EN 0x00000008 |
391 | #define R92C_CR_PROTOCOL_EN 0x00000010 |
392 | #define R92C_CR_SCHEDULE_EN 0x00000020 |
393 | #define R92C_CR_MACTXEN 0x00000040 |
394 | #define R92C_CR_MACRXEN 0x00000080 |
395 | #define R92C_CR_ENSEC 0x00000200 |
396 | #define R92C_CR_NETTYPE_S 16 |
397 | #define R92C_CR_NETTYPE_M 0x00030000 |
398 | #define R92C_CR_NETTYPE_NOLINK 0 |
399 | #define R92C_CR_NETTYPE_ADHOC 1 |
400 | #define R92C_CR_NETTYPE_INFRA 2 |
401 | #define R92C_CR_NETTYPE_AP 3 |
402 | |
403 | /* Bits for R92C_PBP. */ |
404 | #define R92C_PBP_PSRX_M 0x0f |
405 | #define R92C_PBP_PSRX_S 0 |
406 | #define R92C_PBP_PSTX_M 0xf0 |
407 | #define R92C_PBP_PSTX_S 4 |
408 | #define R92C_PBP_64 0 |
409 | #define R92C_PBP_128 1 |
410 | #define R92C_PBP_256 2 |
411 | #define R92C_PBP_512 3 |
412 | #define R92C_PBP_1024 4 |
413 | |
414 | /* Bits for R92C_TRXDMA_CTRL. */ |
415 | #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 |
416 | #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 |
417 | #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 |
418 | #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 |
419 | #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 |
420 | #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 |
421 | #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 |
422 | #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 |
423 | #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 |
424 | #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 |
425 | #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 |
426 | #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 |
427 | #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 |
428 | #define R92C_TRXDMA_CTRL_QUEUE_LOW 1 |
429 | #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 |
430 | #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 |
431 | #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 |
432 | #define R92C_TRXDMA_CTRL_QMAP_S 4 |
433 | /* Shortcuts. */ |
434 | #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 |
435 | #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 |
436 | #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 |
437 | #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 |
438 | #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 |
439 | #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 |
440 | |
441 | /* Bits for R92C_LLT_INIT. */ |
442 | #define R92C_LLT_INIT_DATA_M 0x000000ff |
443 | #define R92C_LLT_INIT_DATA_S 0 |
444 | #define R92C_LLT_INIT_ADDR_M 0x0000ff00 |
445 | #define R92C_LLT_INIT_ADDR_S 8 |
446 | #define R92C_LLT_INIT_OP_M 0xc0000000 |
447 | #define R92C_LLT_INIT_OP_S 30 |
448 | #define R92C_LLT_INIT_OP_NO_ACTIVE 0 |
449 | #define R92C_LLT_INIT_OP_WRITE 1 |
450 | |
451 | /* Bits for R92C_RQPN. */ |
452 | #define R92C_RQPN_HPQ_M 0x000000ff |
453 | #define R92C_RQPN_HPQ_S 0 |
454 | #define R92C_RQPN_LPQ_M 0x0000ff00 |
455 | #define R92C_RQPN_LPQ_S 8 |
456 | #define R92C_RQPN_PUBQ_M 0x00ff0000 |
457 | #define R92C_RQPN_PUBQ_S 16 |
458 | #define R92C_RQPN_LD 0x80000000 |
459 | |
460 | /* Bits for R92C_TDECTRL. */ |
461 | #define R92C_TDECTRL_BLK_DESC_NUM_M 0x0000000f |
462 | #define R92C_TDECTRL_BLK_DESC_NUM_S 4 |
463 | |
464 | /* Bits for R92C_FWHW_TXQ_CTRL. */ |
465 | #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 |
466 | |
467 | /* Bits for R92C_SPEC_SIFS. */ |
468 | #define R92C_SPEC_SIFS_CCK_M 0x00ff |
469 | #define R92C_SPEC_SIFS_CCK_S 0 |
470 | #define R92C_SPEC_SIFS_OFDM_M 0xff00 |
471 | #define R92C_SPEC_SIFS_OFDM_S 8 |
472 | |
473 | /* Bits for R92C_RL. */ |
474 | #define R92C_RL_LRL_M 0x003f |
475 | #define R92C_RL_LRL_S 0 |
476 | #define R92C_RL_SRL_M 0x3f00 |
477 | #define R92C_RL_SRL_S 8 |
478 | |
479 | /* Bits for R92C_RRSR. */ |
480 | #define R92C_RRSR_RATE_BITMAP_M 0x000fffff |
481 | #define R92C_RRSR_RATE_BITMAP_S 0 |
482 | #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 |
483 | #define R92C_RRSR_RATE_ALL 0xfffff |
484 | #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 |
485 | #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 |
486 | #define R92C_RRSR_SHORT 0x00800000 |
487 | |
488 | /* Bits for R92C_EDCA_XX_PARAM. */ |
489 | #define R92C_EDCA_PARAM_AIFS_M 0x000000ff |
490 | #define R92C_EDCA_PARAM_AIFS_S 0 |
491 | #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 |
492 | #define R92C_EDCA_PARAM_ECWMIN_S 8 |
493 | #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 |
494 | #define R92C_EDCA_PARAM_ECWMAX_S 12 |
495 | #define R92C_EDCA_PARAM_TXOP_M 0xffff0000 |
496 | #define R92C_EDCA_PARAM_TXOP_S 16 |
497 | |
498 | /* Bits for R92C_TXPAUSE. */ |
499 | #define R92C_TXPAUSE_AC_VO 0x01 |
500 | #define R92C_TXPAUSE_AC_VI 0x02 |
501 | #define R92C_TXPAUSE_AC_BE 0x04 |
502 | #define R92C_TXPAUSE_AC_BK 0x08 |
503 | |
504 | /* Bits for R92C_BCN_CTRL. */ |
505 | #define R92C_BCN_CTRL_EN_MBSSID 0x02 |
506 | #define R92C_BCN_CTRL_TXBCN_RPT 0x04 |
507 | #define R92C_BCN_CTRL_EN_BCN 0x08 |
508 | #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 |
509 | |
510 | /* Bits for R92C_APSD_CTRL. */ |
511 | #define R92C_APSD_CTRL_OFF 0x40 |
512 | #define R92C_APSD_CTRL_OFF_STATUS 0x80 |
513 | |
514 | /* Bits for R92C_BWOPMODE. */ |
515 | #define R92C_BWOPMODE_11J 0x01 |
516 | #define R92C_BWOPMODE_5G 0x02 |
517 | #define R92C_BWOPMODE_20MHZ 0x04 |
518 | |
519 | /* Bits for R92C_TCR. */ |
520 | #define R92C_TCR_TSFRST 0x00000001 |
521 | #define R92C_TCR_DIS_GCLK 0x00000002 |
522 | #define R92C_TCR_PAD_SEL 0x00000004 |
523 | #define R92C_TCR_PWR_ST 0x00000040 |
524 | #define R92C_TCR_PWRBIT_OW_EN 0x00000080 |
525 | #define R92C_TCR_ACRC 0x00000100 |
526 | #define R92C_TCR_CFENDFORM 0x00000200 |
527 | #define R92C_TCR_ICV 0x00000400 |
528 | |
529 | /* Bits for R92C_RCR. */ |
530 | #define R92C_RCR_AAP 0x00000001 |
531 | #define R92C_RCR_APM 0x00000002 |
532 | #define R92C_RCR_AM 0x00000004 |
533 | #define R92C_RCR_AB 0x00000008 |
534 | #define R92C_RCR_ADD3 0x00000010 |
535 | #define R92C_RCR_APWRMGT 0x00000020 |
536 | #define R92C_RCR_CBSSID_DATA 0x00000040 |
537 | #define R92C_RCR_CBSSID_BCN 0x00000080 |
538 | #define R92C_RCR_ACRC32 0x00000100 |
539 | #define R92C_RCR_AICV 0x00000200 |
540 | #define R92C_RCR_ADF 0x00000800 |
541 | #define R92C_RCR_ACF 0x00001000 |
542 | #define R92C_RCR_AMF 0x00002000 |
543 | #define R92C_RCR_HTC_LOC_CTRL 0x00004000 |
544 | #define R92C_RCR_MFBEN 0x00400000 |
545 | #define R92C_RCR_LSIGEN 0x00800000 |
546 | #define R92C_RCR_ENMBID 0x01000000 |
547 | #define R92C_RCR_APP_BA_SSN 0x08000000 |
548 | #define R92C_RCR_APP_PHYSTS 0x10000000 |
549 | #define R92C_RCR_APP_ICV 0x20000000 |
550 | #define R92C_RCR_APP_MIC 0x40000000 |
551 | #define R92C_RCR_APPFCS 0x80000000 |
552 | |
553 | /* Bits for R92C_CAMCMD. */ |
554 | #define R92C_CAMCMD_ADDR_M 0x0000ffff |
555 | #define R92C_CAMCMD_ADDR_S 0 |
556 | #define R92C_CAMCMD_WRITE 0x00010000 |
557 | #define R92C_CAMCMD_CLR 0x40000000 |
558 | #define R92C_CAMCMD_POLLING 0x80000000 |
559 | |
560 | /* IMR */ |
561 | |
562 | /*Beacon DMA interrupt 6 */ |
563 | #define R92C_IMR_BCNDMAINT6 0x80000000 |
564 | /*Beacon DMA interrupt 5 */ |
565 | #define R92C_IMR_BCNDMAINT5 0x40000000 |
566 | /*Beacon DMA interrupt 4 */ |
567 | #define R92C_IMR_BCNDMAINT4 0x20000000 |
568 | /*Beacon DMA interrupt 3 */ |
569 | #define R92C_IMR_BCNDMAINT3 0x10000000 |
570 | /*Beacon DMA interrupt 2 */ |
571 | #define R92C_IMR_BCNDMAINT2 0x08000000 |
572 | /*Beacon DMA interrupt 1 */ |
573 | #define R92C_IMR_BCNDMAINT1 0x04000000 |
574 | /*Beacon Queue DMA OK interrupt 8 */ |
575 | #define R92C_IMR_BCNDOK8 0x02000000 |
576 | /*Beacon Queue DMA OK interrupt 7 */ |
577 | #define R92C_IMR_BCNDOK7 0x01000000 |
578 | /*Beacon Queue DMA OK interrupt 6 */ |
579 | #define R92C_IMR_BCNDOK6 0x00800000 |
580 | /*Beacon Queue DMA OK interrupt 5 */ |
581 | #define R92C_IMR_BCNDOK5 0x00400000 |
582 | /*Beacon Queue DMA OK interrupt 4 */ |
583 | #define R92C_IMR_BCNDOK4 0x00200000 |
584 | /*Beacon Queue DMA OK interrupt 3 */ |
585 | #define R92C_IMR_BCNDOK3 0x00100000 |
586 | /*Beacon Queue DMA OK interrupt 2 */ |
587 | #define R92C_IMR_BCNDOK2 0x00080000 |
588 | /*Beacon Queue DMA OK interrupt 1 */ |
589 | #define R92C_IMR_BCNDOK1 0x00040000 |
590 | /*Timeout interrupt 2 */ |
591 | #define R92C_IMR_TIMEOUT2 0x00020000 |
592 | /*Timeout interrupt 1 */ |
593 | #define R92C_IMR_TIMEOUT1 0x00010000 |
594 | /*Transmit FIFO Overflow */ |
595 | #define R92C_IMR_TXFOVW 0x00008000 |
596 | /*Power save time out interrupt */ |
597 | #define R92C_IMR_PSTIMEOUT 0x00004000 |
598 | /*Beacon DMA interrupt 0 */ |
599 | #define R92C_IMR_BCNINT 0x00002000 |
600 | /*Receive FIFO Overflow */ |
601 | #define R92C_IMR_RXFOVW 0x00001000 |
602 | /*Receive Descriptor Unavailable */ |
603 | #define R92C_IMR_RDU 0x00000800 |
604 | /*For 92C,ATIM Window End interrupt */ |
605 | #define R92C_IMR_ATIMEND 0x00000400 |
606 | /*Beacon Queue DMA OK interrupt */ |
607 | #define R92C_IMR_BDOK 0x00000200 |
608 | /*High Queue DMA OK interrupt */ |
609 | #define R92C_IMR_HIGHDOK 0x00000100 |
610 | /*Transmit Beacon OK interrupt */ |
611 | #define R92C_IMR_TBDOK 0x00000080 |
612 | /*Management Queue DMA OK interrupt */ |
613 | #define R92C_IMR_MGNTDOK 0x00000040 |
614 | /*For 92C,Transmit Beacon Error interrupt */ |
615 | #define R92C_IMR_TBDER 0x00000020 |
616 | /*AC_BK DMA OK interrupt */ |
617 | #define R92C_IMR_BKDOK 0x00000010 |
618 | /*AC_BE DMA OK interrupt */ |
619 | #define R92C_IMR_BEDOK 0x00000008 |
620 | /*AC_VI DMA OK interrupt */ |
621 | #define R92C_IMR_VIDOK 0x00000004 |
622 | /*AC_VO DMA interrupt */ |
623 | #define R92C_IMR_VODOK 0x00000002 |
624 | /*Receive DMA OK interrupt */ |
625 | #define R92C_IMR_ROK 0x00000001 |
626 | |
627 | #define R92C_IBSS_INT_MASK (R92C_IMR_BCNINT | R92C_IMR_TBDOK | R92C_IMR_TBDER) |
628 | |
629 | /* |
630 | * Baseband registers. |
631 | */ |
632 | #define R92C_FPGA0_RFMOD 0x800 |
633 | #define R92C_FPGA0_TXINFO 0x804 |
634 | #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) |
635 | #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) |
636 | #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) |
637 | #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) |
638 | #define R92C_TXAGC_A_CCK1_MCS32 0xe08 |
639 | #define R92C_TXAGC_B_CCK1_55_MCS32 0x838 |
640 | #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c |
641 | #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) |
642 | #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) |
643 | #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) |
644 | #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) |
645 | #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) |
646 | #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) |
647 | #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) |
648 | #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) |
649 | #define R92C_FPGA0_ANAPARAM2 0x884 |
650 | #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) |
651 | #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) |
652 | #define R92C_FPGA1_RFMOD 0x900 |
653 | #define R92C_FPGA1_TXINFO 0x90c |
654 | #define R92C_CCK0_SYSTEM 0xa00 |
655 | #define R92C_CCK0_AFESETTING 0xa04 |
656 | #define R92C_OFDM0_TRXPATHENA 0xc04 |
657 | #define R92C_OFDM0_TRMUXPAR 0xc08 |
658 | #define R92C_OFDM0_RXIQIMBALANCE(chain) (0xc14 + (chain) * 8) |
659 | #define R92C_OFDM0_ECCATHRESHOLD 0xc4c |
660 | #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) |
661 | #define R92C_OFDM0_AGCPARAM1 0xc70 |
662 | #define 0xc78 |
663 | #define R92C_OFDM0_TXIQIMBALANCE(chain) (0xc80 + (chain) * 8) |
664 | #define R92C_OFDM0_TXAFE(chain) (0xc94 + (chain) * 8) |
665 | #define R92C_OFDM0_RXIQEXTANTA 0xca0 |
666 | #define R92C_OFDM1_LSTF 0xd00 |
667 | |
668 | /* Bits for R92C_FPGA[01]_RFMOD. */ |
669 | #define R92C_RFMOD_40MHZ 0x00000001 |
670 | #define R92C_RFMOD_JAPAN 0x00000002 |
671 | #define R92C_RFMOD_CCK_TXSC 0x00000030 |
672 | #define R92C_RFMOD_CCK_EN 0x01000000 |
673 | #define R92C_RFMOD_OFDM_EN 0x02000000 |
674 | |
675 | /* Bits for R92C_HSSI_PARAM1(i). */ |
676 | #define R92C_HSSI_PARAM1_PI 0x00000100 |
677 | |
678 | /* Bits for R92C_HSSI_PARAM2(i). */ |
679 | #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 |
680 | #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 |
681 | #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 |
682 | #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 |
683 | #define R92C_HSSI_PARAM2_READ_ADDR_S 23 |
684 | #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 |
685 | |
686 | /* Bits for R92C_TXAGC_A_CCK1_MCS32. */ |
687 | #define R92C_TXAGC_A_CCK1_M 0x0000ff00 |
688 | #define R92C_TXAGC_A_CCK1_S 8 |
689 | |
690 | /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ |
691 | #define R92C_TXAGC_B_CCK11_M 0x000000ff |
692 | #define R92C_TXAGC_B_CCK11_S 0 |
693 | #define R92C_TXAGC_A_CCK2_M 0x0000ff00 |
694 | #define R92C_TXAGC_A_CCK2_S 8 |
695 | #define R92C_TXAGC_A_CCK55_M 0x00ff0000 |
696 | #define R92C_TXAGC_A_CCK55_S 16 |
697 | #define R92C_TXAGC_A_CCK11_M 0xff000000 |
698 | #define R92C_TXAGC_A_CCK11_S 24 |
699 | |
700 | /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ |
701 | #define R92C_TXAGC_B_CCK1_M 0x0000ff00 |
702 | #define R92C_TXAGC_B_CCK1_S 8 |
703 | #define R92C_TXAGC_B_CCK2_M 0x00ff0000 |
704 | #define R92C_TXAGC_B_CCK2_S 16 |
705 | #define R92C_TXAGC_B_CCK55_M 0xff000000 |
706 | #define R92C_TXAGC_B_CCK55_S 24 |
707 | |
708 | /* Bits for R92C_TXAGC_RATE18_06(x). */ |
709 | #define R92C_TXAGC_RATE06_M 0x000000ff |
710 | #define R92C_TXAGC_RATE06_S 0 |
711 | #define R92C_TXAGC_RATE09_M 0x0000ff00 |
712 | #define R92C_TXAGC_RATE09_S 8 |
713 | #define R92C_TXAGC_RATE12_M 0x00ff0000 |
714 | #define R92C_TXAGC_RATE12_S 16 |
715 | #define R92C_TXAGC_RATE18_M 0xff000000 |
716 | #define R92C_TXAGC_RATE18_S 24 |
717 | |
718 | /* Bits for R92C_TXAGC_RATE54_24(x). */ |
719 | #define R92C_TXAGC_RATE24_M 0x000000ff |
720 | #define R92C_TXAGC_RATE24_S 0 |
721 | #define R92C_TXAGC_RATE36_M 0x0000ff00 |
722 | #define R92C_TXAGC_RATE36_S 8 |
723 | #define R92C_TXAGC_RATE48_M 0x00ff0000 |
724 | #define R92C_TXAGC_RATE48_S 16 |
725 | #define R92C_TXAGC_RATE54_M 0xff000000 |
726 | #define R92C_TXAGC_RATE54_S 24 |
727 | |
728 | /* Bits for R92C_TXAGC_MCS03_MCS00(x). */ |
729 | #define R92C_TXAGC_MCS00_M 0x000000ff |
730 | #define R92C_TXAGC_MCS00_S 0 |
731 | #define R92C_TXAGC_MCS01_M 0x0000ff00 |
732 | #define R92C_TXAGC_MCS01_S 8 |
733 | #define R92C_TXAGC_MCS02_M 0x00ff0000 |
734 | #define R92C_TXAGC_MCS02_S 16 |
735 | #define R92C_TXAGC_MCS03_M 0xff000000 |
736 | #define R92C_TXAGC_MCS03_S 24 |
737 | |
738 | /* Bits for R92C_TXAGC_MCS07_MCS04(x). */ |
739 | #define R92C_TXAGC_MCS04_M 0x000000ff |
740 | #define R92C_TXAGC_MCS04_S 0 |
741 | #define R92C_TXAGC_MCS05_M 0x0000ff00 |
742 | #define R92C_TXAGC_MCS05_S 8 |
743 | #define R92C_TXAGC_MCS06_M 0x00ff0000 |
744 | #define R92C_TXAGC_MCS06_S 16 |
745 | #define R92C_TXAGC_MCS07_M 0xff000000 |
746 | #define R92C_TXAGC_MCS07_S 24 |
747 | |
748 | /* Bits for R92C_TXAGC_MCS11_MCS08(x). */ |
749 | #define R92C_TXAGC_MCS08_M 0x000000ff |
750 | #define R92C_TXAGC_MCS08_S 0 |
751 | #define R92C_TXAGC_MCS09_M 0x0000ff00 |
752 | #define R92C_TXAGC_MCS09_S 8 |
753 | #define R92C_TXAGC_MCS10_M 0x00ff0000 |
754 | #define R92C_TXAGC_MCS10_S 16 |
755 | #define R92C_TXAGC_MCS11_M 0xff000000 |
756 | #define R92C_TXAGC_MCS11_S 24 |
757 | |
758 | /* Bits for R92C_TXAGC_MCS15_MCS12(x). */ |
759 | #define R92C_TXAGC_MCS12_M 0x000000ff |
760 | #define R92C_TXAGC_MCS12_S 0 |
761 | #define R92C_TXAGC_MCS13_M 0x0000ff00 |
762 | #define R92C_TXAGC_MCS13_S 8 |
763 | #define R92C_TXAGC_MCS14_M 0x00ff0000 |
764 | #define R92C_TXAGC_MCS14_S 16 |
765 | #define R92C_TXAGC_MCS15_M 0xff000000 |
766 | #define R92C_TXAGC_MCS15_S 24 |
767 | |
768 | /* Bits for R92C_LSSI_PARAM(i). */ |
769 | #define R92C_LSSI_PARAM_DATA_M 0x000fffff |
770 | #define R92C_LSSI_PARAM_DATA_S 0 |
771 | #define R92C_LSSI_PARAM_ADDR_M 0x03f00000 |
772 | #define R92C_LSSI_PARAM_ADDR_S 20 |
773 | |
774 | /* Bits for R92C_FPGA0_ANAPARAM2. */ |
775 | #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 |
776 | |
777 | /* Bits for R92C_LSSI_READBACK(i). */ |
778 | #define R92C_LSSI_READBACK_DATA_M 0x000fffff |
779 | #define R92C_LSSI_READBACK_DATA_S 0 |
780 | |
781 | /* Bits for R92C_OFDM0_AGCCORE1(i). */ |
782 | #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f |
783 | #define R92C_OFDM0_AGCCORE1_GAIN_S 0 |
784 | |
785 | |
786 | /* |
787 | * USB registers. |
788 | */ |
789 | #define R92C_USB_INFO 0xfe17 |
790 | #define R92C_USB_SPECIAL_OPTION 0xfe55 |
791 | #define R92C_USB_HCPWM 0xfe57 |
792 | #define R92C_USB_HRPWM 0xfe58 |
793 | #define R92C_USB_DMA_AGG_TO 0xfe5b |
794 | #define R92C_USB_AGG_TO 0xfe5c |
795 | #define R92C_USB_AGG_TH 0xfe5d |
796 | #define R92C_USB_VID 0xfe60 |
797 | #define R92C_USB_PID 0xfe62 |
798 | #define R92C_USB_OPTIONAL 0xfe64 |
799 | #define R92C_USB_EP 0xfe65 |
800 | #define R92C_USB_PHY 0xfe68 |
801 | #define R92C_USB_MAC_ADDR 0xfe70 |
802 | #define R92C_USB_STRING 0xfe80 |
803 | |
804 | /* Bits for R92C_USB_SPECIAL_OPTION. */ |
805 | #define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 |
806 | |
807 | /* Bits for R92C_USB_EP. */ |
808 | #define R92C_USB_EP_HQ_M 0x000f |
809 | #define R92C_USB_EP_HQ_S 0 |
810 | #define R92C_USB_EP_NQ_M 0x00f0 |
811 | #define R92C_USB_EP_NQ_S 4 |
812 | #define R92C_USB_EP_LQ_M 0x0f00 |
813 | #define R92C_USB_EP_LQ_S 8 |
814 | |
815 | |
816 | /* |
817 | * Firmware base address. |
818 | */ |
819 | #define R92C_FW_START_ADDR 0x1000 |
820 | #define R92C_FW_PAGE_SIZE 4096 |
821 | |
822 | |
823 | /* |
824 | * RF (6052) registers. |
825 | */ |
826 | #define R92C_RF_AC 0x00 |
827 | #define R92C_RF_IQADJ_G(i) (0x01 + (i)) |
828 | #define R92C_RF_POW_TRSW 0x05 |
829 | #define R92C_RF_GAIN_RX 0x06 |
830 | #define R92C_RF_GAIN_TX 0x07 |
831 | #define R92C_RF_TXM_IDAC 0x08 |
832 | #define R92C_RF_BS_IQGEN 0x0f |
833 | #define R92C_RF_MODE1 0x10 |
834 | #define R92C_RF_MODE2 0x11 |
835 | #define R92C_RF_RX_AGC_HP 0x12 |
836 | #define R92C_RF_TX_AGC 0x13 |
837 | #define R92C_RF_BIAS 0x14 |
838 | #define R92C_RF_IPA 0x15 |
839 | #define R92C_RF_POW_ABILITY 0x17 |
840 | #define R92C_RF_CHNLBW 0x18 |
841 | #define R92C_RF_RX_G1 0x1a |
842 | #define R92C_RF_RX_G2 0x1b |
843 | #define R92C_RF_RX_BB2 0x1c |
844 | #define R92C_RF_RX_BB1 0x1d |
845 | #define R92C_RF_RCK1 0x1e |
846 | #define R92C_RF_RCK2 0x1f |
847 | #define R92C_RF_TX_G(i) (0x20 + (i)) |
848 | #define R92C_RF_TX_BB1 0x23 |
849 | #define R92C_RF_T_METER 0x24 |
850 | #define R92C_RF_SYN_G(i) (0x25 + (i)) |
851 | #define R92C_RF_RCK_OS 0x30 |
852 | #define R92C_RF_TXPA_G(i) (0x31 + (i)) |
853 | |
854 | /* Bits for R92C_RF_AC. */ |
855 | #define R92C_RF_AC_MODE_M 0x70000 |
856 | #define R92C_RF_AC_MODE_S 16 |
857 | #define R92C_RF_AC_MODE_STANDBY 1 |
858 | |
859 | /* Bits for R92C_RF_CHNLBW. */ |
860 | #define R92C_RF_CHNLBW_CHNL_M 0x003ff |
861 | #define R92C_RF_CHNLBW_CHNL_S 0 |
862 | #define R92C_RF_CHNLBW_BW20 0x00400 |
863 | #define R92C_RF_CHNLBW_LCSTART 0x08000 |
864 | |
865 | |
866 | /* |
867 | * CAM entries. |
868 | */ |
869 | #define R92C_CAM_ENTRY_COUNT 32 |
870 | |
871 | #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) |
872 | #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) |
873 | #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) |
874 | |
875 | /* Bits for R92C_CAM_CTL0(i). */ |
876 | #define R92C_CAM_KEYID_M 0x00000003 |
877 | #define R92C_CAM_KEYID_S 0 |
878 | #define R92C_CAM_ALGO_M 0x0000001c |
879 | #define R92C_CAM_ALGO_S 2 |
880 | #define R92C_CAM_ALGO_NONE 0 |
881 | #define R92C_CAM_ALGO_WEP40 1 |
882 | #define R92C_CAM_ALGO_TKIP 2 |
883 | #define R92C_CAM_ALGO_AES 4 |
884 | #define R92C_CAM_ALGO_WEP104 5 |
885 | #define R92C_CAM_VALID 0x00008000 |
886 | #define R92C_CAM_MACLO_M 0xffff0000 |
887 | #define R92C_CAM_MACLO_S 16 |
888 | |
889 | /* Rate adaptation modes. */ |
890 | #define R92C_RAID_11GN 1 |
891 | #define R92C_RAID_11N 3 |
892 | #define R92C_RAID_11BG 4 |
893 | #define R92C_RAID_11G 5 /* "pure" 11g */ |
894 | #define R92C_RAID_11B 6 |
895 | |
896 | |
897 | /* Macros to access unaligned little-endian memory. */ |
898 | #define LE_READ_2(x) ((x)[0] | (x)[1] << 8) |
899 | #define LE_READ_4(x) ((x)[0] | (x)[1] << 8 | (x)[2] << 16 | (x)[3] << 24) |
900 | |
901 | /* |
902 | * Macros to access subfields in registers. |
903 | */ |
904 | /* Mask and Shift (getter). */ |
905 | #define MS(val, field) \ |
906 | (((val) & field##_M) >> field##_S) |
907 | |
908 | /* Shift and Mask (setter). */ |
909 | #define SM(field, val) \ |
910 | (((val) << field##_S) & field##_M) |
911 | |
912 | /* Rewrite. */ |
913 | #define RW(var, field, val) \ |
914 | (((var) & ~field##_M) | SM(field, val)) |
915 | |
916 | /* |
917 | * Firmware image header. |
918 | */ |
919 | struct r92c_fw_hdr { |
920 | /* QWORD0 */ |
921 | uint16_t signature; |
922 | uint8_t category; |
923 | uint8_t function; |
924 | uint16_t version; |
925 | uint16_t subversion; |
926 | /* QWORD1 */ |
927 | uint8_t month; |
928 | uint8_t date; |
929 | uint8_t hour; |
930 | uint8_t minute; |
931 | uint16_t ramcodesize; |
932 | uint16_t reserved2; |
933 | /* QWORD2 */ |
934 | uint32_t svnidx; |
935 | uint32_t reserved3; |
936 | /* QWORD3 */ |
937 | uint32_t reserved4; |
938 | uint32_t reserved5; |
939 | } __packed; |
940 | |
941 | /* |
942 | * Host to firmware commands. |
943 | */ |
944 | struct r92c_fw_cmd { |
945 | uint8_t id; |
946 | #define R92C_CMD_AP_OFFLOAD 0 |
947 | #define R92C_CMD_SET_PWRMODE 1 |
948 | #define R92C_CMD_JOINBSS_RPT 2 |
949 | #define R92C_CMD_RSVD_PAGE 3 |
950 | #define 4 |
951 | #define 5 |
952 | #define R92C_CMD_MACID_CONFIG 6 |
953 | #define R92C_CMD_MACID_PS_MODE 7 |
954 | #define R92C_CMD_P2P_PS_OFFLOAD 8 |
955 | #define R92C_CMD_SELECTIVE_SUSPEND 9 |
956 | #define R92C_CMD_FLAG_EXT 0x80 |
957 | |
958 | uint8_t msg[5]; |
959 | } __packed; |
960 | |
961 | /* Structure for R92C_CMD_RSSI_SETTING. */ |
962 | struct { |
963 | uint8_t ; |
964 | uint8_t ; |
965 | uint8_t ; |
966 | } __packed; |
967 | |
968 | /* Structure for R92C_CMD_MACID_CONFIG. */ |
969 | struct r92c_fw_cmd_macid_cfg { |
970 | uint32_t mask; |
971 | uint8_t macid; |
972 | #define RTWN_MACID_BSS 0 |
973 | #define RTWN_MACID_BC 4 /* Broadcast. */ |
974 | #define RTWN_MACID_VALID 0x80 |
975 | } __packed; |
976 | |
977 | /* |
978 | * RTL8192CU ROM image. |
979 | */ |
980 | struct r92c_rom { |
981 | uint16_t id; /* 0x8129 */ |
982 | uint8_t reserved1[5]; |
983 | uint8_t dbg_sel; |
984 | uint16_t reserved2; |
985 | uint16_t vid; |
986 | uint16_t pid; |
987 | uint8_t usb_opt; |
988 | uint8_t ep_setting; |
989 | uint16_t reserved3; |
990 | uint8_t usb_phy; |
991 | uint8_t reserved4[3]; |
992 | uint8_t macaddr[6]; |
993 | uint8_t string[61]; /* "Realtek" */ |
994 | uint8_t subcustomer_id; |
995 | uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; |
996 | uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; |
997 | uint8_t ht40_2s_tx_pwr_diff[3]; |
998 | uint8_t ht20_tx_pwr_diff[3]; |
999 | uint8_t ofdm_tx_pwr_diff[3]; |
1000 | uint8_t ht40_max_pwr[3]; |
1001 | uint8_t ht20_max_pwr[3]; |
1002 | uint8_t xtal_calib; |
1003 | uint8_t tssi[R92C_MAX_CHAINS]; |
1004 | uint8_t thermal_meter; |
1005 | uint8_t rf_opt1; |
1006 | #define R92C_ROM_RF1_REGULATORY_M 0x07 |
1007 | #define R92C_ROM_RF1_REGULATORY_S 0 |
1008 | #define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 |
1009 | #define R92C_ROM_RF1_BOARD_TYPE_S 5 |
1010 | #define R92C_BOARD_TYPE_DONGLE 0 |
1011 | #define R92C_BOARD_TYPE_HIGHPA 1 |
1012 | #define R92C_BOARD_TYPE_MINICARD 2 |
1013 | #define R92C_BOARD_TYPE_SOLO 3 |
1014 | #define R92C_BOARD_TYPE_COMBO 4 |
1015 | |
1016 | uint8_t rf_opt2; |
1017 | uint8_t rf_opt3; |
1018 | uint8_t rf_opt4; |
1019 | uint8_t channel_plan; |
1020 | uint8_t version; |
1021 | uint8_t curstomer_id; |
1022 | } __packed; |
1023 | |
1024 | /* Rx MAC descriptor. */ |
1025 | struct r92c_rx_desc { |
1026 | uint32_t rxdw0; |
1027 | #define R92C_RXDW0_PKTLEN_M 0x00003fff |
1028 | #define R92C_RXDW0_PKTLEN_S 0 |
1029 | #define R92C_RXDW0_CRCERR 0x00004000 |
1030 | #define R92C_RXDW0_ICVERR 0x00008000 |
1031 | #define R92C_RXDW0_INFOSZ_M 0x000f0000 |
1032 | #define R92C_RXDW0_INFOSZ_S 16 |
1033 | #define R92C_RXDW0_QOS 0x00800000 |
1034 | #define R92C_RXDW0_SHIFT_M 0x03000000 |
1035 | #define R92C_RXDW0_SHIFT_S 24 |
1036 | #define R92C_RXDW0_PHYST 0x04000000 |
1037 | #define R92C_RXDW0_DECRYPTED 0x08000000 |
1038 | #define R92C_RXDW0_LS 0x10000000 |
1039 | #define R92C_RXDW0_FS 0x20000000 |
1040 | #define R92C_RXDW0_EOR 0x40000000 |
1041 | #define R92C_RXDW0_OWN 0x80000000 |
1042 | |
1043 | uint32_t rxdw1; |
1044 | uint32_t rxdw2; |
1045 | #define R92C_RXDW2_PKTCNT_M 0x00ff0000 |
1046 | #define R92C_RXDW2_PKTCNT_S 16 |
1047 | |
1048 | uint32_t rxdw3; |
1049 | #define R92C_RXDW3_RATE_M 0x0000003f |
1050 | #define R92C_RXDW3_RATE_S 0 |
1051 | #define R92C_RXDW3_HT 0x00000040 |
1052 | #define R92C_RXDW3_HTC 0x00000400 |
1053 | |
1054 | uint32_t rxdw4; |
1055 | uint32_t rxdw5; |
1056 | |
1057 | uint32_t rxbufaddr; |
1058 | uint32_t rxbufaddr64; |
1059 | } __packed __attribute__((aligned(4))); |
1060 | |
1061 | /* Rx PHY descriptor. */ |
1062 | struct r92c_rx_phystat { |
1063 | uint32_t phydw0; |
1064 | uint32_t phydw1; |
1065 | uint32_t phydw2; |
1066 | uint32_t phydw3; |
1067 | uint32_t phydw4; |
1068 | uint32_t phydw5; |
1069 | uint32_t phydw6; |
1070 | uint32_t phydw7; |
1071 | } __packed __attribute__((aligned(4))); |
1072 | |
1073 | /* Rx PHY CCK descriptor. */ |
1074 | struct r92c_rx_cck { |
1075 | uint8_t adc_pwdb[4]; |
1076 | uint8_t sq_rpt; |
1077 | uint8_t agc_rpt; |
1078 | } __packed; |
1079 | |
1080 | /* Tx MAC descriptor. */ |
1081 | struct r92c_tx_desc { |
1082 | uint32_t txdw0; |
1083 | #define R92C_TXDW0_PKTLEN_M 0x0000ffff |
1084 | #define R92C_TXDW0_PKTLEN_S 0 |
1085 | #define R92C_TXDW0_OFFSET_M 0x00ff0000 |
1086 | #define R92C_TXDW0_OFFSET_S 16 |
1087 | #define R92C_TXDW0_BMCAST 0x01000000 |
1088 | #define R92C_TXDW0_LSG 0x04000000 |
1089 | #define R92C_TXDW0_FSG 0x08000000 |
1090 | #define R92C_TXDW0_OWN 0x80000000 |
1091 | |
1092 | uint32_t txdw1; |
1093 | #define R92C_TXDW1_MACID_M 0x0000001f |
1094 | #define R92C_TXDW1_MACID_S 0 |
1095 | #define R92C_TXDW1_AGGEN 0x00000020 |
1096 | #define R92C_TXDW1_AGGBK 0x00000040 |
1097 | #define R92C_TXDW1_QSEL_M 0x00001f00 |
1098 | #define R92C_TXDW1_QSEL_S 8 |
1099 | #define R92C_TXDW1_QSEL_BE 0x00 |
1100 | #define R92C_TXDW1_QSEL_BK 0x02 |
1101 | #define R92C_TXDW1_QSEL_VI 0x05 |
1102 | #define R92C_TXDW1_QSEL_VO 0x07 |
1103 | #define R92C_TXDW1_QSEL_BEACON 0x10 |
1104 | #define R92C_TXDW1_QSEL_HIGH 0x11 |
1105 | #define R92C_TXDW1_QSEL_MGNT 0x12 |
1106 | #define R92C_TXDW1_QSEL_CMD 0x13 |
1107 | #define R92C_TXDW1_RAID_M 0x000f0000 |
1108 | #define R92C_TXDW1_RAID_S 16 |
1109 | #define R92C_TXDW1_CIPHER_M 0x00c00000 |
1110 | #define R92C_TXDW1_CIPHER_S 22 |
1111 | #define R92C_TXDW1_CIPHER_NONE 0 |
1112 | #define R92C_TXDW1_CIPHER_RC4 1 |
1113 | #define R92C_TXDW1_CIPHER_AES 3 |
1114 | #define R92C_TXDW1_PKTOFF_M 0x7c000000 |
1115 | #define R92C_TXDW1_PKTOFF_S 26 |
1116 | |
1117 | uint32_t txdw2; |
1118 | uint16_t txdw3; |
1119 | uint16_t txdseq; |
1120 | |
1121 | uint32_t txdw4; |
1122 | #define R92C_TXDW4_RTSRATE_M 0x0000003f |
1123 | #define R92C_TXDW4_RTSRATE_S 0 |
1124 | #define R92C_TXDW4_QOS 0x00000040 |
1125 | #define R92C_TXDW4_HWSEQ 0x00000080 |
1126 | #define R92C_TXDW4_DRVRATE 0x00000100 |
1127 | #define R92C_TXDW4_CTS2SELF 0x00000800 |
1128 | #define R92C_TXDW4_RTSEN 0x00001000 |
1129 | #define R92C_TXDW4_HWRTSEN 0x00002000 |
1130 | #define R92C_TXDW4_SCO_M 0x003f0000 |
1131 | #define R92C_TXDW4_SCO_S 20 |
1132 | #define R92C_TXDW4_SCO_SCA 1 |
1133 | #define R92C_TXDW4_SCO_SCB 2 |
1134 | #define R92C_TXDW4_40MHZ 0x02000000 |
1135 | |
1136 | uint32_t txdw5; |
1137 | #define R92C_TXDW5_DATARATE_M 0x0000003f |
1138 | #define R92C_TXDW5_DATARATE_S 0 |
1139 | #define R92C_TXDW5_SGI 0x00000040 |
1140 | #define R92C_TXDW5_DATARATE_FBLIMIT_M 0x00001f00 |
1141 | #define R92C_TXDW5_DATARATE_FBLIMIT_S 8 |
1142 | #define R92C_TXDW5_RTSRATE_FBLIMIT_M 0x0001e000 |
1143 | #define R92C_TXDW5_RTSRATE_FBLIMIT_S 13 |
1144 | #define R92C_TXDW5_RETRY_LIMIT_ENABLE 0x00020000 |
1145 | #define R92C_TXDW5_DATA_RETRY_LIMIT_M 0x00fc0000 |
1146 | #define R92C_TXDW5_DATA_RETRY_LIMIT_S 18 |
1147 | #define R92C_TXDW5_AGGNUM_M 0xff000000 |
1148 | #define R92C_TXDW5_AGGNUM_S 24 |
1149 | |
1150 | uint32_t txdw6; |
1151 | |
1152 | uint16_t txbufsize; |
1153 | uint16_t pad; |
1154 | |
1155 | uint32_t txbufaddr; |
1156 | uint32_t txbufaddr64; |
1157 | |
1158 | uint32_t nextdescaddr; |
1159 | uint32_t nextdescaddr64; |
1160 | |
1161 | uint32_t reserved[4]; |
1162 | } __packed __attribute__((aligned(4))); |
1163 | |
1164 | |
1165 | /* |
1166 | * Driver definitions. |
1167 | */ |
1168 | #define RTWN_NTXQUEUES 9 |
1169 | #define RTWN_RX_LIST_COUNT 256 |
1170 | #define RTWN_TX_LIST_COUNT 256 |
1171 | #define RTWN_HOST_CMD_RING_COUNT 32 |
1172 | |
1173 | /* TX queue indices. */ |
1174 | #define RTWN_BK_QUEUE 0 |
1175 | #define RTWN_BE_QUEUE 1 |
1176 | #define RTWN_VI_QUEUE 2 |
1177 | #define RTWN_VO_QUEUE 3 |
1178 | #define RTWN_BEACON_QUEUE 4 |
1179 | #define RTWN_TXCMD_QUEUE 5 |
1180 | #define RTWN_MGNT_QUEUE 6 |
1181 | #define RTWN_HIGH_QUEUE 7 |
1182 | #define RTWN_HCCA_QUEUE 8 |
1183 | |
1184 | /* RX queue indices. */ |
1185 | #define RTWN_RX_QUEUE 0 |
1186 | |
1187 | #define RTWN_RXBUFSZ (16 * 1024) |
1188 | #define RTWN_TXBUFSZ (sizeof(struct r92c_tx_desc) + IEEE80211_MAX_LEN) |
1189 | |
1190 | #define RTWN_RIDX_COUNT 28 |
1191 | |
1192 | #define RTWN_TX_TIMEOUT 5000 /* ms */ |
1193 | |
1194 | #define RTWN_LED_LINK 0 |
1195 | #define RTWN_LED_DATA 1 |
1196 | |
1197 | struct { |
1198 | struct ieee80211_radiotap_header ; |
1199 | uint8_t ; |
1200 | uint8_t ; |
1201 | uint16_t ; |
1202 | uint16_t ; |
1203 | uint8_t ; |
1204 | } __packed; |
1205 | |
1206 | #define RTWN_RX_RADIOTAP_PRESENT \ |
1207 | (1 << IEEE80211_RADIOTAP_FLAGS | \ |
1208 | 1 << IEEE80211_RADIOTAP_RATE | \ |
1209 | 1 << IEEE80211_RADIOTAP_CHANNEL | \ |
1210 | 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
1211 | |
1212 | struct { |
1213 | struct ieee80211_radiotap_header ; |
1214 | uint8_t ; |
1215 | uint16_t ; |
1216 | uint16_t ; |
1217 | } __packed; |
1218 | |
1219 | #define RTWN_TX_RADIOTAP_PRESENT \ |
1220 | (1 << IEEE80211_RADIOTAP_FLAGS | \ |
1221 | 1 << IEEE80211_RADIOTAP_CHANNEL) |
1222 | |
1223 | struct rtwn_softc; |
1224 | |
1225 | struct rtwn_rx_data { |
1226 | bus_dmamap_t map; |
1227 | struct mbuf *m; |
1228 | }; |
1229 | |
1230 | struct rtwn_rx_ring { |
1231 | struct r92c_rx_desc *desc; |
1232 | bus_dmamap_t map; |
1233 | bus_dma_segment_t seg; |
1234 | int nsegs; |
1235 | struct rtwn_rx_data rx_data[RTWN_RX_LIST_COUNT]; |
1236 | |
1237 | }; |
1238 | struct rtwn_tx_data { |
1239 | bus_dmamap_t map; |
1240 | struct mbuf *m; |
1241 | struct ieee80211_node *ni; |
1242 | }; |
1243 | |
1244 | struct rtwn_tx_ring { |
1245 | bus_dmamap_t map; |
1246 | bus_dma_segment_t seg; |
1247 | int nsegs; |
1248 | struct r92c_tx_desc *desc; |
1249 | struct rtwn_tx_data tx_data[RTWN_TX_LIST_COUNT]; |
1250 | int queued; |
1251 | int cur; |
1252 | }; |
1253 | |
1254 | struct rtwn_host_cmd { |
1255 | void (*cb)(struct rtwn_softc *, void *); |
1256 | uint8_t data[256]; |
1257 | }; |
1258 | |
1259 | struct rtwn_cmd_key { |
1260 | struct ieee80211_key key; |
1261 | uint16_t associd; |
1262 | }; |
1263 | |
1264 | struct rtwn_host_cmd_ring { |
1265 | struct rtwn_host_cmd cmd[RTWN_HOST_CMD_RING_COUNT]; |
1266 | int cur; |
1267 | int next; |
1268 | int queued; |
1269 | }; |
1270 | |
1271 | struct rtwn_softc { |
1272 | device_t sc_dev; |
1273 | struct ethercom sc_ec; |
1274 | struct ieee80211com sc_ic; |
1275 | int (*sc_newstate)(struct ieee80211com *, |
1276 | enum ieee80211_state, int); |
1277 | |
1278 | /* PCI specific goo. */ |
1279 | bus_dma_tag_t sc_dmat; |
1280 | pci_chipset_tag_t sc_pc; |
1281 | pcitag_t sc_tag; |
1282 | void *sc_ih; |
1283 | pci_intr_handle_t *sc_pihp; |
1284 | bus_space_tag_t sc_st; |
1285 | bus_space_handle_t sc_sh; |
1286 | bus_size_t sc_mapsize; |
1287 | int sc_cap_off; |
1288 | |
1289 | |
1290 | struct callout scan_to; |
1291 | struct callout calib_to; |
1292 | void *init_task; |
1293 | int ac2idx[WME_NUM_AC]; |
1294 | uint32_t sc_flags; |
1295 | #define RTWN_FLAG_FW_LOADED __BIT(0) |
1296 | #define RTWN_FLAG_CCK_HIPWR __BIT(1) |
1297 | |
1298 | uint32_t chip; |
1299 | #define RTWN_CHIP_88C __BIT(0) |
1300 | #define RTWN_CHIP_92C __BIT(1) |
1301 | #define RTWN_CHIP_92C_1T2R __BIT(2) |
1302 | #define RTWN_CHIP_UMC __BIT(3) |
1303 | #define RTWN_CHIP_UMC_A_CUT __BIT(4) |
1304 | #define RTWN_CHIP_UMC_B_CUT __BIT(5) |
1305 | |
1306 | uint8_t board_type; |
1307 | uint8_t regulatory; |
1308 | uint8_t pa_setting; |
1309 | int avg_pwdb; |
1310 | int thcal_state; |
1311 | int thcal_lctemp; |
1312 | int ntxchains; |
1313 | int nrxchains; |
1314 | int ledlink; |
1315 | |
1316 | int sc_tx_timer; |
1317 | int fwcur; |
1318 | struct rtwn_rx_ring rx_ring; |
1319 | struct rtwn_tx_ring tx_ring[RTWN_NTXQUEUES]; |
1320 | uint32_t qfullmsk; |
1321 | struct r92c_rom rom; |
1322 | |
1323 | uint32_t rf_chnlbw[R92C_MAX_CHAINS]; |
1324 | struct bpf_if *sc_drvbpf; |
1325 | |
1326 | union { |
1327 | struct rtwn_rx_radiotap_header th; |
1328 | uint8_t pad[64]; |
1329 | } sc_rxtapu; |
1330 | #define sc_rxtap sc_rxtapu.th |
1331 | int sc_rxtap_len; |
1332 | |
1333 | union { |
1334 | struct rtwn_tx_radiotap_header th; |
1335 | uint8_t pad[64]; |
1336 | } sc_txtapu; |
1337 | #define sc_txtap sc_txtapu.th |
1338 | int sc_txtap_len; |
1339 | }; |
1340 | |
1341 | #define sc_if sc_ec.ec_if |
1342 | #define GET_IFP(sc) (&(sc)->sc_if) |
1343 | #define IC2IFP(ic) ((ic)->ic_ifp) |
1344 | |
1345 | |
1346 | /* |
1347 | * MAC initialization values. |
1348 | */ |
1349 | static const struct { |
1350 | uint16_t reg; |
1351 | uint8_t val; |
1352 | } rtl8192ce_mac[] = { |
1353 | { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, |
1354 | { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, |
1355 | { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, |
1356 | { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, |
1357 | { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, |
1358 | { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, |
1359 | { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, |
1360 | { 0x45b, 0xb9 }, { 0x460, 0x88 }, { 0x461, 0x88 }, { 0x462, 0x06 }, |
1361 | { 0x463, 0x03 }, { 0x4c8, 0x04 }, { 0x4c9, 0x08 }, { 0x4cc, 0x02 }, |
1362 | { 0x4cd, 0x28 }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, |
1363 | { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, |
1364 | { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, |
1365 | { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, |
1366 | { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, |
1367 | { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, |
1368 | { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x20 }, { 0x547, 0x00 }, |
1369 | { 0x559, 0x02 }, { 0x55a, 0x02 }, { 0x55d, 0xff }, { 0x605, 0x30 }, |
1370 | { 0x608, 0x0e }, { 0x609, 0x2a }, { 0x652, 0x20 }, { 0x63c, 0x0a }, |
1371 | { 0x63d, 0x0e }, { 0x700, 0x21 }, { 0x701, 0x43 }, { 0x702, 0x65 }, |
1372 | { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, { 0x70a, 0x65 }, |
1373 | { 0x70b, 0x87 } |
1374 | }; |
1375 | |
1376 | /* |
1377 | * Baseband initialization values. |
1378 | */ |
1379 | struct rtwn_bb_prog { |
1380 | int count; |
1381 | const uint16_t *regs; |
1382 | const uint32_t *vals; |
1383 | int agccount; |
1384 | const uint32_t *agcvals; |
1385 | }; |
1386 | |
1387 | /* |
1388 | * RTL8192CU and RTL8192CE-VAU. |
1389 | */ |
1390 | static const uint16_t rtl8192ce_bb_regs[] = { |
1391 | 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, |
1392 | 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, |
1393 | 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, |
1394 | 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, |
1395 | 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, |
1396 | 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, |
1397 | 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, |
1398 | 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, |
1399 | 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, |
1400 | 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, |
1401 | 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, |
1402 | 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, |
1403 | 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, |
1404 | 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, |
1405 | 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, |
1406 | 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, |
1407 | 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, |
1408 | 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, |
1409 | 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, |
1410 | 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, |
1411 | 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 |
1412 | }; |
1413 | |
1414 | static const uint32_t rtl8192ce_bb_vals_2t[] = { |
1415 | 0x0011800f, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, |
1416 | 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, |
1417 | 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, |
1418 | 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, |
1419 | 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, |
1420 | 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, |
1421 | 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, |
1422 | 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, |
1423 | 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, |
1424 | 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, |
1425 | 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, |
1426 | 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, |
1427 | 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, |
1428 | 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, |
1429 | 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, |
1430 | 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, |
1431 | 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, |
1432 | 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, |
1433 | 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, |
1434 | 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, |
1435 | 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, |
1436 | 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, |
1437 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, |
1438 | 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, |
1439 | 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, |
1440 | 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, |
1441 | 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, |
1442 | 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, |
1443 | 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, |
1444 | 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, |
1445 | 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, |
1446 | 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, |
1447 | 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, |
1448 | 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, |
1449 | 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, |
1450 | 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, |
1451 | 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, |
1452 | 0x00000000, 0x00000300 |
1453 | }; |
1454 | |
1455 | static const uint32_t rtl8192ce_bb_vals_1t[] = { |
1456 | 0x0011800f, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, |
1457 | 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, |
1458 | 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, |
1459 | 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, |
1460 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, |
1461 | 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, |
1462 | 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, |
1463 | 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, |
1464 | 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, |
1465 | 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, |
1466 | 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, |
1467 | 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, |
1468 | 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, |
1469 | 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, |
1470 | 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, |
1471 | 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, |
1472 | 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, |
1473 | 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, |
1474 | 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, |
1475 | 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, |
1476 | 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, |
1477 | 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, |
1478 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, |
1479 | 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, |
1480 | 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, |
1481 | 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, |
1482 | 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, |
1483 | 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, |
1484 | 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, |
1485 | 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, |
1486 | 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, |
1487 | 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, |
1488 | 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, |
1489 | 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x631b25a0, |
1490 | 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, |
1491 | 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, |
1492 | 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, |
1493 | 0x00000000, 0x00000300, |
1494 | }; |
1495 | |
1496 | static const uint32_t rtl8192ce_agc_vals[] = { |
1497 | 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, |
1498 | 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, |
1499 | 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, |
1500 | 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, |
1501 | 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, |
1502 | 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, |
1503 | 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, |
1504 | 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, |
1505 | 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, |
1506 | 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, |
1507 | 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, |
1508 | 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, |
1509 | 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, |
1510 | 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, |
1511 | 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, |
1512 | 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, |
1513 | 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, |
1514 | 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, |
1515 | 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, |
1516 | 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, |
1517 | 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, |
1518 | 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, |
1519 | 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, |
1520 | 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, |
1521 | 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, |
1522 | 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, |
1523 | 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, |
1524 | 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, |
1525 | 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, |
1526 | 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, |
1527 | 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, |
1528 | 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e |
1529 | }; |
1530 | |
1531 | static const struct rtwn_bb_prog rtl8192ce_bb_prog_2t = { |
1532 | __arraycount(rtl8192ce_bb_regs), |
1533 | rtl8192ce_bb_regs, |
1534 | rtl8192ce_bb_vals_2t, |
1535 | __arraycount(rtl8192ce_agc_vals), |
1536 | rtl8192ce_agc_vals |
1537 | }; |
1538 | |
1539 | static const struct rtwn_bb_prog rtl8192ce_bb_prog_1t = { |
1540 | __arraycount(rtl8192ce_bb_regs), |
1541 | rtl8192ce_bb_regs, |
1542 | rtl8192ce_bb_vals_1t, |
1543 | __arraycount(rtl8192ce_agc_vals), |
1544 | rtl8192ce_agc_vals |
1545 | }; |
1546 | |
1547 | /* |
1548 | * RTL8188CU. |
1549 | */ |
1550 | static const uint32_t rtl8192cu_bb_vals[] = { |
1551 | 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, |
1552 | 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, |
1553 | 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, |
1554 | 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, |
1555 | 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, |
1556 | 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, |
1557 | 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, |
1558 | 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, |
1559 | 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, |
1560 | 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, |
1561 | 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, |
1562 | 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, |
1563 | 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, |
1564 | 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, |
1565 | 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, |
1566 | 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, |
1567 | 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, |
1568 | 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, |
1569 | 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, |
1570 | 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, |
1571 | 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, |
1572 | 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, |
1573 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, |
1574 | 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, |
1575 | 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, |
1576 | 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, |
1577 | 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, |
1578 | 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, |
1579 | 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, |
1580 | 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, |
1581 | 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, |
1582 | 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, |
1583 | 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, |
1584 | 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, |
1585 | 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, |
1586 | 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, |
1587 | 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, |
1588 | 0x00000000, 0x00000300 |
1589 | }; |
1590 | |
1591 | static const struct rtwn_bb_prog rtl8192cu_bb_prog = { |
1592 | __arraycount(rtl8192ce_bb_regs), |
1593 | rtl8192ce_bb_regs, |
1594 | rtl8192cu_bb_vals, |
1595 | __arraycount(rtl8192ce_agc_vals), |
1596 | rtl8192ce_agc_vals |
1597 | }; |
1598 | |
1599 | /* |
1600 | * RTL8188CE-VAU. |
1601 | */ |
1602 | static const uint32_t rtl8188ce_bb_vals[] = { |
1603 | 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, |
1604 | 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, |
1605 | 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, |
1606 | 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, |
1607 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, |
1608 | 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, |
1609 | 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, |
1610 | 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, |
1611 | 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, |
1612 | 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, |
1613 | 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, |
1614 | 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, |
1615 | 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, |
1616 | 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, |
1617 | 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, |
1618 | 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, |
1619 | 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, |
1620 | 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, |
1621 | 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, |
1622 | 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, |
1623 | 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, |
1624 | 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, |
1625 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, |
1626 | 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, |
1627 | 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, |
1628 | 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, |
1629 | 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, |
1630 | 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, |
1631 | 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, |
1632 | 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, |
1633 | 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, |
1634 | 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, |
1635 | 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, |
1636 | 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, |
1637 | 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, |
1638 | 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, |
1639 | 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, |
1640 | 0x00000000, 0x00000300 |
1641 | }; |
1642 | |
1643 | static const uint32_t rtl8188ce_agc_vals[] = { |
1644 | 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, |
1645 | 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, |
1646 | 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, |
1647 | 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, |
1648 | 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, |
1649 | 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, |
1650 | 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, |
1651 | 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, |
1652 | 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, |
1653 | 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, |
1654 | 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, |
1655 | 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, |
1656 | 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, |
1657 | 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, |
1658 | 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, |
1659 | 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, |
1660 | 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, |
1661 | 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, |
1662 | 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, |
1663 | 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, |
1664 | 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, |
1665 | 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, |
1666 | 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, |
1667 | 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, |
1668 | 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, |
1669 | 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, |
1670 | 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, |
1671 | 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, |
1672 | 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, |
1673 | 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, |
1674 | 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, |
1675 | 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e |
1676 | }; |
1677 | |
1678 | static const struct rtwn_bb_prog rtl8188ce_bb_prog = { |
1679 | __arraycount(rtl8192ce_bb_regs), |
1680 | rtl8192ce_bb_regs, |
1681 | rtl8188ce_bb_vals, |
1682 | __arraycount(rtl8188ce_agc_vals), |
1683 | rtl8188ce_agc_vals |
1684 | }; |
1685 | |
1686 | static const uint32_t rtl8188cu_bb_vals[] = { |
1687 | 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, |
1688 | 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, |
1689 | 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, |
1690 | 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, |
1691 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, |
1692 | 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, |
1693 | 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, |
1694 | 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, |
1695 | 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, |
1696 | 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, |
1697 | 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, |
1698 | 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, |
1699 | 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, |
1700 | 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, |
1701 | 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, |
1702 | 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, |
1703 | 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, |
1704 | 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, |
1705 | 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, |
1706 | 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, |
1707 | 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, |
1708 | 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, |
1709 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, |
1710 | 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, |
1711 | 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, |
1712 | 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, |
1713 | 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, |
1714 | 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, |
1715 | 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, |
1716 | 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, |
1717 | 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, |
1718 | 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, |
1719 | 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, |
1720 | 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, |
1721 | 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, |
1722 | 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, |
1723 | 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, |
1724 | 0x00000000, 0x00000300 |
1725 | }; |
1726 | |
1727 | static const struct rtwn_bb_prog rtl8188cu_bb_prog = { |
1728 | __arraycount(rtl8192ce_bb_regs), |
1729 | rtl8192ce_bb_regs, |
1730 | rtl8188cu_bb_vals, |
1731 | __arraycount(rtl8188ce_agc_vals), |
1732 | rtl8188ce_agc_vals |
1733 | }; |
1734 | |
1735 | /* |
1736 | * RTL8188RU. |
1737 | */ |
1738 | static const uint16_t rtl8188ru_bb_regs[] = { |
1739 | 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, |
1740 | 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, |
1741 | 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, |
1742 | 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, |
1743 | 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, |
1744 | 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, |
1745 | 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, |
1746 | 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, |
1747 | 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, |
1748 | 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, |
1749 | 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, |
1750 | 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, |
1751 | 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, |
1752 | 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, |
1753 | 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, |
1754 | 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, |
1755 | 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, |
1756 | 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, |
1757 | 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, |
1758 | 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, |
1759 | 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 |
1760 | }; |
1761 | |
1762 | static const uint32_t rtl8188ru_bb_vals[] = { |
1763 | 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, |
1764 | 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, |
1765 | 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, |
1766 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, |
1767 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
1768 | 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, |
1769 | 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, |
1770 | 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, |
1771 | 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, |
1772 | 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, |
1773 | 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, |
1774 | 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, |
1775 | 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, |
1776 | 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, |
1777 | 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, |
1778 | 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, |
1779 | 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, |
1780 | 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, |
1781 | 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, |
1782 | 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, |
1783 | 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, |
1784 | 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, |
1785 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
1786 | 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, |
1787 | 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, |
1788 | 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, |
1789 | 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, |
1790 | 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, |
1791 | 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, |
1792 | 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, |
1793 | 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, |
1794 | 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, |
1795 | 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, |
1796 | 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, |
1797 | 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, |
1798 | 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, |
1799 | 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, |
1800 | 0x31555448, 0x00000003, 0x00000000, 0x00000300 |
1801 | }; |
1802 | |
1803 | static const uint32_t rtl8188ru_agc_vals[] = { |
1804 | 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, |
1805 | 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, |
1806 | 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, |
1807 | 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, |
1808 | 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, |
1809 | 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, |
1810 | 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, |
1811 | 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, |
1812 | 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, |
1813 | 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, |
1814 | 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, |
1815 | 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, |
1816 | 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, |
1817 | 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, |
1818 | 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, |
1819 | 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, |
1820 | 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, |
1821 | 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, |
1822 | 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, |
1823 | 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, |
1824 | 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, |
1825 | 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, |
1826 | 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, |
1827 | 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, |
1828 | 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, |
1829 | 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, |
1830 | 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, |
1831 | 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, |
1832 | 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, |
1833 | 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, |
1834 | 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, |
1835 | 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e |
1836 | }; |
1837 | |
1838 | static const struct rtwn_bb_prog rtl8188ru_bb_prog = { |
1839 | __arraycount(rtl8188ru_bb_regs), |
1840 | rtl8188ru_bb_regs, |
1841 | rtl8188ru_bb_vals, |
1842 | __arraycount(rtl8188ru_agc_vals), |
1843 | rtl8188ru_agc_vals |
1844 | }; |
1845 | |
1846 | /* |
1847 | * RF initialization values. |
1848 | */ |
1849 | struct rtwn_rf_prog { |
1850 | int count; |
1851 | const uint8_t *regs; |
1852 | const uint32_t *vals; |
1853 | }; |
1854 | |
1855 | /* |
1856 | * RTL8192CU and RTL8192CE-VAU. |
1857 | */ |
1858 | static const uint8_t rtl8192ce_rf1_regs[] = { |
1859 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, |
1860 | 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, |
1861 | 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, |
1862 | 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, |
1863 | 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, |
1864 | 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, |
1865 | 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, |
1866 | 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, |
1867 | 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, |
1868 | 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, |
1869 | 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, |
1870 | 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, |
1871 | 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 |
1872 | }; |
1873 | |
1874 | static const uint32_t rtl8192ce_rf1_vals[] = { |
1875 | 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, |
1876 | 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, |
1877 | 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, |
1878 | 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, |
1879 | 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, |
1880 | 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, |
1881 | 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, |
1882 | 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, |
1883 | 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, |
1884 | 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, |
1885 | 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, |
1886 | 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, |
1887 | 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, |
1888 | 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, |
1889 | 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, |
1890 | 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, |
1891 | 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, |
1892 | 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, |
1893 | 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, |
1894 | 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, |
1895 | 0x30159 |
1896 | }; |
1897 | |
1898 | static const uint8_t rtl8192ce_rf2_regs[] = { |
1899 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, |
1900 | 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, |
1901 | 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, |
1902 | 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 |
1903 | }; |
1904 | |
1905 | static const uint32_t rtl8192ce_rf2_vals[] = { |
1906 | 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, |
1907 | 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, |
1908 | 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, |
1909 | 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, |
1910 | 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, |
1911 | 0xe0330, 0xa0330, 0x60330, 0x20330 |
1912 | }; |
1913 | |
1914 | static const struct rtwn_rf_prog rtl8192ce_rf_prog[] = { |
1915 | { |
1916 | __arraycount(rtl8192ce_rf1_regs), |
1917 | rtl8192ce_rf1_regs, |
1918 | rtl8192ce_rf1_vals |
1919 | }, |
1920 | { |
1921 | __arraycount(rtl8192ce_rf2_regs), |
1922 | rtl8192ce_rf2_regs, |
1923 | rtl8192ce_rf2_vals |
1924 | } |
1925 | }; |
1926 | |
1927 | /* |
1928 | * RTL8188CE-VAU. |
1929 | */ |
1930 | static const uint32_t rtl8188ce_rf_vals[] = { |
1931 | 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, |
1932 | 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, |
1933 | 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, |
1934 | 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, |
1935 | 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, |
1936 | 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, |
1937 | 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, |
1938 | 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, |
1939 | 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, |
1940 | 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, |
1941 | 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, |
1942 | 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, |
1943 | 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, |
1944 | 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, |
1945 | 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, |
1946 | 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, |
1947 | 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, |
1948 | 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, |
1949 | 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, |
1950 | 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, |
1951 | 0x30159 |
1952 | }; |
1953 | |
1954 | static const struct rtwn_rf_prog rtl8188ce_rf_prog[] = { |
1955 | { |
1956 | __arraycount(rtl8192ce_rf1_regs), |
1957 | rtl8192ce_rf1_regs, |
1958 | rtl8188ce_rf_vals |
1959 | } |
1960 | }; |
1961 | |
1962 | |
1963 | /* |
1964 | * RTL8188CU. |
1965 | */ |
1966 | static const uint32_t rtl8188cu_rf_vals[] = { |
1967 | 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, |
1968 | 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, |
1969 | 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, |
1970 | 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, |
1971 | 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, |
1972 | 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, |
1973 | 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, |
1974 | 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, |
1975 | 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, |
1976 | 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, |
1977 | 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, |
1978 | 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, |
1979 | 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, |
1980 | 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, |
1981 | 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, |
1982 | 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, |
1983 | 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, |
1984 | 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, |
1985 | 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, |
1986 | 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, |
1987 | 0x30159 |
1988 | }; |
1989 | |
1990 | static const struct rtwn_rf_prog rtl8188cu_rf_prog[] = { |
1991 | { |
1992 | __arraycount(rtl8192ce_rf1_regs), |
1993 | rtl8192ce_rf1_regs, |
1994 | rtl8188cu_rf_vals |
1995 | } |
1996 | }; |
1997 | |
1998 | /* |
1999 | * RTL8188RU. |
2000 | */ |
2001 | static const uint32_t rtl8188ru_rf_vals[] = { |
2002 | 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, |
2003 | 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, |
2004 | 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, |
2005 | 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, |
2006 | 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, |
2007 | 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, |
2008 | 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, |
2009 | 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, |
2010 | 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, |
2011 | 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, |
2012 | 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, |
2013 | 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, |
2014 | 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, |
2015 | 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, |
2016 | 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, |
2017 | 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, |
2018 | 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, |
2019 | 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, |
2020 | 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, |
2021 | 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, |
2022 | 0x30159 |
2023 | }; |
2024 | |
2025 | static const struct rtwn_rf_prog rtl8188ru_rf_prog[] = { |
2026 | { |
2027 | __arraycount(rtl8192ce_rf1_regs), |
2028 | rtl8192ce_rf1_regs, |
2029 | rtl8188ru_rf_vals |
2030 | } |
2031 | }; |
2032 | |
2033 | struct rtwn_txpwr { |
2034 | uint8_t pwr[3][28]; |
2035 | }; |
2036 | |
2037 | /* |
2038 | * Per RF chain/group/rate Tx gain values. |
2039 | */ |
2040 | static const struct rtwn_txpwr rtl8192cu_txagc[] = { |
2041 | { { /* Chain 0. */ |
2042 | { /* Group 0. */ |
2043 | 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ |
2044 | 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. */ |
2045 | 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. */ |
2046 | 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. */ |
2047 | }, |
2048 | { /* Group 1. */ |
2049 | 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ |
2050 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ |
2051 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ |
2052 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ |
2053 | }, |
2054 | { /* Group 2. */ |
2055 | 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ |
2056 | 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ |
2057 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ |
2058 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ |
2059 | } |
2060 | } }, |
2061 | { { /* Chain 1. */ |
2062 | { /* Group 0. */ |
2063 | 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ |
2064 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ |
2065 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ |
2066 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ |
2067 | }, |
2068 | { /* Group 1. */ |
2069 | 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ |
2070 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ |
2071 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ |
2072 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ |
2073 | }, |
2074 | { /* Group 2. */ |
2075 | 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ |
2076 | 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ |
2077 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ |
2078 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ |
2079 | } |
2080 | } } |
2081 | }; |
2082 | |
2083 | static const struct rtwn_txpwr rtl8188ru_txagc[] = { |
2084 | { { /* Chain 0. */ |
2085 | { /* Group 0. */ |
2086 | 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ |
2087 | 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. */ |
2088 | 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. */ |
2089 | 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. */ |
2090 | }, |
2091 | { /* Group 1. */ |
2092 | 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ |
2093 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ |
2094 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ |
2095 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ |
2096 | }, |
2097 | { /* Group 2. */ |
2098 | 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ |
2099 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ |
2100 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ |
2101 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ |
2102 | } |
2103 | } } |
2104 | }; |
2105 | |