1 | /* |
2 | * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting |
3 | * Copyright (c) 2002-2008 Atheros Communications, Inc. |
4 | * |
5 | * Permission to use, copy, modify, and/or distribute this software for any |
6 | * purpose with or without fee is hereby granted, provided that the above |
7 | * copyright notice and this permission notice appear in all copies. |
8 | * |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
16 | * |
17 | * $Id: ar5416_reset.c,v 1.6 2012/02/12 13:55:27 wiz Exp $ |
18 | */ |
19 | #include "opt_ah.h" |
20 | |
21 | #include "ah.h" |
22 | #include "ah_internal.h" |
23 | #include "ah_devid.h" |
24 | |
25 | #include "ah_eeprom_v14.h" |
26 | |
27 | #include "ar5416/ar5416.h" |
28 | #include "ar5416/ar5416reg.h" |
29 | #include "ar5416/ar5416phy.h" |
30 | |
31 | /* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ |
32 | #define EEP_MINOR(_ah) \ |
33 | (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) |
34 | #define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) |
35 | #define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) |
36 | |
37 | /* Additional Time delay to wait after activiting the Base band */ |
38 | #define BASE_ACTIVATE_DELAY 100 /* 100 usec */ |
39 | #define PLL_SETTLE_DELAY 300 /* 300 usec */ |
40 | #define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ |
41 | |
42 | static void ar5416InitDMA(struct ath_hal *ah); |
43 | static void ar5416InitBB(struct ath_hal *ah, HAL_CHANNEL *chan); |
44 | static void ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode); |
45 | static void ar5416InitQoS(struct ath_hal *ah); |
46 | static void ar5416InitUserSettings(struct ath_hal *ah); |
47 | |
48 | static HAL_BOOL _ar5416SetTransmitPower(struct ath_hal *ah, |
49 | HAL_CHANNEL_INTERNAL *chan, uint16_t *rfXpdGain); |
50 | |
51 | #if 0 |
52 | static HAL_BOOL ar5416ChannelChange(struct ath_hal *, HAL_CHANNEL *); |
53 | #endif |
54 | static void ar5416SetDeltaSlope(struct ath_hal *, HAL_CHANNEL_INTERNAL *); |
55 | |
56 | static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah); |
57 | static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type); |
58 | static void ar5416InitPLL(struct ath_hal *ah, HAL_CHANNEL *chan); |
59 | static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah, |
60 | struct ar5416eeprom *pEepData, |
61 | HAL_CHANNEL_INTERNAL *chan, int16_t *ratesArray, |
62 | uint16_t cfgCtl, uint16_t AntennaReduction, |
63 | uint16_t twiceMaxRegulatoryPower, |
64 | uint16_t powerLimit); |
65 | static HAL_BOOL ar5416SetPowerCalTable(struct ath_hal *ah, |
66 | struct ar5416eeprom *pEepData, |
67 | HAL_CHANNEL_INTERNAL *chan, |
68 | int16_t *pTxPowerIndexOffset); |
69 | static uint16_t ar5416GetMaxEdgePower(uint16_t freq, |
70 | CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz); |
71 | |
72 | static int16_t interpolate(uint16_t target, uint16_t srcLeft, |
73 | uint16_t srcRight, int16_t targetLeft, int16_t targetRight); |
74 | static void ar5416Set11nRegs(struct ath_hal *ah, HAL_CHANNEL *chan); |
75 | static void ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, |
76 | HAL_CHANNEL_INTERNAL *chan, CAL_DATA_PER_FREQ *pRawDataSet, |
77 | uint8_t * bChans, uint16_t availPiers, |
78 | uint16_t tPdGainOverlap, int16_t *pMinCalPower, |
79 | uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, |
80 | uint16_t numXpdGains); |
81 | static HAL_BOOL getLowerUpperIndex(uint8_t target, uint8_t *pList, |
82 | uint16_t listSize, uint16_t *indexL, uint16_t *indexR); |
83 | static HAL_BOOL ar5416FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, |
84 | uint8_t *pPwrList, uint8_t *pVpdList, |
85 | uint16_t numIntercepts, uint8_t *pRetVpdList); |
86 | |
87 | /* |
88 | * Places the device in and out of reset and then places sane |
89 | * values in the registers based on EEPROM config, initialization |
90 | * vectors (as determined by the mode), and station configuration |
91 | * |
92 | * bChannelChange is used to preserve DMA/PCU registers across |
93 | * a HW Reset during channel change. |
94 | */ |
95 | HAL_BOOL |
96 | ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode, |
97 | HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status) |
98 | { |
99 | #define N(a) (sizeof (a) / sizeof (a[0])) |
100 | #define FAIL(_code) do { ecode = _code; goto bad; } while (0) |
101 | struct ath_hal_5212 *ahp = AH5212(ah); |
102 | HAL_CHANNEL_INTERNAL *ichan; |
103 | uint32_t saveDefAntenna, saveLedState; |
104 | uint32_t macStaId1; |
105 | uint16_t rfXpdGain[2]; |
106 | HAL_STATUS ecode; |
107 | uint32_t powerVal, ; |
108 | uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow; |
109 | int i; |
110 | |
111 | OS_MARK(ah, AH_MARK_RESET, bChannelChange); |
112 | #define IS(_c,_f) (((_c)->channelFlags & _f) || 0) |
113 | if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) { |
114 | HALDEBUG(ah, HAL_DEBUG_ANY, |
115 | "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n" , |
116 | __func__, chan->channel, chan->channelFlags); |
117 | FAIL(HAL_EINVAL); |
118 | } |
119 | if ((IS(chan, CHANNEL_OFDM) ^ IS(chan, CHANNEL_CCK)) == 0) { |
120 | HALDEBUG(ah, HAL_DEBUG_ANY, |
121 | "%s: invalid channel %u/0x%x; not marked as OFDM or CCK\n" , |
122 | __func__, chan->channel, chan->channelFlags); |
123 | FAIL(HAL_EINVAL); |
124 | } |
125 | #undef IS |
126 | |
127 | /* Bring out of sleep mode */ |
128 | if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { |
129 | HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n" , |
130 | __func__); |
131 | FAIL(HAL_EIO); |
132 | } |
133 | |
134 | /* |
135 | * Map public channel to private. |
136 | */ |
137 | ichan = ath_hal_checkchannel(ah, chan); |
138 | if (ichan == AH_NULL) { |
139 | HALDEBUG(ah, HAL_DEBUG_ANY, |
140 | "%s: invalid channel %u/0x%x; no mapping\n" , |
141 | __func__, chan->channel, chan->channelFlags); |
142 | FAIL(HAL_EINVAL); |
143 | } else { |
144 | HALDEBUG(ah, HAL_DEBUG_RESET, |
145 | "%s: Ch=%u Max=%d Min=%d\n" ,__func__, |
146 | ichan->channel, ichan->maxTxPower, ichan->minTxPower); |
147 | } |
148 | switch (opmode) { |
149 | case HAL_M_STA: |
150 | case HAL_M_IBSS: |
151 | case HAL_M_HOSTAP: |
152 | case HAL_M_MONITOR: |
153 | break; |
154 | default: |
155 | HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n" , |
156 | __func__, opmode); |
157 | FAIL(HAL_EINVAL); |
158 | break; |
159 | } |
160 | HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); |
161 | |
162 | /* XXX Turn on fast channel change for 5416 */ |
163 | /* |
164 | * Preserve the bmiss rssi threshold and count threshold |
165 | * across resets |
166 | */ |
167 | rssiThrReg = OS_REG_READ(ah, AR_RSSI_THR); |
168 | /* If reg is zero, first time thru set to default val */ |
169 | if (rssiThrReg == 0) |
170 | rssiThrReg = INIT_RSSI_THR; |
171 | |
172 | /* |
173 | * Preserve the antenna on a channel change |
174 | */ |
175 | saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); |
176 | if (saveDefAntenna == 0) /* XXX magic constants */ |
177 | saveDefAntenna = 1; |
178 | |
179 | /* Save hardware flag before chip reset clears the register */ |
180 | macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & |
181 | (AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT); |
182 | |
183 | /* Save led state from pci config register */ |
184 | saveLedState = OS_REG_READ(ah, AR_MAC_LED) & |
185 | (AR_MAC_LED_ASSOC | AR_MAC_LED_MODE | |
186 | AR_MAC_LED_BLINK_THRESH_SEL | AR_MAC_LED_BLINK_SLOW); |
187 | |
188 | if (!ar5416ChipReset(ah, chan)) { |
189 | HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n" , __func__); |
190 | FAIL(HAL_EIO); |
191 | } |
192 | |
193 | /* Restore bmiss rssi & count thresholds */ |
194 | OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg); |
195 | |
196 | OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); |
197 | if (AR_SREV_MERLIN_10_OR_LATER(ah)) |
198 | OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); |
199 | |
200 | if (AR_SREV_KITE(ah)) { |
201 | uint32_t val; |
202 | val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); |
203 | val &= ~AR_PHY_RIFS_INIT_DELAY; |
204 | OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); |
205 | } |
206 | |
207 | AH5416(ah)->ah_writeIni(ah, (HAL_CHANNEL_INTERNAL *)chan); |
208 | |
209 | /* Setup 11n MAC/Phy mode registers */ |
210 | ar5416Set11nRegs(ah, chan); |
211 | |
212 | OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); |
213 | |
214 | HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_DAG_CTRLCCK=0x%x\n" , |
215 | __func__, OS_REG_READ(ah,AR_PHY_DAG_CTRLCCK)); |
216 | HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_ADC_CTL=0x%x\n" , |
217 | __func__, OS_REG_READ(ah,AR_PHY_ADC_CTL)); |
218 | |
219 | /* Set the mute mask to the correct default */ |
220 | if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) |
221 | OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); |
222 | |
223 | if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) { |
224 | /* Clear reg to alllow RX_CLEAR line debug */ |
225 | OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); |
226 | } |
227 | if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) { |
228 | #ifdef notyet |
229 | /* Enable burst prefetch for the data queues */ |
230 | OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... ); |
231 | /* Enable double-buffering */ |
232 | OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS); |
233 | #endif |
234 | } |
235 | |
236 | /* Set ADC/DAC select values */ |
237 | OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); |
238 | |
239 | if (AH5416(ah)->ah_rx_chainmask == 0x5 || |
240 | AH5416(ah)->ah_tx_chainmask == 0x5) |
241 | OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); |
242 | /* Setup Chain Masks */ |
243 | OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, AH5416(ah)->ah_rx_chainmask); |
244 | OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, AH5416(ah)->ah_rx_chainmask); |
245 | OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask); |
246 | |
247 | /* Setup the transmit power values. */ |
248 | if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) { |
249 | HALDEBUG(ah, HAL_DEBUG_ANY, |
250 | "%s: error init'ing transmit power\n" , __func__); |
251 | FAIL(HAL_EIO); |
252 | } |
253 | |
254 | /* Write the analog registers */ |
255 | if (!ahp->ah_rfHal->setRfRegs(ah, ichan, |
256 | IS_CHAN_2GHZ(chan) ? 2 : 1, rfXpdGain)) { |
257 | HALDEBUG(ah, HAL_DEBUG_ANY, |
258 | "%s: ar5212SetRfRegs failed\n" , __func__); |
259 | FAIL(HAL_EIO); |
260 | } |
261 | |
262 | /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ |
263 | if (IS_CHAN_OFDM(chan)|| IS_CHAN_HT(chan)) |
264 | ar5416SetDeltaSlope(ah, ichan); |
265 | |
266 | AH5416(ah)->ah_spurMitigate(ah, (HAL_CHANNEL_INTERNAL *)chan); |
267 | |
268 | /* Setup board specific options for EEPROM version 3 */ |
269 | if (!ah->ah_setBoardValues(ah, chan)) { |
270 | HALDEBUG(ah, HAL_DEBUG_ANY, |
271 | "%s: error setting board options\n" , __func__); |
272 | FAIL(HAL_EIO); |
273 | } |
274 | |
275 | OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); |
276 | |
277 | OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); |
278 | OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) |
279 | | macStaId1 |
280 | | AR_STA_ID1_RTS_USE_DEF |
281 | | ahp->ah_staId1Defaults |
282 | ); |
283 | ar5212SetOperatingMode(ah, opmode); |
284 | |
285 | /* Set Venice BSSID mask according to current state */ |
286 | OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); |
287 | OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); |
288 | |
289 | /* Restore previous led state */ |
290 | OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | saveLedState); |
291 | /* Restore previous antenna */ |
292 | OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); |
293 | |
294 | /* then our BSSID */ |
295 | OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); |
296 | OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4)); |
297 | |
298 | /* Restore bmiss rssi & count thresholds */ |
299 | OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); |
300 | |
301 | OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ |
302 | |
303 | if (!ar5212SetChannel(ah, ichan)) |
304 | FAIL(HAL_EIO); |
305 | |
306 | OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); |
307 | |
308 | /* Set 1:1 QCU to DCU mapping for all queues */ |
309 | for (i = 0; i < AR_NUM_DCU; i++) |
310 | OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); |
311 | |
312 | ahp->ah_intrTxqs = 0; |
313 | for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) |
314 | ar5212ResetTxQueue(ah, i); |
315 | |
316 | ar5416InitIMR(ah, opmode); |
317 | ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); |
318 | ar5416InitQoS(ah); |
319 | ar5416InitUserSettings(ah); |
320 | |
321 | /* |
322 | * disable seq number generation in hw |
323 | */ |
324 | OS_REG_WRITE(ah, AR_STA_ID1, |
325 | OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); |
326 | |
327 | ar5416InitDMA(ah); |
328 | |
329 | /* |
330 | * program OBS bus to see MAC interrupts |
331 | */ |
332 | OS_REG_WRITE(ah, AR_OBS, 8); |
333 | |
334 | #ifdef AR5416_INT_MITIGATION |
335 | OS_REG_WRITE(ah, AR_MIRT, 0); |
336 | OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); |
337 | OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); |
338 | #endif |
339 | |
340 | ar5416InitBB(ah, chan); |
341 | |
342 | /* Setup compression registers */ |
343 | ar5212SetCompRegs(ah); /* XXX not needed? */ |
344 | |
345 | /* |
346 | * 5416 baseband will check the per rate power table |
347 | * and select the lower of the two |
348 | */ |
349 | ackTpcPow = 63; |
350 | ctsTpcPow = 63; |
351 | chirpTpcPow = 63; |
352 | powerVal = SM(ackTpcPow, AR_TPC_ACK) | |
353 | SM(ctsTpcPow, AR_TPC_CTS) | |
354 | SM(chirpTpcPow, AR_TPC_CHIRP); |
355 | OS_REG_WRITE(ah, AR_TPC, powerVal); |
356 | |
357 | if (!ar5416InitCal(ah, chan)) |
358 | FAIL(HAL_ESELFTEST); |
359 | |
360 | AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ |
361 | |
362 | if (bChannelChange) { |
363 | if (!(ichan->privFlags & CHANNEL_DFS)) |
364 | ichan->privFlags &= ~CHANNEL_INTERFERENCE; |
365 | chan->channelFlags = ichan->channelFlags; |
366 | chan->privFlags = ichan->privFlags; |
367 | chan->maxRegTxPower = ichan->maxRegTxPower; |
368 | chan->maxTxPower = ichan->maxTxPower; |
369 | chan->minTxPower = ichan->minTxPower; |
370 | } |
371 | |
372 | HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n" , __func__); |
373 | |
374 | OS_MARK(ah, AH_MARK_RESET_DONE, 0); |
375 | |
376 | return AH_TRUE; |
377 | bad: |
378 | OS_MARK(ah, AH_MARK_RESET_DONE, ecode); |
379 | if (status != AH_NULL) |
380 | *status = ecode; |
381 | return AH_FALSE; |
382 | #undef FAIL |
383 | #undef N |
384 | } |
385 | |
386 | #if 0 |
387 | /* |
388 | * This channel change evaluates whether the selected hardware can |
389 | * perform a synthesizer-only channel change (no reset). If the |
390 | * TX is not stopped, or the RFBus cannot be granted in the given |
391 | * time, the function returns false as a reset is necessary |
392 | */ |
393 | HAL_BOOL |
394 | ar5416ChannelChange(struct ath_hal *ah, HAL_CHANNEL *chan) |
395 | { |
396 | uint32_t ulCount; |
397 | uint32_t data, synthDelay, qnum; |
398 | uint16_t rfXpdGain[4]; |
399 | struct ath_hal_5212 *ahp = AH5212(ah); |
400 | HAL_CHANNEL_INTERNAL *ichan; |
401 | |
402 | /* |
403 | * Map public channel to private. |
404 | */ |
405 | ichan = ath_hal_checkchannel(ah, chan); |
406 | |
407 | /* TX must be stopped or RF Bus grant will not work */ |
408 | for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) { |
409 | if (ar5212NumTxPending(ah, qnum)) { |
410 | HALDEBUG(ah, HAL_DEBUG_ANY, |
411 | "%s: frames pending on queue %d\n" , __func__, qnum); |
412 | return AH_FALSE; |
413 | } |
414 | } |
415 | |
416 | /* |
417 | * Kill last Baseband Rx Frame - Request analog bus grant |
418 | */ |
419 | OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST); |
420 | if (!ath_hal_wait(ah, AR_PHY_RFBUS_GNT, AR_PHY_RFBUS_GRANT_EN, AR_PHY_RFBUS_GRANT_EN)) { |
421 | HALDEBUG(ah, HAL_DEBUG_ANY, "%s: could not kill baseband rx\n" , |
422 | __func__); |
423 | return AH_FALSE; |
424 | } |
425 | |
426 | ar5416Set11nRegs(ah, chan); /* NB: setup 5416-specific regs */ |
427 | |
428 | /* Change the synth */ |
429 | if (!ar5212SetChannel(ah, ichan)) |
430 | return AH_FALSE; |
431 | |
432 | /* Setup the transmit power values. */ |
433 | if (!_ar5416SetTransmitPower(ah, ichan, rfXpdGain)) { |
434 | HALDEBUG(ah, HAL_DEBUG_ANY, |
435 | "%s: error init'ing transmit power\n" , __func__); |
436 | return AH_FALSE; |
437 | } |
438 | |
439 | /* |
440 | * Wait for the frequency synth to settle (synth goes on |
441 | * via PHY_ACTIVE_EN). Read the phy active delay register. |
442 | * Value is in 100ns increments. |
443 | */ |
444 | data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; |
445 | if (IS_CHAN_CCK(ichan)) { |
446 | synthDelay = (4 * data) / 22; |
447 | } else { |
448 | synthDelay = data / 10; |
449 | } |
450 | |
451 | OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); |
452 | |
453 | /* Release the RFBus Grant */ |
454 | OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); |
455 | |
456 | /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ |
457 | if (IS_CHAN_OFDM(ichan)|| IS_CHAN_HT(chan)) { |
458 | if (ahp->ah_eeprom.ee_version >= AR_EEPROM_VER5_3 && |
459 | !IS_CHAN_B(chan)) |
460 | ar5212SetSpurMitigation(ah, ichan); |
461 | ar5416SetDeltaSlope(ah, ichan); |
462 | } |
463 | |
464 | /* XXX spur mitigation for Melin */ |
465 | |
466 | /* Copy over internal channel flags to public hal channel */ |
467 | |
468 | if (!(ichan->privFlags & CHANNEL_DFS)) |
469 | ichan->privFlags &= ~CHANNEL_INTERFERENCE; |
470 | chan->channelFlags = ichan->channelFlags; |
471 | chan->privFlags = ichan->privFlags; |
472 | chan->maxRegTxPower = ichan->maxRegTxPower; |
473 | chan->maxTxPower = ichan->maxTxPower; |
474 | chan->minTxPower = ichan->minTxPower; |
475 | AH_PRIVATE(ah)->ah_curchan->ah_channel_time=0; |
476 | AH_PRIVATE(ah)->ah_curchan->ah_tsf_last = ar5212GetTsf64(ah); |
477 | ar5212TxEnable(ah,AH_TRUE); |
478 | return AH_TRUE; |
479 | } |
480 | #endif |
481 | |
482 | static void |
483 | ar5416InitDMA(struct ath_hal *ah) |
484 | { |
485 | struct ath_hal_5212 *ahp = AH5212(ah); |
486 | |
487 | /* |
488 | * set AHB_MODE not to do cacheline prefetches |
489 | */ |
490 | OS_REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); |
491 | |
492 | /* |
493 | * let mac dma reads be in 128 byte chunks |
494 | */ |
495 | OS_REG_WRITE(ah, AR_TXCFG, |
496 | (OS_REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK) | AR_TXCFG_DMASZ_128B); |
497 | |
498 | /* |
499 | * let mac dma writes be in 128 byte chunks |
500 | */ |
501 | OS_REG_WRITE(ah, AR_RXCFG, |
502 | (OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B); |
503 | |
504 | /* |
505 | * restore TX trigger level |
506 | */ |
507 | OS_REG_WRITE(ah, AR_TXCFG, |
508 | (OS_REG_READ(ah, AR_TXCFG) &~ AR_FTRIG) | |
509 | SM(ahp->ah_txTrigLev, AR_FTRIG)); |
510 | |
511 | /* |
512 | * Setup receive FIFO threshold to hold off TX activities |
513 | */ |
514 | OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); |
515 | |
516 | /* |
517 | * reduce the number of usable entries in PCU TXBUF to avoid |
518 | * wrap around. |
519 | */ |
520 | OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE); |
521 | } |
522 | |
523 | static void |
524 | ar5416InitBB(struct ath_hal *ah, HAL_CHANNEL *chan) |
525 | { |
526 | uint32_t synthDelay; |
527 | |
528 | /* |
529 | * Wait for the frequency synth to settle (synth goes on |
530 | * via AR_PHY_ACTIVE_EN). Read the phy active delay register. |
531 | * Value is in 100ns increments. |
532 | */ |
533 | synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; |
534 | if (IS_CHAN_CCK(chan)) { |
535 | synthDelay = (4 * synthDelay) / 22; |
536 | } else { |
537 | synthDelay /= 10; |
538 | } |
539 | |
540 | /* Turn on PLL on 5416 */ |
541 | HALDEBUG(ah, HAL_DEBUG_RESET, "%s %s channel\n" , |
542 | __func__, IS_CHAN_5GHZ(chan) ? "5GHz" : "2GHz" ); |
543 | ar5416InitPLL(ah, chan); |
544 | |
545 | /* Activate the PHY (includes baseband activate and synthesizer on) */ |
546 | OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); |
547 | |
548 | /* |
549 | * If the AP starts the calibration before the base band timeout |
550 | * completes we could get rx_clear false triggering. Add an |
551 | * extra BASE_ACTIVATE_DELAY usecs to ensure this condition |
552 | * does not happen. |
553 | */ |
554 | if (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) { |
555 | OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY); |
556 | } else if (IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan)) { |
557 | OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY); |
558 | } else { |
559 | OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); |
560 | } |
561 | } |
562 | |
563 | static void |
564 | ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode) |
565 | { |
566 | struct ath_hal_5212 *ahp = AH5212(ah); |
567 | |
568 | /* |
569 | * Setup interrupt handling. Note that ar5212ResetTxQueue |
570 | * manipulates the secondary IMR's as queues are enabled |
571 | * and disabled. This is done with RMW ops to insure the |
572 | * settings we make here are preserved. |
573 | */ |
574 | ahp->ah_maskReg = AR_IMR_TXERR | AR_IMR_TXURN |
575 | | AR_IMR_RXERR | AR_IMR_RXORN |
576 | | AR_IMR_BCNMISC; |
577 | |
578 | #ifdef AR5416_INT_MITIGATION |
579 | ahp->ah_maskReg |= AR_IMR_TXINTM | AR_IMR_RXINTM |
580 | | AR_IMR_TXMINTR | AR_IMR_RXMINTR; |
581 | #else |
582 | ahp->ah_maskReg |= AR_IMR_TXOK | AR_IMR_RXOK; |
583 | #endif |
584 | if (opmode == HAL_M_HOSTAP) |
585 | ahp->ah_maskReg |= AR_IMR_MIB; |
586 | OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); |
587 | /* Enable bus errors that are OR'd to set the HIUERR bit */ |
588 | |
589 | #if 0 |
590 | OS_REG_WRITE(ah, AR_IMR_S2, |
591 | OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST); |
592 | #endif |
593 | } |
594 | |
595 | static void |
596 | ar5416InitQoS(struct ath_hal *ah) |
597 | { |
598 | /* QoS support */ |
599 | OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */ |
600 | OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */ |
601 | |
602 | /* Turn on NOACK Support for QoS packets */ |
603 | OS_REG_WRITE(ah, AR_NOACK, |
604 | SM(2, AR_NOACK_2BIT_VALUE) | |
605 | SM(5, AR_NOACK_BIT_OFFSET) | |
606 | SM(0, AR_NOACK_BYTE_OFFSET)); |
607 | |
608 | /* |
609 | * initialize TXOP for all TIDs |
610 | */ |
611 | OS_REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); |
612 | OS_REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); |
613 | OS_REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); |
614 | OS_REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); |
615 | OS_REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); |
616 | } |
617 | |
618 | static void |
619 | ar5416InitUserSettings(struct ath_hal *ah) |
620 | { |
621 | struct ath_hal_5212 *ahp = AH5212(ah); |
622 | |
623 | /* Restore user-specified settings */ |
624 | if (ahp->ah_miscMode != 0) |
625 | OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); |
626 | if (ahp->ah_sifstime != (u_int) -1) |
627 | ar5212SetSifsTime(ah, ahp->ah_sifstime); |
628 | if (ahp->ah_slottime != (u_int) -1) |
629 | ar5212SetSlotTime(ah, ahp->ah_slottime); |
630 | if (ahp->ah_acktimeout != (u_int) -1) |
631 | ar5212SetAckTimeout(ah, ahp->ah_acktimeout); |
632 | if (ahp->ah_ctstimeout != (u_int) -1) |
633 | ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout); |
634 | if (AH_PRIVATE(ah)->ah_diagreg != 0) |
635 | OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); |
636 | #if 0 /* XXX Todo */ |
637 | if (ahp->ah_globaltxtimeout != (u_int) -1) |
638 | ar5416SetGlobalTxTimeout(ah, ahp->ah_globaltxtimeout); |
639 | #endif |
640 | } |
641 | |
642 | /* |
643 | * Places the hardware into reset and then pulls it out of reset |
644 | */ |
645 | HAL_BOOL |
646 | ar5416ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan) |
647 | { |
648 | OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->channel : 0); |
649 | /* |
650 | * Warm reset is optimistic. |
651 | */ |
652 | if (AR_SREV_MERLIN_20_OR_LATER(ah) && |
653 | ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { |
654 | if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) |
655 | return AH_FALSE; |
656 | } else { |
657 | if (!ar5416SetResetReg(ah, HAL_RESET_WARM)) |
658 | return AH_FALSE; |
659 | } |
660 | |
661 | /* Bring out of sleep mode (AGAIN) */ |
662 | if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) |
663 | return AH_FALSE; |
664 | |
665 | ar5416InitPLL(ah, chan); |
666 | |
667 | /* |
668 | * Perform warm reset before the mode/PLL/turbo registers |
669 | * are changed in order to deactivate the radio. Mode changes |
670 | * with an active radio can result in corrupted shifts to the |
671 | * radio device. |
672 | */ |
673 | if (chan != AH_NULL) { |
674 | uint32_t rfMode; |
675 | |
676 | /* treat channel B as channel G , no B mode suport in owl */ |
677 | rfMode = (IS_CHAN_G(chan) || IS_CHAN_B(chan)) ? |
678 | AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; |
679 | if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { |
680 | /* phy mode bits for 5GHz channels require Fast Clock */ |
681 | rfMode |= AR_PHY_MODE_DYNAMIC |
682 | | AR_PHY_MODE_DYN_CCK_DISABLE; |
683 | } else if (!AR_SREV_MERLIN_10_OR_LATER(ah)) { |
684 | rfMode |= (IS_CHAN_5GHZ(chan)) ? |
685 | AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; |
686 | } |
687 | OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); |
688 | } |
689 | return AH_TRUE; |
690 | } |
691 | |
692 | /* |
693 | * Delta slope coefficient computation. |
694 | * Required for OFDM operation. |
695 | */ |
696 | static void |
697 | ar5416GetDeltaSlopeValues(struct ath_hal *ah, uint32_t coef_scaled, |
698 | uint32_t *coef_mantissa, uint32_t *coef_exponent) |
699 | { |
700 | #define COEF_SCALE_S 24 |
701 | uint32_t coef_exp, coef_man; |
702 | /* |
703 | * ALGO -> coef_exp = 14-floor(log2(coef)); |
704 | * floor(log2(x)) is the highest set bit position |
705 | */ |
706 | for (coef_exp = 31; coef_exp > 0; coef_exp--) |
707 | if ((coef_scaled >> coef_exp) & 0x1) |
708 | break; |
709 | /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */ |
710 | HALASSERT(coef_exp); |
711 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); |
712 | |
713 | /* |
714 | * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5); |
715 | * The coefficient is already shifted up for scaling |
716 | */ |
717 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); |
718 | |
719 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); |
720 | *coef_exponent = coef_exp - 16; |
721 | |
722 | #undef COEF_SCALE_S |
723 | } |
724 | |
725 | void |
726 | ar5416SetDeltaSlope(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) |
727 | { |
728 | #define INIT_CLOCKMHZSCALED 0x64000000 |
729 | uint32_t coef_scaled, ds_coef_exp, ds_coef_man; |
730 | uint32_t clockMhzScaled = INIT_CLOCKMHZSCALED; |
731 | |
732 | CHAN_CENTERS centers; |
733 | |
734 | if (IS_CHAN_TURBO(chan)) |
735 | clockMhzScaled *= 2; |
736 | /* half and quarter rate can divide the scaled clock by 2 or 4 respectively */ |
737 | /* scale for selected channel bandwidth */ |
738 | if (IS_CHAN_HALF_RATE(chan)) { |
739 | clockMhzScaled = clockMhzScaled >> 1; |
740 | } else if (IS_CHAN_QUARTER_RATE(chan)) { |
741 | clockMhzScaled = clockMhzScaled >> 2; |
742 | } |
743 | |
744 | /* |
745 | * ALGO -> coef = 1e8/fcarrier*fclock/40; |
746 | * scaled coef to provide precision for this floating calculation |
747 | */ |
748 | ar5416GetChannelCenters(ah, chan, ¢ers); |
749 | coef_scaled = clockMhzScaled / centers.synth_center; |
750 | |
751 | ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); |
752 | |
753 | OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, |
754 | AR_PHY_TIMING3_DSC_MAN, ds_coef_man); |
755 | OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, |
756 | AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); |
757 | |
758 | /* |
759 | * For Short GI, |
760 | * scaled coeff is 9/10 that of normal coeff |
761 | */ |
762 | coef_scaled = (9 * coef_scaled)/10; |
763 | |
764 | ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); |
765 | |
766 | /* for short gi */ |
767 | OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI, |
768 | AR_PHY_HALFGI_DSC_MAN, ds_coef_man); |
769 | OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI, |
770 | AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); |
771 | #undef INIT_CLOCKMHZSCALED |
772 | } |
773 | |
774 | /* |
775 | * Set a limit on the overall output power. Used for dynamic |
776 | * transmit power control and the like. |
777 | * |
778 | * NB: limit is in units of 0.5 dbM. |
779 | */ |
780 | HAL_BOOL |
781 | ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) |
782 | { |
783 | uint16_t dummyXpdGains[2]; |
784 | |
785 | AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); |
786 | return _ar5416SetTransmitPower(ah, AH_PRIVATE(ah)->ah_curchan, |
787 | dummyXpdGains); |
788 | } |
789 | |
790 | HAL_BOOL |
791 | ar5416GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL *chans, uint32_t nchans) |
792 | { |
793 | struct ath_hal_5212 *ahp = AH5212(ah); |
794 | int16_t minPower, maxPower; |
795 | HAL_CHANNEL *chan; |
796 | int i; |
797 | |
798 | /* |
799 | * Get Pier table max and min powers. |
800 | */ |
801 | for (i = 0; i < nchans; i++) { |
802 | chan = &chans[i]; |
803 | if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) { |
804 | /* NB: rf code returns 1/4 dBm units, convert */ |
805 | chan->maxTxPower = maxPower / 2; |
806 | chan->minTxPower = minPower / 2; |
807 | } else { |
808 | HALDEBUG(ah, HAL_DEBUG_ANY, |
809 | "%s: no min/max power for %u/0x%x\n" , |
810 | __func__, chan->channel, chan->channelFlags); |
811 | chan->maxTxPower = AR5416_MAX_RATE_POWER; |
812 | chan->minTxPower = 0; |
813 | } |
814 | } |
815 | #ifdef AH_DEBUG |
816 | for (i=0; i<nchans; i++) { |
817 | HALDEBUG(ah, HAL_DEBUG_RESET, |
818 | "Chan %d: MaxPow = %d MinPow = %d\n" , |
819 | chans[i].channel,chans[i].maxTxPower, chans[i].minTxPower); |
820 | } |
821 | #endif |
822 | return AH_TRUE; |
823 | } |
824 | |
825 | /* XXX gag, this is sick */ |
826 | typedef enum Ar5416_Rates { |
827 | rate6mb, rate9mb, rate12mb, rate18mb, |
828 | rate24mb, rate36mb, rate48mb, rate54mb, |
829 | rate1l, rate2l, rate2s, rate5_5l, |
830 | rate5_5s, rate11l, rate11s, rateXr, |
831 | rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, |
832 | rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, |
833 | rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, |
834 | rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, |
835 | rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, |
836 | Ar5416RateSize |
837 | } AR5416_RATES; |
838 | |
839 | /************************************************************** |
840 | * ar5416SetTransmitPower |
841 | * |
842 | * Set the transmit power in the baseband for the given |
843 | * operating channel and mode. |
844 | */ |
845 | static HAL_BOOL |
846 | _ar5416SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t *rfXpdGain) |
847 | { |
848 | #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) |
849 | #define N(a) (sizeof (a) / sizeof (a[0])) |
850 | |
851 | MODAL_EEP_HEADER *pModal; |
852 | struct ath_hal_5212 *ahp = AH5212(ah); |
853 | int16_t ratesArray[Ar5416RateSize]; |
854 | int16_t txPowerIndexOffset = 0; |
855 | uint8_t ht40PowerIncForPdadc = 2; |
856 | int i; |
857 | |
858 | uint16_t cfgCtl; |
859 | uint16_t powerLimit; |
860 | uint16_t twiceAntennaReduction; |
861 | uint16_t twiceMaxRegulatoryPower; |
862 | int16_t maxPower; |
863 | HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; |
864 | struct ar5416eeprom *pEepData = &ee->ee_base; |
865 | |
866 | HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); |
867 | |
868 | /* Setup info for the actual eeprom */ |
869 | ath_hal_memzero(ratesArray, sizeof(ratesArray)); |
870 | cfgCtl = ath_hal_getctl(ah, (HAL_CHANNEL *)chan); |
871 | powerLimit = chan->maxRegTxPower * 2; |
872 | twiceAntennaReduction = chan->antennaMax; |
873 | twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); |
874 | pModal = &pEepData->modalHeader[IS_CHAN_2GHZ(chan)]; |
875 | HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n" , |
876 | __func__,chan->channel, cfgCtl ); |
877 | |
878 | if (IS_EEP_MINOR_V2(ah)) { |
879 | ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; |
880 | } |
881 | |
882 | if (!ar5416SetPowerPerRateTable(ah, pEepData, chan, |
883 | &ratesArray[0],cfgCtl, |
884 | twiceAntennaReduction, |
885 | twiceMaxRegulatoryPower, powerLimit)) { |
886 | HALDEBUG(ah, HAL_DEBUG_ANY, |
887 | "%s: unable to set tx power per rate table\n" , __func__); |
888 | return AH_FALSE; |
889 | } |
890 | |
891 | if (!ar5416SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { |
892 | HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n" , |
893 | __func__); |
894 | return AH_FALSE; |
895 | } |
896 | |
897 | maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]); |
898 | |
899 | if (IS_CHAN_2GHZ(chan)) { |
900 | maxPower = AH_MAX(maxPower, ratesArray[rate1l]); |
901 | } |
902 | |
903 | if (IS_CHAN_HT40(chan)) { |
904 | maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]); |
905 | } |
906 | |
907 | ahp->ah_tx6PowerInHalfDbm = maxPower; |
908 | AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; |
909 | ahp->ah_txPowerIndexOffset = txPowerIndexOffset; |
910 | |
911 | /* |
912 | * txPowerIndexOffset is set by the SetPowerTable() call - |
913 | * adjust the rate table (0 offset if rates EEPROM not loaded) |
914 | */ |
915 | for (i = 0; i < N(ratesArray); i++) { |
916 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); |
917 | if (ratesArray[i] > AR5416_MAX_RATE_POWER) |
918 | ratesArray[i] = AR5416_MAX_RATE_POWER; |
919 | } |
920 | |
921 | #ifdef AH_EEPROM_DUMP |
922 | ar5416PrintPowerPerRate(ah, ratesArray); |
923 | #endif |
924 | |
925 | /* Write the OFDM power per rate set */ |
926 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, |
927 | POW_SM(ratesArray[rate18mb], 24) |
928 | | POW_SM(ratesArray[rate12mb], 16) |
929 | | POW_SM(ratesArray[rate9mb], 8) |
930 | | POW_SM(ratesArray[rate6mb], 0) |
931 | ); |
932 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, |
933 | POW_SM(ratesArray[rate54mb], 24) |
934 | | POW_SM(ratesArray[rate48mb], 16) |
935 | | POW_SM(ratesArray[rate36mb], 8) |
936 | | POW_SM(ratesArray[rate24mb], 0) |
937 | ); |
938 | |
939 | if (IS_CHAN_2GHZ(chan)) { |
940 | /* Write the CCK power per rate set */ |
941 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, |
942 | POW_SM(ratesArray[rate2s], 24) |
943 | | POW_SM(ratesArray[rate2l], 16) |
944 | | POW_SM(ratesArray[rateXr], 8) /* XR target power */ |
945 | | POW_SM(ratesArray[rate1l], 0) |
946 | ); |
947 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, |
948 | POW_SM(ratesArray[rate11s], 24) |
949 | | POW_SM(ratesArray[rate11l], 16) |
950 | | POW_SM(ratesArray[rate5_5s], 8) |
951 | | POW_SM(ratesArray[rate5_5l], 0) |
952 | ); |
953 | HALDEBUG(ah, HAL_DEBUG_RESET, |
954 | "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n" , |
955 | __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3), |
956 | OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); |
957 | } |
958 | |
959 | /* Write the HT20 power per rate set */ |
960 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, |
961 | POW_SM(ratesArray[rateHt20_3], 24) |
962 | | POW_SM(ratesArray[rateHt20_2], 16) |
963 | | POW_SM(ratesArray[rateHt20_1], 8) |
964 | | POW_SM(ratesArray[rateHt20_0], 0) |
965 | ); |
966 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, |
967 | POW_SM(ratesArray[rateHt20_7], 24) |
968 | | POW_SM(ratesArray[rateHt20_6], 16) |
969 | | POW_SM(ratesArray[rateHt20_5], 8) |
970 | | POW_SM(ratesArray[rateHt20_4], 0) |
971 | ); |
972 | |
973 | if (IS_CHAN_HT40(chan)) { |
974 | /* Write the HT40 power per rate set */ |
975 | /* Correct PAR difference between HT40 and HT20/LEGACY */ |
976 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, |
977 | POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24) |
978 | | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16) |
979 | | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8) |
980 | | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0) |
981 | ); |
982 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, |
983 | POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24) |
984 | | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16) |
985 | | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8) |
986 | | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0) |
987 | ); |
988 | /* Write the Dup/Ext 40 power per rate set */ |
989 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, |
990 | POW_SM(ratesArray[rateExtOfdm], 24) |
991 | | POW_SM(ratesArray[rateExtCck], 16) |
992 | | POW_SM(ratesArray[rateDupOfdm], 8) |
993 | | POW_SM(ratesArray[rateDupCck], 0) |
994 | ); |
995 | } |
996 | |
997 | /* Write the Power subtraction for dynamic chain changing, for per-packet powertx */ |
998 | OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, |
999 | POW_SM(pModal->pwrDecreaseFor3Chain, 6) |
1000 | | POW_SM(pModal->pwrDecreaseFor2Chain, 0) |
1001 | ); |
1002 | return AH_TRUE; |
1003 | #undef POW_SM |
1004 | #undef N |
1005 | } |
1006 | |
1007 | HAL_BOOL |
1008 | ar5416SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL *chan, |
1009 | uint16_t *rfXpdGain) |
1010 | { |
1011 | return _ar5416SetTransmitPower(ah, ath_hal_checkchannel(ah, chan), |
1012 | rfXpdGain); |
1013 | } |
1014 | |
1015 | /* |
1016 | * Exported call to check for a recent gain reading and return |
1017 | * the current state of the thermal calibration gain engine. |
1018 | */ |
1019 | HAL_RFGAIN |
1020 | ar5416GetRfgain(struct ath_hal *ah) |
1021 | { |
1022 | return HAL_RFGAIN_INACTIVE; |
1023 | } |
1024 | |
1025 | /* |
1026 | * Places all of hardware into reset |
1027 | */ |
1028 | HAL_BOOL |
1029 | ar5416Disable(struct ath_hal *ah) |
1030 | { |
1031 | if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) |
1032 | return AH_FALSE; |
1033 | return ar5416SetResetReg(ah, HAL_RESET_COLD); |
1034 | } |
1035 | |
1036 | /* |
1037 | * Places the PHY and Radio chips into reset. A full reset |
1038 | * must be called to leave this state. The PCI/MAC/PCU are |
1039 | * not placed into reset as we must receive interrupt to |
1040 | * re-enable the hardware. |
1041 | */ |
1042 | HAL_BOOL |
1043 | ar5416PhyDisable(struct ath_hal *ah) |
1044 | { |
1045 | return ar5416SetResetReg(ah, HAL_RESET_WARM); |
1046 | } |
1047 | |
1048 | /* |
1049 | * Write the given reset bit mask into the reset register |
1050 | */ |
1051 | HAL_BOOL |
1052 | ar5416SetResetReg(struct ath_hal *ah, uint32_t type) |
1053 | { |
1054 | switch (type) { |
1055 | case HAL_RESET_POWER_ON: |
1056 | return ar5416SetResetPowerOn(ah); |
1057 | case HAL_RESET_WARM: |
1058 | case HAL_RESET_COLD: |
1059 | return ar5416SetReset(ah, type); |
1060 | default: |
1061 | HALASSERT(AH_FALSE); |
1062 | return AH_FALSE; |
1063 | } |
1064 | } |
1065 | |
1066 | static HAL_BOOL |
1067 | ar5416SetResetPowerOn(struct ath_hal *ah) |
1068 | { |
1069 | /* Power On Reset (Hard Reset) */ |
1070 | |
1071 | /* |
1072 | * Set force wake |
1073 | * |
1074 | * If the MAC was running, previously calling |
1075 | * reset will wake up the MAC but it may go back to sleep |
1076 | * before we can start polling. |
1077 | * Set force wake stops that |
1078 | * This must be called before initiating a hard reset. |
1079 | */ |
1080 | OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
1081 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); |
1082 | |
1083 | /* |
1084 | * RTC reset and clear |
1085 | */ |
1086 | OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); |
1087 | OS_REG_WRITE(ah, AR_RTC_RESET, 0); |
1088 | OS_DELAY(20); |
1089 | OS_REG_WRITE(ah, AR_RC, 0); |
1090 | |
1091 | OS_REG_WRITE(ah, AR_RTC_RESET, 1); |
1092 | |
1093 | /* |
1094 | * Poll till RTC is ON |
1095 | */ |
1096 | if (!ath_hal_wait(ah, AR_RTC_STATUS, AR_RTC_PM_STATUS_M, AR_RTC_STATUS_ON)) { |
1097 | HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC not waking up\n" , __func__); |
1098 | return AH_FALSE; |
1099 | } |
1100 | |
1101 | return ar5416SetReset(ah, HAL_RESET_COLD); |
1102 | } |
1103 | |
1104 | static HAL_BOOL |
1105 | ar5416SetReset(struct ath_hal *ah, int type) |
1106 | { |
1107 | uint32_t tmpReg; |
1108 | |
1109 | /* |
1110 | * Force wake |
1111 | */ |
1112 | OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
1113 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); |
1114 | |
1115 | /* |
1116 | * Reset AHB |
1117 | */ |
1118 | tmpReg = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); |
1119 | if (tmpReg & (AR_INTR_SYNC_LOCAL_TIMEOUT|AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { |
1120 | OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
1121 | OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF); |
1122 | } else { |
1123 | OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); |
1124 | } |
1125 | |
1126 | /* |
1127 | * Set Mac(BB,Phy) Warm Reset |
1128 | */ |
1129 | switch (type) { |
1130 | case HAL_RESET_WARM: |
1131 | OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM); |
1132 | break; |
1133 | case HAL_RESET_COLD: |
1134 | OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM|AR_RTC_RC_MAC_COLD); |
1135 | break; |
1136 | default: |
1137 | HALASSERT(AH_FALSE); |
1138 | break; |
1139 | } |
1140 | |
1141 | /* |
1142 | * Clear resets and force wakeup |
1143 | */ |
1144 | OS_REG_WRITE(ah, AR_RTC_RC, 0); |
1145 | if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) { |
1146 | HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC stuck in MAC reset\n" , __func__); |
1147 | return AH_FALSE; |
1148 | } |
1149 | |
1150 | /* Clear AHB reset */ |
1151 | OS_REG_WRITE(ah, AR_RC, 0); |
1152 | |
1153 | /* Set register and descriptor swapping on |
1154 | * Bigendian platforms on cold reset |
1155 | */ |
1156 | if (type == HAL_RESET_COLD) { |
1157 | #ifdef __BIG_ENDIAN__ |
1158 | uint32_t mask; |
1159 | |
1160 | HALDEBUG(ah, HAL_DEBUG_RESET, |
1161 | "%s Applying descriptor swap\n" , __func__); |
1162 | |
1163 | mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG; |
1164 | #ifndef AH_NEED_DESC_SWAP |
1165 | mask |= AR_CFG_SWTD; |
1166 | #endif |
1167 | OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask)); |
1168 | #else |
1169 | OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); |
1170 | #endif |
1171 | } |
1172 | |
1173 | ar5416InitPLL(ah, AH_NULL); |
1174 | |
1175 | return AH_TRUE; |
1176 | } |
1177 | |
1178 | #ifndef IS_5GHZ_FAST_CLOCK_EN |
1179 | #define IS_5GHZ_FAST_CLOCK_EN(ah, chan) AH_FALSE |
1180 | #endif |
1181 | |
1182 | static void |
1183 | ar5416InitPLL(struct ath_hal *ah, HAL_CHANNEL *chan) |
1184 | { |
1185 | uint32_t pll; |
1186 | |
1187 | if (AR_SREV_MERLIN_10_OR_LATER(ah)) { |
1188 | pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); |
1189 | |
1190 | if (chan != AH_NULL && IS_CHAN_HALF_RATE(chan)) { |
1191 | pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); |
1192 | } else if (chan && IS_CHAN_QUARTER_RATE(chan)) { |
1193 | pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); |
1194 | } |
1195 | if (AR_SREV_MERLIN_20(ah) && |
1196 | chan != AH_NULL && IS_CHAN_5GHZ(chan)) { |
1197 | pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); |
1198 | |
1199 | /* |
1200 | * PLL WAR for Merlin 2.0/2.1 |
1201 | * When doing fast clock, set PLL to 0x142c |
1202 | * Else, set PLL to 0x2850 to prevent reset-to-reset variation |
1203 | */ |
1204 | if (AR_SREV_MERLIN_20(ah)) { |
1205 | if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { |
1206 | pll = 0x142c; |
1207 | } else { |
1208 | pll = 0x2850; |
1209 | } |
1210 | } |
1211 | } else { |
1212 | pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); |
1213 | } |
1214 | } else if (AR_SREV_SOWL_10_OR_LATER(ah)) { |
1215 | pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); |
1216 | |
1217 | if (chan != AH_NULL && IS_CHAN_HALF_RATE(chan)) { |
1218 | pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); |
1219 | } else if (chan && IS_CHAN_QUARTER_RATE(chan)) { |
1220 | pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); |
1221 | } |
1222 | if (chan != AH_NULL && IS_CHAN_5GHZ(chan)) { |
1223 | pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV); |
1224 | } else { |
1225 | pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV); |
1226 | } |
1227 | } else { |
1228 | pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; |
1229 | |
1230 | if (chan != AH_NULL && IS_CHAN_HALF_RATE(chan)) { |
1231 | pll |= SM(0x1, AR_RTC_PLL_CLKSEL); |
1232 | } else if (chan != AH_NULL && IS_CHAN_QUARTER_RATE(chan)) { |
1233 | pll |= SM(0x2, AR_RTC_PLL_CLKSEL); |
1234 | } |
1235 | if (chan != AH_NULL && IS_CHAN_5GHZ(chan)) { |
1236 | pll |= SM(0xa, AR_RTC_PLL_DIV); |
1237 | } else { |
1238 | pll |= SM(0xb, AR_RTC_PLL_DIV); |
1239 | } |
1240 | } |
1241 | OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
1242 | |
1243 | /* TODO: |
1244 | * For multi-band owl, switch between bands by reiniting the PLL. |
1245 | */ |
1246 | |
1247 | OS_DELAY(RTC_PLL_SETTLE_DELAY); |
1248 | |
1249 | OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); |
1250 | } |
1251 | |
1252 | /* |
1253 | * Read EEPROM header info and program the device for correct operation |
1254 | * given the channel value. |
1255 | */ |
1256 | HAL_BOOL |
1257 | ar5416SetBoardValues(struct ath_hal *ah, HAL_CHANNEL *_chan) |
1258 | { |
1259 | HAL_CHANNEL_INTERNAL *chan; |
1260 | const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; |
1261 | const struct ar5416eeprom *eep = &ee->ee_base; |
1262 | const MODAL_EEP_HEADER *pModal; |
1263 | int i, regChainOffset; |
1264 | uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */ |
1265 | |
1266 | HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); |
1267 | |
1268 | chan = ath_hal_checkchannel(ah, _chan); |
1269 | pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); |
1270 | |
1271 | txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; /* workaround for eeprom versions <= 14.2 */ |
1272 | |
1273 | OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); |
1274 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { |
1275 | if (AR_SREV_MERLIN(ah)) { |
1276 | if (i >= 2) break; |
1277 | } |
1278 | if (AR_SREV_OWL_20_OR_LATER(ah) && |
1279 | (AH5416(ah)->ah_rx_chainmask == 0x5 || |
1280 | AH5416(ah)->ah_tx_chainmask == 0x5) && i != 0) { |
1281 | /* Regs are swapped from chain 2 to 1 for 5416 2_0 with |
1282 | * only chains 0 and 2 populated |
1283 | */ |
1284 | regChainOffset = (i == 1) ? 0x2000 : 0x1000; |
1285 | } else { |
1286 | regChainOffset = i * 0x1000; |
1287 | } |
1288 | |
1289 | OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]); |
1290 | OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset, |
1291 | (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) & |
1292 | ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | |
1293 | SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | |
1294 | SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); |
1295 | |
1296 | /* |
1297 | * Large signal upgrade. |
1298 | * XXX update |
1299 | */ |
1300 | |
1301 | if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) { |
1302 | OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset, |
1303 | (OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) | |
1304 | SM(IS_EEP_MINOR_V3(ah) ? pModal->txRxAttenCh[i] : txRxAttenLocal, |
1305 | AR_PHY_RXGAIN_TXRX_ATTEN)); |
1306 | |
1307 | OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, |
1308 | (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) | |
1309 | SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); |
1310 | } |
1311 | } |
1312 | |
1313 | OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling); |
1314 | OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize); |
1315 | OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize); |
1316 | OS_REG_WRITE(ah, AR_PHY_RF_CTL4, |
1317 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1318 | | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1319 | | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
1320 | | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); |
1321 | |
1322 | OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn); |
1323 | |
1324 | if (AR_SREV_MERLIN_10_OR_LATER(ah)) { |
1325 | OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, |
1326 | pModal->thresh62); |
1327 | OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, |
1328 | pModal->thresh62); |
1329 | } else { |
1330 | OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, |
1331 | pModal->thresh62); |
1332 | OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA_THRESH62, |
1333 | pModal->thresh62); |
1334 | } |
1335 | |
1336 | /* Minor Version Specific application */ |
1337 | if (IS_EEP_MINOR_V2(ah)) { |
1338 | OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart); |
1339 | OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn); |
1340 | } |
1341 | |
1342 | if (IS_EEP_MINOR_V3(ah)) { |
1343 | if (IS_CHAN_HT40(chan)) { |
1344 | /* Overwrite switch settling with HT40 value */ |
1345 | OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); |
1346 | } |
1347 | |
1348 | if ((AR_SREV_OWL_20_OR_LATER(ah)) && |
1349 | ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5)){ |
1350 | /* Reg Offsets are swapped for logical mapping */ |
1351 | OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) | |
1352 | SM(pModal->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN)); |
1353 | OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) | |
1354 | SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN)); |
1355 | OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) | |
1356 | SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN)); |
1357 | OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) | |
1358 | SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN)); |
1359 | } else { |
1360 | OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) | |
1361 | SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN)); |
1362 | OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) | |
1363 | SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN)); |
1364 | OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) | |
1365 | SM(pModal->bswMargin[2],AR_PHY_GAIN_2GHZ_BSW_MARGIN)); |
1366 | OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) | |
1367 | SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN)); |
1368 | } |
1369 | OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN, pModal->bswMargin[0]); |
1370 | OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN, pModal->bswAtten[0]); |
1371 | } |
1372 | return AH_TRUE; |
1373 | } |
1374 | |
1375 | /* |
1376 | * Helper functions common for AP/CB/XB |
1377 | */ |
1378 | |
1379 | /* |
1380 | * ar5416SetPowerPerRateTable |
1381 | * |
1382 | * Sets the transmit power in the baseband for the given |
1383 | * operating channel and mode. |
1384 | */ |
1385 | static HAL_BOOL |
1386 | ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, |
1387 | HAL_CHANNEL_INTERNAL *chan, |
1388 | int16_t *ratesArray, uint16_t cfgCtl, |
1389 | uint16_t AntennaReduction, |
1390 | uint16_t twiceMaxRegulatoryPower, |
1391 | uint16_t powerLimit) |
1392 | { |
1393 | #define N(a) (sizeof(a)/sizeof(a[0])) |
1394 | /* Local defines to distinguish between extension and control CTL's */ |
1395 | #define EXT_ADDITIVE (0x8000) |
1396 | #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) |
1397 | #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) |
1398 | #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) |
1399 | |
1400 | uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; |
1401 | int i; |
1402 | int16_t twiceLargestAntenna; |
1403 | CAL_CTL_DATA *rep; |
1404 | CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; |
1405 | CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; |
1406 | CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; |
1407 | int16_t scaledPower, minCtlPower; |
1408 | |
1409 | #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ |
1410 | #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ |
1411 | static const uint16_t ctlModesFor11a[] = { |
1412 | CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 |
1413 | }; |
1414 | static const uint16_t ctlModesFor11g[] = { |
1415 | CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 |
1416 | }; |
1417 | const uint16_t *pCtlMode; |
1418 | uint16_t numCtlModes, ctlMode, freq; |
1419 | CHAN_CENTERS centers; |
1420 | |
1421 | ar5416GetChannelCenters(ah, chan, ¢ers); |
1422 | |
1423 | /* Compute TxPower reduction due to Antenna Gain */ |
1424 | |
1425 | twiceLargestAntenna = AH_MAX(AH_MAX(pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[0], |
1426 | pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[1]), |
1427 | pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[2]); |
1428 | #if 0 |
1429 | /* Turn it back on if we need to calculate per chain antenna gain reduction */ |
1430 | /* Use only if the expected gain > 6dbi */ |
1431 | /* Chain 0 is always used */ |
1432 | twiceLargestAntenna = pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[0]; |
1433 | |
1434 | /* Look at antenna gains of Chains 1 and 2 if the TX mask is set */ |
1435 | if (ahp->ah_tx_chainmask & 0x2) |
1436 | twiceLargestAntenna = AH_MAX(twiceLargestAntenna, |
1437 | pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[1]); |
1438 | |
1439 | if (ahp->ah_tx_chainmask & 0x4) |
1440 | twiceLargestAntenna = AH_MAX(twiceLargestAntenna, |
1441 | pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[2]); |
1442 | #endif |
1443 | twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); |
1444 | |
1445 | /* XXX setup for 5212 use (really used?) */ |
1446 | ath_hal_eepromSet(ah, |
1447 | IS_CHAN_2GHZ(chan) ? AR_EEP_ANTGAINMAX_2 : AR_EEP_ANTGAINMAX_5, |
1448 | twiceLargestAntenna); |
1449 | |
1450 | /* |
1451 | * scaledPower is the minimum of the user input power level and |
1452 | * the regulatory allowed power level |
1453 | */ |
1454 | scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); |
1455 | |
1456 | /* Reduce scaled Power by number of chains active to get to per chain tx power level */ |
1457 | /* TODO: better value than these? */ |
1458 | switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) { |
1459 | case 1: |
1460 | break; |
1461 | case 2: |
1462 | scaledPower -= pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain; |
1463 | break; |
1464 | case 3: |
1465 | scaledPower -= pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain; |
1466 | break; |
1467 | default: |
1468 | return AH_FALSE; /* Unsupported number of chains */ |
1469 | } |
1470 | |
1471 | scaledPower = AH_MAX(0, scaledPower); |
1472 | |
1473 | /* Get target powers from EEPROM - our baseline for TX Power */ |
1474 | if (IS_CHAN_2GHZ(chan)) { |
1475 | /* Setup for CTL modes */ |
1476 | numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ |
1477 | pCtlMode = ctlModesFor11g; |
1478 | |
1479 | ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, |
1480 | AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); |
1481 | ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, |
1482 | AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); |
1483 | ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, |
1484 | AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); |
1485 | |
1486 | if (IS_CHAN_HT40(chan)) { |
1487 | numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ |
1488 | |
1489 | ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, |
1490 | AR5416_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); |
1491 | /* Get target powers for extension channels */ |
1492 | ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, |
1493 | AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); |
1494 | ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, |
1495 | AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); |
1496 | } |
1497 | } else { |
1498 | /* Setup for CTL modes */ |
1499 | numCtlModes = N(ctlModesFor11a) - SUB_NUM_CTL_MODES_AT_5G_40; /* CTL_11A, CTL_5GHT20 */ |
1500 | pCtlMode = ctlModesFor11a; |
1501 | |
1502 | ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G, |
1503 | AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); |
1504 | ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT20, |
1505 | AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); |
1506 | |
1507 | if (IS_CHAN_HT40(chan)) { |
1508 | numCtlModes = N(ctlModesFor11a); /* All 5G CTL's */ |
1509 | |
1510 | ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT40, |
1511 | AR5416_NUM_5G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); |
1512 | ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G, |
1513 | AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); |
1514 | } |
1515 | } |
1516 | |
1517 | /* |
1518 | * For MIMO, need to apply regulatory caps individually across dynamically |
1519 | * running modes: CCK, OFDM, HT20, HT40 |
1520 | * |
1521 | * The outer loop walks through each possible applicable runtime mode. |
1522 | * The inner loop walks through each ctlIndex entry in EEPROM. |
1523 | * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. |
1524 | * |
1525 | */ |
1526 | for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { |
1527 | |
1528 | HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || |
1529 | (pCtlMode[ctlMode] == CTL_2GHT40); |
1530 | if (isHt40CtlMode) { |
1531 | freq = centers.ctl_center; |
1532 | } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { |
1533 | freq = centers.ext_center; |
1534 | } else { |
1535 | freq = centers.ctl_center; |
1536 | } |
1537 | |
1538 | /* walk through each CTL index stored in EEPROM */ |
1539 | for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { |
1540 | uint16_t twiceMinEdgePower; |
1541 | |
1542 | /* compare test group from regulatory channel list with test mode from pCtlMode list */ |
1543 | if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || |
1544 | (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == |
1545 | ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { |
1546 | rep = &(pEepData->ctlData[i]); |
1547 | twiceMinEdgePower = ar5416GetMaxEdgePower(freq, |
1548 | rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1], |
1549 | IS_CHAN_2GHZ(chan)); |
1550 | if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { |
1551 | /* Find the minimum of all CTL edge powers that apply to this channel */ |
1552 | twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); |
1553 | } else { |
1554 | /* specific */ |
1555 | twiceMaxEdgePower = twiceMinEdgePower; |
1556 | break; |
1557 | } |
1558 | } |
1559 | } |
1560 | minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); |
1561 | /* Apply ctl mode to correct target power set */ |
1562 | switch(pCtlMode[ctlMode]) { |
1563 | case CTL_11B: |
1564 | for (i = 0; i < N(targetPowerCck.tPow2x); i++) { |
1565 | targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); |
1566 | } |
1567 | break; |
1568 | case CTL_11A: |
1569 | case CTL_11G: |
1570 | for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { |
1571 | targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); |
1572 | } |
1573 | break; |
1574 | case CTL_5GHT20: |
1575 | case CTL_2GHT20: |
1576 | for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { |
1577 | targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); |
1578 | } |
1579 | break; |
1580 | case CTL_11B_EXT: |
1581 | targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); |
1582 | break; |
1583 | case CTL_11A_EXT: |
1584 | case CTL_11G_EXT: |
1585 | targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); |
1586 | break; |
1587 | case CTL_5GHT40: |
1588 | case CTL_2GHT40: |
1589 | for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { |
1590 | targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); |
1591 | } |
1592 | break; |
1593 | default: |
1594 | return AH_FALSE; |
1595 | break; |
1596 | } |
1597 | } /* end ctl mode checking */ |
1598 | |
1599 | /* Set rates Array from collected data */ |
1600 | ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0]; |
1601 | ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; |
1602 | ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; |
1603 | ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; |
1604 | ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; |
1605 | |
1606 | for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { |
1607 | ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; |
1608 | } |
1609 | |
1610 | if (IS_CHAN_2GHZ(chan)) { |
1611 | ratesArray[rate1l] = targetPowerCck.tPow2x[0]; |
1612 | ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; |
1613 | ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; |
1614 | ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; |
1615 | } |
1616 | if (IS_CHAN_HT40(chan)) { |
1617 | for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { |
1618 | ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; |
1619 | } |
1620 | ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; |
1621 | ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; |
1622 | ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; |
1623 | if (IS_CHAN_2GHZ(chan)) { |
1624 | ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; |
1625 | } |
1626 | } |
1627 | return AH_TRUE; |
1628 | #undef EXT_ADDITIVE |
1629 | #undef CTL_11A_EXT |
1630 | #undef CTL_11G_EXT |
1631 | #undef CTL_11B_EXT |
1632 | #undef SUB_NUM_CTL_MODES_AT_5G_40 |
1633 | #undef SUB_NUM_CTL_MODES_AT_2G_40 |
1634 | #undef N |
1635 | } |
1636 | |
1637 | /************************************************************************** |
1638 | * fbin2freq |
1639 | * |
1640 | * Get channel value from binary representation held in eeprom |
1641 | * RETURNS: the frequency in MHz |
1642 | */ |
1643 | static uint16_t |
1644 | fbin2freq(uint8_t fbin, HAL_BOOL is2GHz) |
1645 | { |
1646 | /* |
1647 | * Reserved value 0xFF provides an empty definition both as |
1648 | * an fbin and as a frequency - do not convert |
1649 | */ |
1650 | if (fbin == AR5416_BCHAN_UNUSED) { |
1651 | return fbin; |
1652 | } |
1653 | |
1654 | return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); |
1655 | } |
1656 | |
1657 | /* |
1658 | * ar5416GetMaxEdgePower |
1659 | * |
1660 | * Find the maximum conformance test limit for the given channel and CTL info |
1661 | */ |
1662 | static uint16_t |
1663 | ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz) |
1664 | { |
1665 | uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; |
1666 | int i; |
1667 | |
1668 | /* Get the edge power */ |
1669 | for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) { |
1670 | /* |
1671 | * If there's an exact channel match or an inband flag set |
1672 | * on the lower channel use the given rdEdgePower |
1673 | */ |
1674 | if (freq == fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { |
1675 | twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER); |
1676 | break; |
1677 | } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel, is2GHz))) { |
1678 | if (fbin2freq(pRdEdgesPower[i - 1].bChannel, is2GHz) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) { |
1679 | twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER); |
1680 | } |
1681 | /* Leave loop - no more affecting edges possible in this monotonic increasing list */ |
1682 | break; |
1683 | } |
1684 | } |
1685 | HALASSERT(twiceMaxEdgePower > 0); |
1686 | return twiceMaxEdgePower; |
1687 | } |
1688 | |
1689 | /************************************************************** |
1690 | * ar5416GetTargetPowers |
1691 | * |
1692 | * Return the rates of target power for the given target power table |
1693 | * channel, and number of channels |
1694 | */ |
1695 | void |
1696 | ar5416GetTargetPowers(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, |
1697 | CAL_TARGET_POWER_HT *powInfo, uint16_t numChannels, |
1698 | CAL_TARGET_POWER_HT *pNewPower, uint16_t numRates, |
1699 | HAL_BOOL isHt40Target) |
1700 | { |
1701 | uint16_t clo, chi; |
1702 | int i; |
1703 | int matchIndex = -1, lowIndex = -1; |
1704 | uint16_t freq; |
1705 | CHAN_CENTERS centers; |
1706 | |
1707 | ar5416GetChannelCenters(ah, chan, ¢ers); |
1708 | freq = isHt40Target ? centers.synth_center : centers.ctl_center; |
1709 | |
1710 | /* Copy the target powers into the temp channel list */ |
1711 | if (freq <= fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) { |
1712 | matchIndex = 0; |
1713 | } else { |
1714 | for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { |
1715 | if (freq == fbin2freq(powInfo[i].bChannel, IS_CHAN_2GHZ(chan))) { |
1716 | matchIndex = i; |
1717 | break; |
1718 | } else if ((freq < fbin2freq(powInfo[i].bChannel, IS_CHAN_2GHZ(chan))) && |
1719 | (freq > fbin2freq(powInfo[i - 1].bChannel, IS_CHAN_2GHZ(chan)))) |
1720 | { |
1721 | lowIndex = i - 1; |
1722 | break; |
1723 | } |
1724 | } |
1725 | if ((matchIndex == -1) && (lowIndex == -1)) { |
1726 | HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IS_CHAN_2GHZ(chan))); |
1727 | matchIndex = i - 1; |
1728 | } |
1729 | } |
1730 | |
1731 | if (matchIndex != -1) { |
1732 | OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower)); |
1733 | } else { |
1734 | HALASSERT(lowIndex != -1); |
1735 | /* |
1736 | * Get the lower and upper channels, target powers, |
1737 | * and interpolate between them. |
1738 | */ |
1739 | clo = fbin2freq(powInfo[lowIndex].bChannel, IS_CHAN_2GHZ(chan)); |
1740 | chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IS_CHAN_2GHZ(chan)); |
1741 | |
1742 | for (i = 0; i < numRates; i++) { |
1743 | pNewPower->tPow2x[i] = (uint8_t)interpolate(freq, clo, chi, |
1744 | powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]); |
1745 | } |
1746 | } |
1747 | } |
1748 | /************************************************************** |
1749 | * ar5416GetTargetPowersLeg |
1750 | * |
1751 | * Return the four rates of target power for the given target power table |
1752 | * channel, and number of channels |
1753 | */ |
1754 | void |
1755 | ar5416GetTargetPowersLeg(struct ath_hal *ah, |
1756 | HAL_CHANNEL_INTERNAL *chan, |
1757 | CAL_TARGET_POWER_LEG *powInfo, uint16_t numChannels, |
1758 | CAL_TARGET_POWER_LEG *pNewPower, uint16_t numRates, |
1759 | HAL_BOOL isExtTarget) |
1760 | { |
1761 | uint16_t clo, chi; |
1762 | int i; |
1763 | int matchIndex = -1, lowIndex = -1; |
1764 | uint16_t freq; |
1765 | CHAN_CENTERS centers; |
1766 | |
1767 | ar5416GetChannelCenters(ah, chan, ¢ers); |
1768 | freq = (isExtTarget) ? centers.ext_center :centers.ctl_center; |
1769 | |
1770 | /* Copy the target powers into the temp channel list */ |
1771 | if (freq <= fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) { |
1772 | matchIndex = 0; |
1773 | } else { |
1774 | for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { |
1775 | if (freq == fbin2freq(powInfo[i].bChannel, IS_CHAN_2GHZ(chan))) { |
1776 | matchIndex = i; |
1777 | break; |
1778 | } else if ((freq < fbin2freq(powInfo[i].bChannel, IS_CHAN_2GHZ(chan))) && |
1779 | (freq > fbin2freq(powInfo[i - 1].bChannel, IS_CHAN_2GHZ(chan)))) |
1780 | { |
1781 | lowIndex = i - 1; |
1782 | break; |
1783 | } |
1784 | } |
1785 | if ((matchIndex == -1) && (lowIndex == -1)) { |
1786 | HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IS_CHAN_2GHZ(chan))); |
1787 | matchIndex = i - 1; |
1788 | } |
1789 | } |
1790 | |
1791 | if (matchIndex != -1) { |
1792 | OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower)); |
1793 | } else { |
1794 | HALASSERT(lowIndex != -1); |
1795 | /* |
1796 | * Get the lower and upper channels, target powers, |
1797 | * and interpolate between them. |
1798 | */ |
1799 | clo = fbin2freq(powInfo[lowIndex].bChannel, IS_CHAN_2GHZ(chan)); |
1800 | chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IS_CHAN_2GHZ(chan)); |
1801 | |
1802 | for (i = 0; i < numRates; i++) { |
1803 | pNewPower->tPow2x[i] = (uint8_t)interpolate(freq, clo, chi, |
1804 | powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]); |
1805 | } |
1806 | } |
1807 | } |
1808 | |
1809 | /************************************************************** |
1810 | * ar5416SetPowerCalTable |
1811 | * |
1812 | * Pull the PDADC piers from cal data and interpolate them across the given |
1813 | * points as well as from the nearest pier(s) to get a power detector |
1814 | * linear voltage to power level table. |
1815 | */ |
1816 | static HAL_BOOL |
1817 | ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, HAL_CHANNEL_INTERNAL *chan, int16_t *pTxPowerIndexOffset) |
1818 | { |
1819 | CAL_DATA_PER_FREQ *pRawDataset; |
1820 | uint8_t *pCalBChans = AH_NULL; |
1821 | uint16_t pdGainOverlap_t2; |
1822 | static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; |
1823 | uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; |
1824 | uint16_t numPiers, i, j; |
1825 | int16_t tMinCalPower; |
1826 | uint16_t numXpdGain, xpdMask; |
1827 | uint16_t xpdGainValues[AR5416_NUM_PD_GAINS]; |
1828 | uint32_t reg32, regOffset, regChainOffset; |
1829 | |
1830 | ath_hal_memzero(xpdGainValues, sizeof(xpdGainValues)); |
1831 | |
1832 | xpdMask = pEepData->modalHeader[IS_CHAN_2GHZ(chan)].xpdGain; |
1833 | |
1834 | if (IS_EEP_MINOR_V2(ah)) { |
1835 | pdGainOverlap_t2 = pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pdGainOverlap; |
1836 | } else { |
1837 | pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); |
1838 | } |
1839 | |
1840 | if (IS_CHAN_2GHZ(chan)) { |
1841 | pCalBChans = pEepData->calFreqPier2G; |
1842 | numPiers = AR5416_NUM_2G_CAL_PIERS; |
1843 | } else { |
1844 | pCalBChans = pEepData->calFreqPier5G; |
1845 | numPiers = AR5416_NUM_5G_CAL_PIERS; |
1846 | } |
1847 | |
1848 | numXpdGain = 0; |
1849 | /* Calculate the value of xpdgains from the xpdGain Mask */ |
1850 | for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { |
1851 | if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { |
1852 | if (numXpdGain >= AR5416_NUM_PD_GAINS) { |
1853 | HALASSERT(0); |
1854 | break; |
1855 | } |
1856 | xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); |
1857 | numXpdGain++; |
1858 | } |
1859 | } |
1860 | |
1861 | /* Write the detector gain biases and their number */ |
1862 | OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) & |
1863 | ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) | |
1864 | SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) | |
1865 | SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3)); |
1866 | |
1867 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { |
1868 | |
1869 | if (AR_SREV_OWL_20_OR_LATER(ah) && |
1870 | ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) { |
1871 | /* Regs are swapped from chain 2 to 1 for 5416 2_0 with |
1872 | * only chains 0 and 2 populated |
1873 | */ |
1874 | regChainOffset = (i == 1) ? 0x2000 : 0x1000; |
1875 | } else { |
1876 | regChainOffset = i * 0x1000; |
1877 | } |
1878 | |
1879 | if (pEepData->baseEepHeader.txMask & (1 << i)) { |
1880 | if (IS_CHAN_2GHZ(chan)) { |
1881 | pRawDataset = pEepData->calPierData2G[i]; |
1882 | } else { |
1883 | pRawDataset = pEepData->calPierData5G[i]; |
1884 | } |
1885 | |
1886 | ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, |
1887 | pCalBChans, numPiers, |
1888 | pdGainOverlap_t2, |
1889 | &tMinCalPower, gainBoundaries, |
1890 | pdadcValues, numXpdGain); |
1891 | |
1892 | if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) { |
1893 | /* |
1894 | * Note the pdadc table may not start at 0 dBm power, could be |
1895 | * negative or greater than 0. Need to offset the power |
1896 | * values by the amount of minPower for griffin |
1897 | */ |
1898 | |
1899 | OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, |
1900 | SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | |
1901 | SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | |
1902 | SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | |
1903 | SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | |
1904 | SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); |
1905 | } |
1906 | |
1907 | /* Write the power values into the baseband power table */ |
1908 | regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; |
1909 | |
1910 | for (j = 0; j < 32; j++) { |
1911 | reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) | |
1912 | ((pdadcValues[4*j + 1] & 0xFF) << 8) | |
1913 | ((pdadcValues[4*j + 2] & 0xFF) << 16) | |
1914 | ((pdadcValues[4*j + 3] & 0xFF) << 24) ; |
1915 | OS_REG_WRITE(ah, regOffset, reg32); |
1916 | |
1917 | #ifdef PDADC_DUMP |
1918 | ath_hal_printf(ah, "PDADC: Chain %d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d |\n" , |
1919 | i, |
1920 | 4*j, pdadcValues[4*j], |
1921 | 4*j+1, pdadcValues[4*j + 1], |
1922 | 4*j+2, pdadcValues[4*j + 2], |
1923 | 4*j+3, pdadcValues[4*j + 3]); |
1924 | #endif |
1925 | regOffset += 4; |
1926 | } |
1927 | } |
1928 | } |
1929 | *pTxPowerIndexOffset = 0; |
1930 | |
1931 | return AH_TRUE; |
1932 | } |
1933 | |
1934 | /************************************************************** |
1935 | * ar5416GetGainBoundariesAndPdadcs |
1936 | * |
1937 | * Uses the data points read from EEPROM to reconstruct the pdadc power table |
1938 | * Called by ar5416SetPowerCalTable only. |
1939 | */ |
1940 | static void |
1941 | ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, |
1942 | HAL_CHANNEL_INTERNAL *chan, CAL_DATA_PER_FREQ *pRawDataSet, |
1943 | uint8_t * bChans, uint16_t availPiers, |
1944 | uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, |
1945 | uint8_t * pPDADCValues, uint16_t numXpdGains) |
1946 | { |
1947 | |
1948 | int i, j, k; |
1949 | int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ |
1950 | uint16_t idxL = 0, idxR = 0, numPiers; /* Pier indexes */ |
1951 | |
1952 | /* filled out Vpd table for all pdGains (chanL) */ |
1953 | static uint8_t vpdTableL[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; |
1954 | |
1955 | /* filled out Vpd table for all pdGains (chanR) */ |
1956 | static uint8_t vpdTableR[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; |
1957 | |
1958 | /* filled out Vpd table for all pdGains (interpolated) */ |
1959 | static uint8_t vpdTableI[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; |
1960 | |
1961 | uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; |
1962 | uint8_t minPwrT4[AR5416_NUM_PD_GAINS]; |
1963 | uint8_t maxPwrT4[AR5416_NUM_PD_GAINS]; |
1964 | int16_t vpdStep; |
1965 | int16_t tmpVal; |
1966 | uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; |
1967 | HAL_BOOL match; |
1968 | int16_t minDelta = 0; |
1969 | CHAN_CENTERS centers; |
1970 | |
1971 | ar5416GetChannelCenters(ah, chan, ¢ers); |
1972 | |
1973 | /* Trim numPiers for the number of populated channel Piers */ |
1974 | for (numPiers = 0; numPiers < availPiers; numPiers++) { |
1975 | if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { |
1976 | break; |
1977 | } |
1978 | } |
1979 | |
1980 | /* Find pier indexes around the current channel */ |
1981 | match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)), |
1982 | bChans, numPiers, &idxL, &idxR); |
1983 | |
1984 | if (match) { |
1985 | /* Directly fill both vpd tables from the matching index */ |
1986 | for (i = 0; i < numXpdGains; i++) { |
1987 | minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; |
1988 | maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; |
1989 | ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pRawDataSet[idxL].pwrPdg[i], |
1990 | pRawDataSet[idxL].vpdPdg[i], AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); |
1991 | } |
1992 | } else { |
1993 | for (i = 0; i < numXpdGains; i++) { |
1994 | pVpdL = pRawDataSet[idxL].vpdPdg[i]; |
1995 | pPwrL = pRawDataSet[idxL].pwrPdg[i]; |
1996 | pVpdR = pRawDataSet[idxR].vpdPdg[i]; |
1997 | pPwrR = pRawDataSet[idxR].pwrPdg[i]; |
1998 | |
1999 | /* Start Vpd interpolation from the max of the minimum powers */ |
2000 | minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); |
2001 | |
2002 | /* End Vpd interpolation from the min of the max powers */ |
2003 | maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); |
2004 | HALASSERT(maxPwrT4[i] > minPwrT4[i]); |
2005 | |
2006 | /* Fill pier Vpds */ |
2007 | ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); |
2008 | ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); |
2009 | |
2010 | /* Interpolate the final vpd */ |
2011 | for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { |
2012 | vpdTableI[i][j] = (uint8_t)(interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)), |
2013 | bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); |
2014 | } |
2015 | } |
2016 | } |
2017 | *pMinCalPower = (int16_t)(minPwrT4[0] / 2); |
2018 | |
2019 | k = 0; /* index for the final table */ |
2020 | for (i = 0; i < numXpdGains; i++) { |
2021 | if (i == (numXpdGains - 1)) { |
2022 | pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); |
2023 | } else { |
2024 | pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); |
2025 | } |
2026 | |
2027 | pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); |
2028 | |
2029 | /* NB: only applies to owl 1.0 */ |
2030 | if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) { |
2031 | /* |
2032 | * fix the gain delta, but get a delta that can be applied to min to |
2033 | * keep the upper power values accurate, don't think max needs to |
2034 | * be adjusted because should not be at that area of the table? |
2035 | */ |
2036 | minDelta = pPdGainBoundaries[0] - 23; |
2037 | pPdGainBoundaries[0] = 23; |
2038 | } |
2039 | else { |
2040 | minDelta = 0; |
2041 | } |
2042 | |
2043 | /* Find starting index for this pdGain */ |
2044 | if (i == 0) { |
2045 | ss = 0; /* for the first pdGain, start from index 0 */ |
2046 | } else { |
2047 | /* need overlap entries extrapolated below. */ |
2048 | ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); |
2049 | } |
2050 | vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); |
2051 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); |
2052 | /* |
2053 | *-ve ss indicates need to extrapolate data below for this pdGain |
2054 | */ |
2055 | while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { |
2056 | tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); |
2057 | pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); |
2058 | ss++; |
2059 | } |
2060 | |
2061 | sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); |
2062 | tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); |
2063 | maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; |
2064 | |
2065 | while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { |
2066 | pPDADCValues[k++] = vpdTableI[i][ss++]; |
2067 | } |
2068 | |
2069 | vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); |
2070 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); |
2071 | /* |
2072 | * for last gain, pdGainBoundary == Pmax_t2, so will |
2073 | * have to extrapolate |
2074 | */ |
2075 | if (tgtIndex > maxIndex) { /* need to extrapolate above */ |
2076 | while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { |
2077 | tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + |
2078 | (ss - maxIndex +1) * vpdStep)); |
2079 | pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); |
2080 | ss++; |
2081 | } |
2082 | } /* extrapolated above */ |
2083 | } /* for all pdGainUsed */ |
2084 | |
2085 | /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ |
2086 | while (i < AR5416_PD_GAINS_IN_MASK) { |
2087 | pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; |
2088 | i++; |
2089 | } |
2090 | |
2091 | while (k < AR5416_NUM_PDADC_VALUES) { |
2092 | pPDADCValues[k] = pPDADCValues[k-1]; |
2093 | k++; |
2094 | } |
2095 | return; |
2096 | } |
2097 | |
2098 | /************************************************************** |
2099 | * getLowerUppderIndex |
2100 | * |
2101 | * Return indices surrounding the value in sorted integer lists. |
2102 | * Requirement: the input list must be monotonically increasing |
2103 | * and populated up to the list size |
2104 | * Returns: match is set if an index in the array matches exactly |
2105 | * or a the target is before or after the range of the array. |
2106 | */ |
2107 | HAL_BOOL |
2108 | getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize, |
2109 | uint16_t *indexL, uint16_t *indexR) |
2110 | { |
2111 | uint16_t i; |
2112 | |
2113 | /* |
2114 | * Check first and last elements for beyond ordered array cases. |
2115 | */ |
2116 | if (target <= pList[0]) { |
2117 | *indexL = *indexR = 0; |
2118 | return AH_TRUE; |
2119 | } |
2120 | if (target >= pList[listSize-1]) { |
2121 | *indexL = *indexR = (uint16_t)(listSize - 1); |
2122 | return AH_TRUE; |
2123 | } |
2124 | |
2125 | /* look for value being near or between 2 values in list */ |
2126 | for (i = 0; i < listSize - 1; i++) { |
2127 | /* |
2128 | * If value is close to the current value of the list |
2129 | * then target is not between values, it is one of the values |
2130 | */ |
2131 | if (pList[i] == target) { |
2132 | *indexL = *indexR = i; |
2133 | return AH_TRUE; |
2134 | } |
2135 | /* |
2136 | * Look for value being between current value and next value |
2137 | * if so return these 2 values |
2138 | */ |
2139 | if (target < pList[i + 1]) { |
2140 | *indexL = i; |
2141 | *indexR = (uint16_t)(i + 1); |
2142 | return AH_FALSE; |
2143 | } |
2144 | } |
2145 | HALASSERT(0); |
2146 | return AH_FALSE; |
2147 | } |
2148 | |
2149 | /************************************************************** |
2150 | * ar5416FillVpdTable |
2151 | * |
2152 | * Fill the Vpdlist for indices Pmax-Pmin |
2153 | * Note: pwrMin, pwrMax and Vpdlist are all in dBm * 4 |
2154 | */ |
2155 | static HAL_BOOL |
2156 | ar5416FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList, |
2157 | uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList) |
2158 | { |
2159 | uint16_t i, k; |
2160 | uint8_t currPwr = pwrMin; |
2161 | uint16_t idxL = 0, idxR = 0; |
2162 | |
2163 | HALASSERT(pwrMax > pwrMin); |
2164 | for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { |
2165 | getLowerUpperIndex(currPwr, pPwrList, numIntercepts, |
2166 | &(idxL), &(idxR)); |
2167 | if (idxR < 1) |
2168 | idxR = 1; /* extrapolate below */ |
2169 | if (idxL == numIntercepts - 1) |
2170 | idxL = (uint16_t)(numIntercepts - 2); /* extrapolate above */ |
2171 | if (pPwrList[idxL] == pPwrList[idxR]) |
2172 | k = pVpdList[idxL]; |
2173 | else |
2174 | k = (uint16_t)( ((currPwr - pPwrList[idxL]) * pVpdList[idxR] + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) / |
2175 | (pPwrList[idxR] - pPwrList[idxL]) ); |
2176 | HALASSERT(k < 256); |
2177 | pRetVpdList[i] = (uint8_t)k; |
2178 | currPwr += 2; /* half dB steps */ |
2179 | } |
2180 | |
2181 | return AH_TRUE; |
2182 | } |
2183 | |
2184 | /************************************************************************** |
2185 | * interpolate |
2186 | * |
2187 | * Returns signed interpolated or the scaled up interpolated value |
2188 | */ |
2189 | static int16_t |
2190 | interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight, |
2191 | int16_t targetLeft, int16_t targetRight) |
2192 | { |
2193 | int16_t rv; |
2194 | |
2195 | if (srcRight == srcLeft) { |
2196 | rv = targetLeft; |
2197 | } else { |
2198 | rv = (int16_t)( ((target - srcLeft) * targetRight + |
2199 | (srcRight - target) * targetLeft) / (srcRight - srcLeft) ); |
2200 | } |
2201 | return rv; |
2202 | } |
2203 | |
2204 | static void |
2205 | ar5416Set11nRegs(struct ath_hal *ah, HAL_CHANNEL *chan) |
2206 | { |
2207 | uint32_t phymode; |
2208 | HAL_HT_MACMODE macmode; /* MAC - 20/40 mode */ |
2209 | |
2210 | if (!IS_CHAN_HT(chan)) |
2211 | return; |
2212 | |
2213 | /* Enable 11n HT, 20 MHz */ |
2214 | phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 |
2215 | | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH; |
2216 | |
2217 | /* Configure baseband for dynamic 20/40 operation */ |
2218 | if (IS_CHAN_HT40(chan)) { |
2219 | phymode |= AR_PHY_FC_DYN2040_EN | AR_PHY_FC_SHORT_GI_40; |
2220 | |
2221 | /* Configure control (primary) channel at +-10MHz */ |
2222 | if ((chan->channelFlags & CHANNEL_HT40PLUS)) |
2223 | phymode |= AR_PHY_FC_DYN2040_PRI_CH; |
2224 | #if 0 |
2225 | /* Configure 20/25 spacing */ |
2226 | if (ht->ht_extprotspacing == HAL_HT_EXTPROTSPACING_25) |
2227 | phymode |= AR_PHY_FC_DYN2040_EXT_CH; |
2228 | #endif |
2229 | macmode = HAL_HT_MACMODE_2040; |
2230 | } else |
2231 | macmode = HAL_HT_MACMODE_20; |
2232 | OS_REG_WRITE(ah, AR_PHY_TURBO, phymode); |
2233 | |
2234 | /* Configure MAC for 20/40 operation */ |
2235 | ar5416Set11nMac2040(ah, macmode); |
2236 | |
2237 | /* global transmit timeout (25 TUs default)*/ |
2238 | /* XXX - put this elsewhere??? */ |
2239 | OS_REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S) ; |
2240 | |
2241 | /* carrier sense timeout */ |
2242 | OS_REG_SET_BIT(ah, AR_GTTM, AR_GTTM_CST_USEC); |
2243 | OS_REG_WRITE(ah, AR_CST, 1 << AR_CST_TIMEOUT_LIMIT_S); |
2244 | } |
2245 | |
2246 | void |
2247 | ar5416GetChannelCenters(struct ath_hal *ah, |
2248 | HAL_CHANNEL_INTERNAL *chan, CHAN_CENTERS *centers) |
2249 | { |
2250 | centers->ctl_center = chan->channel; |
2251 | centers->synth_center = chan->channel; |
2252 | /* |
2253 | * In 20/40 phy mode, the center frequency is |
2254 | * "between" the control and extension channels. |
2255 | */ |
2256 | if (chan->channelFlags & CHANNEL_HT40PLUS) { |
2257 | centers->synth_center += HT40_CHANNEL_CENTER_SHIFT; |
2258 | centers->ext_center = |
2259 | centers->synth_center + HT40_CHANNEL_CENTER_SHIFT; |
2260 | } else if (chan->channelFlags & CHANNEL_HT40MINUS) { |
2261 | centers->synth_center -= HT40_CHANNEL_CENTER_SHIFT; |
2262 | centers->ext_center = |
2263 | centers->synth_center - HT40_CHANNEL_CENTER_SHIFT; |
2264 | } else { |
2265 | centers->ext_center = chan->channel; |
2266 | } |
2267 | } |
2268 | |