1/* $NetBSD: auich.c,v 1.149 2016/07/07 06:55:41 msaitoh Exp $ */
2
3/*-
4 * Copyright (c) 2000, 2004, 2005, 2008 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe and by Charles M. Hannum.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*
33 * Copyright (c) 2000 Michael Shalayeff
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 * 3. The name of the author may not be used to endorse or promote products
45 * derived from this software without specific prior written permission.
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
51 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
52 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
53 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
55 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
56 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
57 * THE POSSIBILITY OF SUCH DAMAGE.
58 *
59 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp
60 */
61
62/*
63 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp>
64 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org>
65 * All rights reserved.
66 *
67 * Redistribution and use in source and binary forms, with or without
68 * modification, are permitted provided that the following conditions
69 * are met:
70 * 1. Redistributions of source code must retain the above copyright
71 * notice, this list of conditions and the following disclaimer.
72 * 2. Redistributions in binary form must reproduce the above copyright
73 * notice, this list of conditions and the following disclaimer in the
74 * documentation and/or other materials provided with the distribution.
75 *
76 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
77 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
78 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
79 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
80 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
81 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
82 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
83 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
84 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
85 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
86 * SUCH DAMAGE.
87 *
88 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp
89 */
90
91
92/* #define AUICH_DEBUG */
93/*
94 * AC'97 audio found on Intel 810/820/440MX chipsets.
95 * http://developer.intel.com/design/chipsets/datashts/290655.htm
96 * http://developer.intel.com/design/chipsets/manuals/298028.htm
97 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm
98 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm
99 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm
100 * AMD8111:
101 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf
102 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf
103 *
104 * TODO:
105 * - Add support for the dedicated microphone input.
106 *
107 * NOTE:
108 * - The 440MX B-stepping at running 100MHz has a hardware erratum.
109 * It causes PCI master abort and hangups until cold reboot.
110 * http://www.intel.com/design/chipsets/specupdt/245051.htm
111 */
112
113#include <sys/cdefs.h>
114__KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.149 2016/07/07 06:55:41 msaitoh Exp $");
115
116#include <sys/param.h>
117#include <sys/systm.h>
118#include <sys/kernel.h>
119#include <sys/kmem.h>
120#include <sys/device.h>
121#include <sys/fcntl.h>
122#include <sys/proc.h>
123#include <sys/sysctl.h>
124#include <sys/audioio.h>
125#include <sys/bus.h>
126#include <sys/rndsource.h>
127
128#include <dev/pci/pcidevs.h>
129#include <dev/pci/pcivar.h>
130#include <dev/pci/auichreg.h>
131
132#include <dev/audio_if.h>
133#include <dev/mulaw.h>
134#include <dev/auconv.h>
135
136#include <dev/ic/ac97reg.h>
137#include <dev/ic/ac97var.h>
138
139struct auich_dma {
140 bus_dmamap_t map;
141 void *addr;
142 bus_dma_segment_t segs[1];
143 int nsegs;
144 size_t size;
145 struct auich_dma *next;
146};
147
148#define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr)
149#define KERNADDR(p) ((void *)((p)->addr))
150
151struct auich_cdata {
152 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX];
153 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX];
154 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX];
155};
156
157#define ICH_CDOFF(x) offsetof(struct auich_cdata, x)
158#define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)])
159#define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)])
160#define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)])
161
162struct auich_softc {
163 device_t sc_dev;
164 void *sc_ih;
165 kmutex_t sc_lock;
166 kmutex_t sc_intr_lock;
167
168 device_t sc_audiodev;
169 audio_device_t sc_audev;
170
171 pci_chipset_tag_t sc_pc;
172 pcitag_t sc_pt;
173 bus_space_tag_t iot;
174 bus_space_handle_t mix_ioh;
175 bus_size_t mix_size;
176 bus_space_handle_t aud_ioh;
177 bus_size_t aud_size;
178 bus_dma_tag_t dmat;
179 pci_intr_handle_t intrh;
180
181 struct ac97_codec_if *codec_if;
182 struct ac97_host_if host_if;
183 int sc_codecnum;
184 int sc_codectype;
185 int sc_fixedrate;
186 enum ac97_host_flags sc_codecflags;
187 bool sc_spdif;
188
189 /* multi-channel control bits */
190 int sc_pcm246_mask;
191 int sc_pcm2;
192 int sc_pcm4;
193 int sc_pcm6;
194
195 /* DMA scatter-gather lists. */
196 bus_dmamap_t sc_cddmamap;
197#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
198
199 struct auich_cdata *sc_cdata;
200
201 struct auich_ring {
202 int qptr;
203 struct auich_dmalist *dmalist;
204
205 uint32_t start, p, end;
206 int blksize;
207
208 void (*intr)(void *);
209 void *arg;
210 } pcmo, pcmi, mici;
211
212 struct auich_dma *sc_dmas;
213
214 /* SiS 7012 hack */
215 int sc_sample_shift;
216 int sc_sts_reg;
217 /* 440MX workaround */
218 int sc_dmamap_flags;
219 /* flags */
220 int sc_iose :1,
221 :31;
222
223 /* sysctl */
224 struct sysctllog *sc_log;
225 uint32_t sc_ac97_clock;
226 int sc_ac97_clock_mib;
227
228 int sc_modem_offset;
229
230#define AUICH_AUDIO_NFORMATS 3
231#define AUICH_MODEM_NFORMATS 1
232 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS];
233 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS];
234 struct audio_encoding_set *sc_encodings;
235 struct audio_encoding_set *sc_spdif_encodings;
236
237 int sc_cas_been_used;
238};
239
240/* Debug */
241#ifdef AUICH_DEBUG
242#define DPRINTF(l,x) do { if (auich_debug & (l)) aprint_normal_dev x; } while(0)
243int auich_debug = 0xfffe;
244#define ICH_DEBUG_CODECIO 0x0001
245#define ICH_DEBUG_DMA 0x0002
246#define ICH_DEBUG_INTR 0x0004
247#else
248#define DPRINTF(x,y) /* nothing */
249#endif
250
251static int auich_match(device_t, cfdata_t, void *);
252static void auich_attach(device_t, device_t, void *);
253static int auich_detach(device_t, int);
254static void auich_childdet(device_t, device_t);
255static int auich_intr(void *);
256
257CFATTACH_DECL2_NEW(auich, sizeof(struct auich_softc),
258 auich_match, auich_attach, auich_detach, NULL, NULL, auich_childdet);
259
260static int auich_open(void *, int);
261static void auich_close(void *);
262static int auich_query_encoding(void *, struct audio_encoding *);
263static int auich_set_params(void *, int, int, audio_params_t *,
264 audio_params_t *, stream_filter_list_t *,
265 stream_filter_list_t *);
266static int auich_round_blocksize(void *, int, int, const audio_params_t *);
267static void auich_halt_pipe(struct auich_softc *, int);
268static int auich_halt_output(void *);
269static int auich_halt_input(void *);
270static int auich_getdev(void *, struct audio_device *);
271static int auich_set_port(void *, mixer_ctrl_t *);
272static int auich_get_port(void *, mixer_ctrl_t *);
273static int auich_query_devinfo(void *, mixer_devinfo_t *);
274static void *auich_allocm(void *, int, size_t);
275static void auich_freem(void *, void *, size_t);
276static size_t auich_round_buffersize(void *, int, size_t);
277static paddr_t auich_mappage(void *, void *, off_t, int);
278static int auich_get_props(void *);
279static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *);
280static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *);
281static int auich_trigger_output(void *, void *, void *, int,
282 void (*)(void *), void *, const audio_params_t *);
283static int auich_trigger_input(void *, void *, void *, int,
284 void (*)(void *), void *, const audio_params_t *);
285static void auich_get_locks(void *, kmutex_t **, kmutex_t **);
286
287static int auich_alloc_cdata(struct auich_softc *);
288
289static int auich_allocmem(struct auich_softc *, size_t, size_t,
290 struct auich_dma *);
291static int auich_freemem(struct auich_softc *, struct auich_dma *);
292
293static bool auich_resume(device_t, const pmf_qual_t *);
294static int auich_set_rate(struct auich_softc *, int, u_long);
295static int auich_sysctl_verify(SYSCTLFN_ARGS);
296static void auich_finish_attach(device_t);
297static void auich_calibrate(struct auich_softc *);
298static void auich_clear_cas(struct auich_softc *);
299
300static int auich_attach_codec(void *, struct ac97_codec_if *);
301static int auich_read_codec(void *, uint8_t, uint16_t *);
302static int auich_write_codec(void *, uint8_t, uint16_t);
303static int auich_reset_codec(void *);
304static enum ac97_host_flags auich_flags_codec(void *);
305static void auich_spdif_event(void *, bool);
306
307static const struct audio_hw_if auich_hw_if = {
308 auich_open,
309 auich_close,
310 NULL, /* drain */
311 auich_query_encoding,
312 auich_set_params,
313 auich_round_blocksize,
314 NULL, /* commit_setting */
315 NULL, /* init_output */
316 NULL, /* init_input */
317 NULL, /* start_output */
318 NULL, /* start_input */
319 auich_halt_output,
320 auich_halt_input,
321 NULL, /* speaker_ctl */
322 auich_getdev,
323 NULL, /* getfd */
324 auich_set_port,
325 auich_get_port,
326 auich_query_devinfo,
327 auich_allocm,
328 auich_freem,
329 auich_round_buffersize,
330 auich_mappage,
331 auich_get_props,
332 auich_trigger_output,
333 auich_trigger_input,
334 NULL, /* dev_ioctl */
335 auich_get_locks,
336};
337
338#define AUICH_FORMATS_1CH 0
339#define AUICH_FORMATS_4CH 1
340#define AUICH_FORMATS_6CH 2
341static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = {
342 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
343 2, AUFMT_STEREO, 0, {8000, 48000}},
344 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
345 4, AUFMT_SURROUND4, 0, {8000, 48000}},
346 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
347 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}},
348};
349
350#define AUICH_SPDIF_NFORMATS 1
351static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = {
352 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
353 2, AUFMT_STEREO, 1, {48000}},
354};
355
356static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = {
357 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
358 1, AUFMT_MONAURAL, 0, {8000, 16000}},
359};
360
361#define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p)
362#define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA)
363#define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA)
364#define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA)
365#define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA)
366#define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC)
367#define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC)
368#define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC)
369#define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC)
370#define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA)
371#define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA)
372#define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC)
373#define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC)
374#define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC)
375#define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC)
376#define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC)
377#define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC)
378#define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC)
379#define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC)
380#define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC)
381#define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC)
382
383#define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD)
384#define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD)
385#define PCIID_ICH6MODEM PCI_ID_CODE0(INTEL, 82801FB_ACM)
386
387struct auich_devtype {
388 pcireg_t id;
389 const char *name;
390 const char *shortname; /* must be less than 11 characters */
391};
392
393static const struct auich_devtype auich_audio_devices[] = {
394 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" },
395 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" },
396 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" },
397 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" },
398 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" },
399 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" },
400 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" },
401 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" },
402 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" },
403 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" },
404 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" },
405 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" },
406 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" },
407 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" },
408 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" },
409 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" },
410 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" },
411 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" },
412 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" },
413 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" },
414 { 0, NULL, NULL },
415};
416
417static const struct auich_devtype auich_modem_devices[] = {
418#ifdef AUICH_ATTACH_MODEM
419 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" },
420 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" },
421 { PCIID_ICH6MODEM, "i82801FB (ICH6) AC-97 Modem", "ICH6MODEM" },
422#endif
423 { 0, NULL, NULL },
424};
425
426static const struct auich_devtype *
427auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices)
428{
429 const struct auich_devtype *d;
430
431 for (d = auich_devices; d->name != NULL; d++) {
432 if (pa->pa_id == d->id)
433 return d;
434 }
435
436 return NULL;
437}
438
439static int
440auich_match(device_t parent, cfdata_t match, void *aux)
441{
442 struct pci_attach_args *pa;
443
444 pa = aux;
445 if (auich_lookup(pa, auich_audio_devices) != NULL)
446 return 1;
447 if (auich_lookup(pa, auich_modem_devices) != NULL)
448 return 1;
449
450 return 0;
451}
452
453static void
454auich_attach(device_t parent, device_t self, void *aux)
455{
456 struct auich_softc *sc = device_private(self);
457 struct pci_attach_args *pa;
458 pcireg_t v, subdev;
459 const char *intrstr;
460 const struct auich_devtype *d;
461 const struct sysctlnode *node, *node_ac97clock;
462 int err, node_mib, i;
463 char intrbuf[PCI_INTRSTR_LEN];
464
465 sc->sc_dev = self;
466 pa = aux;
467
468 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) {
469 sc->sc_modem_offset = 0x10;
470 sc->sc_codectype = AC97_CODEC_TYPE_MODEM;
471 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) {
472 sc->sc_modem_offset = 0;
473 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO;
474 } else
475 panic("auich_attach: impossible");
476
477 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO)
478 aprint_naive(": Audio controller\n");
479 else
480 aprint_naive(": Modem controller\n");
481
482 sc->sc_pc = pa->pa_pc;
483 sc->sc_pt = pa->pa_tag;
484
485 aprint_normal(": %s\n", d->name);
486
487 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6
488 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB
489 || d->id == PCIID_ICH4MODEM) {
490 /*
491 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7
492 */
493
494 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0,
495 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) {
496 goto retry_map;
497 }
498 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0,
499 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) {
500 goto retry_map;
501 }
502 goto map_done;
503 } else
504 goto non_native_map;
505
506retry_map:
507 sc->sc_iose = 1;
508 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG);
509 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG,
510 v | ICH_CFG_IOSE);
511
512non_native_map:
513 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0,
514 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) {
515 aprint_error_dev(self, "can't map codec i/o space\n");
516 return;
517 }
518 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0,
519 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) {
520 aprint_error_dev(self, "can't map device i/o space\n");
521 return;
522 }
523
524map_done:
525 sc->dmat = pa->pa_dmat;
526
527 /* enable bus mastering */
528 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
529 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
530 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE);
531
532 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
533 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO);
534
535 /* Map and establish the interrupt. */
536 if (pci_intr_map(pa, &sc->intrh)) {
537 aprint_error_dev(self, "can't map interrupt\n");
538 return;
539 }
540 intrstr = pci_intr_string(pa->pa_pc, sc->intrh, intrbuf, sizeof(intrbuf));
541 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO,
542 auich_intr, sc);
543 if (sc->sc_ih == NULL) {
544 aprint_error_dev(self, "can't establish interrupt");
545 if (intrstr != NULL)
546 aprint_error(" at %s", intrstr);
547 aprint_error("\n");
548 return;
549 }
550 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
551
552 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname);
553 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN,
554 "0x%02x", PCI_REVISION(pa->pa_class));
555 strlcpy(sc->sc_audev.config, device_xname(self), MAX_AUDIO_DEV_LEN);
556
557 /* SiS 7012 needs special handling */
558 if (d->id == PCIID_SIS7012) {
559 sc->sc_sts_reg = ICH_PICB;
560 sc->sc_sample_shift = 0;
561 sc->sc_pcm246_mask = ICH_SIS_PCM246_MASK;
562 sc->sc_pcm2 = ICH_SIS_PCM2;
563 sc->sc_pcm4 = ICH_SIS_PCM4;
564 sc->sc_pcm6 = ICH_SIS_PCM6;
565 /* Un-mute output. From Linux. */
566 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL,
567 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) |
568 ICH_SIS_CTL_UNMUTE);
569 } else {
570 sc->sc_sts_reg = ICH_STS;
571 sc->sc_sample_shift = 1;
572 sc->sc_pcm246_mask = ICH_PCM246_MASK;
573 sc->sc_pcm2 = ICH_PCM2;
574 sc->sc_pcm4 = ICH_PCM4;
575 sc->sc_pcm6 = ICH_PCM6;
576 }
577
578 /* Workaround for a 440MX B-stepping erratum */
579 sc->sc_dmamap_flags = BUS_DMA_COHERENT;
580 if (d->id == PCIID_440MX) {
581 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE;
582 aprint_normal_dev(self, "DMA bug workaround enabled\n");
583 }
584
585 /* Set up DMA lists. */
586 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0;
587 auich_alloc_cdata(sc);
588
589 DPRINTF(ICH_DEBUG_DMA, (sc->sc_dev, "%s: lists %p %p %p\n",
590 __func__, sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist));
591
592 /* Modem codecs are always the secondary codec on ICH */
593 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0;
594
595 sc->host_if.arg = sc;
596 sc->host_if.attach = auich_attach_codec;
597 sc->host_if.read = auich_read_codec;
598 sc->host_if.write = auich_write_codec;
599 sc->host_if.reset = auich_reset_codec;
600 sc->host_if.flags = auich_flags_codec;
601 sc->host_if.spdif_event = auich_spdif_event;
602
603 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
604 switch (subdev) {
605 case 0x202f161f: /* Gateway 7326GZ */
606 case 0x203a161f: /* Gateway 4028GZ */
607 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */
608 case 0x8144104d: /* Sony VAIO PCG-TR* */
609 case 0x8197104d: /* Sony S1XP */
610 case 0x81c0104d: /* Sony VAIO type T */
611 case 0x81c5104d: /* Sony VAIO VGN-B1XP */
612 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP;
613 break;
614 default:
615 sc->sc_codecflags = 0;
616 break;
617 }
618
619 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype,
620 &sc->sc_lock) != 0)
621 return;
622
623 mutex_enter(&sc->sc_lock);
624 sc->codec_if->vtbl->unlock(sc->codec_if);
625 sc->sc_fixedrate = AC97_IS_FIXED_RATE(sc->codec_if);
626
627 /* setup audio_format */
628 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) {
629 memcpy(sc->sc_audio_formats, auich_audio_formats,
630 sizeof(auich_audio_formats));
631 if (!AC97_IS_4CH(sc->codec_if))
632 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]);
633 if (!AC97_IS_6CH(sc->codec_if))
634 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]);
635 if (AC97_IS_FIXED_RATE(sc->codec_if)) {
636 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) {
637 sc->sc_audio_formats[i].frequency_type = 1;
638 sc->sc_audio_formats[i].frequency[0] = 48000;
639 }
640 }
641 mutex_exit(&sc->sc_lock);
642 if (0 != auconv_create_encodings(sc->sc_audio_formats,
643 AUICH_AUDIO_NFORMATS, &sc->sc_encodings))
644 return;
645 if (0 != auconv_create_encodings(auich_spdif_formats,
646 AUICH_SPDIF_NFORMATS, &sc->sc_spdif_encodings))
647 return;
648 } else {
649 mutex_exit(&sc->sc_lock);
650 memcpy(sc->sc_modem_formats, auich_modem_formats,
651 sizeof(auich_modem_formats));
652 if (0 != auconv_create_encodings(sc->sc_modem_formats,
653 AUICH_MODEM_NFORMATS, &sc->sc_encodings))
654 return;
655 }
656
657 /* Watch for power change */
658 if (!pmf_device_register(self, NULL, auich_resume))
659 aprint_error_dev(self, "couldn't establish power handler\n");
660
661 config_interrupts(self, auich_finish_attach);
662
663 /* sysctl setup */
664 if (sc->sc_fixedrate && sc->sc_codectype == AC97_CODEC_TYPE_AUDIO)
665 return;
666
667 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0,
668 CTLTYPE_NODE, device_xname(self), NULL, NULL, 0,
669 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
670 if (err != 0)
671 goto sysctl_err;
672 node_mib = node->sysctl_num;
673
674 if (!sc->sc_fixedrate) {
675 /* passing the sc address instead of &sc->sc_ac97_clock */
676 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock,
677 CTLFLAG_READWRITE,
678 CTLTYPE_INT, "ac97rate",
679 SYSCTL_DESCR("AC'97 codec link rate"),
680 auich_sysctl_verify, 0, (void *)sc, 0,
681 CTL_HW, node_mib, CTL_CREATE, CTL_EOL);
682 if (err != 0)
683 goto sysctl_err;
684 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num;
685 }
686
687 return;
688
689 sysctl_err:
690 aprint_error_dev(self, "failed to add sysctl nodes. (%d)\n", err);
691 return; /* failure of sysctl is not fatal. */
692}
693
694static void
695auich_childdet(device_t self, device_t child)
696{
697 struct auich_softc *sc = device_private(self);
698
699 KASSERT(sc->sc_audiodev == child);
700 sc->sc_audiodev = NULL;
701}
702
703static int
704auich_detach(device_t self, int flags)
705{
706 struct auich_softc *sc = device_private(self);
707
708 /* audio */
709 if (sc->sc_audiodev != NULL)
710 config_detach(sc->sc_audiodev, flags);
711
712 /* sysctl */
713 sysctl_teardown(&sc->sc_log);
714
715 mutex_enter(&sc->sc_lock);
716
717 /* audio_encoding_set */
718 auconv_delete_encodings(sc->sc_encodings);
719 auconv_delete_encodings(sc->sc_spdif_encodings);
720
721 /* ac97 */
722 if (sc->codec_if != NULL)
723 sc->codec_if->vtbl->detach(sc->codec_if);
724
725 mutex_exit(&sc->sc_lock);
726 mutex_destroy(&sc->sc_lock);
727 mutex_destroy(&sc->sc_intr_lock);
728
729 /* PCI */
730 if (sc->sc_ih != NULL)
731 pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
732 if (sc->mix_size != 0)
733 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size);
734 if (sc->aud_size != 0)
735 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size);
736 return 0;
737}
738
739static int
740auich_sysctl_verify(SYSCTLFN_ARGS)
741{
742 int error, tmp;
743 struct sysctlnode node;
744 struct auich_softc *sc;
745
746 node = *rnode;
747 sc = rnode->sysctl_data;
748 if (node.sysctl_num == sc->sc_ac97_clock_mib) {
749 tmp = sc->sc_ac97_clock;
750 node.sysctl_data = &tmp;
751 error = sysctl_lookup(SYSCTLFN_CALL(&node));
752 if (error || newp == NULL)
753 return error;
754
755 if (tmp < 48000 || tmp > 96000)
756 return EINVAL;
757 mutex_enter(&sc->sc_lock);
758 sc->sc_ac97_clock = tmp;
759 mutex_exit(&sc->sc_lock);
760 }
761
762 return 0;
763}
764
765static void
766auich_finish_attach(device_t self)
767{
768 struct auich_softc *sc = device_private(self);
769
770 mutex_enter(&sc->sc_lock);
771 if (!AC97_IS_FIXED_RATE(sc->codec_if))
772 auich_calibrate(sc);
773 mutex_exit(&sc->sc_lock);
774
775 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, sc->sc_dev);
776
777 return;
778}
779
780#define ICH_CODECIO_INTERVAL 10
781static int
782auich_read_codec(void *v, uint8_t reg, uint16_t *val)
783{
784 struct auich_softc *sc;
785 int i;
786 uint32_t status;
787
788 sc = v;
789 /* wait for an access semaphore */
790 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- &&
791 bus_space_read_1(sc->iot, sc->aud_ioh,
792 ICH_CAS + sc->sc_modem_offset) & 1;
793 DELAY(ICH_CODECIO_INTERVAL));
794
795 /*
796 * Be permissive in first attempt. If previous instances of
797 * this routine were interrupted precisely at this point (after
798 * access is granted by CAS but before a command is sent),
799 * they could have left hardware in an inconsistent state where
800 * a command is expected and therefore semaphore wait would hit
801 * the timeout.
802 */
803 if (!sc->sc_cas_been_used && i <= 0)
804 i = 1;
805 sc->sc_cas_been_used = 1;
806
807 if (i > 0) {
808 *val = bus_space_read_2(sc->iot, sc->mix_ioh,
809 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET));
810 DPRINTF(ICH_DEBUG_CODECIO,
811 (sc->sc_dev, "%s(%x, %x)\n", __func__, reg, *val));
812 status = bus_space_read_4(sc->iot, sc->aud_ioh,
813 ICH_GSTS + sc->sc_modem_offset);
814 if (status & ICH_RCS) {
815 bus_space_write_4(sc->iot, sc->aud_ioh,
816 ICH_GSTS + sc->sc_modem_offset,
817 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI));
818 *val = 0xffff;
819 DPRINTF(ICH_DEBUG_CODECIO,
820 (sc->sc_dev, "%s: read_codec error\n", __func__));
821 if (reg == AC97_REG_GPIO_STATUS)
822 auich_clear_cas(sc);
823 return -1;
824 }
825 if (reg == AC97_REG_GPIO_STATUS)
826 auich_clear_cas(sc);
827 return 0;
828 } else {
829 aprint_normal_dev(sc->sc_dev, "read_codec timeout\n");
830 if (reg == AC97_REG_GPIO_STATUS)
831 auich_clear_cas(sc);
832 return -1;
833 }
834}
835
836static int
837auich_write_codec(void *v, uint8_t reg, uint16_t val)
838{
839 struct auich_softc *sc;
840 int i;
841
842 sc = v;
843 DPRINTF(ICH_DEBUG_CODECIO, (sc->sc_dev, "%s(%x, %x)\n",
844 __func__, reg, val));
845 /* wait for an access semaphore */
846 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- &&
847 bus_space_read_1(sc->iot, sc->aud_ioh,
848 ICH_CAS + sc->sc_modem_offset) & 1;
849 DELAY(ICH_CODECIO_INTERVAL));
850
851 /* Be permissive in first attempt (see comments in auich_read_codec) */
852 if (!sc->sc_cas_been_used && i <= 0)
853 i = 1;
854 sc->sc_cas_been_used = 1;
855
856 if (i > 0) {
857 bus_space_write_2(sc->iot, sc->mix_ioh,
858 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val);
859 return 0;
860 } else {
861 aprint_normal_dev(sc->sc_dev, "write_codec timeout\n");
862 return -1;
863 }
864}
865
866static int
867auich_attach_codec(void *v, struct ac97_codec_if *cif)
868{
869 struct auich_softc *sc;
870
871 sc = v;
872 sc->codec_if = cif;
873
874 return 0;
875}
876
877static int
878auich_reset_codec(void *v)
879{
880 struct auich_softc *sc;
881 int i;
882 uint32_t control, status;
883
884 sc = v;
885 control = bus_space_read_4(sc->iot, sc->aud_ioh,
886 ICH_GCTRL + sc->sc_modem_offset);
887 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) {
888 control &= ~(ICH_ACLSO | sc->sc_pcm246_mask);
889 } else {
890 control &= ~ICH_ACLSO;
891 control |= ICH_GIE;
892 }
893 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET;
894 bus_space_write_4(sc->iot, sc->aud_ioh,
895 ICH_GCTRL + sc->sc_modem_offset, control);
896
897 for (i = 500000; i >= 0; i--) {
898 status = bus_space_read_4(sc->iot, sc->aud_ioh,
899 ICH_GSTS + sc->sc_modem_offset);
900 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR))
901 break;
902 DELAY(1);
903 }
904 if (i <= 0) {
905 aprint_error_dev(sc->sc_dev, "auich_reset_codec: time out\n");
906 return ETIMEDOUT;
907 }
908#ifdef AUICH_DEBUG
909 if (status & ICH_SCR)
910 aprint_normal_dev(sc->sc_dev, "The 2nd codec is ready.\n");
911 if (status & ICH_S2CR)
912 aprint_normal_dev(sc->sc_dev, "The 3rd codec is ready.\n");
913#endif
914 return 0;
915}
916
917static enum ac97_host_flags
918auich_flags_codec(void *v)
919{
920 struct auich_softc *sc = v;
921 return sc->sc_codecflags;
922}
923
924static void
925auich_spdif_event(void *addr, bool flag)
926{
927 struct auich_softc *sc;
928
929 sc = addr;
930 sc->sc_spdif = flag;
931}
932
933static int
934auich_open(void *addr, int flags)
935{
936 struct auich_softc *sc;
937
938 sc = (struct auich_softc *)addr;
939 mutex_spin_exit(&sc->sc_intr_lock);
940 sc->codec_if->vtbl->lock(sc->codec_if);
941 mutex_spin_enter(&sc->sc_intr_lock);
942 return 0;
943}
944
945static void
946auich_close(void *addr)
947{
948 struct auich_softc *sc;
949
950 sc = (struct auich_softc *)addr;
951 mutex_spin_exit(&sc->sc_intr_lock);
952 sc->codec_if->vtbl->unlock(sc->codec_if);
953 mutex_spin_enter(&sc->sc_intr_lock);
954}
955
956static int
957auich_query_encoding(void *v, struct audio_encoding *aep)
958{
959 struct auich_softc *sc;
960
961 sc = (struct auich_softc *)v;
962 return auconv_query_encoding(
963 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep);
964}
965
966static int
967auich_set_rate(struct auich_softc *sc, int mode, u_long srate)
968{
969 int ret;
970 u_int ratetmp;
971
972 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock);
973 ratetmp = srate;
974 if (mode == AUMODE_RECORD)
975 return sc->codec_if->vtbl->set_rate(sc->codec_if,
976 AC97_REG_PCM_LR_ADC_RATE, &ratetmp);
977 ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
978 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp);
979 if (ret)
980 return ret;
981 ratetmp = srate;
982 ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
983 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp);
984 if (ret)
985 return ret;
986 ratetmp = srate;
987 ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
988 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp);
989 return ret;
990}
991
992static int
993auich_set_params(void *v, int setmode, int usemode,
994 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil,
995 stream_filter_list_t *rfil)
996{
997 struct auich_softc *sc;
998 audio_params_t *p;
999 stream_filter_list_t *fil;
1000 int mode, index;
1001 uint32_t control;
1002
1003 sc = v;
1004 for (mode = AUMODE_RECORD; mode != -1;
1005 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) {
1006 if ((setmode & mode) == 0)
1007 continue;
1008
1009 p = mode == AUMODE_PLAY ? play : rec;
1010 fil = mode == AUMODE_PLAY ? pfil : rfil;
1011 if (p == NULL)
1012 continue;
1013
1014 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) {
1015 if (p->sample_rate < 8000 ||
1016 p->sample_rate > 48000)
1017 return EINVAL;
1018
1019 if (!sc->sc_spdif)
1020 index = auconv_set_converter(sc->sc_audio_formats,
1021 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil);
1022 else
1023 index = auconv_set_converter(auich_spdif_formats,
1024 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil);
1025 } else {
1026 if (p->sample_rate != 8000 && p->sample_rate != 16000)
1027 return EINVAL;
1028 index = auconv_set_converter(sc->sc_modem_formats,
1029 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil);
1030 }
1031 if (index < 0)
1032 return EINVAL;
1033 if (fil->req_size > 0)
1034 p = &fil->filters[0].param;
1035 /* p represents HW encoding */
1036 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) {
1037 if (sc->sc_audio_formats[index].frequency_type != 1
1038 && auich_set_rate(sc, mode, p->sample_rate))
1039 return EINVAL;
1040 } else {
1041 if (sc->sc_modem_formats[index].frequency_type != 1
1042 && auich_set_rate(sc, mode, p->sample_rate))
1043 return EINVAL;
1044 auich_write_codec(sc, AC97_REG_LINE1_RATE,
1045 p->sample_rate);
1046 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0);
1047 }
1048 if (mode == AUMODE_PLAY &&
1049 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) {
1050 control = bus_space_read_4(sc->iot, sc->aud_ioh,
1051 ICH_GCTRL + sc->sc_modem_offset);
1052 control &= ~sc->sc_pcm246_mask;
1053 if (p->channels == 4) {
1054 control |= sc->sc_pcm4;
1055 } else if (p->channels == 6) {
1056 control |= sc->sc_pcm6;
1057 }
1058 bus_space_write_4(sc->iot, sc->aud_ioh,
1059 ICH_GCTRL + sc->sc_modem_offset, control);
1060 }
1061 }
1062
1063 return 0;
1064}
1065
1066static int
1067auich_round_blocksize(void *v, int blk, int mode,
1068 const audio_params_t *param)
1069{
1070
1071 return blk & ~0x3f; /* keep good alignment */
1072}
1073
1074static void
1075auich_halt_pipe(struct auich_softc *sc, int pipe)
1076{
1077 int i;
1078 uint32_t status;
1079
1080 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0);
1081 for (i = 0; i < 100; i++) {
1082 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS);
1083 if (status & ICH_DCH)
1084 break;
1085 DELAY(1);
1086 }
1087 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR);
1088
1089#if AUICH_DEBUG
1090 if (i > 0)
1091 aprint_normal_dev(sc->sc_dev, "%s: halt took %d cycles\n",
1092 __func__, i);
1093#endif
1094}
1095
1096static int
1097auich_halt_output(void *v)
1098{
1099 struct auich_softc *sc;
1100
1101 sc = v;
1102 DPRINTF(ICH_DEBUG_DMA, (sc->sc_dev, "%s\n", __func__));
1103
1104 auich_halt_pipe(sc, ICH_PCMO);
1105 sc->pcmo.intr = NULL;
1106
1107 return 0;
1108}
1109
1110static int
1111auich_halt_input(void *v)
1112{
1113 struct auich_softc *sc;
1114
1115 sc = v;
1116 DPRINTF(ICH_DEBUG_DMA, (sc->sc_dev, "%s\n", __func__));
1117
1118 auich_halt_pipe(sc, ICH_PCMI);
1119 sc->pcmi.intr = NULL;
1120
1121 return 0;
1122}
1123
1124static int
1125auich_getdev(void *v, struct audio_device *adp)
1126{
1127 struct auich_softc *sc;
1128
1129 sc = v;
1130 *adp = sc->sc_audev;
1131 return 0;
1132}
1133
1134static int
1135auich_set_port(void *v, mixer_ctrl_t *cp)
1136{
1137 struct auich_softc *sc;
1138
1139 sc = v;
1140 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp);
1141}
1142
1143static int
1144auich_get_port(void *v, mixer_ctrl_t *cp)
1145{
1146 struct auich_softc *sc;
1147
1148 sc = v;
1149 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp);
1150}
1151
1152static int
1153auich_query_devinfo(void *v, mixer_devinfo_t *dp)
1154{
1155 struct auich_softc *sc;
1156
1157 sc = v;
1158 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp);
1159}
1160
1161static void *
1162auich_allocm(void *v, int direction, size_t size)
1163{
1164 struct auich_softc *sc;
1165 struct auich_dma *p;
1166 int error;
1167
1168 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX))
1169 return NULL;
1170
1171 p = kmem_alloc(sizeof(*p), KM_SLEEP);
1172 if (p == NULL)
1173 return NULL;
1174
1175 sc = v;
1176 error = auich_allocmem(sc, size, 0, p);
1177 if (error) {
1178 kmem_free(p, sizeof(*p));
1179 return NULL;
1180 }
1181
1182 p->next = sc->sc_dmas;
1183 sc->sc_dmas = p;
1184
1185 return KERNADDR(p);
1186}
1187
1188static void
1189auich_freem(void *v, void *ptr, size_t size)
1190{
1191 struct auich_softc *sc;
1192 struct auich_dma *p, **pp;
1193
1194 sc = v;
1195 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) {
1196 if (KERNADDR(p) == ptr) {
1197 auich_freemem(sc, p);
1198 *pp = p->next;
1199 kmem_free(p, sizeof(*p));
1200 return;
1201 }
1202 }
1203}
1204
1205static size_t
1206auich_round_buffersize(void *v, int direction, size_t size)
1207{
1208
1209 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX))
1210 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX;
1211
1212 return size;
1213}
1214
1215static paddr_t
1216auich_mappage(void *v, void *mem, off_t off, int prot)
1217{
1218 struct auich_softc *sc;
1219 struct auich_dma *p;
1220
1221 if (off < 0)
1222 return -1;
1223 sc = v;
1224 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next)
1225 continue;
1226 if (!p)
1227 return -1;
1228 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs,
1229 off, prot, BUS_DMA_WAITOK);
1230}
1231
1232static int
1233auich_get_props(void *v)
1234{
1235 struct auich_softc *sc;
1236 int props;
1237
1238 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
1239 sc = v;
1240 /*
1241 * Even if the codec is fixed-rate, set_param() succeeds for any sample
1242 * rate because of aurateconv. Applications can't know what rate the
1243 * device can process in the case of mmap().
1244 */
1245 if (!AC97_IS_FIXED_RATE(sc->codec_if) ||
1246 sc->sc_codectype == AC97_CODEC_TYPE_MODEM)
1247 props |= AUDIO_PROP_MMAP;
1248 return props;
1249}
1250
1251static int
1252auich_intr(void *v)
1253{
1254 struct auich_softc *sc;
1255 int ret, gsts;
1256#ifdef DIAGNOSTIC
1257 int csts;
1258#endif
1259
1260 sc = v;
1261
1262 if (!device_has_power(sc->sc_dev))
1263 return (0);
1264
1265 mutex_spin_enter(&sc->sc_intr_lock);
1266
1267 ret = 0;
1268#ifdef DIAGNOSTIC
1269 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG);
1270 if (csts & PCI_STATUS_MASTER_ABORT) {
1271 aprint_error_dev(sc->sc_dev, "%s: PCI master abort\n",
1272 __func__);
1273 }
1274#endif
1275
1276 gsts = bus_space_read_4(sc->iot, sc->aud_ioh,
1277 ICH_GSTS + sc->sc_modem_offset);
1278 DPRINTF(ICH_DEBUG_INTR, (sc->sc_dev, "%s: gsts=0x%x\n",
1279 __func__, gsts));
1280
1281 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) ||
1282 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) {
1283 int sts;
1284
1285 sts = bus_space_read_2(sc->iot, sc->aud_ioh,
1286 ICH_PCMO + sc->sc_sts_reg);
1287 DPRINTF(ICH_DEBUG_INTR,
1288 (sc->sc_dev, "%s: osts=0x%x\n", __func__, sts));
1289
1290 if (sts & ICH_FIFOE)
1291 aprint_error_dev(sc->sc_dev, "%s: fifo underrun\n",
1292 __func__);
1293
1294 if (sts & ICH_BCIS)
1295 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo);
1296
1297 /* int ack */
1298 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO +
1299 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE));
1300 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO)
1301 bus_space_write_4(sc->iot, sc->aud_ioh,
1302 ICH_GSTS + sc->sc_modem_offset, ICH_POINT);
1303 else
1304 bus_space_write_4(sc->iot, sc->aud_ioh,
1305 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT);
1306 ret++;
1307 }
1308
1309 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) ||
1310 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) {
1311 int sts;
1312
1313 sts = bus_space_read_2(sc->iot, sc->aud_ioh,
1314 ICH_PCMI + sc->sc_sts_reg);
1315 DPRINTF(ICH_DEBUG_INTR,
1316 (sc->sc_dev, "%s: ists=0x%x\n", __func__, sts));
1317
1318 if (sts & ICH_FIFOE)
1319 aprint_error_dev(sc->sc_dev, "%s: fifo overrun\n",
1320 __func__);
1321
1322 if (sts & ICH_BCIS)
1323 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi);
1324
1325 /* int ack */
1326 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI +
1327 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE));
1328 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO)
1329 bus_space_write_4(sc->iot, sc->aud_ioh,
1330 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT);
1331 else
1332 bus_space_write_4(sc->iot, sc->aud_ioh,
1333 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT);
1334 ret++;
1335 }
1336
1337 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) {
1338 int sts;
1339
1340 sts = bus_space_read_2(sc->iot, sc->aud_ioh,
1341 ICH_MICI + sc->sc_sts_reg);
1342 DPRINTF(ICH_DEBUG_INTR,
1343 (sc->sc_dev, "%s: ists=0x%x\n", __func__, sts));
1344
1345 if (sts & ICH_FIFOE)
1346 aprint_error_dev(sc->sc_dev, "%s: fifo overrun\n",
1347 __func__);
1348
1349 if (sts & ICH_BCIS)
1350 auich_intr_pipe(sc, ICH_MICI, &sc->mici);
1351
1352 /* int ack */
1353 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI +
1354 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE));
1355 bus_space_write_4(sc->iot, sc->aud_ioh,
1356 ICH_GSTS + sc->sc_modem_offset, ICH_MINT);
1357 ret++;
1358 }
1359
1360#ifdef AUICH_MODEM_DEBUG
1361 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) {
1362 aprint_normal_dev(sc->sc_dev, "gsts=0x%x\n", gsts);
1363 /* int ack */
1364 bus_space_write_4(sc->iot, sc->aud_ioh,
1365 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI);
1366 ret++;
1367 }
1368#endif
1369
1370 mutex_spin_exit(&sc->sc_intr_lock);
1371
1372 return ret;
1373}
1374
1375static void
1376auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring)
1377{
1378 int blksize, qptr;
1379 struct auich_dmalist *q;
1380
1381 blksize = ring->blksize;
1382
1383 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) {
1384 q = &ring->dmalist[qptr];
1385 q->base = ring->p;
1386 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC;
1387
1388 ring->p += blksize;
1389 if (ring->p >= ring->end)
1390 ring->p = ring->start;
1391 }
1392 ring->qptr = 0;
1393
1394 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI,
1395 (qptr - 1) & ICH_LVI_MASK);
1396 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL,
1397 ICH_IOCE | ICH_FEIE | ICH_RPBM);
1398}
1399
1400static void
1401auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring)
1402{
1403 int blksize, qptr, nqptr;
1404 struct auich_dmalist *q;
1405
1406 blksize = ring->blksize;
1407 qptr = ring->qptr;
1408 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV);
1409
1410 while (qptr != nqptr) {
1411 q = &ring->dmalist[qptr];
1412 q->base = ring->p;
1413 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC;
1414
1415 DPRINTF(ICH_DEBUG_INTR,
1416 (sc->sc_dev, "%s: %p, %p = %x @ 0x%x\n", __func__,
1417 &ring->dmalist[qptr], q, q->len, q->base));
1418
1419 ring->p += blksize;
1420 if (ring->p >= ring->end)
1421 ring->p = ring->start;
1422
1423 qptr = (qptr + 1) & ICH_LVI_MASK;
1424 if (ring->intr)
1425 ring->intr(ring->arg);
1426 }
1427 ring->qptr = qptr;
1428
1429 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI,
1430 (qptr - 1) & ICH_LVI_MASK);
1431}
1432
1433static int
1434auich_trigger_output(void *v, void *start, void *end, int blksize,
1435 void (*intr)(void *), void *arg, const audio_params_t *param)
1436{
1437 struct auich_softc *sc;
1438 struct auich_dma *p;
1439 size_t size;
1440
1441 sc = v;
1442 DPRINTF(ICH_DEBUG_DMA,
1443 (sc->sc_dev, "%s(%p, %p, %d, %p, %p, %p)\n", __func__,
1444 start, end, blksize, intr, arg, param));
1445
1446 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next)
1447 continue;
1448 if (!p) {
1449 aprint_error_dev(sc->sc_dev, "%s: bad addr %p\n", __func__,
1450 start);
1451 return EINVAL;
1452 }
1453
1454 size = (size_t)((char *)end - (char *)start);
1455
1456 sc->pcmo.intr = intr;
1457 sc->pcmo.arg = arg;
1458 sc->pcmo.start = DMAADDR(p);
1459 sc->pcmo.p = sc->pcmo.start;
1460 sc->pcmo.end = sc->pcmo.start + size;
1461 sc->pcmo.blksize = blksize;
1462
1463 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR,
1464 sc->sc_cddma + ICH_PCMO_OFF(0));
1465 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo);
1466
1467 return 0;
1468}
1469
1470static int
1471auich_trigger_input(void *v, void *start, void *end, int blksize,
1472 void (*intr)(void *), void *arg, const audio_params_t *param)
1473{
1474 struct auich_softc *sc;
1475 struct auich_dma *p;
1476 size_t size;
1477
1478 sc = v;
1479 DPRINTF(ICH_DEBUG_DMA,
1480 (sc->sc_dev, "%s(%p, %p, %d, %p, %p, %p)\n", __func__,
1481 start, end, blksize, intr, arg, param));
1482
1483 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next)
1484 continue;
1485 if (!p) {
1486 aprint_error_dev(sc->sc_dev, "%s: bad addr %p\n", __func__,
1487 start);
1488 return EINVAL;
1489 }
1490
1491 size = (size_t)((char *)end - (char *)start);
1492
1493 sc->pcmi.intr = intr;
1494 sc->pcmi.arg = arg;
1495 sc->pcmi.start = DMAADDR(p);
1496 sc->pcmi.p = sc->pcmi.start;
1497 sc->pcmi.end = sc->pcmi.start + size;
1498 sc->pcmi.blksize = blksize;
1499
1500 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR,
1501 sc->sc_cddma + ICH_PCMI_OFF(0));
1502 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi);
1503
1504 return 0;
1505}
1506
1507static int
1508auich_allocmem(struct auich_softc *sc, size_t size, size_t align,
1509 struct auich_dma *p)
1510{
1511 int error;
1512
1513 p->size = size;
1514 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0,
1515 p->segs, sizeof(p->segs)/sizeof(p->segs[0]),
1516 &p->nsegs, BUS_DMA_WAITOK);
1517 if (error)
1518 return error;
1519
1520 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size,
1521 &p->addr, BUS_DMA_WAITOK|sc->sc_dmamap_flags);
1522 if (error)
1523 goto free;
1524
1525 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size,
1526 0, BUS_DMA_WAITOK, &p->map);
1527 if (error)
1528 goto unmap;
1529
1530 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL,
1531 BUS_DMA_WAITOK);
1532 if (error)
1533 goto destroy;
1534 return 0;
1535
1536 destroy:
1537 bus_dmamap_destroy(sc->dmat, p->map);
1538 unmap:
1539 bus_dmamem_unmap(sc->dmat, p->addr, p->size);
1540 free:
1541 bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
1542 return error;
1543}
1544
1545static int
1546auich_freemem(struct auich_softc *sc, struct auich_dma *p)
1547{
1548
1549 bus_dmamap_unload(sc->dmat, p->map);
1550 bus_dmamap_destroy(sc->dmat, p->map);
1551 bus_dmamem_unmap(sc->dmat, p->addr, p->size);
1552 bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
1553 return 0;
1554}
1555
1556static int
1557auich_alloc_cdata(struct auich_softc *sc)
1558{
1559 bus_dma_segment_t seg;
1560 int error, rseg;
1561
1562 /*
1563 * Allocate the control data structure, and create and load the
1564 * DMA map for it.
1565 */
1566 if ((error = bus_dmamem_alloc(sc->dmat,
1567 sizeof(struct auich_cdata),
1568 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) {
1569 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", error);
1570 goto fail_0;
1571 }
1572
1573 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg,
1574 sizeof(struct auich_cdata),
1575 (void **) &sc->sc_cdata,
1576 sc->sc_dmamap_flags)) != 0) {
1577 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", error);
1578 goto fail_1;
1579 }
1580
1581 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1,
1582 sizeof(struct auich_cdata), 0, 0,
1583 &sc->sc_cddmamap)) != 0) {
1584 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, "
1585 "error = %d\n", error);
1586 goto fail_2;
1587 }
1588
1589 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap,
1590 sc->sc_cdata, sizeof(struct auich_cdata),
1591 NULL, 0)) != 0) {
1592 aprint_error_dev(sc->sc_dev, "unable tp load control data DMA map, "
1593 "error = %d\n", error);
1594 goto fail_3;
1595 }
1596
1597 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo;
1598 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi;
1599 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici;
1600
1601 return 0;
1602
1603 fail_3:
1604 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap);
1605 fail_2:
1606 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata,
1607 sizeof(struct auich_cdata));
1608 fail_1:
1609 bus_dmamem_free(sc->dmat, &seg, rseg);
1610 fail_0:
1611 return error;
1612}
1613
1614static bool
1615auich_resume(device_t dv, const pmf_qual_t *qual)
1616{
1617 struct auich_softc *sc = device_private(dv);
1618 pcireg_t v;
1619
1620 mutex_enter(&sc->sc_lock);
1621 mutex_spin_enter(&sc->sc_intr_lock);
1622
1623 if (sc->sc_iose) {
1624 v = pci_conf_read(sc->sc_pc, sc->sc_pt, ICH_CFG);
1625 pci_conf_write(sc->sc_pc, sc->sc_pt, ICH_CFG,
1626 v | ICH_CFG_IOSE);
1627 }
1628
1629 auich_reset_codec(sc);
1630 mutex_spin_exit(&sc->sc_intr_lock);
1631 DELAY(1000);
1632 (sc->codec_if->vtbl->restore_ports)(sc->codec_if);
1633 mutex_exit(&sc->sc_lock);
1634
1635 return true;
1636}
1637
1638/*
1639 * Calibrate card (some boards are overclocked and need scaling)
1640 */
1641static void
1642auich_calibrate(struct auich_softc *sc)
1643{
1644 struct timeval t1, t2;
1645 uint8_t ociv, nciv;
1646 uint64_t wait_us;
1647 uint32_t actual_48k_rate, bytes, ac97rate;
1648 void *temp_buffer;
1649 struct auich_dma *p;
1650 u_int rate;
1651
1652 /*
1653 * Grab audio from input for fixed interval and compare how
1654 * much we actually get with what we expect. Interval needs
1655 * to be sufficiently short that no interrupts are
1656 * generated.
1657 */
1658
1659 /* Force the codec to a known state first. */
1660 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000);
1661 rate = sc->sc_ac97_clock = 48000;
1662 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE,
1663 &rate);
1664
1665 /* Setup a buffer */
1666 bytes = 64000;
1667 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes);
1668
1669 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next)
1670 continue;
1671 if (p == NULL) {
1672 aprint_error_dev(sc->sc_dev, "%s: bad address %p\n",
1673 __func__, temp_buffer);
1674 return;
1675 }
1676 sc->pcmi.dmalist[0].base = DMAADDR(p);
1677 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift);
1678
1679 /*
1680 * our data format is stereo, 16 bit so each sample is 4 bytes.
1681 * assuming we get 48000 samples per second, we get 192000 bytes/sec.
1682 * we're going to start recording with interrupts disabled and measure
1683 * the time taken for one block to complete. we know the block size,
1684 * we know the time in microseconds, we calculate the sample rate:
1685 *
1686 * actual_rate [bps] = bytes / (time [s] * 4)
1687 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4)
1688 * actual_rate [Hz] = (bytes * 250000) / time [us]
1689 */
1690
1691 /* prepare */
1692 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV);
1693 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR,
1694 sc->sc_cddma + ICH_PCMI_OFF(0));
1695 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI,
1696 (0 - 1) & ICH_LVI_MASK);
1697
1698 /* start */
1699 kpreempt_disable();
1700 microtime(&t1);
1701 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM);
1702
1703 /* wait */
1704 nciv = ociv;
1705 do {
1706 microtime(&t2);
1707 if (t2.tv_sec - t1.tv_sec > 1)
1708 break;
1709 nciv = bus_space_read_1(sc->iot, sc->aud_ioh,
1710 ICH_PCMI + ICH_CIV);
1711 } while (nciv == ociv);
1712 microtime(&t2);
1713
1714 /* stop */
1715 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0);
1716 kpreempt_enable();
1717
1718 /* reset */
1719 DELAY(100);
1720 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR);
1721
1722 /* turn time delta into us */
1723 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec;
1724
1725 auich_freem(sc, temp_buffer, bytes);
1726
1727 if (nciv == ociv) {
1728 aprint_error_dev(sc->sc_dev, "ac97 link rate calibration "
1729 "timed out after %" PRIu64 " us\n", wait_us);
1730 return;
1731 }
1732
1733 if (wait_us == 0) {
1734 /* Can happen with emulated hardware */
1735 aprint_error_dev(sc->sc_dev, "abnormal zero delay during "
1736 "calibration\n");
1737 return;
1738 }
1739
1740 rnd_add_data(NULL, &wait_us, sizeof(wait_us), 1);
1741
1742 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us;
1743
1744 if (actual_48k_rate < 50000)
1745 ac97rate = 48000;
1746 else
1747 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000;
1748
1749 aprint_verbose_dev(sc->sc_dev, "measured ac97 link rate at %d Hz",
1750 actual_48k_rate);
1751 if (ac97rate != actual_48k_rate)
1752 aprint_verbose(", will use %d Hz", ac97rate);
1753 aprint_verbose("\n");
1754
1755 sc->sc_ac97_clock = ac97rate;
1756}
1757
1758static void
1759auich_clear_cas(struct auich_softc *sc)
1760{
1761 /* Clear the codec access semaphore */
1762 (void)bus_space_read_2(sc->iot, sc->mix_ioh,
1763 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET));
1764
1765 return;
1766}
1767
1768static void
1769auich_get_locks(void *addr, kmutex_t **intr, kmutex_t **thread)
1770{
1771 struct auich_softc *sc;
1772
1773 sc = addr;
1774 *intr = &sc->sc_intr_lock;
1775 *thread = &sc->sc_lock;
1776}
1777