1 | /*- |
2 | * Copyright (c) 2004 |
3 | * Bill Paul <wpaul@windriver.com>. All rights reserved. |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
8 | * 1. Redistributions of source code must retain the above copyright |
9 | * notice, this list of conditions and the following disclaimer. |
10 | * 2. Redistributions in binary form must reproduce the above copyright |
11 | * notice, this list of conditions and the following disclaimer in the |
12 | * documentation and/or other materials provided with the distribution. |
13 | * 3. All advertising materials mentioning features or use of this software |
14 | * must display the following acknowledgement: |
15 | * This product includes software developed by Bill Paul. |
16 | * 4. Neither the name of the author nor the names of any co-contributors |
17 | * may be used to endorse or promote products derived from this software |
18 | * without specific prior written permission. |
19 | * |
20 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
21 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
23 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
24 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
30 | * THE POSSIBILITY OF SUCH DAMAGE. |
31 | * |
32 | * $FreeBSD: src/sys/dev/vge/if_vgereg.h,v 1.2 2005/01/06 01:43:31 imp Exp $ |
33 | */ |
34 | |
35 | /* |
36 | * Register definitions for the VIA VT6122 gigabit ethernet controller. |
37 | * Definitions for the built-in copper PHY can be found in vgphy.h. |
38 | * |
39 | * The VT612x controllers have 256 bytes of register space. The |
40 | * manual seems to imply that the registers should all be accessed |
41 | * using 32-bit I/O cycles, but some of them are less than 32 bits |
42 | * wide. Go figure. |
43 | */ |
44 | |
45 | #ifndef _IF_VGEREG_H_ |
46 | #define _IF_VGEREG_H_ |
47 | |
48 | #define VGE_PAR0 0x00 /* physical address register */ |
49 | #define VGE_PAR1 0x02 |
50 | #define VGE_PAR2 0x04 |
51 | #define VGE_RXCTL 0x06 /* RX control register */ |
52 | #define VGE_TXCTL 0x07 /* TX control register */ |
53 | #define VGE_CRS0 0x08 /* Global cmd register 0 (w to set) */ |
54 | #define VGE_CRS1 0x09 /* Global cmd register 1 (w to set) */ |
55 | #define VGE_CRS2 0x0A /* Global cmd register 2 (w to set) */ |
56 | #define VGE_CRS3 0x0B /* Global cmd register 3 (w to set) */ |
57 | #define VGE_CRC0 0x0C /* Global cmd register 0 (w to clr) */ |
58 | #define VGE_CRC1 0x0D /* Global cmd register 1 (w to clr) */ |
59 | #define VGE_CRC2 0x0E /* Global cmd register 2 (w to clr) */ |
60 | #define VGE_CRC3 0x0F /* Global cmd register 3 (w to clr) */ |
61 | #define VGE_MAR0 0x10 /* Mcast hash/CAM register 0 */ |
62 | #define VGE_MAR1 0x14 /* Mcast hash/CAM register 1 */ |
63 | #define VGE_CAM0 0x10 |
64 | #define VGE_CAM1 0x11 |
65 | #define VGE_CAM2 0x12 |
66 | #define VGE_CAM3 0x13 |
67 | #define VGE_CAM4 0x14 |
68 | #define VGE_CAM5 0x15 |
69 | #define VGE_CAM6 0x16 |
70 | #define VGE_CAM7 0x17 |
71 | #define VGE_TXDESC_HIADDR 0x18 /* Hi part of 64bit txdesc base addr */ |
72 | #define VGE_DATABUF_HIADDR 0x1C /* Hi part of 64bit data buffer addr */ |
73 | #define VGE_INTCTL0 0x20 /* interrupt control register */ |
74 | #define VGE_RXSUPPTHR 0x20 |
75 | #define VGE_TXSUPPTHR 0x20 |
76 | #define VGE_INTHOLDOFF 0x20 |
77 | #define VGE_INTCTL1 0x21 /* interrupt control register */ |
78 | #define VGE_TXHOSTERR 0x22 /* TX host error status */ |
79 | #define VGE_RXHOSTERR 0x23 /* RX host error status */ |
80 | #define VGE_ISR 0x24 /* Interrupt status register */ |
81 | #define VGE_IMR 0x28 /* Interrupt mask register */ |
82 | #define VGE_TXSTS_PORT 0x2C /* Transmit status port (???) */ |
83 | #define VGE_TXQCSRS 0x30 /* TX queue ctl/status set */ |
84 | #define VGE_RXQCSRS 0x32 /* RX queue ctl/status set */ |
85 | #define VGE_TXQCSRC 0x34 /* TX queue ctl/status clear */ |
86 | #define VGE_RXQCSRC 0x36 /* RX queue ctl/status clear */ |
87 | #define VGE_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */ |
88 | #define VGE_RXDESC_CONSIDX 0x3C /* Current RX descriptor index */ |
89 | #define VGE_RXQTIMER 0x3E /* RX queue timer pend register */ |
90 | #define VGE_TXQTIMER 0x3F /* TX queue timer pend register */ |
91 | #define VGE_TXDESC_ADDR_LO0 0x40 /* TX desc0 base addr (lo 32 bits) */ |
92 | #define VGE_TXDESC_ADDR_LO1 0x44 /* TX desc1 base addr (lo 32 bits) */ |
93 | #define VGE_TXDESC_ADDR_LO2 0x48 /* TX desc2 base addr (lo 32 bits) */ |
94 | #define VGE_TXDESC_ADDR_LO3 0x4C /* TX desc3 base addr (lo 32 bits) */ |
95 | #define VGE_RXDESCNUM 0x50 /* Size of RX desc ring */ |
96 | #define VGE_TXDESCNUM 0x52 /* Size of TX desc ring */ |
97 | #define VGE_TXDESC_CONSIDX0 0x54 /* Current TX descriptor index */ |
98 | #define VGE_TXDESC_CONSIDX1 0x56 /* Current TX descriptor index */ |
99 | #define VGE_TXDESC_CONSIDX2 0x58 /* Current TX descriptor index */ |
100 | #define VGE_TXDESC_CONSIDX3 0x5A /* Current TX descriptor index */ |
101 | #define VGE_TX_PAUSE_TIMER 0x5C /* TX pause frame timer */ |
102 | #define VGE_RXDESC_RESIDUECNT 0x5E /* RX descriptor residue count */ |
103 | #define VGE_FIFOTEST0 0x60 /* FIFO test register */ |
104 | #define VGE_FIFOTEST1 0x64 /* FIFO test register */ |
105 | #define VGE_CAMADDR 0x68 /* CAM address register */ |
106 | #define VGE_CAMCTL 0x69 /* CAM control register */ |
107 | #define VGE_GFTEST 0x6A |
108 | #define VGE_FTSCMD 0x6B |
109 | #define VGE_MIICFG 0x6C /* MII port config register */ |
110 | #define VGE_MIISTS 0x6D /* MII port status register */ |
111 | #define VGE_PHYSTS0 0x6E /* PHY status register */ |
112 | #define VGE_PHYSTS1 0x6F /* PHY status register */ |
113 | #define VGE_MIICMD 0x70 /* MII command register */ |
114 | #define VGE_MIIADDR 0x71 /* MII address register */ |
115 | #define VGE_MIIDATA 0x72 /* MII data register */ |
116 | #define VGE_SSTIMER 0x74 /* single-shot timer */ |
117 | #define VGE_PTIMER 0x76 /* periodic timer */ |
118 | #define VGE_CHIPCFG0 0x78 /* chip config A */ |
119 | #define VGE_CHIPCFG1 0x79 /* chip config B */ |
120 | #define VGE_CHIPCFG2 0x7A /* chip config C */ |
121 | #define VGE_CHIPCFG3 0x7B /* chip config D */ |
122 | #define VGE_DMACFG0 0x7C /* DMA config 0 */ |
123 | #define VGE_DMACFG1 0x7D /* DMA config 1 */ |
124 | #define VGE_RXCFG 0x7E /* MAC RX config */ |
125 | #define VGE_TXCFG 0x7F /* MAC TX config */ |
126 | #define VGE_PWRMGMT 0x82 /* power management shadow register */ |
127 | #define VGE_PWRSTAT 0x83 /* power state shadow register */ |
128 | #define VGE_MIBCSR 0x84 /* MIB control/status register */ |
129 | #define VGE_SWEEDATA 0x85 /* EEPROM software loaded data */ |
130 | #define VGE_MIBDATA 0x88 /* MIB data register */ |
131 | #define VGE_EEWRDAT 0x8C /* EEPROM embedded write */ |
132 | #define VGE_EECSUM 0x92 /* EEPROM checksum */ |
133 | #define VGE_EECSR 0x93 /* EEPROM control/status */ |
134 | #define VGE_EERDDAT 0x94 /* EEPROM embedded read */ |
135 | #define VGE_EEADDR 0x96 /* EEPROM address */ |
136 | #define VGE_EECMD 0x97 /* EEPROM embedded command */ |
137 | #define VGE_CHIPSTRAP 0x99 /* Chip jumper strapping status */ |
138 | #define VGE_MEDIASTRAP 0x9B /* Media jumper strapping */ |
139 | #define VGE_DIAGSTS 0x9C /* Chip diagnostic status */ |
140 | #define VGE_DBGCTL 0x9E /* Chip debug control */ |
141 | #define VGE_DIAGCTL 0x9F /* Chip diagnostic control */ |
142 | #define VGE_WOLCR0S 0xA0 /* WOL0 event set */ |
143 | #define VGE_WOLCR1S 0xA1 /* WOL1 event set */ |
144 | #define VGE_PWRCFGS 0xA2 /* Power management config set */ |
145 | #define VGE_WOLCFGS 0xA3 /* WOL config set */ |
146 | #define VGE_WOLCR0C 0xA4 /* WOL0 event clear */ |
147 | #define VGE_WOLCR1C 0xA5 /* WOL1 event clear */ |
148 | #define VGE_PWRCFGC 0xA6 /* Power management config clear */ |
149 | #define VGE_WOLCFGC 0xA7 /* WOL config clear */ |
150 | #define VGE_WOLSR0S 0xA8 /* WOL status set */ |
151 | #define VGE_WOLSR1S 0xA9 /* WOL status set */ |
152 | #define VGE_WOLSR0C 0xAC /* WOL status clear */ |
153 | #define VGE_WOLSR1C 0xAD /* WOL status clear */ |
154 | #define VGE_WAKEPAT_CRC0 0xB0 |
155 | #define VGE_WAKEPAT_CRC1 0xB2 |
156 | #define VGE_WAKEPAT_CRC2 0xB4 |
157 | #define VGE_WAKEPAT_CRC3 0xB6 |
158 | #define VGE_WAKEPAT_CRC4 0xB8 |
159 | #define VGE_WAKEPAT_CRC5 0xBA |
160 | #define VGE_WAKEPAT_CRC6 0xBC |
161 | #define VGE_WAKEPAT_CRC7 0xBE |
162 | #define VGE_WAKEPAT_MSK0_0 0xC0 |
163 | #define VGE_WAKEPAT_MSK0_1 0xC4 |
164 | #define VGE_WAKEPAT_MSK0_2 0xC8 |
165 | #define VGE_WAKEPAT_MSK0_3 0xCC |
166 | #define VGE_WAKEPAT_MSK1_0 0xD0 |
167 | #define VGE_WAKEPAT_MSK1_1 0xD4 |
168 | #define VGE_WAKEPAT_MSK1_2 0xD8 |
169 | #define VGE_WAKEPAT_MSK1_3 0xDC |
170 | #define VGE_WAKEPAT_MSK2_0 0xE0 |
171 | #define VGE_WAKEPAT_MSK2_1 0xE4 |
172 | #define VGE_WAKEPAT_MSK2_2 0xE8 |
173 | #define VGE_WAKEPAT_MSK2_3 0xEC |
174 | #define VGE_WAKEPAT_MSK3_0 0xF0 |
175 | #define VGE_WAKEPAT_MSK3_1 0xF4 |
176 | #define VGE_WAKEPAT_MSK3_2 0xF8 |
177 | #define VGE_WAKEPAT_MSK3_3 0xFC |
178 | |
179 | /* Receive control register */ |
180 | |
181 | #define VGE_RXCTL_RX_BADFRAMES 0x01 /* accept CRC error frames */ |
182 | #define VGE_RXCTL_RX_RUNT 0x02 /* accept runts */ |
183 | #define VGE_RXCTL_RX_MCAST 0x04 /* accept multicasts */ |
184 | #define VGE_RXCTL_RX_BCAST 0x08 /* accept broadcasts */ |
185 | #define VGE_RXCTL_RX_PROMISC 0x10 /* promisc mode */ |
186 | #define VGE_RXCTL_RX_GIANT 0x20 /* accept VLAN tagged frames */ |
187 | #define VGE_RXCTL_RX_UCAST 0x40 /* use perfect filtering */ |
188 | #define VGE_RXCTL_RX_SYMERR 0x80 /* accept symbol err packet */ |
189 | |
190 | /* Transmit control register */ |
191 | |
192 | #define VGE_TXCTL_LOOPCTL 0x03 /* loopback control */ |
193 | #define VGE_TXCTL_COLLCTL 0x0C /* collision retry control */ |
194 | |
195 | #define VGE_TXLOOPCTL_OFF 0x00 |
196 | #define VGE_TXLOOPCTL_MAC_INTERNAL 0x01 |
197 | #define VGE_TXLOOPCTL_EXTERNAL 0x02 |
198 | |
199 | #define VGE_TXCOLLS_NORMAL 0x00 /* one set of 16 retries */ |
200 | #define VGE_TXCOLLS_32 0x04 /* two sets of 16 retries */ |
201 | #define VGE_TXCOLLS_48 0x08 /* three sets of 16 retries */ |
202 | #define VGE_TXCOLLS_INFINITE 0x0C /* retry forever */ |
203 | |
204 | /* Global command register 0 */ |
205 | |
206 | #define VGE_CR0_START 0x01 /* start NIC */ |
207 | #define VGE_CR0_STOP 0x02 /* stop NIC */ |
208 | #define VGE_CR0_RX_ENABLE 0x04 /* turn on RX engine */ |
209 | #define VGE_CR0_TX_ENABLE 0x08 /* turn on TX engine */ |
210 | |
211 | /* Global command register 1 */ |
212 | |
213 | #define VGE_CR1_NOUCAST 0x01 /* disable unicast reception */ |
214 | #define VGE_CR1_NOPOLL 0x08 /* disable RX/TX desc polling */ |
215 | #define VGE_CR1_TIMER0_ENABLE 0x20 /* enable single shot timer */ |
216 | #define VGE_CR1_TIMER1_ENABLE 0x40 /* enable periodic timer */ |
217 | #define VGE_CR1_SOFTRESET 0x80 /* software reset */ |
218 | |
219 | /* Global command register 2 */ |
220 | |
221 | #define VGE_CR2_TXPAUSE_THRESH_LO 0x03 /* TX pause frame lo threshold */ |
222 | #define VGE_CR2_TXPAUSE_THRESH_HI 0x0C /* TX pause frame hi threshold */ |
223 | #define VGE_CR2_HDX_FLOWCTL_ENABLE 0x10 /* half duplex flow control */ |
224 | #define VGE_CR2_FDX_RXFLOWCTL_ENABLE 0x20 /* full duplex RX flow control */ |
225 | #define VGE_CR2_FDX_TXFLOWCTL_ENABLE 0x40 /* full duplex TX flow control */ |
226 | #define VGE_CR2_XON_ENABLE 0x80 /* 802.3x XON/XOFF flow control */ |
227 | |
228 | /* Global command register 3 */ |
229 | |
230 | #define VGE_CR3_INT_SWPEND 0x01 /* disable multi-level int bits */ |
231 | #define VGE_CR3_INT_GMSK 0x02 /* mask off all interrupts */ |
232 | #define VGE_CR3_INT_HOLDOFF 0x04 /* enable int hold off timer */ |
233 | #define VGE_CR3_DIAG 0x10 /* diagnostic enabled */ |
234 | #define VGE_CR3_PHYRST 0x20 /* assert PHYRSTZ */ |
235 | #define VGE_CR3_STOP_FORCE 0x40 /* force NIC to stopped state */ |
236 | |
237 | /* Interrupt control register */ |
238 | |
239 | #define VGE_INTCTL_SC_RELOAD 0x01 /* reload hold timer */ |
240 | #define VGE_INTCTL_HC_RELOAD 0x02 /* enable hold timer reload */ |
241 | #define VGE_INTCTL_STATUS 0x04 /* interrupt pending status */ |
242 | #define VGE_INTCTL_MASK 0x18 /* multilayer int mask */ |
243 | #define VGE_INTCTL_RXINTSUP_DISABLE 0x20 /* disable RX int supression */ |
244 | #define VGE_INTCTL_TXINTSUP_DISABLE 0x40 /* disable TX int supression */ |
245 | #define VGE_INTCTL_SOFTINT 0x80 /* request soft interrupt */ |
246 | |
247 | #define VGE_INTMASK_LAYER0 0x00 |
248 | #define VGE_INTMASK_LAYER1 0x08 |
249 | #define VGE_INTMASK_ALL 0x10 |
250 | #define VGE_INTMASK_ALL2 0x18 |
251 | |
252 | /* Transmit host error status register */ |
253 | |
254 | #define VGE_TXHOSTERR_TDSTRUCT 0x01 /* bad TX desc structure */ |
255 | #define VGE_TXHOSTERR_TDFETCH_BUSERR 0x02 /* bus error on desc fetch */ |
256 | #define VGE_TXHOSTERR_TDWBACK_BUSERR 0x04 /* bus error on desc writeback */ |
257 | #define VGE_TXHOSTERR_FIFOERR 0x08 /* TX FIFO DMA bus error */ |
258 | |
259 | /* Receive host error status register */ |
260 | |
261 | #define VGE_RXHOSTERR_RDSTRUCT 0x01 /* bad RX desc structure */ |
262 | #define VGE_RXHOSTERR_RDFETCH_BUSERR 0x02 /* bus error on desc fetch */ |
263 | #define VGE_RXHOSTERR_RDWBACK_BUSERR 0x04 /* bus error on desc writeback */ |
264 | #define VGE_RXHOSTERR_FIFOERR 0x08 /* RX FIFO DMA bus error */ |
265 | |
266 | /* Interrupt status register */ |
267 | |
268 | #define VGE_ISR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */ |
269 | #define VGE_ISR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */ |
270 | #define VGE_ISR_RXOK 0x00000004 /* normal RX done */ |
271 | #define VGE_ISR_TXOK 0x00000008 /* combo results for next 4 bits */ |
272 | #define VGE_ISR_TXOK0 0x00000010 /* TX complete on queue 0 */ |
273 | #define VGE_ISR_TXOK1 0x00000020 /* TX complete on queue 1 */ |
274 | #define VGE_ISR_TXOK2 0x00000040 /* TX complete on queue 2 */ |
275 | #define VGE_ISR_TXOK3 0x00000080 /* TX complete on queue 3 */ |
276 | #define VGE_ISR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */ |
277 | #define VGE_ISR_RXPAUSE 0x00000800 /* pause frame RX'ed */ |
278 | #define VGE_ISR_RXOFLOW 0x00001000 /* RX FIFO overflow */ |
279 | #define VGE_ISR_RXNODESC 0x00002000 /* ran out of RX descriptors */ |
280 | #define VGE_ISR_RXNODESC_WARN 0x00004000 /* running out of RX descs */ |
281 | #define VGE_ISR_LINKSTS 0x00008000 /* link status change */ |
282 | #define VGE_ISR_TIMER0 0x00010000 /* one shot timer expired */ |
283 | #define VGE_ISR_TIMER1 0x00020000 /* periodic timer expired */ |
284 | #define VGE_ISR_PWR 0x00040000 /* wake up power event */ |
285 | #define VGE_ISR_PHYINT 0x00080000 /* PHY interrupt */ |
286 | #define VGE_ISR_STOPPED 0x00100000 /* software shutdown complete */ |
287 | #define VGE_ISR_MIBOFLOW 0x00200000 /* MIB counter overflow warning */ |
288 | #define VGE_ISR_SOFTINT 0x00400000 /* software interrupt */ |
289 | #define VGE_ISR_HOLDOFF_RELOAD 0x00800000 /* reload hold timer */ |
290 | #define VGE_ISR_RXDMA_STALL 0x01000000 /* RX DMA stall */ |
291 | #define VGE_ISR_TXDMA_STALL 0x02000000 /* TX DMA STALL */ |
292 | #define VGE_ISR_ISRC0 0x10000000 /* interrupt source indication */ |
293 | #define VGE_ISR_ISRC1 0x20000000 /* interrupt source indication */ |
294 | #define VGE_ISR_ISRC2 0x40000000 /* interrupt source indication */ |
295 | #define VGE_ISR_ISRC3 0x80000000 /* interrupt source indication */ |
296 | |
297 | #define VGE_INTRS (VGE_ISR_TXOK0|VGE_ISR_RXOK|VGE_ISR_STOPPED| \ |
298 | VGE_ISR_RXOFLOW|VGE_ISR_PHYINT| \ |
299 | VGE_ISR_LINKSTS|VGE_ISR_RXNODESC| \ |
300 | VGE_ISR_RXDMA_STALL|VGE_ISR_TXDMA_STALL| \ |
301 | VGE_ISR_MIBOFLOW|VGE_ISR_TIMER0) |
302 | |
303 | /* Interrupt mask register */ |
304 | |
305 | #define VGE_IMR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */ |
306 | #define VGE_IMR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */ |
307 | #define VGE_IMR_RXOK 0x00000004 /* normal RX done */ |
308 | #define VGE_IMR_TXOK 0x00000008 /* combo results for next 4 bits */ |
309 | #define VGE_IMR_TXOK0 0x00000010 /* TX complete on queue 0 */ |
310 | #define VGE_IMR_TXOK1 0x00000020 /* TX complete on queue 1 */ |
311 | #define VGE_IMR_TXOK2 0x00000040 /* TX complete on queue 2 */ |
312 | #define VGE_IMR_TXOK3 0x00000080 /* TX complete on queue 3 */ |
313 | #define VGE_IMR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */ |
314 | #define VGE_IMR_RXPAUSE 0x00000800 /* pause frame RX'ed */ |
315 | #define VGE_IMR_RXOFLOW 0x00001000 /* RX FIFO overflow */ |
316 | #define VGE_IMR_RXNODESC 0x00002000 /* ran out of RX descriptors */ |
317 | #define VGE_IMR_RXNODESC_WARN 0x00004000 /* running out of RX descs */ |
318 | #define VGE_IMR_LINKSTS 0x00008000 /* link status change */ |
319 | #define VGE_IMR_TIMER0 0x00010000 /* one shot timer expired */ |
320 | #define VGE_IMR_TIMER1 0x00020000 /* periodic timer expired */ |
321 | #define VGE_IMR_PWR 0x00040000 /* wake up power event */ |
322 | #define VGE_IMR_PHYINT 0x00080000 /* PHY interrupt */ |
323 | #define VGE_IMR_STOPPED 0x00100000 /* software shutdown complete */ |
324 | #define VGE_IMR_MIBOFLOW 0x00200000 /* MIB counter overflow warning */ |
325 | #define VGE_IMR_SOFTINT 0x00400000 /* software interrupt */ |
326 | #define VGE_IMR_HOLDOFF_RELOAD 0x00800000 /* reload hold timer */ |
327 | #define VGE_IMR_RXDMA_STALL 0x01000000 /* RX DMA stall */ |
328 | #define VGE_IMR_TXDMA_STALL 0x02000000 /* TX DMA STALL */ |
329 | #define VGE_IMR_ISRC0 0x10000000 /* interrupt source indication */ |
330 | #define VGE_IMR_ISRC1 0x20000000 /* interrupt source indication */ |
331 | #define VGE_IMR_ISRC2 0x40000000 /* interrupt source indication */ |
332 | #define VGE_IMR_ISRC3 0x80000000 /* interrupt source indication */ |
333 | |
334 | /* TX descriptor queue control/status register */ |
335 | |
336 | #define VGE_TXQCSR_RUN0 0x0001 /* Enable TX queue 0 */ |
337 | #define VGE_TXQCSR_ACT0 0x0002 /* queue 0 active indicator */ |
338 | #define VGE_TXQCSR_WAK0 0x0004 /* Wake up (poll) queue 0 */ |
339 | #define VGE_TXQCST_DEAD0 0x0008 /* queue 0 dead indicator */ |
340 | #define VGE_TXQCSR_RUN1 0x0010 /* Enable TX queue 1 */ |
341 | #define VGE_TXQCSR_ACT1 0x0020 /* queue 1 active indicator */ |
342 | #define VGE_TXQCSR_WAK1 0x0040 /* Wake up (poll) queue 1 */ |
343 | #define VGE_TXQCST_DEAD1 0x0080 /* queue 1 dead indicator */ |
344 | #define VGE_TXQCSR_RUN2 0x0100 /* Enable TX queue 2 */ |
345 | #define VGE_TXQCSR_ACT2 0x0200 /* queue 2 active indicator */ |
346 | #define VGE_TXQCSR_WAK2 0x0400 /* Wake up (poll) queue 2 */ |
347 | #define VGE_TXQCST_DEAD2 0x0800 /* queue 2 dead indicator */ |
348 | #define VGE_TXQCSR_RUN3 0x1000 /* Enable TX queue 3 */ |
349 | #define VGE_TXQCSR_ACT3 0x2000 /* queue 3 active indicator */ |
350 | #define VGE_TXQCSR_WAK3 0x4000 /* Wake up (poll) queue 3 */ |
351 | #define VGE_TXQCST_DEAD3 0x8000 /* queue 3 dead indicator */ |
352 | |
353 | /* RX descriptor queue control/status register */ |
354 | |
355 | #define VGE_RXQCSR_RUN 0x0001 /* Enable RX queue */ |
356 | #define VGE_RXQCSR_ACT 0x0002 /* queue active indicator */ |
357 | #define VGE_RXQCSR_WAK 0x0004 /* Wake up (poll) queue */ |
358 | #define VGE_RXQCSR_DEAD 0x0008 /* queue dead indicator */ |
359 | |
360 | /* RX/TX queue empty interrupt delay timer register */ |
361 | |
362 | #define VGE_QTIMER_PENDCNT 0x3F |
363 | #define VGE_QTIMER_RESOLUTION 0xC0 |
364 | |
365 | #define VGE_QTIMER_RES_1US 0x00 |
366 | #define VGE_QTIMER_RES_4US 0x40 |
367 | #define VGE_QTIMER_RES_16US 0x80 |
368 | #define VGE_QTIMER_RES_64US 0xC0 |
369 | |
370 | /* CAM address register */ |
371 | |
372 | #define VGE_CAMADDR_ADDR 0x3F /* CAM address to program */ |
373 | #define VGE_CAMADDR_AVSEL 0x40 /* 0 = address cam, 1 = VLAN cam */ |
374 | #define VGE_CAMADDR_ENABLE 0x80 /* enable CAM read/write */ |
375 | |
376 | #define VGE_CAM_MAXADDRS 64 |
377 | |
378 | /* |
379 | * CAM command register |
380 | * Note that the page select bits in this register affect three |
381 | * different things: |
382 | * - The behavior of the MAR0/MAR1 registers at offset 0x10 (the |
383 | * page select bits control whether the MAR0/MAR1 registers affect |
384 | * the multicast hash filter or the CAM table) |
385 | * - The behavior of the interrupt holdoff timer register at offset |
386 | * 0x20 (the page select bits allow you to set the interrupt |
387 | * holdoff timer, the TX interrupt supression count or the |
388 | * RX interrupt supression count) |
389 | * - The behavior the WOL pattern programming registers at offset |
390 | * 0xC0 (controls which pattern is set) |
391 | */ |
392 | |
393 | |
394 | #define VGE_CAMCTL_WRITE 0x04 /* CAM write command */ |
395 | #define VGE_CAMCTL_READ 0x08 /* CAM read command */ |
396 | #define VGE_CAMCTL_INTPKT_SIZ 0x10 /* select interesting pkt CAM size */ |
397 | #define VGE_CAMCTL_INTPKT_ENB 0x20 /* enable interesting packet mode */ |
398 | #define VGE_CAMCTL_PAGESEL 0xC0 /* page select */ |
399 | |
400 | #define VGE_PAGESEL_MAR 0x00 |
401 | #define VGE_PAGESEL_CAMMASK 0x40 |
402 | #define VGE_PAGESEL_CAMDATA 0x80 |
403 | |
404 | #define VGE_PAGESEL_INTHLDOFF 0x00 |
405 | #define VGE_PAGESEL_TXSUPPTHR 0x40 |
406 | #define VGE_PAGESEL_RXSUPPTHR 0x80 |
407 | |
408 | #define VGE_PAGESEL_WOLPAT0 0x00 |
409 | #define VGE_PAGESEL_WOLPAT1 0x40 |
410 | |
411 | /* MII port config register */ |
412 | |
413 | #define VGE_MIICFG_PHYADDR 0x1F /* PHY address (internal PHY is 1) */ |
414 | #define VGE_MIICFG_MDCSPEED 0x20 /* MDC accelerate x 4 */ |
415 | #define VGE_MIICFG_POLLINT 0xC0 /* polling interval */ |
416 | |
417 | #define VGE_MIIPOLLINT_1024 0x00 |
418 | #define VGE_MIIPOLLINT_512 0x40 |
419 | #define VGE_MIIPOLLINT_128 0x80 |
420 | #define VGE_MIIPOLLINT_64 0xC0 |
421 | |
422 | /* MII port status register */ |
423 | |
424 | #define VGE_MIISTS_IIDL 0x80 /* not at sofrware/timer poll cycle */ |
425 | |
426 | /* PHY status register */ |
427 | |
428 | #define VGE_PHYSTS_TXFLOWCAP 0x01 /* resolved TX flow control cap */ |
429 | #define VGE_PHYSTS_RXFLOWCAP 0x02 /* resolved RX flow control cap */ |
430 | #define VGE_PHYSTS_SPEED10 0x04 /* PHY in 10Mbps mode */ |
431 | #define VGE_PHYSTS_SPEED1000 0x08 /* PHY in giga mode */ |
432 | #define VGE_PHYSTS_FDX 0x10 /* PHY in full duplex mode */ |
433 | #define VGE_PHYSTS_LINK 0x40 /* link status */ |
434 | #define VGE_PHYSTS_RESETSTS 0x80 /* reset status */ |
435 | |
436 | /* MII management command register */ |
437 | |
438 | #define VGE_MIICMD_MDC 0x01 /* clock pin */ |
439 | #define VGE_MIICMD_MDI 0x02 /* data in pin */ |
440 | #define VGE_MIICMD_MDO 0x04 /* data out pin */ |
441 | #define VGE_MIICMD_MOUT 0x08 /* data out pin enable */ |
442 | #define VGE_MIICMD_MDP 0x10 /* enable direct programming mode */ |
443 | #define VGE_MIICMD_WCMD 0x20 /* embedded mode write */ |
444 | #define VGE_MIICMD_RCMD 0x40 /* embadded mode read */ |
445 | #define VGE_MIICMD_MAUTO 0x80 /* enable autopolling */ |
446 | |
447 | /* MII address register */ |
448 | |
449 | #define VGE_MIIADDR_SWMPL 0x80 /* initiate priority resolution */ |
450 | |
451 | /* Chip config register A */ |
452 | |
453 | #define VGE_CHIPCFG0_PACPI 0x01 /* pre-ACPI wakeup function */ |
454 | #define VGE_CHIPCFG0_ABSHDN 0x02 /* abnormal shutdown function */ |
455 | #define VGE_CHIPCFG0_GPIO1PD 0x04 /* GPIO pin enable */ |
456 | #define VGE_CHIPCFG0_SKIPTAG 0x08 /* omit 802.1p tag from CRC calc */ |
457 | #define VGE_CHIPCFG0_PHLED 0x30 /* phy LED select */ |
458 | |
459 | /* Chip config register B */ |
460 | /* Note: some of these bits are not documented in the manual! */ |
461 | |
462 | #define VGE_CHIPCFG1_BAKOPT 0x01 |
463 | #define VGE_CHIPCFG1_MBA 0x02 |
464 | #define VGE_CHIPCFG1_CAP 0x04 |
465 | #define VGE_CHIPCFG1_CRANDOM 0x08 |
466 | #define VGE_CHIPCFG1_OFSET 0x10 |
467 | #define VGE_CHIPCFG1_SLOTTIME 0x20 /* slot time 512/500 in giga mode */ |
468 | #define VGE_CHIPCFG1_MIIOPT 0x40 |
469 | #define VGE_CHIPCFG1_GTCKOPT 0x80 |
470 | |
471 | /* Chip config register C */ |
472 | |
473 | #define VGE_CHIPCFG2_EELOAD 0x80 /* enable EEPROM programming */ |
474 | |
475 | /* Chip config register D */ |
476 | |
477 | #define VGE_CHIPCFG3_64BIT_DAC 0x20 /* enable 64bit via DAC */ |
478 | #define VGE_CHIPCFG3_IODISABLE 0x80 /* disable I/O access mode */ |
479 | |
480 | /* DMA config register 0 */ |
481 | |
482 | #define VGE_DMACFG0_BURSTLEN 0x07 /* RX/TX DMA burst (in dwords) */ |
483 | |
484 | #define VGE_DMABURST_8 0x00 |
485 | #define VGE_DMABURST_16 0x01 |
486 | #define VGE_DMABURST_32 0x02 |
487 | #define VGE_DMABURST_64 0x03 |
488 | #define VGE_DMABURST_128 0x04 |
489 | #define VGE_DMABURST_256 0x05 |
490 | #define VGE_DMABURST_STRFWD 0x07 |
491 | |
492 | /* DMA config register 1 */ |
493 | |
494 | #define VGE_DMACFG1_LATENB 0x01 /* Latency timer enable */ |
495 | #define VGE_DMACFG1_MWWAIT 0x02 /* insert wait on master write */ |
496 | #define VGE_DMACFG1_MRWAIT 0x04 /* insert wait on master read */ |
497 | #define VGE_DMACFG1_MRM 0x08 /* use memory read multiple */ |
498 | #define VGE_DMACFG1_PERR_DIS 0x10 /* disable parity error checking */ |
499 | #define VGE_DMACFG1_XMRL 0x20 /* disable memory read line support */ |
500 | |
501 | /* RX MAC config register */ |
502 | |
503 | #define VGE_RXCFG_VLANFILT 0x01 /* filter VLAN ID mismatches */ |
504 | #define VGE_RXCFG_VTAGOPT 0x06 /* VLAN tag handling */ |
505 | #define VGE_RXCFG_FIFO_LOWAT 0x08 /* RX FIFO low watermark (7QW/15QW) */ |
506 | #define VGE_RXCFG_FIFO_THR 0x30 /* RX FIFO threshold */ |
507 | #define VGE_RXCFG_ARB_PRIO 0x80 /* arbitration priority */ |
508 | |
509 | #define VGE_VTAG_OPT0 0x00 /* TX: no tag insertion |
510 | RX: rx all, no tag extraction */ |
511 | |
512 | #define VGE_VTAG_OPT1 0x02 /* TX: no tag insertion |
513 | RX: rx only tagged pkts, no |
514 | extraction */ |
515 | |
516 | #define VGE_VTAG_OPT2 0x04 /* TX: perform tag insertion, |
517 | RX: rx all, extract tags */ |
518 | |
519 | #define VGE_VTAG_OPT3 0x06 /* TX: perform tag insertion, |
520 | RX: rx only tagged pkts, |
521 | with extraction */ |
522 | |
523 | #define VGE_RXFIFOTHR_128BYTES 0x00 |
524 | #define VGE_RXFIFOTHR_512BYTES 0x10 |
525 | #define VGE_RXFIFOTHR_1024BYTES 0x20 |
526 | #define VGE_RXFIFOTHR_STRNFWD 0x30 |
527 | |
528 | /* TX MAC config register */ |
529 | |
530 | #define VGE_TXCFG_SNAPOPT 0x01 /* 1 == insert VLAN tag at |
531 | 13th byte |
532 | 0 == insert VLANM tag after |
533 | SNAP header (21st byte) */ |
534 | #define VGE_TXCFG_NONBLK 0x02 /* priority TX/non-blocking mode */ |
535 | #define VGE_TXCFG_NONBLK_THR 0x0C /* non-blocking threshold */ |
536 | #define VGE_TXCFG_ARB_PRIO 0x80 /* arbitration priority */ |
537 | |
538 | #define VGE_TXBLOCK_64PKTS 0x00 |
539 | #define VGE_TXBLOCK_32PKTS 0x04 |
540 | #define VGE_TXBLOCK_128PKTS 0x08 |
541 | #define VGE_TXBLOCK_8PKTS 0x0C |
542 | |
543 | /* EEPROM control/status register */ |
544 | |
545 | #define VGE_EECSR_EDO 0x01 /* data out pin */ |
546 | #define VGE_EECSR_EDI 0x02 /* data in pin */ |
547 | #define VGE_EECSR_ECK 0x04 /* clock pin */ |
548 | #define VGE_EECSR_ECS 0x08 /* chip select pin */ |
549 | #define VGE_EECSR_DPM 0x10 /* direct program mode enable */ |
550 | #define VGE_EECSR_RELOAD 0x20 /* trigger reload from EEPROM */ |
551 | #define VGE_EECSR_EMBP 0x40 /* embedded program mode enable */ |
552 | |
553 | /* EEPROM embedded command register */ |
554 | |
555 | #define VGE_EECMD_ERD 0x01 /* EEPROM read command */ |
556 | #define VGE_EECMD_EWR 0x02 /* EEPROM write command */ |
557 | #define VGE_EECMD_EWEN 0x04 /* EEPROM write enable */ |
558 | #define VGE_EECMD_EWDIS 0x08 /* EEPROM write disable */ |
559 | #define VGE_EECMD_EDONE 0x80 /* read/write done */ |
560 | |
561 | /* Chip operation and diagnostic control register */ |
562 | |
563 | #define VGE_DIAGCTL_PHYINT_ENB 0x01 /* Enable PHY interrupts */ |
564 | #define VGE_DIAGCTL_TIMER0_RES 0x02 /* timer0 uSec resolution */ |
565 | #define VGE_DIAGCTL_TIMER1_RES 0x04 /* timer1 uSec resolution */ |
566 | #define VGE_DIAGCTL_LPSEL_DIS 0x08 /* disable LPSEL field */ |
567 | #define VGE_DIAGCTL_MACFORCE 0x10 /* MAC side force mode */ |
568 | #define VGE_DIAGCTL_FCRSVD 0x20 /* reserved for future fiber use */ |
569 | #define VGE_DIAGCTL_FDXFORCE 0x40 /* force full duplex mode */ |
570 | #define VGE_DIAGCTL_GMII 0x80 /* force GMII mode, otherwise MII */ |
571 | |
572 | /* Location of station address in EEPROM */ |
573 | #define VGE_EE_EADDR 0 |
574 | |
575 | /* DMA descriptor structures */ |
576 | |
577 | /* |
578 | * Each TX DMA descriptor has a control and status word, and 7 |
579 | * fragment address/length words. If a transmitted packet spans |
580 | * more than 7 fragments, it has to be coalesced. |
581 | */ |
582 | |
583 | #define VGE_TX_FRAGS 7 |
584 | #define VGE_TX_MAXLEN (1 << 14) /* maximum TX packet size */ |
585 | |
586 | struct vge_txfrag { |
587 | volatile uint32_t tf_addrlo; |
588 | volatile uint16_t tf_addrhi; |
589 | volatile uint16_t tf_buflen; |
590 | }; |
591 | |
592 | /* |
593 | * The high bit in the buflen field of fragment #0 has special meaning. |
594 | * Normally, the chip requires the driver to issue a TX poll command |
595 | * for every packet that gets put in the TX DMA queue. Sometimes though, |
596 | * the driver might want to queue up several packets at once and just |
597 | * issue one transmit command to have all of them processed. In order |
598 | * to obtain this behavior, the special 'queue' bit must be set. |
599 | */ |
600 | |
601 | #define VGE_TXDESC_Q 0x8000 |
602 | |
603 | struct vge_txdesc { |
604 | volatile uint32_t td_sts; |
605 | volatile uint32_t td_ctl; |
606 | struct vge_txfrag td_frag[VGE_TX_FRAGS]; |
607 | }; |
608 | |
609 | #define VGE_TDSTS_COLLCNT 0x0000000F /* TX collision count */ |
610 | #define VGE_TDSTS_COLL 0x00000010 /* collision seen */ |
611 | #define VGE_TDSTS_OWINCOLL 0x00000020 /* out of window collision */ |
612 | #define VGE_TDSTS_OWT 0x00000040 /* jumbo frame tx abort */ |
613 | #define VGE_TDSTS_EXCESSCOLL 0x00000080 /* TX aborted, excess colls */ |
614 | #define VGE_TDSTS_HBEATFAIL 0x00000100 /* heartbeat detect failed */ |
615 | #define VGE_TDSTS_CARRLOSS 0x00000200 /* carrier sense lost */ |
616 | #define VGE_TDSTS_SHUTDOWN 0x00000400 /* shutdown during TX */ |
617 | #define VGE_TDSTS_LINKFAIL 0x00001000 /* link fail during TX */ |
618 | #define VGE_TDSTS_GMII 0x00002000 /* GMII transmission */ |
619 | #define VGE_TDSTS_FDX 0x00004000 /* full duplex transmit */ |
620 | #define VGE_TDSTS_TXERR 0x00008000 /* error occurred */ |
621 | #define VGE_TDSTS_SEGSIZE 0x3FFF0000 /* TCP large send size */ |
622 | #define VGE_TDSTS_OWN 0x80000000 /* own bit */ |
623 | |
624 | #define VGE_TDCTL_VLANID 0x00000FFF /* VLAN ID */ |
625 | #define VGE_TDCTL_CFI 0x00001000 /* VLAN CFI bit */ |
626 | #define VGE_TDCTL_PRIO 0x0000E000 /* VLAN prio bits */ |
627 | #define VGE_TDCTL_NOCRC 0x00010000 /* disable CRC generation */ |
628 | #define VGE_TDCTL_JUMBO 0x00020000 /* jumbo frame */ |
629 | #define VGE_TDCTL_TCPCSUM 0x00040000 /* do TCP hw checksum */ |
630 | #define VGE_TDCTL_UDPCSUM 0x00080000 /* do UDP hw checksum */ |
631 | #define VGE_TDCTL_IPCSUM 0x00100000 /* do IP hw checksum */ |
632 | #define VGE_TDCTL_VTAG 0x00200000 /* insert VLAN tag */ |
633 | #define VGE_TDCTL_PRIO_INT 0x00400000 /* priority int request */ |
634 | #define VGE_TDCTL_TIC 0x00800000 /* transfer int request */ |
635 | #define VGE_TDCTL_TCPLSCTL 0x03000000 /* TCP large send ctl */ |
636 | #define VGE_TDCTL_FRAGCNT 0xF0000000 /* number of frags used */ |
637 | |
638 | #define VGE_TD_LS_MOF 0x00000000 /* middle of large send */ |
639 | #define VGE_TD_LS_SOF 0x01000000 /* start of large send */ |
640 | #define VGE_TD_LS_EOF 0x02000000 /* end of large send */ |
641 | #define VGE_TD_LS_NORM 0x03000000 /* normal frame */ |
642 | |
643 | /* Receive DMA descriptors have a single fragment pointer. */ |
644 | |
645 | struct vge_rxdesc { |
646 | volatile uint32_t rd_sts; |
647 | volatile uint32_t rd_ctl; |
648 | volatile uint32_t rd_addrlo; |
649 | volatile uint16_t rd_addrhi; |
650 | volatile uint16_t rd_buflen; |
651 | }; |
652 | |
653 | /* |
654 | * Like the TX descriptor, the high bit in the buflen field in the |
655 | * RX descriptor has special meaning. This bit controls whether or |
656 | * not interrupts are generated for this descriptor. |
657 | */ |
658 | |
659 | #define VGE_RXDESC_I 0x8000 |
660 | |
661 | #define VGE_RDSTS_VIDM 0x00000001 /* VLAN tag filter miss */ |
662 | #define VGE_RDSTS_CRCERR 0x00000002 /* bad CRC error */ |
663 | #define VGE_RDSTS_FAERR 0x00000004 /* frame alignment error */ |
664 | #define VGE_RDSTS_CSUMERR 0x00000008 /* bad TCP/IP checksum */ |
665 | #define VGE_RDSTS_RLERR 0x00000010 /* RX length error */ |
666 | #define VGE_RDSTS_SYMERR 0x00000020 /* PCS symbol error */ |
667 | #define VGE_RDSTS_SNTAG 0x00000040 /* RX'ed tagged SNAP pkt */ |
668 | #define VGE_RDSTS_DETAG 0x00000080 /* VLAN tag extracted */ |
669 | #define VGE_RDSTS_BOUNDARY 0x00000300 /* frame boundary bits */ |
670 | #define VGE_RDSTS_VTAG 0x00000400 /* VLAN tag indicator */ |
671 | #define VGE_RDSTS_UCAST 0x00000800 /* unicast frame */ |
672 | #define VGE_RDSTS_BCAST 0x00001000 /* broadcast frame */ |
673 | #define VGE_RDSTS_MCAST 0x00002000 /* multicast frame */ |
674 | #define VGE_RDSTS_PFT 0x00004000 /* perfect filter hit */ |
675 | #define VGE_RDSTS_RXOK 0x00008000 /* frame is good. */ |
676 | #define VGE_RDSTS_BUFSIZ 0x3FFF0000 /* received frame len */ |
677 | #define VGE_RDSTS_SHUTDOWN 0x40000000 /* shutdown during RX */ |
678 | #define VGE_RDSTS_OWN 0x80000000 /* own bit. */ |
679 | |
680 | #define VGE_RXPKT_ONEFRAG 0x00000000 /* only one fragment */ |
681 | #define VGE_RXPKT_EOF 0x00000100 /* first frag in frame */ |
682 | #define VGE_RXPKT_SOF 0x00000200 /* last frag in frame */ |
683 | #define VGE_RXPKT_MOF 0x00000300 /* intermediate frag */ |
684 | |
685 | #define VGE_RDCTL_VLANID 0x0000FFFF /* VLAN ID info */ |
686 | #define VGE_RDCTL_UDPPKT 0x00010000 /* UDP packet received */ |
687 | #define VGE_RDCTL_TCPPKT 0x00020000 /* TCP packet received */ |
688 | #define VGE_RDCTL_IPPKT 0x00040000 /* IP packet received */ |
689 | #define VGE_RDCTL_UDPZERO 0x00080000 /* pkt with UDP CSUM of 0 */ |
690 | #define VGE_RDCTL_FRAG 0x00100000 /* received IP frag */ |
691 | #define VGE_RDCTL_PROTOCSUMOK 0x00200000 /* TCP/UDP checksum ok */ |
692 | #define VGE_RDCTL_IPCSUMOK 0x00400000 /* IP checksum ok */ |
693 | #define VGE_RDCTL_FILTIDX 0x3C000000 /* interesting filter idx */ |
694 | |
695 | #endif /* _IF_VGEREG_H_ */ |
696 | |