1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 | * DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: |
24 | * Eric Anholt <eric@anholt.net> |
25 | */ |
26 | |
27 | #include <linux/dmi.h> |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> |
30 | #include <linux/i2c.h> |
31 | #include <linux/kernel.h> |
32 | #include <linux/slab.h> |
33 | #include <linux/vgaarb.h> |
34 | #include <drm/drm_edid.h> |
35 | #include <drm/drmP.h> |
36 | #include "intel_drv.h" |
37 | #include <drm/i915_drm.h> |
38 | #include "i915_drv.h" |
39 | #include "i915_trace.h" |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> |
42 | #include <linux/dma_remapping.h> |
43 | #include <linux/err.h> |
44 | #include <asm/bug.h> |
45 | #include <linux/math64.h> |
46 | #include <linux/bitops.h> |
47 | #include <linux/log2.h> |
48 | |
49 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
50 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
51 | |
52 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
53 | struct intel_crtc_config *pipe_config); |
54 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
55 | struct intel_crtc_config *pipe_config); |
56 | |
57 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
58 | int x, int y, struct drm_framebuffer *old_fb); |
59 | static int intel_framebuffer_init(struct drm_device *dev, |
60 | struct intel_framebuffer *ifb, |
61 | struct drm_mode_fb_cmd2 *mode_cmd, |
62 | struct drm_i915_gem_object *obj); |
63 | |
64 | typedef struct { |
65 | int min, max; |
66 | } intel_range_t; |
67 | |
68 | typedef struct { |
69 | int dot_limit; |
70 | int p2_slow, p2_fast; |
71 | } intel_p2_t; |
72 | |
73 | typedef struct intel_limit intel_limit_t; |
74 | struct intel_limit { |
75 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
76 | intel_p2_t p2; |
77 | }; |
78 | |
79 | int |
80 | intel_pch_rawclk(struct drm_device *dev) |
81 | { |
82 | struct drm_i915_private *dev_priv = dev->dev_private; |
83 | |
84 | WARN_ON(!HAS_PCH_SPLIT(dev)); |
85 | |
86 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; |
87 | } |
88 | |
89 | static inline u32 /* units of 100MHz */ |
90 | intel_fdi_link_freq(struct drm_device *dev) |
91 | { |
92 | if (IS_GEN5(dev)) { |
93 | struct drm_i915_private *dev_priv = dev->dev_private; |
94 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
95 | } else |
96 | return 27; |
97 | } |
98 | |
99 | static const intel_limit_t intel_limits_i8xx_dac = { |
100 | .dot = { .min = 25000, .max = 350000 }, |
101 | .vco = { .min = 908000, .max = 1512000 }, |
102 | .n = { .min = 2, .max = 16 }, |
103 | .m = { .min = 96, .max = 140 }, |
104 | .m1 = { .min = 18, .max = 26 }, |
105 | .m2 = { .min = 6, .max = 16 }, |
106 | .p = { .min = 4, .max = 128 }, |
107 | .p1 = { .min = 2, .max = 33 }, |
108 | .p2 = { .dot_limit = 165000, |
109 | .p2_slow = 4, .p2_fast = 2 }, |
110 | }; |
111 | |
112 | static const intel_limit_t intel_limits_i8xx_dvo = { |
113 | .dot = { .min = 25000, .max = 350000 }, |
114 | .vco = { .min = 908000, .max = 1512000 }, |
115 | .n = { .min = 2, .max = 16 }, |
116 | .m = { .min = 96, .max = 140 }, |
117 | .m1 = { .min = 18, .max = 26 }, |
118 | .m2 = { .min = 6, .max = 16 }, |
119 | .p = { .min = 4, .max = 128 }, |
120 | .p1 = { .min = 2, .max = 33 }, |
121 | .p2 = { .dot_limit = 165000, |
122 | .p2_slow = 4, .p2_fast = 4 }, |
123 | }; |
124 | |
125 | static const intel_limit_t intel_limits_i8xx_lvds = { |
126 | .dot = { .min = 25000, .max = 350000 }, |
127 | .vco = { .min = 908000, .max = 1512000 }, |
128 | .n = { .min = 2, .max = 16 }, |
129 | .m = { .min = 96, .max = 140 }, |
130 | .m1 = { .min = 18, .max = 26 }, |
131 | .m2 = { .min = 6, .max = 16 }, |
132 | .p = { .min = 4, .max = 128 }, |
133 | .p1 = { .min = 1, .max = 6 }, |
134 | .p2 = { .dot_limit = 165000, |
135 | .p2_slow = 14, .p2_fast = 7 }, |
136 | }; |
137 | |
138 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
139 | .dot = { .min = 20000, .max = 400000 }, |
140 | .vco = { .min = 1400000, .max = 2800000 }, |
141 | .n = { .min = 1, .max = 6 }, |
142 | .m = { .min = 70, .max = 120 }, |
143 | .m1 = { .min = 8, .max = 18 }, |
144 | .m2 = { .min = 3, .max = 7 }, |
145 | .p = { .min = 5, .max = 80 }, |
146 | .p1 = { .min = 1, .max = 8 }, |
147 | .p2 = { .dot_limit = 200000, |
148 | .p2_slow = 10, .p2_fast = 5 }, |
149 | }; |
150 | |
151 | static const intel_limit_t intel_limits_i9xx_lvds = { |
152 | .dot = { .min = 20000, .max = 400000 }, |
153 | .vco = { .min = 1400000, .max = 2800000 }, |
154 | .n = { .min = 1, .max = 6 }, |
155 | .m = { .min = 70, .max = 120 }, |
156 | .m1 = { .min = 8, .max = 18 }, |
157 | .m2 = { .min = 3, .max = 7 }, |
158 | .p = { .min = 7, .max = 98 }, |
159 | .p1 = { .min = 1, .max = 8 }, |
160 | .p2 = { .dot_limit = 112000, |
161 | .p2_slow = 14, .p2_fast = 7 }, |
162 | }; |
163 | |
164 | |
165 | static const intel_limit_t intel_limits_g4x_sdvo = { |
166 | .dot = { .min = 25000, .max = 270000 }, |
167 | .vco = { .min = 1750000, .max = 3500000}, |
168 | .n = { .min = 1, .max = 4 }, |
169 | .m = { .min = 104, .max = 138 }, |
170 | .m1 = { .min = 17, .max = 23 }, |
171 | .m2 = { .min = 5, .max = 11 }, |
172 | .p = { .min = 10, .max = 30 }, |
173 | .p1 = { .min = 1, .max = 3}, |
174 | .p2 = { .dot_limit = 270000, |
175 | .p2_slow = 10, |
176 | .p2_fast = 10 |
177 | }, |
178 | }; |
179 | |
180 | static const intel_limit_t intel_limits_g4x_hdmi = { |
181 | .dot = { .min = 22000, .max = 400000 }, |
182 | .vco = { .min = 1750000, .max = 3500000}, |
183 | .n = { .min = 1, .max = 4 }, |
184 | .m = { .min = 104, .max = 138 }, |
185 | .m1 = { .min = 16, .max = 23 }, |
186 | .m2 = { .min = 5, .max = 11 }, |
187 | .p = { .min = 5, .max = 80 }, |
188 | .p1 = { .min = 1, .max = 8}, |
189 | .p2 = { .dot_limit = 165000, |
190 | .p2_slow = 10, .p2_fast = 5 }, |
191 | }; |
192 | |
193 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
194 | .dot = { .min = 20000, .max = 115000 }, |
195 | .vco = { .min = 1750000, .max = 3500000 }, |
196 | .n = { .min = 1, .max = 3 }, |
197 | .m = { .min = 104, .max = 138 }, |
198 | .m1 = { .min = 17, .max = 23 }, |
199 | .m2 = { .min = 5, .max = 11 }, |
200 | .p = { .min = 28, .max = 112 }, |
201 | .p1 = { .min = 2, .max = 8 }, |
202 | .p2 = { .dot_limit = 0, |
203 | .p2_slow = 14, .p2_fast = 14 |
204 | }, |
205 | }; |
206 | |
207 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
208 | .dot = { .min = 80000, .max = 224000 }, |
209 | .vco = { .min = 1750000, .max = 3500000 }, |
210 | .n = { .min = 1, .max = 3 }, |
211 | .m = { .min = 104, .max = 138 }, |
212 | .m1 = { .min = 17, .max = 23 }, |
213 | .m2 = { .min = 5, .max = 11 }, |
214 | .p = { .min = 14, .max = 42 }, |
215 | .p1 = { .min = 2, .max = 6 }, |
216 | .p2 = { .dot_limit = 0, |
217 | .p2_slow = 7, .p2_fast = 7 |
218 | }, |
219 | }; |
220 | |
221 | static const intel_limit_t intel_limits_pineview_sdvo = { |
222 | .dot = { .min = 20000, .max = 400000}, |
223 | .vco = { .min = 1700000, .max = 3500000 }, |
224 | /* Pineview's Ncounter is a ring counter */ |
225 | .n = { .min = 3, .max = 6 }, |
226 | .m = { .min = 2, .max = 256 }, |
227 | /* Pineview only has one combined m divider, which we treat as m2. */ |
228 | .m1 = { .min = 0, .max = 0 }, |
229 | .m2 = { .min = 0, .max = 254 }, |
230 | .p = { .min = 5, .max = 80 }, |
231 | .p1 = { .min = 1, .max = 8 }, |
232 | .p2 = { .dot_limit = 200000, |
233 | .p2_slow = 10, .p2_fast = 5 }, |
234 | }; |
235 | |
236 | static const intel_limit_t intel_limits_pineview_lvds = { |
237 | .dot = { .min = 20000, .max = 400000 }, |
238 | .vco = { .min = 1700000, .max = 3500000 }, |
239 | .n = { .min = 3, .max = 6 }, |
240 | .m = { .min = 2, .max = 256 }, |
241 | .m1 = { .min = 0, .max = 0 }, |
242 | .m2 = { .min = 0, .max = 254 }, |
243 | .p = { .min = 7, .max = 112 }, |
244 | .p1 = { .min = 1, .max = 8 }, |
245 | .p2 = { .dot_limit = 112000, |
246 | .p2_slow = 14, .p2_fast = 14 }, |
247 | }; |
248 | |
249 | /* Ironlake / Sandybridge |
250 | * |
251 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
252 | * the range value for them is (actual_value - 2). |
253 | */ |
254 | static const intel_limit_t intel_limits_ironlake_dac = { |
255 | .dot = { .min = 25000, .max = 350000 }, |
256 | .vco = { .min = 1760000, .max = 3510000 }, |
257 | .n = { .min = 1, .max = 5 }, |
258 | .m = { .min = 79, .max = 127 }, |
259 | .m1 = { .min = 12, .max = 22 }, |
260 | .m2 = { .min = 5, .max = 9 }, |
261 | .p = { .min = 5, .max = 80 }, |
262 | .p1 = { .min = 1, .max = 8 }, |
263 | .p2 = { .dot_limit = 225000, |
264 | .p2_slow = 10, .p2_fast = 5 }, |
265 | }; |
266 | |
267 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
268 | .dot = { .min = 25000, .max = 350000 }, |
269 | .vco = { .min = 1760000, .max = 3510000 }, |
270 | .n = { .min = 1, .max = 3 }, |
271 | .m = { .min = 79, .max = 118 }, |
272 | .m1 = { .min = 12, .max = 22 }, |
273 | .m2 = { .min = 5, .max = 9 }, |
274 | .p = { .min = 28, .max = 112 }, |
275 | .p1 = { .min = 2, .max = 8 }, |
276 | .p2 = { .dot_limit = 225000, |
277 | .p2_slow = 14, .p2_fast = 14 }, |
278 | }; |
279 | |
280 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
281 | .dot = { .min = 25000, .max = 350000 }, |
282 | .vco = { .min = 1760000, .max = 3510000 }, |
283 | .n = { .min = 1, .max = 3 }, |
284 | .m = { .min = 79, .max = 127 }, |
285 | .m1 = { .min = 12, .max = 22 }, |
286 | .m2 = { .min = 5, .max = 9 }, |
287 | .p = { .min = 14, .max = 56 }, |
288 | .p1 = { .min = 2, .max = 8 }, |
289 | .p2 = { .dot_limit = 225000, |
290 | .p2_slow = 7, .p2_fast = 7 }, |
291 | }; |
292 | |
293 | /* LVDS 100mhz refclk limits. */ |
294 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
295 | .dot = { .min = 25000, .max = 350000 }, |
296 | .vco = { .min = 1760000, .max = 3510000 }, |
297 | .n = { .min = 1, .max = 2 }, |
298 | .m = { .min = 79, .max = 126 }, |
299 | .m1 = { .min = 12, .max = 22 }, |
300 | .m2 = { .min = 5, .max = 9 }, |
301 | .p = { .min = 28, .max = 112 }, |
302 | .p1 = { .min = 2, .max = 8 }, |
303 | .p2 = { .dot_limit = 225000, |
304 | .p2_slow = 14, .p2_fast = 14 }, |
305 | }; |
306 | |
307 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
308 | .dot = { .min = 25000, .max = 350000 }, |
309 | .vco = { .min = 1760000, .max = 3510000 }, |
310 | .n = { .min = 1, .max = 3 }, |
311 | .m = { .min = 79, .max = 126 }, |
312 | .m1 = { .min = 12, .max = 22 }, |
313 | .m2 = { .min = 5, .max = 9 }, |
314 | .p = { .min = 14, .max = 42 }, |
315 | .p1 = { .min = 2, .max = 6 }, |
316 | .p2 = { .dot_limit = 225000, |
317 | .p2_slow = 7, .p2_fast = 7 }, |
318 | }; |
319 | |
320 | static const intel_limit_t intel_limits_vlv = { |
321 | /* |
322 | * These are the data rate limits (measured in fast clocks) |
323 | * since those are the strictest limits we have. The fast |
324 | * clock and actual rate limits are more relaxed, so checking |
325 | * them would make no difference. |
326 | */ |
327 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, |
328 | .vco = { .min = 4000000, .max = 6000000 }, |
329 | .n = { .min = 1, .max = 7 }, |
330 | .m1 = { .min = 2, .max = 3 }, |
331 | .m2 = { .min = 11, .max = 156 }, |
332 | .p1 = { .min = 2, .max = 3 }, |
333 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
334 | }; |
335 | |
336 | static void vlv_clock(int refclk, intel_clock_t *clock) |
337 | { |
338 | clock->m = clock->m1 * clock->m2; |
339 | clock->p = clock->p1 * clock->p2; |
340 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
341 | return; |
342 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
343 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
344 | } |
345 | |
346 | /** |
347 | * Returns whether any output on the specified pipe is of the specified type |
348 | */ |
349 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
350 | { |
351 | struct drm_device *dev = crtc->dev; |
352 | struct intel_encoder *encoder; |
353 | |
354 | for_each_encoder_on_crtc(dev, crtc, encoder) |
355 | if (encoder->type == type) |
356 | return true; |
357 | |
358 | return false; |
359 | } |
360 | |
361 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
362 | int refclk) |
363 | { |
364 | struct drm_device *dev = crtc->dev; |
365 | const intel_limit_t *limit; |
366 | |
367 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
368 | if (intel_is_dual_link_lvds(dev)) { |
369 | if (refclk == 100000) |
370 | limit = &intel_limits_ironlake_dual_lvds_100m; |
371 | else |
372 | limit = &intel_limits_ironlake_dual_lvds; |
373 | } else { |
374 | if (refclk == 100000) |
375 | limit = &intel_limits_ironlake_single_lvds_100m; |
376 | else |
377 | limit = &intel_limits_ironlake_single_lvds; |
378 | } |
379 | } else |
380 | limit = &intel_limits_ironlake_dac; |
381 | |
382 | return limit; |
383 | } |
384 | |
385 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
386 | { |
387 | struct drm_device *dev = crtc->dev; |
388 | const intel_limit_t *limit; |
389 | |
390 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
391 | if (intel_is_dual_link_lvds(dev)) |
392 | limit = &intel_limits_g4x_dual_channel_lvds; |
393 | else |
394 | limit = &intel_limits_g4x_single_channel_lvds; |
395 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
396 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
397 | limit = &intel_limits_g4x_hdmi; |
398 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
399 | limit = &intel_limits_g4x_sdvo; |
400 | } else /* The option is for other outputs */ |
401 | limit = &intel_limits_i9xx_sdvo; |
402 | |
403 | return limit; |
404 | } |
405 | |
406 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
407 | { |
408 | struct drm_device *dev = crtc->dev; |
409 | const intel_limit_t *limit; |
410 | |
411 | if (HAS_PCH_SPLIT(dev)) |
412 | limit = intel_ironlake_limit(crtc, refclk); |
413 | else if (IS_G4X(dev)) { |
414 | limit = intel_g4x_limit(crtc); |
415 | } else if (IS_PINEVIEW(dev)) { |
416 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
417 | limit = &intel_limits_pineview_lvds; |
418 | else |
419 | limit = &intel_limits_pineview_sdvo; |
420 | } else if (IS_VALLEYVIEW(dev)) { |
421 | limit = &intel_limits_vlv; |
422 | } else if (!IS_GEN2(dev)) { |
423 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
424 | limit = &intel_limits_i9xx_lvds; |
425 | else |
426 | limit = &intel_limits_i9xx_sdvo; |
427 | } else { |
428 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
429 | limit = &intel_limits_i8xx_lvds; |
430 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
431 | limit = &intel_limits_i8xx_dvo; |
432 | else |
433 | limit = &intel_limits_i8xx_dac; |
434 | } |
435 | return limit; |
436 | } |
437 | |
438 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
439 | static void pineview_clock(int refclk, intel_clock_t *clock) |
440 | { |
441 | clock->m = clock->m2 + 2; |
442 | clock->p = clock->p1 * clock->p2; |
443 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
444 | return; |
445 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
446 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
447 | } |
448 | |
449 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
450 | { |
451 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
452 | } |
453 | |
454 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
455 | { |
456 | clock->m = i9xx_dpll_compute_m(clock); |
457 | clock->p = clock->p1 * clock->p2; |
458 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
459 | return; |
460 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
461 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
462 | } |
463 | |
464 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
465 | /** |
466 | * Returns whether the given set of divisors are valid for a given refclk with |
467 | * the given connectors. |
468 | */ |
469 | |
470 | static bool intel_PLL_is_valid(struct drm_device *dev, |
471 | const intel_limit_t *limit, |
472 | const intel_clock_t *clock) |
473 | { |
474 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
475 | INTELPllInvalid("n out of range\n" ); |
476 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
477 | INTELPllInvalid("p1 out of range\n" ); |
478 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
479 | INTELPllInvalid("m2 out of range\n" ); |
480 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
481 | INTELPllInvalid("m1 out of range\n" ); |
482 | |
483 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) |
484 | if (clock->m1 <= clock->m2) |
485 | INTELPllInvalid("m1 <= m2\n" ); |
486 | |
487 | if (!IS_VALLEYVIEW(dev)) { |
488 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
489 | INTELPllInvalid("p out of range\n" ); |
490 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
491 | INTELPllInvalid("m out of range\n" ); |
492 | } |
493 | |
494 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
495 | INTELPllInvalid("vco out of range\n" ); |
496 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
497 | * connector, etc., rather than just a single range. |
498 | */ |
499 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
500 | INTELPllInvalid("dot out of range\n" ); |
501 | |
502 | return true; |
503 | } |
504 | |
505 | static bool |
506 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
507 | int target, int refclk, intel_clock_t *match_clock, |
508 | intel_clock_t *best_clock) |
509 | { |
510 | struct drm_device *dev = crtc->dev; |
511 | intel_clock_t clock; |
512 | int err = target; |
513 | |
514 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
515 | /* |
516 | * For LVDS just rely on its current settings for dual-channel. |
517 | * We haven't figured out how to reliably set up different |
518 | * single/dual channel state, if we even can. |
519 | */ |
520 | if (intel_is_dual_link_lvds(dev)) |
521 | clock.p2 = limit->p2.p2_fast; |
522 | else |
523 | clock.p2 = limit->p2.p2_slow; |
524 | } else { |
525 | if (target < limit->p2.dot_limit) |
526 | clock.p2 = limit->p2.p2_slow; |
527 | else |
528 | clock.p2 = limit->p2.p2_fast; |
529 | } |
530 | |
531 | memset(best_clock, 0, sizeof(*best_clock)); |
532 | |
533 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
534 | clock.m1++) { |
535 | for (clock.m2 = limit->m2.min; |
536 | clock.m2 <= limit->m2.max; clock.m2++) { |
537 | if (clock.m2 >= clock.m1) |
538 | break; |
539 | for (clock.n = limit->n.min; |
540 | clock.n <= limit->n.max; clock.n++) { |
541 | for (clock.p1 = limit->p1.min; |
542 | clock.p1 <= limit->p1.max; clock.p1++) { |
543 | int this_err; |
544 | |
545 | i9xx_clock(refclk, &clock); |
546 | if (!intel_PLL_is_valid(dev, limit, |
547 | &clock)) |
548 | continue; |
549 | if (match_clock && |
550 | clock.p != match_clock->p) |
551 | continue; |
552 | |
553 | this_err = abs(clock.dot - target); |
554 | if (this_err < err) { |
555 | *best_clock = clock; |
556 | err = this_err; |
557 | } |
558 | } |
559 | } |
560 | } |
561 | } |
562 | |
563 | return (err != target); |
564 | } |
565 | |
566 | static bool |
567 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
568 | int target, int refclk, intel_clock_t *match_clock, |
569 | intel_clock_t *best_clock) |
570 | { |
571 | struct drm_device *dev = crtc->dev; |
572 | intel_clock_t clock; |
573 | int err = target; |
574 | |
575 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
576 | /* |
577 | * For LVDS just rely on its current settings for dual-channel. |
578 | * We haven't figured out how to reliably set up different |
579 | * single/dual channel state, if we even can. |
580 | */ |
581 | if (intel_is_dual_link_lvds(dev)) |
582 | clock.p2 = limit->p2.p2_fast; |
583 | else |
584 | clock.p2 = limit->p2.p2_slow; |
585 | } else { |
586 | if (target < limit->p2.dot_limit) |
587 | clock.p2 = limit->p2.p2_slow; |
588 | else |
589 | clock.p2 = limit->p2.p2_fast; |
590 | } |
591 | |
592 | memset(best_clock, 0, sizeof(*best_clock)); |
593 | |
594 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
595 | clock.m1++) { |
596 | for (clock.m2 = limit->m2.min; |
597 | clock.m2 <= limit->m2.max; clock.m2++) { |
598 | for (clock.n = limit->n.min; |
599 | clock.n <= limit->n.max; clock.n++) { |
600 | for (clock.p1 = limit->p1.min; |
601 | clock.p1 <= limit->p1.max; clock.p1++) { |
602 | int this_err; |
603 | |
604 | pineview_clock(refclk, &clock); |
605 | if (!intel_PLL_is_valid(dev, limit, |
606 | &clock)) |
607 | continue; |
608 | if (match_clock && |
609 | clock.p != match_clock->p) |
610 | continue; |
611 | |
612 | this_err = abs(clock.dot - target); |
613 | if (this_err < err) { |
614 | *best_clock = clock; |
615 | err = this_err; |
616 | } |
617 | } |
618 | } |
619 | } |
620 | } |
621 | |
622 | return (err != target); |
623 | } |
624 | |
625 | static bool |
626 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
627 | int target, int refclk, intel_clock_t *match_clock, |
628 | intel_clock_t *best_clock) |
629 | { |
630 | struct drm_device *dev = crtc->dev; |
631 | intel_clock_t clock; |
632 | int max_n; |
633 | bool found; |
634 | /* approximately equals target * 0.00585 */ |
635 | int err_most = (target >> 8) + (target >> 9); |
636 | found = false; |
637 | |
638 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
639 | if (intel_is_dual_link_lvds(dev)) |
640 | clock.p2 = limit->p2.p2_fast; |
641 | else |
642 | clock.p2 = limit->p2.p2_slow; |
643 | } else { |
644 | if (target < limit->p2.dot_limit) |
645 | clock.p2 = limit->p2.p2_slow; |
646 | else |
647 | clock.p2 = limit->p2.p2_fast; |
648 | } |
649 | |
650 | memset(best_clock, 0, sizeof(*best_clock)); |
651 | max_n = limit->n.max; |
652 | /* based on hardware requirement, prefer smaller n to precision */ |
653 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
654 | /* based on hardware requirement, prefere larger m1,m2 */ |
655 | for (clock.m1 = limit->m1.max; |
656 | clock.m1 >= limit->m1.min; clock.m1--) { |
657 | for (clock.m2 = limit->m2.max; |
658 | clock.m2 >= limit->m2.min; clock.m2--) { |
659 | for (clock.p1 = limit->p1.max; |
660 | clock.p1 >= limit->p1.min; clock.p1--) { |
661 | int this_err; |
662 | |
663 | i9xx_clock(refclk, &clock); |
664 | if (!intel_PLL_is_valid(dev, limit, |
665 | &clock)) |
666 | continue; |
667 | |
668 | this_err = abs(clock.dot - target); |
669 | if (this_err < err_most) { |
670 | *best_clock = clock; |
671 | err_most = this_err; |
672 | max_n = clock.n; |
673 | found = true; |
674 | } |
675 | } |
676 | } |
677 | } |
678 | } |
679 | return found; |
680 | } |
681 | |
682 | static bool |
683 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
684 | int target, int refclk, intel_clock_t *match_clock, |
685 | intel_clock_t *best_clock) |
686 | { |
687 | struct drm_device *dev = crtc->dev; |
688 | intel_clock_t clock; |
689 | unsigned int bestppm = 1000000; |
690 | /* min update 19.2 MHz */ |
691 | int max_n = min(limit->n.max, refclk / 19200); |
692 | bool found = false; |
693 | |
694 | target *= 5; /* fast clock */ |
695 | |
696 | memset(best_clock, 0, sizeof(*best_clock)); |
697 | |
698 | /* based on hardware requirement, prefer smaller n to precision */ |
699 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
700 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
701 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
702 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
703 | clock.p = clock.p1 * clock.p2; |
704 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
705 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
706 | unsigned int ppm, diff; |
707 | |
708 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
709 | refclk * clock.m1); |
710 | |
711 | vlv_clock(refclk, &clock); |
712 | |
713 | if (!intel_PLL_is_valid(dev, limit, |
714 | &clock)) |
715 | continue; |
716 | |
717 | diff = abs(clock.dot - target); |
718 | ppm = div_u64(1000000ULL * diff, target); |
719 | |
720 | if (ppm < 100 && clock.p > best_clock->p) { |
721 | bestppm = 0; |
722 | *best_clock = clock; |
723 | found = true; |
724 | } |
725 | |
726 | if (bestppm >= 10 && ppm < bestppm - 10) { |
727 | bestppm = ppm; |
728 | *best_clock = clock; |
729 | found = true; |
730 | } |
731 | } |
732 | } |
733 | } |
734 | } |
735 | |
736 | return found; |
737 | } |
738 | |
739 | bool intel_crtc_active(struct drm_crtc *crtc) |
740 | { |
741 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
742 | |
743 | /* Be paranoid as we can arrive here with only partial |
744 | * state retrieved from the hardware during setup. |
745 | * |
746 | * We can ditch the adjusted_mode.crtc_clock check as soon |
747 | * as Haswell has gained clock readout/fastboot support. |
748 | * |
749 | * We can ditch the crtc->primary->fb check as soon as we can |
750 | * properly reconstruct framebuffers. |
751 | */ |
752 | return intel_crtc->active && crtc->primary->fb && |
753 | intel_crtc->config.adjusted_mode.crtc_clock; |
754 | } |
755 | |
756 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
757 | enum i915_pipe pipe) |
758 | { |
759 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
760 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
761 | |
762 | return intel_crtc->config.cpu_transcoder; |
763 | } |
764 | |
765 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
766 | { |
767 | struct drm_i915_private *dev_priv = dev->dev_private; |
768 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
769 | |
770 | frame = I915_READ(frame_reg); |
771 | |
772 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
773 | DRM_DEBUG_KMS("vblank wait timed out\n" ); |
774 | } |
775 | |
776 | /** |
777 | * intel_wait_for_vblank - wait for vblank on a given pipe |
778 | * @dev: drm device |
779 | * @pipe: pipe to wait for |
780 | * |
781 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
782 | * mode setting code. |
783 | */ |
784 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
785 | { |
786 | struct drm_i915_private *dev_priv = dev->dev_private; |
787 | int pipestat_reg = PIPESTAT(pipe); |
788 | |
789 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
790 | g4x_wait_for_vblank(dev, pipe); |
791 | return; |
792 | } |
793 | |
794 | /* Clear existing vblank status. Note this will clear any other |
795 | * sticky status fields as well. |
796 | * |
797 | * This races with i915_driver_irq_handler() with the result |
798 | * that either function could miss a vblank event. Here it is not |
799 | * fatal, as we will either wait upon the next vblank interrupt or |
800 | * timeout. Generally speaking intel_wait_for_vblank() is only |
801 | * called during modeset at which time the GPU should be idle and |
802 | * should *not* be performing page flips and thus not waiting on |
803 | * vblanks... |
804 | * Currently, the result of us stealing a vblank from the irq |
805 | * handler is that a single frame will be skipped during swapbuffers. |
806 | */ |
807 | I915_WRITE(pipestat_reg, |
808 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
809 | |
810 | /* Wait for vblank interrupt bit to set */ |
811 | if (wait_for(I915_READ(pipestat_reg) & |
812 | PIPE_VBLANK_INTERRUPT_STATUS, |
813 | 50)) |
814 | DRM_DEBUG_KMS("vblank wait timed out\n" ); |
815 | } |
816 | |
817 | static bool pipe_dsl_stopped(struct drm_device *dev, enum i915_pipe pipe) |
818 | { |
819 | struct drm_i915_private *dev_priv = dev->dev_private; |
820 | u32 reg = PIPEDSL(pipe); |
821 | u32 line1, line2; |
822 | u32 line_mask; |
823 | |
824 | if (IS_GEN2(dev)) |
825 | line_mask = DSL_LINEMASK_GEN2; |
826 | else |
827 | line_mask = DSL_LINEMASK_GEN3; |
828 | |
829 | line1 = I915_READ(reg) & line_mask; |
830 | mdelay(5); |
831 | line2 = I915_READ(reg) & line_mask; |
832 | |
833 | return line1 == line2; |
834 | } |
835 | |
836 | /* |
837 | * intel_wait_for_pipe_off - wait for pipe to turn off |
838 | * @dev: drm device |
839 | * @pipe: pipe to wait for |
840 | * |
841 | * After disabling a pipe, we can't wait for vblank in the usual way, |
842 | * spinning on the vblank interrupt status bit, since we won't actually |
843 | * see an interrupt when the pipe is disabled. |
844 | * |
845 | * On Gen4 and above: |
846 | * wait for the pipe register state bit to turn off |
847 | * |
848 | * Otherwise: |
849 | * wait for the display line value to settle (it usually |
850 | * ends up stopping at the start of the next frame). |
851 | * |
852 | */ |
853 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
854 | { |
855 | struct drm_i915_private *dev_priv = dev->dev_private; |
856 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
857 | pipe); |
858 | |
859 | if (INTEL_INFO(dev)->gen >= 4) { |
860 | int reg = PIPECONF(cpu_transcoder); |
861 | |
862 | /* Wait for the Pipe State to go off */ |
863 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
864 | 100)) |
865 | WARN(1, "pipe_off wait timed out\n" ); |
866 | } else { |
867 | /* Wait for the display line to settle */ |
868 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
869 | WARN(1, "pipe_off wait timed out\n" ); |
870 | } |
871 | } |
872 | |
873 | /* |
874 | * ibx_digital_port_connected - is the specified port connected? |
875 | * @dev_priv: i915 private structure |
876 | * @port: the port to test |
877 | * |
878 | * Returns true if @port is connected, false otherwise. |
879 | */ |
880 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
881 | struct intel_digital_port *port) |
882 | { |
883 | u32 bit; |
884 | |
885 | if (HAS_PCH_IBX(dev_priv->dev)) { |
886 | switch(port->port) { |
887 | case PORT_B: |
888 | bit = SDE_PORTB_HOTPLUG; |
889 | break; |
890 | case PORT_C: |
891 | bit = SDE_PORTC_HOTPLUG; |
892 | break; |
893 | case PORT_D: |
894 | bit = SDE_PORTD_HOTPLUG; |
895 | break; |
896 | default: |
897 | return true; |
898 | } |
899 | } else { |
900 | switch(port->port) { |
901 | case PORT_B: |
902 | bit = SDE_PORTB_HOTPLUG_CPT; |
903 | break; |
904 | case PORT_C: |
905 | bit = SDE_PORTC_HOTPLUG_CPT; |
906 | break; |
907 | case PORT_D: |
908 | bit = SDE_PORTD_HOTPLUG_CPT; |
909 | break; |
910 | default: |
911 | return true; |
912 | } |
913 | } |
914 | |
915 | return I915_READ(SDEISR) & bit; |
916 | } |
917 | |
918 | static const char *state_string(bool enabled) |
919 | { |
920 | return enabled ? "on" : "off" ; |
921 | } |
922 | |
923 | /* Only for pre-ILK configs */ |
924 | void assert_pll(struct drm_i915_private *dev_priv, |
925 | enum i915_pipe pipe, bool state) |
926 | { |
927 | int reg; |
928 | u32 val; |
929 | bool cur_state; |
930 | |
931 | reg = DPLL(pipe); |
932 | val = I915_READ(reg); |
933 | cur_state = !!(val & DPLL_VCO_ENABLE); |
934 | WARN(cur_state != state, |
935 | "PLL state assertion failure (expected %s, current %s)\n" , |
936 | state_string(state), state_string(cur_state)); |
937 | } |
938 | |
939 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
940 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
941 | { |
942 | u32 val; |
943 | bool cur_state; |
944 | |
945 | mutex_lock(&dev_priv->dpio_lock); |
946 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
947 | mutex_unlock(&dev_priv->dpio_lock); |
948 | |
949 | cur_state = val & DSI_PLL_VCO_EN; |
950 | WARN(cur_state != state, |
951 | "DSI PLL state assertion failure (expected %s, current %s)\n" , |
952 | state_string(state), state_string(cur_state)); |
953 | } |
954 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) |
955 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) |
956 | |
957 | struct intel_shared_dpll * |
958 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
959 | { |
960 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
961 | |
962 | if (crtc->config.shared_dpll < 0) |
963 | return NULL; |
964 | |
965 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
966 | } |
967 | |
968 | /* For ILK+ */ |
969 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
970 | struct intel_shared_dpll *pll, |
971 | bool state) |
972 | { |
973 | bool cur_state; |
974 | struct intel_dpll_hw_state hw_state; |
975 | |
976 | if (HAS_PCH_LPT(dev_priv->dev)) { |
977 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n" ); |
978 | return; |
979 | } |
980 | |
981 | if (WARN (!pll, |
982 | "asserting DPLL %s with no DPLL\n" , state_string(state))) |
983 | return; |
984 | |
985 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
986 | WARN(cur_state != state, |
987 | "%s assertion failure (expected %s, current %s)\n" , |
988 | pll->name, state_string(state), state_string(cur_state)); |
989 | } |
990 | |
991 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
992 | enum i915_pipe pipe, bool state) |
993 | { |
994 | int reg; |
995 | u32 val; |
996 | bool cur_state; |
997 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
998 | pipe); |
999 | |
1000 | if (HAS_DDI(dev_priv->dev)) { |
1001 | /* DDI does not have a specific FDI_TX register */ |
1002 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
1003 | val = I915_READ(reg); |
1004 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
1005 | } else { |
1006 | reg = FDI_TX_CTL(pipe); |
1007 | val = I915_READ(reg); |
1008 | cur_state = !!(val & FDI_TX_ENABLE); |
1009 | } |
1010 | WARN(cur_state != state, |
1011 | "FDI TX state assertion failure (expected %s, current %s)\n" , |
1012 | state_string(state), state_string(cur_state)); |
1013 | } |
1014 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
1015 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
1016 | |
1017 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
1018 | enum i915_pipe pipe, bool state) |
1019 | { |
1020 | int reg; |
1021 | u32 val; |
1022 | bool cur_state; |
1023 | |
1024 | reg = FDI_RX_CTL(pipe); |
1025 | val = I915_READ(reg); |
1026 | cur_state = !!(val & FDI_RX_ENABLE); |
1027 | WARN(cur_state != state, |
1028 | "FDI RX state assertion failure (expected %s, current %s)\n" , |
1029 | state_string(state), state_string(cur_state)); |
1030 | } |
1031 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
1032 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
1033 | |
1034 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
1035 | enum i915_pipe pipe) |
1036 | { |
1037 | int reg; |
1038 | u32 val; |
1039 | |
1040 | /* ILK FDI PLL is always enabled */ |
1041 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
1042 | return; |
1043 | |
1044 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
1045 | if (HAS_DDI(dev_priv->dev)) |
1046 | return; |
1047 | |
1048 | reg = FDI_TX_CTL(pipe); |
1049 | val = I915_READ(reg); |
1050 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n" ); |
1051 | } |
1052 | |
1053 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1054 | enum i915_pipe pipe, bool state) |
1055 | { |
1056 | int reg; |
1057 | u32 val; |
1058 | bool cur_state; |
1059 | |
1060 | reg = FDI_RX_CTL(pipe); |
1061 | val = I915_READ(reg); |
1062 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1063 | WARN(cur_state != state, |
1064 | "FDI RX PLL assertion failure (expected %s, current %s)\n" , |
1065 | state_string(state), state_string(cur_state)); |
1066 | } |
1067 | |
1068 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1069 | enum i915_pipe pipe) |
1070 | { |
1071 | int pp_reg, lvds_reg; |
1072 | u32 val; |
1073 | enum i915_pipe panel_pipe = PIPE_A; |
1074 | bool locked = true; |
1075 | |
1076 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1077 | pp_reg = PCH_PP_CONTROL; |
1078 | lvds_reg = PCH_LVDS; |
1079 | } else { |
1080 | pp_reg = PP_CONTROL; |
1081 | lvds_reg = LVDS; |
1082 | } |
1083 | |
1084 | val = I915_READ(pp_reg); |
1085 | if (!(val & PANEL_POWER_ON) || |
1086 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) |
1087 | locked = false; |
1088 | |
1089 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) |
1090 | panel_pipe = PIPE_B; |
1091 | |
1092 | WARN(panel_pipe == pipe && locked, |
1093 | "panel assertion failure, pipe %c regs locked\n" , |
1094 | pipe_name(pipe)); |
1095 | } |
1096 | |
1097 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1098 | enum i915_pipe pipe, bool state) |
1099 | { |
1100 | struct drm_device *dev = dev_priv->dev; |
1101 | bool cur_state; |
1102 | |
1103 | if (IS_845G(dev) || IS_I865G(dev)) |
1104 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
1105 | else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) |
1106 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
1107 | else |
1108 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; |
1109 | |
1110 | WARN(cur_state != state, |
1111 | "cursor on pipe %c assertion failure (expected %s, current %s)\n" , |
1112 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
1113 | } |
1114 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) |
1115 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) |
1116 | |
1117 | void assert_pipe(struct drm_i915_private *dev_priv, |
1118 | enum i915_pipe pipe, bool state) |
1119 | { |
1120 | int reg; |
1121 | u32 val; |
1122 | bool cur_state; |
1123 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1124 | pipe); |
1125 | |
1126 | /* if we need the pipe A quirk it must be always on */ |
1127 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
1128 | state = true; |
1129 | |
1130 | if (!intel_display_power_enabled(dev_priv, |
1131 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
1132 | cur_state = false; |
1133 | } else { |
1134 | reg = PIPECONF(cpu_transcoder); |
1135 | val = I915_READ(reg); |
1136 | cur_state = !!(val & PIPECONF_ENABLE); |
1137 | } |
1138 | |
1139 | WARN(cur_state != state, |
1140 | "pipe %c assertion failure (expected %s, current %s)\n" , |
1141 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
1142 | } |
1143 | |
1144 | static void assert_plane(struct drm_i915_private *dev_priv, |
1145 | enum plane plane, bool state) |
1146 | { |
1147 | int reg; |
1148 | u32 val; |
1149 | bool cur_state; |
1150 | |
1151 | reg = DSPCNTR(plane); |
1152 | val = I915_READ(reg); |
1153 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1154 | WARN(cur_state != state, |
1155 | "plane %c assertion failure (expected %s, current %s)\n" , |
1156 | plane_name(plane), state_string(state), state_string(cur_state)); |
1157 | } |
1158 | |
1159 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1160 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
1161 | |
1162 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1163 | enum i915_pipe pipe) |
1164 | { |
1165 | struct drm_device *dev = dev_priv->dev; |
1166 | int reg, i; |
1167 | u32 val; |
1168 | int cur_pipe; |
1169 | |
1170 | /* Primary planes are fixed to pipes on gen4+ */ |
1171 | if (INTEL_INFO(dev)->gen >= 4) { |
1172 | reg = DSPCNTR(pipe); |
1173 | val = I915_READ(reg); |
1174 | WARN(val & DISPLAY_PLANE_ENABLE, |
1175 | "plane %c assertion failure, should be disabled but not\n" , |
1176 | plane_name(pipe)); |
1177 | return; |
1178 | } |
1179 | |
1180 | /* Need to check both planes against the pipe */ |
1181 | for_each_pipe(i) { |
1182 | reg = DSPCNTR(i); |
1183 | val = I915_READ(reg); |
1184 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
1185 | DISPPLANE_SEL_PIPE_SHIFT; |
1186 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
1187 | "plane %c assertion failure, should be off on pipe %c but is still active\n" , |
1188 | plane_name(i), pipe_name(pipe)); |
1189 | } |
1190 | } |
1191 | |
1192 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1193 | enum i915_pipe pipe) |
1194 | { |
1195 | struct drm_device *dev = dev_priv->dev; |
1196 | int reg, sprite; |
1197 | u32 val; |
1198 | |
1199 | if (IS_VALLEYVIEW(dev)) { |
1200 | for_each_sprite(pipe, sprite) { |
1201 | reg = SPCNTR(pipe, sprite); |
1202 | val = I915_READ(reg); |
1203 | WARN(val & SP_ENABLE, |
1204 | "sprite %c assertion failure, should be off on pipe %c but is still active\n" , |
1205 | sprite_name(pipe, sprite), pipe_name(pipe)); |
1206 | } |
1207 | } else if (INTEL_INFO(dev)->gen >= 7) { |
1208 | reg = SPRCTL(pipe); |
1209 | val = I915_READ(reg); |
1210 | WARN(val & SPRITE_ENABLE, |
1211 | "sprite %c assertion failure, should be off on pipe %c but is still active\n" , |
1212 | plane_name(pipe), pipe_name(pipe)); |
1213 | } else if (INTEL_INFO(dev)->gen >= 5) { |
1214 | reg = DVSCNTR(pipe); |
1215 | val = I915_READ(reg); |
1216 | WARN(val & DVS_ENABLE, |
1217 | "sprite %c assertion failure, should be off on pipe %c but is still active\n" , |
1218 | plane_name(pipe), pipe_name(pipe)); |
1219 | } |
1220 | } |
1221 | |
1222 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1223 | { |
1224 | u32 val; |
1225 | bool enabled; |
1226 | |
1227 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
1228 | |
1229 | val = I915_READ(PCH_DREF_CONTROL); |
1230 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
1231 | DREF_SUPERSPREAD_SOURCE_MASK)); |
1232 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n" ); |
1233 | } |
1234 | |
1235 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1236 | enum i915_pipe pipe) |
1237 | { |
1238 | int reg; |
1239 | u32 val; |
1240 | bool enabled; |
1241 | |
1242 | reg = PCH_TRANSCONF(pipe); |
1243 | val = I915_READ(reg); |
1244 | enabled = !!(val & TRANS_ENABLE); |
1245 | WARN(enabled, |
1246 | "transcoder assertion failed, should be off on pipe %c but is still active\n" , |
1247 | pipe_name(pipe)); |
1248 | } |
1249 | |
1250 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1251 | enum i915_pipe pipe, u32 port_sel, u32 val) |
1252 | { |
1253 | if ((val & DP_PORT_EN) == 0) |
1254 | return false; |
1255 | |
1256 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1257 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
1258 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
1259 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1260 | return false; |
1261 | } else { |
1262 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
1263 | return false; |
1264 | } |
1265 | return true; |
1266 | } |
1267 | |
1268 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1269 | enum i915_pipe pipe, u32 val) |
1270 | { |
1271 | if ((val & SDVO_ENABLE) == 0) |
1272 | return false; |
1273 | |
1274 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1275 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1276 | return false; |
1277 | } else { |
1278 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1279 | return false; |
1280 | } |
1281 | return true; |
1282 | } |
1283 | |
1284 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
1285 | enum i915_pipe pipe, u32 val) |
1286 | { |
1287 | if ((val & LVDS_PORT_EN) == 0) |
1288 | return false; |
1289 | |
1290 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1291 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1292 | return false; |
1293 | } else { |
1294 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
1295 | return false; |
1296 | } |
1297 | return true; |
1298 | } |
1299 | |
1300 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
1301 | enum i915_pipe pipe, u32 val) |
1302 | { |
1303 | if ((val & ADPA_DAC_ENABLE) == 0) |
1304 | return false; |
1305 | if (HAS_PCH_CPT(dev_priv->dev)) { |
1306 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1307 | return false; |
1308 | } else { |
1309 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
1310 | return false; |
1311 | } |
1312 | return true; |
1313 | } |
1314 | |
1315 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
1316 | enum i915_pipe pipe, int reg, u32 port_sel) |
1317 | { |
1318 | u32 val = I915_READ(reg); |
1319 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
1320 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n" , |
1321 | reg, pipe_name(pipe)); |
1322 | |
1323 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1324 | && (val & DP_PIPEB_SELECT), |
1325 | "IBX PCH dp port still using transcoder B\n" ); |
1326 | } |
1327 | |
1328 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
1329 | enum i915_pipe pipe, int reg) |
1330 | { |
1331 | u32 val = I915_READ(reg); |
1332 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
1333 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n" , |
1334 | reg, pipe_name(pipe)); |
1335 | |
1336 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
1337 | && (val & SDVO_PIPE_B_SELECT), |
1338 | "IBX PCH hdmi port still using transcoder B\n" ); |
1339 | } |
1340 | |
1341 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
1342 | enum i915_pipe pipe) |
1343 | { |
1344 | int reg; |
1345 | u32 val; |
1346 | |
1347 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1348 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
1349 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
1350 | |
1351 | reg = PCH_ADPA; |
1352 | val = I915_READ(reg); |
1353 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
1354 | "PCH VGA enabled on transcoder %c, should be disabled\n" , |
1355 | pipe_name(pipe)); |
1356 | |
1357 | reg = PCH_LVDS; |
1358 | val = I915_READ(reg); |
1359 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
1360 | "PCH LVDS enabled on transcoder %c, should be disabled\n" , |
1361 | pipe_name(pipe)); |
1362 | |
1363 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1364 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
1365 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
1366 | } |
1367 | |
1368 | static void intel_init_dpio(struct drm_device *dev) |
1369 | { |
1370 | struct drm_i915_private *dev_priv = dev->dev_private; |
1371 | |
1372 | if (!IS_VALLEYVIEW(dev)) |
1373 | return; |
1374 | |
1375 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
1376 | } |
1377 | |
1378 | static void intel_reset_dpio(struct drm_device *dev) |
1379 | { |
1380 | struct drm_i915_private *dev_priv = dev->dev_private; |
1381 | |
1382 | if (!IS_VALLEYVIEW(dev)) |
1383 | return; |
1384 | |
1385 | /* |
1386 | * Enable the CRI clock source so we can get at the display and the |
1387 | * reference clock for VGA hotplug / manual detection. |
1388 | */ |
1389 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
1390 | DPLL_REFA_CLK_ENABLE_VLV | |
1391 | DPLL_INTEGRATED_CRI_CLK_VLV); |
1392 | |
1393 | /* |
1394 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - |
1395 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. |
1396 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) |
1397 | * b. The other bits such as sfr settings / modesel may all be set |
1398 | * to 0. |
1399 | * |
1400 | * This should only be done on init and resume from S3 with both |
1401 | * PLLs disabled, or we risk losing DPIO and PLL synchronization. |
1402 | */ |
1403 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); |
1404 | } |
1405 | |
1406 | static void vlv_enable_pll(struct intel_crtc *crtc) |
1407 | { |
1408 | struct drm_device *dev = crtc->base.dev; |
1409 | struct drm_i915_private *dev_priv = dev->dev_private; |
1410 | int reg = DPLL(crtc->pipe); |
1411 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1412 | |
1413 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1414 | |
1415 | /* No really, not for ILK+ */ |
1416 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); |
1417 | |
1418 | /* PLL is protected by panel, make sure we can write it */ |
1419 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) |
1420 | assert_panel_unlocked(dev_priv, crtc->pipe); |
1421 | |
1422 | I915_WRITE(reg, dpll); |
1423 | POSTING_READ(reg); |
1424 | udelay(150); |
1425 | |
1426 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
1427 | DRM_ERROR("DPLL %d failed to lock\n" , crtc->pipe); |
1428 | |
1429 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); |
1430 | POSTING_READ(DPLL_MD(crtc->pipe)); |
1431 | |
1432 | /* We do this three times for luck */ |
1433 | I915_WRITE(reg, dpll); |
1434 | POSTING_READ(reg); |
1435 | udelay(150); /* wait for warmup */ |
1436 | I915_WRITE(reg, dpll); |
1437 | POSTING_READ(reg); |
1438 | udelay(150); /* wait for warmup */ |
1439 | I915_WRITE(reg, dpll); |
1440 | POSTING_READ(reg); |
1441 | udelay(150); /* wait for warmup */ |
1442 | } |
1443 | |
1444 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
1445 | { |
1446 | struct drm_device *dev = crtc->base.dev; |
1447 | struct drm_i915_private *dev_priv = dev->dev_private; |
1448 | int reg = DPLL(crtc->pipe); |
1449 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
1450 | |
1451 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1452 | |
1453 | /* No really, not for ILK+ */ |
1454 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
1455 | |
1456 | /* PLL is protected by panel, make sure we can write it */ |
1457 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1458 | assert_panel_unlocked(dev_priv, crtc->pipe); |
1459 | |
1460 | I915_WRITE(reg, dpll); |
1461 | |
1462 | /* Wait for the clocks to stabilize. */ |
1463 | POSTING_READ(reg); |
1464 | udelay(150); |
1465 | |
1466 | if (INTEL_INFO(dev)->gen >= 4) { |
1467 | I915_WRITE(DPLL_MD(crtc->pipe), |
1468 | crtc->config.dpll_hw_state.dpll_md); |
1469 | } else { |
1470 | /* The pixel multiplier can only be updated once the |
1471 | * DPLL is enabled and the clocks are stable. |
1472 | * |
1473 | * So write it again. |
1474 | */ |
1475 | I915_WRITE(reg, dpll); |
1476 | } |
1477 | |
1478 | /* We do this three times for luck */ |
1479 | I915_WRITE(reg, dpll); |
1480 | POSTING_READ(reg); |
1481 | udelay(150); /* wait for warmup */ |
1482 | I915_WRITE(reg, dpll); |
1483 | POSTING_READ(reg); |
1484 | udelay(150); /* wait for warmup */ |
1485 | I915_WRITE(reg, dpll); |
1486 | POSTING_READ(reg); |
1487 | udelay(150); /* wait for warmup */ |
1488 | } |
1489 | |
1490 | /** |
1491 | * i9xx_disable_pll - disable a PLL |
1492 | * @dev_priv: i915 private structure |
1493 | * @pipe: pipe PLL to disable |
1494 | * |
1495 | * Disable the PLL for @pipe, making sure the pipe is off first. |
1496 | * |
1497 | * Note! This is for pre-ILK only. |
1498 | */ |
1499 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) |
1500 | { |
1501 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1502 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1503 | return; |
1504 | |
1505 | /* Make sure the pipe isn't still relying on us */ |
1506 | assert_pipe_disabled(dev_priv, pipe); |
1507 | |
1508 | I915_WRITE(DPLL(pipe), 0); |
1509 | POSTING_READ(DPLL(pipe)); |
1510 | } |
1511 | |
1512 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) |
1513 | { |
1514 | u32 val = 0; |
1515 | |
1516 | /* Make sure the pipe isn't still relying on us */ |
1517 | assert_pipe_disabled(dev_priv, pipe); |
1518 | |
1519 | /* |
1520 | * Leave integrated clock source and reference clock enabled for pipe B. |
1521 | * The latter is needed for VGA hotplug / manual detection. |
1522 | */ |
1523 | if (pipe == PIPE_B) |
1524 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
1525 | I915_WRITE(DPLL(pipe), val); |
1526 | POSTING_READ(DPLL(pipe)); |
1527 | } |
1528 | |
1529 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1530 | struct intel_digital_port *dport) |
1531 | { |
1532 | u32 port_mask; |
1533 | |
1534 | switch (dport->port) { |
1535 | case PORT_B: |
1536 | port_mask = DPLL_PORTB_READY_MASK; |
1537 | break; |
1538 | case PORT_C: |
1539 | port_mask = DPLL_PORTC_READY_MASK; |
1540 | break; |
1541 | default: |
1542 | BUG(); |
1543 | } |
1544 | |
1545 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) |
1546 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n" , |
1547 | port_name(dport->port), I915_READ(DPLL(0))); |
1548 | } |
1549 | |
1550 | /** |
1551 | * ironlake_enable_shared_dpll - enable PCH PLL |
1552 | * @dev_priv: i915 private structure |
1553 | * @pipe: pipe PLL to enable |
1554 | * |
1555 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
1556 | * drives the transcoder clock. |
1557 | */ |
1558 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
1559 | { |
1560 | struct drm_device *dev = crtc->base.dev; |
1561 | struct drm_i915_private *dev_priv = dev->dev_private; |
1562 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1563 | |
1564 | /* PCH PLLs only available on ILK, SNB and IVB */ |
1565 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
1566 | if (WARN_ON(pll == NULL)) |
1567 | return; |
1568 | |
1569 | if (WARN_ON(pll->refcount == 0)) |
1570 | return; |
1571 | |
1572 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n" , |
1573 | pll->name, pll->active, pll->on, |
1574 | crtc->base.base.id); |
1575 | |
1576 | if (pll->active++) { |
1577 | WARN_ON(!pll->on); |
1578 | assert_shared_dpll_enabled(dev_priv, pll); |
1579 | return; |
1580 | } |
1581 | WARN_ON(pll->on); |
1582 | |
1583 | DRM_DEBUG_KMS("enabling %s\n" , pll->name); |
1584 | pll->enable(dev_priv, pll); |
1585 | pll->on = true; |
1586 | } |
1587 | |
1588 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
1589 | { |
1590 | struct drm_device *dev = crtc->base.dev; |
1591 | struct drm_i915_private *dev_priv = dev->dev_private; |
1592 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
1593 | |
1594 | /* PCH only available on ILK+ */ |
1595 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
1596 | if (WARN_ON(pll == NULL)) |
1597 | return; |
1598 | |
1599 | if (WARN_ON(pll->refcount == 0)) |
1600 | return; |
1601 | |
1602 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n" , |
1603 | pll->name, pll->active, pll->on, |
1604 | crtc->base.base.id); |
1605 | |
1606 | if (WARN_ON(pll->active == 0)) { |
1607 | assert_shared_dpll_disabled(dev_priv, pll); |
1608 | return; |
1609 | } |
1610 | |
1611 | assert_shared_dpll_enabled(dev_priv, pll); |
1612 | WARN_ON(!pll->on); |
1613 | if (--pll->active) |
1614 | return; |
1615 | |
1616 | DRM_DEBUG_KMS("disabling %s\n" , pll->name); |
1617 | pll->disable(dev_priv, pll); |
1618 | pll->on = false; |
1619 | } |
1620 | |
1621 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1622 | enum i915_pipe pipe) |
1623 | { |
1624 | struct drm_device *dev = dev_priv->dev; |
1625 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
1626 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1627 | uint32_t reg, val, pipeconf_val; |
1628 | |
1629 | /* PCH only available on ILK+ */ |
1630 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
1631 | |
1632 | /* Make sure PCH DPLL is enabled */ |
1633 | assert_shared_dpll_enabled(dev_priv, |
1634 | intel_crtc_to_shared_dpll(intel_crtc)); |
1635 | |
1636 | /* FDI must be feeding us bits for PCH ports */ |
1637 | assert_fdi_tx_enabled(dev_priv, pipe); |
1638 | assert_fdi_rx_enabled(dev_priv, pipe); |
1639 | |
1640 | if (HAS_PCH_CPT(dev)) { |
1641 | /* Workaround: Set the timing override bit before enabling the |
1642 | * pch transcoder. */ |
1643 | reg = TRANS_CHICKEN2(pipe); |
1644 | val = I915_READ(reg); |
1645 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
1646 | I915_WRITE(reg, val); |
1647 | } |
1648 | |
1649 | reg = PCH_TRANSCONF(pipe); |
1650 | val = I915_READ(reg); |
1651 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
1652 | |
1653 | if (HAS_PCH_IBX(dev_priv->dev)) { |
1654 | /* |
1655 | * make the BPC in transcoder be consistent with |
1656 | * that in pipeconf reg. |
1657 | */ |
1658 | val &= ~PIPECONF_BPC_MASK; |
1659 | val |= pipeconf_val & PIPECONF_BPC_MASK; |
1660 | } |
1661 | |
1662 | val &= ~TRANS_INTERLACE_MASK; |
1663 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
1664 | if (HAS_PCH_IBX(dev_priv->dev) && |
1665 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
1666 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1667 | else |
1668 | val |= TRANS_INTERLACED; |
1669 | else |
1670 | val |= TRANS_PROGRESSIVE; |
1671 | |
1672 | I915_WRITE(reg, val | TRANS_ENABLE); |
1673 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
1674 | DRM_ERROR("failed to enable transcoder %c\n" , pipe_name(pipe)); |
1675 | } |
1676 | |
1677 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1678 | enum transcoder cpu_transcoder) |
1679 | { |
1680 | u32 val, pipeconf_val; |
1681 | |
1682 | /* PCH only available on ILK+ */ |
1683 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
1684 | |
1685 | /* FDI must be feeding us bits for PCH ports */ |
1686 | assert_fdi_tx_enabled(dev_priv, (enum i915_pipe) cpu_transcoder); |
1687 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
1688 | |
1689 | /* Workaround: set timing override bit. */ |
1690 | val = I915_READ(_TRANSA_CHICKEN2); |
1691 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
1692 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1693 | |
1694 | val = TRANS_ENABLE; |
1695 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
1696 | |
1697 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1698 | PIPECONF_INTERLACED_ILK) |
1699 | val |= TRANS_INTERLACED; |
1700 | else |
1701 | val |= TRANS_PROGRESSIVE; |
1702 | |
1703 | I915_WRITE(LPT_TRANSCONF, val); |
1704 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) |
1705 | DRM_ERROR("Failed to enable PCH transcoder\n" ); |
1706 | } |
1707 | |
1708 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1709 | enum i915_pipe pipe) |
1710 | { |
1711 | struct drm_device *dev = dev_priv->dev; |
1712 | uint32_t reg, val; |
1713 | |
1714 | /* FDI relies on the transcoder */ |
1715 | assert_fdi_tx_disabled(dev_priv, pipe); |
1716 | assert_fdi_rx_disabled(dev_priv, pipe); |
1717 | |
1718 | /* Ports must be off as well */ |
1719 | assert_pch_ports_disabled(dev_priv, pipe); |
1720 | |
1721 | reg = PCH_TRANSCONF(pipe); |
1722 | val = I915_READ(reg); |
1723 | val &= ~TRANS_ENABLE; |
1724 | I915_WRITE(reg, val); |
1725 | /* wait for PCH transcoder off, transcoder state */ |
1726 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
1727 | DRM_ERROR("failed to disable transcoder %c\n" , pipe_name(pipe)); |
1728 | |
1729 | if (!HAS_PCH_IBX(dev)) { |
1730 | /* Workaround: Clear the timing override chicken bit again. */ |
1731 | reg = TRANS_CHICKEN2(pipe); |
1732 | val = I915_READ(reg); |
1733 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
1734 | I915_WRITE(reg, val); |
1735 | } |
1736 | } |
1737 | |
1738 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
1739 | { |
1740 | u32 val; |
1741 | |
1742 | val = I915_READ(LPT_TRANSCONF); |
1743 | val &= ~TRANS_ENABLE; |
1744 | I915_WRITE(LPT_TRANSCONF, val); |
1745 | /* wait for PCH transcoder off, transcoder state */ |
1746 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
1747 | DRM_ERROR("Failed to disable PCH transcoder\n" ); |
1748 | |
1749 | /* Workaround: clear timing override bit. */ |
1750 | val = I915_READ(_TRANSA_CHICKEN2); |
1751 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
1752 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1753 | } |
1754 | |
1755 | /** |
1756 | * intel_enable_pipe - enable a pipe, asserting requirements |
1757 | * @crtc: crtc responsible for the pipe |
1758 | * |
1759 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
1760 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
1761 | */ |
1762 | static void intel_enable_pipe(struct intel_crtc *crtc) |
1763 | { |
1764 | struct drm_device *dev = crtc->base.dev; |
1765 | struct drm_i915_private *dev_priv = dev->dev_private; |
1766 | enum i915_pipe pipe = crtc->pipe; |
1767 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1768 | pipe); |
1769 | enum i915_pipe pch_transcoder; |
1770 | int reg; |
1771 | u32 val; |
1772 | |
1773 | assert_planes_disabled(dev_priv, pipe); |
1774 | assert_cursor_disabled(dev_priv, pipe); |
1775 | assert_sprites_disabled(dev_priv, pipe); |
1776 | |
1777 | if (HAS_PCH_LPT(dev_priv->dev)) |
1778 | pch_transcoder = TRANSCODER_A; |
1779 | else |
1780 | pch_transcoder = pipe; |
1781 | |
1782 | /* |
1783 | * A pipe without a PLL won't actually be able to drive bits from |
1784 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
1785 | * need the check. |
1786 | */ |
1787 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
1788 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
1789 | assert_dsi_pll_enabled(dev_priv); |
1790 | else |
1791 | assert_pll_enabled(dev_priv, pipe); |
1792 | else { |
1793 | if (crtc->config.has_pch_encoder) { |
1794 | /* if driving the PCH, we need FDI enabled */ |
1795 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1796 | assert_fdi_tx_pll_enabled(dev_priv, |
1797 | (enum i915_pipe) cpu_transcoder); |
1798 | } |
1799 | /* FIXME: assert CPU port conditions for SNB+ */ |
1800 | } |
1801 | |
1802 | reg = PIPECONF(cpu_transcoder); |
1803 | val = I915_READ(reg); |
1804 | if (val & PIPECONF_ENABLE) { |
1805 | WARN_ON(!(pipe == PIPE_A && |
1806 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); |
1807 | return; |
1808 | } |
1809 | |
1810 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
1811 | POSTING_READ(reg); |
1812 | |
1813 | /* |
1814 | * There's no guarantee the pipe will really start running now. It |
1815 | * depends on the Gen, the output type and the relative order between |
1816 | * pipe and plane enabling. Avoid waiting on HSW+ since it's not |
1817 | * necessary. |
1818 | * TODO: audit the previous gens. |
1819 | */ |
1820 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
1821 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1822 | } |
1823 | |
1824 | /** |
1825 | * intel_disable_pipe - disable a pipe, asserting requirements |
1826 | * @dev_priv: i915 private structure |
1827 | * @pipe: pipe to disable |
1828 | * |
1829 | * Disable @pipe, making sure that various hardware specific requirements |
1830 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
1831 | * |
1832 | * @pipe should be %PIPE_A or %PIPE_B. |
1833 | * |
1834 | * Will wait until the pipe has shut down before returning. |
1835 | */ |
1836 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
1837 | enum i915_pipe pipe) |
1838 | { |
1839 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1840 | pipe); |
1841 | int reg; |
1842 | u32 val; |
1843 | |
1844 | /* |
1845 | * Make sure planes won't keep trying to pump pixels to us, |
1846 | * or we might hang the display. |
1847 | */ |
1848 | assert_planes_disabled(dev_priv, pipe); |
1849 | assert_cursor_disabled(dev_priv, pipe); |
1850 | assert_sprites_disabled(dev_priv, pipe); |
1851 | |
1852 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1853 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
1854 | return; |
1855 | |
1856 | reg = PIPECONF(cpu_transcoder); |
1857 | val = I915_READ(reg); |
1858 | if ((val & PIPECONF_ENABLE) == 0) |
1859 | return; |
1860 | |
1861 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
1862 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1863 | } |
1864 | |
1865 | /* |
1866 | * Plane regs are double buffered, going from enabled->disabled needs a |
1867 | * trigger in order to latch. The display address reg provides this. |
1868 | */ |
1869 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
1870 | enum plane plane) |
1871 | { |
1872 | struct drm_device *dev = dev_priv->dev; |
1873 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); |
1874 | |
1875 | I915_WRITE(reg, I915_READ(reg)); |
1876 | POSTING_READ(reg); |
1877 | } |
1878 | |
1879 | /** |
1880 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
1881 | * @dev_priv: i915 private structure |
1882 | * @plane: plane to enable |
1883 | * @pipe: pipe being fed |
1884 | * |
1885 | * Enable @plane on @pipe, making sure that @pipe is running first. |
1886 | */ |
1887 | static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, |
1888 | enum plane plane, enum i915_pipe pipe) |
1889 | { |
1890 | struct intel_crtc *intel_crtc = |
1891 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
1892 | int reg; |
1893 | u32 val; |
1894 | |
1895 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
1896 | assert_pipe_enabled(dev_priv, pipe); |
1897 | |
1898 | WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n" ); |
1899 | |
1900 | intel_crtc->primary_enabled = true; |
1901 | |
1902 | reg = DSPCNTR(plane); |
1903 | val = I915_READ(reg); |
1904 | if (val & DISPLAY_PLANE_ENABLE) |
1905 | return; |
1906 | |
1907 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
1908 | intel_flush_primary_plane(dev_priv, plane); |
1909 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1910 | } |
1911 | |
1912 | /** |
1913 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
1914 | * @dev_priv: i915 private structure |
1915 | * @plane: plane to disable |
1916 | * @pipe: pipe consuming the data |
1917 | * |
1918 | * Disable @plane; should be an independent operation. |
1919 | */ |
1920 | static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv, |
1921 | enum plane plane, enum i915_pipe pipe) |
1922 | { |
1923 | struct intel_crtc *intel_crtc = |
1924 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
1925 | int reg; |
1926 | u32 val; |
1927 | |
1928 | WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n" ); |
1929 | |
1930 | intel_crtc->primary_enabled = false; |
1931 | |
1932 | reg = DSPCNTR(plane); |
1933 | val = I915_READ(reg); |
1934 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1935 | return; |
1936 | |
1937 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); |
1938 | intel_flush_primary_plane(dev_priv, plane); |
1939 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1940 | } |
1941 | |
1942 | static bool need_vtd_wa(struct drm_device *dev) |
1943 | { |
1944 | #ifdef CONFIG_INTEL_IOMMU |
1945 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) |
1946 | return true; |
1947 | #endif |
1948 | return false; |
1949 | } |
1950 | |
1951 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
1952 | { |
1953 | int tile_height; |
1954 | |
1955 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; |
1956 | #ifdef __NetBSD__ /* XXX ALIGN means something else. */ |
1957 | return round_up(height, tile_height); |
1958 | #else |
1959 | return ALIGN(height, tile_height); |
1960 | #endif |
1961 | } |
1962 | |
1963 | int |
1964 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
1965 | struct drm_i915_gem_object *obj, |
1966 | struct intel_ring_buffer *pipelined) |
1967 | { |
1968 | struct drm_i915_private *dev_priv = dev->dev_private; |
1969 | u32 alignment; |
1970 | int ret; |
1971 | |
1972 | switch (obj->tiling_mode) { |
1973 | case I915_TILING_NONE: |
1974 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1975 | alignment = 128 * 1024; |
1976 | else if (INTEL_INFO(dev)->gen >= 4) |
1977 | alignment = 4 * 1024; |
1978 | else |
1979 | alignment = 64 * 1024; |
1980 | break; |
1981 | case I915_TILING_X: |
1982 | /* pin() will align the object as required by fence */ |
1983 | alignment = 0; |
1984 | break; |
1985 | case I915_TILING_Y: |
1986 | WARN(1, "Y tiled bo slipped through, driver bug!\n" ); |
1987 | return -EINVAL; |
1988 | default: |
1989 | BUG(); |
1990 | } |
1991 | |
1992 | /* Note that the w/a also requires 64 PTE of padding following the |
1993 | * bo. We currently fill all unused PTE with the shadow page and so |
1994 | * we should always have valid PTE following the scanout preventing |
1995 | * the VT-d warning. |
1996 | */ |
1997 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
1998 | alignment = 256 * 1024; |
1999 | |
2000 | dev_priv->mm.interruptible = false; |
2001 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
2002 | if (ret) |
2003 | goto err_interruptible; |
2004 | |
2005 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2006 | * fence, whereas 965+ only requires a fence if using |
2007 | * framebuffer compression. For simplicity, we always install |
2008 | * a fence as the cost is not that onerous. |
2009 | */ |
2010 | ret = i915_gem_object_get_fence(obj); |
2011 | if (ret) |
2012 | goto err_unpin; |
2013 | |
2014 | i915_gem_object_pin_fence(obj); |
2015 | |
2016 | dev_priv->mm.interruptible = true; |
2017 | return 0; |
2018 | |
2019 | err_unpin: |
2020 | i915_gem_object_unpin_from_display_plane(obj); |
2021 | err_interruptible: |
2022 | dev_priv->mm.interruptible = true; |
2023 | return ret; |
2024 | } |
2025 | |
2026 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2027 | { |
2028 | i915_gem_object_unpin_fence(obj); |
2029 | i915_gem_object_unpin_from_display_plane(obj); |
2030 | } |
2031 | |
2032 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2033 | * is assumed to be a power-of-two. */ |
2034 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2035 | unsigned int tiling_mode, |
2036 | unsigned int cpp, |
2037 | unsigned int pitch) |
2038 | { |
2039 | if (tiling_mode != I915_TILING_NONE) { |
2040 | unsigned int tile_rows, tiles; |
2041 | |
2042 | tile_rows = *y / 8; |
2043 | *y %= 8; |
2044 | |
2045 | tiles = *x / (512/cpp); |
2046 | *x %= 512/cpp; |
2047 | |
2048 | return tile_rows * pitch * 8 + tiles * 4096; |
2049 | } else { |
2050 | unsigned int offset; |
2051 | |
2052 | offset = *y * pitch + *x * cpp; |
2053 | *y = 0; |
2054 | *x = (offset & 4095) / cpp; |
2055 | return offset & -4096; |
2056 | } |
2057 | } |
2058 | |
2059 | int intel_format_to_fourcc(int format) |
2060 | { |
2061 | switch (format) { |
2062 | case DISPPLANE_8BPP: |
2063 | return DRM_FORMAT_C8; |
2064 | case DISPPLANE_BGRX555: |
2065 | return DRM_FORMAT_XRGB1555; |
2066 | case DISPPLANE_BGRX565: |
2067 | return DRM_FORMAT_RGB565; |
2068 | default: |
2069 | case DISPPLANE_BGRX888: |
2070 | return DRM_FORMAT_XRGB8888; |
2071 | case DISPPLANE_RGBX888: |
2072 | return DRM_FORMAT_XBGR8888; |
2073 | case DISPPLANE_BGRX101010: |
2074 | return DRM_FORMAT_XRGB2101010; |
2075 | case DISPPLANE_RGBX101010: |
2076 | return DRM_FORMAT_XBGR2101010; |
2077 | } |
2078 | } |
2079 | |
2080 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
2081 | struct intel_plane_config *plane_config) |
2082 | { |
2083 | struct drm_device *dev = crtc->base.dev; |
2084 | struct drm_i915_gem_object *obj = NULL; |
2085 | static const struct drm_mode_fb_cmd2 zero_mode_cmd; |
2086 | struct drm_mode_fb_cmd2 mode_cmd = zero_mode_cmd; |
2087 | u32 base = plane_config->base; |
2088 | |
2089 | if (plane_config->size == 0) |
2090 | return false; |
2091 | |
2092 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2093 | plane_config->size); |
2094 | if (!obj) |
2095 | return false; |
2096 | |
2097 | if (plane_config->tiled) { |
2098 | obj->tiling_mode = I915_TILING_X; |
2099 | obj->stride = crtc->base.primary->fb->pitches[0]; |
2100 | } |
2101 | |
2102 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2103 | mode_cmd.width = crtc->base.primary->fb->width; |
2104 | mode_cmd.height = crtc->base.primary->fb->height; |
2105 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; |
2106 | |
2107 | mutex_lock(&dev->struct_mutex); |
2108 | |
2109 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
2110 | &mode_cmd, obj)) { |
2111 | DRM_DEBUG_KMS("intel fb init failed\n" ); |
2112 | goto out_unref_obj; |
2113 | } |
2114 | |
2115 | mutex_unlock(&dev->struct_mutex); |
2116 | |
2117 | DRM_DEBUG_KMS("plane fb obj %p\n" , obj); |
2118 | return true; |
2119 | |
2120 | out_unref_obj: |
2121 | drm_gem_object_unreference(&obj->base); |
2122 | mutex_unlock(&dev->struct_mutex); |
2123 | return false; |
2124 | } |
2125 | |
2126 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, |
2127 | struct intel_plane_config *plane_config) |
2128 | { |
2129 | struct drm_device *dev = intel_crtc->base.dev; |
2130 | struct drm_crtc *c; |
2131 | struct intel_crtc *i; |
2132 | struct intel_framebuffer *fb; |
2133 | |
2134 | if (!intel_crtc->base.primary->fb) |
2135 | return; |
2136 | |
2137 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) |
2138 | return; |
2139 | |
2140 | kfree(intel_crtc->base.primary->fb); |
2141 | intel_crtc->base.primary->fb = NULL; |
2142 | |
2143 | /* |
2144 | * Failed to alloc the obj, check to see if we should share |
2145 | * an fb with another CRTC instead |
2146 | */ |
2147 | list_for_each_entry(c, &dev->mode_config.crtc_list, head) { |
2148 | i = to_intel_crtc(c); |
2149 | |
2150 | if (c == &intel_crtc->base) |
2151 | continue; |
2152 | |
2153 | if (!i->active || !c->primary->fb) |
2154 | continue; |
2155 | |
2156 | fb = to_intel_framebuffer(c->primary->fb); |
2157 | if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) { |
2158 | drm_framebuffer_reference(c->primary->fb); |
2159 | intel_crtc->base.primary->fb = c->primary->fb; |
2160 | break; |
2161 | } |
2162 | } |
2163 | } |
2164 | |
2165 | static int i9xx_update_primary_plane(struct drm_crtc *crtc, |
2166 | struct drm_framebuffer *fb, |
2167 | int x, int y) |
2168 | { |
2169 | struct drm_device *dev = crtc->dev; |
2170 | struct drm_i915_private *dev_priv = dev->dev_private; |
2171 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2172 | struct intel_framebuffer *intel_fb; |
2173 | struct drm_i915_gem_object *obj; |
2174 | int plane = intel_crtc->plane; |
2175 | unsigned long linear_offset; |
2176 | u32 dspcntr; |
2177 | u32 reg; |
2178 | |
2179 | switch (plane) { |
2180 | case 0: |
2181 | case 1: |
2182 | break; |
2183 | default: |
2184 | DRM_ERROR("Can't update plane %c in SAREA\n" , plane_name(plane)); |
2185 | return -EINVAL; |
2186 | } |
2187 | |
2188 | intel_fb = to_intel_framebuffer(fb); |
2189 | obj = intel_fb->obj; |
2190 | |
2191 | reg = DSPCNTR(plane); |
2192 | dspcntr = I915_READ(reg); |
2193 | /* Mask out pixel format bits in case we change it */ |
2194 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
2195 | switch (fb->pixel_format) { |
2196 | case DRM_FORMAT_C8: |
2197 | dspcntr |= DISPPLANE_8BPP; |
2198 | break; |
2199 | case DRM_FORMAT_XRGB1555: |
2200 | case DRM_FORMAT_ARGB1555: |
2201 | dspcntr |= DISPPLANE_BGRX555; |
2202 | break; |
2203 | case DRM_FORMAT_RGB565: |
2204 | dspcntr |= DISPPLANE_BGRX565; |
2205 | break; |
2206 | case DRM_FORMAT_XRGB8888: |
2207 | case DRM_FORMAT_ARGB8888: |
2208 | dspcntr |= DISPPLANE_BGRX888; |
2209 | break; |
2210 | case DRM_FORMAT_XBGR8888: |
2211 | case DRM_FORMAT_ABGR8888: |
2212 | dspcntr |= DISPPLANE_RGBX888; |
2213 | break; |
2214 | case DRM_FORMAT_XRGB2101010: |
2215 | case DRM_FORMAT_ARGB2101010: |
2216 | dspcntr |= DISPPLANE_BGRX101010; |
2217 | break; |
2218 | case DRM_FORMAT_XBGR2101010: |
2219 | case DRM_FORMAT_ABGR2101010: |
2220 | dspcntr |= DISPPLANE_RGBX101010; |
2221 | break; |
2222 | default: |
2223 | BUG(); |
2224 | } |
2225 | |
2226 | if (INTEL_INFO(dev)->gen >= 4) { |
2227 | if (obj->tiling_mode != I915_TILING_NONE) |
2228 | dspcntr |= DISPPLANE_TILED; |
2229 | else |
2230 | dspcntr &= ~DISPPLANE_TILED; |
2231 | } |
2232 | |
2233 | if (IS_G4X(dev)) |
2234 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2235 | |
2236 | I915_WRITE(reg, dspcntr); |
2237 | |
2238 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2239 | |
2240 | if (INTEL_INFO(dev)->gen >= 4) { |
2241 | intel_crtc->dspaddr_offset = |
2242 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2243 | fb->bits_per_pixel / 8, |
2244 | fb->pitches[0]); |
2245 | linear_offset -= intel_crtc->dspaddr_offset; |
2246 | } else { |
2247 | intel_crtc->dspaddr_offset = linear_offset; |
2248 | } |
2249 | |
2250 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n" , |
2251 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2252 | fb->pitches[0]); |
2253 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2254 | if (INTEL_INFO(dev)->gen >= 4) { |
2255 | I915_WRITE(DSPSURF(plane), |
2256 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2257 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2258 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2259 | } else |
2260 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
2261 | POSTING_READ(reg); |
2262 | |
2263 | return 0; |
2264 | } |
2265 | |
2266 | static int ironlake_update_primary_plane(struct drm_crtc *crtc, |
2267 | struct drm_framebuffer *fb, |
2268 | int x, int y) |
2269 | { |
2270 | struct drm_device *dev = crtc->dev; |
2271 | struct drm_i915_private *dev_priv = dev->dev_private; |
2272 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2273 | struct intel_framebuffer *intel_fb; |
2274 | struct drm_i915_gem_object *obj; |
2275 | int plane = intel_crtc->plane; |
2276 | unsigned long linear_offset; |
2277 | u32 dspcntr; |
2278 | u32 reg; |
2279 | |
2280 | switch (plane) { |
2281 | case 0: |
2282 | case 1: |
2283 | case 2: |
2284 | break; |
2285 | default: |
2286 | DRM_ERROR("Can't update plane %c in SAREA\n" , plane_name(plane)); |
2287 | return -EINVAL; |
2288 | } |
2289 | |
2290 | intel_fb = to_intel_framebuffer(fb); |
2291 | obj = intel_fb->obj; |
2292 | |
2293 | reg = DSPCNTR(plane); |
2294 | dspcntr = I915_READ(reg); |
2295 | /* Mask out pixel format bits in case we change it */ |
2296 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
2297 | switch (fb->pixel_format) { |
2298 | case DRM_FORMAT_C8: |
2299 | dspcntr |= DISPPLANE_8BPP; |
2300 | break; |
2301 | case DRM_FORMAT_RGB565: |
2302 | dspcntr |= DISPPLANE_BGRX565; |
2303 | break; |
2304 | case DRM_FORMAT_XRGB8888: |
2305 | case DRM_FORMAT_ARGB8888: |
2306 | dspcntr |= DISPPLANE_BGRX888; |
2307 | break; |
2308 | case DRM_FORMAT_XBGR8888: |
2309 | case DRM_FORMAT_ABGR8888: |
2310 | dspcntr |= DISPPLANE_RGBX888; |
2311 | break; |
2312 | case DRM_FORMAT_XRGB2101010: |
2313 | case DRM_FORMAT_ARGB2101010: |
2314 | dspcntr |= DISPPLANE_BGRX101010; |
2315 | break; |
2316 | case DRM_FORMAT_XBGR2101010: |
2317 | case DRM_FORMAT_ABGR2101010: |
2318 | dspcntr |= DISPPLANE_RGBX101010; |
2319 | break; |
2320 | default: |
2321 | BUG(); |
2322 | } |
2323 | |
2324 | if (obj->tiling_mode != I915_TILING_NONE) |
2325 | dspcntr |= DISPPLANE_TILED; |
2326 | else |
2327 | dspcntr &= ~DISPPLANE_TILED; |
2328 | |
2329 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
2330 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2331 | else |
2332 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2333 | |
2334 | I915_WRITE(reg, dspcntr); |
2335 | |
2336 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2337 | intel_crtc->dspaddr_offset = |
2338 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2339 | fb->bits_per_pixel / 8, |
2340 | fb->pitches[0]); |
2341 | linear_offset -= intel_crtc->dspaddr_offset; |
2342 | |
2343 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n" , |
2344 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
2345 | fb->pitches[0]); |
2346 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
2347 | I915_WRITE(DSPSURF(plane), |
2348 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2349 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
2350 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2351 | } else { |
2352 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
2353 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2354 | } |
2355 | POSTING_READ(reg); |
2356 | |
2357 | return 0; |
2358 | } |
2359 | |
2360 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2361 | static int |
2362 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2363 | int x, int y, enum mode_set_atomic state) |
2364 | { |
2365 | struct drm_device *dev = crtc->dev; |
2366 | struct drm_i915_private *dev_priv = dev->dev_private; |
2367 | |
2368 | if (dev_priv->display.disable_fbc) |
2369 | dev_priv->display.disable_fbc(dev); |
2370 | intel_increase_pllclock(crtc); |
2371 | |
2372 | return dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2373 | } |
2374 | |
2375 | void intel_display_handle_reset(struct drm_device *dev) |
2376 | { |
2377 | struct drm_i915_private *dev_priv = dev->dev_private; |
2378 | struct drm_crtc *crtc; |
2379 | |
2380 | /* |
2381 | * Flips in the rings have been nuked by the reset, |
2382 | * so complete all pending flips so that user space |
2383 | * will get its events and not get stuck. |
2384 | * |
2385 | * Also update the base address of all primary |
2386 | * planes to the the last fb to make sure we're |
2387 | * showing the correct fb after a reset. |
2388 | * |
2389 | * Need to make two loops over the crtcs so that we |
2390 | * don't try to grab a crtc mutex before the |
2391 | * pending_flip_queue really got woken up. |
2392 | */ |
2393 | |
2394 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2395 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2396 | enum plane plane = intel_crtc->plane; |
2397 | |
2398 | intel_prepare_page_flip(dev, plane); |
2399 | intel_finish_page_flip_plane(dev, plane); |
2400 | } |
2401 | |
2402 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
2403 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2404 | |
2405 | mutex_lock(&crtc->mutex); |
2406 | /* |
2407 | * FIXME: Once we have proper support for primary planes (and |
2408 | * disabling them without disabling the entire crtc) allow again |
2409 | * a NULL crtc->primary->fb. |
2410 | */ |
2411 | if (intel_crtc->active && crtc->primary->fb) |
2412 | dev_priv->display.update_primary_plane(crtc, |
2413 | crtc->primary->fb, |
2414 | crtc->x, |
2415 | crtc->y); |
2416 | mutex_unlock(&crtc->mutex); |
2417 | } |
2418 | } |
2419 | |
2420 | static int |
2421 | intel_finish_fb(struct drm_framebuffer *old_fb) |
2422 | { |
2423 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
2424 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2425 | bool was_interruptible = dev_priv->mm.interruptible; |
2426 | int ret; |
2427 | |
2428 | /* Big Hammer, we also need to ensure that any pending |
2429 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
2430 | * current scanout is retired before unpinning the old |
2431 | * framebuffer. |
2432 | * |
2433 | * This should only fail upon a hung GPU, in which case we |
2434 | * can safely continue. |
2435 | */ |
2436 | dev_priv->mm.interruptible = false; |
2437 | ret = i915_gem_object_finish_gpu(obj); |
2438 | dev_priv->mm.interruptible = was_interruptible; |
2439 | |
2440 | return ret; |
2441 | } |
2442 | |
2443 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2444 | { |
2445 | struct drm_device *dev = crtc->dev; |
2446 | struct drm_i915_private *dev_priv = dev->dev_private; |
2447 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2448 | unsigned long flags; |
2449 | bool pending; |
2450 | |
2451 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2452 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
2453 | return false; |
2454 | |
2455 | spin_lock_irqsave(&dev->event_lock, flags); |
2456 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
2457 | spin_unlock_irqrestore(&dev->event_lock, flags); |
2458 | |
2459 | return pending; |
2460 | } |
2461 | |
2462 | static int |
2463 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2464 | struct drm_framebuffer *fb) |
2465 | { |
2466 | struct drm_device *dev = crtc->dev; |
2467 | struct drm_i915_private *dev_priv = dev->dev_private; |
2468 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2469 | struct drm_framebuffer *old_fb; |
2470 | int ret; |
2471 | |
2472 | if (intel_crtc_has_pending_flip(crtc)) { |
2473 | DRM_ERROR("pipe is still busy with an old pageflip\n" ); |
2474 | return -EBUSY; |
2475 | } |
2476 | |
2477 | /* no fb bound */ |
2478 | if (!fb) { |
2479 | DRM_ERROR("No FB bound\n" ); |
2480 | return 0; |
2481 | } |
2482 | |
2483 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
2484 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n" , |
2485 | plane_name(intel_crtc->plane), |
2486 | INTEL_INFO(dev)->num_pipes); |
2487 | return -EINVAL; |
2488 | } |
2489 | |
2490 | mutex_lock(&dev->struct_mutex); |
2491 | ret = intel_pin_and_fence_fb_obj(dev, |
2492 | to_intel_framebuffer(fb)->obj, |
2493 | NULL); |
2494 | mutex_unlock(&dev->struct_mutex); |
2495 | if (ret != 0) { |
2496 | DRM_ERROR("pin & fence failed\n" ); |
2497 | return ret; |
2498 | } |
2499 | |
2500 | /* |
2501 | * Update pipe size and adjust fitter if needed: the reason for this is |
2502 | * that in compute_mode_changes we check the native mode (not the pfit |
2503 | * mode) to see if we can flip rather than do a full mode set. In the |
2504 | * fastboot case, we'll flip, but if we don't update the pipesrc and |
2505 | * pfit state, we'll end up with a big fb scanned out into the wrong |
2506 | * sized surface. |
2507 | * |
2508 | * To fix this properly, we need to hoist the checks up into |
2509 | * compute_mode_changes (or above), check the actual pfit state and |
2510 | * whether the platform allows pfit disable with pipe active, and only |
2511 | * then update the pipesrc and pfit state, even on the flip path. |
2512 | */ |
2513 | if (i915.fastboot) { |
2514 | const struct drm_display_mode *adjusted_mode = |
2515 | &intel_crtc->config.adjusted_mode; |
2516 | |
2517 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
2518 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2519 | (adjusted_mode->crtc_vdisplay - 1)); |
2520 | if (!intel_crtc->config.pch_pfit.enabled && |
2521 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2522 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
2523 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); |
2524 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); |
2525 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); |
2526 | } |
2527 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2528 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; |
2529 | } |
2530 | |
2531 | ret = dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2532 | if (ret) { |
2533 | mutex_lock(&dev->struct_mutex); |
2534 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
2535 | mutex_unlock(&dev->struct_mutex); |
2536 | DRM_ERROR("failed to update base address\n" ); |
2537 | return ret; |
2538 | } |
2539 | |
2540 | old_fb = crtc->primary->fb; |
2541 | crtc->primary->fb = fb; |
2542 | crtc->x = x; |
2543 | crtc->y = y; |
2544 | |
2545 | if (old_fb) { |
2546 | if (intel_crtc->active && old_fb != fb) |
2547 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2548 | mutex_lock(&dev->struct_mutex); |
2549 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
2550 | mutex_unlock(&dev->struct_mutex); |
2551 | } |
2552 | |
2553 | mutex_lock(&dev->struct_mutex); |
2554 | intel_update_fbc(dev); |
2555 | intel_edp_psr_update(dev); |
2556 | mutex_unlock(&dev->struct_mutex); |
2557 | |
2558 | return 0; |
2559 | } |
2560 | |
2561 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2562 | { |
2563 | struct drm_device *dev = crtc->dev; |
2564 | struct drm_i915_private *dev_priv = dev->dev_private; |
2565 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2566 | int pipe = intel_crtc->pipe; |
2567 | u32 reg, temp; |
2568 | |
2569 | /* enable normal train */ |
2570 | reg = FDI_TX_CTL(pipe); |
2571 | temp = I915_READ(reg); |
2572 | if (IS_IVYBRIDGE(dev)) { |
2573 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2574 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
2575 | } else { |
2576 | temp &= ~FDI_LINK_TRAIN_NONE; |
2577 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
2578 | } |
2579 | I915_WRITE(reg, temp); |
2580 | |
2581 | reg = FDI_RX_CTL(pipe); |
2582 | temp = I915_READ(reg); |
2583 | if (HAS_PCH_CPT(dev)) { |
2584 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2585 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
2586 | } else { |
2587 | temp &= ~FDI_LINK_TRAIN_NONE; |
2588 | temp |= FDI_LINK_TRAIN_NONE; |
2589 | } |
2590 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
2591 | |
2592 | /* wait one idle pattern time */ |
2593 | POSTING_READ(reg); |
2594 | udelay(1000); |
2595 | |
2596 | /* IVB wants error correction enabled */ |
2597 | if (IS_IVYBRIDGE(dev)) |
2598 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
2599 | FDI_FE_ERRC_ENABLE); |
2600 | } |
2601 | |
2602 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
2603 | { |
2604 | return crtc->base.enabled && crtc->active && |
2605 | crtc->config.has_pch_encoder; |
2606 | } |
2607 | |
2608 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2609 | { |
2610 | struct drm_i915_private *dev_priv = dev->dev_private; |
2611 | struct intel_crtc *pipe_B_crtc = |
2612 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
2613 | struct intel_crtc *pipe_C_crtc = |
2614 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); |
2615 | uint32_t temp; |
2616 | |
2617 | /* |
2618 | * When everything is off disable fdi C so that we could enable fdi B |
2619 | * with all lanes. Note that we don't care about enabled pipes without |
2620 | * an enabled pch encoder. |
2621 | */ |
2622 | if (!pipe_has_enabled_pch(pipe_B_crtc) && |
2623 | !pipe_has_enabled_pch(pipe_C_crtc)) { |
2624 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2625 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
2626 | |
2627 | temp = I915_READ(SOUTH_CHICKEN1); |
2628 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
2629 | DRM_DEBUG_KMS("disabling fdi C rx\n" ); |
2630 | I915_WRITE(SOUTH_CHICKEN1, temp); |
2631 | } |
2632 | } |
2633 | |
2634 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2635 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
2636 | { |
2637 | struct drm_device *dev = crtc->dev; |
2638 | struct drm_i915_private *dev_priv = dev->dev_private; |
2639 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2640 | int pipe = intel_crtc->pipe; |
2641 | int plane = intel_crtc->plane; |
2642 | u32 reg, temp, tries; |
2643 | |
2644 | /* FDI needs bits from pipe & plane first */ |
2645 | assert_pipe_enabled(dev_priv, pipe); |
2646 | assert_plane_enabled(dev_priv, plane); |
2647 | |
2648 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2649 | for train result */ |
2650 | reg = FDI_RX_IMR(pipe); |
2651 | temp = I915_READ(reg); |
2652 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2653 | temp &= ~FDI_RX_BIT_LOCK; |
2654 | I915_WRITE(reg, temp); |
2655 | I915_READ(reg); |
2656 | udelay(150); |
2657 | |
2658 | /* enable CPU FDI TX and PCH FDI RX */ |
2659 | reg = FDI_TX_CTL(pipe); |
2660 | temp = I915_READ(reg); |
2661 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2662 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2663 | temp &= ~FDI_LINK_TRAIN_NONE; |
2664 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2665 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2666 | |
2667 | reg = FDI_RX_CTL(pipe); |
2668 | temp = I915_READ(reg); |
2669 | temp &= ~FDI_LINK_TRAIN_NONE; |
2670 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2671 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2672 | |
2673 | POSTING_READ(reg); |
2674 | udelay(150); |
2675 | |
2676 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
2677 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2678 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
2679 | FDI_RX_PHASE_SYNC_POINTER_EN); |
2680 | |
2681 | reg = FDI_RX_IIR(pipe); |
2682 | for (tries = 0; tries < 5; tries++) { |
2683 | temp = I915_READ(reg); |
2684 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n" , temp); |
2685 | |
2686 | if ((temp & FDI_RX_BIT_LOCK)) { |
2687 | DRM_DEBUG_KMS("FDI train 1 done.\n" ); |
2688 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2689 | break; |
2690 | } |
2691 | } |
2692 | if (tries == 5) |
2693 | DRM_ERROR("FDI train 1 fail!\n" ); |
2694 | |
2695 | /* Train 2 */ |
2696 | reg = FDI_TX_CTL(pipe); |
2697 | temp = I915_READ(reg); |
2698 | temp &= ~FDI_LINK_TRAIN_NONE; |
2699 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2700 | I915_WRITE(reg, temp); |
2701 | |
2702 | reg = FDI_RX_CTL(pipe); |
2703 | temp = I915_READ(reg); |
2704 | temp &= ~FDI_LINK_TRAIN_NONE; |
2705 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2706 | I915_WRITE(reg, temp); |
2707 | |
2708 | POSTING_READ(reg); |
2709 | udelay(150); |
2710 | |
2711 | reg = FDI_RX_IIR(pipe); |
2712 | for (tries = 0; tries < 5; tries++) { |
2713 | temp = I915_READ(reg); |
2714 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n" , temp); |
2715 | |
2716 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2717 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2718 | DRM_DEBUG_KMS("FDI train 2 done.\n" ); |
2719 | break; |
2720 | } |
2721 | } |
2722 | if (tries == 5) |
2723 | DRM_ERROR("FDI train 2 fail!\n" ); |
2724 | |
2725 | DRM_DEBUG_KMS("FDI train done\n" ); |
2726 | |
2727 | } |
2728 | |
2729 | static const int snb_b_fdi_train_param[] = { |
2730 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2731 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
2732 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
2733 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
2734 | }; |
2735 | |
2736 | /* The FDI link training functions for SNB/Cougarpoint. */ |
2737 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
2738 | { |
2739 | struct drm_device *dev = crtc->dev; |
2740 | struct drm_i915_private *dev_priv = dev->dev_private; |
2741 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2742 | int pipe = intel_crtc->pipe; |
2743 | u32 reg, temp, i, retry; |
2744 | |
2745 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2746 | for train result */ |
2747 | reg = FDI_RX_IMR(pipe); |
2748 | temp = I915_READ(reg); |
2749 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2750 | temp &= ~FDI_RX_BIT_LOCK; |
2751 | I915_WRITE(reg, temp); |
2752 | |
2753 | POSTING_READ(reg); |
2754 | udelay(150); |
2755 | |
2756 | /* enable CPU FDI TX and PCH FDI RX */ |
2757 | reg = FDI_TX_CTL(pipe); |
2758 | temp = I915_READ(reg); |
2759 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2760 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2761 | temp &= ~FDI_LINK_TRAIN_NONE; |
2762 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2763 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2764 | /* SNB-B */ |
2765 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2766 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2767 | |
2768 | I915_WRITE(FDI_RX_MISC(pipe), |
2769 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
2770 | |
2771 | reg = FDI_RX_CTL(pipe); |
2772 | temp = I915_READ(reg); |
2773 | if (HAS_PCH_CPT(dev)) { |
2774 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2775 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2776 | } else { |
2777 | temp &= ~FDI_LINK_TRAIN_NONE; |
2778 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
2779 | } |
2780 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2781 | |
2782 | POSTING_READ(reg); |
2783 | udelay(150); |
2784 | |
2785 | for (i = 0; i < 4; i++) { |
2786 | reg = FDI_TX_CTL(pipe); |
2787 | temp = I915_READ(reg); |
2788 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2789 | temp |= snb_b_fdi_train_param[i]; |
2790 | I915_WRITE(reg, temp); |
2791 | |
2792 | POSTING_READ(reg); |
2793 | udelay(500); |
2794 | |
2795 | for (retry = 0; retry < 5; retry++) { |
2796 | reg = FDI_RX_IIR(pipe); |
2797 | temp = I915_READ(reg); |
2798 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n" , temp); |
2799 | if (temp & FDI_RX_BIT_LOCK) { |
2800 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2801 | DRM_DEBUG_KMS("FDI train 1 done.\n" ); |
2802 | break; |
2803 | } |
2804 | udelay(50); |
2805 | } |
2806 | if (retry < 5) |
2807 | break; |
2808 | } |
2809 | if (i == 4) |
2810 | DRM_ERROR("FDI train 1 fail!\n" ); |
2811 | |
2812 | /* Train 2 */ |
2813 | reg = FDI_TX_CTL(pipe); |
2814 | temp = I915_READ(reg); |
2815 | temp &= ~FDI_LINK_TRAIN_NONE; |
2816 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2817 | if (IS_GEN6(dev)) { |
2818 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2819 | /* SNB-B */ |
2820 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
2821 | } |
2822 | I915_WRITE(reg, temp); |
2823 | |
2824 | reg = FDI_RX_CTL(pipe); |
2825 | temp = I915_READ(reg); |
2826 | if (HAS_PCH_CPT(dev)) { |
2827 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2828 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2829 | } else { |
2830 | temp &= ~FDI_LINK_TRAIN_NONE; |
2831 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
2832 | } |
2833 | I915_WRITE(reg, temp); |
2834 | |
2835 | POSTING_READ(reg); |
2836 | udelay(150); |
2837 | |
2838 | for (i = 0; i < 4; i++) { |
2839 | reg = FDI_TX_CTL(pipe); |
2840 | temp = I915_READ(reg); |
2841 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2842 | temp |= snb_b_fdi_train_param[i]; |
2843 | I915_WRITE(reg, temp); |
2844 | |
2845 | POSTING_READ(reg); |
2846 | udelay(500); |
2847 | |
2848 | for (retry = 0; retry < 5; retry++) { |
2849 | reg = FDI_RX_IIR(pipe); |
2850 | temp = I915_READ(reg); |
2851 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n" , temp); |
2852 | if (temp & FDI_RX_SYMBOL_LOCK) { |
2853 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2854 | DRM_DEBUG_KMS("FDI train 2 done.\n" ); |
2855 | break; |
2856 | } |
2857 | udelay(50); |
2858 | } |
2859 | if (retry < 5) |
2860 | break; |
2861 | } |
2862 | if (i == 4) |
2863 | DRM_ERROR("FDI train 2 fail!\n" ); |
2864 | |
2865 | DRM_DEBUG_KMS("FDI train done.\n" ); |
2866 | } |
2867 | |
2868 | /* Manual link training for Ivy Bridge A0 parts */ |
2869 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
2870 | { |
2871 | struct drm_device *dev = crtc->dev; |
2872 | struct drm_i915_private *dev_priv = dev->dev_private; |
2873 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2874 | int pipe = intel_crtc->pipe; |
2875 | u32 reg, temp, i, j; |
2876 | |
2877 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2878 | for train result */ |
2879 | reg = FDI_RX_IMR(pipe); |
2880 | temp = I915_READ(reg); |
2881 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2882 | temp &= ~FDI_RX_BIT_LOCK; |
2883 | I915_WRITE(reg, temp); |
2884 | |
2885 | POSTING_READ(reg); |
2886 | udelay(150); |
2887 | |
2888 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n" , |
2889 | I915_READ(FDI_RX_IIR(pipe))); |
2890 | |
2891 | /* Try each vswing and preemphasis setting twice before moving on */ |
2892 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { |
2893 | /* disable first in case we need to retry */ |
2894 | reg = FDI_TX_CTL(pipe); |
2895 | temp = I915_READ(reg); |
2896 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
2897 | temp &= ~FDI_TX_ENABLE; |
2898 | I915_WRITE(reg, temp); |
2899 | |
2900 | reg = FDI_RX_CTL(pipe); |
2901 | temp = I915_READ(reg); |
2902 | temp &= ~FDI_LINK_TRAIN_AUTO; |
2903 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2904 | temp &= ~FDI_RX_ENABLE; |
2905 | I915_WRITE(reg, temp); |
2906 | |
2907 | /* enable CPU FDI TX and PCH FDI RX */ |
2908 | reg = FDI_TX_CTL(pipe); |
2909 | temp = I915_READ(reg); |
2910 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2911 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
2912 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
2913 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2914 | temp |= snb_b_fdi_train_param[j/2]; |
2915 | temp |= FDI_COMPOSITE_SYNC; |
2916 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2917 | |
2918 | I915_WRITE(FDI_RX_MISC(pipe), |
2919 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
2920 | |
2921 | reg = FDI_RX_CTL(pipe); |
2922 | temp = I915_READ(reg); |
2923 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2924 | temp |= FDI_COMPOSITE_SYNC; |
2925 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2926 | |
2927 | POSTING_READ(reg); |
2928 | udelay(1); /* should be 0.5us */ |
2929 | |
2930 | for (i = 0; i < 4; i++) { |
2931 | reg = FDI_RX_IIR(pipe); |
2932 | temp = I915_READ(reg); |
2933 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n" , temp); |
2934 | |
2935 | if (temp & FDI_RX_BIT_LOCK || |
2936 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
2937 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
2938 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n" , |
2939 | i); |
2940 | break; |
2941 | } |
2942 | udelay(1); /* should be 0.5us */ |
2943 | } |
2944 | if (i == 4) { |
2945 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n" , j / 2); |
2946 | continue; |
2947 | } |
2948 | |
2949 | /* Train 2 */ |
2950 | reg = FDI_TX_CTL(pipe); |
2951 | temp = I915_READ(reg); |
2952 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2953 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
2954 | I915_WRITE(reg, temp); |
2955 | |
2956 | reg = FDI_RX_CTL(pipe); |
2957 | temp = I915_READ(reg); |
2958 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
2959 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
2960 | I915_WRITE(reg, temp); |
2961 | |
2962 | POSTING_READ(reg); |
2963 | udelay(2); /* should be 1.5us */ |
2964 | |
2965 | for (i = 0; i < 4; i++) { |
2966 | reg = FDI_RX_IIR(pipe); |
2967 | temp = I915_READ(reg); |
2968 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n" , temp); |
2969 | |
2970 | if (temp & FDI_RX_SYMBOL_LOCK || |
2971 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { |
2972 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
2973 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n" , |
2974 | i); |
2975 | goto train_done; |
2976 | } |
2977 | udelay(2); /* should be 1.5us */ |
2978 | } |
2979 | if (i == 4) |
2980 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n" , j / 2); |
2981 | } |
2982 | |
2983 | train_done: |
2984 | DRM_DEBUG_KMS("FDI train done.\n" ); |
2985 | } |
2986 | |
2987 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2988 | { |
2989 | struct drm_device *dev = intel_crtc->base.dev; |
2990 | struct drm_i915_private *dev_priv = dev->dev_private; |
2991 | int pipe = intel_crtc->pipe; |
2992 | u32 reg, temp; |
2993 | |
2994 | |
2995 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
2996 | reg = FDI_RX_CTL(pipe); |
2997 | temp = I915_READ(reg); |
2998 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2999 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
3000 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
3001 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3002 | |
3003 | POSTING_READ(reg); |
3004 | udelay(200); |
3005 | |
3006 | /* Switch from Rawclk to PCDclk */ |
3007 | temp = I915_READ(reg); |
3008 | I915_WRITE(reg, temp | FDI_PCDCLK); |
3009 | |
3010 | POSTING_READ(reg); |
3011 | udelay(200); |
3012 | |
3013 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3014 | reg = FDI_TX_CTL(pipe); |
3015 | temp = I915_READ(reg); |
3016 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
3017 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
3018 | |
3019 | POSTING_READ(reg); |
3020 | udelay(100); |
3021 | } |
3022 | } |
3023 | |
3024 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3025 | { |
3026 | struct drm_device *dev = intel_crtc->base.dev; |
3027 | struct drm_i915_private *dev_priv = dev->dev_private; |
3028 | int pipe = intel_crtc->pipe; |
3029 | u32 reg, temp; |
3030 | |
3031 | /* Switch from PCDclk to Rawclk */ |
3032 | reg = FDI_RX_CTL(pipe); |
3033 | temp = I915_READ(reg); |
3034 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
3035 | |
3036 | /* Disable CPU FDI TX PLL */ |
3037 | reg = FDI_TX_CTL(pipe); |
3038 | temp = I915_READ(reg); |
3039 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
3040 | |
3041 | POSTING_READ(reg); |
3042 | udelay(100); |
3043 | |
3044 | reg = FDI_RX_CTL(pipe); |
3045 | temp = I915_READ(reg); |
3046 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
3047 | |
3048 | /* Wait for the clocks to turn off. */ |
3049 | POSTING_READ(reg); |
3050 | udelay(100); |
3051 | } |
3052 | |
3053 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3054 | { |
3055 | struct drm_device *dev = crtc->dev; |
3056 | struct drm_i915_private *dev_priv = dev->dev_private; |
3057 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3058 | int pipe = intel_crtc->pipe; |
3059 | u32 reg, temp; |
3060 | |
3061 | /* disable CPU FDI tx and PCH FDI rx */ |
3062 | reg = FDI_TX_CTL(pipe); |
3063 | temp = I915_READ(reg); |
3064 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
3065 | POSTING_READ(reg); |
3066 | |
3067 | reg = FDI_RX_CTL(pipe); |
3068 | temp = I915_READ(reg); |
3069 | temp &= ~(0x7 << 16); |
3070 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
3071 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3072 | |
3073 | POSTING_READ(reg); |
3074 | udelay(100); |
3075 | |
3076 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
3077 | if (HAS_PCH_IBX(dev)) { |
3078 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3079 | } |
3080 | |
3081 | /* still set train pattern 1 */ |
3082 | reg = FDI_TX_CTL(pipe); |
3083 | temp = I915_READ(reg); |
3084 | temp &= ~FDI_LINK_TRAIN_NONE; |
3085 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
3086 | I915_WRITE(reg, temp); |
3087 | |
3088 | reg = FDI_RX_CTL(pipe); |
3089 | temp = I915_READ(reg); |
3090 | if (HAS_PCH_CPT(dev)) { |
3091 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3092 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3093 | } else { |
3094 | temp &= ~FDI_LINK_TRAIN_NONE; |
3095 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
3096 | } |
3097 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
3098 | temp &= ~(0x07 << 16); |
3099 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
3100 | I915_WRITE(reg, temp); |
3101 | |
3102 | POSTING_READ(reg); |
3103 | udelay(100); |
3104 | } |
3105 | |
3106 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3107 | { |
3108 | struct intel_crtc *crtc; |
3109 | |
3110 | /* Note that we don't need to be called with mode_config.lock here |
3111 | * as our list of CRTC objects is static for the lifetime of the |
3112 | * device and so cannot disappear as we iterate. Similarly, we can |
3113 | * happily treat the predicates as racy, atomic checks as userspace |
3114 | * cannot claim and pin a new fb without at least acquring the |
3115 | * struct_mutex and so serialising with us. |
3116 | */ |
3117 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
3118 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3119 | continue; |
3120 | |
3121 | if (crtc->unpin_work) |
3122 | intel_wait_for_vblank(dev, crtc->pipe); |
3123 | |
3124 | return true; |
3125 | } |
3126 | |
3127 | return false; |
3128 | } |
3129 | |
3130 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
3131 | { |
3132 | struct drm_device *dev = crtc->dev; |
3133 | struct drm_i915_private *dev_priv = dev->dev_private; |
3134 | |
3135 | if (crtc->primary->fb == NULL) |
3136 | return; |
3137 | |
3138 | #ifdef __NetBSD__ |
3139 | if (cold) { |
3140 | unsigned timo = 1000; |
3141 | while (intel_crtc_has_pending_flip(crtc)) { |
3142 | if (timo-- == 0) |
3143 | /* Give up. */ |
3144 | break; |
3145 | DELAY(10); |
3146 | } |
3147 | } else { |
3148 | unsigned long flags; |
3149 | int ret; |
3150 | |
3151 | spin_lock_irqsave(&dev_priv->pending_flip_lock, flags); |
3152 | WARN_ON(DRM_SPIN_WAITERS_P(&dev_priv->pending_flip_queue, |
3153 | &dev_priv->pending_flip_lock)); |
3154 | DRM_SPIN_WAIT_NOINTR_UNTIL(ret, &dev_priv->pending_flip_queue, |
3155 | &dev_priv->pending_flip_lock, |
3156 | !intel_crtc_has_pending_flip(crtc)); |
3157 | spin_unlock_irqrestore(&dev_priv->pending_flip_lock, flags); |
3158 | } |
3159 | #else |
3160 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3161 | |
3162 | wait_event(dev_priv->pending_flip_queue, |
3163 | !intel_crtc_has_pending_flip(crtc)); |
3164 | #endif |
3165 | |
3166 | mutex_lock(&dev->struct_mutex); |
3167 | intel_finish_fb(crtc->primary->fb); |
3168 | mutex_unlock(&dev->struct_mutex); |
3169 | } |
3170 | |
3171 | /* Program iCLKIP clock to the desired frequency */ |
3172 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
3173 | { |
3174 | struct drm_device *dev = crtc->dev; |
3175 | struct drm_i915_private *dev_priv = dev->dev_private; |
3176 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
3177 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3178 | u32 temp; |
3179 | |
3180 | mutex_lock(&dev_priv->dpio_lock); |
3181 | |
3182 | /* It is necessary to ungate the pixclk gate prior to programming |
3183 | * the divisors, and gate it back when it is done. |
3184 | */ |
3185 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
3186 | |
3187 | /* Disable SSCCTL */ |
3188 | intel_sbi_write(dev_priv, SBI_SSCCTL6, |
3189 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3190 | SBI_SSCCTL_DISABLE, |
3191 | SBI_ICLK); |
3192 | |
3193 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
3194 | if (clock == 20000) { |
3195 | auxdiv = 1; |
3196 | divsel = 0x41; |
3197 | phaseinc = 0x20; |
3198 | } else { |
3199 | /* The iCLK virtual clock root frequency is in MHz, |
3200 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3201 | * divisors, it is necessary to divide one by another, so we |
3202 | * convert the virtual clock precision to KHz here for higher |
3203 | * precision. |
3204 | */ |
3205 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3206 | u32 iclk_pi_range = 64; |
3207 | u32 desired_divisor, msb_divisor_value, pi_value; |
3208 | |
3209 | desired_divisor = (iclk_virtual_root_freq / clock); |
3210 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3211 | pi_value = desired_divisor % iclk_pi_range; |
3212 | |
3213 | auxdiv = 0; |
3214 | divsel = msb_divisor_value - 2; |
3215 | phaseinc = pi_value; |
3216 | } |
3217 | |
3218 | /* This should not happen with any sane values */ |
3219 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
3220 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
3221 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
3222 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
3223 | |
3224 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n" , |
3225 | clock, |
3226 | auxdiv, |
3227 | divsel, |
3228 | phasedir, |
3229 | phaseinc); |
3230 | |
3231 | /* Program SSCDIVINTPHASE6 */ |
3232 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
3233 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3234 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
3235 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
3236 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
3237 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
3238 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
3239 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
3240 | |
3241 | /* Program SSCAUXDIV */ |
3242 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
3243 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3244 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
3245 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
3246 | |
3247 | /* Enable modulator and associated divider */ |
3248 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
3249 | temp &= ~SBI_SSCCTL_DISABLE; |
3250 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
3251 | |
3252 | /* Wait for initialization time */ |
3253 | udelay(24); |
3254 | |
3255 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
3256 | |
3257 | mutex_unlock(&dev_priv->dpio_lock); |
3258 | } |
3259 | |
3260 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3261 | enum i915_pipe pch_transcoder) |
3262 | { |
3263 | struct drm_device *dev = crtc->base.dev; |
3264 | struct drm_i915_private *dev_priv = dev->dev_private; |
3265 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
3266 | |
3267 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), |
3268 | I915_READ(HTOTAL(cpu_transcoder))); |
3269 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), |
3270 | I915_READ(HBLANK(cpu_transcoder))); |
3271 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), |
3272 | I915_READ(HSYNC(cpu_transcoder))); |
3273 | |
3274 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), |
3275 | I915_READ(VTOTAL(cpu_transcoder))); |
3276 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), |
3277 | I915_READ(VBLANK(cpu_transcoder))); |
3278 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), |
3279 | I915_READ(VSYNC(cpu_transcoder))); |
3280 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
3281 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
3282 | } |
3283 | |
3284 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3285 | { |
3286 | struct drm_i915_private *dev_priv = dev->dev_private; |
3287 | uint32_t temp; |
3288 | |
3289 | temp = I915_READ(SOUTH_CHICKEN1); |
3290 | if (temp & FDI_BC_BIFURCATION_SELECT) |
3291 | return; |
3292 | |
3293 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
3294 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
3295 | |
3296 | temp |= FDI_BC_BIFURCATION_SELECT; |
3297 | DRM_DEBUG_KMS("enabling fdi C rx\n" ); |
3298 | I915_WRITE(SOUTH_CHICKEN1, temp); |
3299 | POSTING_READ(SOUTH_CHICKEN1); |
3300 | } |
3301 | |
3302 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
3303 | { |
3304 | struct drm_device *dev = intel_crtc->base.dev; |
3305 | struct drm_i915_private *dev_priv = dev->dev_private; |
3306 | |
3307 | switch (intel_crtc->pipe) { |
3308 | case PIPE_A: |
3309 | break; |
3310 | case PIPE_B: |
3311 | if (intel_crtc->config.fdi_lanes > 2) |
3312 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
3313 | else |
3314 | cpt_enable_fdi_bc_bifurcation(dev); |
3315 | |
3316 | break; |
3317 | case PIPE_C: |
3318 | cpt_enable_fdi_bc_bifurcation(dev); |
3319 | |
3320 | break; |
3321 | default: |
3322 | BUG(); |
3323 | } |
3324 | } |
3325 | |
3326 | /* |
3327 | * Enable PCH resources required for PCH ports: |
3328 | * - PCH PLLs |
3329 | * - FDI training & RX/TX |
3330 | * - update transcoder timings |
3331 | * - DP transcoding bits |
3332 | * - transcoder |
3333 | */ |
3334 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
3335 | { |
3336 | struct drm_device *dev = crtc->dev; |
3337 | struct drm_i915_private *dev_priv = dev->dev_private; |
3338 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3339 | int pipe = intel_crtc->pipe; |
3340 | u32 reg, temp; |
3341 | |
3342 | assert_pch_transcoder_disabled(dev_priv, pipe); |
3343 | |
3344 | if (IS_IVYBRIDGE(dev)) |
3345 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
3346 | |
3347 | /* Write the TU size bits before fdi link training, so that error |
3348 | * detection works. */ |
3349 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
3350 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
3351 | |
3352 | /* For PCH output, training FDI link */ |
3353 | dev_priv->display.fdi_link_train(crtc); |
3354 | |
3355 | /* We need to program the right clock selection before writing the pixel |
3356 | * mutliplier into the DPLL. */ |
3357 | if (HAS_PCH_CPT(dev)) { |
3358 | u32 sel; |
3359 | |
3360 | temp = I915_READ(PCH_DPLL_SEL); |
3361 | temp |= TRANS_DPLL_ENABLE(pipe); |
3362 | sel = TRANS_DPLLB_SEL(pipe); |
3363 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
3364 | temp |= sel; |
3365 | else |
3366 | temp &= ~sel; |
3367 | I915_WRITE(PCH_DPLL_SEL, temp); |
3368 | } |
3369 | |
3370 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3371 | * transcoder, and we actually should do this to not upset any PCH |
3372 | * transcoder that already use the clock when we share it. |
3373 | * |
3374 | * Note that enable_shared_dpll tries to do the right thing, but |
3375 | * get_shared_dpll unconditionally resets the pll - we need that to have |
3376 | * the right LVDS enable sequence. */ |
3377 | ironlake_enable_shared_dpll(intel_crtc); |
3378 | |
3379 | /* set transcoder timing, panel must allow it */ |
3380 | assert_panel_unlocked(dev_priv, pipe); |
3381 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
3382 | |
3383 | intel_fdi_normal_train(crtc); |
3384 | |
3385 | /* For PCH DP, enable TRANS_DP_CTL */ |
3386 | if (HAS_PCH_CPT(dev) && |
3387 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3388 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
3389 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
3390 | reg = TRANS_DP_CTL(pipe); |
3391 | temp = I915_READ(reg); |
3392 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
3393 | TRANS_DP_SYNC_MASK | |
3394 | TRANS_DP_BPC_MASK); |
3395 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3396 | TRANS_DP_ENH_FRAMING); |
3397 | temp |= bpc << 9; /* same format but at 11:9 */ |
3398 | |
3399 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
3400 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
3401 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
3402 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
3403 | |
3404 | switch (intel_trans_dp_port_sel(crtc)) { |
3405 | case PCH_DP_B: |
3406 | temp |= TRANS_DP_PORT_SEL_B; |
3407 | break; |
3408 | case PCH_DP_C: |
3409 | temp |= TRANS_DP_PORT_SEL_C; |
3410 | break; |
3411 | case PCH_DP_D: |
3412 | temp |= TRANS_DP_PORT_SEL_D; |
3413 | break; |
3414 | default: |
3415 | BUG(); |
3416 | } |
3417 | |
3418 | I915_WRITE(reg, temp); |
3419 | } |
3420 | |
3421 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
3422 | } |
3423 | |
3424 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3425 | { |
3426 | struct drm_device *dev = crtc->dev; |
3427 | struct drm_i915_private *dev_priv = dev->dev_private; |
3428 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3429 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3430 | |
3431 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
3432 | |
3433 | lpt_program_iclkip(crtc); |
3434 | |
3435 | /* Set transcoder timing. */ |
3436 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
3437 | |
3438 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
3439 | } |
3440 | |
3441 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
3442 | { |
3443 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3444 | |
3445 | if (pll == NULL) |
3446 | return; |
3447 | |
3448 | if (pll->refcount == 0) { |
3449 | WARN(1, "bad %s refcount\n" , pll->name); |
3450 | return; |
3451 | } |
3452 | |
3453 | if (--pll->refcount == 0) { |
3454 | WARN_ON(pll->on); |
3455 | WARN_ON(pll->active); |
3456 | } |
3457 | |
3458 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
3459 | } |
3460 | |
3461 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
3462 | { |
3463 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3464 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
3465 | enum intel_dpll_id i; |
3466 | |
3467 | if (pll) { |
3468 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n" , |
3469 | crtc->base.base.id, pll->name); |
3470 | intel_put_shared_dpll(crtc); |
3471 | } |
3472 | |
3473 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3474 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
3475 | i = (enum intel_dpll_id) crtc->pipe; |
3476 | pll = &dev_priv->shared_dplls[i]; |
3477 | |
3478 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n" , |
3479 | crtc->base.base.id, pll->name); |
3480 | |
3481 | goto found; |
3482 | } |
3483 | |
3484 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3485 | pll = &dev_priv->shared_dplls[i]; |
3486 | |
3487 | /* Only want to check enabled timings first */ |
3488 | if (pll->refcount == 0) |
3489 | continue; |
3490 | |
3491 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3492 | sizeof(pll->hw_state)) == 0) { |
3493 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n" , |
3494 | crtc->base.base.id, |
3495 | pll->name, pll->refcount, pll->active); |
3496 | |
3497 | goto found; |
3498 | } |
3499 | } |
3500 | |
3501 | /* Ok no matching timings, maybe there's a free one? */ |
3502 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3503 | pll = &dev_priv->shared_dplls[i]; |
3504 | if (pll->refcount == 0) { |
3505 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n" , |
3506 | crtc->base.base.id, pll->name); |
3507 | goto found; |
3508 | } |
3509 | } |
3510 | |
3511 | return NULL; |
3512 | |
3513 | found: |
3514 | crtc->config.shared_dpll = i; |
3515 | DRM_DEBUG_DRIVER("using %s for pipe %c\n" , pll->name, |
3516 | pipe_name(crtc->pipe)); |
3517 | |
3518 | if (pll->active == 0) { |
3519 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3520 | sizeof(pll->hw_state)); |
3521 | |
3522 | DRM_DEBUG_DRIVER("setting up %s\n" , pll->name); |
3523 | WARN_ON(pll->on); |
3524 | assert_shared_dpll_disabled(dev_priv, pll); |
3525 | |
3526 | pll->mode_set(dev_priv, pll); |
3527 | } |
3528 | pll->refcount++; |
3529 | |
3530 | return pll; |
3531 | } |
3532 | |
3533 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
3534 | { |
3535 | struct drm_i915_private *dev_priv = dev->dev_private; |
3536 | int dslreg = PIPEDSL(pipe); |
3537 | u32 temp; |
3538 | |
3539 | temp = I915_READ(dslreg); |
3540 | udelay(500); |
3541 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
3542 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
3543 | DRM_ERROR("mode set failed: pipe %c stuck\n" , pipe_name(pipe)); |
3544 | } |
3545 | } |
3546 | |
3547 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3548 | { |
3549 | struct drm_device *dev = crtc->base.dev; |
3550 | struct drm_i915_private *dev_priv = dev->dev_private; |
3551 | int pipe = crtc->pipe; |
3552 | |
3553 | if (crtc->config.pch_pfit.enabled) { |
3554 | /* Force use of hard-coded filter coefficients |
3555 | * as some pre-programmed values are broken, |
3556 | * e.g. x201. |
3557 | */ |
3558 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
3559 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
3560 | PF_PIPE_SEL_IVB(pipe)); |
3561 | else |
3562 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3563 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); |
3564 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); |
3565 | } |
3566 | } |
3567 | |
3568 | static void intel_enable_planes(struct drm_crtc *crtc) |
3569 | { |
3570 | struct drm_device *dev = crtc->dev; |
3571 | enum i915_pipe pipe = to_intel_crtc(crtc)->pipe; |
3572 | struct drm_plane *plane; |
3573 | struct intel_plane *intel_plane; |
3574 | |
3575 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3576 | intel_plane = to_intel_plane(plane); |
3577 | if (intel_plane->pipe == pipe) |
3578 | intel_plane_restore(&intel_plane->base); |
3579 | } |
3580 | } |
3581 | |
3582 | static void intel_disable_planes(struct drm_crtc *crtc) |
3583 | { |
3584 | struct drm_device *dev = crtc->dev; |
3585 | enum i915_pipe pipe = to_intel_crtc(crtc)->pipe; |
3586 | struct drm_plane *plane; |
3587 | struct intel_plane *intel_plane; |
3588 | |
3589 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3590 | intel_plane = to_intel_plane(plane); |
3591 | if (intel_plane->pipe == pipe) |
3592 | intel_plane_disable(&intel_plane->base); |
3593 | } |
3594 | } |
3595 | |
3596 | void hsw_enable_ips(struct intel_crtc *crtc) |
3597 | { |
3598 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3599 | |
3600 | if (!crtc->config.ips_enabled) |
3601 | return; |
3602 | |
3603 | /* We can only enable IPS after we enable a plane and wait for a vblank. |
3604 | * We guarantee that the plane is enabled by calling intel_enable_ips |
3605 | * only after intel_enable_plane. And intel_enable_plane already waits |
3606 | * for a vblank, so all we need to do here is to enable the IPS bit. */ |
3607 | assert_plane_enabled(dev_priv, crtc->plane); |
3608 | if (IS_BROADWELL(crtc->base.dev)) { |
3609 | mutex_lock(&dev_priv->rps.hw_lock); |
3610 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); |
3611 | mutex_unlock(&dev_priv->rps.hw_lock); |
3612 | /* Quoting Art Runyan: "its not safe to expect any particular |
3613 | * value in IPS_CTL bit 31 after enabling IPS through the |
3614 | * mailbox." Moreover, the mailbox may return a bogus state, |
3615 | * so we need to just enable it and continue on. |
3616 | */ |
3617 | } else { |
3618 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
3619 | /* The bit only becomes 1 in the next vblank, so this wait here |
3620 | * is essentially intel_wait_for_vblank. If we don't have this |
3621 | * and don't wait for vblanks until the end of crtc_enable, then |
3622 | * the HW state readout code will complain that the expected |
3623 | * IPS_CTL value is not the one we read. */ |
3624 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) |
3625 | DRM_ERROR("Timed out waiting for IPS enable\n" ); |
3626 | } |
3627 | } |
3628 | |
3629 | void hsw_disable_ips(struct intel_crtc *crtc) |
3630 | { |
3631 | struct drm_device *dev = crtc->base.dev; |
3632 | struct drm_i915_private *dev_priv = dev->dev_private; |
3633 | |
3634 | if (!crtc->config.ips_enabled) |
3635 | return; |
3636 | |
3637 | assert_plane_enabled(dev_priv, crtc->plane); |
3638 | if (IS_BROADWELL(crtc->base.dev)) { |
3639 | mutex_lock(&dev_priv->rps.hw_lock); |
3640 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); |
3641 | mutex_unlock(&dev_priv->rps.hw_lock); |
3642 | } else { |
3643 | I915_WRITE(IPS_CTL, 0); |
3644 | POSTING_READ(IPS_CTL); |
3645 | } |
3646 | |
3647 | /* We need to wait for a vblank before we can disable the plane. */ |
3648 | intel_wait_for_vblank(dev, crtc->pipe); |
3649 | } |
3650 | |
3651 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
3652 | static void intel_crtc_load_lut(struct drm_crtc *crtc) |
3653 | { |
3654 | struct drm_device *dev = crtc->dev; |
3655 | struct drm_i915_private *dev_priv = dev->dev_private; |
3656 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3657 | enum i915_pipe pipe = intel_crtc->pipe; |
3658 | int palreg = PALETTE(pipe); |
3659 | int i; |
3660 | bool reenable_ips = false; |
3661 | |
3662 | /* The clocks have to be on to load the palette. */ |
3663 | if (!crtc->enabled || !intel_crtc->active) |
3664 | return; |
3665 | |
3666 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { |
3667 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
3668 | assert_dsi_pll_enabled(dev_priv); |
3669 | else |
3670 | assert_pll_enabled(dev_priv, pipe); |
3671 | } |
3672 | |
3673 | /* use legacy palette for Ironlake */ |
3674 | if (HAS_PCH_SPLIT(dev)) |
3675 | palreg = LGC_PALETTE(pipe); |
3676 | |
3677 | /* Workaround : Do not read or write the pipe palette/gamma data while |
3678 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
3679 | */ |
3680 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
3681 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3682 | GAMMA_MODE_MODE_SPLIT)) { |
3683 | hsw_disable_ips(intel_crtc); |
3684 | reenable_ips = true; |
3685 | } |
3686 | |
3687 | for (i = 0; i < 256; i++) { |
3688 | I915_WRITE(palreg + 4 * i, |
3689 | (intel_crtc->lut_r[i] << 16) | |
3690 | (intel_crtc->lut_g[i] << 8) | |
3691 | intel_crtc->lut_b[i]); |
3692 | } |
3693 | |
3694 | if (reenable_ips) |
3695 | hsw_enable_ips(intel_crtc); |
3696 | } |
3697 | |
3698 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3699 | { |
3700 | struct drm_device *dev = crtc->dev; |
3701 | struct drm_i915_private *dev_priv = dev->dev_private; |
3702 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3703 | struct intel_encoder *encoder; |
3704 | int pipe = intel_crtc->pipe; |
3705 | int plane = intel_crtc->plane; |
3706 | |
3707 | WARN_ON(!crtc->enabled); |
3708 | |
3709 | if (intel_crtc->active) |
3710 | return; |
3711 | |
3712 | intel_crtc->active = true; |
3713 | |
3714 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3715 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
3716 | |
3717 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3718 | if (encoder->pre_enable) |
3719 | encoder->pre_enable(encoder); |
3720 | |
3721 | if (intel_crtc->config.has_pch_encoder) { |
3722 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3723 | * cpu pipes, hence this is separate from all the other fdi/pch |
3724 | * enabling. */ |
3725 | ironlake_fdi_pll_enable(intel_crtc); |
3726 | } else { |
3727 | assert_fdi_tx_disabled(dev_priv, pipe); |
3728 | assert_fdi_rx_disabled(dev_priv, pipe); |
3729 | } |
3730 | |
3731 | ironlake_pfit_enable(intel_crtc); |
3732 | |
3733 | /* |
3734 | * On ILK+ LUT must be loaded before the pipe is running but with |
3735 | * clocks enabled |
3736 | */ |
3737 | intel_crtc_load_lut(crtc); |
3738 | |
3739 | intel_update_watermarks(crtc); |
3740 | intel_enable_pipe(intel_crtc); |
3741 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
3742 | intel_enable_planes(crtc); |
3743 | intel_crtc_update_cursor(crtc, true); |
3744 | |
3745 | if (intel_crtc->config.has_pch_encoder) |
3746 | ironlake_pch_enable(crtc); |
3747 | |
3748 | mutex_lock(&dev->struct_mutex); |
3749 | intel_update_fbc(dev); |
3750 | mutex_unlock(&dev->struct_mutex); |
3751 | |
3752 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3753 | encoder->enable(encoder); |
3754 | |
3755 | if (HAS_PCH_CPT(dev)) |
3756 | cpt_verify_modeset(dev, intel_crtc->pipe); |
3757 | |
3758 | /* |
3759 | * There seems to be a race in PCH platform hw (at least on some |
3760 | * outputs) where an enabled pipe still completes any pageflip right |
3761 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
3762 | * as the first vblank happend, everything works as expected. Hence just |
3763 | * wait for one vblank before returning to avoid strange things |
3764 | * happening. |
3765 | */ |
3766 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3767 | } |
3768 | |
3769 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3770 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
3771 | { |
3772 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
3773 | } |
3774 | |
3775 | static void haswell_crtc_enable_planes(struct drm_crtc *crtc) |
3776 | { |
3777 | struct drm_device *dev = crtc->dev; |
3778 | struct drm_i915_private *dev_priv = dev->dev_private; |
3779 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3780 | int pipe = intel_crtc->pipe; |
3781 | int plane = intel_crtc->plane; |
3782 | |
3783 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
3784 | intel_enable_planes(crtc); |
3785 | intel_crtc_update_cursor(crtc, true); |
3786 | |
3787 | hsw_enable_ips(intel_crtc); |
3788 | |
3789 | mutex_lock(&dev->struct_mutex); |
3790 | intel_update_fbc(dev); |
3791 | mutex_unlock(&dev->struct_mutex); |
3792 | } |
3793 | |
3794 | static void haswell_crtc_disable_planes(struct drm_crtc *crtc) |
3795 | { |
3796 | struct drm_device *dev = crtc->dev; |
3797 | struct drm_i915_private *dev_priv = dev->dev_private; |
3798 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3799 | int pipe = intel_crtc->pipe; |
3800 | int plane = intel_crtc->plane; |
3801 | |
3802 | intel_crtc_wait_for_pending_flips(crtc); |
3803 | drm_vblank_off(dev, pipe); |
3804 | |
3805 | /* FBC must be disabled before disabling the plane on HSW. */ |
3806 | if (dev_priv->fbc.plane == plane) |
3807 | intel_disable_fbc(dev); |
3808 | |
3809 | hsw_disable_ips(intel_crtc); |
3810 | |
3811 | intel_crtc_update_cursor(crtc, false); |
3812 | intel_disable_planes(crtc); |
3813 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); |
3814 | } |
3815 | |
3816 | /* |
3817 | * This implements the workaround described in the "notes" section of the mode |
3818 | * set sequence documentation. When going from no pipes or single pipe to |
3819 | * multiple pipes, and planes are enabled after the pipe, we need to wait at |
3820 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. |
3821 | */ |
3822 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) |
3823 | { |
3824 | struct drm_device *dev = crtc->base.dev; |
3825 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; |
3826 | |
3827 | /* We want to get the other_active_crtc only if there's only 1 other |
3828 | * active crtc. */ |
3829 | list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { |
3830 | if (!crtc_it->active || crtc_it == crtc) |
3831 | continue; |
3832 | |
3833 | if (other_active_crtc) |
3834 | return; |
3835 | |
3836 | other_active_crtc = crtc_it; |
3837 | } |
3838 | if (!other_active_crtc) |
3839 | return; |
3840 | |
3841 | intel_wait_for_vblank(dev, other_active_crtc->pipe); |
3842 | intel_wait_for_vblank(dev, other_active_crtc->pipe); |
3843 | } |
3844 | |
3845 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3846 | { |
3847 | struct drm_device *dev = crtc->dev; |
3848 | struct drm_i915_private *dev_priv = dev->dev_private; |
3849 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3850 | struct intel_encoder *encoder; |
3851 | int pipe = intel_crtc->pipe; |
3852 | |
3853 | WARN_ON(!crtc->enabled); |
3854 | |
3855 | if (intel_crtc->active) |
3856 | return; |
3857 | |
3858 | intel_crtc->active = true; |
3859 | |
3860 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
3861 | if (intel_crtc->config.has_pch_encoder) |
3862 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
3863 | |
3864 | if (intel_crtc->config.has_pch_encoder) |
3865 | dev_priv->display.fdi_link_train(crtc); |
3866 | |
3867 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3868 | if (encoder->pre_enable) |
3869 | encoder->pre_enable(encoder); |
3870 | |
3871 | intel_ddi_enable_pipe_clock(intel_crtc); |
3872 | |
3873 | ironlake_pfit_enable(intel_crtc); |
3874 | |
3875 | /* |
3876 | * On ILK+ LUT must be loaded before the pipe is running but with |
3877 | * clocks enabled |
3878 | */ |
3879 | intel_crtc_load_lut(crtc); |
3880 | |
3881 | intel_ddi_set_pipe_settings(crtc); |
3882 | intel_ddi_enable_transcoder_func(crtc); |
3883 | |
3884 | intel_update_watermarks(crtc); |
3885 | intel_enable_pipe(intel_crtc); |
3886 | |
3887 | if (intel_crtc->config.has_pch_encoder) |
3888 | lpt_pch_enable(crtc); |
3889 | |
3890 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
3891 | encoder->enable(encoder); |
3892 | intel_opregion_notify_encoder(encoder, true); |
3893 | } |
3894 | |
3895 | /* If we change the relative order between pipe/planes enabling, we need |
3896 | * to change the workaround. */ |
3897 | haswell_mode_set_planes_workaround(intel_crtc); |
3898 | haswell_crtc_enable_planes(crtc); |
3899 | } |
3900 | |
3901 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3902 | { |
3903 | struct drm_device *dev = crtc->base.dev; |
3904 | struct drm_i915_private *dev_priv = dev->dev_private; |
3905 | int pipe = crtc->pipe; |
3906 | |
3907 | /* To avoid upsetting the power well on haswell only disable the pfit if |
3908 | * it's in use. The hw state code will make sure we get this right. */ |
3909 | if (crtc->config.pch_pfit.enabled) { |
3910 | I915_WRITE(PF_CTL(pipe), 0); |
3911 | I915_WRITE(PF_WIN_POS(pipe), 0); |
3912 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
3913 | } |
3914 | } |
3915 | |
3916 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3917 | { |
3918 | struct drm_device *dev = crtc->dev; |
3919 | struct drm_i915_private *dev_priv = dev->dev_private; |
3920 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3921 | struct intel_encoder *encoder; |
3922 | int pipe = intel_crtc->pipe; |
3923 | int plane = intel_crtc->plane; |
3924 | u32 reg, temp; |
3925 | |
3926 | |
3927 | if (!intel_crtc->active) |
3928 | return; |
3929 | |
3930 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3931 | encoder->disable(encoder); |
3932 | |
3933 | intel_crtc_wait_for_pending_flips(crtc); |
3934 | drm_vblank_off(dev, pipe); |
3935 | |
3936 | if (dev_priv->fbc.plane == plane) |
3937 | intel_disable_fbc(dev); |
3938 | |
3939 | intel_crtc_update_cursor(crtc, false); |
3940 | intel_disable_planes(crtc); |
3941 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); |
3942 | |
3943 | if (intel_crtc->config.has_pch_encoder) |
3944 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
3945 | |
3946 | intel_disable_pipe(dev_priv, pipe); |
3947 | |
3948 | ironlake_pfit_disable(intel_crtc); |
3949 | |
3950 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3951 | if (encoder->post_disable) |
3952 | encoder->post_disable(encoder); |
3953 | |
3954 | if (intel_crtc->config.has_pch_encoder) { |
3955 | ironlake_fdi_disable(crtc); |
3956 | |
3957 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3958 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
3959 | |
3960 | if (HAS_PCH_CPT(dev)) { |
3961 | /* disable TRANS_DP_CTL */ |
3962 | reg = TRANS_DP_CTL(pipe); |
3963 | temp = I915_READ(reg); |
3964 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
3965 | TRANS_DP_PORT_SEL_MASK); |
3966 | temp |= TRANS_DP_PORT_SEL_NONE; |
3967 | I915_WRITE(reg, temp); |
3968 | |
3969 | /* disable DPLL_SEL */ |
3970 | temp = I915_READ(PCH_DPLL_SEL); |
3971 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
3972 | I915_WRITE(PCH_DPLL_SEL, temp); |
3973 | } |
3974 | |
3975 | /* disable PCH DPLL */ |
3976 | intel_disable_shared_dpll(intel_crtc); |
3977 | |
3978 | ironlake_fdi_pll_disable(intel_crtc); |
3979 | } |
3980 | |
3981 | intel_crtc->active = false; |
3982 | intel_update_watermarks(crtc); |
3983 | |
3984 | mutex_lock(&dev->struct_mutex); |
3985 | intel_update_fbc(dev); |
3986 | mutex_unlock(&dev->struct_mutex); |
3987 | } |
3988 | |
3989 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
3990 | { |
3991 | struct drm_device *dev = crtc->dev; |
3992 | struct drm_i915_private *dev_priv = dev->dev_private; |
3993 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3994 | struct intel_encoder *encoder; |
3995 | int pipe = intel_crtc->pipe; |
3996 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
3997 | |
3998 | if (!intel_crtc->active) |
3999 | return; |
4000 | |
4001 | haswell_crtc_disable_planes(crtc); |
4002 | |
4003 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4004 | intel_opregion_notify_encoder(encoder, false); |
4005 | encoder->disable(encoder); |
4006 | } |
4007 | |
4008 | if (intel_crtc->config.has_pch_encoder) |
4009 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
4010 | intel_disable_pipe(dev_priv, pipe); |
4011 | |
4012 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4013 | |
4014 | ironlake_pfit_disable(intel_crtc); |
4015 | |
4016 | intel_ddi_disable_pipe_clock(intel_crtc); |
4017 | |
4018 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4019 | if (encoder->post_disable) |
4020 | encoder->post_disable(encoder); |
4021 | |
4022 | if (intel_crtc->config.has_pch_encoder) { |
4023 | lpt_disable_pch_transcoder(dev_priv); |
4024 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
4025 | intel_ddi_fdi_disable(crtc); |
4026 | } |
4027 | |
4028 | intel_crtc->active = false; |
4029 | intel_update_watermarks(crtc); |
4030 | |
4031 | mutex_lock(&dev->struct_mutex); |
4032 | intel_update_fbc(dev); |
4033 | mutex_unlock(&dev->struct_mutex); |
4034 | } |
4035 | |
4036 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4037 | { |
4038 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4039 | intel_put_shared_dpll(intel_crtc); |
4040 | } |
4041 | |
4042 | static void haswell_crtc_off(struct drm_crtc *crtc) |
4043 | { |
4044 | intel_ddi_put_crtc_pll(crtc); |
4045 | } |
4046 | |
4047 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
4048 | { |
4049 | if (!enable && intel_crtc->overlay) { |
4050 | struct drm_device *dev = intel_crtc->base.dev; |
4051 | struct drm_i915_private *dev_priv = dev->dev_private; |
4052 | |
4053 | mutex_lock(&dev->struct_mutex); |
4054 | dev_priv->mm.interruptible = false; |
4055 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
4056 | dev_priv->mm.interruptible = true; |
4057 | mutex_unlock(&dev->struct_mutex); |
4058 | } |
4059 | |
4060 | /* Let userspace switch the overlay on again. In most cases userspace |
4061 | * has to recompute where to put it anyway. |
4062 | */ |
4063 | } |
4064 | |
4065 | /** |
4066 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware |
4067 | * cursor plane briefly if not already running after enabling the display |
4068 | * plane. |
4069 | * This workaround avoids occasional blank screens when self refresh is |
4070 | * enabled. |
4071 | */ |
4072 | static void |
4073 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum i915_pipe pipe) |
4074 | { |
4075 | u32 cntl = I915_READ(CURCNTR(pipe)); |
4076 | |
4077 | if ((cntl & CURSOR_MODE) == 0) { |
4078 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); |
4079 | |
4080 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); |
4081 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); |
4082 | intel_wait_for_vblank(dev_priv->dev, pipe); |
4083 | I915_WRITE(CURCNTR(pipe), cntl); |
4084 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); |
4085 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); |
4086 | } |
4087 | } |
4088 | |
4089 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4090 | { |
4091 | struct drm_device *dev = crtc->base.dev; |
4092 | struct drm_i915_private *dev_priv = dev->dev_private; |
4093 | struct intel_crtc_config *pipe_config = &crtc->config; |
4094 | |
4095 | if (!crtc->config.gmch_pfit.control) |
4096 | return; |
4097 | |
4098 | /* |
4099 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4100 | * according to register description and PRM. |
4101 | */ |
4102 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4103 | assert_pipe_disabled(dev_priv, crtc->pipe); |
4104 | |
4105 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4106 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); |
4107 | |
4108 | /* Border color in case we don't scale up to the full screen. Black by |
4109 | * default, change to something else for debugging. */ |
4110 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
4111 | } |
4112 | |
4113 | #define for_each_power_domain(domain, mask) \ |
4114 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
4115 | if ((1 << (domain)) & (mask)) |
4116 | |
4117 | enum intel_display_power_domain |
4118 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) |
4119 | { |
4120 | struct drm_device *dev = intel_encoder->base.dev; |
4121 | struct intel_digital_port *intel_dig_port; |
4122 | |
4123 | switch (intel_encoder->type) { |
4124 | case INTEL_OUTPUT_UNKNOWN: |
4125 | /* Only DDI platforms should ever use this output type */ |
4126 | WARN_ON_ONCE(!HAS_DDI(dev)); |
4127 | case INTEL_OUTPUT_DISPLAYPORT: |
4128 | case INTEL_OUTPUT_HDMI: |
4129 | case INTEL_OUTPUT_EDP: |
4130 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
4131 | switch (intel_dig_port->port) { |
4132 | case PORT_A: |
4133 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; |
4134 | case PORT_B: |
4135 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; |
4136 | case PORT_C: |
4137 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; |
4138 | case PORT_D: |
4139 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; |
4140 | default: |
4141 | WARN_ON_ONCE(1); |
4142 | return POWER_DOMAIN_PORT_OTHER; |
4143 | } |
4144 | case INTEL_OUTPUT_ANALOG: |
4145 | return POWER_DOMAIN_PORT_CRT; |
4146 | case INTEL_OUTPUT_DSI: |
4147 | return POWER_DOMAIN_PORT_DSI; |
4148 | default: |
4149 | return POWER_DOMAIN_PORT_OTHER; |
4150 | } |
4151 | } |
4152 | |
4153 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
4154 | { |
4155 | struct drm_device *dev = crtc->dev; |
4156 | struct intel_encoder *intel_encoder; |
4157 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4158 | enum i915_pipe pipe = intel_crtc->pipe; |
4159 | bool pfit_enabled = intel_crtc->config.pch_pfit.enabled; |
4160 | unsigned long mask; |
4161 | enum transcoder transcoder; |
4162 | |
4163 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); |
4164 | |
4165 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
4166 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
4167 | if (pfit_enabled) |
4168 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
4169 | |
4170 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4171 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
4172 | |
4173 | return mask; |
4174 | } |
4175 | |
4176 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, |
4177 | bool enable) |
4178 | { |
4179 | if (dev_priv->power_domains.init_power_on == enable) |
4180 | return; |
4181 | |
4182 | if (enable) |
4183 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
4184 | else |
4185 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
4186 | |
4187 | dev_priv->power_domains.init_power_on = enable; |
4188 | } |
4189 | |
4190 | static void modeset_update_crtc_power_domains(struct drm_device *dev) |
4191 | { |
4192 | struct drm_i915_private *dev_priv = dev->dev_private; |
4193 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
4194 | struct intel_crtc *crtc; |
4195 | |
4196 | /* |
4197 | * First get all needed power domains, then put all unneeded, to avoid |
4198 | * any unnecessary toggling of the power wells. |
4199 | */ |
4200 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
4201 | enum intel_display_power_domain domain; |
4202 | |
4203 | if (!crtc->base.enabled) |
4204 | continue; |
4205 | |
4206 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
4207 | |
4208 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) |
4209 | intel_display_power_get(dev_priv, domain); |
4210 | } |
4211 | |
4212 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
4213 | enum intel_display_power_domain domain; |
4214 | |
4215 | for_each_power_domain(domain, crtc->enabled_power_domains) |
4216 | intel_display_power_put(dev_priv, domain); |
4217 | |
4218 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; |
4219 | } |
4220 | |
4221 | intel_display_set_init_power(dev_priv, false); |
4222 | } |
4223 | |
4224 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
4225 | { |
4226 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
4227 | |
4228 | /* Obtain SKU information */ |
4229 | mutex_lock(&dev_priv->dpio_lock); |
4230 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
4231 | CCK_FUSE_HPLL_FREQ_MASK; |
4232 | mutex_unlock(&dev_priv->dpio_lock); |
4233 | |
4234 | return vco_freq[hpll_freq]; |
4235 | } |
4236 | |
4237 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
4238 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) |
4239 | { |
4240 | struct drm_i915_private *dev_priv = dev->dev_private; |
4241 | u32 val, cmd; |
4242 | |
4243 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ |
4244 | cmd = 2; |
4245 | else if (cdclk == 266) |
4246 | cmd = 1; |
4247 | else |
4248 | cmd = 0; |
4249 | |
4250 | mutex_lock(&dev_priv->rps.hw_lock); |
4251 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
4252 | val &= ~DSPFREQGUAR_MASK; |
4253 | val |= (cmd << DSPFREQGUAR_SHIFT); |
4254 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
4255 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
4256 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), |
4257 | 50)) { |
4258 | DRM_ERROR("timed out waiting for CDclk change\n" ); |
4259 | } |
4260 | mutex_unlock(&dev_priv->rps.hw_lock); |
4261 | |
4262 | if (cdclk == 400) { |
4263 | u32 divider, vco; |
4264 | |
4265 | vco = valleyview_get_vco(dev_priv); |
4266 | divider = ((vco << 1) / cdclk) - 1; |
4267 | |
4268 | mutex_lock(&dev_priv->dpio_lock); |
4269 | /* adjust cdclk divider */ |
4270 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
4271 | val &= ~0xf; |
4272 | val |= divider; |
4273 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); |
4274 | mutex_unlock(&dev_priv->dpio_lock); |
4275 | } |
4276 | |
4277 | mutex_lock(&dev_priv->dpio_lock); |
4278 | /* adjust self-refresh exit latency value */ |
4279 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); |
4280 | val &= ~0x7f; |
4281 | |
4282 | /* |
4283 | * For high bandwidth configs, we set a higher latency in the bunit |
4284 | * so that the core display fetch happens in time to avoid underruns. |
4285 | */ |
4286 | if (cdclk == 400) |
4287 | val |= 4500 / 250; /* 4.5 usec */ |
4288 | else |
4289 | val |= 3000 / 250; /* 3.0 usec */ |
4290 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); |
4291 | mutex_unlock(&dev_priv->dpio_lock); |
4292 | |
4293 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ |
4294 | intel_i2c_reset(dev); |
4295 | } |
4296 | |
4297 | static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) |
4298 | { |
4299 | int cur_cdclk, vco; |
4300 | int divider; |
4301 | |
4302 | vco = valleyview_get_vco(dev_priv); |
4303 | |
4304 | mutex_lock(&dev_priv->dpio_lock); |
4305 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
4306 | mutex_unlock(&dev_priv->dpio_lock); |
4307 | |
4308 | divider &= 0xf; |
4309 | |
4310 | cur_cdclk = (vco << 1) / (divider + 1); |
4311 | |
4312 | return cur_cdclk; |
4313 | } |
4314 | |
4315 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
4316 | int max_pixclk) |
4317 | { |
4318 | /* |
4319 | * Really only a few cases to deal with, as only 4 CDclks are supported: |
4320 | * 200MHz |
4321 | * 267MHz |
4322 | * 320MHz |
4323 | * 400MHz |
4324 | * So we check to see whether we're above 90% of the lower bin and |
4325 | * adjust if needed. |
4326 | */ |
4327 | if (max_pixclk > 288000) { |
4328 | return 400; |
4329 | } else if (max_pixclk > 240000) { |
4330 | return 320; |
4331 | } else |
4332 | return 266; |
4333 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ |
4334 | } |
4335 | |
4336 | /* compute the max pixel clock for new configuration */ |
4337 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) |
4338 | { |
4339 | struct drm_device *dev = dev_priv->dev; |
4340 | struct intel_crtc *intel_crtc; |
4341 | int max_pixclk = 0; |
4342 | |
4343 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
4344 | base.head) { |
4345 | if (intel_crtc->new_enabled) |
4346 | max_pixclk = max(max_pixclk, |
4347 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
4348 | } |
4349 | |
4350 | return max_pixclk; |
4351 | } |
4352 | |
4353 | static void valleyview_modeset_global_pipes(struct drm_device *dev, |
4354 | unsigned *prepare_pipes) |
4355 | { |
4356 | struct drm_i915_private *dev_priv = dev->dev_private; |
4357 | struct intel_crtc *intel_crtc; |
4358 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
4359 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4360 | |
4361 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk) |
4362 | return; |
4363 | |
4364 | /* disable/enable all currently active pipes while we change cdclk */ |
4365 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
4366 | base.head) |
4367 | if (intel_crtc->base.enabled) |
4368 | *prepare_pipes |= (1 << intel_crtc->pipe); |
4369 | } |
4370 | |
4371 | static void valleyview_modeset_global_resources(struct drm_device *dev) |
4372 | { |
4373 | struct drm_i915_private *dev_priv = dev->dev_private; |
4374 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
4375 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4376 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4377 | |
4378 | if (req_cdclk != cur_cdclk) |
4379 | valleyview_set_cdclk(dev, req_cdclk); |
4380 | modeset_update_crtc_power_domains(dev); |
4381 | } |
4382 | |
4383 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4384 | { |
4385 | struct drm_device *dev = crtc->dev; |
4386 | struct drm_i915_private *dev_priv = dev->dev_private; |
4387 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4388 | struct intel_encoder *encoder; |
4389 | int pipe = intel_crtc->pipe; |
4390 | int plane = intel_crtc->plane; |
4391 | bool is_dsi; |
4392 | |
4393 | WARN_ON(!crtc->enabled); |
4394 | |
4395 | if (intel_crtc->active) |
4396 | return; |
4397 | |
4398 | intel_crtc->active = true; |
4399 | |
4400 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4401 | if (encoder->pre_pll_enable) |
4402 | encoder->pre_pll_enable(encoder); |
4403 | |
4404 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4405 | |
4406 | if (!is_dsi) |
4407 | vlv_enable_pll(intel_crtc); |
4408 | |
4409 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4410 | if (encoder->pre_enable) |
4411 | encoder->pre_enable(encoder); |
4412 | |
4413 | i9xx_pfit_enable(intel_crtc); |
4414 | |
4415 | intel_crtc_load_lut(crtc); |
4416 | |
4417 | intel_update_watermarks(crtc); |
4418 | intel_enable_pipe(intel_crtc); |
4419 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4420 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
4421 | intel_enable_planes(crtc); |
4422 | intel_crtc_update_cursor(crtc, true); |
4423 | |
4424 | intel_update_fbc(dev); |
4425 | |
4426 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4427 | encoder->enable(encoder); |
4428 | } |
4429 | |
4430 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
4431 | { |
4432 | struct drm_device *dev = crtc->dev; |
4433 | struct drm_i915_private *dev_priv = dev->dev_private; |
4434 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4435 | struct intel_encoder *encoder; |
4436 | int pipe = intel_crtc->pipe; |
4437 | int plane = intel_crtc->plane; |
4438 | |
4439 | WARN_ON(!crtc->enabled); |
4440 | |
4441 | if (intel_crtc->active) |
4442 | return; |
4443 | |
4444 | intel_crtc->active = true; |
4445 | |
4446 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4447 | if (encoder->pre_enable) |
4448 | encoder->pre_enable(encoder); |
4449 | |
4450 | i9xx_enable_pll(intel_crtc); |
4451 | |
4452 | i9xx_pfit_enable(intel_crtc); |
4453 | |
4454 | intel_crtc_load_lut(crtc); |
4455 | |
4456 | intel_update_watermarks(crtc); |
4457 | intel_enable_pipe(intel_crtc); |
4458 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4459 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
4460 | intel_enable_planes(crtc); |
4461 | /* The fixup needs to happen before cursor is enabled */ |
4462 | if (IS_G4X(dev)) |
4463 | g4x_fixup_plane(dev_priv, pipe); |
4464 | intel_crtc_update_cursor(crtc, true); |
4465 | |
4466 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
4467 | intel_crtc_dpms_overlay(intel_crtc, true); |
4468 | |
4469 | intel_update_fbc(dev); |
4470 | |
4471 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4472 | encoder->enable(encoder); |
4473 | } |
4474 | |
4475 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4476 | { |
4477 | struct drm_device *dev = crtc->base.dev; |
4478 | struct drm_i915_private *dev_priv = dev->dev_private; |
4479 | |
4480 | if (!crtc->config.gmch_pfit.control) |
4481 | return; |
4482 | |
4483 | assert_pipe_disabled(dev_priv, crtc->pipe); |
4484 | |
4485 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n" , |
4486 | I915_READ(PFIT_CONTROL)); |
4487 | I915_WRITE(PFIT_CONTROL, 0); |
4488 | } |
4489 | |
4490 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4491 | { |
4492 | struct drm_device *dev = crtc->dev; |
4493 | struct drm_i915_private *dev_priv = dev->dev_private; |
4494 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4495 | struct intel_encoder *encoder; |
4496 | int pipe = intel_crtc->pipe; |
4497 | int plane = intel_crtc->plane; |
4498 | |
4499 | if (!intel_crtc->active) |
4500 | return; |
4501 | |
4502 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4503 | encoder->disable(encoder); |
4504 | |
4505 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
4506 | intel_crtc_wait_for_pending_flips(crtc); |
4507 | drm_vblank_off(dev, pipe); |
4508 | |
4509 | if (dev_priv->fbc.plane == plane) |
4510 | intel_disable_fbc(dev); |
4511 | |
4512 | intel_crtc_dpms_overlay(intel_crtc, false); |
4513 | intel_crtc_update_cursor(crtc, false); |
4514 | intel_disable_planes(crtc); |
4515 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); |
4516 | |
4517 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
4518 | intel_disable_pipe(dev_priv, pipe); |
4519 | |
4520 | i9xx_pfit_disable(intel_crtc); |
4521 | |
4522 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4523 | if (encoder->post_disable) |
4524 | encoder->post_disable(encoder); |
4525 | |
4526 | if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
4527 | vlv_disable_pll(dev_priv, pipe); |
4528 | else if (!IS_VALLEYVIEW(dev)) |
4529 | i9xx_disable_pll(dev_priv, pipe); |
4530 | |
4531 | intel_crtc->active = false; |
4532 | intel_update_watermarks(crtc); |
4533 | |
4534 | intel_update_fbc(dev); |
4535 | } |
4536 | |
4537 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4538 | { |
4539 | } |
4540 | |
4541 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4542 | bool enabled) |
4543 | { |
4544 | struct drm_device *dev = crtc->dev; |
4545 | struct drm_i915_master_private *master_priv; |
4546 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4547 | int pipe = intel_crtc->pipe; |
4548 | |
4549 | if (!dev->primary->master) |
4550 | return; |
4551 | |
4552 | master_priv = dev->primary->master->driver_priv; |
4553 | if (!master_priv->sarea_priv) |
4554 | return; |
4555 | |
4556 | switch (pipe) { |
4557 | case 0: |
4558 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
4559 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
4560 | break; |
4561 | case 1: |
4562 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
4563 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
4564 | break; |
4565 | default: |
4566 | DRM_ERROR("Can't update pipe %c in SAREA\n" , pipe_name(pipe)); |
4567 | break; |
4568 | } |
4569 | } |
4570 | |
4571 | /** |
4572 | * Sets the power management mode of the pipe and plane. |
4573 | */ |
4574 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
4575 | { |
4576 | struct drm_device *dev = crtc->dev; |
4577 | struct drm_i915_private *dev_priv = dev->dev_private; |
4578 | struct intel_encoder *intel_encoder; |
4579 | bool enable = false; |
4580 | |
4581 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4582 | enable |= intel_encoder->connectors_active; |
4583 | |
4584 | if (enable) |
4585 | dev_priv->display.crtc_enable(crtc); |
4586 | else |
4587 | dev_priv->display.crtc_disable(crtc); |
4588 | |
4589 | intel_crtc_update_sarea(crtc, enable); |
4590 | } |
4591 | |
4592 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4593 | { |
4594 | struct drm_device *dev = crtc->dev; |
4595 | struct drm_connector *connector; |
4596 | struct drm_i915_private *dev_priv = dev->dev_private; |
4597 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4598 | |
4599 | /* crtc should still be enabled when we disable it. */ |
4600 | WARN_ON(!crtc->enabled); |
4601 | |
4602 | dev_priv->display.crtc_disable(crtc); |
4603 | intel_crtc->eld_vld = false; |
4604 | intel_crtc_update_sarea(crtc, false); |
4605 | dev_priv->display.off(crtc); |
4606 | |
4607 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
4608 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
4609 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
4610 | |
4611 | if (crtc->primary->fb) { |
4612 | mutex_lock(&dev->struct_mutex); |
4613 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj); |
4614 | mutex_unlock(&dev->struct_mutex); |
4615 | crtc->primary->fb = NULL; |
4616 | } |
4617 | |
4618 | /* Update computed state. */ |
4619 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
4620 | if (!connector->encoder || !connector->encoder->crtc) |
4621 | continue; |
4622 | |
4623 | if (connector->encoder->crtc != crtc) |
4624 | continue; |
4625 | |
4626 | connector->dpms = DRM_MODE_DPMS_OFF; |
4627 | to_intel_encoder(connector->encoder)->connectors_active = false; |
4628 | } |
4629 | } |
4630 | |
4631 | void intel_encoder_destroy(struct drm_encoder *encoder) |
4632 | { |
4633 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
4634 | |
4635 | drm_encoder_cleanup(encoder); |
4636 | kfree(intel_encoder); |
4637 | } |
4638 | |
4639 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
4640 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4641 | * state of the entire output pipe. */ |
4642 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
4643 | { |
4644 | if (mode == DRM_MODE_DPMS_ON) { |
4645 | encoder->connectors_active = true; |
4646 | |
4647 | intel_crtc_update_dpms(encoder->base.crtc); |
4648 | } else { |
4649 | encoder->connectors_active = false; |
4650 | |
4651 | intel_crtc_update_dpms(encoder->base.crtc); |
4652 | } |
4653 | } |
4654 | |
4655 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4656 | * internal consistency). */ |
4657 | static void intel_connector_check_state(struct intel_connector *connector) |
4658 | { |
4659 | if (connector->get_hw_state(connector)) { |
4660 | struct intel_encoder *encoder = connector->encoder; |
4661 | struct drm_crtc *crtc; |
4662 | bool encoder_enabled; |
4663 | enum i915_pipe pipe; |
4664 | |
4665 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n" , |
4666 | connector->base.base.id, |
4667 | drm_get_connector_name(&connector->base)); |
4668 | |
4669 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
4670 | "wrong connector dpms state\n" ); |
4671 | WARN(connector->base.encoder != &encoder->base, |
4672 | "active connector not linked to encoder\n" ); |
4673 | WARN(!encoder->connectors_active, |
4674 | "encoder->connectors_active not set\n" ); |
4675 | |
4676 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); |
4677 | WARN(!encoder_enabled, "encoder not enabled\n" ); |
4678 | if (WARN_ON(!encoder->base.crtc)) |
4679 | return; |
4680 | |
4681 | crtc = encoder->base.crtc; |
4682 | |
4683 | WARN(!crtc->enabled, "crtc not enabled\n" ); |
4684 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n" ); |
4685 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
4686 | "encoder active on the wrong pipe\n" ); |
4687 | } |
4688 | } |
4689 | |
4690 | /* Even simpler default implementation, if there's really no special case to |
4691 | * consider. */ |
4692 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
4693 | { |
4694 | /* All the simple cases only support two dpms states. */ |
4695 | if (mode != DRM_MODE_DPMS_ON) |
4696 | mode = DRM_MODE_DPMS_OFF; |
4697 | |
4698 | if (mode == connector->dpms) |
4699 | return; |
4700 | |
4701 | connector->dpms = mode; |
4702 | |
4703 | /* Only need to change hw state when actually enabled */ |
4704 | if (connector->encoder) |
4705 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); |
4706 | |
4707 | intel_modeset_check_state(connector->dev); |
4708 | } |
4709 | |
4710 | /* Simple connector->get_hw_state implementation for encoders that support only |
4711 | * one connector and no cloning and hence the encoder state determines the state |
4712 | * of the connector. */ |
4713 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
4714 | { |
4715 | enum i915_pipe pipe = 0; |
4716 | struct intel_encoder *encoder = connector->encoder; |
4717 | |
4718 | return encoder->get_hw_state(encoder, &pipe); |
4719 | } |
4720 | |
4721 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum i915_pipe pipe, |
4722 | struct intel_crtc_config *pipe_config) |
4723 | { |
4724 | struct drm_i915_private *dev_priv = dev->dev_private; |
4725 | struct intel_crtc *pipe_B_crtc = |
4726 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
4727 | |
4728 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n" , |
4729 | pipe_name(pipe), pipe_config->fdi_lanes); |
4730 | if (pipe_config->fdi_lanes > 4) { |
4731 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n" , |
4732 | pipe_name(pipe), pipe_config->fdi_lanes); |
4733 | return false; |
4734 | } |
4735 | |
4736 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
4737 | if (pipe_config->fdi_lanes > 2) { |
4738 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n" , |
4739 | pipe_config->fdi_lanes); |
4740 | return false; |
4741 | } else { |
4742 | return true; |
4743 | } |
4744 | } |
4745 | |
4746 | if (INTEL_INFO(dev)->num_pipes == 2) |
4747 | return true; |
4748 | |
4749 | /* Ivybridge 3 pipe is really complicated */ |
4750 | switch (pipe) { |
4751 | case PIPE_A: |
4752 | return true; |
4753 | case PIPE_B: |
4754 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && |
4755 | pipe_config->fdi_lanes > 2) { |
4756 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n" , |
4757 | pipe_name(pipe), pipe_config->fdi_lanes); |
4758 | return false; |
4759 | } |
4760 | return true; |
4761 | case PIPE_C: |
4762 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
4763 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4764 | if (pipe_config->fdi_lanes > 2) { |
4765 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n" , |
4766 | pipe_name(pipe), pipe_config->fdi_lanes); |
4767 | return false; |
4768 | } |
4769 | } else { |
4770 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n" ); |
4771 | return false; |
4772 | } |
4773 | return true; |
4774 | default: |
4775 | BUG(); |
4776 | } |
4777 | } |
4778 | |
4779 | #define RETRY 1 |
4780 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, |
4781 | struct intel_crtc_config *pipe_config) |
4782 | { |
4783 | struct drm_device *dev = intel_crtc->base.dev; |
4784 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4785 | int lane, link_bw, fdi_dotclock; |
4786 | bool setup_ok, needs_recompute = false; |
4787 | |
4788 | retry: |
4789 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4790 | * each output octet as 10 bits. The actual frequency |
4791 | * is stored as a divider into a 100MHz clock, and the |
4792 | * mode pixel clock is stored in units of 1KHz. |
4793 | * Hence the bw of each lane in terms of the mode signal |
4794 | * is: |
4795 | */ |
4796 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
4797 | |
4798 | fdi_dotclock = adjusted_mode->crtc_clock; |
4799 | |
4800 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
4801 | pipe_config->pipe_bpp); |
4802 | |
4803 | pipe_config->fdi_lanes = lane; |
4804 | |
4805 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
4806 | link_bw, &pipe_config->fdi_m_n); |
4807 | |
4808 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4809 | intel_crtc->pipe, pipe_config); |
4810 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { |
4811 | pipe_config->pipe_bpp -= 2*3; |
4812 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n" , |
4813 | pipe_config->pipe_bpp); |
4814 | needs_recompute = true; |
4815 | pipe_config->bw_constrained = true; |
4816 | |
4817 | goto retry; |
4818 | } |
4819 | |
4820 | if (needs_recompute) |
4821 | return RETRY; |
4822 | |
4823 | return setup_ok ? 0 : -EINVAL; |
4824 | } |
4825 | |
4826 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4827 | struct intel_crtc_config *pipe_config) |
4828 | { |
4829 | pipe_config->ips_enabled = i915.enable_ips && |
4830 | hsw_crtc_supports_ips(crtc) && |
4831 | pipe_config->pipe_bpp <= 24; |
4832 | } |
4833 | |
4834 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
4835 | struct intel_crtc_config *pipe_config) |
4836 | { |
4837 | struct drm_device *dev = crtc->base.dev; |
4838 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4839 | |
4840 | /* FIXME should check pixel clock limits on all platforms */ |
4841 | if (INTEL_INFO(dev)->gen < 4) { |
4842 | struct drm_i915_private *dev_priv = dev->dev_private; |
4843 | int clock_limit = |
4844 | dev_priv->display.get_display_clock_speed(dev); |
4845 | |
4846 | /* |
4847 | * Enable pixel doubling when the dot clock |
4848 | * is > 90% of the (display) core speed. |
4849 | * |
4850 | * GDG double wide on either pipe, |
4851 | * otherwise pipe A only. |
4852 | */ |
4853 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
4854 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
4855 | clock_limit *= 2; |
4856 | pipe_config->double_wide = true; |
4857 | } |
4858 | |
4859 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
4860 | return -EINVAL; |
4861 | } |
4862 | |
4863 | /* |
4864 | * Pipe horizontal size must be even in: |
4865 | * - DVO ganged mode |
4866 | * - LVDS dual channel mode |
4867 | * - Double wide pipe |
4868 | */ |
4869 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
4870 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
4871 | pipe_config->pipe_src_w &= ~1; |
4872 | |
4873 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4874 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
4875 | */ |
4876 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
4877 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) |
4878 | return -EINVAL; |
4879 | |
4880 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
4881 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
4882 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
4883 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4884 | * for lvds. */ |
4885 | pipe_config->pipe_bpp = 8*3; |
4886 | } |
4887 | |
4888 | if (HAS_IPS(dev)) |
4889 | hsw_compute_ips_config(crtc, pipe_config); |
4890 | |
4891 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old |
4892 | * clock survives for now. */ |
4893 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
4894 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
4895 | |
4896 | if (pipe_config->has_pch_encoder) |
4897 | return ironlake_fdi_compute_config(crtc, pipe_config); |
4898 | |
4899 | return 0; |
4900 | } |
4901 | |
4902 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4903 | { |
4904 | return 400000; /* FIXME */ |
4905 | } |
4906 | |
4907 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4908 | { |
4909 | return 400000; |
4910 | } |
4911 | |
4912 | static int i915_get_display_clock_speed(struct drm_device *dev) |
4913 | { |
4914 | return 333000; |
4915 | } |
4916 | |
4917 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4918 | { |
4919 | return 200000; |
4920 | } |
4921 | |
4922 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4923 | { |
4924 | u16 gcfgc = 0; |
4925 | |
4926 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4927 | |
4928 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
4929 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
4930 | return 267000; |
4931 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
4932 | return 333000; |
4933 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
4934 | return 444000; |
4935 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
4936 | return 200000; |
4937 | default: |
4938 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n" , gcfgc); |
4939 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
4940 | return 133000; |
4941 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
4942 | return 167000; |
4943 | } |
4944 | } |
4945 | |
4946 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4947 | { |
4948 | u16 gcfgc = 0; |
4949 | |
4950 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4951 | |
4952 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
4953 | return 133000; |
4954 | else { |
4955 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
4956 | case GC_DISPLAY_CLOCK_333_MHZ: |
4957 | return 333000; |
4958 | default: |
4959 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
4960 | return 190000; |
4961 | } |
4962 | } |
4963 | } |
4964 | |
4965 | static int i865_get_display_clock_speed(struct drm_device *dev) |
4966 | { |
4967 | return 266000; |
4968 | } |
4969 | |
4970 | static int i855_get_display_clock_speed(struct drm_device *dev) |
4971 | { |
4972 | u16 hpllcc = 0; |
4973 | /* Assume that the hardware is in the high speed state. This |
4974 | * should be the default. |
4975 | */ |
4976 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
4977 | case GC_CLOCK_133_200: |
4978 | case GC_CLOCK_100_200: |
4979 | return 200000; |
4980 | case GC_CLOCK_166_250: |
4981 | return 250000; |
4982 | case GC_CLOCK_100_133: |
4983 | return 133000; |
4984 | } |
4985 | |
4986 | /* Shouldn't happen */ |
4987 | return 0; |
4988 | } |
4989 | |
4990 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4991 | { |
4992 | return 133000; |
4993 | } |
4994 | |
4995 | static void |
4996 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
4997 | { |
4998 | while (*num > DATA_LINK_M_N_MASK || |
4999 | *den > DATA_LINK_M_N_MASK) { |
5000 | *num >>= 1; |
5001 | *den >>= 1; |
5002 | } |
5003 | } |
5004 | |
5005 | static void compute_m_n(unsigned int m, unsigned int n, |
5006 | uint32_t *ret_m, uint32_t *ret_n) |
5007 | { |
5008 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
5009 | *ret_m = div_u64((uint64_t) m * *ret_n, n); |
5010 | intel_reduce_m_n_ratio(ret_m, ret_n); |
5011 | } |
5012 | |
5013 | void |
5014 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, |
5015 | int pixel_clock, int link_clock, |
5016 | struct intel_link_m_n *m_n) |
5017 | { |
5018 | m_n->tu = 64; |
5019 | |
5020 | compute_m_n(bits_per_pixel * pixel_clock, |
5021 | link_clock * nlanes * 8, |
5022 | &m_n->gmch_m, &m_n->gmch_n); |
5023 | |
5024 | compute_m_n(pixel_clock, link_clock, |
5025 | &m_n->link_m, &m_n->link_n); |
5026 | } |
5027 | |
5028 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5029 | { |
5030 | if (i915.panel_use_ssc >= 0) |
5031 | return i915.panel_use_ssc != 0; |
5032 | return dev_priv->vbt.lvds_use_ssc |
5033 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
5034 | } |
5035 | |
5036 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5037 | { |
5038 | struct drm_device *dev = crtc->dev; |
5039 | struct drm_i915_private *dev_priv = dev->dev_private; |
5040 | int refclk; |
5041 | |
5042 | if (IS_VALLEYVIEW(dev)) { |
5043 | refclk = 100000; |
5044 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
5045 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
5046 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5047 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n" , refclk); |
5048 | } else if (!IS_GEN2(dev)) { |
5049 | refclk = 96000; |
5050 | } else { |
5051 | refclk = 48000; |
5052 | } |
5053 | |
5054 | return refclk; |
5055 | } |
5056 | |
5057 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
5058 | { |
5059 | return (1 << dpll->n) << 16 | dpll->m2; |
5060 | } |
5061 | |
5062 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5063 | { |
5064 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
5065 | } |
5066 | |
5067 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
5068 | intel_clock_t *reduced_clock) |
5069 | { |
5070 | struct drm_device *dev = crtc->base.dev; |
5071 | struct drm_i915_private *dev_priv = dev->dev_private; |
5072 | int pipe = crtc->pipe; |
5073 | u32 fp, fp2 = 0; |
5074 | |
5075 | if (IS_PINEVIEW(dev)) { |
5076 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
5077 | if (reduced_clock) |
5078 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
5079 | } else { |
5080 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
5081 | if (reduced_clock) |
5082 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
5083 | } |
5084 | |
5085 | I915_WRITE(FP0(pipe), fp); |
5086 | crtc->config.dpll_hw_state.fp0 = fp; |
5087 | |
5088 | crtc->lowfreq_avail = false; |
5089 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
5090 | reduced_clock && i915.powersave) { |
5091 | I915_WRITE(FP1(pipe), fp2); |
5092 | crtc->config.dpll_hw_state.fp1 = fp2; |
5093 | crtc->lowfreq_avail = true; |
5094 | } else { |
5095 | I915_WRITE(FP1(pipe), fp); |
5096 | crtc->config.dpll_hw_state.fp1 = fp; |
5097 | } |
5098 | } |
5099 | |
5100 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum i915_pipe |
5101 | pipe) |
5102 | { |
5103 | u32 reg_val; |
5104 | |
5105 | /* |
5106 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
5107 | * and set it to a reasonable value instead. |
5108 | */ |
5109 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
5110 | reg_val &= 0xffffff00; |
5111 | reg_val |= 0x00000030; |
5112 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
5113 | |
5114 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
5115 | reg_val &= 0x8cffffff; |
5116 | reg_val = 0x8c000000; |
5117 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
5118 | |
5119 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
5120 | reg_val &= 0xffffff00; |
5121 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
5122 | |
5123 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
5124 | reg_val &= 0x00ffffff; |
5125 | reg_val |= 0xb0000000; |
5126 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
5127 | } |
5128 | |
5129 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5130 | struct intel_link_m_n *m_n) |
5131 | { |
5132 | struct drm_device *dev = crtc->base.dev; |
5133 | struct drm_i915_private *dev_priv = dev->dev_private; |
5134 | int pipe = crtc->pipe; |
5135 | |
5136 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5137 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); |
5138 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); |
5139 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); |
5140 | } |
5141 | |
5142 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
5143 | struct intel_link_m_n *m_n) |
5144 | { |
5145 | struct drm_device *dev = crtc->base.dev; |
5146 | struct drm_i915_private *dev_priv = dev->dev_private; |
5147 | int pipe = crtc->pipe; |
5148 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
5149 | |
5150 | if (INTEL_INFO(dev)->gen >= 5) { |
5151 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5152 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); |
5153 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); |
5154 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); |
5155 | } else { |
5156 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5157 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); |
5158 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); |
5159 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); |
5160 | } |
5161 | } |
5162 | |
5163 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
5164 | { |
5165 | if (crtc->config.has_pch_encoder) |
5166 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
5167 | else |
5168 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
5169 | } |
5170 | |
5171 | static void vlv_update_pll(struct intel_crtc *crtc) |
5172 | { |
5173 | struct drm_device *dev = crtc->base.dev; |
5174 | struct drm_i915_private *dev_priv = dev->dev_private; |
5175 | int pipe = crtc->pipe; |
5176 | u32 dpll, mdiv; |
5177 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
5178 | u32 coreclk, reg_val, dpll_md; |
5179 | |
5180 | mutex_lock(&dev_priv->dpio_lock); |
5181 | |
5182 | bestn = crtc->config.dpll.n; |
5183 | bestm1 = crtc->config.dpll.m1; |
5184 | bestm2 = crtc->config.dpll.m2; |
5185 | bestp1 = crtc->config.dpll.p1; |
5186 | bestp2 = crtc->config.dpll.p2; |
5187 | |
5188 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5189 | |
5190 | /* PLL B needs special handling */ |
5191 | if (pipe) |
5192 | vlv_pllb_recal_opamp(dev_priv, pipe); |
5193 | |
5194 | /* Set up Tx target for periodic Rcomp update */ |
5195 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
5196 | |
5197 | /* Disable target IRef on PLL */ |
5198 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
5199 | reg_val &= 0x00ffffff; |
5200 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
5201 | |
5202 | /* Disable fast lock */ |
5203 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
5204 | |
5205 | /* Set idtafcrecal before PLL is enabled */ |
5206 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5207 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
5208 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
5209 | mdiv |= (1 << DPIO_K_SHIFT); |
5210 | |
5211 | /* |
5212 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
5213 | * but we don't support that). |
5214 | * Note: don't use the DAC post divider as it seems unstable. |
5215 | */ |
5216 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
5217 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
5218 | |
5219 | mdiv |= DPIO_ENABLE_CALIBRATION; |
5220 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
5221 | |
5222 | /* Set HBR and RBR LPF coefficients */ |
5223 | if (crtc->config.port_clock == 162000 || |
5224 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
5225 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
5226 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
5227 | 0x009f0003); |
5228 | else |
5229 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
5230 | 0x00d0000f); |
5231 | |
5232 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
5233 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { |
5234 | /* Use SSC source */ |
5235 | if (!pipe) |
5236 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
5237 | 0x0df40000); |
5238 | else |
5239 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
5240 | 0x0df70000); |
5241 | } else { /* HDMI or VGA */ |
5242 | /* Use bend source */ |
5243 | if (!pipe) |
5244 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
5245 | 0x0df70000); |
5246 | else |
5247 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
5248 | 0x0df40000); |
5249 | } |
5250 | |
5251 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
5252 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5253 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || |
5254 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) |
5255 | coreclk |= 0x01000000; |
5256 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
5257 | |
5258 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
5259 | |
5260 | /* |
5261 | * Enable DPIO clock input. We should never disable the reference |
5262 | * clock for pipe B, since VGA hotplug / manual detection depends |
5263 | * on it. |
5264 | */ |
5265 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
5266 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
5267 | /* We should never disable this, set it here for state tracking */ |
5268 | if (pipe == PIPE_B) |
5269 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
5270 | dpll |= DPLL_VCO_ENABLE; |
5271 | crtc->config.dpll_hw_state.dpll = dpll; |
5272 | |
5273 | dpll_md = (crtc->config.pixel_multiplier - 1) |
5274 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
5275 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
5276 | |
5277 | if (crtc->config.has_dp_encoder) |
5278 | intel_dp_set_m_n(crtc); |
5279 | |
5280 | mutex_unlock(&dev_priv->dpio_lock); |
5281 | } |
5282 | |
5283 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5284 | intel_clock_t *reduced_clock, |
5285 | int num_connectors) |
5286 | { |
5287 | struct drm_device *dev = crtc->base.dev; |
5288 | struct drm_i915_private *dev_priv = dev->dev_private; |
5289 | u32 dpll; |
5290 | bool is_sdvo; |
5291 | struct dpll *clock = &crtc->config.dpll; |
5292 | |
5293 | i9xx_update_pll_dividers(crtc, reduced_clock); |
5294 | |
5295 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5296 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); |
5297 | |
5298 | dpll = DPLL_VGA_MODE_DIS; |
5299 | |
5300 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
5301 | dpll |= DPLLB_MODE_LVDS; |
5302 | else |
5303 | dpll |= DPLLB_MODE_DAC_SERIAL; |
5304 | |
5305 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5306 | dpll |= (crtc->config.pixel_multiplier - 1) |
5307 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
5308 | } |
5309 | |
5310 | if (is_sdvo) |
5311 | dpll |= DPLL_SDVO_HIGH_SPEED; |
5312 | |
5313 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
5314 | dpll |= DPLL_SDVO_HIGH_SPEED; |
5315 | |
5316 | /* compute bitmask from p1 value */ |
5317 | if (IS_PINEVIEW(dev)) |
5318 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
5319 | else { |
5320 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5321 | if (IS_G4X(dev) && reduced_clock) |
5322 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
5323 | } |
5324 | switch (clock->p2) { |
5325 | case 5: |
5326 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
5327 | break; |
5328 | case 7: |
5329 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
5330 | break; |
5331 | case 10: |
5332 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
5333 | break; |
5334 | case 14: |
5335 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
5336 | break; |
5337 | } |
5338 | if (INTEL_INFO(dev)->gen >= 4) |
5339 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
5340 | |
5341 | if (crtc->config.sdvo_tv_clock) |
5342 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
5343 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
5344 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5345 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
5346 | else |
5347 | dpll |= PLL_REF_INPUT_DREFCLK; |
5348 | |
5349 | dpll |= DPLL_VCO_ENABLE; |
5350 | crtc->config.dpll_hw_state.dpll = dpll; |
5351 | |
5352 | if (INTEL_INFO(dev)->gen >= 4) { |
5353 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5354 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
5355 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
5356 | } |
5357 | |
5358 | if (crtc->config.has_dp_encoder) |
5359 | intel_dp_set_m_n(crtc); |
5360 | } |
5361 | |
5362 | static void i8xx_update_pll(struct intel_crtc *crtc, |
5363 | intel_clock_t *reduced_clock, |
5364 | int num_connectors) |
5365 | { |
5366 | struct drm_device *dev = crtc->base.dev; |
5367 | struct drm_i915_private *dev_priv = dev->dev_private; |
5368 | u32 dpll; |
5369 | struct dpll *clock = &crtc->config.dpll; |
5370 | |
5371 | i9xx_update_pll_dividers(crtc, reduced_clock); |
5372 | |
5373 | dpll = DPLL_VGA_MODE_DIS; |
5374 | |
5375 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
5376 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5377 | } else { |
5378 | if (clock->p1 == 2) |
5379 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
5380 | else |
5381 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5382 | if (clock->p2 == 4) |
5383 | dpll |= PLL_P2_DIVIDE_BY_4; |
5384 | } |
5385 | |
5386 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5387 | dpll |= DPLL_DVO_2X_MODE; |
5388 | |
5389 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
5390 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5391 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
5392 | else |
5393 | dpll |= PLL_REF_INPUT_DREFCLK; |
5394 | |
5395 | dpll |= DPLL_VCO_ENABLE; |
5396 | crtc->config.dpll_hw_state.dpll = dpll; |
5397 | } |
5398 | |
5399 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
5400 | { |
5401 | struct drm_device *dev = intel_crtc->base.dev; |
5402 | struct drm_i915_private *dev_priv = dev->dev_private; |
5403 | enum i915_pipe pipe = intel_crtc->pipe; |
5404 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
5405 | struct drm_display_mode *adjusted_mode = |
5406 | &intel_crtc->config.adjusted_mode; |
5407 | uint32_t crtc_vtotal, crtc_vblank_end; |
5408 | int vsyncshift = 0; |
5409 | |
5410 | /* We need to be careful not to changed the adjusted mode, for otherwise |
5411 | * the hw state checker will get angry at the mismatch. */ |
5412 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
5413 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
5414 | |
5415 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5416 | /* the chip adds 2 halflines automatically */ |
5417 | crtc_vtotal -= 1; |
5418 | crtc_vblank_end -= 1; |
5419 | |
5420 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) |
5421 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
5422 | else |
5423 | vsyncshift = adjusted_mode->crtc_hsync_start - |
5424 | adjusted_mode->crtc_htotal / 2; |
5425 | if (vsyncshift < 0) |
5426 | vsyncshift += adjusted_mode->crtc_htotal; |
5427 | } |
5428 | |
5429 | if (INTEL_INFO(dev)->gen > 3) |
5430 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
5431 | |
5432 | I915_WRITE(HTOTAL(cpu_transcoder), |
5433 | (adjusted_mode->crtc_hdisplay - 1) | |
5434 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5435 | I915_WRITE(HBLANK(cpu_transcoder), |
5436 | (adjusted_mode->crtc_hblank_start - 1) | |
5437 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5438 | I915_WRITE(HSYNC(cpu_transcoder), |
5439 | (adjusted_mode->crtc_hsync_start - 1) | |
5440 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5441 | |
5442 | I915_WRITE(VTOTAL(cpu_transcoder), |
5443 | (adjusted_mode->crtc_vdisplay - 1) | |
5444 | ((crtc_vtotal - 1) << 16)); |
5445 | I915_WRITE(VBLANK(cpu_transcoder), |
5446 | (adjusted_mode->crtc_vblank_start - 1) | |
5447 | ((crtc_vblank_end - 1) << 16)); |
5448 | I915_WRITE(VSYNC(cpu_transcoder), |
5449 | (adjusted_mode->crtc_vsync_start - 1) | |
5450 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5451 | |
5452 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5453 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is |
5454 | * documented on the DDI_FUNC_CTL register description, EDP Input Select |
5455 | * bits. */ |
5456 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && |
5457 | (pipe == PIPE_B || pipe == PIPE_C)) |
5458 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); |
5459 | |
5460 | /* pipesrc controls the size that is scaled from, which should |
5461 | * always be the user's requested size. |
5462 | */ |
5463 | I915_WRITE(PIPESRC(pipe), |
5464 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5465 | (intel_crtc->config.pipe_src_h - 1)); |
5466 | } |
5467 | |
5468 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5469 | struct intel_crtc_config *pipe_config) |
5470 | { |
5471 | struct drm_device *dev = crtc->base.dev; |
5472 | struct drm_i915_private *dev_priv = dev->dev_private; |
5473 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
5474 | uint32_t tmp; |
5475 | |
5476 | tmp = I915_READ(HTOTAL(cpu_transcoder)); |
5477 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
5478 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
5479 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
5480 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
5481 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
5482 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
5483 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
5484 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
5485 | |
5486 | tmp = I915_READ(VTOTAL(cpu_transcoder)); |
5487 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
5488 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
5489 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
5490 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
5491 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
5492 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
5493 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
5494 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
5495 | |
5496 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { |
5497 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
5498 | pipe_config->adjusted_mode.crtc_vtotal += 1; |
5499 | pipe_config->adjusted_mode.crtc_vblank_end += 1; |
5500 | } |
5501 | |
5502 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
5503 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5504 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; |
5505 | |
5506 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; |
5507 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; |
5508 | } |
5509 | |
5510 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5511 | struct intel_crtc_config *pipe_config) |
5512 | { |
5513 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
5514 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; |
5515 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; |
5516 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; |
5517 | |
5518 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
5519 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; |
5520 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
5521 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
5522 | |
5523 | mode->flags = pipe_config->adjusted_mode.flags; |
5524 | |
5525 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
5526 | mode->flags |= pipe_config->adjusted_mode.flags; |
5527 | } |
5528 | |
5529 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5530 | { |
5531 | struct drm_device *dev = intel_crtc->base.dev; |
5532 | struct drm_i915_private *dev_priv = dev->dev_private; |
5533 | uint32_t pipeconf; |
5534 | |
5535 | pipeconf = 0; |
5536 | |
5537 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5538 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) |
5539 | pipeconf |= PIPECONF_ENABLE; |
5540 | |
5541 | if (intel_crtc->config.double_wide) |
5542 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
5543 | |
5544 | /* only g4x and later have fancy bpc/dither controls */ |
5545 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5546 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5547 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) |
5548 | pipeconf |= PIPECONF_DITHER_EN | |
5549 | PIPECONF_DITHER_TYPE_SP; |
5550 | |
5551 | switch (intel_crtc->config.pipe_bpp) { |
5552 | case 18: |
5553 | pipeconf |= PIPECONF_6BPC; |
5554 | break; |
5555 | case 24: |
5556 | pipeconf |= PIPECONF_8BPC; |
5557 | break; |
5558 | case 30: |
5559 | pipeconf |= PIPECONF_10BPC; |
5560 | break; |
5561 | default: |
5562 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5563 | BUG(); |
5564 | } |
5565 | } |
5566 | |
5567 | if (HAS_PIPE_CXSR(dev)) { |
5568 | if (intel_crtc->lowfreq_avail) { |
5569 | DRM_DEBUG_KMS("enabling CxSR downclocking\n" ); |
5570 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
5571 | } else { |
5572 | DRM_DEBUG_KMS("disabling CxSR downclocking\n" ); |
5573 | } |
5574 | } |
5575 | |
5576 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
5577 | if (INTEL_INFO(dev)->gen < 4 || |
5578 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) |
5579 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
5580 | else |
5581 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; |
5582 | } else |
5583 | pipeconf |= PIPECONF_PROGRESSIVE; |
5584 | |
5585 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5586 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
5587 | |
5588 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5589 | POSTING_READ(PIPECONF(intel_crtc->pipe)); |
5590 | } |
5591 | |
5592 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
5593 | int x, int y, |
5594 | struct drm_framebuffer *fb) |
5595 | { |
5596 | struct drm_device *dev = crtc->dev; |
5597 | struct drm_i915_private *dev_priv = dev->dev_private; |
5598 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5599 | int pipe = intel_crtc->pipe; |
5600 | int plane = intel_crtc->plane; |
5601 | int refclk, num_connectors = 0; |
5602 | intel_clock_t clock, reduced_clock; |
5603 | u32 dspcntr; |
5604 | bool ok, has_reduced_clock = false; |
5605 | bool is_lvds = false, is_dsi = false; |
5606 | struct intel_encoder *encoder; |
5607 | const intel_limit_t *limit; |
5608 | int ret; |
5609 | |
5610 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5611 | switch (encoder->type) { |
5612 | case INTEL_OUTPUT_LVDS: |
5613 | is_lvds = true; |
5614 | break; |
5615 | case INTEL_OUTPUT_DSI: |
5616 | is_dsi = true; |
5617 | break; |
5618 | } |
5619 | |
5620 | num_connectors++; |
5621 | } |
5622 | |
5623 | if (is_dsi) |
5624 | goto skip_dpll; |
5625 | |
5626 | if (!intel_crtc->config.clock_set) { |
5627 | refclk = i9xx_get_refclk(crtc, num_connectors); |
5628 | |
5629 | /* |
5630 | * Returns a set of divisors for the desired target clock with |
5631 | * the given refclk, or FALSE. The returned values represent |
5632 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + |
5633 | * 2) / p1 / p2. |
5634 | */ |
5635 | limit = intel_limit(crtc, refclk); |
5636 | ok = dev_priv->display.find_dpll(limit, crtc, |
5637 | intel_crtc->config.port_clock, |
5638 | refclk, NULL, &clock); |
5639 | if (!ok) { |
5640 | DRM_ERROR("Couldn't find PLL settings for mode!\n" ); |
5641 | return -EINVAL; |
5642 | } |
5643 | |
5644 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5645 | /* |
5646 | * Ensure we match the reduced clock's P to the target |
5647 | * clock. If the clocks don't match, we can't switch |
5648 | * the display clock by using the FP0/FP1. In such case |
5649 | * we will disable the LVDS downclock feature. |
5650 | */ |
5651 | has_reduced_clock = |
5652 | dev_priv->display.find_dpll(limit, crtc, |
5653 | dev_priv->lvds_downclock, |
5654 | refclk, &clock, |
5655 | &reduced_clock); |
5656 | } |
5657 | /* Compat-code for transition, will disappear. */ |
5658 | intel_crtc->config.dpll.n = clock.n; |
5659 | intel_crtc->config.dpll.m1 = clock.m1; |
5660 | intel_crtc->config.dpll.m2 = clock.m2; |
5661 | intel_crtc->config.dpll.p1 = clock.p1; |
5662 | intel_crtc->config.dpll.p2 = clock.p2; |
5663 | } |
5664 | |
5665 | if (IS_GEN2(dev)) { |
5666 | i8xx_update_pll(intel_crtc, |
5667 | has_reduced_clock ? &reduced_clock : NULL, |
5668 | num_connectors); |
5669 | } else if (IS_VALLEYVIEW(dev)) { |
5670 | vlv_update_pll(intel_crtc); |
5671 | } else { |
5672 | i9xx_update_pll(intel_crtc, |
5673 | has_reduced_clock ? &reduced_clock : NULL, |
5674 | num_connectors); |
5675 | } |
5676 | |
5677 | skip_dpll: |
5678 | /* Set up the display plane register */ |
5679 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
5680 | |
5681 | if (!IS_VALLEYVIEW(dev)) { |
5682 | if (pipe == 0) |
5683 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
5684 | else |
5685 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
5686 | } |
5687 | |
5688 | intel_set_pipe_timings(intel_crtc); |
5689 | |
5690 | /* pipesrc and dspsize control the size that is scaled from, |
5691 | * which should always be the user's requested size. |
5692 | */ |
5693 | I915_WRITE(DSPSIZE(plane), |
5694 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
5695 | (intel_crtc->config.pipe_src_w - 1)); |
5696 | I915_WRITE(DSPPOS(plane), 0); |
5697 | |
5698 | i9xx_set_pipeconf(intel_crtc); |
5699 | |
5700 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5701 | POSTING_READ(DSPCNTR(plane)); |
5702 | |
5703 | ret = intel_pipe_set_base(crtc, x, y, fb); |
5704 | |
5705 | return ret; |
5706 | } |
5707 | |
5708 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5709 | struct intel_crtc_config *pipe_config) |
5710 | { |
5711 | struct drm_device *dev = crtc->base.dev; |
5712 | struct drm_i915_private *dev_priv = dev->dev_private; |
5713 | uint32_t tmp; |
5714 | |
5715 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
5716 | return; |
5717 | |
5718 | tmp = I915_READ(PFIT_CONTROL); |
5719 | if (!(tmp & PFIT_ENABLE)) |
5720 | return; |
5721 | |
5722 | /* Check whether the pfit is attached to our pipe. */ |
5723 | if (INTEL_INFO(dev)->gen < 4) { |
5724 | if (crtc->pipe != PIPE_B) |
5725 | return; |
5726 | } else { |
5727 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) |
5728 | return; |
5729 | } |
5730 | |
5731 | pipe_config->gmch_pfit.control = tmp; |
5732 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5733 | if (INTEL_INFO(dev)->gen < 5) |
5734 | pipe_config->gmch_pfit.lvds_border_bits = |
5735 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
5736 | } |
5737 | |
5738 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5739 | struct intel_crtc_config *pipe_config) |
5740 | { |
5741 | struct drm_device *dev = crtc->base.dev; |
5742 | struct drm_i915_private *dev_priv = dev->dev_private; |
5743 | int pipe = pipe_config->cpu_transcoder; |
5744 | intel_clock_t clock; |
5745 | u32 mdiv; |
5746 | int refclk = 100000; |
5747 | |
5748 | mutex_lock(&dev_priv->dpio_lock); |
5749 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
5750 | mutex_unlock(&dev_priv->dpio_lock); |
5751 | |
5752 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
5753 | clock.m2 = mdiv & DPIO_M2DIV_MASK; |
5754 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
5755 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
5756 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
5757 | |
5758 | vlv_clock(refclk, &clock); |
5759 | |
5760 | /* clock.dot is the fast clock */ |
5761 | pipe_config->port_clock = clock.dot / 5; |
5762 | } |
5763 | |
5764 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
5765 | struct intel_plane_config *plane_config) |
5766 | { |
5767 | struct drm_device *dev = crtc->base.dev; |
5768 | struct drm_i915_private *dev_priv = dev->dev_private; |
5769 | u32 val, base; |
5770 | int pipe = crtc->pipe, plane = crtc->plane; |
5771 | int fourcc, pixel_format; |
5772 | int aligned_height; |
5773 | |
5774 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
5775 | if (!crtc->base.primary->fb) { |
5776 | DRM_DEBUG_KMS("failed to alloc fb\n" ); |
5777 | return; |
5778 | } |
5779 | |
5780 | val = I915_READ(DSPCNTR(plane)); |
5781 | |
5782 | if (INTEL_INFO(dev)->gen >= 4) |
5783 | if (val & DISPPLANE_TILED) |
5784 | plane_config->tiled = true; |
5785 | |
5786 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
5787 | fourcc = intel_format_to_fourcc(pixel_format); |
5788 | crtc->base.primary->fb->pixel_format = fourcc; |
5789 | crtc->base.primary->fb->bits_per_pixel = |
5790 | drm_format_plane_cpp(fourcc, 0) * 8; |
5791 | |
5792 | if (INTEL_INFO(dev)->gen >= 4) { |
5793 | if (plane_config->tiled) |
5794 | (void)I915_READ(DSPTILEOFF(plane)); |
5795 | else |
5796 | (void)I915_READ(DSPLINOFF(plane)); |
5797 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; |
5798 | } else { |
5799 | base = I915_READ(DSPADDR(plane)); |
5800 | } |
5801 | plane_config->base = base; |
5802 | |
5803 | val = I915_READ(PIPESRC(pipe)); |
5804 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
5805 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; |
5806 | |
5807 | val = I915_READ(DSPSTRIDE(pipe)); |
5808 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
5809 | |
5810 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
5811 | plane_config->tiled); |
5812 | |
5813 | #ifdef __NetBSD__ /* XXX ALIGN means something else. */ |
5814 | plane_config->size = round_up(crtc->base.primary->fb->pitches[0] * |
5815 | aligned_height, PAGE_SIZE); |
5816 | #else |
5817 | plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] * |
5818 | aligned_height, PAGE_SIZE); |
5819 | #endif |
5820 | |
5821 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , |
5822 | pipe, plane, crtc->base.primary->fb->width, |
5823 | crtc->base.primary->fb->height, |
5824 | crtc->base.primary->fb->bits_per_pixel, base, |
5825 | crtc->base.primary->fb->pitches[0], |
5826 | plane_config->size); |
5827 | |
5828 | } |
5829 | |
5830 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5831 | struct intel_crtc_config *pipe_config) |
5832 | { |
5833 | struct drm_device *dev = crtc->base.dev; |
5834 | struct drm_i915_private *dev_priv = dev->dev_private; |
5835 | uint32_t tmp; |
5836 | |
5837 | if (!intel_display_power_enabled(dev_priv, |
5838 | POWER_DOMAIN_PIPE(crtc->pipe))) |
5839 | return false; |
5840 | |
5841 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
5842 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
5843 | |
5844 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5845 | if (!(tmp & PIPECONF_ENABLE)) |
5846 | return false; |
5847 | |
5848 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5849 | switch (tmp & PIPECONF_BPC_MASK) { |
5850 | case PIPECONF_6BPC: |
5851 | pipe_config->pipe_bpp = 18; |
5852 | break; |
5853 | case PIPECONF_8BPC: |
5854 | pipe_config->pipe_bpp = 24; |
5855 | break; |
5856 | case PIPECONF_10BPC: |
5857 | pipe_config->pipe_bpp = 30; |
5858 | break; |
5859 | default: |
5860 | break; |
5861 | } |
5862 | } |
5863 | |
5864 | if (INTEL_INFO(dev)->gen < 4) |
5865 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
5866 | |
5867 | intel_get_pipe_timings(crtc, pipe_config); |
5868 | |
5869 | i9xx_get_pfit_config(crtc, pipe_config); |
5870 | |
5871 | if (INTEL_INFO(dev)->gen >= 4) { |
5872 | tmp = I915_READ(DPLL_MD(crtc->pipe)); |
5873 | pipe_config->pixel_multiplier = |
5874 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) |
5875 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; |
5876 | pipe_config->dpll_hw_state.dpll_md = tmp; |
5877 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5878 | tmp = I915_READ(DPLL(crtc->pipe)); |
5879 | pipe_config->pixel_multiplier = |
5880 | ((tmp & SDVO_MULTIPLIER_MASK) |
5881 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; |
5882 | } else { |
5883 | /* Note that on i915G/GM the pixel multiplier is in the sdvo |
5884 | * port and will be fixed up in the encoder->get_config |
5885 | * function. */ |
5886 | pipe_config->pixel_multiplier = 1; |
5887 | } |
5888 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5889 | if (!IS_VALLEYVIEW(dev)) { |
5890 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
5891 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); |
5892 | } else { |
5893 | /* Mask out read-only status bits. */ |
5894 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
5895 | DPLL_PORTC_READY_MASK | |
5896 | DPLL_PORTB_READY_MASK); |
5897 | } |
5898 | |
5899 | if (IS_VALLEYVIEW(dev)) |
5900 | vlv_crtc_clock_get(crtc, pipe_config); |
5901 | else |
5902 | i9xx_crtc_clock_get(crtc, pipe_config); |
5903 | |
5904 | return true; |
5905 | } |
5906 | |
5907 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
5908 | { |
5909 | struct drm_i915_private *dev_priv = dev->dev_private; |
5910 | struct drm_mode_config *mode_config = &dev->mode_config; |
5911 | struct intel_encoder *encoder; |
5912 | u32 val, final; |
5913 | bool has_lvds = false; |
5914 | bool has_cpu_edp = false; |
5915 | bool has_panel = false; |
5916 | bool has_ck505 = false; |
5917 | bool can_ssc = false; |
5918 | |
5919 | /* We need to take the global config into account */ |
5920 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5921 | base.head) { |
5922 | switch (encoder->type) { |
5923 | case INTEL_OUTPUT_LVDS: |
5924 | has_panel = true; |
5925 | has_lvds = true; |
5926 | break; |
5927 | case INTEL_OUTPUT_EDP: |
5928 | has_panel = true; |
5929 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
5930 | has_cpu_edp = true; |
5931 | break; |
5932 | } |
5933 | } |
5934 | |
5935 | if (HAS_PCH_IBX(dev)) { |
5936 | has_ck505 = dev_priv->vbt.display_clock_mode; |
5937 | can_ssc = has_ck505; |
5938 | } else { |
5939 | has_ck505 = false; |
5940 | can_ssc = true; |
5941 | } |
5942 | |
5943 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n" , |
5944 | has_panel, has_lvds, has_ck505); |
5945 | |
5946 | /* Ironlake: try to setup display ref clock before DPLL |
5947 | * enabling. This is only under driver's control after |
5948 | * PCH B stepping, previous chipset stepping should be |
5949 | * ignoring this setting. |
5950 | */ |
5951 | val = I915_READ(PCH_DREF_CONTROL); |
5952 | |
5953 | /* As we must carefully and slowly disable/enable each source in turn, |
5954 | * compute the final state we want first and check if we need to |
5955 | * make any changes at all. |
5956 | */ |
5957 | final = val; |
5958 | final &= ~DREF_NONSPREAD_SOURCE_MASK; |
5959 | if (has_ck505) |
5960 | final |= DREF_NONSPREAD_CK505_ENABLE; |
5961 | else |
5962 | final |= DREF_NONSPREAD_SOURCE_ENABLE; |
5963 | |
5964 | final &= ~DREF_SSC_SOURCE_MASK; |
5965 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5966 | final &= ~DREF_SSC1_ENABLE; |
5967 | |
5968 | if (has_panel) { |
5969 | final |= DREF_SSC_SOURCE_ENABLE; |
5970 | |
5971 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
5972 | final |= DREF_SSC1_ENABLE; |
5973 | |
5974 | if (has_cpu_edp) { |
5975 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
5976 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
5977 | else |
5978 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
5979 | } else |
5980 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5981 | } else { |
5982 | final |= DREF_SSC_SOURCE_DISABLE; |
5983 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
5984 | } |
5985 | |
5986 | if (final == val) |
5987 | return; |
5988 | |
5989 | /* Always enable nonspread source */ |
5990 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
5991 | |
5992 | if (has_ck505) |
5993 | val |= DREF_NONSPREAD_CK505_ENABLE; |
5994 | else |
5995 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
5996 | |
5997 | if (has_panel) { |
5998 | val &= ~DREF_SSC_SOURCE_MASK; |
5999 | val |= DREF_SSC_SOURCE_ENABLE; |
6000 | |
6001 | /* SSC must be turned on before enabling the CPU output */ |
6002 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
6003 | DRM_DEBUG_KMS("Using SSC on panel\n" ); |
6004 | val |= DREF_SSC1_ENABLE; |
6005 | } else |
6006 | val &= ~DREF_SSC1_ENABLE; |
6007 | |
6008 | /* Get SSC going before enabling the outputs */ |
6009 | I915_WRITE(PCH_DREF_CONTROL, val); |
6010 | POSTING_READ(PCH_DREF_CONTROL); |
6011 | udelay(200); |
6012 | |
6013 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
6014 | |
6015 | /* Enable CPU source on CPU attached eDP */ |
6016 | if (has_cpu_edp) { |
6017 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
6018 | DRM_DEBUG_KMS("Using SSC on eDP\n" ); |
6019 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
6020 | } |
6021 | else |
6022 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
6023 | } else |
6024 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
6025 | |
6026 | I915_WRITE(PCH_DREF_CONTROL, val); |
6027 | POSTING_READ(PCH_DREF_CONTROL); |
6028 | udelay(200); |
6029 | } else { |
6030 | DRM_DEBUG_KMS("Disabling SSC entirely\n" ); |
6031 | |
6032 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
6033 | |
6034 | /* Turn off CPU output */ |
6035 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
6036 | |
6037 | I915_WRITE(PCH_DREF_CONTROL, val); |
6038 | POSTING_READ(PCH_DREF_CONTROL); |
6039 | udelay(200); |
6040 | |
6041 | /* Turn off the SSC source */ |
6042 | val &= ~DREF_SSC_SOURCE_MASK; |
6043 | val |= DREF_SSC_SOURCE_DISABLE; |
6044 | |
6045 | /* Turn off SSC1 */ |
6046 | val &= ~DREF_SSC1_ENABLE; |
6047 | |
6048 | I915_WRITE(PCH_DREF_CONTROL, val); |
6049 | POSTING_READ(PCH_DREF_CONTROL); |
6050 | udelay(200); |
6051 | } |
6052 | |
6053 | BUG_ON(val != final); |
6054 | } |
6055 | |
6056 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
6057 | { |
6058 | uint32_t tmp; |
6059 | |
6060 | tmp = I915_READ(SOUTH_CHICKEN2); |
6061 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
6062 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
6063 | |
6064 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6065 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
6066 | DRM_ERROR("FDI mPHY reset assert timeout\n" ); |
6067 | |
6068 | tmp = I915_READ(SOUTH_CHICKEN2); |
6069 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
6070 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
6071 | |
6072 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6073 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
6074 | DRM_ERROR("FDI mPHY reset de-assert timeout\n" ); |
6075 | } |
6076 | |
6077 | /* WaMPhyProgramming:hsw */ |
6078 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) |
6079 | { |
6080 | uint32_t tmp; |
6081 | |
6082 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); |
6083 | tmp &= ~(0xFF << 24); |
6084 | tmp |= (0x12 << 24); |
6085 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); |
6086 | |
6087 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6088 | tmp |= (1 << 11); |
6089 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); |
6090 | |
6091 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); |
6092 | tmp |= (1 << 11); |
6093 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); |
6094 | |
6095 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6096 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
6097 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); |
6098 | |
6099 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); |
6100 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
6101 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); |
6102 | |
6103 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6104 | tmp &= ~(7 << 13); |
6105 | tmp |= (5 << 13); |
6106 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); |
6107 | |
6108 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6109 | tmp &= ~(7 << 13); |
6110 | tmp |= (5 << 13); |
6111 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); |
6112 | |
6113 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); |
6114 | tmp &= ~0xFF; |
6115 | tmp |= 0x1C; |
6116 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); |
6117 | |
6118 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); |
6119 | tmp &= ~0xFF; |
6120 | tmp |= 0x1C; |
6121 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); |
6122 | |
6123 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); |
6124 | tmp &= ~(0xFF << 16); |
6125 | tmp |= (0x1C << 16); |
6126 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); |
6127 | |
6128 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); |
6129 | tmp &= ~(0xFF << 16); |
6130 | tmp |= (0x1C << 16); |
6131 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); |
6132 | |
6133 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6134 | tmp |= (1 << 27); |
6135 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); |
6136 | |
6137 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6138 | tmp |= (1 << 27); |
6139 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); |
6140 | |
6141 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6142 | tmp &= ~(0xF << 28); |
6143 | tmp |= (4 << 28); |
6144 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); |
6145 | |
6146 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6147 | tmp &= ~(0xF << 28); |
6148 | tmp |= (4 << 28); |
6149 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); |
6150 | } |
6151 | |
6152 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6153 | * Programming" based on the parameters passed: |
6154 | * - Sequence to enable CLKOUT_DP |
6155 | * - Sequence to enable CLKOUT_DP without spread |
6156 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O |
6157 | */ |
6158 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, |
6159 | bool with_fdi) |
6160 | { |
6161 | struct drm_i915_private *dev_priv = dev->dev_private; |
6162 | uint32_t reg, tmp; |
6163 | |
6164 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n" )) |
6165 | with_spread = true; |
6166 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && |
6167 | with_fdi, "LP PCH doesn't have FDI\n" )) |
6168 | with_fdi = false; |
6169 | |
6170 | mutex_lock(&dev_priv->dpio_lock); |
6171 | |
6172 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
6173 | tmp &= ~SBI_SSCCTL_DISABLE; |
6174 | tmp |= SBI_SSCCTL_PATHALT; |
6175 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
6176 | |
6177 | udelay(24); |
6178 | |
6179 | if (with_spread) { |
6180 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
6181 | tmp &= ~SBI_SSCCTL_PATHALT; |
6182 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
6183 | |
6184 | if (with_fdi) { |
6185 | lpt_reset_fdi_mphy(dev_priv); |
6186 | lpt_program_fdi_mphy(dev_priv); |
6187 | } |
6188 | } |
6189 | |
6190 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6191 | SBI_GEN0 : SBI_DBUFF0; |
6192 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
6193 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
6194 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
6195 | |
6196 | mutex_unlock(&dev_priv->dpio_lock); |
6197 | } |
6198 | |
6199 | /* Sequence to disable CLKOUT_DP */ |
6200 | static void lpt_disable_clkout_dp(struct drm_device *dev) |
6201 | { |
6202 | struct drm_i915_private *dev_priv = dev->dev_private; |
6203 | uint32_t reg, tmp; |
6204 | |
6205 | mutex_lock(&dev_priv->dpio_lock); |
6206 | |
6207 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6208 | SBI_GEN0 : SBI_DBUFF0; |
6209 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
6210 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
6211 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
6212 | |
6213 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
6214 | if (!(tmp & SBI_SSCCTL_DISABLE)) { |
6215 | if (!(tmp & SBI_SSCCTL_PATHALT)) { |
6216 | tmp |= SBI_SSCCTL_PATHALT; |
6217 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
6218 | udelay(32); |
6219 | } |
6220 | tmp |= SBI_SSCCTL_DISABLE; |
6221 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
6222 | } |
6223 | |
6224 | mutex_unlock(&dev_priv->dpio_lock); |
6225 | } |
6226 | |
6227 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6228 | { |
6229 | struct drm_mode_config *mode_config = &dev->mode_config; |
6230 | struct intel_encoder *encoder; |
6231 | bool has_vga = false; |
6232 | |
6233 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
6234 | switch (encoder->type) { |
6235 | case INTEL_OUTPUT_ANALOG: |
6236 | has_vga = true; |
6237 | break; |
6238 | } |
6239 | } |
6240 | |
6241 | if (has_vga) |
6242 | lpt_enable_clkout_dp(dev, true, true); |
6243 | else |
6244 | lpt_disable_clkout_dp(dev); |
6245 | } |
6246 | |
6247 | /* |
6248 | * Initialize reference clocks when the driver loads |
6249 | */ |
6250 | void intel_init_pch_refclk(struct drm_device *dev) |
6251 | { |
6252 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
6253 | ironlake_init_pch_refclk(dev); |
6254 | else if (HAS_PCH_LPT(dev)) |
6255 | lpt_init_pch_refclk(dev); |
6256 | } |
6257 | |
6258 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6259 | { |
6260 | struct drm_device *dev = crtc->dev; |
6261 | struct drm_i915_private *dev_priv = dev->dev_private; |
6262 | struct intel_encoder *encoder; |
6263 | int num_connectors = 0; |
6264 | bool is_lvds = false; |
6265 | |
6266 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
6267 | switch (encoder->type) { |
6268 | case INTEL_OUTPUT_LVDS: |
6269 | is_lvds = true; |
6270 | break; |
6271 | } |
6272 | num_connectors++; |
6273 | } |
6274 | |
6275 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
6276 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n" , |
6277 | dev_priv->vbt.lvds_ssc_freq); |
6278 | return dev_priv->vbt.lvds_ssc_freq; |
6279 | } |
6280 | |
6281 | return 120000; |
6282 | } |
6283 | |
6284 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
6285 | { |
6286 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
6287 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6288 | int pipe = intel_crtc->pipe; |
6289 | uint32_t val; |
6290 | |
6291 | val = 0; |
6292 | |
6293 | switch (intel_crtc->config.pipe_bpp) { |
6294 | case 18: |
6295 | val |= PIPECONF_6BPC; |
6296 | break; |
6297 | case 24: |
6298 | val |= PIPECONF_8BPC; |
6299 | break; |
6300 | case 30: |
6301 | val |= PIPECONF_10BPC; |
6302 | break; |
6303 | case 36: |
6304 | val |= PIPECONF_12BPC; |
6305 | break; |
6306 | default: |
6307 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6308 | BUG(); |
6309 | } |
6310 | |
6311 | if (intel_crtc->config.dither) |
6312 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6313 | |
6314 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
6315 | val |= PIPECONF_INTERLACED_ILK; |
6316 | else |
6317 | val |= PIPECONF_PROGRESSIVE; |
6318 | |
6319 | if (intel_crtc->config.limited_color_range) |
6320 | val |= PIPECONF_COLOR_RANGE_SELECT; |
6321 | |
6322 | I915_WRITE(PIPECONF(pipe), val); |
6323 | POSTING_READ(PIPECONF(pipe)); |
6324 | } |
6325 | |
6326 | /* |
6327 | * Set up the pipe CSC unit. |
6328 | * |
6329 | * Currently only full range RGB to limited range RGB conversion |
6330 | * is supported, but eventually this should handle various |
6331 | * RGB<->YCbCr scenarios as well. |
6332 | */ |
6333 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
6334 | { |
6335 | struct drm_device *dev = crtc->dev; |
6336 | struct drm_i915_private *dev_priv = dev->dev_private; |
6337 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6338 | int pipe = intel_crtc->pipe; |
6339 | uint16_t coeff = 0x7800; /* 1.0 */ |
6340 | |
6341 | /* |
6342 | * TODO: Check what kind of values actually come out of the pipe |
6343 | * with these coeff/postoff values and adjust to get the best |
6344 | * accuracy. Perhaps we even need to take the bpc value into |
6345 | * consideration. |
6346 | */ |
6347 | |
6348 | if (intel_crtc->config.limited_color_range) |
6349 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6350 | |
6351 | /* |
6352 | * GY/GU and RY/RU should be the other way around according |
6353 | * to BSpec, but reality doesn't agree. Just set them up in |
6354 | * a way that results in the correct picture. |
6355 | */ |
6356 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); |
6357 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); |
6358 | |
6359 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); |
6360 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); |
6361 | |
6362 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); |
6363 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); |
6364 | |
6365 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); |
6366 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); |
6367 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); |
6368 | |
6369 | if (INTEL_INFO(dev)->gen > 6) { |
6370 | uint16_t postoff = 0; |
6371 | |
6372 | if (intel_crtc->config.limited_color_range) |
6373 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
6374 | |
6375 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
6376 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
6377 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); |
6378 | |
6379 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); |
6380 | } else { |
6381 | uint32_t mode = CSC_MODE_YUV_TO_RGB; |
6382 | |
6383 | if (intel_crtc->config.limited_color_range) |
6384 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6385 | |
6386 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); |
6387 | } |
6388 | } |
6389 | |
6390 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
6391 | { |
6392 | struct drm_device *dev = crtc->dev; |
6393 | struct drm_i915_private *dev_priv = dev->dev_private; |
6394 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6395 | enum i915_pipe pipe = intel_crtc->pipe; |
6396 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
6397 | uint32_t val; |
6398 | |
6399 | val = 0; |
6400 | |
6401 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
6402 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6403 | |
6404 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
6405 | val |= PIPECONF_INTERLACED_ILK; |
6406 | else |
6407 | val |= PIPECONF_PROGRESSIVE; |
6408 | |
6409 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6410 | POSTING_READ(PIPECONF(cpu_transcoder)); |
6411 | |
6412 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
6413 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
6414 | |
6415 | if (IS_BROADWELL(dev)) { |
6416 | val = 0; |
6417 | |
6418 | switch (intel_crtc->config.pipe_bpp) { |
6419 | case 18: |
6420 | val |= PIPEMISC_DITHER_6_BPC; |
6421 | break; |
6422 | case 24: |
6423 | val |= PIPEMISC_DITHER_8_BPC; |
6424 | break; |
6425 | case 30: |
6426 | val |= PIPEMISC_DITHER_10_BPC; |
6427 | break; |
6428 | case 36: |
6429 | val |= PIPEMISC_DITHER_12_BPC; |
6430 | break; |
6431 | default: |
6432 | /* Case prevented by pipe_config_set_bpp. */ |
6433 | BUG(); |
6434 | } |
6435 | |
6436 | if (intel_crtc->config.dither) |
6437 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
6438 | |
6439 | I915_WRITE(PIPEMISC(pipe), val); |
6440 | } |
6441 | } |
6442 | |
6443 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6444 | intel_clock_t *clock, |
6445 | bool *has_reduced_clock, |
6446 | intel_clock_t *reduced_clock) |
6447 | { |
6448 | struct drm_device *dev = crtc->dev; |
6449 | struct drm_i915_private *dev_priv = dev->dev_private; |
6450 | struct intel_encoder *intel_encoder; |
6451 | int refclk; |
6452 | const intel_limit_t *limit; |
6453 | bool ret, is_lvds = false; |
6454 | |
6455 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6456 | switch (intel_encoder->type) { |
6457 | case INTEL_OUTPUT_LVDS: |
6458 | is_lvds = true; |
6459 | break; |
6460 | } |
6461 | } |
6462 | |
6463 | refclk = ironlake_get_refclk(crtc); |
6464 | |
6465 | /* |
6466 | * Returns a set of divisors for the desired target clock with the given |
6467 | * refclk, or FALSE. The returned values represent the clock equation: |
6468 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
6469 | */ |
6470 | limit = intel_limit(crtc, refclk); |
6471 | ret = dev_priv->display.find_dpll(limit, crtc, |
6472 | to_intel_crtc(crtc)->config.port_clock, |
6473 | refclk, NULL, clock); |
6474 | if (!ret) |
6475 | return false; |
6476 | |
6477 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6478 | /* |
6479 | * Ensure we match the reduced clock's P to the target clock. |
6480 | * If the clocks don't match, we can't switch the display clock |
6481 | * by using the FP0/FP1. In such case we will disable the LVDS |
6482 | * downclock feature. |
6483 | */ |
6484 | *has_reduced_clock = |
6485 | dev_priv->display.find_dpll(limit, crtc, |
6486 | dev_priv->lvds_downclock, |
6487 | refclk, clock, |
6488 | reduced_clock); |
6489 | } |
6490 | |
6491 | return true; |
6492 | } |
6493 | |
6494 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6495 | { |
6496 | /* |
6497 | * Account for spread spectrum to avoid |
6498 | * oversubscribing the link. Max center spread |
6499 | * is 2.5%; use 5% for safety's sake. |
6500 | */ |
6501 | u32 bps = target_clock * bpp * 21 / 20; |
6502 | return DIV_ROUND_UP(bps, link_bw * 8); |
6503 | } |
6504 | |
6505 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6506 | { |
6507 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
6508 | } |
6509 | |
6510 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
6511 | u32 *fp, |
6512 | intel_clock_t *reduced_clock, u32 *fp2) |
6513 | { |
6514 | struct drm_crtc *crtc = &intel_crtc->base; |
6515 | struct drm_device *dev = crtc->dev; |
6516 | struct drm_i915_private *dev_priv = dev->dev_private; |
6517 | struct intel_encoder *intel_encoder; |
6518 | uint32_t dpll; |
6519 | int factor, num_connectors = 0; |
6520 | bool is_lvds = false, is_sdvo = false; |
6521 | |
6522 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6523 | switch (intel_encoder->type) { |
6524 | case INTEL_OUTPUT_LVDS: |
6525 | is_lvds = true; |
6526 | break; |
6527 | case INTEL_OUTPUT_SDVO: |
6528 | case INTEL_OUTPUT_HDMI: |
6529 | is_sdvo = true; |
6530 | break; |
6531 | } |
6532 | |
6533 | num_connectors++; |
6534 | } |
6535 | |
6536 | /* Enable autotuning of the PLL clock (if permissible) */ |
6537 | factor = 21; |
6538 | if (is_lvds) { |
6539 | if ((intel_panel_use_ssc(dev_priv) && |
6540 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6541 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
6542 | factor = 25; |
6543 | } else if (intel_crtc->config.sdvo_tv_clock) |
6544 | factor = 20; |
6545 | |
6546 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
6547 | *fp |= FP_CB_TUNE; |
6548 | |
6549 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6550 | *fp2 |= FP_CB_TUNE; |
6551 | |
6552 | dpll = 0; |
6553 | |
6554 | if (is_lvds) |
6555 | dpll |= DPLLB_MODE_LVDS; |
6556 | else |
6557 | dpll |= DPLLB_MODE_DAC_SERIAL; |
6558 | |
6559 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6560 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
6561 | |
6562 | if (is_sdvo) |
6563 | dpll |= DPLL_SDVO_HIGH_SPEED; |
6564 | if (intel_crtc->config.has_dp_encoder) |
6565 | dpll |= DPLL_SDVO_HIGH_SPEED; |
6566 | |
6567 | /* compute bitmask from p1 value */ |
6568 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6569 | /* also FPA1 */ |
6570 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
6571 | |
6572 | switch (intel_crtc->config.dpll.p2) { |
6573 | case 5: |
6574 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
6575 | break; |
6576 | case 7: |
6577 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
6578 | break; |
6579 | case 10: |
6580 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
6581 | break; |
6582 | case 14: |
6583 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
6584 | break; |
6585 | } |
6586 | |
6587 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6588 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6589 | else |
6590 | dpll |= PLL_REF_INPUT_DREFCLK; |
6591 | |
6592 | return dpll | DPLL_VCO_ENABLE; |
6593 | } |
6594 | |
6595 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
6596 | int x, int y, |
6597 | struct drm_framebuffer *fb) |
6598 | { |
6599 | struct drm_device *dev = crtc->dev; |
6600 | struct drm_i915_private *dev_priv = dev->dev_private; |
6601 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6602 | int pipe = intel_crtc->pipe; |
6603 | int plane = intel_crtc->plane; |
6604 | int num_connectors = 0; |
6605 | intel_clock_t clock, reduced_clock; |
6606 | u32 dpll = 0, fp = 0, fp2 = 0; |
6607 | bool ok, has_reduced_clock = false; |
6608 | bool is_lvds = false; |
6609 | struct intel_encoder *encoder; |
6610 | struct intel_shared_dpll *pll; |
6611 | int ret; |
6612 | |
6613 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
6614 | switch (encoder->type) { |
6615 | case INTEL_OUTPUT_LVDS: |
6616 | is_lvds = true; |
6617 | break; |
6618 | } |
6619 | |
6620 | num_connectors++; |
6621 | } |
6622 | |
6623 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
6624 | "Unexpected PCH type %d\n" , INTEL_PCH_TYPE(dev)); |
6625 | |
6626 | ok = ironlake_compute_clocks(crtc, &clock, |
6627 | &has_reduced_clock, &reduced_clock); |
6628 | if (!ok && !intel_crtc->config.clock_set) { |
6629 | DRM_ERROR("Couldn't find PLL settings for mode!\n" ); |
6630 | return -EINVAL; |
6631 | } |
6632 | /* Compat-code for transition, will disappear. */ |
6633 | if (!intel_crtc->config.clock_set) { |
6634 | intel_crtc->config.dpll.n = clock.n; |
6635 | intel_crtc->config.dpll.m1 = clock.m1; |
6636 | intel_crtc->config.dpll.m2 = clock.m2; |
6637 | intel_crtc->config.dpll.p1 = clock.p1; |
6638 | intel_crtc->config.dpll.p2 = clock.p2; |
6639 | } |
6640 | |
6641 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
6642 | if (intel_crtc->config.has_pch_encoder) { |
6643 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
6644 | if (has_reduced_clock) |
6645 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
6646 | |
6647 | dpll = ironlake_compute_dpll(intel_crtc, |
6648 | &fp, &reduced_clock, |
6649 | has_reduced_clock ? &fp2 : NULL); |
6650 | |
6651 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
6652 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
6653 | if (has_reduced_clock) |
6654 | intel_crtc->config.dpll_hw_state.fp1 = fp2; |
6655 | else |
6656 | intel_crtc->config.dpll_hw_state.fp1 = fp; |
6657 | |
6658 | pll = intel_get_shared_dpll(intel_crtc); |
6659 | if (pll == NULL) { |
6660 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n" , |
6661 | pipe_name(pipe)); |
6662 | return -EINVAL; |
6663 | } |
6664 | } else |
6665 | intel_put_shared_dpll(intel_crtc); |
6666 | |
6667 | if (intel_crtc->config.has_dp_encoder) |
6668 | intel_dp_set_m_n(intel_crtc); |
6669 | |
6670 | if (is_lvds && has_reduced_clock && i915.powersave) |
6671 | intel_crtc->lowfreq_avail = true; |
6672 | else |
6673 | intel_crtc->lowfreq_avail = false; |
6674 | |
6675 | intel_set_pipe_timings(intel_crtc); |
6676 | |
6677 | if (intel_crtc->config.has_pch_encoder) { |
6678 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6679 | &intel_crtc->config.fdi_m_n); |
6680 | } |
6681 | |
6682 | ironlake_set_pipeconf(crtc); |
6683 | |
6684 | /* Set up the display plane register */ |
6685 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
6686 | POSTING_READ(DSPCNTR(plane)); |
6687 | |
6688 | ret = intel_pipe_set_base(crtc, x, y, fb); |
6689 | |
6690 | return ret; |
6691 | } |
6692 | |
6693 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
6694 | struct intel_link_m_n *m_n) |
6695 | { |
6696 | struct drm_device *dev = crtc->base.dev; |
6697 | struct drm_i915_private *dev_priv = dev->dev_private; |
6698 | enum i915_pipe pipe = crtc->pipe; |
6699 | |
6700 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); |
6701 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); |
6702 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) |
6703 | & ~TU_SIZE_MASK; |
6704 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); |
6705 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) |
6706 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
6707 | } |
6708 | |
6709 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, |
6710 | enum transcoder transcoder, |
6711 | struct intel_link_m_n *m_n) |
6712 | { |
6713 | struct drm_device *dev = crtc->base.dev; |
6714 | struct drm_i915_private *dev_priv = dev->dev_private; |
6715 | enum i915_pipe pipe = crtc->pipe; |
6716 | |
6717 | if (INTEL_INFO(dev)->gen >= 5) { |
6718 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
6719 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
6720 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
6721 | & ~TU_SIZE_MASK; |
6722 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
6723 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
6724 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
6725 | } else { |
6726 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); |
6727 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); |
6728 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) |
6729 | & ~TU_SIZE_MASK; |
6730 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); |
6731 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) |
6732 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
6733 | } |
6734 | } |
6735 | |
6736 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
6737 | struct intel_crtc_config *pipe_config) |
6738 | { |
6739 | if (crtc->config.has_pch_encoder) |
6740 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
6741 | else |
6742 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
6743 | &pipe_config->dp_m_n); |
6744 | } |
6745 | |
6746 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
6747 | struct intel_crtc_config *pipe_config) |
6748 | { |
6749 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
6750 | &pipe_config->fdi_m_n); |
6751 | } |
6752 | |
6753 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
6754 | struct intel_crtc_config *pipe_config) |
6755 | { |
6756 | struct drm_device *dev = crtc->base.dev; |
6757 | struct drm_i915_private *dev_priv = dev->dev_private; |
6758 | uint32_t tmp; |
6759 | |
6760 | tmp = I915_READ(PF_CTL(crtc->pipe)); |
6761 | |
6762 | if (tmp & PF_ENABLE) { |
6763 | pipe_config->pch_pfit.enabled = true; |
6764 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
6765 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); |
6766 | |
6767 | /* We currently do not free assignements of panel fitters on |
6768 | * ivb/hsw (since we don't use the higher upscaling modes which |
6769 | * differentiates them) so just WARN about this case for now. */ |
6770 | if (IS_GEN7(dev)) { |
6771 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
6772 | PF_PIPE_SEL_IVB(crtc->pipe)); |
6773 | } |
6774 | } |
6775 | } |
6776 | |
6777 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
6778 | struct intel_plane_config *plane_config) |
6779 | { |
6780 | struct drm_device *dev = crtc->base.dev; |
6781 | struct drm_i915_private *dev_priv = dev->dev_private; |
6782 | u32 val, base; |
6783 | int pipe = crtc->pipe, plane = crtc->plane; |
6784 | int fourcc, pixel_format; |
6785 | int aligned_height; |
6786 | |
6787 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6788 | if (!crtc->base.primary->fb) { |
6789 | DRM_DEBUG_KMS("failed to alloc fb\n" ); |
6790 | return; |
6791 | } |
6792 | |
6793 | val = I915_READ(DSPCNTR(plane)); |
6794 | |
6795 | if (INTEL_INFO(dev)->gen >= 4) |
6796 | if (val & DISPPLANE_TILED) |
6797 | plane_config->tiled = true; |
6798 | |
6799 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
6800 | fourcc = intel_format_to_fourcc(pixel_format); |
6801 | crtc->base.primary->fb->pixel_format = fourcc; |
6802 | crtc->base.primary->fb->bits_per_pixel = |
6803 | drm_format_plane_cpp(fourcc, 0) * 8; |
6804 | |
6805 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; |
6806 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
6807 | (void)I915_READ(DSPOFFSET(plane)); |
6808 | } else { |
6809 | if (plane_config->tiled) |
6810 | (void)I915_READ(DSPTILEOFF(plane)); |
6811 | else |
6812 | (void)I915_READ(DSPLINOFF(plane)); |
6813 | } |
6814 | plane_config->base = base; |
6815 | |
6816 | val = I915_READ(PIPESRC(pipe)); |
6817 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
6818 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; |
6819 | |
6820 | val = I915_READ(DSPSTRIDE(pipe)); |
6821 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
6822 | |
6823 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
6824 | plane_config->tiled); |
6825 | |
6826 | #ifdef __NetBSD__ /* XXX ALIGN means something else. */ |
6827 | plane_config->size = round_up(crtc->base.primary->fb->pitches[0] * |
6828 | aligned_height, PAGE_SIZE); |
6829 | #else |
6830 | plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] * |
6831 | aligned_height, PAGE_SIZE); |
6832 | #endif |
6833 | |
6834 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , |
6835 | pipe, plane, crtc->base.primary->fb->width, |
6836 | crtc->base.primary->fb->height, |
6837 | crtc->base.primary->fb->bits_per_pixel, base, |
6838 | crtc->base.primary->fb->pitches[0], |
6839 | plane_config->size); |
6840 | } |
6841 | |
6842 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
6843 | struct intel_crtc_config *pipe_config) |
6844 | { |
6845 | struct drm_device *dev = crtc->base.dev; |
6846 | struct drm_i915_private *dev_priv = dev->dev_private; |
6847 | uint32_t tmp; |
6848 | |
6849 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
6850 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6851 | |
6852 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6853 | if (!(tmp & PIPECONF_ENABLE)) |
6854 | return false; |
6855 | |
6856 | switch (tmp & PIPECONF_BPC_MASK) { |
6857 | case PIPECONF_6BPC: |
6858 | pipe_config->pipe_bpp = 18; |
6859 | break; |
6860 | case PIPECONF_8BPC: |
6861 | pipe_config->pipe_bpp = 24; |
6862 | break; |
6863 | case PIPECONF_10BPC: |
6864 | pipe_config->pipe_bpp = 30; |
6865 | break; |
6866 | case PIPECONF_12BPC: |
6867 | pipe_config->pipe_bpp = 36; |
6868 | break; |
6869 | default: |
6870 | break; |
6871 | } |
6872 | |
6873 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
6874 | struct intel_shared_dpll *pll; |
6875 | |
6876 | pipe_config->has_pch_encoder = true; |
6877 | |
6878 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
6879 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
6880 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
6881 | |
6882 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
6883 | |
6884 | if (HAS_PCH_IBX(dev_priv->dev)) { |
6885 | pipe_config->shared_dpll = |
6886 | (enum intel_dpll_id) crtc->pipe; |
6887 | } else { |
6888 | tmp = I915_READ(PCH_DPLL_SEL); |
6889 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
6890 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; |
6891 | else |
6892 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; |
6893 | } |
6894 | |
6895 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
6896 | |
6897 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
6898 | &pipe_config->dpll_hw_state)); |
6899 | |
6900 | tmp = pipe_config->dpll_hw_state.dpll; |
6901 | pipe_config->pixel_multiplier = |
6902 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
6903 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
6904 | |
6905 | ironlake_pch_clock_get(crtc, pipe_config); |
6906 | } else { |
6907 | pipe_config->pixel_multiplier = 1; |
6908 | } |
6909 | |
6910 | intel_get_pipe_timings(crtc, pipe_config); |
6911 | |
6912 | ironlake_get_pfit_config(crtc, pipe_config); |
6913 | |
6914 | return true; |
6915 | } |
6916 | |
6917 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
6918 | { |
6919 | struct drm_device *dev = dev_priv->dev; |
6920 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; |
6921 | struct intel_crtc *crtc; |
6922 | unsigned long irqflags; |
6923 | uint32_t val; |
6924 | |
6925 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
6926 | WARN(crtc->active, "CRTC for pipe %c enabled\n" , |
6927 | pipe_name(crtc->pipe)); |
6928 | |
6929 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n" ); |
6930 | WARN(plls->spll_refcount, "SPLL enabled\n" ); |
6931 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n" ); |
6932 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n" ); |
6933 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n" ); |
6934 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
6935 | "CPU PWM1 enabled\n" ); |
6936 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
6937 | "CPU PWM2 enabled\n" ); |
6938 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
6939 | "PCH PWM1 enabled\n" ); |
6940 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
6941 | "Utility pin enabled\n" ); |
6942 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n" ); |
6943 | |
6944 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
6945 | val = I915_READ(DEIMR); |
6946 | WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff, |
6947 | "Unexpected DEIMR bits enabled: 0x%x\n" , val); |
6948 | val = I915_READ(SDEIMR); |
6949 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
6950 | "Unexpected SDEIMR bits enabled: 0x%x\n" , val); |
6951 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
6952 | } |
6953 | |
6954 | /* |
6955 | * This function implements pieces of two sequences from BSpec: |
6956 | * - Sequence for display software to disable LCPLL |
6957 | * - Sequence for display software to allow package C8+ |
6958 | * The steps implemented here are just the steps that actually touch the LCPLL |
6959 | * register. Callers should take care of disabling all the display engine |
6960 | * functions, doing the mode unset, fixing interrupts, etc. |
6961 | */ |
6962 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6963 | bool switch_to_fclk, bool allow_power_down) |
6964 | { |
6965 | uint32_t val; |
6966 | |
6967 | assert_can_disable_lcpll(dev_priv); |
6968 | |
6969 | val = I915_READ(LCPLL_CTL); |
6970 | |
6971 | if (switch_to_fclk) { |
6972 | val |= LCPLL_CD_SOURCE_FCLK; |
6973 | I915_WRITE(LCPLL_CTL, val); |
6974 | |
6975 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
6976 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
6977 | DRM_ERROR("Switching to FCLK failed\n" ); |
6978 | |
6979 | val = I915_READ(LCPLL_CTL); |
6980 | } |
6981 | |
6982 | val |= LCPLL_PLL_DISABLE; |
6983 | I915_WRITE(LCPLL_CTL, val); |
6984 | POSTING_READ(LCPLL_CTL); |
6985 | |
6986 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
6987 | DRM_ERROR("LCPLL still locked\n" ); |
6988 | |
6989 | val = I915_READ(D_COMP); |
6990 | val |= D_COMP_COMP_DISABLE; |
6991 | mutex_lock(&dev_priv->rps.hw_lock); |
6992 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) |
6993 | DRM_ERROR("Failed to disable D_COMP\n" ); |
6994 | mutex_unlock(&dev_priv->rps.hw_lock); |
6995 | POSTING_READ(D_COMP); |
6996 | ndelay(100); |
6997 | |
6998 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) |
6999 | DRM_ERROR("D_COMP RCOMP still in progress\n" ); |
7000 | |
7001 | if (allow_power_down) { |
7002 | val = I915_READ(LCPLL_CTL); |
7003 | val |= LCPLL_POWER_DOWN_ALLOW; |
7004 | I915_WRITE(LCPLL_CTL, val); |
7005 | POSTING_READ(LCPLL_CTL); |
7006 | } |
7007 | } |
7008 | |
7009 | /* |
7010 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
7011 | * source. |
7012 | */ |
7013 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
7014 | { |
7015 | uint32_t val; |
7016 | unsigned long irqflags; |
7017 | |
7018 | val = I915_READ(LCPLL_CTL); |
7019 | |
7020 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
7021 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
7022 | return; |
7023 | |
7024 | /* |
7025 | * Make sure we're not on PC8 state before disabling PC8, otherwise |
7026 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. |
7027 | * |
7028 | * The other problem is that hsw_restore_lcpll() is called as part of |
7029 | * the runtime PM resume sequence, so we can't just call |
7030 | * gen6_gt_force_wake_get() because that function calls |
7031 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount |
7032 | * while we are on the resume sequence. So to solve this problem we have |
7033 | * to call special forcewake code that doesn't touch runtime PM and |
7034 | * doesn't enable the forcewake delayed work. |
7035 | */ |
7036 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
7037 | if (dev_priv->uncore.forcewake_count++ == 0) |
7038 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
7039 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
7040 | |
7041 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7042 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
7043 | I915_WRITE(LCPLL_CTL, val); |
7044 | POSTING_READ(LCPLL_CTL); |
7045 | } |
7046 | |
7047 | val = I915_READ(D_COMP); |
7048 | val |= D_COMP_COMP_FORCE; |
7049 | val &= ~D_COMP_COMP_DISABLE; |
7050 | mutex_lock(&dev_priv->rps.hw_lock); |
7051 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) |
7052 | DRM_ERROR("Failed to enable D_COMP\n" ); |
7053 | mutex_unlock(&dev_priv->rps.hw_lock); |
7054 | POSTING_READ(D_COMP); |
7055 | |
7056 | val = I915_READ(LCPLL_CTL); |
7057 | val &= ~LCPLL_PLL_DISABLE; |
7058 | I915_WRITE(LCPLL_CTL, val); |
7059 | |
7060 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) |
7061 | DRM_ERROR("LCPLL not locked yet\n" ); |
7062 | |
7063 | if (val & LCPLL_CD_SOURCE_FCLK) { |
7064 | val = I915_READ(LCPLL_CTL); |
7065 | val &= ~LCPLL_CD_SOURCE_FCLK; |
7066 | I915_WRITE(LCPLL_CTL, val); |
7067 | |
7068 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
7069 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
7070 | DRM_ERROR("Switching back to LCPLL failed\n" ); |
7071 | } |
7072 | |
7073 | /* See the big comment above. */ |
7074 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
7075 | if (--dev_priv->uncore.forcewake_count == 0) |
7076 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
7077 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
7078 | } |
7079 | |
7080 | /* |
7081 | * Package states C8 and deeper are really deep PC states that can only be |
7082 | * reached when all the devices on the system allow it, so even if the graphics |
7083 | * device allows PC8+, it doesn't mean the system will actually get to these |
7084 | * states. Our driver only allows PC8+ when going into runtime PM. |
7085 | * |
7086 | * The requirements for PC8+ are that all the outputs are disabled, the power |
7087 | * well is disabled and most interrupts are disabled, and these are also |
7088 | * requirements for runtime PM. When these conditions are met, we manually do |
7089 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk |
7090 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard |
7091 | * hang the machine. |
7092 | * |
7093 | * When we really reach PC8 or deeper states (not just when we allow it) we lose |
7094 | * the state of some registers, so when we come back from PC8+ we need to |
7095 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't |
7096 | * need to take care of the registers kept by RC6. Notice that this happens even |
7097 | * if we don't put the device in PCI D3 state (which is what currently happens |
7098 | * because of the runtime PM support). |
7099 | * |
7100 | * For more, read "Display Sequences for Package C8" on the hardware |
7101 | * documentation. |
7102 | */ |
7103 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
7104 | { |
7105 | struct drm_device *dev = dev_priv->dev; |
7106 | uint32_t val; |
7107 | |
7108 | WARN_ON(!HAS_PC8(dev)); |
7109 | |
7110 | DRM_DEBUG_KMS("Enabling package C8+\n" ); |
7111 | |
7112 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7113 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
7114 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
7115 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
7116 | } |
7117 | |
7118 | lpt_disable_clkout_dp(dev); |
7119 | hsw_runtime_pm_disable_interrupts(dev); |
7120 | hsw_disable_lcpll(dev_priv, true, true); |
7121 | } |
7122 | |
7123 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
7124 | { |
7125 | struct drm_device *dev = dev_priv->dev; |
7126 | uint32_t val; |
7127 | |
7128 | WARN_ON(!HAS_PC8(dev)); |
7129 | |
7130 | DRM_DEBUG_KMS("Disabling package C8+\n" ); |
7131 | |
7132 | hsw_restore_lcpll(dev_priv); |
7133 | hsw_runtime_pm_restore_interrupts(dev); |
7134 | lpt_init_pch_refclk(dev); |
7135 | |
7136 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7137 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
7138 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
7139 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
7140 | } |
7141 | |
7142 | intel_prepare_ddi(dev); |
7143 | i915_gem_init_swizzling(dev); |
7144 | mutex_lock(&dev_priv->rps.hw_lock); |
7145 | gen6_update_ring_freq(dev); |
7146 | mutex_unlock(&dev_priv->rps.hw_lock); |
7147 | } |
7148 | |
7149 | static void haswell_modeset_global_resources(struct drm_device *dev) |
7150 | { |
7151 | modeset_update_crtc_power_domains(dev); |
7152 | } |
7153 | |
7154 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
7155 | int x, int y, |
7156 | struct drm_framebuffer *fb) |
7157 | { |
7158 | struct drm_device *dev = crtc->dev; |
7159 | struct drm_i915_private *dev_priv = dev->dev_private; |
7160 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7161 | int plane = intel_crtc->plane; |
7162 | int ret; |
7163 | |
7164 | if (!intel_ddi_pll_select(intel_crtc)) |
7165 | return -EINVAL; |
7166 | intel_ddi_pll_enable(intel_crtc); |
7167 | |
7168 | if (intel_crtc->config.has_dp_encoder) |
7169 | intel_dp_set_m_n(intel_crtc); |
7170 | |
7171 | intel_crtc->lowfreq_avail = false; |
7172 | |
7173 | intel_set_pipe_timings(intel_crtc); |
7174 | |
7175 | if (intel_crtc->config.has_pch_encoder) { |
7176 | intel_cpu_transcoder_set_m_n(intel_crtc, |
7177 | &intel_crtc->config.fdi_m_n); |
7178 | } |
7179 | |
7180 | haswell_set_pipeconf(crtc); |
7181 | |
7182 | intel_set_pipe_csc(crtc); |
7183 | |
7184 | /* Set up the display plane register */ |
7185 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
7186 | POSTING_READ(DSPCNTR(plane)); |
7187 | |
7188 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7189 | |
7190 | return ret; |
7191 | } |
7192 | |
7193 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
7194 | struct intel_crtc_config *pipe_config) |
7195 | { |
7196 | struct drm_device *dev = crtc->base.dev; |
7197 | struct drm_i915_private *dev_priv = dev->dev_private; |
7198 | enum intel_display_power_domain pfit_domain; |
7199 | uint32_t tmp; |
7200 | |
7201 | if (!intel_display_power_enabled(dev_priv, |
7202 | POWER_DOMAIN_PIPE(crtc->pipe))) |
7203 | return false; |
7204 | |
7205 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
7206 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7207 | |
7208 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7209 | if (tmp & TRANS_DDI_FUNC_ENABLE) { |
7210 | enum i915_pipe trans_edp_pipe; |
7211 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
7212 | default: |
7213 | WARN(1, "unknown pipe linked to edp transcoder\n" ); |
7214 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
7215 | case TRANS_DDI_EDP_INPUT_A_ON: |
7216 | trans_edp_pipe = PIPE_A; |
7217 | break; |
7218 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
7219 | trans_edp_pipe = PIPE_B; |
7220 | break; |
7221 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
7222 | trans_edp_pipe = PIPE_C; |
7223 | break; |
7224 | } |
7225 | |
7226 | if (trans_edp_pipe == crtc->pipe) |
7227 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
7228 | } |
7229 | |
7230 | if (!intel_display_power_enabled(dev_priv, |
7231 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
7232 | return false; |
7233 | |
7234 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
7235 | if (!(tmp & PIPECONF_ENABLE)) |
7236 | return false; |
7237 | |
7238 | /* |
7239 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
7240 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
7241 | * the PCH transcoder is on. |
7242 | */ |
7243 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
7244 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
7245 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
7246 | pipe_config->has_pch_encoder = true; |
7247 | |
7248 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
7249 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
7250 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
7251 | |
7252 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
7253 | } |
7254 | |
7255 | intel_get_pipe_timings(crtc, pipe_config); |
7256 | |
7257 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
7258 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
7259 | ironlake_get_pfit_config(crtc, pipe_config); |
7260 | |
7261 | if (IS_HASWELL(dev)) |
7262 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
7263 | (I915_READ(IPS_CTL) & IPS_ENABLE); |
7264 | |
7265 | pipe_config->pixel_multiplier = 1; |
7266 | |
7267 | return true; |
7268 | } |
7269 | |
7270 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
7271 | int x, int y, |
7272 | struct drm_framebuffer *fb) |
7273 | { |
7274 | struct drm_device *dev = crtc->dev; |
7275 | struct drm_i915_private *dev_priv = dev->dev_private; |
7276 | struct intel_encoder *encoder; |
7277 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7278 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
7279 | int pipe = intel_crtc->pipe; |
7280 | int ret; |
7281 | |
7282 | drm_vblank_pre_modeset(dev, pipe); |
7283 | |
7284 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
7285 | |
7286 | drm_vblank_post_modeset(dev, pipe); |
7287 | |
7288 | if (ret != 0) |
7289 | return ret; |
7290 | |
7291 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
7292 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n" , |
7293 | encoder->base.base.id, |
7294 | drm_get_encoder_name(&encoder->base), |
7295 | mode->base.id, mode->name); |
7296 | encoder->mode_set(encoder); |
7297 | } |
7298 | |
7299 | return 0; |
7300 | } |
7301 | |
7302 | static struct { |
7303 | int clock; |
7304 | u32 config; |
7305 | } hdmi_audio_clock[] = { |
7306 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
7307 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
7308 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, |
7309 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
7310 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
7311 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
7312 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, |
7313 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
7314 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
7315 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
7316 | }; |
7317 | |
7318 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
7319 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) |
7320 | { |
7321 | int i; |
7322 | |
7323 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { |
7324 | if (mode->clock == hdmi_audio_clock[i].clock) |
7325 | break; |
7326 | } |
7327 | |
7328 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { |
7329 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n" , mode->clock); |
7330 | i = 1; |
7331 | } |
7332 | |
7333 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n" , |
7334 | hdmi_audio_clock[i].clock, |
7335 | hdmi_audio_clock[i].config); |
7336 | |
7337 | return hdmi_audio_clock[i].config; |
7338 | } |
7339 | |
7340 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7341 | int reg_eldv, uint32_t bits_eldv, |
7342 | int reg_elda, uint32_t bits_elda, |
7343 | int reg_edid) |
7344 | { |
7345 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7346 | uint8_t *eld = connector->eld; |
7347 | uint32_t i; |
7348 | |
7349 | i = I915_READ(reg_eldv); |
7350 | i &= bits_eldv; |
7351 | |
7352 | if (!eld[0]) |
7353 | return !i; |
7354 | |
7355 | if (!i) |
7356 | return false; |
7357 | |
7358 | i = I915_READ(reg_elda); |
7359 | i &= ~bits_elda; |
7360 | I915_WRITE(reg_elda, i); |
7361 | |
7362 | for (i = 0; i < eld[2]; i++) |
7363 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
7364 | return false; |
7365 | |
7366 | return true; |
7367 | } |
7368 | |
7369 | static void g4x_write_eld(struct drm_connector *connector, |
7370 | struct drm_crtc *crtc, |
7371 | struct drm_display_mode *mode) |
7372 | { |
7373 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7374 | uint8_t *eld = connector->eld; |
7375 | uint32_t eldv; |
7376 | uint32_t len; |
7377 | uint32_t i; |
7378 | |
7379 | i = I915_READ(G4X_AUD_VID_DID); |
7380 | |
7381 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
7382 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
7383 | else |
7384 | eldv = G4X_ELDV_DEVCTG; |
7385 | |
7386 | if (intel_eld_uptodate(connector, |
7387 | G4X_AUD_CNTL_ST, eldv, |
7388 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
7389 | G4X_HDMIW_HDMIEDID)) |
7390 | return; |
7391 | |
7392 | i = I915_READ(G4X_AUD_CNTL_ST); |
7393 | i &= ~(eldv | G4X_ELD_ADDR); |
7394 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
7395 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
7396 | |
7397 | if (!eld[0]) |
7398 | return; |
7399 | |
7400 | len = min_t(uint8_t, eld[2], len); |
7401 | DRM_DEBUG_DRIVER("ELD size %d\n" , len); |
7402 | for (i = 0; i < len; i++) |
7403 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
7404 | |
7405 | i = I915_READ(G4X_AUD_CNTL_ST); |
7406 | i |= eldv; |
7407 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
7408 | } |
7409 | |
7410 | static void haswell_write_eld(struct drm_connector *connector, |
7411 | struct drm_crtc *crtc, |
7412 | struct drm_display_mode *mode) |
7413 | { |
7414 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7415 | uint8_t *eld = connector->eld; |
7416 | struct drm_device *dev = crtc->dev; |
7417 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7418 | uint32_t eldv; |
7419 | uint32_t i; |
7420 | int len; |
7421 | int pipe = to_intel_crtc(crtc)->pipe; |
7422 | int tmp; |
7423 | |
7424 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
7425 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
7426 | int aud_config = HSW_AUD_CFG(pipe); |
7427 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
7428 | |
7429 | |
7430 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n" ); |
7431 | |
7432 | /* Audio output enable */ |
7433 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n" ); |
7434 | tmp = I915_READ(aud_cntrl_st2); |
7435 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
7436 | I915_WRITE(aud_cntrl_st2, tmp); |
7437 | |
7438 | /* Wait for 1 vertical blank */ |
7439 | intel_wait_for_vblank(dev, pipe); |
7440 | |
7441 | /* Set ELD valid state */ |
7442 | tmp = I915_READ(aud_cntrl_st2); |
7443 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n" , tmp); |
7444 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7445 | I915_WRITE(aud_cntrl_st2, tmp); |
7446 | tmp = I915_READ(aud_cntrl_st2); |
7447 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n" , tmp); |
7448 | |
7449 | /* Enable HDMI mode */ |
7450 | tmp = I915_READ(aud_config); |
7451 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n" , tmp); |
7452 | /* clear N_programing_enable and N_value_index */ |
7453 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); |
7454 | I915_WRITE(aud_config, tmp); |
7455 | |
7456 | DRM_DEBUG_DRIVER("ELD on pipe %c\n" , pipe_name(pipe)); |
7457 | |
7458 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
7459 | intel_crtc->eld_vld = true; |
7460 | |
7461 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7462 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n" ); |
7463 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
7464 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
7465 | } else { |
7466 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); |
7467 | } |
7468 | |
7469 | if (intel_eld_uptodate(connector, |
7470 | aud_cntrl_st2, eldv, |
7471 | aud_cntl_st, IBX_ELD_ADDRESS, |
7472 | hdmiw_hdmiedid)) |
7473 | return; |
7474 | |
7475 | i = I915_READ(aud_cntrl_st2); |
7476 | i &= ~eldv; |
7477 | I915_WRITE(aud_cntrl_st2, i); |
7478 | |
7479 | if (!eld[0]) |
7480 | return; |
7481 | |
7482 | i = I915_READ(aud_cntl_st); |
7483 | i &= ~IBX_ELD_ADDRESS; |
7484 | I915_WRITE(aud_cntl_st, i); |
7485 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
7486 | DRM_DEBUG_DRIVER("port num:%d\n" , i); |
7487 | |
7488 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
7489 | DRM_DEBUG_DRIVER("ELD size %d\n" , len); |
7490 | for (i = 0; i < len; i++) |
7491 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
7492 | |
7493 | i = I915_READ(aud_cntrl_st2); |
7494 | i |= eldv; |
7495 | I915_WRITE(aud_cntrl_st2, i); |
7496 | |
7497 | } |
7498 | |
7499 | static void ironlake_write_eld(struct drm_connector *connector, |
7500 | struct drm_crtc *crtc, |
7501 | struct drm_display_mode *mode) |
7502 | { |
7503 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7504 | uint8_t *eld = connector->eld; |
7505 | uint32_t eldv; |
7506 | uint32_t i; |
7507 | int len; |
7508 | int hdmiw_hdmiedid; |
7509 | int aud_config; |
7510 | int aud_cntl_st; |
7511 | int aud_cntrl_st2; |
7512 | int pipe = to_intel_crtc(crtc)->pipe; |
7513 | |
7514 | if (HAS_PCH_IBX(connector->dev)) { |
7515 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7516 | aud_config = IBX_AUD_CFG(pipe); |
7517 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
7518 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
7519 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7520 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); |
7521 | aud_config = VLV_AUD_CFG(pipe); |
7522 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); |
7523 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; |
7524 | } else { |
7525 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7526 | aud_config = CPT_AUD_CFG(pipe); |
7527 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
7528 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
7529 | } |
7530 | |
7531 | DRM_DEBUG_DRIVER("ELD on pipe %c\n" , pipe_name(pipe)); |
7532 | |
7533 | if (IS_VALLEYVIEW(connector->dev)) { |
7534 | struct intel_encoder *intel_encoder; |
7535 | struct intel_digital_port *intel_dig_port; |
7536 | |
7537 | intel_encoder = intel_attached_encoder(connector); |
7538 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
7539 | i = intel_dig_port->port; |
7540 | } else { |
7541 | i = I915_READ(aud_cntl_st); |
7542 | i = (i >> 29) & DIP_PORT_SEL_MASK; |
7543 | /* DIP_Port_Select, 0x1 = PortB */ |
7544 | } |
7545 | |
7546 | if (!i) { |
7547 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n" ); |
7548 | /* operate blindly on all ports */ |
7549 | eldv = IBX_ELD_VALIDB; |
7550 | eldv |= IBX_ELD_VALIDB << 4; |
7551 | eldv |= IBX_ELD_VALIDB << 8; |
7552 | } else { |
7553 | DRM_DEBUG_DRIVER("ELD on port %c\n" , port_name(i)); |
7554 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
7555 | } |
7556 | |
7557 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7558 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n" ); |
7559 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
7560 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
7561 | } else { |
7562 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); |
7563 | } |
7564 | |
7565 | if (intel_eld_uptodate(connector, |
7566 | aud_cntrl_st2, eldv, |
7567 | aud_cntl_st, IBX_ELD_ADDRESS, |
7568 | hdmiw_hdmiedid)) |
7569 | return; |
7570 | |
7571 | i = I915_READ(aud_cntrl_st2); |
7572 | i &= ~eldv; |
7573 | I915_WRITE(aud_cntrl_st2, i); |
7574 | |
7575 | if (!eld[0]) |
7576 | return; |
7577 | |
7578 | i = I915_READ(aud_cntl_st); |
7579 | i &= ~IBX_ELD_ADDRESS; |
7580 | I915_WRITE(aud_cntl_st, i); |
7581 | |
7582 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
7583 | DRM_DEBUG_DRIVER("ELD size %d\n" , len); |
7584 | for (i = 0; i < len; i++) |
7585 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
7586 | |
7587 | i = I915_READ(aud_cntrl_st2); |
7588 | i |= eldv; |
7589 | I915_WRITE(aud_cntrl_st2, i); |
7590 | } |
7591 | |
7592 | void intel_write_eld(struct drm_encoder *encoder, |
7593 | struct drm_display_mode *mode) |
7594 | { |
7595 | struct drm_crtc *crtc = encoder->crtc; |
7596 | struct drm_connector *connector; |
7597 | struct drm_device *dev = encoder->dev; |
7598 | struct drm_i915_private *dev_priv = dev->dev_private; |
7599 | |
7600 | connector = drm_select_eld(encoder, mode); |
7601 | if (!connector) |
7602 | return; |
7603 | |
7604 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n" , |
7605 | connector->base.id, |
7606 | drm_get_connector_name(connector), |
7607 | connector->encoder->base.id, |
7608 | drm_get_encoder_name(connector->encoder)); |
7609 | |
7610 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
7611 | |
7612 | if (dev_priv->display.write_eld) |
7613 | dev_priv->display.write_eld(connector, crtc, mode); |
7614 | } |
7615 | |
7616 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7617 | { |
7618 | struct drm_device *dev = crtc->dev; |
7619 | struct drm_i915_private *dev_priv = dev->dev_private; |
7620 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7621 | bool visible = base != 0; |
7622 | u32 cntl; |
7623 | |
7624 | if (intel_crtc->cursor_visible == visible) |
7625 | return; |
7626 | |
7627 | cntl = I915_READ(_CURACNTR); |
7628 | if (visible) { |
7629 | /* On these chipsets we can only modify the base whilst |
7630 | * the cursor is disabled. |
7631 | */ |
7632 | I915_WRITE(_CURABASE, base); |
7633 | |
7634 | cntl &= ~(CURSOR_FORMAT_MASK); |
7635 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
7636 | cntl |= CURSOR_ENABLE | |
7637 | CURSOR_GAMMA_ENABLE | |
7638 | CURSOR_FORMAT_ARGB; |
7639 | } else |
7640 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
7641 | I915_WRITE(_CURACNTR, cntl); |
7642 | |
7643 | intel_crtc->cursor_visible = visible; |
7644 | } |
7645 | |
7646 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
7647 | { |
7648 | struct drm_device *dev = crtc->dev; |
7649 | struct drm_i915_private *dev_priv = dev->dev_private; |
7650 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7651 | int pipe = intel_crtc->pipe; |
7652 | bool visible = base != 0; |
7653 | |
7654 | if (intel_crtc->cursor_visible != visible) { |
7655 | int16_t width = intel_crtc->cursor_width; |
7656 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
7657 | if (base) { |
7658 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
7659 | cntl |= MCURSOR_GAMMA_ENABLE; |
7660 | |
7661 | switch (width) { |
7662 | case 64: |
7663 | cntl |= CURSOR_MODE_64_ARGB_AX; |
7664 | break; |
7665 | case 128: |
7666 | cntl |= CURSOR_MODE_128_ARGB_AX; |
7667 | break; |
7668 | case 256: |
7669 | cntl |= CURSOR_MODE_256_ARGB_AX; |
7670 | break; |
7671 | default: |
7672 | WARN_ON(1); |
7673 | return; |
7674 | } |
7675 | cntl |= pipe << 28; /* Connect to correct pipe */ |
7676 | } else { |
7677 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
7678 | cntl |= CURSOR_MODE_DISABLE; |
7679 | } |
7680 | I915_WRITE(CURCNTR(pipe), cntl); |
7681 | |
7682 | intel_crtc->cursor_visible = visible; |
7683 | } |
7684 | /* and commit changes on next vblank */ |
7685 | POSTING_READ(CURCNTR(pipe)); |
7686 | I915_WRITE(CURBASE(pipe), base); |
7687 | POSTING_READ(CURBASE(pipe)); |
7688 | } |
7689 | |
7690 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7691 | { |
7692 | struct drm_device *dev = crtc->dev; |
7693 | struct drm_i915_private *dev_priv = dev->dev_private; |
7694 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7695 | int pipe = intel_crtc->pipe; |
7696 | bool visible = base != 0; |
7697 | |
7698 | if (intel_crtc->cursor_visible != visible) { |
7699 | int16_t width = intel_crtc->cursor_width; |
7700 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
7701 | if (base) { |
7702 | cntl &= ~CURSOR_MODE; |
7703 | cntl |= MCURSOR_GAMMA_ENABLE; |
7704 | switch (width) { |
7705 | case 64: |
7706 | cntl |= CURSOR_MODE_64_ARGB_AX; |
7707 | break; |
7708 | case 128: |
7709 | cntl |= CURSOR_MODE_128_ARGB_AX; |
7710 | break; |
7711 | case 256: |
7712 | cntl |= CURSOR_MODE_256_ARGB_AX; |
7713 | break; |
7714 | default: |
7715 | WARN_ON(1); |
7716 | return; |
7717 | } |
7718 | } else { |
7719 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
7720 | cntl |= CURSOR_MODE_DISABLE; |
7721 | } |
7722 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
7723 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
7724 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
7725 | } |
7726 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
7727 | |
7728 | intel_crtc->cursor_visible = visible; |
7729 | } |
7730 | /* and commit changes on next vblank */ |
7731 | POSTING_READ(CURCNTR_IVB(pipe)); |
7732 | I915_WRITE(CURBASE_IVB(pipe), base); |
7733 | POSTING_READ(CURBASE_IVB(pipe)); |
7734 | } |
7735 | |
7736 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
7737 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7738 | bool on) |
7739 | { |
7740 | struct drm_device *dev = crtc->dev; |
7741 | struct drm_i915_private *dev_priv = dev->dev_private; |
7742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7743 | int pipe = intel_crtc->pipe; |
7744 | int x = intel_crtc->cursor_x; |
7745 | int y = intel_crtc->cursor_y; |
7746 | u32 base = 0, pos = 0; |
7747 | bool visible; |
7748 | |
7749 | if (on) |
7750 | base = intel_crtc->cursor_addr; |
7751 | |
7752 | if (x >= intel_crtc->config.pipe_src_w) |
7753 | base = 0; |
7754 | |
7755 | if (y >= intel_crtc->config.pipe_src_h) |
7756 | base = 0; |
7757 | |
7758 | if (x < 0) { |
7759 | if (x + intel_crtc->cursor_width <= 0) |
7760 | base = 0; |
7761 | |
7762 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
7763 | x = -x; |
7764 | } |
7765 | pos |= x << CURSOR_X_SHIFT; |
7766 | |
7767 | if (y < 0) { |
7768 | if (y + intel_crtc->cursor_height <= 0) |
7769 | base = 0; |
7770 | |
7771 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
7772 | y = -y; |
7773 | } |
7774 | pos |= y << CURSOR_Y_SHIFT; |
7775 | |
7776 | visible = base != 0; |
7777 | if (!visible && !intel_crtc->cursor_visible) |
7778 | return; |
7779 | |
7780 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
7781 | I915_WRITE(CURPOS_IVB(pipe), pos); |
7782 | ivb_update_cursor(crtc, base); |
7783 | } else { |
7784 | I915_WRITE(CURPOS(pipe), pos); |
7785 | if (IS_845G(dev) || IS_I865G(dev)) |
7786 | i845_update_cursor(crtc, base); |
7787 | else |
7788 | i9xx_update_cursor(crtc, base); |
7789 | } |
7790 | } |
7791 | |
7792 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
7793 | struct drm_file *file, |
7794 | uint32_t handle, |
7795 | uint32_t width, uint32_t height) |
7796 | { |
7797 | struct drm_device *dev = crtc->dev; |
7798 | struct drm_i915_private *dev_priv = dev->dev_private; |
7799 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7800 | struct drm_gem_object *gobj; |
7801 | struct drm_i915_gem_object *obj; |
7802 | unsigned old_width; |
7803 | uint32_t addr; |
7804 | int ret; |
7805 | |
7806 | /* if we want to turn off the cursor ignore width and height */ |
7807 | if (!handle) { |
7808 | DRM_DEBUG_KMS("cursor off\n" ); |
7809 | addr = 0; |
7810 | obj = NULL; |
7811 | mutex_lock(&dev->struct_mutex); |
7812 | goto finish; |
7813 | } |
7814 | |
7815 | /* Check for which cursor types we support */ |
7816 | if (!((width == 64 && height == 64) || |
7817 | (width == 128 && height == 128 && !IS_GEN2(dev)) || |
7818 | (width == 256 && height == 256 && !IS_GEN2(dev)))) { |
7819 | DRM_DEBUG("Cursor dimension not supported\n" ); |
7820 | return -EINVAL; |
7821 | } |
7822 | |
7823 | gobj = drm_gem_object_lookup(dev, file, handle); |
7824 | if (gobj == NULL) |
7825 | return -ENOENT; |
7826 | obj = to_intel_bo(gobj); |
7827 | |
7828 | if (obj->base.size < width * height * 4) { |
7829 | DRM_DEBUG_KMS("buffer is to small\n" ); |
7830 | ret = -ENOMEM; |
7831 | goto fail; |
7832 | } |
7833 | |
7834 | /* we only need to pin inside GTT if cursor is non-phy */ |
7835 | mutex_lock(&dev->struct_mutex); |
7836 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
7837 | unsigned alignment; |
7838 | |
7839 | if (obj->tiling_mode) { |
7840 | DRM_DEBUG_KMS("cursor cannot be tiled\n" ); |
7841 | ret = -EINVAL; |
7842 | goto fail_locked; |
7843 | } |
7844 | |
7845 | /* Note that the w/a also requires 2 PTE of padding following |
7846 | * the bo. We currently fill all unused PTE with the shadow |
7847 | * page and so we should always have valid PTE following the |
7848 | * cursor preventing the VT-d warning. |
7849 | */ |
7850 | alignment = 0; |
7851 | if (need_vtd_wa(dev)) |
7852 | alignment = 64*1024; |
7853 | |
7854 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
7855 | if (ret) { |
7856 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n" ); |
7857 | goto fail_locked; |
7858 | } |
7859 | |
7860 | ret = i915_gem_object_put_fence(obj); |
7861 | if (ret) { |
7862 | DRM_DEBUG_KMS("failed to release fence for cursor" ); |
7863 | goto fail_unpin; |
7864 | } |
7865 | |
7866 | addr = i915_gem_obj_ggtt_offset(obj); |
7867 | } else { |
7868 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
7869 | ret = i915_gem_object_attach_phys(obj, align); |
7870 | if (ret) { |
7871 | DRM_DEBUG_KMS("failed to attach phys object\n" ); |
7872 | goto fail_locked; |
7873 | } |
7874 | addr = obj->phys_handle->busaddr; |
7875 | } |
7876 | |
7877 | if (IS_GEN2(dev)) |
7878 | I915_WRITE(CURSIZE, (height << 12) | width); |
7879 | |
7880 | finish: |
7881 | if (intel_crtc->cursor_bo) { |
7882 | if (!INTEL_INFO(dev)->cursor_needs_physical) |
7883 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
7884 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
7885 | } |
7886 | |
7887 | mutex_unlock(&dev->struct_mutex); |
7888 | |
7889 | old_width = intel_crtc->cursor_width; |
7890 | |
7891 | intel_crtc->cursor_addr = addr; |
7892 | intel_crtc->cursor_bo = obj; |
7893 | intel_crtc->cursor_width = width; |
7894 | intel_crtc->cursor_height = height; |
7895 | |
7896 | if (intel_crtc->active) { |
7897 | if (old_width != width) |
7898 | intel_update_watermarks(crtc); |
7899 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
7900 | } |
7901 | |
7902 | return 0; |
7903 | fail_unpin: |
7904 | i915_gem_object_unpin_from_display_plane(obj); |
7905 | fail_locked: |
7906 | mutex_unlock(&dev->struct_mutex); |
7907 | fail: |
7908 | drm_gem_object_unreference_unlocked(&obj->base); |
7909 | return ret; |
7910 | } |
7911 | |
7912 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
7913 | { |
7914 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7915 | |
7916 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
7917 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); |
7918 | |
7919 | if (intel_crtc->active) |
7920 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
7921 | |
7922 | return 0; |
7923 | } |
7924 | |
7925 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7926 | u16 *blue, uint32_t start, uint32_t size) |
7927 | { |
7928 | int end = (start + size > 256) ? 256 : start + size, i; |
7929 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7930 | |
7931 | for (i = start; i < end; i++) { |
7932 | intel_crtc->lut_r[i] = red[i] >> 8; |
7933 | intel_crtc->lut_g[i] = green[i] >> 8; |
7934 | intel_crtc->lut_b[i] = blue[i] >> 8; |
7935 | } |
7936 | |
7937 | intel_crtc_load_lut(crtc); |
7938 | } |
7939 | |
7940 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7941 | static struct drm_display_mode load_detect_mode = { |
7942 | DRM_MODE("640x480" , DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
7943 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
7944 | }; |
7945 | |
7946 | struct drm_framebuffer * |
7947 | __intel_framebuffer_create(struct drm_device *dev, |
7948 | struct drm_mode_fb_cmd2 *mode_cmd, |
7949 | struct drm_i915_gem_object *obj) |
7950 | { |
7951 | struct intel_framebuffer *intel_fb; |
7952 | int ret; |
7953 | |
7954 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
7955 | if (!intel_fb) { |
7956 | drm_gem_object_unreference_unlocked(&obj->base); |
7957 | return ERR_PTR(-ENOMEM); |
7958 | } |
7959 | |
7960 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
7961 | if (ret) |
7962 | goto err; |
7963 | |
7964 | return &intel_fb->base; |
7965 | err: |
7966 | drm_gem_object_unreference_unlocked(&obj->base); |
7967 | kfree(intel_fb); |
7968 | |
7969 | return ERR_PTR(ret); |
7970 | } |
7971 | |
7972 | static struct drm_framebuffer * |
7973 | intel_framebuffer_create(struct drm_device *dev, |
7974 | struct drm_mode_fb_cmd2 *mode_cmd, |
7975 | struct drm_i915_gem_object *obj) |
7976 | { |
7977 | struct drm_framebuffer *fb; |
7978 | int ret; |
7979 | |
7980 | ret = i915_mutex_lock_interruptible(dev); |
7981 | if (ret) |
7982 | return ERR_PTR(ret); |
7983 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); |
7984 | mutex_unlock(&dev->struct_mutex); |
7985 | |
7986 | return fb; |
7987 | } |
7988 | |
7989 | static u32 |
7990 | intel_framebuffer_pitch_for_width(int width, int bpp) |
7991 | { |
7992 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
7993 | #ifdef __NetBSD__ /* XXX ALIGN means something else. */ |
7994 | return round_up(pitch, 64); |
7995 | #else |
7996 | return ALIGN(pitch, 64); |
7997 | #endif |
7998 | } |
7999 | |
8000 | static u32 |
8001 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
8002 | { |
8003 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
8004 | #ifdef __NetBSD__ /* XXX ALIGN means something else. */ |
8005 | return round_up(pitch * mode->vdisplay, PAGE_SIZE); |
8006 | #else |
8007 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
8008 | #endif |
8009 | } |
8010 | |
8011 | static struct drm_framebuffer * |
8012 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
8013 | struct drm_display_mode *mode, |
8014 | int depth, int bpp) |
8015 | { |
8016 | struct drm_i915_gem_object *obj; |
8017 | static const struct drm_mode_fb_cmd2 zero_mode_cmd; |
8018 | struct drm_mode_fb_cmd2 mode_cmd = zero_mode_cmd; |
8019 | |
8020 | obj = i915_gem_alloc_object(dev, |
8021 | intel_framebuffer_size_for_mode(mode, bpp)); |
8022 | if (obj == NULL) |
8023 | return ERR_PTR(-ENOMEM); |
8024 | |
8025 | mode_cmd.width = mode->hdisplay; |
8026 | mode_cmd.height = mode->vdisplay; |
8027 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8028 | bpp); |
8029 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
8030 | |
8031 | return intel_framebuffer_create(dev, &mode_cmd, obj); |
8032 | } |
8033 | |
8034 | static struct drm_framebuffer * |
8035 | mode_fits_in_fbdev(struct drm_device *dev, |
8036 | struct drm_display_mode *mode) |
8037 | { |
8038 | #ifdef CONFIG_DRM_I915_FBDEV |
8039 | struct drm_i915_private *dev_priv = dev->dev_private; |
8040 | struct drm_i915_gem_object *obj; |
8041 | struct drm_framebuffer *fb; |
8042 | |
8043 | if (!dev_priv->fbdev) |
8044 | return NULL; |
8045 | |
8046 | if (!dev_priv->fbdev->fb) |
8047 | return NULL; |
8048 | |
8049 | obj = dev_priv->fbdev->fb->obj; |
8050 | BUG_ON(!obj); |
8051 | |
8052 | fb = &dev_priv->fbdev->fb->base; |
8053 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8054 | fb->bits_per_pixel)) |
8055 | return NULL; |
8056 | |
8057 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
8058 | return NULL; |
8059 | |
8060 | return fb; |
8061 | #else |
8062 | return NULL; |
8063 | #endif |
8064 | } |
8065 | |
8066 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
8067 | struct drm_display_mode *mode, |
8068 | struct intel_load_detect_pipe *old) |
8069 | { |
8070 | struct intel_crtc *intel_crtc; |
8071 | struct intel_encoder *intel_encoder = |
8072 | intel_attached_encoder(connector); |
8073 | struct drm_crtc *possible_crtc; |
8074 | struct drm_encoder *encoder = &intel_encoder->base; |
8075 | struct drm_crtc *crtc = NULL; |
8076 | struct drm_device *dev = encoder->dev; |
8077 | struct drm_framebuffer *fb; |
8078 | int i = -1; |
8079 | |
8080 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n" , |
8081 | connector->base.id, drm_get_connector_name(connector), |
8082 | encoder->base.id, drm_get_encoder_name(encoder)); |
8083 | |
8084 | /* |
8085 | * Algorithm gets a little messy: |
8086 | * |
8087 | * - if the connector already has an assigned crtc, use it (but make |
8088 | * sure it's on first) |
8089 | * |
8090 | * - try to find the first unused crtc that can drive this connector, |
8091 | * and use that if we find one |
8092 | */ |
8093 | |
8094 | /* See if we already have a CRTC for this connector */ |
8095 | if (encoder->crtc) { |
8096 | crtc = encoder->crtc; |
8097 | |
8098 | mutex_lock(&crtc->mutex); |
8099 | |
8100 | old->dpms_mode = connector->dpms; |
8101 | old->load_detect_temp = false; |
8102 | |
8103 | /* Make sure the crtc and connector are running */ |
8104 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8105 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
8106 | |
8107 | return true; |
8108 | } |
8109 | |
8110 | /* Find an unused one (if possible) */ |
8111 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
8112 | i++; |
8113 | if (!(encoder->possible_crtcs & (1 << i))) |
8114 | continue; |
8115 | if (!possible_crtc->enabled) { |
8116 | crtc = possible_crtc; |
8117 | break; |
8118 | } |
8119 | } |
8120 | |
8121 | /* |
8122 | * If we didn't find an unused CRTC, don't use any. |
8123 | */ |
8124 | if (!crtc) { |
8125 | DRM_DEBUG_KMS("no pipe available for load-detect\n" ); |
8126 | return false; |
8127 | } |
8128 | |
8129 | mutex_lock(&crtc->mutex); |
8130 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8131 | to_intel_connector(connector)->new_encoder = intel_encoder; |
8132 | |
8133 | intel_crtc = to_intel_crtc(crtc); |
8134 | intel_crtc->new_enabled = true; |
8135 | intel_crtc->new_config = &intel_crtc->config; |
8136 | old->dpms_mode = connector->dpms; |
8137 | old->load_detect_temp = true; |
8138 | old->release_fb = NULL; |
8139 | |
8140 | if (!mode) |
8141 | mode = &load_detect_mode; |
8142 | |
8143 | /* We need a framebuffer large enough to accommodate all accesses |
8144 | * that the plane may generate whilst we perform load detection. |
8145 | * We can not rely on the fbcon either being present (we get called |
8146 | * during its initialisation to detect all boot displays, or it may |
8147 | * not even exist) or that it is large enough to satisfy the |
8148 | * requested mode. |
8149 | */ |
8150 | fb = mode_fits_in_fbdev(dev, mode); |
8151 | if (fb == NULL) { |
8152 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n" ); |
8153 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8154 | old->release_fb = fb; |
8155 | } else |
8156 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n" ); |
8157 | if (IS_ERR(fb)) { |
8158 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n" ); |
8159 | goto fail; |
8160 | } |
8161 | |
8162 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
8163 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n" ); |
8164 | if (old->release_fb) |
8165 | old->release_fb->funcs->destroy(old->release_fb); |
8166 | goto fail; |
8167 | } |
8168 | |
8169 | /* let the connector get through one full cycle before testing */ |
8170 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
8171 | return true; |
8172 | |
8173 | fail: |
8174 | intel_crtc->new_enabled = crtc->enabled; |
8175 | if (intel_crtc->new_enabled) |
8176 | intel_crtc->new_config = &intel_crtc->config; |
8177 | else |
8178 | intel_crtc->new_config = NULL; |
8179 | mutex_unlock(&crtc->mutex); |
8180 | return false; |
8181 | } |
8182 | |
8183 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8184 | struct intel_load_detect_pipe *old) |
8185 | { |
8186 | struct intel_encoder *intel_encoder = |
8187 | intel_attached_encoder(connector); |
8188 | struct drm_encoder *encoder = &intel_encoder->base; |
8189 | struct drm_crtc *crtc = encoder->crtc; |
8190 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8191 | |
8192 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n" , |
8193 | connector->base.id, drm_get_connector_name(connector), |
8194 | encoder->base.id, drm_get_encoder_name(encoder)); |
8195 | |
8196 | if (old->load_detect_temp) { |
8197 | to_intel_connector(connector)->new_encoder = NULL; |
8198 | intel_encoder->new_crtc = NULL; |
8199 | intel_crtc->new_enabled = false; |
8200 | intel_crtc->new_config = NULL; |
8201 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
8202 | |
8203 | if (old->release_fb) { |
8204 | drm_framebuffer_unregister_private(old->release_fb); |
8205 | drm_framebuffer_unreference(old->release_fb); |
8206 | } |
8207 | |
8208 | mutex_unlock(&crtc->mutex); |
8209 | return; |
8210 | } |
8211 | |
8212 | /* Switch crtc and encoder back off if necessary */ |
8213 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8214 | connector->funcs->dpms(connector, old->dpms_mode); |
8215 | |
8216 | mutex_unlock(&crtc->mutex); |
8217 | } |
8218 | |
8219 | static int i9xx_pll_refclk(struct drm_device *dev, |
8220 | const struct intel_crtc_config *pipe_config) |
8221 | { |
8222 | struct drm_i915_private *dev_priv = dev->dev_private; |
8223 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
8224 | |
8225 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) |
8226 | return dev_priv->vbt.lvds_ssc_freq; |
8227 | else if (HAS_PCH_SPLIT(dev)) |
8228 | return 120000; |
8229 | else if (!IS_GEN2(dev)) |
8230 | return 96000; |
8231 | else |
8232 | return 48000; |
8233 | } |
8234 | |
8235 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
8236 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8237 | struct intel_crtc_config *pipe_config) |
8238 | { |
8239 | struct drm_device *dev = crtc->base.dev; |
8240 | struct drm_i915_private *dev_priv = dev->dev_private; |
8241 | int pipe = pipe_config->cpu_transcoder; |
8242 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
8243 | u32 fp; |
8244 | intel_clock_t clock; |
8245 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
8246 | |
8247 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
8248 | fp = pipe_config->dpll_hw_state.fp0; |
8249 | else |
8250 | fp = pipe_config->dpll_hw_state.fp1; |
8251 | |
8252 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
8253 | if (IS_PINEVIEW(dev)) { |
8254 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
8255 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
8256 | } else { |
8257 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
8258 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
8259 | } |
8260 | |
8261 | if (!IS_GEN2(dev)) { |
8262 | if (IS_PINEVIEW(dev)) |
8263 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
8264 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
8265 | else |
8266 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
8267 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8268 | |
8269 | switch (dpll & DPLL_MODE_MASK) { |
8270 | case DPLLB_MODE_DAC_SERIAL: |
8271 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
8272 | 5 : 10; |
8273 | break; |
8274 | case DPLLB_MODE_LVDS: |
8275 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
8276 | 7 : 14; |
8277 | break; |
8278 | default: |
8279 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
8280 | "mode\n" , (int)(dpll & DPLL_MODE_MASK)); |
8281 | return; |
8282 | } |
8283 | |
8284 | if (IS_PINEVIEW(dev)) |
8285 | pineview_clock(refclk, &clock); |
8286 | else |
8287 | i9xx_clock(refclk, &clock); |
8288 | } else { |
8289 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
8290 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
8291 | |
8292 | if (is_lvds) { |
8293 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
8294 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8295 | |
8296 | if (lvds & LVDS_CLKB_POWER_UP) |
8297 | clock.p2 = 7; |
8298 | else |
8299 | clock.p2 = 14; |
8300 | } else { |
8301 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
8302 | clock.p1 = 2; |
8303 | else { |
8304 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
8305 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
8306 | } |
8307 | if (dpll & PLL_P2_DIVIDE_BY_4) |
8308 | clock.p2 = 4; |
8309 | else |
8310 | clock.p2 = 2; |
8311 | } |
8312 | |
8313 | i9xx_clock(refclk, &clock); |
8314 | } |
8315 | |
8316 | /* |
8317 | * This value includes pixel_multiplier. We will use |
8318 | * port_clock to compute adjusted_mode.crtc_clock in the |
8319 | * encoder's get_config() function. |
8320 | */ |
8321 | pipe_config->port_clock = clock.dot; |
8322 | } |
8323 | |
8324 | int intel_dotclock_calculate(int link_freq, |
8325 | const struct intel_link_m_n *m_n) |
8326 | { |
8327 | /* |
8328 | * The calculation for the data clock is: |
8329 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
8330 | * But we want to avoid losing precison if possible, so: |
8331 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
8332 | * |
8333 | * and the link clock is simpler: |
8334 | * link_clock = (m * link_clock) / n |
8335 | */ |
8336 | |
8337 | if (!m_n->link_n) |
8338 | return 0; |
8339 | |
8340 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8341 | } |
8342 | |
8343 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8344 | struct intel_crtc_config *pipe_config) |
8345 | { |
8346 | struct drm_device *dev = crtc->base.dev; |
8347 | |
8348 | /* read out port_clock from the DPLL */ |
8349 | i9xx_crtc_clock_get(crtc, pipe_config); |
8350 | |
8351 | /* |
8352 | * This value does not include pixel_multiplier. |
8353 | * We will check that port_clock and adjusted_mode.crtc_clock |
8354 | * agree once we know their relationship in the encoder's |
8355 | * get_config() function. |
8356 | */ |
8357 | pipe_config->adjusted_mode.crtc_clock = |
8358 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8359 | &pipe_config->fdi_m_n); |
8360 | } |
8361 | |
8362 | /** Returns the currently programmed mode of the given pipe. */ |
8363 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
8364 | struct drm_crtc *crtc) |
8365 | { |
8366 | struct drm_i915_private *dev_priv = dev->dev_private; |
8367 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8368 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8369 | struct drm_display_mode *mode; |
8370 | struct intel_crtc_config pipe_config; |
8371 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8372 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
8373 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
8374 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
8375 | enum i915_pipe pipe = intel_crtc->pipe; |
8376 | |
8377 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
8378 | if (!mode) |
8379 | return NULL; |
8380 | |
8381 | /* |
8382 | * Construct a pipe_config sufficient for getting the clock info |
8383 | * back out of crtc_clock_get. |
8384 | * |
8385 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
8386 | * to use a real value here instead. |
8387 | */ |
8388 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
8389 | pipe_config.pixel_multiplier = 1; |
8390 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8391 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); |
8392 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); |
8393 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8394 | |
8395 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
8396 | mode->hdisplay = (htot & 0xffff) + 1; |
8397 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
8398 | mode->hsync_start = (hsync & 0xffff) + 1; |
8399 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
8400 | mode->vdisplay = (vtot & 0xffff) + 1; |
8401 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
8402 | mode->vsync_start = (vsync & 0xffff) + 1; |
8403 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
8404 | |
8405 | drm_mode_set_name(mode); |
8406 | |
8407 | return mode; |
8408 | } |
8409 | |
8410 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
8411 | { |
8412 | struct drm_device *dev = crtc->dev; |
8413 | struct drm_i915_private *dev_priv = dev->dev_private; |
8414 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8415 | int pipe = intel_crtc->pipe; |
8416 | int dpll_reg = DPLL(pipe); |
8417 | int dpll; |
8418 | |
8419 | if (HAS_PCH_SPLIT(dev)) |
8420 | return; |
8421 | |
8422 | if (!dev_priv->lvds_downclock_avail) |
8423 | return; |
8424 | |
8425 | dpll = I915_READ(dpll_reg); |
8426 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
8427 | DRM_DEBUG_DRIVER("upclocking LVDS\n" ); |
8428 | |
8429 | assert_panel_unlocked(dev_priv, pipe); |
8430 | |
8431 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
8432 | I915_WRITE(dpll_reg, dpll); |
8433 | intel_wait_for_vblank(dev, pipe); |
8434 | |
8435 | dpll = I915_READ(dpll_reg); |
8436 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
8437 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n" ); |
8438 | } |
8439 | } |
8440 | |
8441 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
8442 | { |
8443 | struct drm_device *dev = crtc->dev; |
8444 | struct drm_i915_private *dev_priv = dev->dev_private; |
8445 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8446 | |
8447 | if (HAS_PCH_SPLIT(dev)) |
8448 | return; |
8449 | |
8450 | if (!dev_priv->lvds_downclock_avail) |
8451 | return; |
8452 | |
8453 | /* |
8454 | * Since this is called by a timer, we should never get here in |
8455 | * the manual case. |
8456 | */ |
8457 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
8458 | int pipe = intel_crtc->pipe; |
8459 | int dpll_reg = DPLL(pipe); |
8460 | int dpll; |
8461 | |
8462 | DRM_DEBUG_DRIVER("downclocking LVDS\n" ); |
8463 | |
8464 | assert_panel_unlocked(dev_priv, pipe); |
8465 | |
8466 | dpll = I915_READ(dpll_reg); |
8467 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8468 | I915_WRITE(dpll_reg, dpll); |
8469 | intel_wait_for_vblank(dev, pipe); |
8470 | dpll = I915_READ(dpll_reg); |
8471 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
8472 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n" ); |
8473 | } |
8474 | |
8475 | } |
8476 | |
8477 | void intel_mark_busy(struct drm_device *dev) |
8478 | { |
8479 | struct drm_i915_private *dev_priv = dev->dev_private; |
8480 | |
8481 | if (dev_priv->mm.busy) |
8482 | return; |
8483 | |
8484 | intel_runtime_pm_get(dev_priv); |
8485 | i915_update_gfx_val(dev_priv); |
8486 | dev_priv->mm.busy = true; |
8487 | } |
8488 | |
8489 | void intel_mark_idle(struct drm_device *dev) |
8490 | { |
8491 | struct drm_i915_private *dev_priv = dev->dev_private; |
8492 | struct drm_crtc *crtc; |
8493 | |
8494 | if (!dev_priv->mm.busy) |
8495 | return; |
8496 | |
8497 | dev_priv->mm.busy = false; |
8498 | |
8499 | if (!i915.powersave) |
8500 | goto out; |
8501 | |
8502 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8503 | if (!crtc->primary->fb) |
8504 | continue; |
8505 | |
8506 | intel_decrease_pllclock(crtc); |
8507 | } |
8508 | |
8509 | if (INTEL_INFO(dev)->gen >= 6) |
8510 | gen6_rps_idle(dev->dev_private); |
8511 | |
8512 | out: |
8513 | intel_runtime_pm_put(dev_priv); |
8514 | } |
8515 | |
8516 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
8517 | struct intel_ring_buffer *ring) |
8518 | { |
8519 | struct drm_device *dev = obj->base.dev; |
8520 | struct drm_crtc *crtc; |
8521 | |
8522 | if (!i915.powersave) |
8523 | return; |
8524 | |
8525 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8526 | if (!crtc->primary->fb) |
8527 | continue; |
8528 | |
8529 | if (to_intel_framebuffer(crtc->primary->fb)->obj != obj) |
8530 | continue; |
8531 | |
8532 | intel_increase_pllclock(crtc); |
8533 | if (ring && intel_fbc_enabled(dev)) |
8534 | ring->fbc_dirty = true; |
8535 | } |
8536 | } |
8537 | |
8538 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8539 | { |
8540 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8541 | struct drm_device *dev = crtc->dev; |
8542 | struct intel_unpin_work *work; |
8543 | unsigned long flags; |
8544 | |
8545 | spin_lock_irqsave(&dev->event_lock, flags); |
8546 | work = intel_crtc->unpin_work; |
8547 | intel_crtc->unpin_work = NULL; |
8548 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8549 | |
8550 | if (work) { |
8551 | cancel_work_sync(&work->work); |
8552 | kfree(work); |
8553 | } |
8554 | |
8555 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
8556 | |
8557 | drm_crtc_cleanup(crtc); |
8558 | |
8559 | kfree(intel_crtc); |
8560 | } |
8561 | |
8562 | static void intel_unpin_work_fn(struct work_struct *__work) |
8563 | { |
8564 | struct intel_unpin_work *work = |
8565 | container_of(__work, struct intel_unpin_work, work); |
8566 | struct drm_device *dev = work->crtc->dev; |
8567 | |
8568 | mutex_lock(&dev->struct_mutex); |
8569 | intel_unpin_fb_obj(work->old_fb_obj); |
8570 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8571 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8572 | |
8573 | intel_update_fbc(dev); |
8574 | mutex_unlock(&dev->struct_mutex); |
8575 | |
8576 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
8577 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); |
8578 | |
8579 | kfree(work); |
8580 | } |
8581 | |
8582 | static void do_intel_finish_page_flip(struct drm_device *dev, |
8583 | struct drm_crtc *crtc) |
8584 | { |
8585 | struct drm_i915_private *dev_priv = dev->dev_private; |
8586 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8587 | struct intel_unpin_work *work; |
8588 | unsigned long flags; |
8589 | |
8590 | /* Ignore early vblank irqs */ |
8591 | if (intel_crtc == NULL) |
8592 | return; |
8593 | |
8594 | spin_lock_irqsave(&dev->event_lock, flags); |
8595 | work = intel_crtc->unpin_work; |
8596 | |
8597 | /* Ensure we don't miss a work->pending update ... */ |
8598 | smp_rmb(); |
8599 | |
8600 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
8601 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8602 | return; |
8603 | } |
8604 | |
8605 | /* and that the unpin work is consistent wrt ->pending. */ |
8606 | smp_rmb(); |
8607 | |
8608 | intel_crtc->unpin_work = NULL; |
8609 | |
8610 | if (work->event) |
8611 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); |
8612 | |
8613 | drm_vblank_put(dev, intel_crtc->pipe); |
8614 | |
8615 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8616 | |
8617 | #ifdef __NetBSD__ /* XXX */ |
8618 | spin_lock_irqsave(&dev_priv->pending_flip_lock, flags); |
8619 | DRM_SPIN_WAKEUP_ALL(&dev_priv->pending_flip_queue, |
8620 | &dev_priv->pending_flip_lock); |
8621 | spin_unlock_irqrestore(&dev_priv->pending_flip_lock, flags); |
8622 | #else |
8623 | wake_up_all(&dev_priv->pending_flip_queue); |
8624 | #endif |
8625 | |
8626 | queue_work(dev_priv->wq, &work->work); |
8627 | |
8628 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
8629 | } |
8630 | |
8631 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8632 | { |
8633 | struct drm_i915_private *dev_priv = dev->dev_private; |
8634 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
8635 | |
8636 | do_intel_finish_page_flip(dev, crtc); |
8637 | } |
8638 | |
8639 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
8640 | { |
8641 | struct drm_i915_private *dev_priv = dev->dev_private; |
8642 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
8643 | |
8644 | do_intel_finish_page_flip(dev, crtc); |
8645 | } |
8646 | |
8647 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
8648 | { |
8649 | struct drm_i915_private *dev_priv = dev->dev_private; |
8650 | struct intel_crtc *intel_crtc = |
8651 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
8652 | unsigned long flags; |
8653 | |
8654 | /* NB: An MMIO update of the plane base pointer will also |
8655 | * generate a page-flip completion irq, i.e. every modeset |
8656 | * is also accompanied by a spurious intel_prepare_page_flip(). |
8657 | */ |
8658 | spin_lock_irqsave(&dev->event_lock, flags); |
8659 | if (intel_crtc->unpin_work) |
8660 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
8661 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8662 | } |
8663 | |
8664 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
8665 | { |
8666 | /* Ensure that the work item is consistent when activating it ... */ |
8667 | smp_wmb(); |
8668 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); |
8669 | /* and that it is marked active as soon as the irq could fire. */ |
8670 | smp_wmb(); |
8671 | } |
8672 | |
8673 | static int intel_gen2_queue_flip(struct drm_device *dev, |
8674 | struct drm_crtc *crtc, |
8675 | struct drm_framebuffer *fb, |
8676 | struct drm_i915_gem_object *obj, |
8677 | uint32_t flags) |
8678 | { |
8679 | struct drm_i915_private *dev_priv = dev->dev_private; |
8680 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8681 | u32 flip_mask; |
8682 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8683 | int ret; |
8684 | |
8685 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8686 | if (ret) |
8687 | goto err; |
8688 | |
8689 | ret = intel_ring_begin(ring, 6); |
8690 | if (ret) |
8691 | goto err_unpin; |
8692 | |
8693 | /* Can't queue multiple flips, so wait for the previous |
8694 | * one to finish before executing the next. |
8695 | */ |
8696 | if (intel_crtc->plane) |
8697 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
8698 | else |
8699 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
8700 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8701 | intel_ring_emit(ring, MI_NOOP); |
8702 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8703 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
8704 | intel_ring_emit(ring, fb->pitches[0]); |
8705 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8706 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
8707 | |
8708 | intel_mark_page_flip_active(intel_crtc); |
8709 | __intel_ring_advance(ring); |
8710 | return 0; |
8711 | |
8712 | err_unpin: |
8713 | intel_unpin_fb_obj(obj); |
8714 | err: |
8715 | return ret; |
8716 | } |
8717 | |
8718 | static int intel_gen3_queue_flip(struct drm_device *dev, |
8719 | struct drm_crtc *crtc, |
8720 | struct drm_framebuffer *fb, |
8721 | struct drm_i915_gem_object *obj, |
8722 | uint32_t flags) |
8723 | { |
8724 | struct drm_i915_private *dev_priv = dev->dev_private; |
8725 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8726 | u32 flip_mask; |
8727 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8728 | int ret; |
8729 | |
8730 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8731 | if (ret) |
8732 | goto err; |
8733 | |
8734 | ret = intel_ring_begin(ring, 6); |
8735 | if (ret) |
8736 | goto err_unpin; |
8737 | |
8738 | if (intel_crtc->plane) |
8739 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
8740 | else |
8741 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
8742 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8743 | intel_ring_emit(ring, MI_NOOP); |
8744 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
8745 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
8746 | intel_ring_emit(ring, fb->pitches[0]); |
8747 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8748 | intel_ring_emit(ring, MI_NOOP); |
8749 | |
8750 | intel_mark_page_flip_active(intel_crtc); |
8751 | __intel_ring_advance(ring); |
8752 | return 0; |
8753 | |
8754 | err_unpin: |
8755 | intel_unpin_fb_obj(obj); |
8756 | err: |
8757 | return ret; |
8758 | } |
8759 | |
8760 | static int intel_gen4_queue_flip(struct drm_device *dev, |
8761 | struct drm_crtc *crtc, |
8762 | struct drm_framebuffer *fb, |
8763 | struct drm_i915_gem_object *obj, |
8764 | uint32_t flags) |
8765 | { |
8766 | struct drm_i915_private *dev_priv = dev->dev_private; |
8767 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8768 | uint32_t pf, pipesrc; |
8769 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8770 | int ret; |
8771 | |
8772 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8773 | if (ret) |
8774 | goto err; |
8775 | |
8776 | ret = intel_ring_begin(ring, 4); |
8777 | if (ret) |
8778 | goto err_unpin; |
8779 | |
8780 | /* i965+ uses the linear or tiled offsets from the |
8781 | * Display Registers (which do not change across a page-flip) |
8782 | * so we need only reprogram the base address. |
8783 | */ |
8784 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8785 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
8786 | intel_ring_emit(ring, fb->pitches[0]); |
8787 | intel_ring_emit(ring, |
8788 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
8789 | obj->tiling_mode); |
8790 | |
8791 | /* XXX Enabling the panel-fitter across page-flip is so far |
8792 | * untested on non-native modes, so ignore it for now. |
8793 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
8794 | */ |
8795 | pf = 0; |
8796 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
8797 | intel_ring_emit(ring, pf | pipesrc); |
8798 | |
8799 | intel_mark_page_flip_active(intel_crtc); |
8800 | __intel_ring_advance(ring); |
8801 | return 0; |
8802 | |
8803 | err_unpin: |
8804 | intel_unpin_fb_obj(obj); |
8805 | err: |
8806 | return ret; |
8807 | } |
8808 | |
8809 | static int intel_gen6_queue_flip(struct drm_device *dev, |
8810 | struct drm_crtc *crtc, |
8811 | struct drm_framebuffer *fb, |
8812 | struct drm_i915_gem_object *obj, |
8813 | uint32_t flags) |
8814 | { |
8815 | struct drm_i915_private *dev_priv = dev->dev_private; |
8816 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8817 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8818 | uint32_t pf, pipesrc; |
8819 | int ret; |
8820 | |
8821 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8822 | if (ret) |
8823 | goto err; |
8824 | |
8825 | ret = intel_ring_begin(ring, 4); |
8826 | if (ret) |
8827 | goto err_unpin; |
8828 | |
8829 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8830 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
8831 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
8832 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8833 | |
8834 | /* Contrary to the suggestions in the documentation, |
8835 | * "Enable Panel Fitter" does not seem to be required when page |
8836 | * flipping with a non-native mode, and worse causes a normal |
8837 | * modeset to fail. |
8838 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
8839 | */ |
8840 | pf = 0; |
8841 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
8842 | intel_ring_emit(ring, pf | pipesrc); |
8843 | |
8844 | intel_mark_page_flip_active(intel_crtc); |
8845 | __intel_ring_advance(ring); |
8846 | return 0; |
8847 | |
8848 | err_unpin: |
8849 | intel_unpin_fb_obj(obj); |
8850 | err: |
8851 | return ret; |
8852 | } |
8853 | |
8854 | static int intel_gen7_queue_flip(struct drm_device *dev, |
8855 | struct drm_crtc *crtc, |
8856 | struct drm_framebuffer *fb, |
8857 | struct drm_i915_gem_object *obj, |
8858 | uint32_t flags) |
8859 | { |
8860 | struct drm_i915_private *dev_priv = dev->dev_private; |
8861 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8862 | struct intel_ring_buffer *ring; |
8863 | uint32_t plane_bit = 0; |
8864 | int len, ret; |
8865 | |
8866 | ring = obj->ring; |
8867 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
8868 | ring = &dev_priv->ring[BCS]; |
8869 | |
8870 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8871 | if (ret) |
8872 | goto err; |
8873 | |
8874 | switch(intel_crtc->plane) { |
8875 | case PLANE_A: |
8876 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
8877 | break; |
8878 | case PLANE_B: |
8879 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
8880 | break; |
8881 | case PLANE_C: |
8882 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
8883 | break; |
8884 | default: |
8885 | WARN_ONCE(1, "unknown plane in flip command\n" ); |
8886 | ret = -ENODEV; |
8887 | goto err_unpin; |
8888 | } |
8889 | |
8890 | len = 4; |
8891 | if (ring->id == RCS) |
8892 | len += 6; |
8893 | |
8894 | /* |
8895 | * BSpec MI_DISPLAY_FLIP for IVB: |
8896 | * "The full packet must be contained within the same cache line." |
8897 | * |
8898 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same |
8899 | * cacheline, if we ever start emitting more commands before |
8900 | * the MI_DISPLAY_FLIP we may need to first emit everything else, |
8901 | * then do the cacheline alignment, and finally emit the |
8902 | * MI_DISPLAY_FLIP. |
8903 | */ |
8904 | ret = intel_ring_cacheline_align(ring); |
8905 | if (ret) |
8906 | goto err_unpin; |
8907 | |
8908 | ret = intel_ring_begin(ring, len); |
8909 | if (ret) |
8910 | goto err_unpin; |
8911 | |
8912 | /* Unmask the flip-done completion message. Note that the bspec says that |
8913 | * we should do this for both the BCS and RCS, and that we must not unmask |
8914 | * more than one flip event at any time (or ensure that one flip message |
8915 | * can be sent by waiting for flip-done prior to queueing new flips). |
8916 | * Experimentation says that BCS works despite DERRMR masking all |
8917 | * flip-done completion events and that unmasking all planes at once |
8918 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
8919 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
8920 | */ |
8921 | if (ring->id == RCS) { |
8922 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
8923 | intel_ring_emit(ring, DERRMR); |
8924 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
8925 | DERRMR_PIPEB_PRI_FLIP_DONE | |
8926 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
8927 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
8928 | MI_SRM_LRM_GLOBAL_GTT); |
8929 | intel_ring_emit(ring, DERRMR); |
8930 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
8931 | } |
8932 | |
8933 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
8934 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
8935 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8936 | intel_ring_emit(ring, (MI_NOOP)); |
8937 | |
8938 | intel_mark_page_flip_active(intel_crtc); |
8939 | __intel_ring_advance(ring); |
8940 | return 0; |
8941 | |
8942 | err_unpin: |
8943 | intel_unpin_fb_obj(obj); |
8944 | err: |
8945 | return ret; |
8946 | } |
8947 | |
8948 | static int intel_default_queue_flip(struct drm_device *dev, |
8949 | struct drm_crtc *crtc, |
8950 | struct drm_framebuffer *fb, |
8951 | struct drm_i915_gem_object *obj, |
8952 | uint32_t flags) |
8953 | { |
8954 | return -ENODEV; |
8955 | } |
8956 | |
8957 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
8958 | struct drm_framebuffer *fb, |
8959 | struct drm_pending_vblank_event *event, |
8960 | uint32_t page_flip_flags) |
8961 | { |
8962 | struct drm_device *dev = crtc->dev; |
8963 | struct drm_i915_private *dev_priv = dev->dev_private; |
8964 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
8965 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
8966 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8967 | struct intel_unpin_work *work; |
8968 | unsigned long flags; |
8969 | int ret; |
8970 | |
8971 | /* Can't change pixel format via MI display flips. */ |
8972 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
8973 | return -EINVAL; |
8974 | |
8975 | /* |
8976 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
8977 | * Note that pitch changes could also affect these register. |
8978 | */ |
8979 | if (INTEL_INFO(dev)->gen > 3 && |
8980 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
8981 | fb->pitches[0] != crtc->primary->fb->pitches[0])) |
8982 | return -EINVAL; |
8983 | |
8984 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
8985 | goto out_hang; |
8986 | |
8987 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
8988 | if (work == NULL) |
8989 | return -ENOMEM; |
8990 | |
8991 | work->event = event; |
8992 | work->crtc = crtc; |
8993 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
8994 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8995 | |
8996 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
8997 | if (ret) |
8998 | goto free_work; |
8999 | |
9000 | /* We borrow the event spin lock for protecting unpin_work */ |
9001 | spin_lock_irqsave(&dev->event_lock, flags); |
9002 | if (intel_crtc->unpin_work) { |
9003 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9004 | kfree(work); |
9005 | drm_vblank_put(dev, intel_crtc->pipe); |
9006 | |
9007 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n" ); |
9008 | return -EBUSY; |
9009 | } |
9010 | intel_crtc->unpin_work = work; |
9011 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9012 | |
9013 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9014 | flush_workqueue(dev_priv->wq); |
9015 | |
9016 | ret = i915_mutex_lock_interruptible(dev); |
9017 | if (ret) |
9018 | goto cleanup; |
9019 | |
9020 | /* Reference the objects for the scheduled work. */ |
9021 | drm_gem_object_reference(&work->old_fb_obj->base); |
9022 | drm_gem_object_reference(&obj->base); |
9023 | |
9024 | crtc->primary->fb = fb; |
9025 | |
9026 | work->pending_flip_obj = obj; |
9027 | |
9028 | work->enable_stall_check = true; |
9029 | |
9030 | atomic_inc(&intel_crtc->unpin_work_count); |
9031 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
9032 | |
9033 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
9034 | if (ret) |
9035 | goto cleanup_pending; |
9036 | |
9037 | intel_disable_fbc(dev); |
9038 | intel_mark_fb_busy(obj, NULL); |
9039 | mutex_unlock(&dev->struct_mutex); |
9040 | |
9041 | trace_i915_flip_request(intel_crtc->plane, obj); |
9042 | |
9043 | return 0; |
9044 | |
9045 | cleanup_pending: |
9046 | atomic_dec(&intel_crtc->unpin_work_count); |
9047 | crtc->primary->fb = old_fb; |
9048 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9049 | drm_gem_object_unreference(&obj->base); |
9050 | mutex_unlock(&dev->struct_mutex); |
9051 | |
9052 | cleanup: |
9053 | spin_lock_irqsave(&dev->event_lock, flags); |
9054 | intel_crtc->unpin_work = NULL; |
9055 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9056 | |
9057 | drm_vblank_put(dev, intel_crtc->pipe); |
9058 | free_work: |
9059 | kfree(work); |
9060 | |
9061 | if (ret == -EIO) { |
9062 | out_hang: |
9063 | intel_crtc_wait_for_pending_flips(crtc); |
9064 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); |
9065 | if (ret == 0 && event) |
9066 | drm_send_vblank_event(dev, intel_crtc->pipe, event); |
9067 | } |
9068 | return ret; |
9069 | } |
9070 | |
9071 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
9072 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9073 | .load_lut = intel_crtc_load_lut, |
9074 | }; |
9075 | |
9076 | /** |
9077 | * intel_modeset_update_staged_output_state |
9078 | * |
9079 | * Updates the staged output configuration state, e.g. after we've read out the |
9080 | * current hw state. |
9081 | */ |
9082 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
9083 | { |
9084 | struct intel_crtc *crtc; |
9085 | struct intel_encoder *encoder; |
9086 | struct intel_connector *connector; |
9087 | |
9088 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9089 | base.head) { |
9090 | connector->new_encoder = |
9091 | to_intel_encoder(connector->base.encoder); |
9092 | } |
9093 | |
9094 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9095 | base.head) { |
9096 | encoder->new_crtc = |
9097 | to_intel_crtc(encoder->base.crtc); |
9098 | } |
9099 | |
9100 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
9101 | base.head) { |
9102 | crtc->new_enabled = crtc->base.enabled; |
9103 | |
9104 | if (crtc->new_enabled) |
9105 | crtc->new_config = &crtc->config; |
9106 | else |
9107 | crtc->new_config = NULL; |
9108 | } |
9109 | } |
9110 | |
9111 | /** |
9112 | * intel_modeset_commit_output_state |
9113 | * |
9114 | * This function copies the stage display pipe configuration to the real one. |
9115 | */ |
9116 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
9117 | { |
9118 | struct intel_crtc *crtc; |
9119 | struct intel_encoder *encoder; |
9120 | struct intel_connector *connector; |
9121 | |
9122 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9123 | base.head) { |
9124 | connector->base.encoder = &connector->new_encoder->base; |
9125 | } |
9126 | |
9127 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9128 | base.head) { |
9129 | encoder->base.crtc = &encoder->new_crtc->base; |
9130 | } |
9131 | |
9132 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
9133 | base.head) { |
9134 | crtc->base.enabled = crtc->new_enabled; |
9135 | } |
9136 | } |
9137 | |
9138 | static void |
9139 | connected_sink_compute_bpp(struct intel_connector * connector, |
9140 | struct intel_crtc_config *pipe_config) |
9141 | { |
9142 | int bpp = pipe_config->pipe_bpp; |
9143 | |
9144 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n" , |
9145 | connector->base.base.id, |
9146 | drm_get_connector_name(&connector->base)); |
9147 | |
9148 | /* Don't use an invalid EDID bpc value */ |
9149 | if (connector->base.display_info.bpc && |
9150 | connector->base.display_info.bpc * 3 < bpp) { |
9151 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n" , |
9152 | bpp, connector->base.display_info.bpc*3); |
9153 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; |
9154 | } |
9155 | |
9156 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
9157 | if (connector->base.display_info.bpc == 0 && bpp > 24) { |
9158 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n" , |
9159 | bpp); |
9160 | pipe_config->pipe_bpp = 24; |
9161 | } |
9162 | } |
9163 | |
9164 | static int |
9165 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9166 | struct drm_framebuffer *fb, |
9167 | struct intel_crtc_config *pipe_config) |
9168 | { |
9169 | struct drm_device *dev = crtc->base.dev; |
9170 | struct intel_connector *connector; |
9171 | int bpp; |
9172 | |
9173 | switch (fb->pixel_format) { |
9174 | case DRM_FORMAT_C8: |
9175 | bpp = 8*3; /* since we go through a colormap */ |
9176 | break; |
9177 | case DRM_FORMAT_XRGB1555: |
9178 | case DRM_FORMAT_ARGB1555: |
9179 | /* checked in intel_framebuffer_init already */ |
9180 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) |
9181 | return -EINVAL; |
9182 | case DRM_FORMAT_RGB565: |
9183 | bpp = 6*3; /* min is 18bpp */ |
9184 | break; |
9185 | case DRM_FORMAT_XBGR8888: |
9186 | case DRM_FORMAT_ABGR8888: |
9187 | /* checked in intel_framebuffer_init already */ |
9188 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
9189 | return -EINVAL; |
9190 | case DRM_FORMAT_XRGB8888: |
9191 | case DRM_FORMAT_ARGB8888: |
9192 | bpp = 8*3; |
9193 | break; |
9194 | case DRM_FORMAT_XRGB2101010: |
9195 | case DRM_FORMAT_ARGB2101010: |
9196 | case DRM_FORMAT_XBGR2101010: |
9197 | case DRM_FORMAT_ABGR2101010: |
9198 | /* checked in intel_framebuffer_init already */ |
9199 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
9200 | return -EINVAL; |
9201 | bpp = 10*3; |
9202 | break; |
9203 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
9204 | default: |
9205 | DRM_DEBUG_KMS("unsupported depth\n" ); |
9206 | return -EINVAL; |
9207 | } |
9208 | |
9209 | pipe_config->pipe_bpp = bpp; |
9210 | |
9211 | /* Clamp display bpp to EDID value */ |
9212 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9213 | base.head) { |
9214 | if (!connector->new_encoder || |
9215 | connector->new_encoder->new_crtc != crtc) |
9216 | continue; |
9217 | |
9218 | connected_sink_compute_bpp(connector, pipe_config); |
9219 | } |
9220 | |
9221 | return bpp; |
9222 | } |
9223 | |
9224 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
9225 | { |
9226 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " |
9227 | "type: 0x%x flags: 0x%x\n" , |
9228 | mode->crtc_clock, |
9229 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
9230 | mode->crtc_hsync_end, mode->crtc_htotal, |
9231 | mode->crtc_vdisplay, mode->crtc_vsync_start, |
9232 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); |
9233 | } |
9234 | |
9235 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
9236 | struct intel_crtc_config *pipe_config, |
9237 | const char *context) |
9238 | { |
9239 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n" , crtc->base.base.id, |
9240 | context, pipe_name(crtc->pipe)); |
9241 | |
9242 | DRM_DEBUG_KMS("cpu_transcoder: %c\n" , transcoder_name(pipe_config->cpu_transcoder)); |
9243 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n" , |
9244 | pipe_config->pipe_bpp, pipe_config->dither); |
9245 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n" , |
9246 | pipe_config->has_pch_encoder, |
9247 | pipe_config->fdi_lanes, |
9248 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
9249 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
9250 | pipe_config->fdi_m_n.tu); |
9251 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n" , |
9252 | pipe_config->has_dp_encoder, |
9253 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
9254 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, |
9255 | pipe_config->dp_m_n.tu); |
9256 | DRM_DEBUG_KMS("requested mode:\n" ); |
9257 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); |
9258 | DRM_DEBUG_KMS("adjusted mode:\n" ); |
9259 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); |
9260 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
9261 | DRM_DEBUG_KMS("port clock: %d\n" , pipe_config->port_clock); |
9262 | DRM_DEBUG_KMS("pipe src size: %dx%d\n" , |
9263 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
9264 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n" , |
9265 | pipe_config->gmch_pfit.control, |
9266 | pipe_config->gmch_pfit.pgm_ratios, |
9267 | pipe_config->gmch_pfit.lvds_border_bits); |
9268 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n" , |
9269 | pipe_config->pch_pfit.pos, |
9270 | pipe_config->pch_pfit.size, |
9271 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled" ); |
9272 | DRM_DEBUG_KMS("ips: %i\n" , pipe_config->ips_enabled); |
9273 | DRM_DEBUG_KMS("double wide: %i\n" , pipe_config->double_wide); |
9274 | } |
9275 | |
9276 | static bool encoders_cloneable(const struct intel_encoder *a, |
9277 | const struct intel_encoder *b) |
9278 | { |
9279 | /* masks could be asymmetric, so check both ways */ |
9280 | return a == b || (a->cloneable & (1 << b->type) && |
9281 | b->cloneable & (1 << a->type)); |
9282 | } |
9283 | |
9284 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, |
9285 | struct intel_encoder *encoder) |
9286 | { |
9287 | struct drm_device *dev = crtc->base.dev; |
9288 | struct intel_encoder *source_encoder; |
9289 | |
9290 | list_for_each_entry(source_encoder, |
9291 | &dev->mode_config.encoder_list, base.head) { |
9292 | if (source_encoder->new_crtc != crtc) |
9293 | continue; |
9294 | |
9295 | if (!encoders_cloneable(encoder, source_encoder)) |
9296 | return false; |
9297 | } |
9298 | |
9299 | return true; |
9300 | } |
9301 | |
9302 | static bool check_encoder_cloning(struct intel_crtc *crtc) |
9303 | { |
9304 | struct drm_device *dev = crtc->base.dev; |
9305 | struct intel_encoder *encoder; |
9306 | |
9307 | list_for_each_entry(encoder, |
9308 | &dev->mode_config.encoder_list, base.head) { |
9309 | if (encoder->new_crtc != crtc) |
9310 | continue; |
9311 | |
9312 | if (!check_single_encoder_cloning(crtc, encoder)) |
9313 | return false; |
9314 | } |
9315 | |
9316 | return true; |
9317 | } |
9318 | |
9319 | static struct intel_crtc_config * |
9320 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
9321 | struct drm_framebuffer *fb, |
9322 | struct drm_display_mode *mode) |
9323 | { |
9324 | struct drm_device *dev = crtc->dev; |
9325 | struct intel_encoder *encoder; |
9326 | struct intel_crtc_config *pipe_config; |
9327 | int plane_bpp, ret = -EINVAL; |
9328 | bool retry = true; |
9329 | |
9330 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
9331 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n" ); |
9332 | return ERR_PTR(-EINVAL); |
9333 | } |
9334 | |
9335 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9336 | if (!pipe_config) |
9337 | return ERR_PTR(-ENOMEM); |
9338 | |
9339 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
9340 | drm_mode_copy(&pipe_config->requested_mode, mode); |
9341 | |
9342 | pipe_config->cpu_transcoder = |
9343 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
9344 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9345 | |
9346 | /* |
9347 | * Sanitize sync polarity flags based on requested ones. If neither |
9348 | * positive or negative polarity is requested, treat this as meaning |
9349 | * negative polarity. |
9350 | */ |
9351 | if (!(pipe_config->adjusted_mode.flags & |
9352 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
9353 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
9354 | |
9355 | if (!(pipe_config->adjusted_mode.flags & |
9356 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
9357 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
9358 | |
9359 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
9360 | * plane pixel format and any sink constraints into account. Returns the |
9361 | * source plane bpp so that dithering can be selected on mismatches |
9362 | * after encoders and crtc also have had their say. */ |
9363 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
9364 | fb, pipe_config); |
9365 | if (plane_bpp < 0) |
9366 | goto fail; |
9367 | |
9368 | /* |
9369 | * Determine the real pipe dimensions. Note that stereo modes can |
9370 | * increase the actual pipe size due to the frame doubling and |
9371 | * insertion of additional space for blanks between the frame. This |
9372 | * is stored in the crtc timings. We use the requested mode to do this |
9373 | * computation to clearly distinguish it from the adjusted mode, which |
9374 | * can be changed by the connectors in the below retry loop. |
9375 | */ |
9376 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); |
9377 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; |
9378 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; |
9379 | |
9380 | encoder_retry: |
9381 | /* Ensure the port clock defaults are reset when retrying. */ |
9382 | pipe_config->port_clock = 0; |
9383 | pipe_config->pixel_multiplier = 1; |
9384 | |
9385 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
9386 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
9387 | |
9388 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
9389 | * adjust it according to limitations or connector properties, and also |
9390 | * a chance to reject the mode entirely. |
9391 | */ |
9392 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9393 | base.head) { |
9394 | |
9395 | if (&encoder->new_crtc->base != crtc) |
9396 | continue; |
9397 | |
9398 | if (!(encoder->compute_config(encoder, pipe_config))) { |
9399 | DRM_DEBUG_KMS("Encoder config failure\n" ); |
9400 | goto fail; |
9401 | } |
9402 | } |
9403 | |
9404 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9405 | * done afterwards in case the encoder adjusts the mode. */ |
9406 | if (!pipe_config->port_clock) |
9407 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
9408 | * pipe_config->pixel_multiplier; |
9409 | |
9410 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
9411 | if (ret < 0) { |
9412 | DRM_DEBUG_KMS("CRTC fixup failed\n" ); |
9413 | goto fail; |
9414 | } |
9415 | |
9416 | if (ret == RETRY) { |
9417 | if (WARN(!retry, "loop in pipe configuration computation\n" )) { |
9418 | ret = -EINVAL; |
9419 | goto fail; |
9420 | } |
9421 | |
9422 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n" ); |
9423 | retry = false; |
9424 | goto encoder_retry; |
9425 | } |
9426 | |
9427 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
9428 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n" , |
9429 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
9430 | |
9431 | return pipe_config; |
9432 | fail: |
9433 | kfree(pipe_config); |
9434 | return ERR_PTR(ret); |
9435 | } |
9436 | |
9437 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9438 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ |
9439 | static void |
9440 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, |
9441 | unsigned *prepare_pipes, unsigned *disable_pipes) |
9442 | { |
9443 | struct intel_crtc *intel_crtc; |
9444 | struct drm_device *dev = crtc->dev; |
9445 | struct intel_encoder *encoder; |
9446 | struct intel_connector *connector; |
9447 | struct drm_crtc *tmp_crtc; |
9448 | |
9449 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
9450 | |
9451 | /* Check which crtcs have changed outputs connected to them, these need |
9452 | * to be part of the prepare_pipes mask. We don't (yet) support global |
9453 | * modeset across multiple crtcs, so modeset_pipes will only have one |
9454 | * bit set at most. */ |
9455 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9456 | base.head) { |
9457 | if (connector->base.encoder == &connector->new_encoder->base) |
9458 | continue; |
9459 | |
9460 | if (connector->base.encoder) { |
9461 | tmp_crtc = connector->base.encoder->crtc; |
9462 | |
9463 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
9464 | } |
9465 | |
9466 | if (connector->new_encoder) |
9467 | *prepare_pipes |= |
9468 | 1 << connector->new_encoder->new_crtc->pipe; |
9469 | } |
9470 | |
9471 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9472 | base.head) { |
9473 | if (encoder->base.crtc == &encoder->new_crtc->base) |
9474 | continue; |
9475 | |
9476 | if (encoder->base.crtc) { |
9477 | tmp_crtc = encoder->base.crtc; |
9478 | |
9479 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
9480 | } |
9481 | |
9482 | if (encoder->new_crtc) |
9483 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
9484 | } |
9485 | |
9486 | /* Check for pipes that will be enabled/disabled ... */ |
9487 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
9488 | base.head) { |
9489 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
9490 | continue; |
9491 | |
9492 | if (!intel_crtc->new_enabled) |
9493 | *disable_pipes |= 1 << intel_crtc->pipe; |
9494 | else |
9495 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9496 | } |
9497 | |
9498 | |
9499 | /* set_mode is also used to update properties on life display pipes. */ |
9500 | intel_crtc = to_intel_crtc(crtc); |
9501 | if (intel_crtc->new_enabled) |
9502 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9503 | |
9504 | /* |
9505 | * For simplicity do a full modeset on any pipe where the output routing |
9506 | * changed. We could be more clever, but that would require us to be |
9507 | * more careful with calling the relevant encoder->mode_set functions. |
9508 | */ |
9509 | if (*prepare_pipes) |
9510 | *modeset_pipes = *prepare_pipes; |
9511 | |
9512 | /* ... and mask these out. */ |
9513 | *modeset_pipes &= ~(*disable_pipes); |
9514 | *prepare_pipes &= ~(*disable_pipes); |
9515 | |
9516 | /* |
9517 | * HACK: We don't (yet) fully support global modesets. intel_set_config |
9518 | * obies this rule, but the modeset restore mode of |
9519 | * intel_modeset_setup_hw_state does not. |
9520 | */ |
9521 | *modeset_pipes &= 1 << intel_crtc->pipe; |
9522 | *prepare_pipes &= 1 << intel_crtc->pipe; |
9523 | |
9524 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n" , |
9525 | *modeset_pipes, *prepare_pipes, *disable_pipes); |
9526 | } |
9527 | |
9528 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
9529 | { |
9530 | struct drm_encoder *encoder; |
9531 | struct drm_device *dev = crtc->dev; |
9532 | |
9533 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9534 | if (encoder->crtc == crtc) |
9535 | return true; |
9536 | |
9537 | return false; |
9538 | } |
9539 | |
9540 | static void |
9541 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) |
9542 | { |
9543 | struct intel_encoder *intel_encoder; |
9544 | struct intel_crtc *intel_crtc; |
9545 | struct drm_connector *connector; |
9546 | |
9547 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, |
9548 | base.head) { |
9549 | if (!intel_encoder->base.crtc) |
9550 | continue; |
9551 | |
9552 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
9553 | |
9554 | if (prepare_pipes & (1 << intel_crtc->pipe)) |
9555 | intel_encoder->connectors_active = false; |
9556 | } |
9557 | |
9558 | intel_modeset_commit_output_state(dev); |
9559 | |
9560 | /* Double check state. */ |
9561 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
9562 | base.head) { |
9563 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
9564 | WARN_ON(intel_crtc->new_config && |
9565 | intel_crtc->new_config != &intel_crtc->config); |
9566 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); |
9567 | } |
9568 | |
9569 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
9570 | if (!connector->encoder || !connector->encoder->crtc) |
9571 | continue; |
9572 | |
9573 | intel_crtc = to_intel_crtc(connector->encoder->crtc); |
9574 | |
9575 | if (prepare_pipes & (1 << intel_crtc->pipe)) { |
9576 | struct drm_property *dpms_property = |
9577 | dev->mode_config.dpms_property; |
9578 | |
9579 | connector->dpms = DRM_MODE_DPMS_ON; |
9580 | drm_object_property_set_value(&connector->base, |
9581 | dpms_property, |
9582 | DRM_MODE_DPMS_ON); |
9583 | |
9584 | intel_encoder = to_intel_encoder(connector->encoder); |
9585 | intel_encoder->connectors_active = true; |
9586 | } |
9587 | } |
9588 | |
9589 | } |
9590 | |
9591 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
9592 | { |
9593 | int diff; |
9594 | |
9595 | if (clock1 == clock2) |
9596 | return true; |
9597 | |
9598 | if (!clock1 || !clock2) |
9599 | return false; |
9600 | |
9601 | diff = abs(clock1 - clock2); |
9602 | |
9603 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
9604 | return true; |
9605 | |
9606 | return false; |
9607 | } |
9608 | |
9609 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9610 | list_for_each_entry((intel_crtc), \ |
9611 | &(dev)->mode_config.crtc_list, \ |
9612 | base.head) \ |
9613 | if (mask & (1 <<(intel_crtc)->pipe)) |
9614 | |
9615 | static bool |
9616 | intel_pipe_config_compare(struct drm_device *dev, |
9617 | struct intel_crtc_config *current_config, |
9618 | struct intel_crtc_config *pipe_config) |
9619 | { |
9620 | #define PIPE_CONF_CHECK_X(name) \ |
9621 | if (current_config->name != pipe_config->name) { \ |
9622 | DRM_ERROR("mismatch in " #name " " \ |
9623 | "(expected 0x%08x, found 0x%08x)\n", \ |
9624 | current_config->name, \ |
9625 | pipe_config->name); \ |
9626 | return false; \ |
9627 | } |
9628 | |
9629 | #define PIPE_CONF_CHECK_I(name) \ |
9630 | if (current_config->name != pipe_config->name) { \ |
9631 | DRM_ERROR("mismatch in " #name " " \ |
9632 | "(expected %i, found %i)\n", \ |
9633 | current_config->name, \ |
9634 | pipe_config->name); \ |
9635 | return false; \ |
9636 | } |
9637 | |
9638 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9639 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
9640 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
9641 | "(expected %i, found %i)\n", \ |
9642 | current_config->name & (mask), \ |
9643 | pipe_config->name & (mask)); \ |
9644 | return false; \ |
9645 | } |
9646 | |
9647 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9648 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ |
9649 | DRM_ERROR("mismatch in " #name " " \ |
9650 | "(expected %i, found %i)\n", \ |
9651 | current_config->name, \ |
9652 | pipe_config->name); \ |
9653 | return false; \ |
9654 | } |
9655 | |
9656 | #define PIPE_CONF_QUIRK(quirk) \ |
9657 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
9658 | |
9659 | PIPE_CONF_CHECK_I(cpu_transcoder); |
9660 | |
9661 | PIPE_CONF_CHECK_I(has_pch_encoder); |
9662 | PIPE_CONF_CHECK_I(fdi_lanes); |
9663 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
9664 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); |
9665 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); |
9666 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); |
9667 | PIPE_CONF_CHECK_I(fdi_m_n.tu); |
9668 | |
9669 | PIPE_CONF_CHECK_I(has_dp_encoder); |
9670 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); |
9671 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); |
9672 | PIPE_CONF_CHECK_I(dp_m_n.link_m); |
9673 | PIPE_CONF_CHECK_I(dp_m_n.link_n); |
9674 | PIPE_CONF_CHECK_I(dp_m_n.tu); |
9675 | |
9676 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9677 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); |
9678 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); |
9679 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); |
9680 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); |
9681 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); |
9682 | |
9683 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); |
9684 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); |
9685 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); |
9686 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); |
9687 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); |
9688 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); |
9689 | |
9690 | PIPE_CONF_CHECK_I(pixel_multiplier); |
9691 | |
9692 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9693 | DRM_MODE_FLAG_INTERLACE); |
9694 | |
9695 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
9696 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9697 | DRM_MODE_FLAG_PHSYNC); |
9698 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9699 | DRM_MODE_FLAG_NHSYNC); |
9700 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9701 | DRM_MODE_FLAG_PVSYNC); |
9702 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9703 | DRM_MODE_FLAG_NVSYNC); |
9704 | } |
9705 | |
9706 | PIPE_CONF_CHECK_I(pipe_src_w); |
9707 | PIPE_CONF_CHECK_I(pipe_src_h); |
9708 | |
9709 | /* |
9710 | * FIXME: BIOS likes to set up a cloned config with lvds+external |
9711 | * screen. Since we don't yet re-compute the pipe config when moving |
9712 | * just the lvds port away to another pipe the sw tracking won't match. |
9713 | * |
9714 | * Proper atomic modesets with recomputed global state will fix this. |
9715 | * Until then just don't check gmch state for inherited modes. |
9716 | */ |
9717 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { |
9718 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
9719 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
9720 | if (INTEL_INFO(dev)->gen < 4) |
9721 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
9722 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); |
9723 | } |
9724 | |
9725 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9726 | if (current_config->pch_pfit.enabled) { |
9727 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
9728 | PIPE_CONF_CHECK_I(pch_pfit.size); |
9729 | } |
9730 | |
9731 | /* BDW+ don't expose a synchronous way to read the state */ |
9732 | if (IS_HASWELL(dev)) |
9733 | PIPE_CONF_CHECK_I(ips_enabled); |
9734 | |
9735 | PIPE_CONF_CHECK_I(double_wide); |
9736 | |
9737 | PIPE_CONF_CHECK_I(shared_dpll); |
9738 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
9739 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
9740 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
9741 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
9742 | |
9743 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9744 | PIPE_CONF_CHECK_I(pipe_bpp); |
9745 | |
9746 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
9747 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
9748 | |
9749 | #undef PIPE_CONF_CHECK_X |
9750 | #undef PIPE_CONF_CHECK_I |
9751 | #undef PIPE_CONF_CHECK_FLAGS |
9752 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
9753 | #undef PIPE_CONF_QUIRK |
9754 | |
9755 | return true; |
9756 | } |
9757 | |
9758 | static void |
9759 | check_connector_state(struct drm_device *dev) |
9760 | { |
9761 | struct intel_connector *connector; |
9762 | |
9763 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9764 | base.head) { |
9765 | /* This also checks the encoder/connector hw state with the |
9766 | * ->get_hw_state callbacks. */ |
9767 | intel_connector_check_state(connector); |
9768 | |
9769 | WARN(&connector->new_encoder->base != connector->base.encoder, |
9770 | "connector's staged encoder doesn't match current encoder\n" ); |
9771 | } |
9772 | } |
9773 | |
9774 | static void |
9775 | check_encoder_state(struct drm_device *dev) |
9776 | { |
9777 | struct intel_encoder *encoder; |
9778 | struct intel_connector *connector; |
9779 | |
9780 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9781 | base.head) { |
9782 | bool enabled = false; |
9783 | bool active = false; |
9784 | enum i915_pipe pipe, tracked_pipe; |
9785 | |
9786 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n" , |
9787 | encoder->base.base.id, |
9788 | drm_get_encoder_name(&encoder->base)); |
9789 | |
9790 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
9791 | "encoder's stage crtc doesn't match current crtc\n" ); |
9792 | WARN(encoder->connectors_active && !encoder->base.crtc, |
9793 | "encoder's active_connectors set, but no crtc\n" ); |
9794 | |
9795 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9796 | base.head) { |
9797 | if (connector->base.encoder != &encoder->base) |
9798 | continue; |
9799 | enabled = true; |
9800 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
9801 | active = true; |
9802 | } |
9803 | WARN(!!encoder->base.crtc != enabled, |
9804 | "encoder's enabled state mismatch " |
9805 | "(expected %i, found %i)\n" , |
9806 | !!encoder->base.crtc, enabled); |
9807 | WARN(active && !encoder->base.crtc, |
9808 | "active encoder with no crtc\n" ); |
9809 | |
9810 | WARN(encoder->connectors_active != active, |
9811 | "encoder's computed active state doesn't match tracked active state " |
9812 | "(expected %i, found %i)\n" , active, encoder->connectors_active); |
9813 | |
9814 | active = encoder->get_hw_state(encoder, &pipe); |
9815 | WARN(active != encoder->connectors_active, |
9816 | "encoder's hw state doesn't match sw tracking " |
9817 | "(expected %i, found %i)\n" , |
9818 | encoder->connectors_active, active); |
9819 | |
9820 | if (!encoder->base.crtc) |
9821 | continue; |
9822 | |
9823 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
9824 | WARN(active && pipe != tracked_pipe, |
9825 | "active encoder's pipe doesn't match" |
9826 | "(expected %i, found %i)\n" , |
9827 | tracked_pipe, pipe); |
9828 | |
9829 | } |
9830 | } |
9831 | |
9832 | static void |
9833 | check_crtc_state(struct drm_device *dev) |
9834 | { |
9835 | struct drm_i915_private *dev_priv = dev->dev_private; |
9836 | struct intel_crtc *crtc; |
9837 | struct intel_encoder *encoder; |
9838 | struct intel_crtc_config pipe_config; |
9839 | |
9840 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
9841 | base.head) { |
9842 | bool enabled = false; |
9843 | bool active = false; |
9844 | |
9845 | memset(&pipe_config, 0, sizeof(pipe_config)); |
9846 | |
9847 | DRM_DEBUG_KMS("[CRTC:%d]\n" , |
9848 | crtc->base.base.id); |
9849 | |
9850 | WARN(crtc->active && !crtc->base.enabled, |
9851 | "active crtc, but not enabled in sw tracking\n" ); |
9852 | |
9853 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9854 | base.head) { |
9855 | if (encoder->base.crtc != &crtc->base) |
9856 | continue; |
9857 | enabled = true; |
9858 | if (encoder->connectors_active) |
9859 | active = true; |
9860 | } |
9861 | |
9862 | WARN(active != crtc->active, |
9863 | "crtc's computed active state doesn't match tracked active state " |
9864 | "(expected %i, found %i)\n" , active, crtc->active); |
9865 | WARN(enabled != crtc->base.enabled, |
9866 | "crtc's computed enabled state doesn't match tracked enabled state " |
9867 | "(expected %i, found %i)\n" , enabled, crtc->base.enabled); |
9868 | |
9869 | active = dev_priv->display.get_pipe_config(crtc, |
9870 | &pipe_config); |
9871 | |
9872 | /* hw state is inconsistent with the pipe A quirk */ |
9873 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
9874 | active = crtc->active; |
9875 | |
9876 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9877 | base.head) { |
9878 | enum i915_pipe pipe; |
9879 | if (encoder->base.crtc != &crtc->base) |
9880 | continue; |
9881 | if (encoder->get_hw_state(encoder, &pipe)) |
9882 | encoder->get_config(encoder, &pipe_config); |
9883 | } |
9884 | |
9885 | WARN(crtc->active != active, |
9886 | "crtc active state doesn't match with hw state " |
9887 | "(expected %i, found %i)\n" , crtc->active, active); |
9888 | |
9889 | if (active && |
9890 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { |
9891 | WARN(1, "pipe state doesn't match!\n" ); |
9892 | intel_dump_pipe_config(crtc, &pipe_config, |
9893 | "[hw state]" ); |
9894 | intel_dump_pipe_config(crtc, &crtc->config, |
9895 | "[sw state]" ); |
9896 | } |
9897 | } |
9898 | } |
9899 | |
9900 | static void |
9901 | check_shared_dpll_state(struct drm_device *dev) |
9902 | { |
9903 | struct drm_i915_private *dev_priv = dev->dev_private; |
9904 | struct intel_crtc *crtc; |
9905 | struct intel_dpll_hw_state dpll_hw_state; |
9906 | int i; |
9907 | |
9908 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
9909 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
9910 | int enabled_crtcs = 0, active_crtcs = 0; |
9911 | bool active; |
9912 | |
9913 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
9914 | |
9915 | DRM_DEBUG_KMS("%s\n" , pll->name); |
9916 | |
9917 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); |
9918 | |
9919 | WARN(pll->active > pll->refcount, |
9920 | "more active pll users than references: %i vs %i\n" , |
9921 | pll->active, pll->refcount); |
9922 | WARN(pll->active && !pll->on, |
9923 | "pll in active use but not on in sw tracking\n" ); |
9924 | WARN(pll->on && !pll->active, |
9925 | "pll in on but not on in use in sw tracking\n" ); |
9926 | WARN(pll->on != active, |
9927 | "pll on state mismatch (expected %i, found %i)\n" , |
9928 | pll->on, active); |
9929 | |
9930 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
9931 | base.head) { |
9932 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
9933 | enabled_crtcs++; |
9934 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
9935 | active_crtcs++; |
9936 | } |
9937 | WARN(pll->active != active_crtcs, |
9938 | "pll active crtcs mismatch (expected %i, found %i)\n" , |
9939 | pll->active, active_crtcs); |
9940 | WARN(pll->refcount != enabled_crtcs, |
9941 | "pll enabled crtcs mismatch (expected %i, found %i)\n" , |
9942 | pll->refcount, enabled_crtcs); |
9943 | |
9944 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, |
9945 | sizeof(dpll_hw_state)), |
9946 | "pll hw state mismatch\n" ); |
9947 | } |
9948 | } |
9949 | |
9950 | void |
9951 | intel_modeset_check_state(struct drm_device *dev) |
9952 | { |
9953 | check_connector_state(dev); |
9954 | check_encoder_state(dev); |
9955 | check_crtc_state(dev); |
9956 | check_shared_dpll_state(dev); |
9957 | } |
9958 | |
9959 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
9960 | int dotclock) |
9961 | { |
9962 | /* |
9963 | * FDI already provided one idea for the dotclock. |
9964 | * Yell if the encoder disagrees. |
9965 | */ |
9966 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
9967 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n" , |
9968 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
9969 | } |
9970 | |
9971 | static int __intel_set_mode(struct drm_crtc *crtc, |
9972 | struct drm_display_mode *mode, |
9973 | int x, int y, struct drm_framebuffer *fb) |
9974 | { |
9975 | struct drm_device *dev = crtc->dev; |
9976 | struct drm_i915_private *dev_priv = dev->dev_private; |
9977 | struct drm_display_mode *saved_mode; |
9978 | struct intel_crtc_config *pipe_config = NULL; |
9979 | struct intel_crtc *intel_crtc; |
9980 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
9981 | int ret = 0; |
9982 | |
9983 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
9984 | if (!saved_mode) |
9985 | return -ENOMEM; |
9986 | |
9987 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
9988 | &prepare_pipes, &disable_pipes); |
9989 | |
9990 | *saved_mode = crtc->mode; |
9991 | |
9992 | /* Hack: Because we don't (yet) support global modeset on multiple |
9993 | * crtcs, we don't keep track of the new mode for more than one crtc. |
9994 | * Hence simply check whether any bit is set in modeset_pipes in all the |
9995 | * pieces of code that are not yet converted to deal with mutliple crtcs |
9996 | * changing their mode at the same time. */ |
9997 | if (modeset_pipes) { |
9998 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
9999 | if (IS_ERR(pipe_config)) { |
10000 | ret = PTR_ERR(pipe_config); |
10001 | pipe_config = NULL; |
10002 | |
10003 | goto out; |
10004 | } |
10005 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
10006 | "[modeset]" ); |
10007 | to_intel_crtc(crtc)->new_config = pipe_config; |
10008 | } |
10009 | |
10010 | /* |
10011 | * See if the config requires any additional preparation, e.g. |
10012 | * to adjust global state with pipes off. We need to do this |
10013 | * here so we can get the modeset_pipe updated config for the new |
10014 | * mode set on this crtc. For other crtcs we need to use the |
10015 | * adjusted_mode bits in the crtc directly. |
10016 | */ |
10017 | if (IS_VALLEYVIEW(dev)) { |
10018 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
10019 | |
10020 | /* may have added more to prepare_pipes than we should */ |
10021 | prepare_pipes &= ~disable_pipes; |
10022 | } |
10023 | |
10024 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10025 | intel_crtc_disable(&intel_crtc->base); |
10026 | |
10027 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10028 | if (intel_crtc->base.enabled) |
10029 | dev_priv->display.crtc_disable(&intel_crtc->base); |
10030 | } |
10031 | |
10032 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10033 | * to set it here already despite that we pass it down the callchain. |
10034 | */ |
10035 | if (modeset_pipes) { |
10036 | crtc->mode = *mode; |
10037 | /* mode_set/enable/disable functions rely on a correct pipe |
10038 | * config. */ |
10039 | to_intel_crtc(crtc)->config = *pipe_config; |
10040 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
10041 | |
10042 | /* |
10043 | * Calculate and store various constants which |
10044 | * are later needed by vblank and swap-completion |
10045 | * timestamping. They are derived from true hwmode. |
10046 | */ |
10047 | drm_calc_timestamping_constants(crtc, |
10048 | &pipe_config->adjusted_mode); |
10049 | } |
10050 | |
10051 | /* Only after disabling all output pipelines that will be changed can we |
10052 | * update the the output configuration. */ |
10053 | intel_modeset_update_state(dev, prepare_pipes); |
10054 | |
10055 | if (dev_priv->display.modeset_global_resources) |
10056 | dev_priv->display.modeset_global_resources(dev); |
10057 | |
10058 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
10059 | * on the DPLL. |
10060 | */ |
10061 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
10062 | ret = intel_crtc_mode_set(&intel_crtc->base, |
10063 | x, y, fb); |
10064 | if (ret) |
10065 | goto done; |
10066 | } |
10067 | |
10068 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
10069 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
10070 | dev_priv->display.crtc_enable(&intel_crtc->base); |
10071 | |
10072 | /* FIXME: add subpixel order */ |
10073 | done: |
10074 | if (ret && crtc->enabled) |
10075 | crtc->mode = *saved_mode; |
10076 | |
10077 | out: |
10078 | kfree(pipe_config); |
10079 | kfree(saved_mode); |
10080 | return ret; |
10081 | } |
10082 | |
10083 | static int intel_set_mode(struct drm_crtc *crtc, |
10084 | struct drm_display_mode *mode, |
10085 | int x, int y, struct drm_framebuffer *fb) |
10086 | { |
10087 | int ret; |
10088 | |
10089 | ret = __intel_set_mode(crtc, mode, x, y, fb); |
10090 | |
10091 | if (ret == 0) |
10092 | intel_modeset_check_state(crtc->dev); |
10093 | |
10094 | return ret; |
10095 | } |
10096 | |
10097 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
10098 | { |
10099 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
10100 | } |
10101 | |
10102 | #undef for_each_intel_crtc_masked |
10103 | |
10104 | static void intel_set_config_free(struct intel_set_config *config) |
10105 | { |
10106 | if (!config) |
10107 | return; |
10108 | |
10109 | kfree(config->save_connector_encoders); |
10110 | kfree(config->save_encoder_crtcs); |
10111 | kfree(config->save_crtc_enabled); |
10112 | kfree(config); |
10113 | } |
10114 | |
10115 | static int intel_set_config_save_state(struct drm_device *dev, |
10116 | struct intel_set_config *config) |
10117 | { |
10118 | struct drm_crtc *crtc; |
10119 | struct drm_encoder *encoder; |
10120 | struct drm_connector *connector; |
10121 | int count; |
10122 | |
10123 | config->save_crtc_enabled = |
10124 | kcalloc(dev->mode_config.num_crtc, |
10125 | sizeof(bool), GFP_KERNEL); |
10126 | if (!config->save_crtc_enabled) |
10127 | return -ENOMEM; |
10128 | |
10129 | config->save_encoder_crtcs = |
10130 | kcalloc(dev->mode_config.num_encoder, |
10131 | sizeof(struct drm_crtc *), GFP_KERNEL); |
10132 | if (!config->save_encoder_crtcs) |
10133 | return -ENOMEM; |
10134 | |
10135 | config->save_connector_encoders = |
10136 | kcalloc(dev->mode_config.num_connector, |
10137 | sizeof(struct drm_encoder *), GFP_KERNEL); |
10138 | if (!config->save_connector_encoders) |
10139 | return -ENOMEM; |
10140 | |
10141 | /* Copy data. Note that driver private data is not affected. |
10142 | * Should anything bad happen only the expected state is |
10143 | * restored, not the drivers personal bookkeeping. |
10144 | */ |
10145 | count = 0; |
10146 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
10147 | config->save_crtc_enabled[count++] = crtc->enabled; |
10148 | } |
10149 | |
10150 | count = 0; |
10151 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
10152 | config->save_encoder_crtcs[count++] = encoder->crtc; |
10153 | } |
10154 | |
10155 | count = 0; |
10156 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
10157 | config->save_connector_encoders[count++] = connector->encoder; |
10158 | } |
10159 | |
10160 | return 0; |
10161 | } |
10162 | |
10163 | static void intel_set_config_restore_state(struct drm_device *dev, |
10164 | struct intel_set_config *config) |
10165 | { |
10166 | struct intel_crtc *crtc; |
10167 | struct intel_encoder *encoder; |
10168 | struct intel_connector *connector; |
10169 | int count; |
10170 | |
10171 | count = 0; |
10172 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
10173 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
10174 | |
10175 | if (crtc->new_enabled) |
10176 | crtc->new_config = &crtc->config; |
10177 | else |
10178 | crtc->new_config = NULL; |
10179 | } |
10180 | |
10181 | count = 0; |
10182 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10183 | encoder->new_crtc = |
10184 | to_intel_crtc(config->save_encoder_crtcs[count++]); |
10185 | } |
10186 | |
10187 | count = 0; |
10188 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
10189 | connector->new_encoder = |
10190 | to_intel_encoder(config->save_connector_encoders[count++]); |
10191 | } |
10192 | } |
10193 | |
10194 | static bool |
10195 | is_crtc_connector_off(struct drm_mode_set *set) |
10196 | { |
10197 | int i; |
10198 | |
10199 | if (set->num_connectors == 0) |
10200 | return false; |
10201 | |
10202 | if (WARN_ON(set->connectors == NULL)) |
10203 | return false; |
10204 | |
10205 | for (i = 0; i < set->num_connectors; i++) |
10206 | if (set->connectors[i]->encoder && |
10207 | set->connectors[i]->encoder->crtc == set->crtc && |
10208 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) |
10209 | return true; |
10210 | |
10211 | return false; |
10212 | } |
10213 | |
10214 | static void |
10215 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, |
10216 | struct intel_set_config *config) |
10217 | { |
10218 | |
10219 | /* We should be able to check here if the fb has the same properties |
10220 | * and then just flip_or_move it */ |
10221 | if (is_crtc_connector_off(set)) { |
10222 | config->mode_changed = true; |
10223 | } else if (set->crtc->primary->fb != set->fb) { |
10224 | /* If we have no fb then treat it as a full mode set */ |
10225 | if (set->crtc->primary->fb == NULL) { |
10226 | struct intel_crtc *intel_crtc = |
10227 | to_intel_crtc(set->crtc); |
10228 | |
10229 | if (intel_crtc->active && i915.fastboot) { |
10230 | DRM_DEBUG_KMS("crtc has no fb, will flip\n" ); |
10231 | config->fb_changed = true; |
10232 | } else { |
10233 | DRM_DEBUG_KMS("inactive crtc, full mode set\n" ); |
10234 | config->mode_changed = true; |
10235 | } |
10236 | } else if (set->fb == NULL) { |
10237 | config->mode_changed = true; |
10238 | } else if (set->fb->pixel_format != |
10239 | set->crtc->primary->fb->pixel_format) { |
10240 | config->mode_changed = true; |
10241 | } else { |
10242 | config->fb_changed = true; |
10243 | } |
10244 | } |
10245 | |
10246 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
10247 | config->fb_changed = true; |
10248 | |
10249 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { |
10250 | DRM_DEBUG_KMS("modes are different, full mode set\n" ); |
10251 | drm_mode_debug_printmodeline(&set->crtc->mode); |
10252 | drm_mode_debug_printmodeline(set->mode); |
10253 | config->mode_changed = true; |
10254 | } |
10255 | |
10256 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n" , |
10257 | set->crtc->base.id, config->mode_changed, config->fb_changed); |
10258 | } |
10259 | |
10260 | static int |
10261 | intel_modeset_stage_output_state(struct drm_device *dev, |
10262 | struct drm_mode_set *set, |
10263 | struct intel_set_config *config) |
10264 | { |
10265 | struct intel_connector *connector; |
10266 | struct intel_encoder *encoder; |
10267 | struct intel_crtc *crtc; |
10268 | int ro; |
10269 | |
10270 | /* The upper layers ensure that we either disable a crtc or have a list |
10271 | * of connectors. For paranoia, double-check this. */ |
10272 | WARN_ON(!set->fb && (set->num_connectors != 0)); |
10273 | WARN_ON(set->fb && (set->num_connectors == 0)); |
10274 | |
10275 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10276 | base.head) { |
10277 | /* Otherwise traverse passed in connector list and get encoders |
10278 | * for them. */ |
10279 | for (ro = 0; ro < set->num_connectors; ro++) { |
10280 | if (set->connectors[ro] == &connector->base) { |
10281 | connector->new_encoder = connector->encoder; |
10282 | break; |
10283 | } |
10284 | } |
10285 | |
10286 | /* If we disable the crtc, disable all its connectors. Also, if |
10287 | * the connector is on the changing crtc but not on the new |
10288 | * connector list, disable it. */ |
10289 | if ((!set->fb || ro == set->num_connectors) && |
10290 | connector->base.encoder && |
10291 | connector->base.encoder->crtc == set->crtc) { |
10292 | connector->new_encoder = NULL; |
10293 | |
10294 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n" , |
10295 | connector->base.base.id, |
10296 | drm_get_connector_name(&connector->base)); |
10297 | } |
10298 | |
10299 | |
10300 | if (&connector->new_encoder->base != connector->base.encoder) { |
10301 | DRM_DEBUG_KMS("encoder changed, full mode switch\n" ); |
10302 | config->mode_changed = true; |
10303 | } |
10304 | } |
10305 | /* connector->new_encoder is now updated for all connectors. */ |
10306 | |
10307 | /* Update crtc of enabled connectors. */ |
10308 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10309 | base.head) { |
10310 | struct drm_crtc *new_crtc; |
10311 | |
10312 | if (!connector->new_encoder) |
10313 | continue; |
10314 | |
10315 | new_crtc = connector->new_encoder->base.crtc; |
10316 | |
10317 | for (ro = 0; ro < set->num_connectors; ro++) { |
10318 | if (set->connectors[ro] == &connector->base) |
10319 | new_crtc = set->crtc; |
10320 | } |
10321 | |
10322 | /* Make sure the new CRTC will work with the encoder */ |
10323 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
10324 | new_crtc)) { |
10325 | return -EINVAL; |
10326 | } |
10327 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
10328 | |
10329 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n" , |
10330 | connector->base.base.id, |
10331 | drm_get_connector_name(&connector->base), |
10332 | new_crtc->base.id); |
10333 | } |
10334 | |
10335 | /* Check for any encoders that needs to be disabled. */ |
10336 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10337 | base.head) { |
10338 | int num_connectors = 0; |
10339 | list_for_each_entry(connector, |
10340 | &dev->mode_config.connector_list, |
10341 | base.head) { |
10342 | if (connector->new_encoder == encoder) { |
10343 | WARN_ON(!connector->new_encoder->new_crtc); |
10344 | num_connectors++; |
10345 | } |
10346 | } |
10347 | |
10348 | if (num_connectors == 0) |
10349 | encoder->new_crtc = NULL; |
10350 | else if (num_connectors > 1) |
10351 | return -EINVAL; |
10352 | |
10353 | /* Only now check for crtc changes so we don't miss encoders |
10354 | * that will be disabled. */ |
10355 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
10356 | DRM_DEBUG_KMS("crtc changed, full mode switch\n" ); |
10357 | config->mode_changed = true; |
10358 | } |
10359 | } |
10360 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
10361 | |
10362 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10363 | base.head) { |
10364 | crtc->new_enabled = false; |
10365 | |
10366 | list_for_each_entry(encoder, |
10367 | &dev->mode_config.encoder_list, |
10368 | base.head) { |
10369 | if (encoder->new_crtc == crtc) { |
10370 | crtc->new_enabled = true; |
10371 | break; |
10372 | } |
10373 | } |
10374 | |
10375 | if (crtc->new_enabled != crtc->base.enabled) { |
10376 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n" , |
10377 | crtc->new_enabled ? "en" : "dis" ); |
10378 | config->mode_changed = true; |
10379 | } |
10380 | |
10381 | if (crtc->new_enabled) |
10382 | crtc->new_config = &crtc->config; |
10383 | else |
10384 | crtc->new_config = NULL; |
10385 | } |
10386 | |
10387 | return 0; |
10388 | } |
10389 | |
10390 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
10391 | { |
10392 | struct drm_device *dev = crtc->base.dev; |
10393 | struct intel_encoder *encoder; |
10394 | struct intel_connector *connector; |
10395 | |
10396 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n" , |
10397 | pipe_name(crtc->pipe)); |
10398 | |
10399 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
10400 | if (connector->new_encoder && |
10401 | connector->new_encoder->new_crtc == crtc) |
10402 | connector->new_encoder = NULL; |
10403 | } |
10404 | |
10405 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10406 | if (encoder->new_crtc == crtc) |
10407 | encoder->new_crtc = NULL; |
10408 | } |
10409 | |
10410 | crtc->new_enabled = false; |
10411 | crtc->new_config = NULL; |
10412 | } |
10413 | |
10414 | static int intel_crtc_set_config(struct drm_mode_set *set) |
10415 | { |
10416 | struct drm_device *dev; |
10417 | struct drm_mode_set save_set; |
10418 | struct intel_set_config *config; |
10419 | int ret; |
10420 | |
10421 | BUG_ON(!set); |
10422 | BUG_ON(!set->crtc); |
10423 | BUG_ON(!set->crtc->helper_private); |
10424 | |
10425 | /* Enforce sane interface api - has been abused by the fb helper. */ |
10426 | BUG_ON(!set->mode && set->fb); |
10427 | BUG_ON(set->fb && set->num_connectors == 0); |
10428 | |
10429 | if (set->fb) { |
10430 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n" , |
10431 | set->crtc->base.id, set->fb->base.id, |
10432 | (int)set->num_connectors, set->x, set->y); |
10433 | } else { |
10434 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n" , set->crtc->base.id); |
10435 | } |
10436 | |
10437 | dev = set->crtc->dev; |
10438 | |
10439 | ret = -ENOMEM; |
10440 | config = kzalloc(sizeof(*config), GFP_KERNEL); |
10441 | if (!config) |
10442 | goto out_config; |
10443 | |
10444 | ret = intel_set_config_save_state(dev, config); |
10445 | if (ret) |
10446 | goto out_config; |
10447 | |
10448 | save_set.crtc = set->crtc; |
10449 | save_set.mode = &set->crtc->mode; |
10450 | save_set.x = set->crtc->x; |
10451 | save_set.y = set->crtc->y; |
10452 | save_set.fb = set->crtc->primary->fb; |
10453 | |
10454 | /* Compute whether we need a full modeset, only an fb base update or no |
10455 | * change at all. In the future we might also check whether only the |
10456 | * mode changed, e.g. for LVDS where we only change the panel fitter in |
10457 | * such cases. */ |
10458 | intel_set_config_compute_mode_changes(set, config); |
10459 | |
10460 | ret = intel_modeset_stage_output_state(dev, set, config); |
10461 | if (ret) |
10462 | goto fail; |
10463 | |
10464 | if (config->mode_changed) { |
10465 | ret = intel_set_mode(set->crtc, set->mode, |
10466 | set->x, set->y, set->fb); |
10467 | } else if (config->fb_changed) { |
10468 | intel_crtc_wait_for_pending_flips(set->crtc); |
10469 | |
10470 | ret = intel_pipe_set_base(set->crtc, |
10471 | set->x, set->y, set->fb); |
10472 | /* |
10473 | * In the fastboot case this may be our only check of the |
10474 | * state after boot. It would be better to only do it on |
10475 | * the first update, but we don't have a nice way of doing that |
10476 | * (and really, set_config isn't used much for high freq page |
10477 | * flipping, so increasing its cost here shouldn't be a big |
10478 | * deal). |
10479 | */ |
10480 | if (i915.fastboot && ret == 0) |
10481 | intel_modeset_check_state(set->crtc->dev); |
10482 | } |
10483 | |
10484 | if (ret) { |
10485 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n" , |
10486 | set->crtc->base.id, ret); |
10487 | fail: |
10488 | intel_set_config_restore_state(dev, config); |
10489 | |
10490 | /* |
10491 | * HACK: if the pipe was on, but we didn't have a framebuffer, |
10492 | * force the pipe off to avoid oopsing in the modeset code |
10493 | * due to fb==NULL. This should only happen during boot since |
10494 | * we don't yet reconstruct the FB from the hardware state. |
10495 | */ |
10496 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) |
10497 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); |
10498 | |
10499 | /* Try to restore the config */ |
10500 | if (config->mode_changed && |
10501 | intel_set_mode(save_set.crtc, save_set.mode, |
10502 | save_set.x, save_set.y, save_set.fb)) |
10503 | DRM_ERROR("failed to restore config after modeset failure\n" ); |
10504 | } |
10505 | |
10506 | out_config: |
10507 | intel_set_config_free(config); |
10508 | return ret; |
10509 | } |
10510 | |
10511 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
10512 | .cursor_set = intel_crtc_cursor_set, |
10513 | .cursor_move = intel_crtc_cursor_move, |
10514 | .gamma_set = intel_crtc_gamma_set, |
10515 | .set_config = intel_crtc_set_config, |
10516 | .destroy = intel_crtc_destroy, |
10517 | .page_flip = intel_crtc_page_flip, |
10518 | }; |
10519 | |
10520 | static void intel_cpu_pll_init(struct drm_device *dev) |
10521 | { |
10522 | if (HAS_DDI(dev)) |
10523 | intel_ddi_pll_init(dev); |
10524 | } |
10525 | |
10526 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
10527 | struct intel_shared_dpll *pll, |
10528 | struct intel_dpll_hw_state *hw_state) |
10529 | { |
10530 | uint32_t val; |
10531 | |
10532 | val = I915_READ(PCH_DPLL(pll->id)); |
10533 | hw_state->dpll = val; |
10534 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
10535 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
10536 | |
10537 | return val & DPLL_VCO_ENABLE; |
10538 | } |
10539 | |
10540 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10541 | struct intel_shared_dpll *pll) |
10542 | { |
10543 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); |
10544 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); |
10545 | } |
10546 | |
10547 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10548 | struct intel_shared_dpll *pll) |
10549 | { |
10550 | /* PCH refclock must be enabled first */ |
10551 | ibx_assert_pch_refclk_enabled(dev_priv); |
10552 | |
10553 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10554 | |
10555 | /* Wait for the clocks to stabilize. */ |
10556 | POSTING_READ(PCH_DPLL(pll->id)); |
10557 | udelay(150); |
10558 | |
10559 | /* The pixel multiplier can only be updated once the |
10560 | * DPLL is enabled and the clocks are stable. |
10561 | * |
10562 | * So write it again. |
10563 | */ |
10564 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10565 | POSTING_READ(PCH_DPLL(pll->id)); |
10566 | udelay(200); |
10567 | } |
10568 | |
10569 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, |
10570 | struct intel_shared_dpll *pll) |
10571 | { |
10572 | struct drm_device *dev = dev_priv->dev; |
10573 | struct intel_crtc *crtc; |
10574 | |
10575 | /* Make sure no transcoder isn't still depending on us. */ |
10576 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
10577 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
10578 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
10579 | } |
10580 | |
10581 | I915_WRITE(PCH_DPLL(pll->id), 0); |
10582 | POSTING_READ(PCH_DPLL(pll->id)); |
10583 | udelay(200); |
10584 | } |
10585 | |
10586 | static const char *ibx_pch_dpll_names[] = { |
10587 | "PCH DPLL A" , |
10588 | "PCH DPLL B" , |
10589 | }; |
10590 | |
10591 | static void ibx_pch_dpll_init(struct drm_device *dev) |
10592 | { |
10593 | struct drm_i915_private *dev_priv = dev->dev_private; |
10594 | int i; |
10595 | |
10596 | dev_priv->num_shared_dpll = 2; |
10597 | |
10598 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10599 | dev_priv->shared_dplls[i].id = i; |
10600 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; |
10601 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
10602 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
10603 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; |
10604 | dev_priv->shared_dplls[i].get_hw_state = |
10605 | ibx_pch_dpll_get_hw_state; |
10606 | } |
10607 | } |
10608 | |
10609 | static void intel_shared_dpll_init(struct drm_device *dev) |
10610 | { |
10611 | struct drm_i915_private *dev_priv = dev->dev_private; |
10612 | |
10613 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
10614 | ibx_pch_dpll_init(dev); |
10615 | else |
10616 | dev_priv->num_shared_dpll = 0; |
10617 | |
10618 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
10619 | } |
10620 | |
10621 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
10622 | { |
10623 | struct drm_i915_private *dev_priv = dev->dev_private; |
10624 | struct intel_crtc *intel_crtc; |
10625 | int i; |
10626 | |
10627 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
10628 | if (intel_crtc == NULL) |
10629 | return; |
10630 | |
10631 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
10632 | |
10633 | if (IS_GEN2(dev)) { |
10634 | intel_crtc->max_cursor_width = GEN2_CURSOR_WIDTH; |
10635 | intel_crtc->max_cursor_height = GEN2_CURSOR_HEIGHT; |
10636 | } else { |
10637 | intel_crtc->max_cursor_width = CURSOR_WIDTH; |
10638 | intel_crtc->max_cursor_height = CURSOR_HEIGHT; |
10639 | } |
10640 | dev->mode_config.cursor_width = intel_crtc->max_cursor_width; |
10641 | dev->mode_config.cursor_height = intel_crtc->max_cursor_height; |
10642 | |
10643 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
10644 | for (i = 0; i < 256; i++) { |
10645 | intel_crtc->lut_r[i] = i; |
10646 | intel_crtc->lut_g[i] = i; |
10647 | intel_crtc->lut_b[i] = i; |
10648 | } |
10649 | |
10650 | /* |
10651 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port |
10652 | * is hooked to plane B. Hence we want plane A feeding pipe B. |
10653 | */ |
10654 | intel_crtc->pipe = pipe; |
10655 | intel_crtc->plane = pipe; |
10656 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
10657 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n" ); |
10658 | intel_crtc->plane = !pipe; |
10659 | } |
10660 | |
10661 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
10662 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
10663 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
10664 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
10665 | |
10666 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
10667 | } |
10668 | |
10669 | enum i915_pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
10670 | { |
10671 | struct drm_encoder *encoder = connector->base.encoder; |
10672 | |
10673 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); |
10674 | |
10675 | if (!encoder) |
10676 | return INVALID_PIPE; |
10677 | |
10678 | return to_intel_crtc(encoder->crtc)->pipe; |
10679 | } |
10680 | |
10681 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
10682 | struct drm_file *file) |
10683 | { |
10684 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
10685 | struct drm_mode_object *drmmode_obj; |
10686 | struct intel_crtc *crtc; |
10687 | |
10688 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
10689 | return -ENODEV; |
10690 | |
10691 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
10692 | DRM_MODE_OBJECT_CRTC); |
10693 | |
10694 | if (!drmmode_obj) { |
10695 | DRM_ERROR("no such CRTC id\n" ); |
10696 | return -ENOENT; |
10697 | } |
10698 | |
10699 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
10700 | pipe_from_crtc_id->pipe = crtc->pipe; |
10701 | |
10702 | return 0; |
10703 | } |
10704 | |
10705 | static int intel_encoder_clones(struct intel_encoder *encoder) |
10706 | { |
10707 | struct drm_device *dev = encoder->base.dev; |
10708 | struct intel_encoder *source_encoder; |
10709 | int index_mask = 0; |
10710 | int entry = 0; |
10711 | |
10712 | list_for_each_entry(source_encoder, |
10713 | &dev->mode_config.encoder_list, base.head) { |
10714 | if (encoders_cloneable(encoder, source_encoder)) |
10715 | index_mask |= (1 << entry); |
10716 | |
10717 | entry++; |
10718 | } |
10719 | |
10720 | return index_mask; |
10721 | } |
10722 | |
10723 | static bool has_edp_a(struct drm_device *dev) |
10724 | { |
10725 | struct drm_i915_private *dev_priv = dev->dev_private; |
10726 | |
10727 | if (!IS_MOBILE(dev)) |
10728 | return false; |
10729 | |
10730 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
10731 | return false; |
10732 | |
10733 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
10734 | return false; |
10735 | |
10736 | return true; |
10737 | } |
10738 | |
10739 | const char *intel_output_name(int output) |
10740 | { |
10741 | static const char *names[] = { |
10742 | [INTEL_OUTPUT_UNUSED] = "Unused" , |
10743 | [INTEL_OUTPUT_ANALOG] = "Analog" , |
10744 | [INTEL_OUTPUT_DVO] = "DVO" , |
10745 | [INTEL_OUTPUT_SDVO] = "SDVO" , |
10746 | [INTEL_OUTPUT_LVDS] = "LVDS" , |
10747 | [INTEL_OUTPUT_TVOUT] = "TV" , |
10748 | [INTEL_OUTPUT_HDMI] = "HDMI" , |
10749 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort" , |
10750 | [INTEL_OUTPUT_EDP] = "eDP" , |
10751 | [INTEL_OUTPUT_DSI] = "DSI" , |
10752 | [INTEL_OUTPUT_UNKNOWN] = "Unknown" , |
10753 | }; |
10754 | |
10755 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) |
10756 | return "Invalid" ; |
10757 | |
10758 | return names[output]; |
10759 | } |
10760 | |
10761 | static void intel_setup_outputs(struct drm_device *dev) |
10762 | { |
10763 | struct drm_i915_private *dev_priv = dev->dev_private; |
10764 | struct intel_encoder *encoder; |
10765 | bool dpd_is_edp = false; |
10766 | |
10767 | intel_lvds_init(dev); |
10768 | |
10769 | if (!IS_ULT(dev)) |
10770 | intel_crt_init(dev); |
10771 | |
10772 | if (HAS_DDI(dev)) { |
10773 | int found; |
10774 | |
10775 | /* Haswell uses DDI functions to detect digital outputs */ |
10776 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
10777 | /* DDI A only supports eDP */ |
10778 | if (found) |
10779 | intel_ddi_init(dev, PORT_A); |
10780 | |
10781 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
10782 | * register */ |
10783 | found = I915_READ(SFUSE_STRAP); |
10784 | |
10785 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
10786 | intel_ddi_init(dev, PORT_B); |
10787 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
10788 | intel_ddi_init(dev, PORT_C); |
10789 | if (found & SFUSE_STRAP_DDID_DETECTED) |
10790 | intel_ddi_init(dev, PORT_D); |
10791 | } else if (HAS_PCH_SPLIT(dev)) { |
10792 | int found; |
10793 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
10794 | |
10795 | if (has_edp_a(dev)) |
10796 | intel_dp_init(dev, DP_A, PORT_A); |
10797 | |
10798 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
10799 | /* PCH SDVOB multiplex with HDMIB */ |
10800 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
10801 | if (!found) |
10802 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
10803 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
10804 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
10805 | } |
10806 | |
10807 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
10808 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
10809 | |
10810 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
10811 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
10812 | |
10813 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
10814 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
10815 | |
10816 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
10817 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
10818 | } else if (IS_VALLEYVIEW(dev)) { |
10819 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
10820 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
10821 | PORT_B); |
10822 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
10823 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); |
10824 | } |
10825 | |
10826 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
10827 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
10828 | PORT_C); |
10829 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
10830 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
10831 | } |
10832 | |
10833 | intel_dsi_init(dev); |
10834 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
10835 | bool found = false; |
10836 | |
10837 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
10838 | DRM_DEBUG_KMS("probing SDVOB\n" ); |
10839 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
10840 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
10841 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n" ); |
10842 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
10843 | } |
10844 | |
10845 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
10846 | intel_dp_init(dev, DP_B, PORT_B); |
10847 | } |
10848 | |
10849 | /* Before G4X SDVOC doesn't have its own detect register */ |
10850 | |
10851 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
10852 | DRM_DEBUG_KMS("probing SDVOC\n" ); |
10853 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
10854 | } |
10855 | |
10856 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
10857 | |
10858 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
10859 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n" ); |
10860 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
10861 | } |
10862 | if (SUPPORTS_INTEGRATED_DP(dev)) |
10863 | intel_dp_init(dev, DP_C, PORT_C); |
10864 | } |
10865 | |
10866 | if (SUPPORTS_INTEGRATED_DP(dev) && |
10867 | (I915_READ(DP_D) & DP_DETECTED)) |
10868 | intel_dp_init(dev, DP_D, PORT_D); |
10869 | } else if (IS_GEN2(dev)) |
10870 | intel_dvo_init(dev); |
10871 | |
10872 | if (SUPPORTS_TV(dev)) |
10873 | intel_tv_init(dev); |
10874 | |
10875 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10876 | encoder->base.possible_crtcs = encoder->crtc_mask; |
10877 | encoder->base.possible_clones = |
10878 | intel_encoder_clones(encoder); |
10879 | } |
10880 | |
10881 | intel_init_pch_refclk(dev); |
10882 | |
10883 | drm_helper_move_panel_connectors_to_head(dev); |
10884 | } |
10885 | |
10886 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
10887 | { |
10888 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
10889 | |
10890 | drm_framebuffer_cleanup(fb); |
10891 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
10892 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
10893 | kfree(intel_fb); |
10894 | } |
10895 | |
10896 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
10897 | struct drm_file *file, |
10898 | unsigned int *handle) |
10899 | { |
10900 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
10901 | struct drm_i915_gem_object *obj = intel_fb->obj; |
10902 | |
10903 | return drm_gem_handle_create(file, &obj->base, handle); |
10904 | } |
10905 | |
10906 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
10907 | .destroy = intel_user_framebuffer_destroy, |
10908 | .create_handle = intel_user_framebuffer_create_handle, |
10909 | }; |
10910 | |
10911 | static int intel_framebuffer_init(struct drm_device *dev, |
10912 | struct intel_framebuffer *intel_fb, |
10913 | struct drm_mode_fb_cmd2 *mode_cmd, |
10914 | struct drm_i915_gem_object *obj) |
10915 | { |
10916 | int aligned_height; |
10917 | int pitch_limit; |
10918 | int ret; |
10919 | |
10920 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
10921 | |
10922 | if (obj->tiling_mode == I915_TILING_Y) { |
10923 | DRM_DEBUG("hardware does not support tiling Y\n" ); |
10924 | return -EINVAL; |
10925 | } |
10926 | |
10927 | if (mode_cmd->pitches[0] & 63) { |
10928 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n" , |
10929 | mode_cmd->pitches[0]); |
10930 | return -EINVAL; |
10931 | } |
10932 | |
10933 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
10934 | pitch_limit = 32*1024; |
10935 | } else if (INTEL_INFO(dev)->gen >= 4) { |
10936 | if (obj->tiling_mode) |
10937 | pitch_limit = 16*1024; |
10938 | else |
10939 | pitch_limit = 32*1024; |
10940 | } else if (INTEL_INFO(dev)->gen >= 3) { |
10941 | if (obj->tiling_mode) |
10942 | pitch_limit = 8*1024; |
10943 | else |
10944 | pitch_limit = 16*1024; |
10945 | } else |
10946 | /* XXX DSPC is limited to 4k tiled */ |
10947 | pitch_limit = 8*1024; |
10948 | |
10949 | if (mode_cmd->pitches[0] > pitch_limit) { |
10950 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n" , |
10951 | obj->tiling_mode ? "tiled" : "linear" , |
10952 | mode_cmd->pitches[0], pitch_limit); |
10953 | return -EINVAL; |
10954 | } |
10955 | |
10956 | if (obj->tiling_mode != I915_TILING_NONE && |
10957 | mode_cmd->pitches[0] != obj->stride) { |
10958 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n" , |
10959 | mode_cmd->pitches[0], obj->stride); |
10960 | return -EINVAL; |
10961 | } |
10962 | |
10963 | /* Reject formats not supported by any plane early. */ |
10964 | switch (mode_cmd->pixel_format) { |
10965 | case DRM_FORMAT_C8: |
10966 | case DRM_FORMAT_RGB565: |
10967 | case DRM_FORMAT_XRGB8888: |
10968 | case DRM_FORMAT_ARGB8888: |
10969 | break; |
10970 | case DRM_FORMAT_XRGB1555: |
10971 | case DRM_FORMAT_ARGB1555: |
10972 | if (INTEL_INFO(dev)->gen > 3) { |
10973 | DRM_DEBUG("unsupported pixel format: %s\n" , |
10974 | drm_get_format_name(mode_cmd->pixel_format)); |
10975 | return -EINVAL; |
10976 | } |
10977 | break; |
10978 | case DRM_FORMAT_XBGR8888: |
10979 | case DRM_FORMAT_ABGR8888: |
10980 | case DRM_FORMAT_XRGB2101010: |
10981 | case DRM_FORMAT_ARGB2101010: |
10982 | case DRM_FORMAT_XBGR2101010: |
10983 | case DRM_FORMAT_ABGR2101010: |
10984 | if (INTEL_INFO(dev)->gen < 4) { |
10985 | DRM_DEBUG("unsupported pixel format: %s\n" , |
10986 | drm_get_format_name(mode_cmd->pixel_format)); |
10987 | return -EINVAL; |
10988 | } |
10989 | break; |
10990 | case DRM_FORMAT_YUYV: |
10991 | case DRM_FORMAT_UYVY: |
10992 | case DRM_FORMAT_YVYU: |
10993 | case DRM_FORMAT_VYUY: |
10994 | if (INTEL_INFO(dev)->gen < 5) { |
10995 | DRM_DEBUG("unsupported pixel format: %s\n" , |
10996 | drm_get_format_name(mode_cmd->pixel_format)); |
10997 | return -EINVAL; |
10998 | } |
10999 | break; |
11000 | default: |
11001 | DRM_DEBUG("unsupported pixel format: %s\n" , |
11002 | drm_get_format_name(mode_cmd->pixel_format)); |
11003 | return -EINVAL; |
11004 | } |
11005 | |
11006 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
11007 | if (mode_cmd->offsets[0] != 0) |
11008 | return -EINVAL; |
11009 | |
11010 | aligned_height = intel_align_height(dev, mode_cmd->height, |
11011 | obj->tiling_mode); |
11012 | /* FIXME drm helper for size checks (especially planar formats)? */ |
11013 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) |
11014 | return -EINVAL; |
11015 | |
11016 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
11017 | intel_fb->obj = obj; |
11018 | intel_fb->obj->framebuffer_references++; |
11019 | |
11020 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
11021 | if (ret) { |
11022 | DRM_ERROR("framebuffer init failed %d\n" , ret); |
11023 | return ret; |
11024 | } |
11025 | |
11026 | return 0; |
11027 | } |
11028 | |
11029 | static struct drm_framebuffer * |
11030 | intel_user_framebuffer_create(struct drm_device *dev, |
11031 | struct drm_file *filp, |
11032 | struct drm_mode_fb_cmd2 *mode_cmd) |
11033 | { |
11034 | struct drm_gem_object *gobj; |
11035 | struct drm_i915_gem_object *obj; |
11036 | |
11037 | gobj = drm_gem_object_lookup(dev, filp, mode_cmd->handles[0]); |
11038 | if (gobj == NULL) |
11039 | return ERR_PTR(-ENOENT); |
11040 | obj = to_intel_bo(gobj); |
11041 | |
11042 | return intel_framebuffer_create(dev, mode_cmd, obj); |
11043 | } |
11044 | |
11045 | #ifndef CONFIG_DRM_I915_FBDEV |
11046 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
11047 | { |
11048 | } |
11049 | #endif |
11050 | |
11051 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
11052 | .fb_create = intel_user_framebuffer_create, |
11053 | .output_poll_changed = intel_fbdev_output_poll_changed, |
11054 | }; |
11055 | |
11056 | /* Set up chip specific display functions */ |
11057 | static void intel_init_display(struct drm_device *dev) |
11058 | { |
11059 | struct drm_i915_private *dev_priv = dev->dev_private; |
11060 | |
11061 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
11062 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
11063 | else if (IS_VALLEYVIEW(dev)) |
11064 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
11065 | else if (IS_PINEVIEW(dev)) |
11066 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
11067 | else |
11068 | dev_priv->display.find_dpll = i9xx_find_best_dpll; |
11069 | |
11070 | if (HAS_DDI(dev)) { |
11071 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
11072 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
11073 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
11074 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
11075 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
11076 | dev_priv->display.off = haswell_crtc_off; |
11077 | dev_priv->display.update_primary_plane = |
11078 | ironlake_update_primary_plane; |
11079 | } else if (HAS_PCH_SPLIT(dev)) { |
11080 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
11081 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
11082 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
11083 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
11084 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
11085 | dev_priv->display.off = ironlake_crtc_off; |
11086 | dev_priv->display.update_primary_plane = |
11087 | ironlake_update_primary_plane; |
11088 | } else if (IS_VALLEYVIEW(dev)) { |
11089 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
11090 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
11091 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
11092 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
11093 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
11094 | dev_priv->display.off = i9xx_crtc_off; |
11095 | dev_priv->display.update_primary_plane = |
11096 | i9xx_update_primary_plane; |
11097 | } else { |
11098 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
11099 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
11100 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
11101 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
11102 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
11103 | dev_priv->display.off = i9xx_crtc_off; |
11104 | dev_priv->display.update_primary_plane = |
11105 | i9xx_update_primary_plane; |
11106 | } |
11107 | |
11108 | /* Returns the core display clock speed */ |
11109 | if (IS_VALLEYVIEW(dev)) |
11110 | dev_priv->display.get_display_clock_speed = |
11111 | valleyview_get_display_clock_speed; |
11112 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
11113 | dev_priv->display.get_display_clock_speed = |
11114 | i945_get_display_clock_speed; |
11115 | else if (IS_I915G(dev)) |
11116 | dev_priv->display.get_display_clock_speed = |
11117 | i915_get_display_clock_speed; |
11118 | else if (IS_I945GM(dev) || IS_845G(dev)) |
11119 | dev_priv->display.get_display_clock_speed = |
11120 | i9xx_misc_get_display_clock_speed; |
11121 | else if (IS_PINEVIEW(dev)) |
11122 | dev_priv->display.get_display_clock_speed = |
11123 | pnv_get_display_clock_speed; |
11124 | else if (IS_I915GM(dev)) |
11125 | dev_priv->display.get_display_clock_speed = |
11126 | i915gm_get_display_clock_speed; |
11127 | else if (IS_I865G(dev)) |
11128 | dev_priv->display.get_display_clock_speed = |
11129 | i865_get_display_clock_speed; |
11130 | else if (IS_I85X(dev)) |
11131 | dev_priv->display.get_display_clock_speed = |
11132 | i855_get_display_clock_speed; |
11133 | else /* 852, 830 */ |
11134 | dev_priv->display.get_display_clock_speed = |
11135 | i830_get_display_clock_speed; |
11136 | |
11137 | if (HAS_PCH_SPLIT(dev)) { |
11138 | if (IS_GEN5(dev)) { |
11139 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
11140 | dev_priv->display.write_eld = ironlake_write_eld; |
11141 | } else if (IS_GEN6(dev)) { |
11142 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
11143 | dev_priv->display.write_eld = ironlake_write_eld; |
11144 | } else if (IS_IVYBRIDGE(dev)) { |
11145 | /* FIXME: detect B0+ stepping and use auto training */ |
11146 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
11147 | dev_priv->display.write_eld = ironlake_write_eld; |
11148 | dev_priv->display.modeset_global_resources = |
11149 | ivb_modeset_global_resources; |
11150 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
11151 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
11152 | dev_priv->display.write_eld = haswell_write_eld; |
11153 | dev_priv->display.modeset_global_resources = |
11154 | haswell_modeset_global_resources; |
11155 | } |
11156 | } else if (IS_G4X(dev)) { |
11157 | dev_priv->display.write_eld = g4x_write_eld; |
11158 | } else if (IS_VALLEYVIEW(dev)) { |
11159 | dev_priv->display.modeset_global_resources = |
11160 | valleyview_modeset_global_resources; |
11161 | dev_priv->display.write_eld = ironlake_write_eld; |
11162 | } |
11163 | |
11164 | /* Default just returns -ENODEV to indicate unsupported */ |
11165 | dev_priv->display.queue_flip = intel_default_queue_flip; |
11166 | |
11167 | switch (INTEL_INFO(dev)->gen) { |
11168 | case 2: |
11169 | dev_priv->display.queue_flip = intel_gen2_queue_flip; |
11170 | break; |
11171 | |
11172 | case 3: |
11173 | dev_priv->display.queue_flip = intel_gen3_queue_flip; |
11174 | break; |
11175 | |
11176 | case 4: |
11177 | case 5: |
11178 | dev_priv->display.queue_flip = intel_gen4_queue_flip; |
11179 | break; |
11180 | |
11181 | case 6: |
11182 | dev_priv->display.queue_flip = intel_gen6_queue_flip; |
11183 | break; |
11184 | case 7: |
11185 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
11186 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
11187 | break; |
11188 | } |
11189 | |
11190 | intel_panel_init_backlight_funcs(dev); |
11191 | } |
11192 | |
11193 | /* |
11194 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
11195 | * resume, or other times. This quirk makes sure that's the case for |
11196 | * affected systems. |
11197 | */ |
11198 | static void quirk_pipea_force(struct drm_device *dev) |
11199 | { |
11200 | struct drm_i915_private *dev_priv = dev->dev_private; |
11201 | |
11202 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
11203 | DRM_INFO("applying pipe a force quirk\n" ); |
11204 | } |
11205 | |
11206 | /* |
11207 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
11208 | */ |
11209 | static void quirk_ssc_force_disable(struct drm_device *dev) |
11210 | { |
11211 | struct drm_i915_private *dev_priv = dev->dev_private; |
11212 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
11213 | DRM_INFO("applying lvds SSC disable quirk\n" ); |
11214 | } |
11215 | |
11216 | /* |
11217 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
11218 | * brightness value |
11219 | */ |
11220 | static void quirk_invert_brightness(struct drm_device *dev) |
11221 | { |
11222 | struct drm_i915_private *dev_priv = dev->dev_private; |
11223 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
11224 | DRM_INFO("applying inverted panel brightness quirk\n" ); |
11225 | } |
11226 | |
11227 | struct intel_quirk { |
11228 | int device; |
11229 | int subsystem_vendor; |
11230 | int subsystem_device; |
11231 | void (*hook)(struct drm_device *dev); |
11232 | }; |
11233 | |
11234 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
11235 | struct intel_dmi_quirk { |
11236 | void (*hook)(struct drm_device *dev); |
11237 | const struct dmi_system_id (*dmi_id_list)[]; |
11238 | }; |
11239 | |
11240 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
11241 | { |
11242 | DRM_INFO("Backlight polarity reversed on %s\n" , id->ident); |
11243 | return 1; |
11244 | } |
11245 | |
11246 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
11247 | { |
11248 | .dmi_id_list = &(const struct dmi_system_id[]) { |
11249 | { |
11250 | .callback = intel_dmi_reverse_brightness, |
11251 | .ident = "NCR Corporation" , |
11252 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation" ), |
11253 | DMI_MATCH(DMI_PRODUCT_NAME, "" ), |
11254 | }, |
11255 | }, |
11256 | { .callback = NULL } /* terminating entry */ |
11257 | }, |
11258 | .hook = quirk_invert_brightness, |
11259 | }, |
11260 | }; |
11261 | |
11262 | static struct intel_quirk intel_quirks[] = { |
11263 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
11264 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
11265 | |
11266 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
11267 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
11268 | |
11269 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
11270 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
11271 | |
11272 | /* 830 needs to leave pipe A & dpll A up */ |
11273 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
11274 | |
11275 | /* Lenovo U160 cannot use SSC on LVDS */ |
11276 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
11277 | |
11278 | /* Sony Vaio Y cannot use SSC on LVDS */ |
11279 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
11280 | |
11281 | /* Acer Aspire 5734Z must invert backlight brightness */ |
11282 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
11283 | |
11284 | /* Acer/eMachines G725 */ |
11285 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, |
11286 | |
11287 | /* Acer/eMachines e725 */ |
11288 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, |
11289 | |
11290 | /* Acer/Packard Bell NCL20 */ |
11291 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
11292 | |
11293 | /* Acer Aspire 4736Z */ |
11294 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
11295 | |
11296 | /* Acer Aspire 5336 */ |
11297 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, |
11298 | }; |
11299 | |
11300 | static void intel_init_quirks(struct drm_device *dev) |
11301 | { |
11302 | struct pci_dev *d = dev->pdev; |
11303 | int i; |
11304 | |
11305 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
11306 | struct intel_quirk *q = &intel_quirks[i]; |
11307 | |
11308 | if (d->device == q->device && |
11309 | (d->subsystem_vendor == q->subsystem_vendor || |
11310 | q->subsystem_vendor == PCI_ANY_ID) && |
11311 | (d->subsystem_device == q->subsystem_device || |
11312 | q->subsystem_device == PCI_ANY_ID)) |
11313 | q->hook(dev); |
11314 | } |
11315 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
11316 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) |
11317 | intel_dmi_quirks[i].hook(dev); |
11318 | } |
11319 | } |
11320 | |
11321 | /* Disable the VGA plane that we never use */ |
11322 | void i915_disable_vga(struct drm_device *dev) |
11323 | { |
11324 | struct drm_i915_private *dev_priv = dev->dev_private; |
11325 | u8 sr1; |
11326 | u32 vga_reg = i915_vgacntrl_reg(dev); |
11327 | |
11328 | #ifdef __NetBSD__ |
11329 | { |
11330 | const bus_addr_t vgabase = 0x3c0; |
11331 | const bus_space_tag_t iot = dev->pdev->pd_pa.pa_iot; |
11332 | bus_space_handle_t ioh; |
11333 | int error; |
11334 | |
11335 | error = bus_space_map(iot, vgabase, 0x10, 0, &ioh); |
11336 | if (error) { |
11337 | aprint_error_dev(dev->pdev->pd_dev, |
11338 | "unable to map VGA registers: %d\n" , error); |
11339 | } else { |
11340 | CTASSERT(vgabase <= VGA_SR_INDEX); |
11341 | CTASSERT(vgabase <= VGA_SR_DATA); |
11342 | bus_space_write_1(iot, ioh, VGA_SR_INDEX - vgabase, SR01); |
11343 | sr1 = bus_space_read_1(iot, ioh, VGA_SR_DATA - vgabase); |
11344 | bus_space_write_1(iot, ioh, VGA_SR_DATA - vgabase, |
11345 | (sr1 | __BIT(5))); |
11346 | bus_space_unmap(iot, ioh, 0x10); |
11347 | } |
11348 | } |
11349 | #else |
11350 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
11351 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
11352 | outb(SR01, VGA_SR_INDEX); |
11353 | sr1 = inb(VGA_SR_DATA); |
11354 | outb(sr1 | 1<<5, VGA_SR_DATA); |
11355 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
11356 | #endif |
11357 | udelay(300); |
11358 | |
11359 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
11360 | POSTING_READ(vga_reg); |
11361 | } |
11362 | |
11363 | void intel_modeset_init_hw(struct drm_device *dev) |
11364 | { |
11365 | intel_prepare_ddi(dev); |
11366 | |
11367 | intel_init_clock_gating(dev); |
11368 | |
11369 | intel_reset_dpio(dev); |
11370 | |
11371 | mutex_lock(&dev->struct_mutex); |
11372 | intel_enable_gt_powersave(dev); |
11373 | mutex_unlock(&dev->struct_mutex); |
11374 | } |
11375 | |
11376 | void intel_modeset_suspend_hw(struct drm_device *dev) |
11377 | { |
11378 | intel_suspend_hw(dev); |
11379 | } |
11380 | |
11381 | void intel_modeset_init(struct drm_device *dev) |
11382 | { |
11383 | struct drm_i915_private *dev_priv = dev->dev_private; |
11384 | int sprite, ret; |
11385 | enum i915_pipe pipe; |
11386 | struct intel_crtc *crtc; |
11387 | |
11388 | drm_mode_config_init(dev); |
11389 | |
11390 | dev->mode_config.min_width = 0; |
11391 | dev->mode_config.min_height = 0; |
11392 | |
11393 | dev->mode_config.preferred_depth = 24; |
11394 | dev->mode_config.prefer_shadow = 1; |
11395 | |
11396 | dev->mode_config.funcs = &intel_mode_funcs; |
11397 | |
11398 | intel_init_quirks(dev); |
11399 | |
11400 | intel_init_pm(dev); |
11401 | |
11402 | if (INTEL_INFO(dev)->num_pipes == 0) |
11403 | return; |
11404 | |
11405 | intel_init_display(dev); |
11406 | |
11407 | if (IS_GEN2(dev)) { |
11408 | dev->mode_config.max_width = 2048; |
11409 | dev->mode_config.max_height = 2048; |
11410 | } else if (IS_GEN3(dev)) { |
11411 | dev->mode_config.max_width = 4096; |
11412 | dev->mode_config.max_height = 4096; |
11413 | } else { |
11414 | dev->mode_config.max_width = 8192; |
11415 | dev->mode_config.max_height = 8192; |
11416 | } |
11417 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
11418 | |
11419 | DRM_DEBUG_KMS("%d display pipe%s available.\n" , |
11420 | INTEL_INFO(dev)->num_pipes, |
11421 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : "" ); |
11422 | |
11423 | for_each_pipe(pipe) { |
11424 | intel_crtc_init(dev, pipe); |
11425 | for_each_sprite(pipe, sprite) { |
11426 | ret = intel_plane_init(dev, pipe, sprite); |
11427 | if (ret) |
11428 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n" , |
11429 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
11430 | } |
11431 | } |
11432 | |
11433 | intel_init_dpio(dev); |
11434 | intel_reset_dpio(dev); |
11435 | |
11436 | intel_cpu_pll_init(dev); |
11437 | intel_shared_dpll_init(dev); |
11438 | |
11439 | #ifndef __NetBSD__ /* XXX We wait until intelfb is ready. */ |
11440 | /* Just disable it once at startup */ |
11441 | i915_disable_vga(dev); |
11442 | #endif |
11443 | intel_setup_outputs(dev); |
11444 | |
11445 | /* Just in case the BIOS is doing something questionable. */ |
11446 | intel_disable_fbc(dev); |
11447 | |
11448 | mutex_lock(&dev->mode_config.mutex); |
11449 | intel_modeset_setup_hw_state(dev, false); |
11450 | mutex_unlock(&dev->mode_config.mutex); |
11451 | |
11452 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
11453 | base.head) { |
11454 | if (!crtc->active) |
11455 | continue; |
11456 | |
11457 | /* |
11458 | * Note that reserving the BIOS fb up front prevents us |
11459 | * from stuffing other stolen allocations like the ring |
11460 | * on top. This prevents some ugliness at boot time, and |
11461 | * can even allow for smooth boot transitions if the BIOS |
11462 | * fb is large enough for the active pipe configuration. |
11463 | */ |
11464 | if (dev_priv->display.get_plane_config) { |
11465 | dev_priv->display.get_plane_config(crtc, |
11466 | &crtc->plane_config); |
11467 | /* |
11468 | * If the fb is shared between multiple heads, we'll |
11469 | * just get the first one. |
11470 | */ |
11471 | intel_find_plane_obj(crtc, &crtc->plane_config); |
11472 | } |
11473 | } |
11474 | } |
11475 | |
11476 | static void intel_enable_pipe_a(struct drm_device *dev) |
11477 | { |
11478 | struct intel_connector *connector; |
11479 | struct drm_connector *crt = NULL; |
11480 | struct intel_load_detect_pipe load_detect_temp; |
11481 | |
11482 | /* We can't just switch on the pipe A, we need to set things up with a |
11483 | * proper mode and output configuration. As a gross hack, enable pipe A |
11484 | * by enabling the load detect pipe once. */ |
11485 | list_for_each_entry(connector, |
11486 | &dev->mode_config.connector_list, |
11487 | base.head) { |
11488 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
11489 | crt = &connector->base; |
11490 | break; |
11491 | } |
11492 | } |
11493 | |
11494 | if (!crt) |
11495 | return; |
11496 | |
11497 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) |
11498 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
11499 | |
11500 | |
11501 | } |
11502 | |
11503 | static bool |
11504 | intel_check_plane_mapping(struct intel_crtc *crtc) |
11505 | { |
11506 | struct drm_device *dev = crtc->base.dev; |
11507 | struct drm_i915_private *dev_priv = dev->dev_private; |
11508 | u32 reg, val; |
11509 | |
11510 | if (INTEL_INFO(dev)->num_pipes == 1) |
11511 | return true; |
11512 | |
11513 | reg = DSPCNTR(!crtc->plane); |
11514 | val = I915_READ(reg); |
11515 | |
11516 | if ((val & DISPLAY_PLANE_ENABLE) && |
11517 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
11518 | return false; |
11519 | |
11520 | return true; |
11521 | } |
11522 | |
11523 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
11524 | { |
11525 | struct drm_device *dev = crtc->base.dev; |
11526 | struct drm_i915_private *dev_priv = dev->dev_private; |
11527 | u32 reg; |
11528 | |
11529 | /* Clear any frame start delays used for debugging left by the BIOS */ |
11530 | reg = PIPECONF(crtc->config.cpu_transcoder); |
11531 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
11532 | |
11533 | /* We need to sanitize the plane -> pipe mapping first because this will |
11534 | * disable the crtc (and hence change the state) if it is wrong. Note |
11535 | * that gen4+ has a fixed plane -> pipe mapping. */ |
11536 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
11537 | struct intel_connector *connector; |
11538 | bool plane; |
11539 | |
11540 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n" , |
11541 | crtc->base.base.id); |
11542 | |
11543 | /* Pipe has the wrong plane attached and the plane is active. |
11544 | * Temporarily change the plane mapping and disable everything |
11545 | * ... */ |
11546 | plane = crtc->plane; |
11547 | crtc->plane = !plane; |
11548 | dev_priv->display.crtc_disable(&crtc->base); |
11549 | crtc->plane = plane; |
11550 | |
11551 | /* ... and break all links. */ |
11552 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11553 | base.head) { |
11554 | if (connector->encoder->base.crtc != &crtc->base) |
11555 | continue; |
11556 | |
11557 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
11558 | connector->base.encoder = NULL; |
11559 | } |
11560 | /* multiple connectors may have the same encoder: |
11561 | * handle them and break crtc link separately */ |
11562 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11563 | base.head) |
11564 | if (connector->encoder->base.crtc == &crtc->base) { |
11565 | connector->encoder->base.crtc = NULL; |
11566 | connector->encoder->connectors_active = false; |
11567 | } |
11568 | |
11569 | WARN_ON(crtc->active); |
11570 | crtc->base.enabled = false; |
11571 | } |
11572 | |
11573 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
11574 | crtc->pipe == PIPE_A && !crtc->active) { |
11575 | /* BIOS forgot to enable pipe A, this mostly happens after |
11576 | * resume. Force-enable the pipe to fix this, the update_dpms |
11577 | * call below we restore the pipe to the right state, but leave |
11578 | * the required bits on. */ |
11579 | intel_enable_pipe_a(dev); |
11580 | } |
11581 | |
11582 | /* Adjust the state of the output pipe according to whether we |
11583 | * have active connectors/encoders. */ |
11584 | intel_crtc_update_dpms(&crtc->base); |
11585 | |
11586 | if (crtc->active != crtc->base.enabled) { |
11587 | struct intel_encoder *encoder; |
11588 | |
11589 | /* This can happen either due to bugs in the get_hw_state |
11590 | * functions or because the pipe is force-enabled due to the |
11591 | * pipe A quirk. */ |
11592 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n" , |
11593 | crtc->base.base.id, |
11594 | crtc->base.enabled ? "enabled" : "disabled" , |
11595 | crtc->active ? "enabled" : "disabled" ); |
11596 | |
11597 | crtc->base.enabled = crtc->active; |
11598 | |
11599 | /* Because we only establish the connector -> encoder -> |
11600 | * crtc links if something is active, this means the |
11601 | * crtc is now deactivated. Break the links. connector |
11602 | * -> encoder links are only establish when things are |
11603 | * actually up, hence no need to break them. */ |
11604 | WARN_ON(crtc->active); |
11605 | |
11606 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
11607 | WARN_ON(encoder->connectors_active); |
11608 | encoder->base.crtc = NULL; |
11609 | } |
11610 | } |
11611 | if (crtc->active) { |
11612 | /* |
11613 | * We start out with underrun reporting disabled to avoid races. |
11614 | * For correct bookkeeping mark this on active crtcs. |
11615 | * |
11616 | * No protection against concurrent access is required - at |
11617 | * worst a fifo underrun happens which also sets this to false. |
11618 | */ |
11619 | crtc->cpu_fifo_underrun_disabled = true; |
11620 | crtc->pch_fifo_underrun_disabled = true; |
11621 | } |
11622 | } |
11623 | |
11624 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
11625 | { |
11626 | struct intel_connector *connector; |
11627 | struct drm_device *dev = encoder->base.dev; |
11628 | |
11629 | /* We need to check both for a crtc link (meaning that the |
11630 | * encoder is active and trying to read from a pipe) and the |
11631 | * pipe itself being active. */ |
11632 | bool has_active_crtc = encoder->base.crtc && |
11633 | to_intel_crtc(encoder->base.crtc)->active; |
11634 | |
11635 | if (encoder->connectors_active && !has_active_crtc) { |
11636 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n" , |
11637 | encoder->base.base.id, |
11638 | drm_get_encoder_name(&encoder->base)); |
11639 | |
11640 | /* Connector is active, but has no active pipe. This is |
11641 | * fallout from our resume register restoring. Disable |
11642 | * the encoder manually again. */ |
11643 | if (encoder->base.crtc) { |
11644 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n" , |
11645 | encoder->base.base.id, |
11646 | drm_get_encoder_name(&encoder->base)); |
11647 | encoder->disable(encoder); |
11648 | } |
11649 | encoder->base.crtc = NULL; |
11650 | encoder->connectors_active = false; |
11651 | |
11652 | /* Inconsistent output/port/pipe state happens presumably due to |
11653 | * a bug in one of the get_hw_state functions. Or someplace else |
11654 | * in our code, like the register restore mess on resume. Clamp |
11655 | * things to off as a safer default. */ |
11656 | list_for_each_entry(connector, |
11657 | &dev->mode_config.connector_list, |
11658 | base.head) { |
11659 | if (connector->encoder != encoder) |
11660 | continue; |
11661 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
11662 | connector->base.encoder = NULL; |
11663 | } |
11664 | } |
11665 | /* Enabled encoders without active connectors will be fixed in |
11666 | * the crtc fixup. */ |
11667 | } |
11668 | |
11669 | void i915_redisable_vga_power_on(struct drm_device *dev) |
11670 | { |
11671 | struct drm_i915_private *dev_priv = dev->dev_private; |
11672 | u32 vga_reg = i915_vgacntrl_reg(dev); |
11673 | |
11674 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
11675 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n" ); |
11676 | i915_disable_vga(dev); |
11677 | } |
11678 | } |
11679 | |
11680 | void i915_redisable_vga(struct drm_device *dev) |
11681 | { |
11682 | struct drm_i915_private *dev_priv = dev->dev_private; |
11683 | |
11684 | /* This function can be called both from intel_modeset_setup_hw_state or |
11685 | * at a very early point in our resume sequence, where the power well |
11686 | * structures are not yet restored. Since this function is at a very |
11687 | * paranoid "someone might have enabled VGA while we were not looking" |
11688 | * level, just check if the power well is enabled instead of trying to |
11689 | * follow the "don't touch the power well if we don't need it" policy |
11690 | * the rest of the driver uses. */ |
11691 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
11692 | return; |
11693 | |
11694 | i915_redisable_vga_power_on(dev); |
11695 | } |
11696 | |
11697 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
11698 | { |
11699 | struct drm_i915_private *dev_priv = dev->dev_private; |
11700 | enum i915_pipe pipe; |
11701 | struct intel_crtc *crtc; |
11702 | struct intel_encoder *encoder; |
11703 | struct intel_connector *connector; |
11704 | int i; |
11705 | |
11706 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
11707 | base.head) { |
11708 | memset(&crtc->config, 0, sizeof(crtc->config)); |
11709 | |
11710 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
11711 | |
11712 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11713 | &crtc->config); |
11714 | |
11715 | crtc->base.enabled = crtc->active; |
11716 | crtc->primary_enabled = crtc->active; |
11717 | |
11718 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n" , |
11719 | crtc->base.base.id, |
11720 | crtc->active ? "enabled" : "disabled" ); |
11721 | } |
11722 | |
11723 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
11724 | if (HAS_DDI(dev)) |
11725 | intel_ddi_setup_hw_pll_state(dev); |
11726 | |
11727 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11728 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
11729 | |
11730 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); |
11731 | pll->active = 0; |
11732 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
11733 | base.head) { |
11734 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
11735 | pll->active++; |
11736 | } |
11737 | pll->refcount = pll->active; |
11738 | |
11739 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n" , |
11740 | pll->name, pll->refcount, pll->on); |
11741 | } |
11742 | |
11743 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
11744 | base.head) { |
11745 | pipe = 0; |
11746 | |
11747 | if (encoder->get_hw_state(encoder, &pipe)) { |
11748 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11749 | encoder->base.crtc = &crtc->base; |
11750 | encoder->get_config(encoder, &crtc->config); |
11751 | } else { |
11752 | encoder->base.crtc = NULL; |
11753 | } |
11754 | |
11755 | encoder->connectors_active = false; |
11756 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n" , |
11757 | encoder->base.base.id, |
11758 | drm_get_encoder_name(&encoder->base), |
11759 | encoder->base.crtc ? "enabled" : "disabled" , |
11760 | pipe_name(pipe)); |
11761 | } |
11762 | |
11763 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11764 | base.head) { |
11765 | if (connector->get_hw_state(connector)) { |
11766 | connector->base.dpms = DRM_MODE_DPMS_ON; |
11767 | connector->encoder->connectors_active = true; |
11768 | connector->base.encoder = &connector->encoder->base; |
11769 | } else { |
11770 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
11771 | connector->base.encoder = NULL; |
11772 | } |
11773 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n" , |
11774 | connector->base.base.id, |
11775 | drm_get_connector_name(&connector->base), |
11776 | connector->base.encoder ? "enabled" : "disabled" ); |
11777 | } |
11778 | } |
11779 | |
11780 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
11781 | * and i915 state tracking structures. */ |
11782 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
11783 | bool force_restore) |
11784 | { |
11785 | struct drm_i915_private *dev_priv = dev->dev_private; |
11786 | enum i915_pipe pipe; |
11787 | struct intel_crtc *crtc; |
11788 | struct intel_encoder *encoder; |
11789 | int i; |
11790 | |
11791 | intel_modeset_readout_hw_state(dev); |
11792 | |
11793 | /* |
11794 | * Now that we have the config, copy it to each CRTC struct |
11795 | * Note that this could go away if we move to using crtc_config |
11796 | * checking everywhere. |
11797 | */ |
11798 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
11799 | base.head) { |
11800 | if (crtc->active && i915.fastboot) { |
11801 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
11802 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: " , |
11803 | crtc->base.base.id); |
11804 | drm_mode_debug_printmodeline(&crtc->base.mode); |
11805 | } |
11806 | } |
11807 | |
11808 | /* HW state is read out, now we need to sanitize this mess. */ |
11809 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
11810 | base.head) { |
11811 | intel_sanitize_encoder(encoder); |
11812 | } |
11813 | |
11814 | for_each_pipe(pipe) { |
11815 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11816 | intel_sanitize_crtc(crtc); |
11817 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]" ); |
11818 | } |
11819 | |
11820 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11821 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
11822 | |
11823 | if (!pll->on || pll->active) |
11824 | continue; |
11825 | |
11826 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n" , pll->name); |
11827 | |
11828 | pll->disable(dev_priv, pll); |
11829 | pll->on = false; |
11830 | } |
11831 | |
11832 | if (HAS_PCH_SPLIT(dev)) |
11833 | ilk_wm_get_hw_state(dev); |
11834 | |
11835 | if (force_restore) { |
11836 | i915_redisable_vga(dev); |
11837 | |
11838 | /* |
11839 | * We need to use raw interfaces for restoring state to avoid |
11840 | * checking (bogus) intermediate states. |
11841 | */ |
11842 | for_each_pipe(pipe) { |
11843 | struct drm_crtc *crtc = |
11844 | dev_priv->pipe_to_crtc_mapping[pipe]; |
11845 | |
11846 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
11847 | crtc->primary->fb); |
11848 | } |
11849 | } else { |
11850 | intel_modeset_update_staged_output_state(dev); |
11851 | } |
11852 | |
11853 | intel_modeset_check_state(dev); |
11854 | } |
11855 | |
11856 | void intel_modeset_gem_init(struct drm_device *dev) |
11857 | { |
11858 | struct drm_crtc *c; |
11859 | struct intel_framebuffer *fb; |
11860 | |
11861 | mutex_lock(&dev->struct_mutex); |
11862 | intel_init_gt_powersave(dev); |
11863 | mutex_unlock(&dev->struct_mutex); |
11864 | |
11865 | intel_modeset_init_hw(dev); |
11866 | |
11867 | intel_setup_overlay(dev); |
11868 | |
11869 | /* |
11870 | * Make sure any fbs we allocated at startup are properly |
11871 | * pinned & fenced. When we do the allocation it's too early |
11872 | * for this. |
11873 | */ |
11874 | mutex_lock(&dev->struct_mutex); |
11875 | list_for_each_entry(c, &dev->mode_config.crtc_list, head) { |
11876 | if (!c->primary->fb) |
11877 | continue; |
11878 | |
11879 | fb = to_intel_framebuffer(c->primary->fb); |
11880 | if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) { |
11881 | DRM_ERROR("failed to pin boot fb on pipe %d\n" , |
11882 | to_intel_crtc(c)->pipe); |
11883 | drm_framebuffer_unreference(c->primary->fb); |
11884 | c->primary->fb = NULL; |
11885 | } |
11886 | } |
11887 | mutex_unlock(&dev->struct_mutex); |
11888 | } |
11889 | |
11890 | void intel_connector_unregister(struct intel_connector *intel_connector) |
11891 | { |
11892 | struct drm_connector *connector = &intel_connector->base; |
11893 | |
11894 | intel_panel_destroy_backlight(connector); |
11895 | drm_sysfs_connector_remove(connector); |
11896 | } |
11897 | |
11898 | void intel_modeset_cleanup(struct drm_device *dev) |
11899 | { |
11900 | struct drm_i915_private *dev_priv = dev->dev_private; |
11901 | struct drm_crtc *crtc; |
11902 | struct drm_connector *connector; |
11903 | |
11904 | /* |
11905 | * Interrupts and polling as the first thing to avoid creating havoc. |
11906 | * Too much stuff here (turning of rps, connectors, ...) would |
11907 | * experience fancy races otherwise. |
11908 | */ |
11909 | drm_irq_uninstall(dev); |
11910 | cancel_work_sync(&dev_priv->hotplug_work); |
11911 | /* |
11912 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
11913 | * poll handlers. Hence disable polling after hpd handling is shut down. |
11914 | */ |
11915 | drm_kms_helper_poll_fini(dev); |
11916 | |
11917 | mutex_lock(&dev->struct_mutex); |
11918 | |
11919 | intel_unregister_dsm_handler(); |
11920 | |
11921 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
11922 | /* Skip inactive CRTCs */ |
11923 | if (!crtc->primary->fb) |
11924 | continue; |
11925 | |
11926 | intel_increase_pllclock(crtc); |
11927 | } |
11928 | |
11929 | intel_disable_fbc(dev); |
11930 | |
11931 | intel_disable_gt_powersave(dev); |
11932 | |
11933 | ironlake_teardown_rc6(dev); |
11934 | |
11935 | mutex_unlock(&dev->struct_mutex); |
11936 | |
11937 | /* flush any delayed tasks or pending work */ |
11938 | flush_scheduled_work(); |
11939 | |
11940 | /* destroy the backlight and sysfs files before encoders/connectors */ |
11941 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
11942 | struct intel_connector *intel_connector; |
11943 | |
11944 | intel_connector = to_intel_connector(connector); |
11945 | intel_connector->unregister(intel_connector); |
11946 | } |
11947 | |
11948 | drm_mode_config_cleanup(dev); |
11949 | |
11950 | intel_cleanup_overlay(dev); |
11951 | |
11952 | mutex_lock(&dev->struct_mutex); |
11953 | intel_cleanup_gt_powersave(dev); |
11954 | mutex_unlock(&dev->struct_mutex); |
11955 | } |
11956 | |
11957 | /* |
11958 | * Return which encoder is currently attached for connector. |
11959 | */ |
11960 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
11961 | { |
11962 | return &intel_attached_encoder(connector)->base; |
11963 | } |
11964 | |
11965 | void intel_connector_attach_encoder(struct intel_connector *connector, |
11966 | struct intel_encoder *encoder) |
11967 | { |
11968 | connector->encoder = encoder; |
11969 | drm_mode_connector_attach_encoder(&connector->base, |
11970 | &encoder->base); |
11971 | } |
11972 | |
11973 | /* |
11974 | * set vga decode state - true == enable VGA decode |
11975 | */ |
11976 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
11977 | { |
11978 | struct drm_i915_private *dev_priv = dev->dev_private; |
11979 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
11980 | u16 gmch_ctrl; |
11981 | |
11982 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
11983 | DRM_ERROR("failed to read control word\n" ); |
11984 | return -EIO; |
11985 | } |
11986 | |
11987 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
11988 | return 0; |
11989 | |
11990 | if (state) |
11991 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
11992 | else |
11993 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
11994 | |
11995 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { |
11996 | DRM_ERROR("failed to write control word\n" ); |
11997 | return -EIO; |
11998 | } |
11999 | |
12000 | return 0; |
12001 | } |
12002 | |
12003 | struct intel_display_error_state { |
12004 | |
12005 | u32 power_well_driver; |
12006 | |
12007 | int num_transcoders; |
12008 | |
12009 | struct intel_cursor_error_state { |
12010 | u32 control; |
12011 | u32 position; |
12012 | u32 base; |
12013 | u32 size; |
12014 | } cursor[I915_MAX_PIPES]; |
12015 | |
12016 | struct intel_pipe_error_state { |
12017 | bool power_domain_on; |
12018 | u32 source; |
12019 | } pipe[I915_MAX_PIPES]; |
12020 | |
12021 | struct intel_plane_error_state { |
12022 | u32 control; |
12023 | u32 stride; |
12024 | u32 size; |
12025 | u32 pos; |
12026 | u32 addr; |
12027 | u32 surface; |
12028 | u32 tile_offset; |
12029 | } plane[I915_MAX_PIPES]; |
12030 | |
12031 | struct intel_transcoder_error_state { |
12032 | bool power_domain_on; |
12033 | enum transcoder cpu_transcoder; |
12034 | |
12035 | u32 conf; |
12036 | |
12037 | u32 htotal; |
12038 | u32 hblank; |
12039 | u32 hsync; |
12040 | u32 vtotal; |
12041 | u32 vblank; |
12042 | u32 vsync; |
12043 | } transcoder[4]; |
12044 | }; |
12045 | |
12046 | struct intel_display_error_state * |
12047 | intel_display_capture_error_state(struct drm_device *dev) |
12048 | { |
12049 | struct drm_i915_private *dev_priv = dev->dev_private; |
12050 | struct intel_display_error_state *error; |
12051 | int transcoders[] = { |
12052 | TRANSCODER_A, |
12053 | TRANSCODER_B, |
12054 | TRANSCODER_C, |
12055 | TRANSCODER_EDP, |
12056 | }; |
12057 | int i; |
12058 | |
12059 | if (INTEL_INFO(dev)->num_pipes == 0) |
12060 | return NULL; |
12061 | |
12062 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
12063 | if (error == NULL) |
12064 | return NULL; |
12065 | |
12066 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
12067 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
12068 | |
12069 | for_each_pipe(i) { |
12070 | error->pipe[i].power_domain_on = |
12071 | intel_display_power_enabled_sw(dev_priv, |
12072 | POWER_DOMAIN_PIPE(i)); |
12073 | if (!error->pipe[i].power_domain_on) |
12074 | continue; |
12075 | |
12076 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
12077 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
12078 | error->cursor[i].position = I915_READ(CURPOS(i)); |
12079 | error->cursor[i].base = I915_READ(CURBASE(i)); |
12080 | } else { |
12081 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); |
12082 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); |
12083 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); |
12084 | } |
12085 | |
12086 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
12087 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
12088 | if (INTEL_INFO(dev)->gen <= 3) { |
12089 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
12090 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
12091 | } |
12092 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
12093 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
12094 | if (INTEL_INFO(dev)->gen >= 4) { |
12095 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
12096 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
12097 | } |
12098 | |
12099 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
12100 | } |
12101 | |
12102 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
12103 | if (HAS_DDI(dev_priv->dev)) |
12104 | error->num_transcoders++; /* Account for eDP. */ |
12105 | |
12106 | for (i = 0; i < error->num_transcoders; i++) { |
12107 | enum transcoder cpu_transcoder = transcoders[i]; |
12108 | |
12109 | error->transcoder[i].power_domain_on = |
12110 | intel_display_power_enabled_sw(dev_priv, |
12111 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
12112 | if (!error->transcoder[i].power_domain_on) |
12113 | continue; |
12114 | |
12115 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
12116 | |
12117 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
12118 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
12119 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); |
12120 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); |
12121 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
12122 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
12123 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
12124 | } |
12125 | |
12126 | return error; |
12127 | } |
12128 | |
12129 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
12130 | |
12131 | void |
12132 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
12133 | struct drm_device *dev, |
12134 | struct intel_display_error_state *error) |
12135 | { |
12136 | int i; |
12137 | |
12138 | if (!error) |
12139 | return; |
12140 | |
12141 | err_printf(m, "Num Pipes: %d\n" , INTEL_INFO(dev)->num_pipes); |
12142 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
12143 | err_printf(m, "PWR_WELL_CTL2: %08x\n" , |
12144 | error->power_well_driver); |
12145 | for_each_pipe(i) { |
12146 | err_printf(m, "Pipe [%d]:\n" , i); |
12147 | err_printf(m, " Power: %s\n" , |
12148 | error->pipe[i].power_domain_on ? "on" : "off" ); |
12149 | err_printf(m, " SRC: %08x\n" , error->pipe[i].source); |
12150 | |
12151 | err_printf(m, "Plane [%d]:\n" , i); |
12152 | err_printf(m, " CNTR: %08x\n" , error->plane[i].control); |
12153 | err_printf(m, " STRIDE: %08x\n" , error->plane[i].stride); |
12154 | if (INTEL_INFO(dev)->gen <= 3) { |
12155 | err_printf(m, " SIZE: %08x\n" , error->plane[i].size); |
12156 | err_printf(m, " POS: %08x\n" , error->plane[i].pos); |
12157 | } |
12158 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
12159 | err_printf(m, " ADDR: %08x\n" , error->plane[i].addr); |
12160 | if (INTEL_INFO(dev)->gen >= 4) { |
12161 | err_printf(m, " SURF: %08x\n" , error->plane[i].surface); |
12162 | err_printf(m, " TILEOFF: %08x\n" , error->plane[i].tile_offset); |
12163 | } |
12164 | |
12165 | err_printf(m, "Cursor [%d]:\n" , i); |
12166 | err_printf(m, " CNTR: %08x\n" , error->cursor[i].control); |
12167 | err_printf(m, " POS: %08x\n" , error->cursor[i].position); |
12168 | err_printf(m, " BASE: %08x\n" , error->cursor[i].base); |
12169 | } |
12170 | |
12171 | for (i = 0; i < error->num_transcoders; i++) { |
12172 | err_printf(m, "CPU transcoder: %c\n" , |
12173 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
12174 | err_printf(m, " Power: %s\n" , |
12175 | error->transcoder[i].power_domain_on ? "on" : "off" ); |
12176 | err_printf(m, " CONF: %08x\n" , error->transcoder[i].conf); |
12177 | err_printf(m, " HTOTAL: %08x\n" , error->transcoder[i].htotal); |
12178 | err_printf(m, " HBLANK: %08x\n" , error->transcoder[i].hblank); |
12179 | err_printf(m, " HSYNC: %08x\n" , error->transcoder[i].hsync); |
12180 | err_printf(m, " VTOTAL: %08x\n" , error->transcoder[i].vtotal); |
12181 | err_printf(m, " VBLANK: %08x\n" , error->transcoder[i].vblank); |
12182 | err_printf(m, " VSYNC: %08x\n" , error->transcoder[i].vsync); |
12183 | } |
12184 | } |
12185 | |