1 | /* $NetBSD: if_wmreg.h,v 1.93 2016/11/16 08:56:17 msaitoh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 2001 Wasabi Systems, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * Written by Jason R. Thorpe for Wasabi Systems, Inc. |
8 | * |
9 | * Redistribution and use in source and binary forms, with or without |
10 | * modification, are permitted provided that the following conditions |
11 | * are met: |
12 | * 1. Redistributions of source code must retain the above copyright |
13 | * notice, this list of conditions and the following disclaimer. |
14 | * 2. Redistributions in binary form must reproduce the above copyright |
15 | * notice, this list of conditions and the following disclaimer in the |
16 | * documentation and/or other materials provided with the distribution. |
17 | * 3. All advertising materials mentioning features or use of this software |
18 | * must display the following acknowledgement: |
19 | * This product includes software developed for the NetBSD Project by |
20 | * Wasabi Systems, Inc. |
21 | * 4. The name of Wasabi Systems, Inc. may not be used to endorse |
22 | * or promote products derived from this software without specific prior |
23 | * written permission. |
24 | * |
25 | * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND |
26 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
27 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC |
29 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
30 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
31 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
32 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
33 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
34 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
35 | * POSSIBILITY OF SUCH DAMAGE. |
36 | */ |
37 | |
38 | /****************************************************************************** |
39 | |
40 | Copyright (c) 2001-2012, Intel Corporation |
41 | All rights reserved. |
42 | |
43 | Redistribution and use in source and binary forms, with or without |
44 | modification, are permitted provided that the following conditions are met: |
45 | |
46 | 1. Redistributions of source code must retain the above copyright notice, |
47 | this list of conditions and the following disclaimer. |
48 | |
49 | 2. Redistributions in binary form must reproduce the above copyright |
50 | notice, this list of conditions and the following disclaimer in the |
51 | documentation and/or other materials provided with the distribution. |
52 | |
53 | 3. Neither the name of the Intel Corporation nor the names of its |
54 | contributors may be used to endorse or promote products derived from |
55 | this software without specific prior written permission. |
56 | |
57 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
58 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
59 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
60 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
61 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
62 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
63 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
64 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
65 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
66 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
67 | POSSIBILITY OF SUCH DAMAGE. |
68 | |
69 | ******************************************************************************/ |
70 | |
71 | /* |
72 | * Register description for the Intel i82542 (``Wiseman''), |
73 | * i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit |
74 | * Ethernet chips. |
75 | */ |
76 | |
77 | /* |
78 | * The wiseman supports 64-bit PCI addressing. This structure |
79 | * describes the address in descriptors. |
80 | */ |
81 | typedef struct wiseman_addr { |
82 | uint32_t wa_low; /* low-order 32 bits */ |
83 | uint32_t wa_high; /* high-order 32 bits */ |
84 | } __packed wiseman_addr_t; |
85 | |
86 | /* |
87 | * The Wiseman receive descriptor. |
88 | * |
89 | * The receive descriptor ring must be aligned to a 4K boundary, |
90 | * and there must be an even multiple of 8 descriptors in the ring. |
91 | */ |
92 | typedef struct wiseman_rxdesc { |
93 | volatile wiseman_addr_t wrx_addr; /* buffer address */ |
94 | |
95 | volatile uint16_t wrx_len; /* buffer length */ |
96 | volatile uint16_t wrx_cksum; /* checksum (starting at PCSS)*/ |
97 | |
98 | volatile uint8_t wrx_status; /* Rx status */ |
99 | volatile uint8_t wrx_errors; /* Rx errors */ |
100 | volatile uint16_t wrx_special; /* special field (VLAN, etc.) */ |
101 | } __packed wiseman_rxdesc_t; |
102 | |
103 | /* wrx_status bits */ |
104 | #define WRX_ST_DD (1U << 0) /* descriptor done */ |
105 | #define WRX_ST_EOP (1U << 1) /* end of packet */ |
106 | #define WRX_ST_IXSM (1U << 2) /* ignore checksum indication */ |
107 | #define WRX_ST_VP (1U << 3) /* VLAN packet */ |
108 | #define WRX_ST_BPDU (1U << 4) /* ??? */ |
109 | #define WRX_ST_TCPCS (1U << 5) /* TCP checksum performed */ |
110 | #define WRX_ST_IPCS (1U << 6) /* IP checksum performed */ |
111 | #define WRX_ST_PIF (1U << 7) /* passed in-exact filter */ |
112 | |
113 | /* wrx_error bits */ |
114 | #define WRX_ER_CE (1U << 0) /* CRC error */ |
115 | #define WRX_ER_SE (1U << 1) /* symbol error */ |
116 | #define WRX_ER_SEQ (1U << 2) /* sequence error */ |
117 | #define WRX_ER_ICE (1U << 3) /* ??? */ |
118 | #define WRX_ER_CXE (1U << 4) /* carrier extension error */ |
119 | #define WRX_ER_TCPE (1U << 5) /* TCP checksum error */ |
120 | #define WRX_ER_IPE (1U << 6) /* IP checksum error */ |
121 | #define WRX_ER_RXE (1U << 7) /* Rx data error */ |
122 | |
123 | /* wrx_special field for VLAN packets */ |
124 | #define WRX_VLAN_ID(x) ((x) & 0x0fff) /* VLAN identifier */ |
125 | #define WRX_VLAN_CFI (1U << 12) /* Canonical Form Indicator */ |
126 | #define WRX_VLAN_PRI(x) (((x) >> 13) & 7)/* VLAN priority field */ |
127 | |
128 | /* |
129 | * The Wiseman transmit descriptor. |
130 | * |
131 | * The transmit descriptor ring must be aligned to a 4K boundary, |
132 | * and there must be an even multiple of 8 descriptors in the ring. |
133 | */ |
134 | typedef struct wiseman_tx_fields { |
135 | uint8_t wtxu_status; /* Tx status */ |
136 | uint8_t wtxu_options; /* options */ |
137 | uint16_t wtxu_vlan; /* VLAN info */ |
138 | } __packed wiseman_txfields_t; |
139 | typedef struct wiseman_txdesc { |
140 | wiseman_addr_t wtx_addr; /* buffer address */ |
141 | uint32_t wtx_cmdlen; /* command and length */ |
142 | wiseman_txfields_t wtx_fields; /* fields; see below */ |
143 | } __packed wiseman_txdesc_t; |
144 | |
145 | /* Commands for wtx_cmdlen */ |
146 | #define WTX_CMD_EOP (1U << 24) /* end of packet */ |
147 | #define WTX_CMD_IFCS (1U << 25) /* insert FCS */ |
148 | #define WTX_CMD_RS (1U << 27) /* report status */ |
149 | #define WTX_CMD_RPS (1U << 28) /* report packet sent */ |
150 | #define WTX_CMD_DEXT (1U << 29) /* descriptor extension */ |
151 | #define WTX_CMD_VLE (1U << 30) /* VLAN enable */ |
152 | #define WTX_CMD_IDE (1U << 31) /* interrupt delay enable */ |
153 | |
154 | /* Descriptor types (if DEXT is set) */ |
155 | #define WTX_DTYP_C (0U << 20) /* context */ |
156 | #define WTX_DTYP_D (1U << 20) /* data */ |
157 | |
158 | /* wtx_fields status bits */ |
159 | #define WTX_ST_DD (1U << 0) /* descriptor done */ |
160 | #define WTX_ST_EC (1U << 1) /* excessive collisions */ |
161 | #define WTX_ST_LC (1U << 2) /* late collision */ |
162 | #define WTX_ST_TU (1U << 3) /* transmit underrun */ |
163 | |
164 | /* wtx_fields option bits for IP/TCP/UDP checksum offload */ |
165 | #define WTX_IXSM (1U << 0) /* IP checksum offload */ |
166 | #define WTX_TXSM (1U << 1) /* TCP/UDP checksum offload */ |
167 | |
168 | /* Maximum payload per Tx descriptor */ |
169 | #define WTX_MAX_LEN 4096 |
170 | |
171 | /* |
172 | * The Livengood TCP/IP context descriptor. |
173 | */ |
174 | struct livengood_tcpip_ctxdesc { |
175 | uint32_t tcpip_ipcs; /* IP checksum context */ |
176 | uint32_t tcpip_tucs; /* TCP/UDP checksum context */ |
177 | uint32_t tcpip_cmdlen; |
178 | uint32_t tcpip_seg; /* TCP segmentation context */ |
179 | }; |
180 | |
181 | /* commands for context descriptors */ |
182 | #define WTX_TCPIP_CMD_TCP (1U << 24) /* 1 = TCP, 0 = UDP */ |
183 | #define WTX_TCPIP_CMD_IP (1U << 25) /* 1 = IPv4, 0 = IPv6 */ |
184 | #define WTX_TCPIP_CMD_TSE (1U << 26) /* segmentation context valid */ |
185 | |
186 | #define WTX_TCPIP_IPCSS(x) ((x) << 0) /* checksum start */ |
187 | #define WTX_TCPIP_IPCSO(x) ((x) << 8) /* checksum value offset */ |
188 | #define WTX_TCPIP_IPCSE(x) ((x) << 16) /* checksum end */ |
189 | |
190 | #define WTX_TCPIP_TUCSS(x) ((x) << 0) /* checksum start */ |
191 | #define WTX_TCPIP_TUCSO(x) ((x) << 8) /* checksum value offset */ |
192 | #define WTX_TCPIP_TUCSE(x) ((x) << 16) /* checksum end */ |
193 | |
194 | #define WTX_TCPIP_SEG_STATUS(x) ((x) << 0) |
195 | #define WTX_TCPIP_SEG_HDRLEN(x) ((x) << 8) |
196 | #define WTX_TCPIP_SEG_MSS(x) ((x) << 16) |
197 | |
198 | /* |
199 | * PCI config registers used by the Wiseman. |
200 | */ |
201 | #define WM_PCI_MMBA PCI_MAPREG_START |
202 | /* registers for FLASH access on ICH8 */ |
203 | #define WM_ICH8_FLASH 0x0014 |
204 | |
205 | #define WM_PCI_LTR_CAP_LPT 0xa8 |
206 | |
207 | /* XXX Only for PCH_SPT? */ |
208 | #define WM_PCI_DESCRING_STATUS 0xe4 |
209 | #define DESCRING_STATUS_FLUSH_REQ __BIT(8) |
210 | |
211 | /* |
212 | * Wiseman Control/Status Registers. |
213 | */ |
214 | #define WMREG_CTRL 0x0000 /* Device Control Register */ |
215 | #define CTRL_FD (1U << 0) /* full duplex */ |
216 | #define CTRL_BEM (1U << 1) /* big-endian mode */ |
217 | #define CTRL_PRIOR (1U << 2) /* 0 = receive, 1 = fair */ |
218 | #define CTRL_GIO_M_DIS (1U << 2) /* disabl PCI master access */ |
219 | #define CTRL_LRST (1U << 3) /* link reset */ |
220 | #define CTRL_ASDE (1U << 5) /* auto speed detect enable */ |
221 | #define CTRL_SLU (1U << 6) /* set link up */ |
222 | #define CTRL_ILOS (1U << 7) /* invert loss of signal */ |
223 | #define CTRL_SPEED(x) ((x) << 8) /* speed (Livengood) */ |
224 | #define CTRL_SPEED_10 CTRL_SPEED(0) |
225 | #define CTRL_SPEED_100 CTRL_SPEED(1) |
226 | #define CTRL_SPEED_1000 CTRL_SPEED(2) |
227 | #define CTRL_SPEED_MASK CTRL_SPEED(3) |
228 | #define CTRL_FRCSPD (1U << 11) /* force speed (Livengood) */ |
229 | #define CTRL_FRCFDX (1U << 12) /* force full-duplex (Livengood) */ |
230 | #define CTRL_D_UD_EN (1U << 13) /* Dock/Undock enable */ |
231 | #define CTRL_D_UD_POL (1U << 14) /* Defined polarity of Dock/Undock indication in SDP[0] */ |
232 | #define CTRL_F_PHY_R (1U << 15) /* Reset both PHY ports, through PHYRST_N pin */ |
233 | #define CTRL_EXT_LINK_EN (1U << 16) /* enable link status from external LINK_0 and LINK_1 pins */ |
234 | #define CTRL_LANPHYPC_OVERRIDE (1U << 16) /* SW control of LANPHYPC */ |
235 | #define CTRL_LANPHYPC_VALUE (1U << 17) /* SW value of LANPHYPC */ |
236 | #define CTRL_SWDPINS_SHIFT 18 |
237 | #define CTRL_SWDPINS_MASK 0x0f |
238 | #define CTRL_SWDPIN(x) (1U << (CTRL_SWDPINS_SHIFT + (x))) |
239 | #define CTRL_SWDPIO_SHIFT 22 |
240 | #define CTRL_SWDPIO_MASK 0x0f |
241 | #define CTRL_SWDPIO(x) (1U << (CTRL_SWDPIO_SHIFT + (x))) |
242 | #define CTRL_MEHE (1U << 19) /* Memory Error Handling Enable(I217)*/ |
243 | #define CTRL_RST (1U << 26) /* device reset */ |
244 | #define CTRL_RFCE (1U << 27) /* Rx flow control enable */ |
245 | #define CTRL_TFCE (1U << 28) /* Tx flow control enable */ |
246 | #define CTRL_VME (1U << 30) /* VLAN Mode Enable */ |
247 | #define CTRL_PHY_RESET (1U << 31) /* PHY reset (Cordova) */ |
248 | |
249 | #define WMREG_CTRL_SHADOW 0x0004 /* Device Control Register (shadow) */ |
250 | |
251 | #define WMREG_STATUS 0x0008 /* Device Status Register */ |
252 | #define STATUS_FD (1U << 0) /* full duplex */ |
253 | #define STATUS_LU (1U << 1) /* link up */ |
254 | #define STATUS_TCKOK (1U << 2) /* Tx clock running */ |
255 | #define STATUS_RBCOK (1U << 3) /* Rx clock running */ |
256 | #define STATUS_FUNCID_SHIFT 2 /* 82546 function ID */ |
257 | #define STATUS_FUNCID_MASK 3 /* ... */ |
258 | #define STATUS_TXOFF (1U << 4) /* Tx paused */ |
259 | #define STATUS_TBIMODE (1U << 5) /* fiber mode (Livengood) */ |
260 | #define STATUS_SPEED __BITS(7, 6) /* speed indication */ |
261 | #define STATUS_SPEED_10 0 |
262 | #define STATUS_SPEED_100 1 |
263 | #define STATUS_SPEED_1000 2 |
264 | #define STATUS_ASDV(x) ((x) << 8) /* auto speed det. val. (Livengood) */ |
265 | #define STATUS_LAN_INIT_DONE (1U << 9) /* Lan Init Completion by NVM */ |
266 | #define STATUS_MTXCKOK (1U << 10) /* MTXD clock running */ |
267 | #define STATUS_PHYRA (1U << 10) /* PHY Reset Asserted (PCH) */ |
268 | #define STATUS_PCI66 (1U << 11) /* 66MHz bus (Livengood) */ |
269 | #define STATUS_BUS64 (1U << 12) /* 64-bit bus (Livengood) */ |
270 | #define STATUS_PCIX_MODE (1U << 13) /* PCIX mode (Cordova) */ |
271 | #define STATUS_PCIXSPD(x) ((x) << 14) /* PCIX speed indication (Cordova) */ |
272 | #define STATUS_PCIXSPD_50_66 STATUS_PCIXSPD(0) |
273 | #define STATUS_PCIXSPD_66_100 STATUS_PCIXSPD(1) |
274 | #define STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2) |
275 | #define STATUS_PCIXSPD_MASK STATUS_PCIXSPD(3) |
276 | #define STATUS_GIO_M_ENA (1U << 19) /* GIO master enable */ |
277 | #define STATUS_DEV_RST_SET (1U << 20) /* Device Reset Set */ |
278 | |
279 | /* Strapping Option Register (PCH_SPT and newer) */ |
280 | #define WMREG_STRAP 0x000c |
281 | #define STRAP_NVMSIZE __BITS(1, 6) |
282 | #define STRAP_FREQ __BITS(12, 13) |
283 | #define STRAP_SMBUSADDR __BITS(17, 23) |
284 | |
285 | #define WMREG_EECD 0x0010 /* EEPROM Control Register */ |
286 | #define EECD_SK (1U << 0) /* clock */ |
287 | #define EECD_CS (1U << 1) /* chip select */ |
288 | #define EECD_DI (1U << 2) /* data in */ |
289 | #define EECD_DO (1U << 3) /* data out */ |
290 | #define EECD_FWE(x) ((x) << 4) /* flash write enable control */ |
291 | #define EECD_FWE_DISABLED EECD_FWE(1) |
292 | #define EECD_FWE_ENABLED EECD_FWE(2) |
293 | #define EECD_EE_REQ (1U << 6) /* (shared) EEPROM request */ |
294 | #define EECD_EE_GNT (1U << 7) /* (shared) EEPROM grant */ |
295 | #define EECD_EE_PRES (1U << 8) /* EEPROM present */ |
296 | #define EECD_EE_SIZE (1U << 9) /* EEPROM size |
297 | (0 = 64 word, 1 = 256 word) */ |
298 | #define EECD_EE_AUTORD (1U << 9) /* auto read done */ |
299 | #define EECD_EE_ABITS (1U << 10) /* EEPROM address bits |
300 | (based on type) */ |
301 | #define EECD_EE_SIZE_EX_MASK __BITS(14,11) /* EEPROM size for new devices */ |
302 | #define EECD_EE_TYPE (1U << 13) /* EEPROM type |
303 | (0 = Microwire, 1 = SPI) */ |
304 | #define EECD_SEC1VAL (1U << 22) /* Sector One Valid */ |
305 | #define EECD_SEC1VAL_VALMASK (EECD_EE_AUTORD | EECD_EE_PRES) /* Valid Mask */ |
306 | |
307 | #define WMREG_EERD 0x0014 /* EEPROM read */ |
308 | #define EERD_DONE 0x02 /* done bit */ |
309 | #define EERD_START 0x01 /* First bit for telling part to start operation */ |
310 | #define EERD_ADDR_SHIFT 2 /* Shift to the address bits */ |
311 | #define EERD_DATA_SHIFT 16 /* Offset to data in EEPROM read/write registers */ |
312 | |
313 | #define WMREG_FEXTNVM6 0x0010 /* Future Extended NVM 6 */ |
314 | #define FEXTNVM6_K1_OFF_ENABLE __BIT(31) |
315 | |
316 | #define WMREG_CTRL_EXT 0x0018 /* Extended Device Control Register */ |
317 | #define CTRL_EXT_NSICR __BIT(0) /* Non Interrupt clear on read */ |
318 | #define CTRL_EXT_GPI_EN(x) (1U << (x)) /* gpin interrupt enable */ |
319 | #define CTRL_EXT_NVMVS __BITS(0, 1) /* NVM valid sector */ |
320 | #define CTRL_EXT_LPCD __BIT(2) /* LCD Power Cycle Done */ |
321 | #define CTRL_EXT_SWDPINS_SHIFT 4 |
322 | #define CTRL_EXT_SWDPINS_MASK 0x0d |
323 | /* The bit order of the SW Definable pin is not 6543 but 3654! */ |
324 | #define CTRL_EXT_SWDPIN(x) (1U << (CTRL_EXT_SWDPINS_SHIFT \ |
325 | + ((x) == 3 ? 3 : ((x) - 4)))) |
326 | #define CTRL_EXT_SWDPIO_SHIFT 8 |
327 | #define CTRL_EXT_SWDPIO_MASK 0x0d |
328 | #define CTRL_EXT_SWDPIO(x) (1U << (CTRL_EXT_SWDPIO_SHIFT \ |
329 | + ((x) == 3 ? 3 : ((x) - 4)))) |
330 | #define CTRL_EXT_FORCE_SMBUS __BIT(11) /* Force SMBus mode */ |
331 | #define CTRL_EXT_ASDCHK (1U << 12) /* ASD check */ |
332 | #define CTRL_EXT_EE_RST (1U << 13) /* EEPROM reset */ |
333 | #define CTRL_EXT_IPS (1U << 14) /* invert power state bit 0 */ |
334 | #define CTRL_EXT_SPD_BYPS (1U << 15) /* speed select bypass */ |
335 | #define CTRL_EXT_IPS1 (1U << 16) /* invert power state bit 1 */ |
336 | #define CTRL_EXT_RO_DIS (1U << 17) /* relaxed ordering disabled */ |
337 | #define CTRL_EXT_SDLPE (1U << 18) /* SerDes Low Power Enable */ |
338 | #define CTRL_EXT_DMA_DYN_CLK (1U << 19) /* DMA Dynamic Gating Enable */ |
339 | #define CTRL_EXT_PHYPDEN __BIT(20) |
340 | #define CTRL_EXT_LINK_MODE_MASK 0x00C00000 |
341 | #define CTRL_EXT_LINK_MODE_GMII 0x00000000 |
342 | #define CTRL_EXT_LINK_MODE_KMRN 0x00000000 |
343 | #define CTRL_EXT_LINK_MODE_1000KX 0x00400000 |
344 | #define CTRL_EXT_LINK_MODE_SGMII 0x00800000 |
345 | #define CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 |
346 | #define CTRL_EXT_LINK_MODE_TBI 0x00C00000 |
347 | #define CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 |
348 | #define CTRL_EXT_EIAME __BIT(24) /* Extended Interrupt Auto Mask En */ |
349 | #define CTRL_EXT_I2C_ENA 0x02000000 /* I2C enable */ |
350 | #define CTRL_EXT_DRV_LOAD 0x10000000 |
351 | #define CTRL_EXT_PBA __BIT(31) /* PBA Support */ |
352 | |
353 | #define WMREG_MDIC 0x0020 /* MDI Control Register */ |
354 | #define MDIC_DATA(x) ((x) & 0xffff) |
355 | #define MDIC_REGADD(x) ((x) << 16) |
356 | #define MDIC_PHY_SHIFT 21 |
357 | #define MDIC_PHY_MASK __BITS(25, 21) |
358 | #define MDIC_PHYADD(x) ((x) << 21) |
359 | #define MDIC_OP_WRITE (1U << 26) |
360 | #define MDIC_OP_READ (2U << 26) |
361 | #define MDIC_READY (1U << 28) |
362 | #define MDIC_I (1U << 29) /* interrupt on MDI complete */ |
363 | #define MDIC_E (1U << 30) /* MDI error */ |
364 | #define MDIC_DEST (1U << 31) /* Destination */ |
365 | |
366 | #define WMREG_SCTL 0x0024 /* SerDes Control - RW */ |
367 | /* |
368 | * These 4 macros are also used for other 8bit control registers on the |
369 | * 82575 |
370 | */ |
371 | #define SCTL_CTL_READY (1U << 31) |
372 | #define SCTL_CTL_DATA_MASK 0x000000ff |
373 | #define SCTL_CTL_ADDR_SHIFT 8 |
374 | #define SCTL_CTL_POLL_TIMEOUT 640 |
375 | #define SCTL_DISABLE_SERDES_LOOPBACK 0x0400 |
376 | |
377 | #define WMREG_FEXTNVM4 0x0024 /* Future Extended NVM 4 - RW */ |
378 | #define FEXTNVM4_BEACON_DURATION __BITS(2, 0) |
379 | #define FEXTNVM4_BEACON_DURATION_8US 0x7 |
380 | #define FEXTNVM4_BEACON_DURATION_16US 0x3 |
381 | |
382 | #define WMREG_FCAL 0x0028 /* Flow Control Address Low */ |
383 | #define FCAL_CONST 0x00c28001 /* Flow Control MAC addr low */ |
384 | |
385 | #define WMREG_FCAH 0x002c /* Flow Control Address High */ |
386 | #define FCAH_CONST 0x00000100 /* Flow Control MAC addr high */ |
387 | |
388 | #define WMREG_FCT 0x0030 /* Flow Control Type */ |
389 | |
390 | #define WMREG_KUMCTRLSTA 0x0034 /* MAC-PHY interface - RW */ |
391 | #define KUMCTRLSTA_MASK 0x0000FFFF |
392 | #define KUMCTRLSTA_OFFSET 0x001F0000 |
393 | #define KUMCTRLSTA_OFFSET_SHIFT 16 |
394 | #define KUMCTRLSTA_REN 0x00200000 |
395 | |
396 | #define KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 |
397 | #define KUMCTRLSTA_OFFSET_CTRL 0x00000001 |
398 | #define KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 |
399 | #define KUMCTRLSTA_OFFSET_DIAG 0x00000003 |
400 | #define KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 |
401 | #define KUMCTRLSTA_OFFSET_K1_CONFIG 0x00000007 |
402 | #define KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 |
403 | #define KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 |
404 | #define KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E |
405 | #define KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F |
406 | |
407 | /* FIFO Control */ |
408 | #define KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 |
409 | #define KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 |
410 | |
411 | /* In-Band Control */ |
412 | #define KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT 0x00000500 |
413 | #define KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 |
414 | |
415 | /* Diag */ |
416 | #define KUMCTRLSTA_DIAG_NELPBK 0x1000 |
417 | |
418 | /* K1 Config */ |
419 | #define KUMCTRLSTA_K1_ENABLE 0x0002 |
420 | |
421 | /* Half-Duplex Control */ |
422 | #define KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 |
423 | #define KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 |
424 | |
425 | #define WMREG_VET 0x0038 /* VLAN Ethertype */ |
426 | #define WMREG_MDPHYA 0x003C /* PHY address - RW */ |
427 | |
428 | #define WMREG_FEXTNVM3 0x003c /* Future Extended NVM 3 */ |
429 | #define FEXTNVM3_PHY_CFG_COUNTER_MASK __BITS(27, 26) |
430 | #define FEXTNVM3_PHY_CFG_COUNTER_50MS __BIT(27) |
431 | |
432 | #define WMREG_RAL_BASE 0x0040 /* Receive Address List */ |
433 | #define WMREG_CORDOVA_RAL_BASE 0x5400 |
434 | #define WMREG_RAL_LO(b, x) ((b) + ((x) << 3)) |
435 | #define WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4) |
436 | /* |
437 | * Receive Address List: The LO part is the low-order 32-bits |
438 | * of the MAC address. The HI part is the high-order 16-bits |
439 | * along with a few control bits. |
440 | */ |
441 | #define RAL_AS(x) ((x) << 16) /* address select */ |
442 | #define RAL_AS_DEST RAL_AS(0) /* (cordova?) */ |
443 | #define RAL_AS_SOURCE RAL_AS(1) /* (cordova?) */ |
444 | #define RAL_RDR1 (1U << 30) /* put packet in alt. rx ring */ |
445 | #define RAL_AV (1U << 31) /* entry is valid */ |
446 | |
447 | #define WM_RAL_TABSIZE 15 /* RAL size for old devices */ |
448 | #define WM_RAL_TABSIZE_ICH8 7 /* RAL size for ICH* and PCH* */ |
449 | #define WM_RAL_TABSIZE_PCH2 5 /* RAL size for PCH2 */ |
450 | #define WM_RAL_TABSIZE_PCH_LPT 12 /* RAL size for PCH_LPT */ |
451 | #define WM_RAL_TABSIZE_82575 16 /* RAL size for 82575 */ |
452 | #define WM_RAL_TABSIZE_82576 24 /* RAL size for 82576 and 82580 */ |
453 | #define WM_RAL_TABSIZE_I350 32 /* RAL size for I350 */ |
454 | |
455 | #define WMREG_ICR 0x00c0 /* Interrupt Cause Register */ |
456 | #define ICR_TXDW (1U << 0) /* Tx desc written back */ |
457 | #define ICR_TXQE (1U << 1) /* Tx queue empty */ |
458 | #define ICR_LSC (1U << 2) /* link status change */ |
459 | #define ICR_RXSEQ (1U << 3) /* receive sequence error */ |
460 | #define ICR_RXDMT0 (1U << 4) /* Rx ring 0 nearly empty */ |
461 | #define ICR_RXO (1U << 6) /* Rx overrun */ |
462 | #define ICR_RXT0 (1U << 7) /* Rx ring 0 timer */ |
463 | #define ICR_MDAC (1U << 9) /* MDIO access complete */ |
464 | #define ICR_RXCFG (1U << 10) /* Receiving /C/ */ |
465 | #define ICR_GPI(x) (1U << (x)) /* general purpose interrupts */ |
466 | #define ICR_RXQ(x) __BIT(20+(x)) /* 82574: Rx queue x interrupt x=0,1 */ |
467 | #define ICR_TXQ(x) __BIT(22+(x)) /* 82574: Tx queue x interrupt x=0,1 */ |
468 | #define ICR_OTHER __BIT(24) /* 82574: Other interrupt */ |
469 | #define ICR_INT (1U << 31) /* device generated an interrupt */ |
470 | |
471 | #define WMREG_ITR 0x00c4 /* Interrupt Throttling Register */ |
472 | #define ITR_IVAL_MASK 0xffff /* Interval mask */ |
473 | #define ITR_IVAL_SHIFT 0 /* Interval shift */ |
474 | |
475 | #define WMREG_ICS 0x00c8 /* Interrupt Cause Set Register */ |
476 | /* See ICR bits. */ |
477 | |
478 | #define WMREG_IMS 0x00d0 /* Interrupt Mask Set Register */ |
479 | /* See ICR bits. */ |
480 | |
481 | #define WMREG_IMC 0x00d8 /* Interrupt Mask Clear Register */ |
482 | /* See ICR bits. */ |
483 | |
484 | #define WMREG_EIAC_82574 0x00dc /* Interrupt Auto Clear Register */ |
485 | #define WMREG_EIAC_82574_MSIX_MASK (ICR_RXQ(0) | ICR_RXQ(1) \ |
486 | | ICR_TXQ(0) | ICR_TXQ(1) | ICR_OTHER) |
487 | |
488 | #define WMREG_FEXTNVM7 0x00e4 /* Future Extended NVM 7 */ |
489 | #define FEXTNVM7_SIDE_CLK_UNGATE __BIT(2) |
490 | #define FEXTNVM7_DIS_SMB_PERST __BIT(5) |
491 | #define FEXTNVM7_DIS_PB_READ __BIT(18) |
492 | |
493 | #define WMREG_IVAR 0x00e4 /* Interrupt Vector Allocation Register */ |
494 | #define WMREG_IVAR0 0x01700 /* Interrupt Vector Allocation */ |
495 | #define IVAR_ALLOC_MASK __BITS(0, 6) /* Bit 5 and 6 are reserved */ |
496 | #define IVAR_VALID __BIT(7) |
497 | /* IVAR definitions for 82580 and newer */ |
498 | #define WMREG_IVAR_Q(x) (WMREG_IVAR0 + ((x) / 2) * 4) |
499 | #define IVAR_TX_MASK_Q(x) (0x000000ff << (((x) % 2) == 0 ? 8 : 24)) |
500 | #define IVAR_RX_MASK_Q(x) (0x000000ff << (((x) % 2) == 0 ? 0 : 16)) |
501 | /* IVAR definitions for 82576 */ |
502 | #define WMREG_IVAR_Q_82576(x) (WMREG_IVAR0 + ((x) & 0x7) * 4) |
503 | #define IVAR_TX_MASK_Q_82576(x) (0x000000ff << (((x) / 8) == 0 ? 8 : 24)) |
504 | #define IVAR_RX_MASK_Q_82576(x) (0x000000ff << (((x) / 8) == 0 ? 0 : 16)) |
505 | /* IVAR definitions for 82574 */ |
506 | #define IVAR_ALLOC_MASK_82574 __BITS(0, 2) |
507 | #define IVAR_VALID_82574 __BIT(3) |
508 | #define IVAR_TX_MASK_Q_82574(x) (0x0000000f << ((x) == 0 ? 8 : 12)) |
509 | #define IVAR_RX_MASK_Q_82574(x) (0x0000000f << ((x) == 0 ? 0 : 4)) |
510 | #define IVAR_OTHER_MASK __BITS(16, 19) |
511 | #define IVAR_INT_ON_ALL_WB __BIT(31) |
512 | |
513 | #define WMREG_IVAR_MISC 0x01740 /* IVAR for other causes */ |
514 | #define IVAR_MISC_TCPTIMER __BITS(0, 7) |
515 | #define IVAR_MISC_OTHER __BITS(8, 15) |
516 | |
517 | #define WMREG_LTRV 0x00f8 /* Latency Tolerance Reporting */ |
518 | #define LTRV_VALUE __BITS(9, 0) |
519 | #define LTRV_SCALE __BITS(12, 10) |
520 | #define LTRV_SCALE_MAX 5 |
521 | #define LTRV_SNOOP_REQ __BIT(15) |
522 | #define LTRV_SEND __BIT(30) |
523 | #define LTRV_NONSNOOP __BITS(31, 16) |
524 | #define LTRV_NONSNOOP_REQ __BIT(31) |
525 | |
526 | #define WMREG_RCTL 0x0100 /* Receive Control */ |
527 | #define RCTL_EN (1U << 1) /* receiver enable */ |
528 | #define RCTL_SBP (1U << 2) /* store bad packets */ |
529 | #define RCTL_UPE (1U << 3) /* unicast promisc. enable */ |
530 | #define RCTL_MPE (1U << 4) /* multicast promisc. enable */ |
531 | #define RCTL_LPE (1U << 5) /* large packet enable */ |
532 | #define RCTL_LBM(x) ((x) << 6) /* loopback mode */ |
533 | #define RCTL_LBM_NONE RCTL_LBM(0) |
534 | #define RCTL_LBM_PHY RCTL_LBM(3) |
535 | #define RCTL_RDMTS(x) ((x) << 8) /* receive desc. min thresh size */ |
536 | #define RCTL_RDMTS_1_2 RCTL_RDMTS(0) |
537 | #define RCTL_RDMTS_1_4 RCTL_RDMTS(1) |
538 | #define RCTL_RDMTS_1_8 RCTL_RDMTS(2) |
539 | #define RCTL_RDMTS_MASK RCTL_RDMTS(3) |
540 | #define RCTL_MO(x) ((x) << 12) /* multicast offset */ |
541 | #define RCTL_BAM (1U << 15) /* broadcast accept mode */ |
542 | #define RCTL_RDMTS_HEX __BIT(16) |
543 | #define RCTL_2k (0 << 16) /* 2k Rx buffers */ |
544 | #define RCTL_1k (1 << 16) /* 1k Rx buffers */ |
545 | #define RCTL_512 (2 << 16) /* 512 byte Rx buffers */ |
546 | #define RCTL_256 (3 << 16) /* 256 byte Rx buffers */ |
547 | #define RCTL_BSEX_16k (1 << 16) /* 16k Rx buffers (BSEX) */ |
548 | #define RCTL_BSEX_8k (2 << 16) /* 8k Rx buffers (BSEX) */ |
549 | #define RCTL_BSEX_4k (3 << 16) /* 4k Rx buffers (BSEX) */ |
550 | #define RCTL_DPF (1U << 22) /* discard pause frames */ |
551 | #define RCTL_PMCF (1U << 23) /* pass MAC control frames */ |
552 | #define RCTL_BSEX (1U << 25) /* buffer size extension (Livengood) */ |
553 | #define RCTL_SECRC (1U << 26) /* strip Ethernet CRC */ |
554 | |
555 | #define WMREG_OLD_RDTR0 0x0108 /* Receive Delay Timer (ring 0) */ |
556 | #define WMREG_RDTR 0x2820 |
557 | #define RDTR_FPD (1U << 31) /* flush partial descriptor */ |
558 | |
559 | #define WMREG_LTRC 0x01a0 /* Latency Tolerance Reportiong Control */ |
560 | |
561 | #define WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */ |
562 | #define WMREG_RDBAL(x) \ |
563 | ((x) < 4 ? (0x02800 + ((x) * 0x100)) : \ |
564 | (0x0C000 + ((x) * 0x40))) |
565 | |
566 | #define WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */ |
567 | #define WMREG_RDBAH(x) \ |
568 | ((x) < 4 ? (0x02804 + ((x) * 0x100)) : \ |
569 | (0x0c004 + ((x) * 0x40))) |
570 | |
571 | #define WMREG_OLD_RDLEN0 0x0118 /* Receive Descriptor Length (ring 0) */ |
572 | #define WMREG_RDLEN(x) \ |
573 | ((x) < 4 ? (0x02808 + ((x) * 0x100)) : \ |
574 | (0x0c008 + ((x) * 0x40))) |
575 | |
576 | #define WMREG_SRRCTL(x) \ |
577 | ((x) < 4 ? (0x0280c + ((x) * 0x100)) : \ |
578 | (0x0c00c + ((x) * 0x40))) /* additional recv control used in 82575 ... */ |
579 | #define SRRCTL_BSIZEPKT_MASK 0x0000007f |
580 | #define SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ |
581 | #define SRRCTL_BSIZEHDRSIZE_MASK 0x00000f00 |
582 | #define SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ |
583 | #define SRRCTL_DESCTYPE_LEGACY 0x00000000 |
584 | #define SRRCTL_DESCTYPE_ADV_ONEBUF (1U << 25) |
585 | #define SRRCTL_DESCTYPE_HDR_SPLIT (2U << 25) |
586 | #define SRRCTL_DESCTYPE_HDR_REPLICATION (3U << 25) |
587 | #define SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT (4U << 25) |
588 | #define SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS (5U << 25) /* 82575 only */ |
589 | #define SRRCTL_DESCTYPE_MASK (7U << 25) |
590 | #define SRRCTL_DROP_EN 0x80000000 |
591 | |
592 | #define WMREG_OLD_RDH0 0x0120 /* Receive Descriptor Head (ring 0) */ |
593 | #define WMREG_RDH(x) \ |
594 | ((x) < 4 ? (0x02810 + ((x) * 0x100)) : \ |
595 | (0x0C010 + ((x) * 0x40))) |
596 | |
597 | #define WMREG_OLD_RDT0 0x0128 /* Receive Descriptor Tail (ring 0) */ |
598 | #define WMREG_RDT(x) \ |
599 | ((x) < 4 ? (0x02818 + ((x) * 0x100)) : \ |
600 | (0x0C018 + ((x) * 0x40))) |
601 | |
602 | #define WMREG_RXDCTL(x) \ |
603 | ((x) < 4 ? (0x02828 + ((x) * 0x100)) : \ |
604 | (0x0c028 + ((x) * 0x40))) /* Receive Descriptor Control */ |
605 | #define RXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ |
606 | #define RXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ |
607 | #define RXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ |
608 | #define RXDCTL_GRAN (1U << 24) /* 0 = cacheline, 1 = descriptor */ |
609 | /* flags used starting with 82575 ... */ |
610 | #define RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ |
611 | #define RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ |
612 | |
613 | #define WMREG_OLD_RDTR1 0x0130 /* Receive Delay Timer (ring 1) */ |
614 | #define WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */ |
615 | #define WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */ |
616 | #define WMREG_OLD_RDLEN1 0x0140 /* Receive Drscriptor Length (ring 1) */ |
617 | #define WMREG_OLD_RDH1 0x0148 |
618 | #define WMREG_OLD_RDT1 0x0150 |
619 | #define WMREG_OLD_FCRTH 0x0160 /* Flow Control Rx Threshold Hi (OLD) */ |
620 | #define WMREG_FCRTL 0x2160 /* Flow Control Rx Threshold Lo */ |
621 | #define FCRTH_DFLT 0x00008000 |
622 | |
623 | #define WMREG_OLD_FCRTL 0x0168 /* Flow Control Rx Threshold Lo (OLD) */ |
624 | #define WMREG_FCRTH 0x2168 /* Flow Control Rx Threhsold Hi */ |
625 | #define FCRTL_DFLT 0x00004000 |
626 | #define FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ |
627 | |
628 | #define WMREG_FCTTV 0x0170 /* Flow Control Transmit Timer Value */ |
629 | #define FCTTV_DFLT 0x00000600 |
630 | |
631 | #define WMREG_TXCW 0x0178 /* Transmit Configuration Word (TBI mode) */ |
632 | /* See MII ANAR_X bits. */ |
633 | #define TXCW_FD (1U << 5) /* Full Duplex */ |
634 | #define TXCW_HD (1U << 6) /* Half Duplex */ |
635 | #define TXCW_SYM_PAUSE (1U << 7) /* sym pause request */ |
636 | #define TXCW_ASYM_PAUSE (1U << 8) /* asym pause request */ |
637 | #define TXCW_TxConfig (1U << 30) /* Tx Config */ |
638 | #define TXCW_ANE (1U << 31) /* Autonegotiate */ |
639 | |
640 | #define WMREG_RXCW 0x0180 /* Receive Configuration Word (TBI mode) */ |
641 | /* See MII ANLPAR_X bits. */ |
642 | #define RXCW_NC (1U << 26) /* no carrier */ |
643 | #define RXCW_IV (1U << 27) /* config invalid */ |
644 | #define RXCW_CC (1U << 28) /* config change */ |
645 | #define RXCW_C (1U << 29) /* /C/ reception */ |
646 | #define RXCW_SYNCH (1U << 30) /* synchronized */ |
647 | #define RXCW_ANC (1U << 31) /* autonegotiation complete */ |
648 | |
649 | #define WMREG_MTA 0x0200 /* Multicast Table Array */ |
650 | #define WMREG_CORDOVA_MTA 0x5200 |
651 | |
652 | #define WMREG_TCTL 0x0400 /* Transmit Control Register */ |
653 | #define TCTL_EN (1U << 1) /* transmitter enable */ |
654 | #define TCTL_PSP (1U << 3) /* pad short packets */ |
655 | #define TCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - collision threshold */ |
656 | #define TCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - collision distance */ |
657 | #define TCTL_SWXOFF (1U << 22) /* software XOFF */ |
658 | #define TCTL_RTLC (1U << 24) /* retransmit on late collision */ |
659 | #define TCTL_NRTU (1U << 25) /* no retransmit on underrun */ |
660 | #define TCTL_MULR (1U << 28) /* multiple request */ |
661 | |
662 | #define TX_COLLISION_THRESHOLD 15 |
663 | #define TX_COLLISION_DISTANCE_HDX 512 |
664 | #define TX_COLLISION_DISTANCE_FDX 64 |
665 | |
666 | #define WMREG_TCTL_EXT 0x0404 /* Transmit Control Register */ |
667 | #define TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ |
668 | #define TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ |
669 | |
670 | #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 |
671 | |
672 | #define WMREG_TIPG 0x0410 /* Transmit IPG Register */ |
673 | #define TIPG_IPGT(x) (x) /* IPG transmit time */ |
674 | #define TIPG_IPGR1(x) ((x) << 10) /* IPG receive time 1 */ |
675 | #define TIPG_IPGR2(x) ((x) << 20) /* IPG receive time 2 */ |
676 | #define TIPG_WM_DFLT (TIPG_IPGT(0x0a) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x0a)) |
677 | #define TIPG_LG_DFLT (TIPG_IPGT(0x06) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) |
678 | #define TIPG_1000T_DFLT (TIPG_IPGT(0x08) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) |
679 | #define TIPG_1000T_80003_DFLT \ |
680 | (TIPG_IPGT(0x08) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) |
681 | #define TIPG_10_100_80003_DFLT \ |
682 | (TIPG_IPGT(0x09) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) |
683 | |
684 | #define WMREG_TQC 0x0418 |
685 | |
686 | #define WMREG_OLD_TDBAL 0x0420 /* Transmit Descriptor Base Lo */ |
687 | #define WMREG_TDBAL(x) \ |
688 | ((x) < 4 ? (0x03800 + ((x) * 0x100)) : \ |
689 | (0x0E000 + ((x) * 0x40))) |
690 | |
691 | #define WMREG_OLD_TDBAH 0x0424 /* Transmit Descriptor Base Hi */ |
692 | #define WMREG_TDBAH(x)\ |
693 | ((x) < 4 ? (0x03804 + ((x) * 0x100)) : \ |
694 | (0x0E004 + ((x) * 0x40))) |
695 | |
696 | #define WMREG_OLD_TDLEN 0x0428 /* Transmit Descriptor Length */ |
697 | #define WMREG_TDLEN(x) \ |
698 | ((x) < 4 ? (0x03808 + ((x) * 0x100)) : \ |
699 | (0x0E008 + ((x) * 0x40))) |
700 | |
701 | #define WMREG_OLD_TDH 0x0430 /* Transmit Descriptor Head */ |
702 | #define WMREG_TDH(x) \ |
703 | ((x) < 4 ? (0x03810 + ((x) * 0x100)) : \ |
704 | (0x0E010 + ((x) * 0x40))) |
705 | |
706 | #define WMREG_OLD_TDT 0x0438 /* Transmit Descriptor Tail */ |
707 | #define WMREG_TDT(x) \ |
708 | ((x) < 4 ? (0x03818 + ((x) * 0x100)) : \ |
709 | (0x0E018 + ((x) * 0x40))) |
710 | |
711 | #define WMREG_OLD_TIDV 0x0440 /* Transmit Delay Interrupt Value */ |
712 | #define WMREG_TIDV 0x3820 |
713 | |
714 | #define WMREG_AIT 0x0458 /* Adaptive IFS Throttle */ |
715 | #define WMREG_VFTA 0x0600 |
716 | |
717 | #define WMREG_MDICNFG 0x0e04 /* MDC/MDIO Configuration Register */ |
718 | #define MDICNFG_PHY_SHIFT 21 |
719 | #define MDICNFG_PHY_MASK __BITS(25, 21) |
720 | #define MDICNFG_COM_MDIO __BIT(30) |
721 | #define MDICNFG_DEST __BIT(31) |
722 | |
723 | #define WM_MC_TABSIZE 128 |
724 | #define WM_ICH8_MC_TABSIZE 32 |
725 | #define WM_VLAN_TABSIZE 128 |
726 | |
727 | #define WMREG_PHPM 0x0e14 /* PHY Power Management */ |
728 | #define PHPM_GO_LINK_D __BIT(5) /* Go Link Disconnect */ |
729 | |
730 | #define WMREG_EEER 0x0e30 /* Energy Efficiency Ethernet "EEE" */ |
731 | #define EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ |
732 | #define EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ |
733 | #define EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ |
734 | #define EEER_EEER_NEG 0x20000000 /* EEER capability nego */ |
735 | #define EEER_EEER_RX_LPI_STATUS 0x40000000 /* EEER Rx in LPI state */ |
736 | #define EEER_EEER_TX_LPI_STATUS 0x80000000 /* EEER Tx in LPI state */ |
737 | #define WMREG_EEE_SU 0x0e34 /* EEE Setup */ |
738 | #define WMREG_IPCNFG 0x0e38 /* Internal PHY Configuration */ |
739 | #define IPCNFG_10BASE_TE 0x00000002 /* IPCNFG 10BASE-Te low power op. */ |
740 | #define IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ |
741 | #define IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ |
742 | |
743 | #define WMREG_EXTCNFCTR 0x0f00 /* Extended Configuration Control */ |
744 | #define EXTCNFCTR_PCIE_WRITE_ENABLE 0x00000001 |
745 | #define EXTCNFCTR_PHY_WRITE_ENABLE 0x00000002 |
746 | #define EXTCNFCTR_D_UD_ENABLE 0x00000004 |
747 | #define EXTCNFCTR_D_UD_LATENCY 0x00000008 |
748 | #define EXTCNFCTR_D_UD_OWNER 0x00000010 |
749 | #define EXTCNFCTR_MDIO_SW_OWNERSHIP 0x00000020 |
750 | #define EXTCNFCTR_MDIO_HW_OWNERSHIP 0x00000040 |
751 | #define EXTCNFCTR_GATE_PHY_CFG 0x00000080 |
752 | #define EXTCNFCTR_EXT_CNF_POINTER 0x0FFF0000 |
753 | |
754 | #define WMREG_PHY_CTRL 0x0f10 /* PHY control */ |
755 | #define PHY_CTRL_SPD_EN (1 << 0) |
756 | #define PHY_CTRL_D0A_LPLU (1 << 1) |
757 | #define PHY_CTRL_NOND0A_LPLU (1 << 2) |
758 | #define PHY_CTRL_NOND0A_GBE_DIS (1 << 3) |
759 | #define PHY_CTRL_GBE_DIS (1 << 6) |
760 | |
761 | #define WMREG_PCIEANACFG 0x0f18 /* PCIE Analog Config */ |
762 | |
763 | #define WMREG_IOSFPC 0x0f28 /* Tx corrupted data */ |
764 | |
765 | #define WMREG_PBA 0x1000 /* Packet Buffer Allocation */ |
766 | #define PBA_BYTE_SHIFT 10 /* KB -> bytes */ |
767 | #define PBA_ADDR_SHIFT 7 /* KB -> quadwords */ |
768 | #define PBA_8K 0x0008 |
769 | #define PBA_10K 0x000a |
770 | #define PBA_12K 0x000c |
771 | #define PBA_14K 0x000e |
772 | #define PBA_16K 0x0010 /* 16K, default Tx allocation */ |
773 | #define PBA_20K 0x0014 |
774 | #define PBA_22K 0x0016 |
775 | #define PBA_24K 0x0018 |
776 | #define PBA_26K 0x001a |
777 | #define PBA_30K 0x001e |
778 | #define PBA_32K 0x0020 |
779 | #define PBA_34K 0x0022 |
780 | #define PBA_35K 0x0023 |
781 | #define PBA_40K 0x0028 |
782 | #define PBA_48K 0x0030 /* 48K, default Rx allocation */ |
783 | #define PBA_64K 0x0040 |
784 | #define PBA_RXA_MASK __BITS(15, 0) |
785 | |
786 | #define WMREG_PBS 0x1008 /* Packet Buffer Size (ICH) */ |
787 | |
788 | #define WMREG_PBECCSTS 0x100c /* Packet Buffer ECC Status (PCH_LPT) */ |
789 | #define PBECCSTS_CORR_ERR_CNT_MASK 0x000000ff |
790 | #define PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000ff00 |
791 | #define PBECCSTS_UNCORR_ECC_ENABLE 0x00010000 |
792 | |
793 | #define WMREG_EEMNGCTL 0x1010 /* MNG EEprom Control */ |
794 | #define EEMNGCTL_CFGDONE_0 0x040000 /* MNG config cycle done */ |
795 | #define EEMNGCTL_CFGDONE_1 0x080000 /* 2nd port */ |
796 | |
797 | #define WMREG_I2CCMD 0x1028 /* SFPI2C Command Register - RW */ |
798 | #define I2CCMD_REG_ADDR_SHIFT 16 |
799 | #define I2CCMD_REG_ADDR 0x00ff0000 |
800 | #define I2CCMD_PHY_ADDR_SHIFT 24 |
801 | #define I2CCMD_PHY_ADDR 0x07000000 |
802 | #define I2CCMD_OPCODE_READ 0x08000000 |
803 | #define I2CCMD_OPCODE_WRITE 0x00000000 |
804 | #define I2CCMD_RESET 0x10000000 |
805 | #define I2CCMD_READY 0x20000000 |
806 | #define I2CCMD_INTERRUPT_ENA 0x40000000 |
807 | #define I2CCMD_ERROR 0x80000000 |
808 | #define MAX_SGMII_PHY_REG_ADDR 255 |
809 | #define I2CCMD_PHY_TIMEOUT 200 |
810 | |
811 | #define WMREG_EEWR 0x102c /* EEPROM write */ |
812 | |
813 | #define WMREG_PBA_ECC 0x01100 /* PBA ECC */ |
814 | #define PBA_ECC_COUNTER_MASK 0xfff00000 /* ECC counter mask */ |
815 | #define PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ |
816 | #define PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ |
817 | #define PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ |
818 | #define PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ |
819 | |
820 | #define WMREG_GPIE 0x01514 /* General Purpose Interrupt Enable */ |
821 | #define GPIE_NSICR __BIT(0) /* Non Selective Interrupt Clear */ |
822 | #define GPIE_MULTI_MSIX __BIT(4) /* Multiple MSIX */ |
823 | #define GPIE_EIAME __BIT(30) /* Extended Interrupt Auto Mask Ena. */ |
824 | #define GPIE_PBA __BIT(31) /* PBA support */ |
825 | |
826 | #define WMREG_EICS 0x01520 /* Ext. Interrupt Cause Set - WO */ |
827 | #define WMREG_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ |
828 | #define WMREG_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ |
829 | #define WMREG_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ |
830 | #define WMREG_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ |
831 | |
832 | #define WMREG_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ |
833 | |
834 | #define WMREG_MSIXBM(x) (0x1600 + (x) * 4) /* MSI-X Allocation */ |
835 | |
836 | #define EITR_RX_QUEUE(x) __BIT(0+(x)) /* Rx Queue x Interrupt x=[0-3] */ |
837 | #define EITR_TX_QUEUE(x) __BIT(8+(x)) /* Tx Queue x Interrupt x=[0-3] */ |
838 | #define EITR_TCP_TIMER 0x40000000 /* TCP Timer */ |
839 | #define EITR_OTHER 0x80000000 /* Interrupt Cause Active */ |
840 | |
841 | #define WMREG_EITR(x) (0x01680 + (0x4 * (x))) |
842 | #define EITR_ITR_INT_MASK 0x0000ffff |
843 | |
844 | #define WMREG_RXPBS 0x2404 /* Rx Packet Buffer Size */ |
845 | #define RXPBS_SIZE_MASK_82576 0x0000007F |
846 | |
847 | #define WMREG_RDFH 0x2410 /* Receive Data FIFO Head */ |
848 | #define WMREG_RDFT 0x2418 /* Receive Data FIFO Tail */ |
849 | #define WMREG_RDFHS 0x2420 /* Receive Data FIFO Head Saved */ |
850 | #define WMREG_RDFTS 0x2428 /* Receive Data FIFO Tail Saved */ |
851 | #define WMREG_RADV 0x282c /* Receive Interrupt Absolute Delay Timer */ |
852 | |
853 | #define WMREG_TXDMAC 0x3000 /* Transfer DMA Control */ |
854 | #define TXDMAC_DPP (1U << 0) /* disable packet prefetch */ |
855 | |
856 | #define WMREG_KABGTXD 0x3004 /* AFE and Gap Transmit Ref Data */ |
857 | #define KABGTXD_BGSQLBIAS 0x00050000 |
858 | |
859 | #define WMREG_TDFH 0x3410 /* Transmit Data FIFO Head */ |
860 | #define WMREG_TDFT 0x3418 /* Transmit Data FIFO Tail */ |
861 | #define WMREG_TDFHS 0x3420 /* Transmit Data FIFO Head Saved */ |
862 | #define WMREG_TDFTS 0x3428 /* Transmit Data FIFO Tail Saved */ |
863 | #define WMREG_TDFPC 0x3430 /* Transmit Data FIFO Packet Count */ |
864 | |
865 | #define WMREG_TXDCTL(n) /* Trandmit Descriptor Control */ \ |
866 | (((n) < 4) ? (0x3828 + ((n) * 0x100)) : (0xe028 + ((n) * 0x40))) |
867 | #define TXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ |
868 | #define TXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ |
869 | #define TXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ |
870 | /* flags used starting with 82575 ... */ |
871 | #define TXDCTL_COUNT_DESC __BIT(22) /* Enable the counting of desc. |
872 | still to be processed. */ |
873 | #define TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ |
874 | #define TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ |
875 | #define TXDCTL_PRIORITY 0x08000000 |
876 | |
877 | #define WMREG_TADV 0x382c /* Transmit Absolute Interrupt Delay Timer */ |
878 | #define WMREG_TSPMT 0x3830 /* TCP Segmentation Pad and Minimum |
879 | Threshold (Cordova) */ |
880 | #define TSPMT_TSMT(x) (x) /* TCP seg min transfer */ |
881 | #define TSPMT_TSPBP(x) ((x) << 16) /* TCP seg pkt buf padding */ |
882 | |
883 | #define WMREG_TARC0 0x3840 /* Tx arbitration count (0) */ |
884 | #define WMREG_TARC1 0x3940 /* Tx arbitration count (1) */ |
885 | |
886 | #define WMREG_CRCERRS 0x4000 /* CRC Error Count */ |
887 | #define WMREG_ALGNERRC 0x4004 /* Alignment Error Count */ |
888 | #define WMREG_SYMERRC 0x4008 /* Symbol Error Count */ |
889 | #define WMREG_RXERRC 0x400c /* receive error Count - R/clr */ |
890 | #define WMREG_MPC 0x4010 /* Missed Packets Count - R/clr */ |
891 | #define WMREG_COLC 0x4028 /* collision Count - R/clr */ |
892 | #define WMREG_SEC 0x4038 /* Sequence Error Count */ |
893 | #define WMREG_CEXTERR 0x403c /* Carrier Extension Error Count */ |
894 | #define WMREG_RLEC 0x4040 /* Receive Length Error Count */ |
895 | #define WMREG_XONRXC 0x4048 /* XON Rx Count - R/clr */ |
896 | #define WMREG_XONTXC 0x404c /* XON Tx Count - R/clr */ |
897 | #define WMREG_XOFFRXC 0x4050 /* XOFF Rx Count - R/clr */ |
898 | #define WMREG_XOFFTXC 0x4054 /* XOFF Tx Count - R/clr */ |
899 | #define WMREG_FCRUC 0x4058 /* Flow Control Rx Unsupported Count - R/clr */ |
900 | #define WMREG_RNBC 0x40a0 /* Receive No Buffers Count */ |
901 | #define WMREG_TLPIC 0x4148 /* EEE Tx LPI Count */ |
902 | #define WMREG_RLPIC 0x414c /* EEE Rx LPI Count */ |
903 | |
904 | #define WMREG_PCS_CFG 0x4200 /* PCS Configuration */ |
905 | #define PCS_CFG_PCS_EN __BIT(3) |
906 | |
907 | #define WMREG_PCS_LCTL 0x4208 /* PCS Link Control */ |
908 | #define PCS_LCTL_FSV_1000 __BIT(2) /* AN Timeout Enable */ |
909 | #define PCS_LCTL_FDV_FULL __BIT(3) /* AN Timeout Enable */ |
910 | #define PCS_LCTL_FSD __BIT(4) /* AN Timeout Enable */ |
911 | #define PCS_LCTL_FORCE_FC __BIT(7) /* AN Timeout Enable */ |
912 | #define PCS_LCTL_AN_ENABLE __BIT(16) /* AN Timeout Enable */ |
913 | #define PCS_LCTL_AN_RESTART __BIT(17) /* AN Timeout Enable */ |
914 | #define PCS_LCTL_AN_TIMEOUT __BIT(18) /* AN Timeout Enable */ |
915 | |
916 | #define WMREG_PCS_LSTS 0x420c /* PCS Link Status */ |
917 | #define PCS_LSTS_LINKOK __BIT(0) |
918 | #define PCS_LSTS_SPEED_100 __BIT(1) |
919 | #define PCS_LSTS_SPEED_1000 __BIT(2) |
920 | #define PCS_LSTS_FDX __BIT(3) |
921 | #define PCS_LSTS_AN_COMP __BIT(16) |
922 | |
923 | #define WMREG_PCS_ANADV 0x4218 /* AN Advertsement */ |
924 | #define WMREG_PCS_LPAB 0x421c /* Link Partnet Ability */ |
925 | |
926 | #define WMREG_RXCSUM 0x5000 /* Receive Checksum register */ |
927 | #define RXCSUM_PCSS 0x000000ff /* Packet Checksum Start */ |
928 | #define RXCSUM_IPOFL (1U << 8) /* IP checksum offload */ |
929 | #define RXCSUM_TUOFL (1U << 9) /* TCP/UDP checksum offload */ |
930 | #define RXCSUM_IPV6OFL (1U << 10) /* IPv6 checksum offload */ |
931 | #define RXCSUM_CRCOFL (1U << 11) /* SCTP CRC32 checksum offload */ |
932 | #define RXCSUM_IPPCSE (1U << 12) /* IP payload checksum enable */ |
933 | #define RXCSUM_PCSD (1U << 13) /* packet checksum disabled */ |
934 | |
935 | #define WMREG_RLPML 0x5004 /* Rx Long Packet Max Length */ |
936 | |
937 | #define WMREG_RFCTL 0x5008 /* Receive Filter Control */ |
938 | #define WMREG_RFCTL_NFSWDIS __BIT(6) /* NFS Write Disable */ |
939 | #define WMREG_RFCTL_NFSRDIS __BIT(7) /* NFS Read Disable */ |
940 | #define WMREG_RFCTL_ACKDIS __BIT(12) /* ACK Accelerate Disable */ |
941 | #define WMREG_RFCTL_ACKD_DIS __BIT(13) /* ACK data Disable */ |
942 | #define WMREG_RFCTL_IPV6EXDIS __BIT(16) /* IPv6 Extension Header Disable */ |
943 | #define WMREG_RFCTL_NEWIPV6EXDIS __BIT(17) /* New IPv6 Extension Header */ |
944 | |
945 | #define WMREG_WUC 0x5800 /* Wakeup Control */ |
946 | #define WUC_APME 0x00000001 /* APM Enable */ |
947 | #define WUC_PME_EN 0x00000002 /* PME Enable */ |
948 | |
949 | #define WMREG_WUFC 0x5808 /* Wakeup Filter COntrol */ |
950 | #define WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ |
951 | #define WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ |
952 | #define WUFC_MC 0x00000008 /* Directed Multicast Wakeup En */ |
953 | #define WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ |
954 | #define WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup En */ |
955 | #define WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup En */ |
956 | #define WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup En */ |
957 | |
958 | #define WMREG_MRQC 0x5818 /* Multiple Receive Queues Command */ |
959 | #define 0x00000000 |
960 | #define __BIT(0) /* enable RSS for 82574 */ |
961 | #define __BIT(1) /* enable hardware max RSS without VMDq */ |
962 | #define __BITS(1, 0) /* enable RSS with VMDq */ |
963 | #define MRQC_DEFQ_MASK __BITS(5, 3) |
964 | /* |
965 | * Defines the default queue in non VMDq |
966 | * mode according to value of the Multiple Receive |
967 | * Queues Enable field. |
968 | */ |
969 | #define __SHFTIN(__BIT(1), MRQC_DEFQ_MASK) |
970 | /* |
971 | * the destination of all packets |
972 | * not forwarded by RSS or filters |
973 | */ |
974 | #define MRQC_DEFQ_NOT_MAC_ETH __SHFTIN(__BITS(1, 0), MRQC_DEFQ_MASK) |
975 | /* |
976 | * Def_Q field is ignored. Queueing |
977 | * decision of all packets not forwarded |
978 | * by MAC address and Ether-type filters |
979 | * is according to VT_CTL.DEF_PL field. |
980 | */ |
981 | #define MRQC_DEFQ_IGNORED1 __SHFTIN(__BIT(2), MRQC_DEFQ_MASK) |
982 | /* Def_Q field is ignored */ |
983 | #define MRQC_DEFQ_IGNORED2 __SHFTIN(__BIT(2)|__BIT(0), MRQC_DEFQ_MASK) |
984 | /* Def_Q field is ignored */ |
985 | #define MRQC_DEFQ_VMDQ __SHFTIN(__BITS(2, 1), MRQC_DEFQ_MASK) |
986 | /* for VMDq mode */ |
987 | #define __BIT(16) |
988 | #define __BIT(17) |
989 | #define __BIT(18) |
990 | #define __BIT(19) |
991 | #define __BIT(20) |
992 | #define __BIT(21) |
993 | #define __BIT(22) |
994 | #define __BIT(23) |
995 | #define __BIT(24) |
996 | |
997 | #define WMREG_RETA_Q(x) (0x5c00 + ((x) >> 2) * 4) /* Redirection Table */ |
998 | #define RETA_NUM_ENTRIES 128 |
999 | #define RETA_ENTRY_MASK_Q(x) (0x000000ff << (((x) % 4) * 8)) /* Redirection Table */ |
1000 | #define RETA_ENT_QINDEX_MASK __BITS(3,0) /*queue index for 82580 and newer */ |
1001 | #define RETA_ENT_QINDEX0_MASK_82575 __BITS(3,2) /*queue index for pool0 */ |
1002 | #define RETA_ENT_QINDEX1_MASK_82575 __BITS(7,6) /*queue index for pool1 and regular RSS */ |
1003 | #define RETA_ENT_QINDEX_MASK_82574 __BIT(7) /*queue index for 82574 */ |
1004 | |
1005 | #define (x) (0x5c80 + (x) * 4) /* RSS Random Key Register */ |
1006 | #define 10 |
1007 | |
1008 | #define WMREG_MANC 0x5820 /* Management Control */ |
1009 | #define MANC_SMBUS_EN 0x00000001 |
1010 | #define MANC_ASF_EN 0x00000002 |
1011 | #define MANC_ARP_EN 0x00002000 |
1012 | #define MANC_RECV_TCO_RESET 0x00010000 |
1013 | #define MANC_RECV_TCO_EN 0x00020000 |
1014 | #define MANC_BLK_PHY_RST_ON_IDE 0x00040000 |
1015 | #define MANC_RECV_ALL 0x00080000 |
1016 | #define MANC_EN_MAC_ADDR_FILTER 0x00100000 |
1017 | #define MANC_EN_MNG2HOST 0x00200000 |
1018 | |
1019 | #define WMREG_MANC2H 0x5860 /* Management Control To Host - RW */ |
1020 | #define MANC2H_PORT_623 (1 << 5) |
1021 | #define MANC2H_PORT_624 (1 << 6) |
1022 | |
1023 | #define WMREG_GCR 0x5b00 /* PCIe Control */ |
1024 | #define GCR_RXD_NO_SNOOP 0x00000001 |
1025 | #define GCR_RXDSCW_NO_SNOOP 0x00000002 |
1026 | #define GCR_RXDSCR_NO_SNOOP 0x00000004 |
1027 | #define GCR_TXD_NO_SNOOP 0x00000008 |
1028 | #define GCR_TXDSCW_NO_SNOOP 0x00000010 |
1029 | #define GCR_TXDSCR_NO_SNOOP 0x00000020 |
1030 | #define GCR_CMPL_TMOUT_MASK 0x0000f000 |
1031 | #define GCR_CMPL_TMOUT_10MS 0x00001000 |
1032 | #define GCR_CMPL_TMOUT_RESEND 0x00010000 |
1033 | #define GCR_CAP_VER2 0x00040000 |
1034 | #define GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 |
1035 | |
1036 | #define WMREG_FACTPS 0x5b30 /* Function Active and Power State to MNG */ |
1037 | #define FACTPS_MNGCG 0x20000000 |
1038 | #define FACTPS_LFS 0x40000000 /* LAN Function Select */ |
1039 | |
1040 | #define WMREG_GIOCTL 0x5b44 /* GIO Analog Control Register */ |
1041 | #define WMREG_CCMCTL 0x5b48 /* CCM Control Register */ |
1042 | #define WMREG_SCCTL 0x5b4c /* PCIc PLL Configuration Register */ |
1043 | |
1044 | #define WMREG_SWSM 0x5b50 /* SW Semaphore */ |
1045 | #define SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ |
1046 | #define SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ |
1047 | #define SWSM_WMNG 0x00000004 /* Wake MNG Clock */ |
1048 | #define SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ |
1049 | /* Intel driver defines H2ME register at 0x5b50 */ |
1050 | #define WMREG_H2ME 0x5b50 /* SW Semaphore */ |
1051 | #define H2ME_ULP __BIT(11) |
1052 | #define H2ME_ENFORCE_SETTINGS __BIT(12) |
1053 | |
1054 | #define WMREG_FWSM 0x5b54 /* FW Semaphore */ |
1055 | #define FWSM_MODE __BITS(1, 3) |
1056 | #define MNG_ICH_IAMT_MODE 0x2 /* PT mode? */ |
1057 | #define MNG_IAMT_MODE 0x3 |
1058 | #define FWSM_RSPCIPHY __BIT(6) /* Reset PHY on PCI reset */ |
1059 | #define FWSM_WLOCK_MAC __BITS(7, 9) /* Reset PHY on PCI reset */ |
1060 | #define FWSM_ULP_CFG_DONE __BIT(10) |
1061 | #define FWSM_FW_VALID __BIT(15) /* FW established a valid mode */ |
1062 | |
1063 | #define WMREG_SWSM2 0x5b58 /* SW Semaphore 2 */ |
1064 | #define SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ |
1065 | |
1066 | #define WMREG_SW_FW_SYNC 0x5b5c /* software-firmware semaphore */ |
1067 | #define SWFW_EEP_SM 0x0001 /* eeprom access */ |
1068 | #define SWFW_PHY0_SM 0x0002 /* first ctrl phy access */ |
1069 | #define SWFW_PHY1_SM 0x0004 /* second ctrl phy access */ |
1070 | #define SWFW_MAC_CSR_SM 0x0008 |
1071 | #define SWFW_PHY2_SM 0x0020 /* first ctrl phy access */ |
1072 | #define SWFW_PHY3_SM 0x0040 /* first ctrl phy access */ |
1073 | #define SWFW_SOFT_SHIFT 0 /* software semaphores */ |
1074 | #define SWFW_FIRM_SHIFT 16 /* firmware semaphores */ |
1075 | |
1076 | #define WMREG_GCR2 0x5b64 /* 3GPIO Control Register 2 */ |
1077 | #define WMREG_FEXTNVM9 0x5bb4 /* Future Extended NVM 9 */ |
1078 | #define WMREG_FEXTNVM11 0x5bbc /* Future Extended NVM 11 */ |
1079 | #define FEXTNVM11_DIS_MULRFIX __BIT(13) /* Disable MULR fix */ |
1080 | |
1081 | #define WMREG_CRC_OFFSET 0x5f50 |
1082 | |
1083 | #define WMREG_EEC 0x12010 |
1084 | #define EEC_FLASH_DETECTED (1U << 19) /* FLASH */ |
1085 | #define EEC_FLUPD (1U << 23) /* Update FLASH */ |
1086 | |
1087 | #define WMREG_EEARBC_I210 0x12024 |
1088 | |
1089 | /* |
1090 | * NVM related values. |
1091 | * Microwire, SPI, and flash |
1092 | */ |
1093 | #define UWIRE_OPC_ERASE 0x04 /* MicroWire "erase" opcode */ |
1094 | #define UWIRE_OPC_WRITE 0x05 /* MicroWire "write" opcode */ |
1095 | #define UWIRE_OPC_READ 0x06 /* MicroWire "read" opcode */ |
1096 | |
1097 | #define SPI_OPC_WRITE 0x02 /* SPI "write" opcode */ |
1098 | #define SPI_OPC_READ 0x03 /* SPI "read" opcode */ |
1099 | #define SPI_OPC_A8 0x08 /* opcode bit 3 == address bit 8 */ |
1100 | #define SPI_OPC_WREN 0x06 /* SPI "set write enable" opcode */ |
1101 | #define SPI_OPC_WRDI 0x04 /* SPI "clear write enable" opcode */ |
1102 | #define SPI_OPC_RDSR 0x05 /* SPI "read status" opcode */ |
1103 | #define SPI_OPC_WRSR 0x01 /* SPI "write status" opcode */ |
1104 | #define SPI_MAX_RETRIES 5000 /* max wait of 5ms for RDY signal */ |
1105 | |
1106 | #define SPI_SR_RDY 0x01 |
1107 | #define SPI_SR_WEN 0x02 |
1108 | #define SPI_SR_BP0 0x04 |
1109 | #define SPI_SR_BP1 0x08 |
1110 | #define SPI_SR_WPEN 0x80 |
1111 | |
1112 | #define NVM_CHECKSUM 0xBABA |
1113 | #define NVM_SIZE 0x0040 |
1114 | #define NVM_WORD_SIZE_BASE_SHIFT 6 |
1115 | |
1116 | #define NVM_OFF_MACADDR 0x0000 /* MAC address offset 0 */ |
1117 | #define NVM_OFF_MACADDR1 0x0001 /* MAC address offset 1 */ |
1118 | #define NVM_OFF_MACADDR2 0x0002 /* MAC address offset 2 */ |
1119 | #define NVM_OFF_COMPAT 0x0003 |
1120 | #define NVM_OFF_ID_LED_SETTINGS 0x0004 |
1121 | #define NVM_OFF_VERSION 0x0005 |
1122 | #define NVM_OFF_CFG1 0x000a /* config word 1 */ |
1123 | #define NVM_OFF_CFG2 0x000f /* config word 2 */ |
1124 | #define NVM_OFF_EEPROM_SIZE 0x0012 /* NVM SIZE */ |
1125 | #define NVM_OFF_CFG4 0x0013 /* config word 4 */ |
1126 | #define NVM_OFF_CFG3_PORTB 0x0014 /* config word 3 */ |
1127 | #define NVM_OFF_FUTURE_INIT_WORD1 0x0019 |
1128 | #define NVM_OFF_INIT_3GIO_3 0x001a /* PCIe Initial Configuration Word 3 */ |
1129 | #define NVM_OFF_K1_CONFIG 0x001b /* NVM K1 Config */ |
1130 | #define NVM_OFF_LED_1_CFG 0x001c |
1131 | #define NVM_OFF_LED_0_2_CFG 0x001f |
1132 | #define NVM_OFF_SWDPIN 0x0020 /* SWD Pins (Cordova) */ |
1133 | #define NVM_OFF_CFG3_PORTA 0x0024 /* config word 3 */ |
1134 | #define NVM_OFF_ALT_MAC_ADDR_PTR 0x0037 /* to the alternative MAC addresses */ |
1135 | #define NVM_OFF_COMB_VER_PTR 0x003d |
1136 | #define NVM_OFF_IMAGE_UID0 0x0042 |
1137 | #define NVM_OFF_IMAGE_UID1 0x0043 |
1138 | |
1139 | #define NVM_COMPAT_VALID_CHECKSUM 0x0001 |
1140 | |
1141 | #define NVM_CFG1_LVDID (1U << 0) |
1142 | #define NVM_CFG1_LSSID (1U << 1) |
1143 | #define NVM_CFG1_PME_CLOCK (1U << 2) |
1144 | #define NVM_CFG1_PM (1U << 3) |
1145 | #define NVM_CFG1_ILOS (1U << 4) |
1146 | #define NVM_CFG1_SWDPIO_SHIFT 5 |
1147 | #define NVM_CFG1_SWDPIO_MASK (0xf << NVM_CFG1_SWDPIO_SHIFT) |
1148 | #define NVM_CFG1_IPS1 (1U << 8) |
1149 | #define NVM_CFG1_LRST (1U << 9) |
1150 | #define NVM_CFG1_FD (1U << 10) |
1151 | #define NVM_CFG1_FRCSPD (1U << 11) |
1152 | #define NVM_CFG1_IPS0 (1U << 12) |
1153 | #define NVM_CFG1_64_32_BAR (1U << 13) |
1154 | |
1155 | #define NVM_CFG2_CSR_RD_SPLIT (1U << 1) |
1156 | #define NVM_CFG2_82544_APM_EN (1U << 2) |
1157 | #define NVM_CFG2_64_BIT (1U << 3) |
1158 | #define NVM_CFG2_MAX_READ (1U << 4) |
1159 | #define NVM_CFG2_DMCR_MAP (1U << 5) |
1160 | #define NVM_CFG2_133_CAP (1U << 6) |
1161 | #define NVM_CFG2_MSI_DIS (1U << 7) |
1162 | #define NVM_CFG2_FLASH_DIS (1U << 8) |
1163 | #define NVM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9) |
1164 | #define NVM_CFG2_APM_EN (1U << 10) |
1165 | #define NVM_CFG2_ANE (1U << 11) |
1166 | #define NVM_CFG2_PAUSE(x) (((x) & 3) >> 12) |
1167 | #define NVM_CFG2_ASDE (1U << 14) |
1168 | #define NVM_CFG2_APM_PME (1U << 15) |
1169 | #define NVM_CFG2_SWDPIO_SHIFT 4 |
1170 | #define NVM_CFG2_SWDPIO_MASK (0xf << NVM_CFG2_SWDPIO_SHIFT) |
1171 | #define NVM_CFG2_MNGM_SHIFT 13 /* Manageability Operation mode */ |
1172 | #define NVM_CFG2_MNGM_MASK (3U << NVM_CFG2_MNGM_SHIFT) |
1173 | #define NVM_CFG2_MNGM_DIS 0 |
1174 | #define NVM_CFG2_MNGM_NCSI 1 |
1175 | #define NVM_CFG2_MNGM_PT 2 |
1176 | |
1177 | #define NVM_COMPAT_SERDES_FORCE_MODE __BIT(14) /* Don't use autonego */ |
1178 | |
1179 | #define NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM 0x0040 |
1180 | |
1181 | #define NVM_K1_CONFIG_ENABLE 0x01 |
1182 | |
1183 | #define NVM_SWDPIN_MASK 0xdf |
1184 | #define NVM_SWDPIN_SWDPIN_SHIFT 0 |
1185 | #define NVM_SWDPIN_SWDPIO_SHIFT 8 |
1186 | |
1187 | #define NVM_3GIO_3_ASPM_MASK (0x3 << 2) /* Active State PM Support */ |
1188 | |
1189 | #define NVM_CFG3_APME (1U << 10) |
1190 | #define NVM_CFG3_PORTA_EXT_MDIO (1U << 2) /* External MDIO Interface */ |
1191 | #define NVM_CFG3_PORTA_COM_MDIO (1U << 3) /* MDIO Interface is shared */ |
1192 | |
1193 | #define NVM_OFF_MACADDR_82571(x) (3 * (x)) |
1194 | |
1195 | /* |
1196 | * EEPROM Partitioning. See Table 6-1, "EEPROM Top Level Partitioning" |
1197 | * in 82580's datasheet. |
1198 | */ |
1199 | #define NVM_OFF_LAN_FUNC_82580(x) ((x) ? (0x40 + (0x40 * (x))) : 0) |
1200 | |
1201 | #define NVM_COMBO_VER_OFF 0x0083 |
1202 | |
1203 | #define NVM_MAJOR_MASK 0xf000 |
1204 | #define NVM_MAJOR_SHIFT 12 |
1205 | #define NVM_MINOR_MASK 0x0ff0 |
1206 | #define NVM_MINOR_SHIFT 4 |
1207 | #define NVM_BUILD_MASK 0x000f |
1208 | #define NVM_UID_VALID 0x8000 |
1209 | |
1210 | /* iNVM Registers for i21[01] */ |
1211 | #define WM_INVM_DATA_REG(reg) (0x12120 + 4*(reg)) |
1212 | #define INVM_SIZE 64 /* Number of INVM Data Registers */ |
1213 | |
1214 | /* iNVM default vaule */ |
1215 | #define NVM_INIT_CTRL_2_DEFAULT_I211 0x7243 |
1216 | #define NVM_INIT_CTRL_4_DEFAULT_I211 0x00c1 |
1217 | #define NVM_LED_1_CFG_DEFAULT_I211 0x0184 |
1218 | #define NVM_LED_0_2_CFG_DEFAULT_I211 0x200c |
1219 | #define NVM_RESERVED_WORD 0xffff |
1220 | |
1221 | #define INVM_DWORD_TO_RECORD_TYPE(dword) ((dword) & 0x7) |
1222 | #define INVM_DWORD_TO_WORD_ADDRESS(dword) (((dword) & 0x0000FE00) >> 9) |
1223 | #define INVM_DWORD_TO_WORD_DATA(dword) (((dword) & 0xFFFF0000) >> 16) |
1224 | |
1225 | #define INVM_UNINITIALIZED_STRUCTURE 0x0 |
1226 | #define INVM_WORD_AUTOLOAD_STRUCTURE 0x1 |
1227 | #define INVM_CSR_AUTOLOAD_STRUCTURE 0x2 |
1228 | #define INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE 0x3 |
1229 | #define INVM_RSA_KEY_SHA256_STRUCTURE 0x4 |
1230 | #define INVM_INVALIDATED_STRUCTURE 0xf |
1231 | |
1232 | #define INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8 |
1233 | #define INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1 |
1234 | |
1235 | #define INVM_DEFAULT_AL 0x202f |
1236 | #define INVM_AUTOLOAD 0x0a |
1237 | #define INVM_PLL_WO_VAL 0x0010 |
1238 | |
1239 | /* Version and Image Type field */ |
1240 | #define INVM_VER_1 __BITS(12,3) |
1241 | #define INVM_VER_2 __BITS(22,13) |
1242 | #define INVM_IMGTYPE __BITS(28,23) |
1243 | #define INVM_MINOR __BITS(3,0) |
1244 | #define INVM_MAJOR __BITS(9,4) |
1245 | |
1246 | /* Word definitions for ID LED Settings */ |
1247 | #define ID_LED_RESERVED_FFFF 0xFFFF |
1248 | |
1249 | /* ich8 flash control */ |
1250 | #define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ |
1251 | #define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ |
1252 | #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ |
1253 | #define ICH_FLASH_SEG_SIZE_256 256 |
1254 | #define ICH_FLASH_SEG_SIZE_4K 4096 |
1255 | #define ICH_FLASH_SEG_SIZE_64K 65536 |
1256 | |
1257 | #define ICH_CYCLE_READ 0x0 |
1258 | #define ICH_CYCLE_RESERVED 0x1 |
1259 | #define ICH_CYCLE_WRITE 0x2 |
1260 | #define ICH_CYCLE_ERASE 0x3 |
1261 | |
1262 | #define ICH_FLASH_GFPREG 0x0000 |
1263 | #define ICH_FLASH_HSFSTS 0x0004 /* Flash Status Register */ |
1264 | #define HSFSTS_DONE 0x0001 /* Flash Cycle Done */ |
1265 | #define HSFSTS_ERR 0x0002 /* Flash Cycle Error */ |
1266 | #define HSFSTS_DAEL 0x0004 /* Direct Access error Log */ |
1267 | #define HSFSTS_ERSZ_MASK 0x0018 /* Block/Sector Erase Size */ |
1268 | #define HSFSTS_ERSZ_SHIFT 3 |
1269 | #define HSFSTS_FLINPRO 0x0020 /* flash SPI cycle in Progress */ |
1270 | #define HSFSTS_FLDVAL 0x4000 /* Flash Descriptor Valid */ |
1271 | #define HSFSTS_FLLK 0x8000 /* Flash Configuration Lock-Down */ |
1272 | #define ICH_FLASH_HSFCTL 0x0006 /* Flash control Register */ |
1273 | #define HSFCTL_GO 0x0001 /* Flash Cycle Go */ |
1274 | #define HSFCTL_CYCLE_MASK 0x0006 /* Flash Cycle */ |
1275 | #define HSFCTL_CYCLE_SHIFT 1 |
1276 | #define HSFCTL_BCOUNT_MASK 0x0300 /* Data Byte Count */ |
1277 | #define HSFCTL_BCOUNT_SHIFT 8 |
1278 | #define ICH_FLASH_FADDR 0x0008 |
1279 | #define ICH_FLASH_FDATA0 0x0010 |
1280 | #define ICH_FLASH_FRACC 0x0050 |
1281 | #define ICH_FLASH_FREG0 0x0054 |
1282 | #define ICH_FLASH_FREG1 0x0058 |
1283 | #define ICH_FLASH_FREG2 0x005C |
1284 | #define ICH_FLASH_FREG3 0x0060 |
1285 | #define ICH_FLASH_FPR0 0x0074 |
1286 | #define ICH_FLASH_FPR1 0x0078 |
1287 | #define ICH_FLASH_SSFSTS 0x0090 |
1288 | #define ICH_FLASH_SSFCTL 0x0092 |
1289 | #define ICH_FLASH_PREOP 0x0094 |
1290 | #define ICH_FLASH_OPTYPE 0x0096 |
1291 | #define 0x0098 |
1292 | |
1293 | #define ICH_FLASH_REG_MAPSIZE 0x00A0 |
1294 | #define ICH_FLASH_SECTOR_SIZE 4096 |
1295 | #define ICH_GFPREG_BASE_MASK 0x1FFF |
1296 | #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF |
1297 | |
1298 | #define ICH_NVM_SIG_WORD 0x13 |
1299 | #define ICH_NVM_SIG_MASK 0xc000 |
1300 | #define ICH_NVM_VALID_SIG_MASK 0xc0 |
1301 | #define ICH_NVM_SIG_VALUE 0x80 |
1302 | |
1303 | #define NVM_SIZE_MULTIPLIER 4096 /* multiplier for NVMS field */ |
1304 | #define WM_PCH_SPT_FLASHOFFSET 0xe000 /* offset of NVM access regs(PCH_SPT)*/ |
1305 | |
1306 | /* for PCI express Capability registers */ |
1307 | #define WM_PCIE_DCSR2_16MS 0x00000005 |
1308 | |
1309 | /* SFF SFP ROM data */ |
1310 | #define SFF_SFP_ID_OFF 0x00 |
1311 | #define SFF_SFP_ID_UNKNOWN 0x00 /* Unknown */ |
1312 | #define SFF_SFP_ID_SFF 0x02 /* Module soldered to motherboard */ |
1313 | #define SFF_SFP_ID_SFP 0x03 /* SFP transceiver */ |
1314 | |
1315 | #define SFF_SFP_ETH_FLAGS_OFF 0x06 |
1316 | #define SFF_SFP_ETH_FLAGS_1000SX 0x01 |
1317 | #define SFF_SFP_ETH_FLAGS_1000LX 0x02 |
1318 | #define SFF_SFP_ETH_FLAGS_1000CX 0x04 |
1319 | #define SFF_SFP_ETH_FLAGS_1000T 0x08 |
1320 | #define SFF_SFP_ETH_FLAGS_100FX 0x10 |
1321 | |
1322 | /* I21[01] PHY related definitions */ |
1323 | #define GS40G_PAGE_SELECT 0x16 |
1324 | #define GS40G_PAGE_SHIFT 16 |
1325 | #define GS40G_OFFSET_MASK 0xffff |
1326 | #define GS40G_PHY_PLL_FREQ_PAGE 0xfc0000 |
1327 | #define GS40G_PHY_PLL_FREQ_REG 0x000e |
1328 | #define GS40G_PHY_PLL_UNCONF 0xff |
1329 | |
1330 | /* advanced TX descriptor for 82575 and newer */ |
1331 | typedef union nq_txdesc { |
1332 | struct { |
1333 | uint64_t nqtxd_addr; |
1334 | uint32_t nqtxd_cmdlen; |
1335 | uint32_t nqtxd_fields; |
1336 | } nqtx_data; |
1337 | struct { |
1338 | uint32_t nqtxc_vl_len; |
1339 | uint32_t nqtxc_sn; |
1340 | uint32_t nqtxc_cmd; |
1341 | uint32_t nqtxc_mssidx; |
1342 | } nqrx_ctx; |
1343 | } __packed nq_txdesc_t; |
1344 | |
1345 | |
1346 | /* Commands for nqtxd_cmdlen and nqtxc_cmd */ |
1347 | #define NQTX_CMD_EOP (1U << 24) /* end of packet */ |
1348 | #define NQTX_CMD_IFCS (1U << 25) /* insert FCS */ |
1349 | #define NQTX_CMD_RS (1U << 27) /* report status */ |
1350 | #define NQTX_CMD_DEXT (1U << 29) /* descriptor extension */ |
1351 | #define NQTX_CMD_VLE (1U << 30) /* VLAN enable */ |
1352 | #define NQTX_CMD_TSE (1U << 31) /* TCP segmentation enable */ |
1353 | |
1354 | /* Descriptor types (if DEXT is set) */ |
1355 | #define NQTX_DTYP_C (2U << 20) /* context */ |
1356 | #define NQTX_DTYP_D (3U << 20) /* data */ |
1357 | |
1358 | #define NQTXD_FIELDS_IDX_SHIFT 4 /* context index shift */ |
1359 | #define NQTXD_FIELDS_IDX_MASK 0xf |
1360 | #define NQTXD_FIELDS_PAYLEN_SHIFT 14 /* payload len shift */ |
1361 | #define NQTXD_FIELDS_PAYLEN_MASK 0x3ffff |
1362 | |
1363 | #define NQTXD_FIELDS_IXSM (1U << 8) /* do IP checksum */ |
1364 | #define NQTXD_FIELDS_TUXSM (1U << 9) /* do TCP/UDP checksum */ |
1365 | |
1366 | #define NQTXC_VLLEN_IPLEN_SHIFT 0 /* IP header len */ |
1367 | #define NQTXC_VLLEN_IPLEN_MASK 0x1ff |
1368 | #define NQTXC_VLLEN_MACLEN_SHIFT 9 /* MAC header len */ |
1369 | #define NQTXC_VLLEN_MACLEN_MASK 0x7f |
1370 | #define NQTXC_VLLEN_VLAN_SHIFT 16 /* vlan number */ |
1371 | #define NQTXC_VLLEN_VLAN_MASK 0xffff |
1372 | |
1373 | #define NQTXC_CMD_MKRLOC_SHIFT 0 /* IP checksum offset */ |
1374 | #define NQTXC_CMD_MKRLOC_MASK 0x1ff |
1375 | #define NQTXC_CMD_SNAP (1U << 9) |
1376 | #define NQTXC_CMD_IP4 (1U << 10) |
1377 | #define NQTXC_CMD_IP6 (0U << 10) |
1378 | #define NQTXC_CMD_TCP (1U << 11) |
1379 | #define NQTXC_CMD_UDP (0U << 11) |
1380 | #define NQTXC_MSSIDX_IDX_SHIFT 4 /* context index shift */ |
1381 | #define NQTXC_MSSIDX_IDX_MASK 0xf |
1382 | #define NQTXC_MSSIDX_L4LEN_SHIFT 8 /* L4 header len shift */ |
1383 | #define NQTXC_MSSIDX_L4LEN_MASK 0xff |
1384 | #define NQTXC_MSSIDX_MSS_SHIFT 16 /* MSS */ |
1385 | #define NQTXC_MSSIDX_MSS_MASK 0xffff |
1386 | |