1 | /* $NetBSD: nouveau_subdev_devinit_nv04.c,v 1.3 2016/04/22 19:52:56 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (C) 2010 Francisco Jerez. |
5 | * All Rights Reserved. |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining |
8 | * a copy of this software and associated documentation files (the |
9 | * "Software"), to deal in the Software without restriction, including |
10 | * without limitation the rights to use, copy, modify, merge, publish, |
11 | * distribute, sublicense, and/or sell copies of the Software, and to |
12 | * permit persons to whom the Software is furnished to do so, subject to |
13 | * the following conditions: |
14 | * |
15 | * The above copyright notice and this permission notice (including the |
16 | * next paragraph) shall be included in all copies or substantial |
17 | * portions of the Software. |
18 | * |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
20 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
22 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
23 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
24 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
25 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
26 | * |
27 | */ |
28 | |
29 | #include <sys/cdefs.h> |
30 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_devinit_nv04.c,v 1.3 2016/04/22 19:52:56 riastradh Exp $" ); |
31 | |
32 | #include <subdev/vga.h> |
33 | |
34 | #include "fbmem.h" |
35 | #include "nv04.h" |
36 | |
37 | static void |
38 | nv04_devinit_meminit(struct nouveau_devinit *devinit) |
39 | { |
40 | struct nv04_devinit_priv *priv = (void *)devinit; |
41 | u32 patt = 0xdeadbeef; |
42 | struct io_mapping *fb; |
43 | int i; |
44 | |
45 | /* Map the framebuffer aperture */ |
46 | fb = fbmem_init(nv_device(priv)); |
47 | if (!fb) { |
48 | nv_error(priv, "failed to map fb\n" ); |
49 | return; |
50 | } |
51 | |
52 | /* Sequencer and refresh off */ |
53 | nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20); |
54 | nv_mask(priv, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); |
55 | |
56 | nv_mask(priv, NV04_PFB_BOOT_0, ~0, |
57 | NV04_PFB_BOOT_0_RAM_AMOUNT_16MB | |
58 | NV04_PFB_BOOT_0_RAM_WIDTH_128 | |
59 | NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT); |
60 | |
61 | for (i = 0; i < 4; i++) |
62 | fbmem_poke(fb, 4 * i, patt); |
63 | |
64 | fbmem_poke(fb, 0x400000, patt + 1); |
65 | |
66 | if (fbmem_peek(fb, 0) == patt + 1) { |
67 | nv_mask(priv, NV04_PFB_BOOT_0, |
68 | NV04_PFB_BOOT_0_RAM_TYPE, |
69 | NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT); |
70 | nv_mask(priv, NV04_PFB_DEBUG_0, |
71 | NV04_PFB_DEBUG_0_REFRESH_OFF, 0); |
72 | |
73 | for (i = 0; i < 4; i++) |
74 | fbmem_poke(fb, 4 * i, patt); |
75 | |
76 | if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff)) |
77 | nv_mask(priv, NV04_PFB_BOOT_0, |
78 | NV04_PFB_BOOT_0_RAM_WIDTH_128 | |
79 | NV04_PFB_BOOT_0_RAM_AMOUNT, |
80 | NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); |
81 | } else |
82 | if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) { |
83 | nv_mask(priv, NV04_PFB_BOOT_0, |
84 | NV04_PFB_BOOT_0_RAM_WIDTH_128 | |
85 | NV04_PFB_BOOT_0_RAM_AMOUNT, |
86 | NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); |
87 | } else |
88 | if (fbmem_peek(fb, 0) != patt) { |
89 | if (fbmem_readback(fb, 0x800000, patt)) |
90 | nv_mask(priv, NV04_PFB_BOOT_0, |
91 | NV04_PFB_BOOT_0_RAM_AMOUNT, |
92 | NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); |
93 | else |
94 | nv_mask(priv, NV04_PFB_BOOT_0, |
95 | NV04_PFB_BOOT_0_RAM_AMOUNT, |
96 | NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); |
97 | |
98 | nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, |
99 | NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT); |
100 | } else |
101 | if (!fbmem_readback(fb, 0x800000, patt)) { |
102 | nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, |
103 | NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); |
104 | |
105 | } |
106 | |
107 | /* Refresh on, sequencer on */ |
108 | nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); |
109 | nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20); |
110 | fbmem_fini(fb); |
111 | } |
112 | |
113 | static int |
114 | powerctrl_1_shift(int chip_version, int reg) |
115 | { |
116 | int shift = -4; |
117 | |
118 | if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20) |
119 | return shift; |
120 | |
121 | switch (reg) { |
122 | case 0x680520: |
123 | shift += 4; |
124 | /*FALLTHROUGH*/ |
125 | case 0x680508: |
126 | shift += 4; |
127 | /*FALLTHROUGH*/ |
128 | case 0x680504: |
129 | shift += 4; |
130 | /*FALLTHROUGH*/ |
131 | case 0x680500: |
132 | shift += 4; |
133 | /*FALLTHROUGH*/ |
134 | } |
135 | |
136 | /* |
137 | * the shift for vpll regs is only used for nv3x chips with a single |
138 | * stage pll |
139 | */ |
140 | if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 || |
141 | chip_version == 0x36 || chip_version >= 0x40)) |
142 | shift = -4; |
143 | |
144 | return shift; |
145 | } |
146 | |
147 | void |
148 | setPLL_single(struct nouveau_devinit *devinit, u32 reg, |
149 | struct nouveau_pll_vals *pv) |
150 | { |
151 | int chip_version = nouveau_bios(devinit)->version.chip; |
152 | uint32_t oldpll = nv_rd32(devinit, reg); |
153 | int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff; |
154 | uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; |
155 | uint32_t saved_powerctrl_1 = 0; |
156 | int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg); |
157 | |
158 | if (oldpll == pll) |
159 | return; /* already set */ |
160 | |
161 | if (shift_powerctrl_1 >= 0) { |
162 | saved_powerctrl_1 = nv_rd32(devinit, 0x001584); |
163 | nv_wr32(devinit, 0x001584, |
164 | (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | |
165 | 1 << shift_powerctrl_1); |
166 | } |
167 | |
168 | if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) |
169 | /* upclock -- write new post divider first */ |
170 | nv_wr32(devinit, reg, pv->log2P << 16 | (oldpll & 0xffff)); |
171 | else |
172 | /* downclock -- write new NM first */ |
173 | nv_wr32(devinit, reg, (oldpll & 0xffff0000) | pv->NM1); |
174 | |
175 | if ((chip_version < 0x17 || chip_version == 0x1a) && |
176 | chip_version != 0x11) |
177 | /* wait a bit on older chips */ |
178 | msleep(64); |
179 | nv_rd32(devinit, reg); |
180 | |
181 | /* then write the other half as well */ |
182 | nv_wr32(devinit, reg, pll); |
183 | |
184 | if (shift_powerctrl_1 >= 0) |
185 | nv_wr32(devinit, 0x001584, saved_powerctrl_1); |
186 | } |
187 | |
188 | static uint32_t |
189 | new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) |
190 | { |
191 | bool head_a = (reg1 == 0x680508); |
192 | |
193 | if (ss) /* single stage pll mode */ |
194 | ramdac580 |= head_a ? 0x00000100 : 0x10000000; |
195 | else |
196 | ramdac580 &= head_a ? 0xfffffeff : 0xefffffff; |
197 | |
198 | return ramdac580; |
199 | } |
200 | |
201 | void |
202 | setPLL_double_highregs(struct nouveau_devinit *devinit, u32 reg1, |
203 | struct nouveau_pll_vals *pv) |
204 | { |
205 | int chip_version = nouveau_bios(devinit)->version.chip; |
206 | bool nv3035 = chip_version == 0x30 || chip_version == 0x35; |
207 | uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); |
208 | uint32_t oldpll1 = nv_rd32(devinit, reg1); |
209 | uint32_t oldpll2 = !nv3035 ? nv_rd32(devinit, reg2) : 0; |
210 | uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; |
211 | uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; |
212 | uint32_t oldramdac580 = 0, ramdac580 = 0; |
213 | bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */ |
214 | uint32_t saved_powerctrl_1 = 0, savedc040 = 0; |
215 | int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1); |
216 | |
217 | /* model specific additions to generic pll1 and pll2 set up above */ |
218 | if (nv3035) { |
219 | pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | |
220 | (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4; |
221 | pll2 = 0; |
222 | } |
223 | if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */ |
224 | oldramdac580 = nv_rd32(devinit, 0x680580); |
225 | ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580); |
226 | if (oldramdac580 != ramdac580) |
227 | oldpll1 = ~0; /* force mismatch */ |
228 | if (single_stage) |
229 | /* magic value used by nvidia in single stage mode */ |
230 | pll2 |= 0x011f; |
231 | } |
232 | if (chip_version > 0x70) |
233 | /* magic bits set by the blob (but not the bios) on g71-73 */ |
234 | pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; |
235 | |
236 | if (oldpll1 == pll1 && oldpll2 == pll2) |
237 | return; /* already set */ |
238 | |
239 | if (shift_powerctrl_1 >= 0) { |
240 | saved_powerctrl_1 = nv_rd32(devinit, 0x001584); |
241 | nv_wr32(devinit, 0x001584, |
242 | (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | |
243 | 1 << shift_powerctrl_1); |
244 | } |
245 | |
246 | if (chip_version >= 0x40) { |
247 | int shift_c040 = 14; |
248 | |
249 | switch (reg1) { |
250 | case 0x680504: |
251 | shift_c040 += 2; |
252 | /*FALLTHROUGH*/ |
253 | case 0x680500: |
254 | shift_c040 += 2; |
255 | /*FALLTHROUGH*/ |
256 | case 0x680520: |
257 | shift_c040 += 2; |
258 | /*FALLTHROUGH*/ |
259 | case 0x680508: |
260 | shift_c040 += 2; |
261 | /*FALLTHROUGH*/ |
262 | } |
263 | |
264 | savedc040 = nv_rd32(devinit, 0xc040); |
265 | if (shift_c040 != 14) |
266 | nv_wr32(devinit, 0xc040, savedc040 & ~(3 << shift_c040)); |
267 | } |
268 | |
269 | if (oldramdac580 != ramdac580) |
270 | nv_wr32(devinit, 0x680580, ramdac580); |
271 | |
272 | if (!nv3035) |
273 | nv_wr32(devinit, reg2, pll2); |
274 | nv_wr32(devinit, reg1, pll1); |
275 | |
276 | if (shift_powerctrl_1 >= 0) |
277 | nv_wr32(devinit, 0x001584, saved_powerctrl_1); |
278 | if (chip_version >= 0x40) |
279 | nv_wr32(devinit, 0xc040, savedc040); |
280 | } |
281 | |
282 | void |
283 | setPLL_double_lowregs(struct nouveau_devinit *devinit, u32 NMNMreg, |
284 | struct nouveau_pll_vals *pv) |
285 | { |
286 | /* When setting PLLs, there is a merry game of disabling and enabling |
287 | * various bits of hardware during the process. This function is a |
288 | * synthesis of six nv4x traces, nearly each card doing a subtly |
289 | * different thing. With luck all the necessary bits for each card are |
290 | * combined herein. Without luck it deviates from each card's formula |
291 | * so as to not work on any :) |
292 | */ |
293 | |
294 | uint32_t Preg = NMNMreg - 4; |
295 | bool mpll = Preg == 0x4020; |
296 | uint32_t oldPval = nv_rd32(devinit, Preg); |
297 | uint32_t NMNM = pv->NM2 << 16 | pv->NM1; |
298 | uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | |
299 | 0xc << 28 | pv->log2P << 16; |
300 | uint32_t saved4600 = 0; |
301 | /* some cards have different maskc040s */ |
302 | uint32_t maskc040 = ~(3 << 14), savedc040; |
303 | bool single_stage = !pv->NM2 || pv->N2 == pv->M2; |
304 | |
305 | if (nv_rd32(devinit, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval) |
306 | return; |
307 | |
308 | if (Preg == 0x4000) |
309 | maskc040 = ~0x333; |
310 | if (Preg == 0x4058) |
311 | maskc040 = ~(0xc << 24); |
312 | |
313 | if (mpll) { |
314 | struct nvbios_pll info; |
315 | uint8_t Pval2; |
316 | |
317 | if (nvbios_pll_parse(nouveau_bios(devinit), Preg, &info)) |
318 | return; |
319 | |
320 | Pval2 = pv->log2P + info.bias_p; |
321 | if (Pval2 > info.max_p) |
322 | Pval2 = info.max_p; |
323 | Pval |= 1 << 28 | Pval2 << 20; |
324 | |
325 | saved4600 = nv_rd32(devinit, 0x4600); |
326 | nv_wr32(devinit, 0x4600, saved4600 | 8 << 28); |
327 | } |
328 | if (single_stage) |
329 | Pval |= mpll ? 1 << 12 : 1 << 8; |
330 | |
331 | nv_wr32(devinit, Preg, oldPval | 1 << 28); |
332 | nv_wr32(devinit, Preg, Pval & ~(4 << 28)); |
333 | if (mpll) { |
334 | Pval |= 8 << 20; |
335 | nv_wr32(devinit, 0x4020, Pval & ~(0xc << 28)); |
336 | nv_wr32(devinit, 0x4038, Pval & ~(0xc << 28)); |
337 | } |
338 | |
339 | savedc040 = nv_rd32(devinit, 0xc040); |
340 | nv_wr32(devinit, 0xc040, savedc040 & maskc040); |
341 | |
342 | nv_wr32(devinit, NMNMreg, NMNM); |
343 | if (NMNMreg == 0x4024) |
344 | nv_wr32(devinit, 0x403c, NMNM); |
345 | |
346 | nv_wr32(devinit, Preg, Pval); |
347 | if (mpll) { |
348 | Pval &= ~(8 << 20); |
349 | nv_wr32(devinit, 0x4020, Pval); |
350 | nv_wr32(devinit, 0x4038, Pval); |
351 | nv_wr32(devinit, 0x4600, saved4600); |
352 | } |
353 | |
354 | nv_wr32(devinit, 0xc040, savedc040); |
355 | |
356 | if (mpll) { |
357 | nv_wr32(devinit, 0x4020, Pval & ~(1 << 28)); |
358 | nv_wr32(devinit, 0x4038, Pval & ~(1 << 28)); |
359 | } |
360 | } |
361 | |
362 | int |
363 | nv04_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) |
364 | { |
365 | struct nouveau_bios *bios = nouveau_bios(devinit); |
366 | struct nouveau_pll_vals pv; |
367 | struct nvbios_pll info; |
368 | int cv = bios->version.chip; |
369 | int N1, M1, N2, M2, P; |
370 | int ret; |
371 | |
372 | ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info); |
373 | if (ret) |
374 | return ret; |
375 | |
376 | ret = nv04_pll_calc(nv_subdev(devinit), &info, freq, |
377 | &N1, &M1, &N2, &M2, &P); |
378 | if (!ret) |
379 | return -EINVAL; |
380 | |
381 | pv.refclk = info.refclk; |
382 | pv.N1 = N1; |
383 | pv.M1 = M1; |
384 | pv.N2 = N2; |
385 | pv.M2 = M2; |
386 | pv.log2P = P; |
387 | |
388 | if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || |
389 | cv >= 0x40) { |
390 | if (type > 0x405c) |
391 | setPLL_double_highregs(devinit, type, &pv); |
392 | else |
393 | setPLL_double_lowregs(devinit, type, &pv); |
394 | } else |
395 | setPLL_single(devinit, type, &pv); |
396 | |
397 | return 0; |
398 | } |
399 | |
400 | int |
401 | nv04_devinit_fini(struct nouveau_object *object, bool suspend) |
402 | { |
403 | struct nv04_devinit_priv *priv = (void *)object; |
404 | int ret; |
405 | |
406 | /* make i2c busses accessible */ |
407 | nv_mask(priv, 0x000200, 0x00000001, 0x00000001); |
408 | |
409 | ret = nouveau_devinit_fini(&priv->base, suspend); |
410 | if (ret) |
411 | return ret; |
412 | |
413 | /* unslave crtcs */ |
414 | #if 0 /* XXX Can't happen: priv->owner is unsigned. */ |
415 | if (priv->owner < 0) |
416 | priv->owner = nv_rdvgaowner(priv); |
417 | #endif |
418 | nv_wrvgaowner(priv, 0); |
419 | |
420 | return 0; |
421 | } |
422 | |
423 | int |
424 | nv04_devinit_init(struct nouveau_object *object) |
425 | { |
426 | struct nv04_devinit_priv *priv = (void *)object; |
427 | |
428 | if (!priv->base.post) { |
429 | u32 htotal = nv_rdvgac(priv, 0, 0x06); |
430 | htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x01) << 8; |
431 | htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x20) << 4; |
432 | htotal |= (nv_rdvgac(priv, 0, 0x25) & 0x01) << 10; |
433 | htotal |= (nv_rdvgac(priv, 0, 0x41) & 0x01) << 11; |
434 | if (!htotal) { |
435 | nv_info(priv, "adaptor not initialised\n" ); |
436 | priv->base.post = true; |
437 | } |
438 | } |
439 | |
440 | return nouveau_devinit_init(&priv->base); |
441 | } |
442 | |
443 | void |
444 | nv04_devinit_dtor(struct nouveau_object *object) |
445 | { |
446 | struct nv04_devinit_priv *priv = (void *)object; |
447 | |
448 | /* restore vga owner saved at first init */ |
449 | nv_wrvgaowner(priv, priv->owner); |
450 | |
451 | nouveau_devinit_destroy(&priv->base); |
452 | } |
453 | |
454 | int |
455 | nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
456 | struct nouveau_oclass *oclass, void *data, u32 size, |
457 | struct nouveau_object **pobject) |
458 | { |
459 | struct nv04_devinit_priv *priv; |
460 | int ret; |
461 | |
462 | ret = nouveau_devinit_create(parent, engine, oclass, &priv); |
463 | *pobject = nv_object(priv); |
464 | if (ret) |
465 | return ret; |
466 | |
467 | priv->owner = -1; |
468 | return 0; |
469 | } |
470 | |
471 | struct nouveau_oclass * |
472 | nv04_devinit_oclass = &(struct nouveau_devinit_impl) { |
473 | .base.handle = NV_SUBDEV(DEVINIT, 0x04), |
474 | .base.ofuncs = &(struct nouveau_ofuncs) { |
475 | .ctor = nv04_devinit_ctor, |
476 | .dtor = nv04_devinit_dtor, |
477 | .init = nv04_devinit_init, |
478 | .fini = nv04_devinit_fini, |
479 | }, |
480 | .meminit = nv04_devinit_meminit, |
481 | .pll_set = nv04_devinit_pll_set, |
482 | }.base; |
483 | |