1/* $NetBSD: arn9280.c,v 1.2 2013/04/03 14:20:02 christos Exp $ */
2/* $OpenBSD: ar9280.c,v 1.18 2012/06/10 21:23:36 kettenis Exp $ */
3
4/*-
5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
6 * Copyright (c) 2008-2009 Atheros Communications Inc.
7 *
8 * Permission to use, copy, modify, and/or distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21/*
22 * Driver for Atheros 802.11a/g/n chipsets.
23 * Routines for AR9220, AR9223, AR9280 and AR9281 chipsets.
24 */
25
26#include <sys/cdefs.h>
27__KERNEL_RCSID(0, "$NetBSD: arn9280.c,v 1.2 2013/04/03 14:20:02 christos Exp $");
28
29#include <sys/param.h>
30#include <sys/sockio.h>
31#include <sys/mbuf.h>
32#include <sys/kernel.h>
33#include <sys/socket.h>
34#include <sys/systm.h>
35#include <sys/malloc.h>
36#include <sys/queue.h>
37#include <sys/callout.h>
38#include <sys/conf.h>
39#include <sys/device.h>
40
41#include <sys/bus.h>
42#include <sys/endian.h>
43#include <sys/intr.h>
44
45#include <net/bpf.h>
46#include <net/if.h>
47#include <net/if_arp.h>
48#include <net/if_dl.h>
49#include <net/if_ether.h>
50#include <net/if_media.h>
51#include <net/if_types.h>
52
53#include <netinet/in.h>
54#include <netinet/in_systm.h>
55#include <netinet/in_var.h>
56#include <netinet/ip.h>
57
58#include <net80211/ieee80211_var.h>
59#include <net80211/ieee80211_amrr.h>
60#include <net80211/ieee80211_radiotap.h>
61
62#include <dev/ic/athnreg.h>
63#include <dev/ic/athnvar.h>
64
65#include <dev/ic/arn5008reg.h>
66#include <dev/ic/arn5008.h>
67#include <dev/ic/arn5416reg.h> /* We share the ROM layout. */
68#include <dev/ic/arn5416.h> /* We share the ROM layout. */
69#include <dev/ic/arn9280reg.h>
70#include <dev/ic/arn9280.h>
71
72#define Static static
73
74Static void ar9280_init_from_rom(struct athn_softc *,
75 struct ieee80211_channel *, struct ieee80211_channel *);
76Static void ar9280_olpc_init(struct athn_softc *);
77Static void ar9280_olpc_temp_compensation(struct athn_softc *);
78Static void ar9280_setup(struct athn_softc *);
79
80PUBLIC int
81ar9280_attach(struct athn_softc *sc)
82{
83
84 sc->sc_eep_base = AR5416_EEP_START_LOC;
85 sc->sc_eep_size = sizeof(struct ar5416_eeprom);
86 sc->sc_def_nf = AR9280_PHY_CCA_MAX_GOOD_VALUE;
87 sc->sc_ngpiopins = (sc->sc_flags & ATHN_FLAG_USB) ? 16 : 10;
88 sc->sc_led_pin = 1;
89 sc->sc_workaround = AR9280_WA_DEFAULT;
90 sc->sc_ops.setup = ar9280_setup;
91 sc->sc_ops.swap_rom = ar5416_swap_rom;
92 sc->sc_ops.init_from_rom = ar9280_init_from_rom;
93 sc->sc_ops.set_txpower = ar5416_set_txpower;
94 sc->sc_ops.set_synth = ar9280_set_synth;
95 sc->sc_ops.spur_mitigate = ar9280_spur_mitigate;
96 sc->sc_ops.get_spur_chans = ar5416_get_spur_chans;
97 sc->sc_ops.olpc_init = ar9280_olpc_init;
98 sc->sc_ops.olpc_temp_compensation = ar9280_olpc_temp_compensation;
99 sc->sc_ini = &ar9280_2_0_ini;
100 sc->sc_serdes = &ar9280_2_0_serdes;
101
102 return ar5008_attach(sc);
103}
104
105Static void
106ar9280_setup(struct athn_softc *sc)
107{
108 const struct ar5416_eeprom *eep = sc->sc_eep;
109 uint8_t type;
110
111 /* Determine if open loop power control should be used. */
112 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19 &&
113 eep->baseEepHeader.openLoopPwrCntl)
114 sc->sc_flags |= ATHN_FLAG_OLPC;
115
116 /* Determine if fast PLL clock is supported. */
117 if (AR_SREV_9280_20(sc) &&
118 (sc->sc_eep_rev <= AR_EEP_MINOR_VER_16 ||
119 eep->baseEepHeader.fastClk5g))
120 sc->sc_flags |= ATHN_FLAG_FAST_PLL_CLOCK;
121
122 /*
123 * Determine if initialization value for AR_AN_TOP2 must be fixed.
124 * This is required for some AR9220 devices such as Ubiquiti SR71-12.
125 */
126 if (AR_SREV_9280_20(sc) &&
127 sc->sc_eep_rev > AR_EEP_MINOR_VER_10 &&
128 !eep->baseEepHeader.pwdclkind) {
129 DPRINTFN(DBG_INIT, sc, "AR_AN_TOP2 fixup required\n");
130 sc->sc_flags |= ATHN_FLAG_AN_TOP2_FIXUP;
131 }
132
133 if (AR_SREV_9280_20(sc)) {
134 /* Check if we have a valid rxGainType field in ROM. */
135 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_17) {
136 /* Select initialization values based on ROM. */
137 type = eep->baseEepHeader.rxGainType;
138 DPRINTFN(DBG_INIT, sc, "Rx gain type=0x%x\n", type);
139 if (type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
140 sc->sc_rx_gain = &ar9280_2_0_rx_gain_23db_backoff;
141 else if (type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
142 sc->sc_rx_gain = &ar9280_2_0_rx_gain_13db_backoff;
143 else
144 sc->sc_rx_gain = &ar9280_2_0_rx_gain;
145 }
146 else
147 sc->sc_rx_gain = &ar9280_2_0_rx_gain;
148
149 /* Check if we have a valid txGainType field in ROM. */
150 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19) {
151 /* Select initialization values based on ROM. */
152 type = eep->baseEepHeader.txGainType;
153 DPRINTFN(DBG_INIT, sc, "Tx gain type=0x%x\n", type);
154 if (type == AR_EEP_TXGAIN_HIGH_POWER)
155 sc->sc_tx_gain = &ar9280_2_0_tx_gain_high_power;
156 else
157 sc->sc_tx_gain = &ar9280_2_0_tx_gain;
158 }
159 else
160 sc->sc_tx_gain = &ar9280_2_0_tx_gain;
161 }
162}
163
164PUBLIC int
165ar9280_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
166 struct ieee80211_channel *extc)
167{
168 uint32_t phy, reg, ndiv = 0;
169 uint32_t freq = c->ic_freq;
170
171 phy = AR_READ(sc, AR9280_PHY_SYNTH_CONTROL) & ~0x3fffffff;
172
173 if (IEEE80211_IS_CHAN_2GHZ(c)) {
174 phy |= (freq << 16) / 15;
175 phy |= AR9280_BMODE | AR9280_FRACMODE;
176
177 if (AR_SREV_9287_11_OR_LATER(sc)) {
178 /* NB: Magic values from the Linux driver. */
179 if (freq == 2484) { /* Channel 14. */
180 /* Japanese regulatory requirements. */
181 AR_WRITE(sc, AR_PHY(637), 0x00000000);
182 AR_WRITE(sc, AR_PHY(638), 0xefff0301);
183 AR_WRITE(sc, AR_PHY(639), 0xca9228ee);
184 }
185 else {
186 AR_WRITE(sc, AR_PHY(637), 0x00fffeff);
187 AR_WRITE(sc, AR_PHY(638), 0x00f5f9ff);
188 AR_WRITE(sc, AR_PHY(639), 0xb79f6427);
189 }
190 }
191 else {
192 reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
193 if (freq == 2484) /* Channel 14. */
194 reg |= AR_PHY_CCK_TX_CTRL_JAPAN;
195 else
196 reg &= ~AR_PHY_CCK_TX_CTRL_JAPAN;
197 AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
198 }
199 }
200 else {
201 if (AR_SREV_9285_10_OR_LATER(sc) ||
202 sc->sc_eep_rev < AR_EEP_MINOR_VER_22 ||
203 !((struct ar5416_base_eep_header *)sc->sc_eep)->frac_n_5g) {
204 if ((freq % 20) == 0) {
205 ndiv = (freq * 3) / 60;
206 phy |= SM(AR9280_AMODE_REFSEL, 3);
207 }
208 else if ((freq % 10) == 0) {
209 ndiv = (freq * 6) / 60;
210 phy |= SM(AR9280_AMODE_REFSEL, 2);
211 }
212 }
213 if (ndiv != 0) {
214 phy |= (ndiv & 0x1ff) << 17;
215 phy |= (ndiv & ~0x1ff) * 2;
216 }
217 else {
218 phy |= (freq << 15) / 15;
219 phy |= AR9280_FRACMODE;
220
221 reg = AR_READ(sc, AR_AN_SYNTH9);
222 reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1);
223 AR_WRITE(sc, AR_AN_SYNTH9, reg);
224 }
225 }
226 AR_WRITE_BARRIER(sc);
227 DPRINTFN(DBG_RF, sc, "AR9280_PHY_SYNTH_CONTROL=0x%08x\n", phy);
228 AR_WRITE(sc, AR9280_PHY_SYNTH_CONTROL, phy);
229 AR_WRITE_BARRIER(sc);
230 return 0;
231}
232
233Static void
234ar9280_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
235 struct ieee80211_channel *extc)
236{
237 static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 };
238 const struct ar5416_eeprom *eep = sc->sc_eep;
239 const struct ar5416_modal_eep_header *modal;
240 uint32_t reg, offset;
241 uint8_t txRxAtten;
242 int i;
243
244 modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)];
245
246 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
247
248 for (i = 0; i < AR9280_MAX_CHAINS; i++) {
249 if (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5)
250 offset = chainoffset[i];
251 else
252 offset = i * 0x1000;
253
254 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
255 modal->antCtrlChain[i]);
256
257 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
258 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
259 modal->iqCalICh[i]);
260 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
261 modal->iqCalQCh[i]);
262 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
263
264 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3) {
265 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
266 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
267 modal->bswMargin[i]);
268 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
269 modal->bswAtten[i]);
270 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
271 modal->xatten2Margin[i]);
272 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
273 modal->xatten2Db[i]);
274 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
275 }
276 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3)
277 txRxAtten = modal->txRxAttenCh[i];
278 else /* Workaround for ROM versions < 14.3. */
279 txRxAtten = IEEE80211_IS_CHAN_2GHZ(c) ? 23 : 44;
280 reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
281 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
282 txRxAtten);
283 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
284 modal->rxTxMarginCh[i]);
285 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
286 }
287 if (IEEE80211_IS_CHAN_2GHZ(c)) {
288 reg = AR_READ(sc, AR_AN_RF2G1_CH0);
289 reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob);
290 reg = RW(reg, AR_AN_RF2G1_CH0_DB, modal->db);
291 AR_WRITE(sc, AR_AN_RF2G1_CH0, reg);
292 AR_WRITE_BARRIER(sc);
293 DELAY(100);
294
295 reg = AR_READ(sc, AR_AN_RF2G1_CH1);
296 reg = RW(reg, AR_AN_RF2G1_CH1_OB, modal->ob_ch1);
297 reg = RW(reg, AR_AN_RF2G1_CH1_DB, modal->db_ch1);
298 AR_WRITE(sc, AR_AN_RF2G1_CH1, reg);
299 AR_WRITE_BARRIER(sc);
300 DELAY(100);
301 }
302 else {
303 reg = AR_READ(sc, AR_AN_RF5G1_CH0);
304 reg = RW(reg, AR_AN_RF5G1_CH0_OB5, modal->ob);
305 reg = RW(reg, AR_AN_RF5G1_CH0_DB5, modal->db);
306 AR_WRITE(sc, AR_AN_RF5G1_CH0, reg);
307 AR_WRITE_BARRIER(sc);
308 DELAY(100);
309
310 reg = AR_READ(sc, AR_AN_RF5G1_CH1);
311 reg = RW(reg, AR_AN_RF5G1_CH1_OB5, modal->ob_ch1);
312 reg = RW(reg, AR_AN_RF5G1_CH1_DB5, modal->db_ch1);
313 AR_WRITE(sc, AR_AN_RF5G1_CH1, reg);
314 AR_WRITE_BARRIER(sc);
315 DELAY(100);
316 }
317 reg = AR_READ(sc, AR_AN_TOP2);
318 if ((sc->sc_flags & ATHN_FLAG_USB) && IEEE80211_IS_CHAN_5GHZ(c)) {
319 /*
320 * Hardcode the output voltage of x-PA bias LDO to the
321 * lowest value for UB94 such that the card doesn't get
322 * too hot.
323 */
324 reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, 0);
325 }
326 else
327 reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
328 if (modal->flagBits & AR5416_EEP_FLAG_LOCALBIAS)
329 reg |= AR_AN_TOP2_LOCALBIAS;
330 else
331 reg &= ~AR_AN_TOP2_LOCALBIAS;
332 AR_WRITE(sc, AR_AN_TOP2, reg);
333 AR_WRITE_BARRIER(sc);
334 DELAY(100);
335
336 reg = AR_READ(sc, AR_PHY_XPA_CFG);
337 if (modal->flagBits & AR5416_EEP_FLAG_FORCEXPAON)
338 reg |= AR_PHY_FORCE_XPA_CFG;
339 else
340 reg &= ~AR_PHY_FORCE_XPA_CFG;
341 AR_WRITE(sc, AR_PHY_XPA_CFG, reg);
342
343 reg = AR_READ(sc, AR_PHY_SETTLING);
344 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
345 AR_WRITE(sc, AR_PHY_SETTLING, reg);
346
347 reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
348 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
349 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
350
351 reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
352 reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
353 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
354 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
355 AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
356
357 reg = AR_READ(sc, AR_PHY_RF_CTL3);
358 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
359 AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
360
361 reg = AR_READ(sc, AR_PHY_CCA(0));
362 reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
363 AR_WRITE(sc, AR_PHY_CCA(0), reg);
364
365 reg = AR_READ(sc, AR_PHY_EXT_CCA0);
366 reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
367 AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
368
369 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) {
370 reg = AR_READ(sc, AR_PHY_RF_CTL2);
371 reg = RW(reg, AR_PHY_TX_END_DATA_START,
372 modal->txFrameToDataStart);
373 reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
374 AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
375 }
376#ifndef IEEE80211_NO_HT
377 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) {
378 /* Overwrite switch settling with HT-40 value. */
379 reg = AR_READ(sc, AR_PHY_SETTLING);
380 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
381 AR_WRITE(sc, AR_PHY_SETTLING, reg);
382 }
383#endif
384 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19) {
385 reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
386 reg = RW(reg, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
387 MS(modal->miscBits, AR5416_EEP_MISC_TX_DAC_SCALE_CCK));
388 AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
389 }
390 if (AR_SREV_9280_20(sc) &&
391 sc->sc_eep_rev >= AR_EEP_MINOR_VER_20) {
392 reg = AR_READ(sc, AR_AN_TOP1);
393 if (eep->baseEepHeader.dacLpMode &&
394 (IEEE80211_IS_CHAN_2GHZ(c) ||
395 !eep->baseEepHeader.dacHiPwrMode_5G))
396 reg |= AR_AN_TOP1_DACLPMODE;
397 else
398 reg &= ~AR_AN_TOP1_DACLPMODE;
399 AR_WRITE(sc, AR_AN_TOP1, reg);
400 AR_WRITE_BARRIER(sc);
401 DELAY(100);
402
403 reg = AR_READ(sc, AR_PHY_FRAME_CTL);
404 reg = RW(reg, AR_PHY_FRAME_CTL_TX_CLIP,
405 MS(modal->miscBits, AR5416_EEP_MISC_TX_CLIP));
406 AR_WRITE(sc, AR_PHY_FRAME_CTL, reg);
407
408 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL9);
409 reg = RW(reg, AR_PHY_TX_DESIRED_SCALE_CCK,
410 eep->baseEepHeader.desiredScaleCCK);
411 AR_WRITE(sc, AR_PHY_TX_PWRCTRL9, reg);
412 }
413 AR_WRITE_BARRIER(sc);
414}
415
416PUBLIC void
417ar9280_olpc_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
418 int chain, uint8_t *boundaries, uint8_t *pdadcs, uint8_t *txgain)
419{
420 const struct ar5416_eeprom *eep = sc->sc_eep;
421 const struct ar_cal_data_per_freq_olpc *pierdata;
422 const uint8_t *pierfreq;
423 uint8_t fbin, pcdac, pwr, idx;
424 int i, lo, hi, npiers;
425
426 if (IEEE80211_IS_CHAN_2GHZ(c)) {
427 pierfreq = eep->calFreqPier2G;
428 pierdata = (const struct ar_cal_data_per_freq_olpc *)
429 eep->calPierData2G[chain];
430 npiers = AR5416_NUM_2G_CAL_PIERS;
431 }
432 else {
433 pierfreq = eep->calFreqPier5G;
434 pierdata = (const struct ar_cal_data_per_freq_olpc *)
435 eep->calPierData5G[chain];
436 npiers = AR5416_NUM_5G_CAL_PIERS;
437 }
438 /* Find channel in ROM pier table. */
439 fbin = athn_chan2fbin(c);
440 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
441
442 /* Get average. */
443 pwr = (pierdata[lo].pwrPdg[0][0] + pierdata[hi].pwrPdg[0][0]) / 2;
444 pwr /= 2; /* Convert to dB. */
445
446 /* Find power control digital-to-analog converter (PCDAC) value. */
447 pcdac = pierdata[hi].pcdac[0][0];
448 for (idx = 0; idx < AR9280_TX_GAIN_TABLE_SIZE - 1; idx++)
449 if (pcdac <= sc->sc_tx_gain_tbl[idx])
450 break;
451 *txgain = idx;
452
453 DPRINTFN(DBG_RF, sc,
454 "fbin=%d lo=%d hi=%d pwr=%d pcdac=%d txgain=%d\n",
455 fbin, lo, hi, pwr, pcdac, idx);
456
457 /* Fill phase domain analog-to-digital converter (PDADC) table. */
458 for (i = 0; i < AR_NUM_PDADC_VALUES; i++)
459 pdadcs[i] = (i < pwr) ? 0x00 : 0xff;
460
461 for (i = 0; i < AR_PD_GAINS_IN_MASK; i++)
462 boundaries[i] = AR9280_PD_GAIN_BOUNDARY_DEFAULT;
463}
464
465PUBLIC void
466ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
467 struct ieee80211_channel *extc)
468{
469 const struct ar_spur_chan *spurchans;
470 int spur, bin, spur_delta_phase, spur_freq_sd, spur_subchannel_sd;
471 int spur_off, range, i;
472
473 /* NB: Always clear. */
474 AR_CLRBITS(sc, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
475
476 range = (extc != NULL) ? 19 : 10;
477
478 spurchans = sc->sc_ops.get_spur_chans(sc, IEEE80211_IS_CHAN_2GHZ(c));
479 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
480 spur = spurchans[i].spurChan;
481 if (spur == AR_NO_SPUR)
482 return; /* XXX disable if it was enabled! */
483 spur /= 10;
484 if (IEEE80211_IS_CHAN_2GHZ(c))
485 spur += AR_BASE_FREQ_2GHZ;
486 else
487 spur += AR_BASE_FREQ_5GHZ;
488 spur -= c->ic_freq;
489 if (abs(spur) < range)
490 break;
491 }
492 if (i == AR_EEPROM_MODAL_SPURS)
493 return; /* XXX disable if it was enabled! */
494 DPRINTFN(DBG_RF, sc, "enabling spur mitigation\n");
495
496 AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
497 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
498 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
499 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
500 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
501
502 AR_WRITE(sc, AR_PHY_SPUR_REG,
503 AR_PHY_SPUR_REG_MASK_RATE_CNTL |
504 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
505 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
506 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
507 SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH));
508
509#ifndef IEEE80211_NO_HT
510 if (extc != NULL) {
511 spur_delta_phase = (spur * 262144) / 10;
512 if (spur < 0) {
513 spur_subchannel_sd = 1;
514 spur_off = spur + 10;
515 }
516 else {
517 spur_subchannel_sd = 0;
518 spur_off = spur - 10;
519 }
520 }
521 else
522#endif
523 {
524 spur_delta_phase = (spur * 524288) / 10;
525 spur_subchannel_sd = 0;
526 spur_off = spur;
527 }
528 if (IEEE80211_IS_CHAN_2GHZ(c))
529 spur_freq_sd = (spur_off * 2048) / 44;
530 else
531 spur_freq_sd = (spur_off * 2048) / 40;
532
533 AR_WRITE(sc, AR_PHY_TIMING11,
534 AR_PHY_TIMING11_USE_SPUR_IN_AGC |
535 SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) |
536 SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase));
537
538 AR_WRITE(sc, AR_PHY_SFCORR_EXT,
539 SM(AR_PHY_SFCORR_SPUR_SUBCHNL_SD, spur_subchannel_sd));
540 AR_WRITE_BARRIER(sc);
541
542 bin = spur * 320;
543 ar5008_set_viterbi_mask(sc, bin);
544}
545
546PUBLIC void
547ar9280_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
548{
549 const struct athn_gain *prog = sc->sc_rx_gain;
550 const uint32_t *pvals;
551 int i;
552
553 if (IEEE80211_IS_CHAN_2GHZ(c))
554 pvals = prog->vals_2g;
555 else
556 pvals = prog->vals_5g;
557 for (i = 0; i < prog->nregs; i++)
558 AR_WRITE(sc, prog->regs[i], pvals[i]);
559}
560
561PUBLIC void
562ar9280_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
563{
564 const struct athn_gain *prog = sc->sc_tx_gain;
565 const uint32_t *pvals;
566 int i;
567
568 if (IEEE80211_IS_CHAN_2GHZ(c))
569 pvals = prog->vals_2g;
570 else
571 pvals = prog->vals_5g;
572 for (i = 0; i < prog->nregs; i++)
573 AR_WRITE(sc, prog->regs[i], pvals[i]);
574}
575
576Static void
577ar9280_olpc_init(struct athn_softc *sc)
578{
579 uint32_t reg;
580 int i;
581
582 /* Save original Tx gain values. */
583 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
584 reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
585 sc->sc_tx_gain_tbl[i] = MS(reg, AR_PHY_TX_GAIN);
586 }
587 /* Initial Tx gain temperature compensation. */
588 sc->sc_tcomp = 0;
589}
590
591Static void
592ar9280_olpc_temp_compensation(struct athn_softc *sc)
593{
594 const struct ar5416_eeprom *eep = sc->sc_eep;
595 int8_t pdadc, txgain, tcomp;
596 uint32_t reg;
597 int i;
598
599 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
600 pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
601 DPRINTFN(DBG_RF, sc, "PD Avg Out=%d\n", pdadc);
602
603 if (sc->sc_pdadc == 0 || pdadc == 0)
604 return; /* No frames transmitted yet. */
605
606 /* Compute Tx gain temperature compensation. */
607 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_20 &&
608 eep->baseEepHeader.dacHiPwrMode_5G)
609 tcomp = (pdadc - sc->sc_pdadc + 4) / 8;
610 else
611 tcomp = (pdadc - sc->sc_pdadc + 5) / 10;
612 DPRINTFN(DBG_RF, sc, "OLPC temp compensation=%d\n", tcomp);
613
614 if (tcomp == sc->sc_tcomp)
615 return; /* Don't rewrite the same values. */
616 sc->sc_tcomp = tcomp;
617
618 /* Adjust Tx gain values. */
619 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
620 txgain = sc->sc_tx_gain_tbl[i] - tcomp;
621 if (txgain < 0)
622 txgain = 0;
623 reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
624 reg = RW(reg, AR_PHY_TX_GAIN, txgain);
625 AR_WRITE(sc, AR_PHY_TX_GAIN_TBL(i), reg);
626 }
627 AR_WRITE_BARRIER(sc);
628}
629