1/* $NetBSD: fwohci_pci.c,v 1.43 2016/07/07 06:55:41 msaitoh Exp $ */
2
3/*-
4 * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas of 3am Software Foundry.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: fwohci_pci.c,v 1.43 2016/07/07 06:55:41 msaitoh Exp $");
34
35#include <sys/param.h>
36#include <sys/bus.h>
37#include <sys/device.h>
38#include <sys/intr.h>
39#include <sys/select.h>
40#include <sys/socket.h>
41#include <sys/systm.h>
42
43#include <dev/pci/pcidevs.h>
44#include <dev/pci/pcireg.h>
45#include <dev/pci/pcivar.h>
46#include <dev/ieee1394/firewire.h>
47#include <dev/ieee1394/firewirereg.h>
48#include <dev/ieee1394/fwdma.h>
49#include <dev/ieee1394/fwohcireg.h>
50#include <dev/ieee1394/fwohcivar.h>
51
52struct fwohci_pci_softc {
53 struct fwohci_softc psc_sc;
54
55 pci_chipset_tag_t psc_pc;
56 pcitag_t psc_tag;
57
58 void *psc_ih;
59};
60
61static int fwohci_pci_match(device_t, cfdata_t, void *);
62static void fwohci_pci_attach(device_t, device_t, void *);
63static int fwohci_pci_detach(device_t, int);
64
65static bool fwohci_pci_suspend(device_t, const pmf_qual_t *);
66static bool fwohci_pci_resume(device_t, const pmf_qual_t *);
67
68CFATTACH_DECL_NEW(fwohci_pci, sizeof(struct fwohci_pci_softc),
69 fwohci_pci_match, fwohci_pci_attach, fwohci_pci_detach, NULL);
70
71static int
72fwohci_pci_match(device_t parent, cfdata_t match, void *aux)
73{
74 struct pci_attach_args *pa = (struct pci_attach_args *) aux;
75
76 /*
77 * XXX
78 * Firewire controllers used in some G3 PowerBooks hang the system
79 * when trying to discover devices - don't attach to those for now
80 * until someone with the right hardware can investigate
81 */
82 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE) &&
83 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_PBG3_FW))
84 return 0;
85 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
86 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_FIREWIRE &&
87 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_OHCI)
88 return 1;
89
90 return 0;
91}
92
93static void
94fwohci_pci_attach(device_t parent, device_t self, void *aux)
95{
96 struct pci_attach_args *pa = (struct pci_attach_args *) aux;
97 struct fwohci_pci_softc *psc = device_private(self);
98 char const *intrstr;
99 pci_intr_handle_t ih;
100 uint32_t csr;
101 char intrbuf[PCI_INTRSTR_LEN];
102
103 pci_aprint_devinfo(pa, "IEEE 1394 Controller");
104
105 fwohci_init(&psc->psc_sc);
106
107 psc->psc_sc.fc.dev = self;
108 psc->psc_sc.fc.dmat = pa->pa_dmat;
109 psc->psc_pc = pa->pa_pc;
110 psc->psc_tag = pa->pa_tag;
111
112 /* Map I/O registers */
113 if (pci_mapreg_map(pa, PCI_OHCI_MAP_REGISTER, PCI_MAPREG_TYPE_MEM, 0,
114 &psc->psc_sc.bst, &psc->psc_sc.bsh, NULL, &psc->psc_sc.bssize)) {
115 aprint_error_dev(self, "can't map OHCI register space\n");
116 goto fail;
117 }
118
119 /* Disable interrupts, so we don't get any spurious ones. */
120 OWRITE(&psc->psc_sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
121
122 /* Enable the device. */
123 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
124 csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
125 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr);
126
127 /*
128 * Some Sun FireWire controllers have their intpin register
129 * bogusly set to 0, although it should be 3. Correct that.
130 */
131 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN) &&
132 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_FIREWIRE))
133 if (pa->pa_intrpin == 0)
134 pa->pa_intrpin = 3;
135
136 /* Map and establish the interrupt. */
137 if (pci_intr_map(pa, &ih)) {
138 aprint_error_dev(self, "couldn't map interrupt\n");
139 goto fail;
140 }
141 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf));
142 psc->psc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, fwohci_intr,
143 &psc->psc_sc);
144 if (psc->psc_ih == NULL) {
145 aprint_error_dev(self, "couldn't establish interrupt");
146 if (intrstr != NULL)
147 aprint_error(" at %s", intrstr);
148 aprint_error("\n");
149 goto fail;
150 }
151 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
152
153 if (fwohci_attach(&psc->psc_sc) != 0)
154 goto fail;
155
156 if (!pmf_device_register(self, fwohci_pci_suspend, fwohci_pci_resume))
157 aprint_error_dev(self, "couldn't establish power handler\n");
158
159 return;
160
161fail:
162 /* In the event that we fail to attach, register a null pnp handler */
163 if (!pmf_device_register(self, NULL, NULL))
164 aprint_error_dev(self, "couldn't establish power handler\n");
165
166 return;
167}
168
169static int
170fwohci_pci_detach(device_t self, int flags)
171{
172 struct fwohci_pci_softc *psc = device_private(self);
173 int rv;
174
175 pmf_device_deregister(self);
176 rv = fwohci_detach(&psc->psc_sc, flags);
177 if (rv)
178 return rv;
179
180 if (psc->psc_ih != NULL) {
181 pci_intr_disestablish(psc->psc_pc, psc->psc_ih);
182 psc->psc_ih = NULL;
183 }
184 if (psc->psc_sc.bssize) {
185 bus_space_unmap(psc->psc_sc.bst, psc->psc_sc.bsh,
186 psc->psc_sc.bssize);
187 psc->psc_sc.bssize = 0;
188 }
189 return 0;
190}
191
192static bool
193fwohci_pci_suspend(device_t dv, const pmf_qual_t *qual)
194{
195 struct fwohci_pci_softc *psc = device_private(dv);
196 int s;
197
198 s = splbio();
199 fwohci_stop(&psc->psc_sc);
200 splx(s);
201
202 return true;
203}
204
205static bool
206fwohci_pci_resume(device_t dv, const pmf_qual_t *qual)
207{
208 struct fwohci_pci_softc *psc = device_private(dv);
209 int s;
210
211 s = splbio();
212 fwohci_resume(&psc->psc_sc);
213 splx(s);
214
215 return true;
216}
217