1 | /* $NetBSD: rtwphy.c,v 1.16 2013/11/15 14:52:11 nisimura Exp $ */ |
2 | /*- |
3 | * Copyright (c) 2004, 2005 David Young. All rights reserved. |
4 | * |
5 | * Programmed for NetBSD by David Young. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * |
16 | * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY |
17 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
18 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A |
19 | * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David |
20 | * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
21 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED |
22 | * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
24 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
27 | * OF SUCH DAMAGE. |
28 | */ |
29 | /* |
30 | * Control the Philips SA2400 RF front-end and the baseband processor |
31 | * built into the Realtek RTL8180. |
32 | */ |
33 | |
34 | #include <sys/cdefs.h> |
35 | __KERNEL_RCSID(0, "$NetBSD: rtwphy.c,v 1.16 2013/11/15 14:52:11 nisimura Exp $" ); |
36 | |
37 | #include <sys/param.h> |
38 | #include <sys/systm.h> |
39 | #include <sys/types.h> |
40 | #include <sys/device.h> |
41 | |
42 | #include <sys/bus.h> |
43 | |
44 | #include <net/if.h> |
45 | #include <net/if_media.h> |
46 | #include <net/if_ether.h> |
47 | |
48 | #include <net80211/ieee80211_netbsd.h> |
49 | #include <net80211/ieee80211_radiotap.h> |
50 | #include <net80211/ieee80211_var.h> |
51 | |
52 | #include <dev/ic/rtwreg.h> |
53 | #include <dev/ic/max2820reg.h> |
54 | #include <dev/ic/sa2400reg.h> |
55 | #include <dev/ic/rtwvar.h> |
56 | #include <dev/ic/rtwphyio.h> |
57 | #include <dev/ic/rtwphy.h> |
58 | |
59 | static int rtw_max2820_pwrstate(struct rtw_rf *, enum rtw_pwrstate); |
60 | static int rtw_sa2400_pwrstate(struct rtw_rf *, enum rtw_pwrstate); |
61 | |
62 | #define GCT_WRITE(__gr, __addr, __val, __label) \ |
63 | do { \ |
64 | if (rtw_rfbus_write(&(__gr)->gr_bus, RTW_RFCHIPID_GCT, \ |
65 | (__addr), (__val)) == -1) \ |
66 | goto __label; \ |
67 | } while(0) |
68 | |
69 | static int |
70 | rtw_bbp_preinit(struct rtw_regs *regs, u_int antatten0, int dflantb, |
71 | u_int freq) |
72 | { |
73 | u_int antatten = antatten0; |
74 | if (dflantb) |
75 | antatten |= RTW_BBP_ANTATTEN_DFLANTB; |
76 | if (freq == 2484) /* channel 14 */ |
77 | antatten |= RTW_BBP_ANTATTEN_CHAN14; |
78 | return rtw_bbp_write(regs, RTW_BBP_ANTATTEN, antatten); |
79 | } |
80 | |
81 | static int |
82 | rtw_bbp_init(struct rtw_regs *regs, struct rtw_bbpset *bb, int antdiv, |
83 | int dflantb, uint8_t cs_threshold, u_int freq) |
84 | { |
85 | int rc; |
86 | uint32_t sys2, sys3; |
87 | |
88 | sys2 = bb->bb_sys2; |
89 | if (antdiv) |
90 | sys2 |= RTW_BBP_SYS2_ANTDIV; |
91 | sys3 = bb->bb_sys3 | |
92 | __SHIFTIN(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK); |
93 | |
94 | #define RTW_BBP_WRITE_OR_RETURN(reg, val) \ |
95 | if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \ |
96 | return rc; |
97 | |
98 | RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS1, bb->bb_sys1); |
99 | RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TXAGC, bb->bb_txagc); |
100 | RTW_BBP_WRITE_OR_RETURN(RTW_BBP_LNADET, bb->bb_lnadet); |
101 | RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCINI, bb->bb_ifagcini); |
102 | RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCLIMIT, bb->bb_ifagclimit); |
103 | RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCDET, bb->bb_ifagcdet); |
104 | |
105 | if ((rc = rtw_bbp_preinit(regs, bb->bb_antatten, dflantb, freq)) != 0) |
106 | return rc; |
107 | |
108 | RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TRL, bb->bb_trl); |
109 | RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS2, sys2); |
110 | RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS3, sys3); |
111 | RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHESTLIM, bb->bb_chestlim); |
112 | RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHSQLIM, bb->bb_chsqlim); |
113 | return 0; |
114 | } |
115 | |
116 | static int |
117 | rtw_sa2400_txpower(struct rtw_rf *rf, uint8_t opaque_txpower) |
118 | { |
119 | struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; |
120 | struct rtw_rfbus *bus = &sa->sa_bus; |
121 | |
122 | return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_TX, |
123 | opaque_txpower); |
124 | } |
125 | |
126 | /* make sure we're using the same settings as the reference driver */ |
127 | static void |
128 | verify_syna(u_int freq, uint32_t val) |
129 | { |
130 | #ifdef DIAGNOSTIC |
131 | uint32_t expected_val = ~val; |
132 | |
133 | switch (freq) { |
134 | case 2412: |
135 | expected_val = 0x0000096c; /* ch 1 */ |
136 | break; |
137 | case 2417: |
138 | expected_val = 0x00080970; /* ch 2 */ |
139 | break; |
140 | case 2422: |
141 | expected_val = 0x00100974; /* ch 3 */ |
142 | break; |
143 | case 2427: |
144 | expected_val = 0x00180978; /* ch 4 */ |
145 | break; |
146 | case 2432: |
147 | expected_val = 0x00000980; /* ch 5 */ |
148 | break; |
149 | case 2437: |
150 | expected_val = 0x00080984; /* ch 6 */ |
151 | break; |
152 | case 2442: |
153 | expected_val = 0x00100988; /* ch 7 */ |
154 | break; |
155 | case 2447: |
156 | expected_val = 0x0018098c; /* ch 8 */ |
157 | break; |
158 | case 2452: |
159 | expected_val = 0x00000994; /* ch 9 */ |
160 | break; |
161 | case 2457: |
162 | expected_val = 0x00080998; /* ch 10 */ |
163 | break; |
164 | case 2462: |
165 | expected_val = 0x0010099c; /* ch 11 */ |
166 | break; |
167 | case 2467: |
168 | expected_val = 0x001809a0; /* ch 12 */ |
169 | break; |
170 | case 2472: |
171 | expected_val = 0x000009a8; /* ch 13 */ |
172 | break; |
173 | case 2484: |
174 | expected_val = 0x000009b4; /* ch 14 */ |
175 | break; |
176 | } |
177 | KASSERT(val == expected_val); |
178 | #endif |
179 | } |
180 | |
181 | /* freq is in MHz */ |
182 | static int |
183 | rtw_sa2400_tune(struct rtw_rf *rf, u_int freq) |
184 | { |
185 | struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; |
186 | struct rtw_rfbus *bus = &sa->sa_bus; |
187 | int rc; |
188 | uint32_t syna, synb, sync; |
189 | |
190 | /* XO = 44MHz, R = 11, hence N is in units of XO / R = 4MHz. |
191 | * |
192 | * The channel spacing (5MHz) is not divisible by 4MHz, so |
193 | * we set the fractional part of N to compensate. |
194 | */ |
195 | int n = freq / 4, nf = (freq % 4) * 2; |
196 | |
197 | syna = __SHIFTIN(nf, SA2400_SYNA_NF_MASK) | __SHIFTIN(n, SA2400_SYNA_N_MASK); |
198 | verify_syna(freq, syna); |
199 | |
200 | /* Divide the 44MHz crystal down to 4MHz. Set the fractional |
201 | * compensation charge pump value to agree with the fractional |
202 | * modulus. |
203 | */ |
204 | synb = __SHIFTIN(11, SA2400_SYNB_R_MASK) | SA2400_SYNB_L_NORMAL | |
205 | SA2400_SYNB_ON | SA2400_SYNB_ONE | |
206 | __SHIFTIN(80, SA2400_SYNB_FC_MASK); /* agrees w/ SA2400_SYNA_FM = 0 */ |
207 | |
208 | sync = SA2400_SYNC_CP_NORMAL; |
209 | |
210 | if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNA, |
211 | syna)) != 0) |
212 | return rc; |
213 | if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNB, |
214 | synb)) != 0) |
215 | return rc; |
216 | if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNC, |
217 | sync)) != 0) |
218 | return rc; |
219 | return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYND, 0x0); |
220 | } |
221 | |
222 | static int |
223 | rtw_sa2400_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) |
224 | { |
225 | struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; |
226 | struct rtw_rfbus *bus = &sa->sa_bus; |
227 | uint32_t opmode; |
228 | opmode = SA2400_OPMODE_DEFAULTS; |
229 | switch (power) { |
230 | case RTW_ON: |
231 | opmode |= SA2400_OPMODE_MODE_TXRX; |
232 | break; |
233 | case RTW_SLEEP: |
234 | opmode |= SA2400_OPMODE_MODE_WAIT; |
235 | break; |
236 | case RTW_OFF: |
237 | opmode |= SA2400_OPMODE_MODE_SLEEP; |
238 | break; |
239 | } |
240 | |
241 | if (sa->sa_digphy) |
242 | opmode |= SA2400_OPMODE_DIGIN; |
243 | |
244 | return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, |
245 | opmode); |
246 | } |
247 | |
248 | static int |
249 | rtw_sa2400_manrx_init(struct rtw_sa2400 *sa) |
250 | { |
251 | uint32_t manrx; |
252 | |
253 | /* XXX we are not supposed to be in RXMGC mode when we do |
254 | * this? |
255 | */ |
256 | manrx = SA2400_MANRX_AHSN; |
257 | manrx |= SA2400_MANRX_TEN; |
258 | manrx |= __SHIFTIN(1023, SA2400_MANRX_RXGAIN_MASK); |
259 | |
260 | return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_MANRX, |
261 | manrx); |
262 | } |
263 | |
264 | static int |
265 | rtw_sa2400_vcocal_start(struct rtw_sa2400 *sa, int start) |
266 | { |
267 | uint32_t opmode; |
268 | |
269 | opmode = SA2400_OPMODE_DEFAULTS; |
270 | if (start) |
271 | opmode |= SA2400_OPMODE_MODE_VCOCALIB; |
272 | else |
273 | opmode |= SA2400_OPMODE_MODE_SLEEP; |
274 | |
275 | if (sa->sa_digphy) |
276 | opmode |= SA2400_OPMODE_DIGIN; |
277 | |
278 | return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, |
279 | opmode); |
280 | } |
281 | |
282 | static int |
283 | rtw_sa2400_vco_calibration(struct rtw_sa2400 *sa) |
284 | { |
285 | int rc; |
286 | /* calibrate VCO */ |
287 | if ((rc = rtw_sa2400_vcocal_start(sa, 1)) != 0) |
288 | return rc; |
289 | DELAY(2200); /* 2.2 milliseconds */ |
290 | /* XXX superfluous: SA2400 automatically entered SLEEP mode. */ |
291 | return rtw_sa2400_vcocal_start(sa, 0); |
292 | } |
293 | |
294 | static int |
295 | rtw_sa2400_filter_calibration(struct rtw_sa2400 *sa) |
296 | { |
297 | uint32_t opmode; |
298 | |
299 | opmode = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_FCALIB; |
300 | if (sa->sa_digphy) |
301 | opmode |= SA2400_OPMODE_DIGIN; |
302 | |
303 | return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, |
304 | opmode); |
305 | } |
306 | |
307 | static int |
308 | rtw_sa2400_dc_calibration(struct rtw_sa2400 *sa) |
309 | { |
310 | struct rtw_rf *rf = &sa->sa_rf; |
311 | int rc; |
312 | uint32_t dccal; |
313 | |
314 | (*rf->rf_continuous_tx_cb)(rf->rf_continuous_tx_arg, 1); |
315 | |
316 | dccal = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_TXRX; |
317 | |
318 | rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, |
319 | dccal); |
320 | if (rc != 0) |
321 | return rc; |
322 | |
323 | DELAY(5); /* DCALIB after being in Tx mode for 5 |
324 | * microseconds |
325 | */ |
326 | |
327 | dccal &= ~SA2400_OPMODE_MODE_MASK; |
328 | dccal |= SA2400_OPMODE_MODE_DCALIB; |
329 | |
330 | rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, |
331 | dccal); |
332 | if (rc != 0) |
333 | return rc; |
334 | |
335 | DELAY(20); /* calibration takes at most 20 microseconds */ |
336 | |
337 | (*rf->rf_continuous_tx_cb)(rf->rf_continuous_tx_arg, 0); |
338 | |
339 | return 0; |
340 | } |
341 | |
342 | static int |
343 | rtw_sa2400_agc_init(struct rtw_sa2400 *sa) |
344 | { |
345 | uint32_t agc; |
346 | |
347 | agc = __SHIFTIN(25, SA2400_AGC_MAXGAIN_MASK); |
348 | agc |= __SHIFTIN(7, SA2400_AGC_BBPDELAY_MASK); |
349 | agc |= __SHIFTIN(15, SA2400_AGC_LNADELAY_MASK); |
350 | agc |= __SHIFTIN(27, SA2400_AGC_RXONDELAY_MASK); |
351 | |
352 | return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_AGC, |
353 | agc); |
354 | } |
355 | |
356 | static void |
357 | rtw_sa2400_destroy(struct rtw_rf *rf) |
358 | { |
359 | struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; |
360 | memset(sa, 0, sizeof(*sa)); |
361 | free(sa, M_DEVBUF); |
362 | } |
363 | |
364 | static int |
365 | rtw_sa2400_calibrate(struct rtw_rf *rf, u_int freq) |
366 | { |
367 | struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; |
368 | int i, rc; |
369 | |
370 | /* XXX reference driver calibrates VCO twice. Is it a bug? */ |
371 | for (i = 0; i < 2; i++) { |
372 | if ((rc = rtw_sa2400_vco_calibration(sa)) != 0) |
373 | return rc; |
374 | } |
375 | /* VCO calibration erases synthesizer registers, so re-tune */ |
376 | if ((rc = rtw_sa2400_tune(rf, freq)) != 0) |
377 | return rc; |
378 | if ((rc = rtw_sa2400_filter_calibration(sa)) != 0) |
379 | return rc; |
380 | /* analog PHY needs DC calibration */ |
381 | if (!sa->sa_digphy) |
382 | return rtw_sa2400_dc_calibration(sa); |
383 | return 0; |
384 | } |
385 | |
386 | static int |
387 | rtw_sa2400_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower, |
388 | enum rtw_pwrstate power) |
389 | { |
390 | struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; |
391 | int rc; |
392 | |
393 | if ((rc = rtw_sa2400_txpower(rf, opaque_txpower)) != 0) |
394 | return rc; |
395 | |
396 | /* skip configuration if it's time to sleep or to power-down. */ |
397 | if (power == RTW_SLEEP || power == RTW_OFF) |
398 | return rtw_sa2400_pwrstate(rf, power); |
399 | |
400 | /* go to sleep for configuration */ |
401 | if ((rc = rtw_sa2400_pwrstate(rf, RTW_SLEEP)) != 0) |
402 | return rc; |
403 | |
404 | if ((rc = rtw_sa2400_tune(rf, freq)) != 0) |
405 | return rc; |
406 | if ((rc = rtw_sa2400_agc_init(sa)) != 0) |
407 | return rc; |
408 | if ((rc = rtw_sa2400_manrx_init(sa)) != 0) |
409 | return rc; |
410 | if ((rc = rtw_sa2400_calibrate(rf, freq)) != 0) |
411 | return rc; |
412 | |
413 | /* enter Tx/Rx mode */ |
414 | return rtw_sa2400_pwrstate(rf, power); |
415 | } |
416 | |
417 | struct rtw_rf * |
418 | rtw_sa2400_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int digphy) |
419 | { |
420 | struct rtw_sa2400 *sa; |
421 | struct rtw_rfbus *bus; |
422 | struct rtw_rf *rf; |
423 | struct rtw_bbpset *bb; |
424 | |
425 | sa = malloc(sizeof(*sa), M_DEVBUF, M_NOWAIT | M_ZERO); |
426 | if (sa == NULL) |
427 | return NULL; |
428 | |
429 | sa->sa_digphy = digphy; |
430 | |
431 | rf = &sa->sa_rf; |
432 | bus = &sa->sa_bus; |
433 | |
434 | rf->rf_init = rtw_sa2400_init; |
435 | rf->rf_destroy = rtw_sa2400_destroy; |
436 | rf->rf_txpower = rtw_sa2400_txpower; |
437 | rf->rf_tune = rtw_sa2400_tune; |
438 | rf->rf_pwrstate = rtw_sa2400_pwrstate; |
439 | bb = &rf->rf_bbpset; |
440 | |
441 | /* XXX magic */ |
442 | bb->bb_antatten = RTW_BBP_ANTATTEN_PHILIPS_MAGIC; |
443 | bb->bb_chestlim = 0x00; |
444 | bb->bb_chsqlim = 0xa0; |
445 | bb->bb_ifagcdet = 0x64; |
446 | bb->bb_ifagcini = 0x90; |
447 | bb->bb_ifagclimit = 0x1a; |
448 | bb->bb_lnadet = 0xe0; |
449 | bb->bb_sys1 = 0x98; |
450 | bb->bb_sys2 = 0x47; |
451 | bb->bb_sys3 = 0x90; |
452 | bb->bb_trl = 0x88; |
453 | bb->bb_txagc = 0x38; |
454 | |
455 | bus->b_regs = regs; |
456 | bus->b_write = rf_write; |
457 | |
458 | return &sa->sa_rf; |
459 | } |
460 | |
461 | static int |
462 | rtw_grf5101_txpower(struct rtw_rf *rf, uint8_t opaque_txpower) |
463 | { |
464 | struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; |
465 | |
466 | GCT_WRITE(gr, 0x15, 0, err); |
467 | GCT_WRITE(gr, 0x06, opaque_txpower, err); |
468 | GCT_WRITE(gr, 0x15, 0x10, err); |
469 | GCT_WRITE(gr, 0x15, 0x00, err); |
470 | return 0; |
471 | err: |
472 | return -1; |
473 | } |
474 | |
475 | static int |
476 | rtw_grf5101_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) |
477 | { |
478 | struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; |
479 | switch (power) { |
480 | case RTW_OFF: |
481 | case RTW_SLEEP: |
482 | GCT_WRITE(gr, 0x07, 0x0000, err); |
483 | GCT_WRITE(gr, 0x1f, 0x0045, err); |
484 | GCT_WRITE(gr, 0x1f, 0x0005, err); |
485 | GCT_WRITE(gr, 0x00, 0x08e4, err); |
486 | default: |
487 | break; |
488 | case RTW_ON: |
489 | GCT_WRITE(gr, 0x1f, 0x0001, err); |
490 | DELAY(10); |
491 | GCT_WRITE(gr, 0x1f, 0x0001, err); |
492 | DELAY(10); |
493 | GCT_WRITE(gr, 0x1f, 0x0041, err); |
494 | DELAY(10); |
495 | GCT_WRITE(gr, 0x1f, 0x0061, err); |
496 | DELAY(10); |
497 | GCT_WRITE(gr, 0x00, 0x0ae4, err); |
498 | DELAY(10); |
499 | GCT_WRITE(gr, 0x07, 0x1000, err); |
500 | DELAY(100); |
501 | break; |
502 | } |
503 | |
504 | return 0; |
505 | err: |
506 | return -1; |
507 | } |
508 | |
509 | static int |
510 | rtw_grf5101_tune(struct rtw_rf *rf, u_int freq) |
511 | { |
512 | int channel; |
513 | struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; |
514 | |
515 | if (freq == 2484) |
516 | channel = 14; |
517 | else if ((channel = (freq - 2412) / 5 + 1) < 1 || channel > 13) { |
518 | RTW_DPRINTF(RTW_DEBUG_PHY, |
519 | ("%s: invalid channel %d (freq %d)\n" , __func__, channel, |
520 | freq)); |
521 | return -1; |
522 | } |
523 | |
524 | GCT_WRITE(gr, 0x07, 0, err); |
525 | GCT_WRITE(gr, 0x0b, channel - 1, err); |
526 | GCT_WRITE(gr, 0x07, 0x1000, err); |
527 | return 0; |
528 | err: |
529 | return -1; |
530 | } |
531 | |
532 | static int |
533 | rtw_grf5101_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower, |
534 | enum rtw_pwrstate power) |
535 | { |
536 | int rc; |
537 | struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; |
538 | |
539 | /* |
540 | * These values have been derived from the rtl8180-sa2400 |
541 | * Linux driver. It is unknown what they all do, GCT refuse |
542 | * to release any documentation so these are more than |
543 | * likely sub optimal settings |
544 | */ |
545 | |
546 | GCT_WRITE(gr, 0x01, 0x1a23, err); |
547 | GCT_WRITE(gr, 0x02, 0x4971, err); |
548 | GCT_WRITE(gr, 0x03, 0x41de, err); |
549 | GCT_WRITE(gr, 0x04, 0x2d80, err); |
550 | |
551 | GCT_WRITE(gr, 0x05, 0x61ff, err); |
552 | |
553 | GCT_WRITE(gr, 0x06, 0x0, err); |
554 | |
555 | GCT_WRITE(gr, 0x08, 0x7533, err); |
556 | GCT_WRITE(gr, 0x09, 0xc401, err); |
557 | GCT_WRITE(gr, 0x0a, 0x0, err); |
558 | GCT_WRITE(gr, 0x0c, 0x1c7, err); |
559 | GCT_WRITE(gr, 0x0d, 0x29d3, err); |
560 | GCT_WRITE(gr, 0x0e, 0x2e8, err); |
561 | GCT_WRITE(gr, 0x10, 0x192, err); |
562 | GCT_WRITE(gr, 0x11, 0x248, err); |
563 | GCT_WRITE(gr, 0x12, 0x0, err); |
564 | GCT_WRITE(gr, 0x13, 0x20c4, err); |
565 | GCT_WRITE(gr, 0x14, 0xf4fc, err); |
566 | GCT_WRITE(gr, 0x15, 0x0, err); |
567 | GCT_WRITE(gr, 0x16, 0x1500, err); |
568 | |
569 | if ((rc = rtw_grf5101_txpower(rf, opaque_txpower)) != 0) |
570 | return rc; |
571 | |
572 | if ((rc = rtw_grf5101_tune(rf, freq)) != 0) |
573 | return rc; |
574 | |
575 | return 0; |
576 | err: |
577 | return -1; |
578 | } |
579 | |
580 | static void |
581 | rtw_grf5101_destroy(struct rtw_rf *rf) |
582 | { |
583 | struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; |
584 | memset(gr, 0, sizeof(*gr)); |
585 | free(gr, M_DEVBUF); |
586 | } |
587 | |
588 | struct rtw_rf * |
589 | rtw_grf5101_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, |
590 | int digphy) |
591 | { |
592 | struct rtw_grf5101 *gr; |
593 | struct rtw_rfbus *bus; |
594 | struct rtw_rf *rf; |
595 | struct rtw_bbpset *bb; |
596 | |
597 | gr = malloc(sizeof(*gr), M_DEVBUF, M_NOWAIT | M_ZERO); |
598 | if (gr == NULL) |
599 | return NULL; |
600 | |
601 | rf = &gr->gr_rf; |
602 | bus = &gr->gr_bus; |
603 | |
604 | rf->rf_init = rtw_grf5101_init; |
605 | rf->rf_destroy = rtw_grf5101_destroy; |
606 | rf->rf_txpower = rtw_grf5101_txpower; |
607 | rf->rf_tune = rtw_grf5101_tune; |
608 | rf->rf_pwrstate = rtw_grf5101_pwrstate; |
609 | bb = &rf->rf_bbpset; |
610 | |
611 | /* XXX magic */ |
612 | bb->bb_antatten = RTW_BBP_ANTATTEN_GCT_MAGIC; |
613 | bb->bb_chestlim = 0x00; |
614 | bb->bb_chsqlim = 0xa0; |
615 | bb->bb_ifagcdet = 0x64; |
616 | bb->bb_ifagcini = 0x90; |
617 | bb->bb_ifagclimit = 0x1e; |
618 | bb->bb_lnadet = 0xc0; |
619 | bb->bb_sys1 = 0xa8; |
620 | bb->bb_sys2 = 0x47; |
621 | bb->bb_sys3 = 0x9b; |
622 | bb->bb_trl = 0x88; |
623 | bb->bb_txagc = 0x08; |
624 | |
625 | bus->b_regs = regs; |
626 | bus->b_write = rf_write; |
627 | |
628 | return &gr->gr_rf; |
629 | } |
630 | |
631 | /* freq is in MHz */ |
632 | static int |
633 | rtw_max2820_tune(struct rtw_rf *rf, u_int freq) |
634 | { |
635 | struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; |
636 | struct rtw_rfbus *bus = &mx->mx_bus; |
637 | |
638 | if (freq < 2400 || freq > 2499) |
639 | return -1; |
640 | |
641 | return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_CHANNEL, |
642 | __SHIFTIN(freq - 2400, MAX2820_CHANNEL_CF_MASK)); |
643 | } |
644 | |
645 | static void |
646 | rtw_max2820_destroy(struct rtw_rf *rf) |
647 | { |
648 | struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; |
649 | memset(mx, 0, sizeof(*mx)); |
650 | free(mx, M_DEVBUF); |
651 | } |
652 | |
653 | static int |
654 | rtw_max2820_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower, |
655 | enum rtw_pwrstate power) |
656 | { |
657 | struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; |
658 | struct rtw_rfbus *bus = &mx->mx_bus; |
659 | int rc; |
660 | |
661 | if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TEST, |
662 | MAX2820_TEST_DEFAULT)) != 0) |
663 | return rc; |
664 | |
665 | if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, |
666 | MAX2820_ENABLE_DEFAULT)) != 0) |
667 | return rc; |
668 | |
669 | /* skip configuration if it's time to sleep or to power-down. */ |
670 | if ((rc = rtw_max2820_pwrstate(rf, power)) != 0) |
671 | return rc; |
672 | else if (power == RTW_OFF || power == RTW_SLEEP) |
673 | return 0; |
674 | |
675 | if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_SYNTH, |
676 | MAX2820_SYNTH_R_44MHZ)) != 0) |
677 | return rc; |
678 | |
679 | if ((rc = rtw_max2820_tune(rf, freq)) != 0) |
680 | return rc; |
681 | |
682 | /* XXX The MAX2820 datasheet indicates that 1C and 2C should not |
683 | * be changed from 7, however, the reference driver sets them |
684 | * to 4 and 1, respectively. |
685 | */ |
686 | if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_RECEIVE, |
687 | MAX2820_RECEIVE_DL_DEFAULT | |
688 | __SHIFTIN(4, MAX2820A_RECEIVE_1C_MASK) | |
689 | __SHIFTIN(1, MAX2820A_RECEIVE_2C_MASK))) != 0) |
690 | return rc; |
691 | |
692 | return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TRANSMIT, |
693 | MAX2820_TRANSMIT_PA_DEFAULT); |
694 | } |
695 | |
696 | static int |
697 | rtw_max2820_txpower(struct rtw_rf *rf, uint8_t opaque_txpower) |
698 | { |
699 | /* TBD */ |
700 | return 0; |
701 | } |
702 | |
703 | static int |
704 | rtw_max2820_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) |
705 | { |
706 | uint32_t enable; |
707 | struct rtw_max2820 *mx; |
708 | struct rtw_rfbus *bus; |
709 | |
710 | mx = (struct rtw_max2820 *)rf; |
711 | bus = &mx->mx_bus; |
712 | |
713 | switch (power) { |
714 | case RTW_OFF: |
715 | case RTW_SLEEP: |
716 | default: |
717 | enable = 0x0; |
718 | break; |
719 | case RTW_ON: |
720 | enable = MAX2820_ENABLE_DEFAULT; |
721 | break; |
722 | } |
723 | return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, enable); |
724 | } |
725 | |
726 | struct rtw_rf * |
727 | rtw_max2820_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int is_a) |
728 | { |
729 | struct rtw_max2820 *mx; |
730 | struct rtw_rfbus *bus; |
731 | struct rtw_rf *rf; |
732 | struct rtw_bbpset *bb; |
733 | |
734 | mx = malloc(sizeof(*mx), M_DEVBUF, M_NOWAIT | M_ZERO); |
735 | if (mx == NULL) |
736 | return NULL; |
737 | |
738 | mx->mx_is_a = is_a; |
739 | |
740 | rf = &mx->mx_rf; |
741 | bus = &mx->mx_bus; |
742 | |
743 | rf->rf_init = rtw_max2820_init; |
744 | rf->rf_destroy = rtw_max2820_destroy; |
745 | rf->rf_txpower = rtw_max2820_txpower; |
746 | rf->rf_tune = rtw_max2820_tune; |
747 | rf->rf_pwrstate = rtw_max2820_pwrstate; |
748 | bb = &rf->rf_bbpset; |
749 | |
750 | /* XXX magic */ |
751 | bb->bb_antatten = RTW_BBP_ANTATTEN_MAXIM_MAGIC; |
752 | bb->bb_chestlim = 0; |
753 | bb->bb_chsqlim = 159; |
754 | bb->bb_ifagcdet = 100; |
755 | bb->bb_ifagcini = 144; |
756 | bb->bb_ifagclimit = 26; |
757 | bb->bb_lnadet = 248; |
758 | bb->bb_sys1 = 136; |
759 | bb->bb_sys2 = 71; |
760 | bb->bb_sys3 = 155; |
761 | bb->bb_trl = 136; |
762 | bb->bb_txagc = 8; |
763 | |
764 | bus->b_regs = regs; |
765 | bus->b_write = rf_write; |
766 | |
767 | return &mx->mx_rf; |
768 | } |
769 | |
770 | /* freq is in MHz */ |
771 | int |
772 | rtw_phy_init(struct rtw_regs *regs, struct rtw_rf *rf, uint8_t opaque_txpower, |
773 | uint8_t cs_threshold, u_int freq, int antdiv, int dflantb, |
774 | enum rtw_pwrstate power) |
775 | { |
776 | int rc; |
777 | RTW_DPRINTF(RTW_DEBUG_PHY, |
778 | ("%s: txpower %u csthresh %u freq %u antdiv %u dflantb %u " |
779 | "pwrstate %s\n" , __func__, opaque_txpower, cs_threshold, freq, |
780 | antdiv, dflantb, rtw_pwrstate_string(power))); |
781 | |
782 | /* XXX is this really necessary? */ |
783 | if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0) |
784 | return rc; |
785 | if ((rc = rtw_bbp_preinit(regs, rf->rf_bbpset.bb_antatten, dflantb, |
786 | freq)) != 0) |
787 | return rc; |
788 | if ((rc = rtw_rf_tune(rf, freq)) != 0) |
789 | return rc; |
790 | /* initialize RF */ |
791 | if ((rc = rtw_rf_init(rf, freq, opaque_txpower, power)) != 0) |
792 | return rc; |
793 | #if 0 /* what is this redundant tx power setting here for? */ |
794 | if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0) |
795 | return rc; |
796 | #endif |
797 | return rtw_bbp_init(regs, &rf->rf_bbpset, antdiv, dflantb, |
798 | cs_threshold, freq); |
799 | } |
800 | |