1 | /* $NetBSD: tqphyreg.h,v 1.4 2005/12/11 12:22:42 christos Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1999 Soren S. Jorvang. |
5 | * All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions, and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * |
16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
26 | * SUCH DAMAGE. |
27 | */ |
28 | |
29 | #ifndef _DEV_MII_TQPHYREG_H_ |
30 | #define _DEV_MII_TQPHYREG_H_ |
31 | |
32 | /* |
33 | * TDK TSC78Q2120 PHY registers |
34 | * |
35 | * Documentation available at http://www.tsc.tdk.com/lan/78Q2120.pdf . |
36 | */ |
37 | |
38 | /* |
39 | * http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html has this to say: |
40 | * |
41 | * TDK Semiconductor (formerly Silicon Systems) 78Q2120 (10/100) and 78Q2121 |
42 | * (100Mbps only) MII transceivers. The first PHY available which worked at |
43 | * both 5.0 and 3.3V. Used on the 3Com 3c574 and Ositech products. The OUI |
44 | * is 00:c0:39, models 20 and 21. Warning: The older revision 3 part has |
45 | * several bugs. It always responds to MDIO address 0, and has clear-only |
46 | * semantics for the capability-advertise registers. The current (3/99) |
47 | * revision 11 part, shipping since 8/98, has reportedly fixed these problems. |
48 | */ |
49 | |
50 | #define MII_TQPHY_VENDOR 0x10 /* Vendor specific register */ |
51 | #define VENDOR_RPTR 0x8000 /* Repeater mode */ |
52 | #define VENDOR_INTLEVEL 0x4000 /* INTR pin level */ |
53 | #define VENDOR_RSVD1 0x2000 /* Reserved */ |
54 | #define VENDOR_TXHIM 0x1000 /* Transmit high impedance */ |
55 | #define VENDOR_SEQTESTINHIBIT 0x0800 /* Disables 10baseT SQE testing */ |
56 | #define VENDOR_10BT_LOOPBACK 0x0400 /* 10baseT natural loopback */ |
57 | #define VENDOR_GPIO1_DAT 0x0200 /* General purpose I/O 1 data */ |
58 | #define VENDOR_GPIO1_DIR 0x0100 /* General purpose I/O 1 direction */ |
59 | #define VENDOR_GPIO0_DAT 0x0080 /* General purpose I/O 0 data */ |
60 | #define VENDOR_GPIO0_DIR 0x0040 /* General purpose I/O 0 direction */ |
61 | #define VENDOR_APOL 0x0020 /* Auto polarity */ |
62 | #define VENDOR_RVSPOL 0x0010 /* Reverse polarity */ |
63 | #define VENDOR_RSVD2 0x0008 /* Reserved (must be zero) */ |
64 | #define VENDOR_RSVD3 0x0004 /* Reserved (must be zero) */ |
65 | #define VENDOR_PCSBP 0x0002 /* PCS bypass */ |
66 | #define VENDOR_RXCC 0x0001 /* Receive clock control */ |
67 | |
68 | #define MII_TQPHY_INTR 0x11 /* Interrupt control/status register */ |
69 | #define INTR_JABBER_IE 0x8000 /* Jabber interrupt enable */ |
70 | #define INTR_RXER_IE 0x4000 /* Receive error enable */ |
71 | #define INTR_PRX_IE 0x2000 /* Page received enable */ |
72 | #define INTR_PFD_IE 0x1000 /* Parallel detect fault enable */ |
73 | #define INTR_LPACK_IE 0x0800 /* Link partner ack. enable */ |
74 | #define INTR_LSCHG_IE 0x0400 /* Link status change enable */ |
75 | #define INTR_RFAULT_IE 0x0200 /* Remote fault enable */ |
76 | #define INTR_ANEGCOMP_IE 0x0100 /* Autonegotiation complete enable */ |
77 | #define INTR_JABBER_INT 0x0080 /* Jabber interrupt */ |
78 | #define INTR_RXER_INT 0x0040 /* Receive error interrupt */ |
79 | #define INTR_PRX_INT 0x0020 /* Page receive interrupt */ |
80 | #define INTR_PDF_INT 0x0010 /* Parallel detect fault interrupt */ |
81 | #define INTR_LPACK_INT 0x0008 /* Link partner ack. interrupt */ |
82 | #define INTR_LSCHG_INT 0x0004 /* Link status change interrupt */ |
83 | #define INTR_RFAULT_INT 0x0002 /* Remote fault interrupt */ |
84 | #define INTR_ANEGCOMP_INT 0x0001 /* Autonegotiation complete interrupt */ |
85 | |
86 | #define MII_TQPHY_DIAG 0x12 /* Diagnostic register */ |
87 | #define DIAG_ANEGF 0x1000 /* Autonegotiation fail */ |
88 | #define DIAG_DPLX 0x0800 /* Duplex (half/full) */ |
89 | #define DIAG_RATE 0x0400 /* Rate (10/100) */ |
90 | #define DIAG_RXPASS 0x0200 /* Receive pass */ |
91 | #define DIAG_RXLOCK 0x0100 /* Receive lock */ |
92 | |
93 | #endif /* _DEV_MII_TQPHYREG_H_ */ |
94 | |