1/* $NetBSD: nouveau_engine_graph_nv40.c,v 1.1.1.1 2014/08/06 12:36:26 riastradh Exp $ */
2
3/*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26
27#include <sys/cdefs.h>
28__KERNEL_RCSID(0, "$NetBSD: nouveau_engine_graph_nv40.c,v 1.1.1.1 2014/08/06 12:36:26 riastradh Exp $");
29
30#include <core/client.h>
31#include <core/os.h>
32#include <core/class.h>
33#include <core/handle.h>
34#include <core/engctx.h>
35
36#include <subdev/fb.h>
37#include <subdev/timer.h>
38
39#include <engine/graph.h>
40#include <engine/fifo.h>
41
42#include "nv40.h"
43#include "regs.h"
44
45struct nv40_graph_priv {
46 struct nouveau_graph base;
47 u32 size;
48};
49
50struct nv40_graph_chan {
51 struct nouveau_graph_chan base;
52};
53
54static u64
55nv40_graph_units(struct nouveau_graph *graph)
56{
57 struct nv40_graph_priv *priv = (void *)graph;
58
59 return nv_rd32(priv, 0x1540);
60}
61
62/*******************************************************************************
63 * Graphics object classes
64 ******************************************************************************/
65
66static int
67nv40_graph_object_ctor(struct nouveau_object *parent,
68 struct nouveau_object *engine,
69 struct nouveau_oclass *oclass, void *data, u32 size,
70 struct nouveau_object **pobject)
71{
72 struct nouveau_gpuobj *obj;
73 int ret;
74
75 ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
76 20, 16, 0, &obj);
77 *pobject = nv_object(obj);
78 if (ret)
79 return ret;
80
81 nv_wo32(obj, 0x00, nv_mclass(obj));
82 nv_wo32(obj, 0x04, 0x00000000);
83 nv_wo32(obj, 0x08, 0x00000000);
84#ifdef __BIG_ENDIAN
85 nv_mo32(obj, 0x08, 0x01000000, 0x01000000);
86#endif
87 nv_wo32(obj, 0x0c, 0x00000000);
88 nv_wo32(obj, 0x10, 0x00000000);
89 return 0;
90}
91
92static struct nouveau_ofuncs
93nv40_graph_ofuncs = {
94 .ctor = nv40_graph_object_ctor,
95 .dtor = _nouveau_gpuobj_dtor,
96 .init = _nouveau_gpuobj_init,
97 .fini = _nouveau_gpuobj_fini,
98 .rd32 = _nouveau_gpuobj_rd32,
99 .wr32 = _nouveau_gpuobj_wr32,
100};
101
102static struct nouveau_oclass
103nv40_graph_sclass[] = {
104 { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
105 { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
106 { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
107 { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
108 { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
109 { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
110 { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
111 { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
112 { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
113 { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
114 { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
115 { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
116 { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
117 { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
118 { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
119 { 0x4097, &nv40_graph_ofuncs, NULL }, /* curie */
120 {},
121};
122
123static struct nouveau_oclass
124nv44_graph_sclass[] = {
125 { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
126 { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
127 { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
128 { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
129 { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
130 { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
131 { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
132 { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
133 { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
134 { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
135 { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
136 { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
137 { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
138 { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
139 { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
140 { 0x4497, &nv40_graph_ofuncs, NULL }, /* curie */
141 {},
142};
143
144/*******************************************************************************
145 * PGRAPH context
146 ******************************************************************************/
147
148static int
149nv40_graph_context_ctor(struct nouveau_object *parent,
150 struct nouveau_object *engine,
151 struct nouveau_oclass *oclass, void *data, u32 size,
152 struct nouveau_object **pobject)
153{
154 struct nv40_graph_priv *priv = (void *)engine;
155 struct nv40_graph_chan *chan;
156 int ret;
157
158 ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
159 priv->size, 16,
160 NVOBJ_FLAG_ZERO_ALLOC, &chan);
161 *pobject = nv_object(chan);
162 if (ret)
163 return ret;
164
165 nv40_grctx_fill(nv_device(priv), nv_gpuobj(chan));
166 nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4);
167 return 0;
168}
169
170static int
171nv40_graph_context_fini(struct nouveau_object *object, bool suspend)
172{
173 struct nv40_graph_priv *priv = (void *)object->engine;
174 struct nv40_graph_chan *chan = (void *)object;
175 u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
176 int ret = 0;
177
178 nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
179
180 if (nv_rd32(priv, 0x40032c) == inst) {
181 if (suspend) {
182 nv_wr32(priv, 0x400720, 0x00000000);
183 nv_wr32(priv, 0x400784, inst);
184 nv_mask(priv, 0x400310, 0x00000020, 0x00000020);
185 nv_mask(priv, 0x400304, 0x00000001, 0x00000001);
186 if (!nv_wait(priv, 0x400300, 0x00000001, 0x00000000)) {
187 u32 insn = nv_rd32(priv, 0x400308);
188 nv_warn(priv, "ctxprog timeout 0x%08x\n", insn);
189 ret = -EBUSY;
190 }
191 }
192
193 nv_mask(priv, 0x40032c, 0x01000000, 0x00000000);
194 }
195
196 if (nv_rd32(priv, 0x400330) == inst)
197 nv_mask(priv, 0x400330, 0x01000000, 0x00000000);
198
199 nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
200 return ret;
201}
202
203static struct nouveau_oclass
204nv40_graph_cclass = {
205 .handle = NV_ENGCTX(GR, 0x40),
206 .ofuncs = &(struct nouveau_ofuncs) {
207 .ctor = nv40_graph_context_ctor,
208 .dtor = _nouveau_graph_context_dtor,
209 .init = _nouveau_graph_context_init,
210 .fini = nv40_graph_context_fini,
211 .rd32 = _nouveau_graph_context_rd32,
212 .wr32 = _nouveau_graph_context_wr32,
213 },
214};
215
216/*******************************************************************************
217 * PGRAPH engine/subdev functions
218 ******************************************************************************/
219
220static void
221nv40_graph_tile_prog(struct nouveau_engine *engine, int i)
222{
223 struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
224 struct nouveau_fifo *pfifo = nouveau_fifo(engine);
225 struct nv40_graph_priv *priv = (void *)engine;
226 unsigned long flags;
227
228 pfifo->pause(pfifo, &flags);
229 nv04_graph_idle(priv);
230
231 switch (nv_device(priv)->chipset) {
232 case 0x40:
233 case 0x41:
234 case 0x42:
235 case 0x43:
236 case 0x45:
237 case 0x4e:
238 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
239 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
240 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
241 nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
242 nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
243 nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
244 switch (nv_device(priv)->chipset) {
245 case 0x40:
246 case 0x45:
247 nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
248 nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);
249 break;
250 case 0x41:
251 case 0x42:
252 case 0x43:
253 nv_wr32(priv, NV41_PGRAPH_ZCOMP0(i), tile->zcomp);
254 nv_wr32(priv, NV41_PGRAPH_ZCOMP1(i), tile->zcomp);
255 break;
256 default:
257 break;
258 }
259 break;
260 case 0x44:
261 case 0x4a:
262 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
263 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
264 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
265 break;
266 case 0x46:
267 case 0x4c:
268 case 0x47:
269 case 0x49:
270 case 0x4b:
271 case 0x63:
272 case 0x67:
273 case 0x68:
274 nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch);
275 nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit);
276 nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr);
277 nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
278 nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
279 nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
280 switch (nv_device(priv)->chipset) {
281 case 0x47:
282 case 0x49:
283 case 0x4b:
284 nv_wr32(priv, NV47_PGRAPH_ZCOMP0(i), tile->zcomp);
285 nv_wr32(priv, NV47_PGRAPH_ZCOMP1(i), tile->zcomp);
286 break;
287 default:
288 break;
289 }
290 break;
291 default:
292 break;
293 }
294
295 pfifo->start(pfifo, &flags);
296}
297
298static void
299nv40_graph_intr(struct nouveau_subdev *subdev)
300{
301 struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
302 struct nouveau_engine *engine = nv_engine(subdev);
303 struct nouveau_object *engctx;
304 struct nouveau_handle *handle = NULL;
305 struct nv40_graph_priv *priv = (void *)subdev;
306 u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
307 u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
308 u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
309 u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff;
310 u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
311 u32 subc = (addr & 0x00070000) >> 16;
312 u32 mthd = (addr & 0x00001ffc);
313 u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
314 u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff;
315 u32 show = stat;
316 int chid;
317
318 engctx = nouveau_engctx_get(engine, inst);
319 chid = pfifo->chid(pfifo, engctx);
320
321 if (stat & NV_PGRAPH_INTR_ERROR) {
322 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
323 handle = nouveau_handle_get_class(engctx, class);
324 if (handle && !nv_call(handle->object, mthd, data))
325 show &= ~NV_PGRAPH_INTR_ERROR;
326 nouveau_handle_put(handle);
327 }
328
329 if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
330 nv_mask(priv, 0x402000, 0, 0);
331 }
332 }
333
334 nv_wr32(priv, NV03_PGRAPH_INTR, stat);
335 nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
336
337 if (show) {
338 nv_error(priv, "%s", "");
339 nouveau_bitfield_print(nv10_graph_intr_name, show);
340 pr_cont(" nsource:");
341 nouveau_bitfield_print(nv04_graph_nsource, nsource);
342 pr_cont(" nstatus:");
343 nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
344 pr_cont("\n");
345 nv_error(priv,
346 "ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
347 chid, inst << 4, nouveau_client_name(engctx), subc,
348 class, mthd, data);
349 }
350
351 nouveau_engctx_put(engctx);
352}
353
354static int
355nv40_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
356 struct nouveau_oclass *oclass, void *data, u32 size,
357 struct nouveau_object **pobject)
358{
359 struct nv40_graph_priv *priv;
360 int ret;
361
362 ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
363 *pobject = nv_object(priv);
364 if (ret)
365 return ret;
366
367 nv_subdev(priv)->unit = 0x00001000;
368 nv_subdev(priv)->intr = nv40_graph_intr;
369 nv_engine(priv)->cclass = &nv40_graph_cclass;
370 if (nv44_graph_class(priv))
371 nv_engine(priv)->sclass = nv44_graph_sclass;
372 else
373 nv_engine(priv)->sclass = nv40_graph_sclass;
374 nv_engine(priv)->tile_prog = nv40_graph_tile_prog;
375
376 priv->base.units = nv40_graph_units;
377 return 0;
378}
379
380static int
381nv40_graph_init(struct nouveau_object *object)
382{
383 struct nouveau_engine *engine = nv_engine(object);
384 struct nouveau_fb *pfb = nouveau_fb(object);
385 struct nv40_graph_priv *priv = (void *)engine;
386 int ret, i, j;
387 u32 vramsz;
388
389 ret = nouveau_graph_init(&priv->base);
390 if (ret)
391 return ret;
392
393 /* generate and upload context program */
394 ret = nv40_grctx_init(nv_device(priv), &priv->size);
395 if (ret)
396 return ret;
397
398 /* No context present currently */
399 nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
400
401 nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
402 nv_wr32(priv, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
403
404 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
405 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
406 nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
407 nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
408 nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
409 nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
410
411 nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
412 nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF);
413
414 j = nv_rd32(priv, 0x1540) & 0xff;
415 if (j) {
416 for (i = 0; !(j & 1); j >>= 1, i++)
417 ;
418 nv_wr32(priv, 0x405000, i);
419 }
420
421 if (nv_device(priv)->chipset == 0x40) {
422 nv_wr32(priv, 0x4009b0, 0x83280fff);
423 nv_wr32(priv, 0x4009b4, 0x000000a0);
424 } else {
425 nv_wr32(priv, 0x400820, 0x83280eff);
426 nv_wr32(priv, 0x400824, 0x000000a0);
427 }
428
429 switch (nv_device(priv)->chipset) {
430 case 0x40:
431 case 0x45:
432 nv_wr32(priv, 0x4009b8, 0x0078e366);
433 nv_wr32(priv, 0x4009bc, 0x0000014c);
434 break;
435 case 0x41:
436 case 0x42: /* pciid also 0x00Cx */
437 /* case 0x0120: XXX (pciid) */
438 nv_wr32(priv, 0x400828, 0x007596ff);
439 nv_wr32(priv, 0x40082c, 0x00000108);
440 break;
441 case 0x43:
442 nv_wr32(priv, 0x400828, 0x0072cb77);
443 nv_wr32(priv, 0x40082c, 0x00000108);
444 break;
445 case 0x44:
446 case 0x46: /* G72 */
447 case 0x4a:
448 case 0x4c: /* G7x-based C51 */
449 case 0x4e:
450 nv_wr32(priv, 0x400860, 0);
451 nv_wr32(priv, 0x400864, 0);
452 break;
453 case 0x47: /* G70 */
454 case 0x49: /* G71 */
455 case 0x4b: /* G73 */
456 nv_wr32(priv, 0x400828, 0x07830610);
457 nv_wr32(priv, 0x40082c, 0x0000016A);
458 break;
459 default:
460 break;
461 }
462
463 nv_wr32(priv, 0x400b38, 0x2ffff800);
464 nv_wr32(priv, 0x400b3c, 0x00006000);
465
466 /* Tiling related stuff. */
467 switch (nv_device(priv)->chipset) {
468 case 0x44:
469 case 0x4a:
470 nv_wr32(priv, 0x400bc4, 0x1003d888);
471 nv_wr32(priv, 0x400bbc, 0xb7a7b500);
472 break;
473 case 0x46:
474 nv_wr32(priv, 0x400bc4, 0x0000e024);
475 nv_wr32(priv, 0x400bbc, 0xb7a7b520);
476 break;
477 case 0x4c:
478 case 0x4e:
479 case 0x67:
480 nv_wr32(priv, 0x400bc4, 0x1003d888);
481 nv_wr32(priv, 0x400bbc, 0xb7a7b540);
482 break;
483 default:
484 break;
485 }
486
487 /* Turn all the tiling regions off. */
488 for (i = 0; i < pfb->tile.regions; i++)
489 engine->tile_prog(engine, i);
490
491 /* begin RAM config */
492 vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
493 switch (nv_device(priv)->chipset) {
494 case 0x40:
495 nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
496 nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
497 nv_wr32(priv, 0x4069A4, nv_rd32(priv, 0x100200));
498 nv_wr32(priv, 0x4069A8, nv_rd32(priv, 0x100204));
499 nv_wr32(priv, 0x400820, 0);
500 nv_wr32(priv, 0x400824, 0);
501 nv_wr32(priv, 0x400864, vramsz);
502 nv_wr32(priv, 0x400868, vramsz);
503 break;
504 default:
505 switch (nv_device(priv)->chipset) {
506 case 0x41:
507 case 0x42:
508 case 0x43:
509 case 0x45:
510 case 0x4e:
511 case 0x44:
512 case 0x4a:
513 nv_wr32(priv, 0x4009F0, nv_rd32(priv, 0x100200));
514 nv_wr32(priv, 0x4009F4, nv_rd32(priv, 0x100204));
515 break;
516 default:
517 nv_wr32(priv, 0x400DF0, nv_rd32(priv, 0x100200));
518 nv_wr32(priv, 0x400DF4, nv_rd32(priv, 0x100204));
519 break;
520 }
521 nv_wr32(priv, 0x4069F0, nv_rd32(priv, 0x100200));
522 nv_wr32(priv, 0x4069F4, nv_rd32(priv, 0x100204));
523 nv_wr32(priv, 0x400840, 0);
524 nv_wr32(priv, 0x400844, 0);
525 nv_wr32(priv, 0x4008A0, vramsz);
526 nv_wr32(priv, 0x4008A4, vramsz);
527 break;
528 }
529
530 return 0;
531}
532
533struct nouveau_oclass
534nv40_graph_oclass = {
535 .handle = NV_ENGINE(GR, 0x40),
536 .ofuncs = &(struct nouveau_ofuncs) {
537 .ctor = nv40_graph_ctor,
538 .dtor = _nouveau_graph_dtor,
539 .init = nv40_graph_init,
540 .fini = _nouveau_graph_fini,
541 },
542};
543