1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef PP_SISLANDS_SMC_H |
24 | #define PP_SISLANDS_SMC_H |
25 | |
26 | #include "ppsmc.h" |
27 | |
28 | #pragma pack(push, 1) |
29 | |
30 | #define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 |
31 | |
32 | struct PP_SIslands_Dpm2PerfLevel |
33 | { |
34 | uint8_t MaxPS; |
35 | uint8_t TgtAct; |
36 | uint8_t MaxPS_StepInc; |
37 | uint8_t MaxPS_StepDec; |
38 | uint8_t PSSamplingTime; |
39 | uint8_t NearTDPDec; |
40 | uint8_t AboveSafeInc; |
41 | uint8_t BelowSafeInc; |
42 | uint8_t PSDeltaLimit; |
43 | uint8_t PSDeltaWin; |
44 | uint16_t PwrEfficiencyRatio; |
45 | uint8_t Reserved[4]; |
46 | }; |
47 | |
48 | typedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel; |
49 | |
50 | struct PP_SIslands_DPM2Status |
51 | { |
52 | uint32_t dpm2Flags; |
53 | uint8_t CurrPSkip; |
54 | uint8_t CurrPSkipPowerShift; |
55 | uint8_t CurrPSkipTDP; |
56 | uint8_t CurrPSkipOCP; |
57 | uint8_t MaxSPLLIndex; |
58 | uint8_t MinSPLLIndex; |
59 | uint8_t CurrSPLLIndex; |
60 | uint8_t InfSweepMode; |
61 | uint8_t InfSweepDir; |
62 | uint8_t TDPexceeded; |
63 | uint8_t reserved; |
64 | uint8_t SwitchDownThreshold; |
65 | uint32_t SwitchDownCounter; |
66 | uint32_t SysScalingFactor; |
67 | }; |
68 | |
69 | typedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status; |
70 | |
71 | struct PP_SIslands_DPM2Parameters |
72 | { |
73 | uint32_t TDPLimit; |
74 | uint32_t NearTDPLimit; |
75 | uint32_t SafePowerLimit; |
76 | uint32_t PowerBoostLimit; |
77 | uint32_t MinLimitDelta; |
78 | }; |
79 | typedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters; |
80 | |
81 | struct PP_SIslands_PAPMStatus |
82 | { |
83 | uint32_t EstimatedDGPU_T; |
84 | uint32_t EstimatedDGPU_P; |
85 | uint32_t EstimatedAPU_T; |
86 | uint32_t EstimatedAPU_P; |
87 | uint8_t dGPU_T_Limit_Exceeded; |
88 | uint8_t reserved[3]; |
89 | }; |
90 | typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus; |
91 | |
92 | struct PP_SIslands_PAPMParameters |
93 | { |
94 | uint32_t NearTDPLimitTherm; |
95 | uint32_t NearTDPLimitPAPM; |
96 | uint32_t PlatformPowerLimit; |
97 | uint32_t dGPU_T_Limit; |
98 | uint32_t dGPU_T_Warning; |
99 | uint32_t dGPU_T_Hysteresis; |
100 | }; |
101 | typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters; |
102 | |
103 | struct SISLANDS_SMC_SCLK_VALUE |
104 | { |
105 | uint32_t vCG_SPLL_FUNC_CNTL; |
106 | uint32_t vCG_SPLL_FUNC_CNTL_2; |
107 | uint32_t vCG_SPLL_FUNC_CNTL_3; |
108 | uint32_t vCG_SPLL_FUNC_CNTL_4; |
109 | uint32_t vCG_SPLL_SPREAD_SPECTRUM; |
110 | uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; |
111 | uint32_t sclk_value; |
112 | }; |
113 | |
114 | typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE; |
115 | |
116 | struct SISLANDS_SMC_MCLK_VALUE |
117 | { |
118 | uint32_t vMPLL_FUNC_CNTL; |
119 | uint32_t vMPLL_FUNC_CNTL_1; |
120 | uint32_t vMPLL_FUNC_CNTL_2; |
121 | uint32_t vMPLL_AD_FUNC_CNTL; |
122 | uint32_t vMPLL_DQ_FUNC_CNTL; |
123 | uint32_t vMCLK_PWRMGT_CNTL; |
124 | uint32_t vDLL_CNTL; |
125 | uint32_t vMPLL_SS; |
126 | uint32_t vMPLL_SS2; |
127 | uint32_t mclk_value; |
128 | }; |
129 | |
130 | typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE; |
131 | |
132 | struct SISLANDS_SMC_VOLTAGE_VALUE |
133 | { |
134 | uint16_t value; |
135 | uint8_t index; |
136 | uint8_t phase_settings; |
137 | }; |
138 | |
139 | typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE; |
140 | |
141 | struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL |
142 | { |
143 | uint8_t ACIndex; |
144 | uint8_t displayWatermark; |
145 | uint8_t gen2PCIE; |
146 | uint8_t UVDWatermark; |
147 | uint8_t VCEWatermark; |
148 | uint8_t strobeMode; |
149 | uint8_t mcFlags; |
150 | uint8_t padding; |
151 | uint32_t aT; |
152 | uint32_t bSP; |
153 | SISLANDS_SMC_SCLK_VALUE sclk; |
154 | SISLANDS_SMC_MCLK_VALUE mclk; |
155 | SISLANDS_SMC_VOLTAGE_VALUE vddc; |
156 | SISLANDS_SMC_VOLTAGE_VALUE mvdd; |
157 | SISLANDS_SMC_VOLTAGE_VALUE vddci; |
158 | SISLANDS_SMC_VOLTAGE_VALUE std_vddc; |
159 | uint8_t hysteresisUp; |
160 | uint8_t hysteresisDown; |
161 | uint8_t stateFlags; |
162 | uint8_t arbRefreshState; |
163 | uint32_t SQPowerThrottle; |
164 | uint32_t SQPowerThrottle_2; |
165 | uint32_t MaxPoweredUpCU; |
166 | SISLANDS_SMC_VOLTAGE_VALUE high_temp_vddc; |
167 | SISLANDS_SMC_VOLTAGE_VALUE low_temp_vddc; |
168 | uint32_t reserved[2]; |
169 | PP_SIslands_Dpm2PerfLevel dpm2; |
170 | }; |
171 | |
172 | #define SISLANDS_SMC_STROBE_RATIO 0x0F |
173 | #define SISLANDS_SMC_STROBE_ENABLE 0x10 |
174 | |
175 | #define SISLANDS_SMC_MC_EDC_RD_FLAG 0x01 |
176 | #define SISLANDS_SMC_MC_EDC_WR_FLAG 0x02 |
177 | #define SISLANDS_SMC_MC_RTT_ENABLE 0x04 |
178 | #define SISLANDS_SMC_MC_STUTTER_EN 0x08 |
179 | #define SISLANDS_SMC_MC_PG_EN 0x10 |
180 | |
181 | typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL; |
182 | |
183 | struct SISLANDS_SMC_SWSTATE |
184 | { |
185 | uint8_t flags; |
186 | uint8_t levelCount; |
187 | uint8_t padding2; |
188 | uint8_t padding3; |
189 | SISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1]; |
190 | }; |
191 | |
192 | typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE; |
193 | |
194 | #define SISLANDS_SMC_VOLTAGEMASK_VDDC 0 |
195 | #define SISLANDS_SMC_VOLTAGEMASK_MVDD 1 |
196 | #define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2 |
197 | #define SISLANDS_SMC_VOLTAGEMASK_MAX 4 |
198 | |
199 | struct SISLANDS_SMC_VOLTAGEMASKTABLE |
200 | { |
201 | uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX]; |
202 | }; |
203 | |
204 | typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE; |
205 | |
206 | #define SISLANDS_MAX_NO_VREG_STEPS 32 |
207 | |
208 | struct SISLANDS_SMC_STATETABLE |
209 | { |
210 | uint8_t thermalProtectType; |
211 | uint8_t systemFlags; |
212 | uint8_t maxVDDCIndexInPPTable; |
213 | uint8_t extraFlags; |
214 | uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS]; |
215 | SISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; |
216 | SISLANDS_SMC_VOLTAGEMASKTABLE phaseMaskTable; |
217 | PP_SIslands_DPM2Parameters dpm2Params; |
218 | SISLANDS_SMC_SWSTATE initialState; |
219 | SISLANDS_SMC_SWSTATE ACPIState; |
220 | SISLANDS_SMC_SWSTATE ULVState; |
221 | SISLANDS_SMC_SWSTATE driverState; |
222 | SISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1]; |
223 | }; |
224 | |
225 | typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE; |
226 | |
227 | #define SI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0 |
228 | #define SI_SMC_SOFT_REGISTER_delay_vreg 0xC |
229 | #define SI_SMC_SOFT_REGISTER_delay_acpi 0x28 |
230 | #define SI_SMC_SOFT_REGISTER_seq_index 0x5C |
231 | #define SI_SMC_SOFT_REGISTER_mvdd_chg_time 0x60 |
232 | #define SI_SMC_SOFT_REGISTER_mclk_switch_lim 0x70 |
233 | #define SI_SMC_SOFT_REGISTER_watermark_threshold 0x78 |
234 | #define SI_SMC_SOFT_REGISTER_phase_shedding_delay 0x88 |
235 | #define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay 0x8C |
236 | #define SI_SMC_SOFT_REGISTER_mc_block_delay 0x98 |
237 | #define SI_SMC_SOFT_REGISTER_ticks_per_us 0xA8 |
238 | #define SI_SMC_SOFT_REGISTER_crtc_index 0xC4 |
239 | #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min 0xC8 |
240 | #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max 0xCC |
241 | #define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width 0xF4 |
242 | #define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen 0xFC |
243 | #define SI_SMC_SOFT_REGISTER_vr_hot_gpio 0x100 |
244 | |
245 | #define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 |
246 | #define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32 |
247 | |
248 | #define SMC_SISLANDS_SCALE_I 7 |
249 | #define SMC_SISLANDS_SCALE_R 12 |
250 | |
251 | struct PP_SIslands_CacConfig |
252 | { |
253 | uint16_t cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES]; |
254 | uint32_t lkge_lut_V0; |
255 | uint32_t lkge_lut_Vstep; |
256 | uint32_t WinTime; |
257 | uint32_t R_LL; |
258 | uint32_t calculation_repeats; |
259 | uint32_t l2numWin_TDP; |
260 | uint32_t dc_cac; |
261 | uint8_t lts_truncate_n; |
262 | uint8_t SHIFT_N; |
263 | uint8_t log2_PG_LKG_SCALE; |
264 | uint8_t cac_temp; |
265 | uint32_t lkge_lut_T0; |
266 | uint32_t lkge_lut_Tstep; |
267 | }; |
268 | |
269 | typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig; |
270 | |
271 | #define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16 |
272 | #define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 |
273 | |
274 | struct SMC_SIslands_MCRegisterAddress |
275 | { |
276 | uint16_t s0; |
277 | uint16_t s1; |
278 | }; |
279 | |
280 | typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress; |
281 | |
282 | struct SMC_SIslands_MCRegisterSet |
283 | { |
284 | uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; |
285 | }; |
286 | |
287 | typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet; |
288 | |
289 | struct SMC_SIslands_MCRegisters |
290 | { |
291 | uint8_t last; |
292 | uint8_t reserved[3]; |
293 | SMC_SIslands_MCRegisterAddress address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; |
294 | SMC_SIslands_MCRegisterSet data[SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; |
295 | }; |
296 | |
297 | typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters; |
298 | |
299 | struct SMC_SIslands_MCArbDramTimingRegisterSet |
300 | { |
301 | uint32_t mc_arb_dram_timing; |
302 | uint32_t mc_arb_dram_timing2; |
303 | uint8_t mc_arb_rfsh_rate; |
304 | uint8_t mc_arb_burst_time; |
305 | uint8_t padding[2]; |
306 | }; |
307 | |
308 | typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet; |
309 | |
310 | struct SMC_SIslands_MCArbDramTimingRegisters |
311 | { |
312 | uint8_t arb_current; |
313 | uint8_t reserved[3]; |
314 | SMC_SIslands_MCArbDramTimingRegisterSet data[16]; |
315 | }; |
316 | |
317 | typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters; |
318 | |
319 | struct SMC_SISLANDS_SPLL_DIV_TABLE |
320 | { |
321 | uint32_t freq[256]; |
322 | uint32_t ss[256]; |
323 | }; |
324 | |
325 | #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff |
326 | #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0 |
327 | #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000 |
328 | #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25 |
329 | #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff |
330 | #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0 |
331 | #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000 |
332 | #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20 |
333 | |
334 | typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE; |
335 | |
336 | #define SMC_SISLANDS_DTE_MAX_FILTER_STAGES 5 |
337 | |
338 | #define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16 |
339 | |
340 | struct Smc_SIslands_DTE_Configuration |
341 | { |
342 | uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; |
343 | uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; |
344 | uint32_t K; |
345 | uint32_t T0; |
346 | uint32_t MaxT; |
347 | uint8_t WindowSize; |
348 | uint8_t Tdep_count; |
349 | uint8_t temp_select; |
350 | uint8_t DTE_mode; |
351 | uint8_t T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; |
352 | uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; |
353 | uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; |
354 | uint32_t Tthreshold; |
355 | }; |
356 | |
357 | typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration; |
358 | |
359 | #define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON 1 |
360 | |
361 | #define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x10000 |
362 | |
363 | #define SISLANDS_SMC_FIRMWARE_HEADER_version 0x0 |
364 | #define SISLANDS_SMC_FIRMWARE_HEADER_flags 0x4 |
365 | #define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0xC |
366 | #define SISLANDS_SMC_FIRMWARE_HEADER_stateTable 0x10 |
367 | #define SISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x14 |
368 | #define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable 0x18 |
369 | #define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x24 |
370 | #define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x30 |
371 | #define SISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x38 |
372 | #define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration 0x40 |
373 | #define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters 0x48 |
374 | |
375 | #pragma pack(pop) |
376 | |
377 | int si_copy_bytes_to_smc(struct radeon_device *rdev, |
378 | u32 smc_start_address, |
379 | const u8 *src, u32 byte_count, u32 limit); |
380 | void si_start_smc(struct radeon_device *rdev); |
381 | void si_reset_smc(struct radeon_device *rdev); |
382 | int si_program_jump_on_start(struct radeon_device *rdev); |
383 | void si_stop_smc_clock(struct radeon_device *rdev); |
384 | void si_start_smc_clock(struct radeon_device *rdev); |
385 | bool si_is_smc_running(struct radeon_device *rdev); |
386 | PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg); |
387 | PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev); |
388 | int si_load_smc_ucode(struct radeon_device *rdev, u32 limit); |
389 | int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, |
390 | u32 *value, u32 limit); |
391 | int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, |
392 | u32 value, u32 limit); |
393 | |
394 | #endif |
395 | |
396 | |