1 | /* $NetBSD: artsata.c,v 1.26 2014/03/29 19:28:24 christos Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 2003 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Jason R. Thorpe of Wasabi Systems, Inc. |
9 | * |
10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions |
12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. |
15 | * 2. Redistributions in binary form must reproduce the above copyright |
16 | * notice, this list of conditions and the following disclaimer in the |
17 | * documentation and/or other materials provided with the distribution. |
18 | * |
19 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
20 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
21 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
22 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
29 | * POSSIBILITY OF SUCH DAMAGE. |
30 | */ |
31 | |
32 | #include <sys/cdefs.h> |
33 | __KERNEL_RCSID(0, "$NetBSD: artsata.c,v 1.26 2014/03/29 19:28:24 christos Exp $" ); |
34 | |
35 | #include "opt_pciide.h" |
36 | |
37 | #include <sys/param.h> |
38 | #include <sys/systm.h> |
39 | #include <sys/malloc.h> |
40 | |
41 | #include <dev/pci/pcivar.h> |
42 | #include <dev/pci/pcidevs.h> |
43 | #include <dev/pci/pciidereg.h> |
44 | #include <dev/pci/pciidevar.h> |
45 | #include <dev/pci/pciide_i31244_reg.h> |
46 | |
47 | #include <dev/ata/satareg.h> |
48 | #include <dev/ata/satavar.h> |
49 | #include <dev/ata/atareg.h> |
50 | #include <dev/ata/atavar.h> |
51 | |
52 | static void artisea_chip_map(struct pciide_softc*, |
53 | const struct pci_attach_args *); |
54 | |
55 | static int artsata_match(device_t, cfdata_t, void *); |
56 | static void artsata_attach(device_t, device_t, void *); |
57 | |
58 | static const struct pciide_product_desc pciide_artsata_products[] = { |
59 | { PCI_PRODUCT_INTEL_31244, |
60 | 0, |
61 | "Intel 31244 Serial ATA Controller" , |
62 | artisea_chip_map, |
63 | }, |
64 | { 0, |
65 | 0, |
66 | NULL, |
67 | NULL |
68 | } |
69 | }; |
70 | |
71 | struct artisea_cmd_map |
72 | { |
73 | u_int8_t offset; |
74 | u_int8_t size; |
75 | }; |
76 | |
77 | static const struct artisea_cmd_map artisea_dpa_cmd_map[] = |
78 | { |
79 | {ARTISEA_SUPDDR, 4}, /* 0 Data */ |
80 | {ARTISEA_SUPDER, 1}, /* 1 Error */ |
81 | {ARTISEA_SUPDCSR, 2}, /* 2 Sector Count */ |
82 | {ARTISEA_SUPDSNR, 2}, /* 3 Sector Number */ |
83 | {ARTISEA_SUPDCLR, 2}, /* 4 Cylinder Low */ |
84 | {ARTISEA_SUPDCHR, 2}, /* 5 Cylinder High */ |
85 | {ARTISEA_SUPDDHR, 1}, /* 6 Device/Head */ |
86 | {ARTISEA_SUPDCR, 1}, /* 7 Command */ |
87 | {ARTISEA_SUPDSR, 1}, /* 8 Status */ |
88 | {ARTISEA_SUPDFR, 2} /* 9 Feature */ |
89 | }; |
90 | |
91 | #define ARTISEA_NUM_CHAN 4 |
92 | |
93 | CFATTACH_DECL_NEW(artsata, sizeof(struct pciide_softc), |
94 | artsata_match, artsata_attach, pciide_detach, NULL); |
95 | |
96 | static int |
97 | artsata_match(device_t parent, cfdata_t match, void *aux) |
98 | { |
99 | struct pci_attach_args *pa = aux; |
100 | |
101 | if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { |
102 | if (pciide_lookup_product(pa->pa_id, pciide_artsata_products)) |
103 | return (2); |
104 | } |
105 | return (0); |
106 | } |
107 | |
108 | static void |
109 | artsata_attach(device_t parent, device_t self, void *aux) |
110 | { |
111 | struct pci_attach_args *pa = aux; |
112 | struct pciide_softc *sc = device_private(self); |
113 | |
114 | sc->sc_wdcdev.sc_atac.atac_dev = self; |
115 | |
116 | pciide_common_attach(sc, pa, |
117 | pciide_lookup_product(pa->pa_id, pciide_artsata_products)); |
118 | |
119 | } |
120 | |
121 | static void |
122 | artisea_mapregs(const struct pci_attach_args *pa, struct pciide_channel *cp, |
123 | int (*pci_intr)(void *)) |
124 | { |
125 | struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); |
126 | struct ata_channel *wdc_cp = &cp->ata_channel; |
127 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); |
128 | const char *intrstr; |
129 | pci_intr_handle_t intrhandle; |
130 | int i; |
131 | char intrbuf[PCI_INTRSTR_LEN]; |
132 | |
133 | cp->compat = 0; |
134 | |
135 | if (sc->sc_pci_ih == NULL) { |
136 | if (pci_intr_map(pa, &intrhandle) != 0) { |
137 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
138 | "couldn't map native-PCI interrupt\n" ); |
139 | goto bad; |
140 | } |
141 | intrstr = pci_intr_string(pa->pa_pc, intrhandle, |
142 | intrbuf, sizeof(intrbuf)); |
143 | sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, |
144 | intrhandle, IPL_BIO, pci_intr, sc); |
145 | if (sc->sc_pci_ih != NULL) { |
146 | aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
147 | "using %s for native-PCI interrupt\n" , intrstr); |
148 | } else { |
149 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
150 | "couldn't establish native-PCI interrupt" ); |
151 | if (intrstr != NULL) |
152 | aprint_error(" at %s" , intrstr); |
153 | aprint_error("\n" ); |
154 | goto bad; |
155 | } |
156 | } |
157 | cp->ih = sc->sc_pci_ih; |
158 | wdr->cmd_iot = sc->sc_ba5_st; |
159 | if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh, |
160 | ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200, |
161 | &wdr->cmd_baseioh) != 0) { |
162 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
163 | "couldn't map %s channel cmd regs\n" , cp->name); |
164 | goto bad; |
165 | } |
166 | |
167 | wdr->ctl_iot = sc->sc_ba5_st; |
168 | if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, |
169 | ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) { |
170 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
171 | "couldn't map %s channel ctl regs\n" , cp->name); |
172 | goto bad; |
173 | } |
174 | wdr->ctl_ioh = cp->ctl_baseioh; |
175 | |
176 | for (i = 0; i < WDC_NREG + 2; i++) { |
177 | |
178 | if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, |
179 | artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size, |
180 | &wdr->cmd_iohs[i]) != 0) { |
181 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
182 | "couldn't subregion %s channel cmd regs\n" , |
183 | cp->name); |
184 | goto bad; |
185 | } |
186 | } |
187 | wdr->data32iot = wdr->cmd_iot; |
188 | wdr->data32ioh = wdr->cmd_iohs[0]; |
189 | |
190 | wdr->sata_iot = wdr->cmd_iot; |
191 | wdr->sata_baseioh = wdr->cmd_baseioh; |
192 | |
193 | if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, |
194 | ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR, 1, |
195 | &wdr->sata_status) != 0) { |
196 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
197 | "couldn't map channel %d sata_status regs\n" , |
198 | wdc_cp->ch_channel); |
199 | goto bad; |
200 | } |
201 | if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, |
202 | ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSER, 1, |
203 | &wdr->sata_error) != 0) { |
204 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
205 | "couldn't map channel %d sata_error regs\n" , |
206 | wdc_cp->ch_channel); |
207 | goto bad; |
208 | } |
209 | if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, |
210 | ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 1, |
211 | &wdr->sata_control) != 0) { |
212 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
213 | "couldn't map channel %d sata_control regs\n" , |
214 | wdc_cp->ch_channel); |
215 | goto bad; |
216 | } |
217 | |
218 | wdcattach(wdc_cp); |
219 | return; |
220 | |
221 | bad: |
222 | wdc_cp->ch_flags |= ATACH_DISABLED; |
223 | return; |
224 | } |
225 | |
226 | static int |
227 | artisea_chansetup(struct pciide_softc *sc, int channel, |
228 | pcireg_t interface) |
229 | { |
230 | struct pciide_channel *cp = &sc->pciide_channels[channel]; |
231 | sc->wdc_chanarray[channel] = &cp->ata_channel; |
232 | cp->name = PCIIDE_CHANNEL_NAME(channel); |
233 | cp->ata_channel.ch_channel = channel; |
234 | cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; |
235 | cp->ata_channel.ch_queue = |
236 | malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); |
237 | if (cp->ata_channel.ch_queue == NULL) { |
238 | aprint_error("%s %s channel: " |
239 | "can't allocate memory for command queue" , |
240 | device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); |
241 | return 0; |
242 | } |
243 | return 1; |
244 | } |
245 | |
246 | static void |
247 | artisea_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) |
248 | { |
249 | struct pciide_channel *pc; |
250 | int chan; |
251 | u_int32_t dma_ctl; |
252 | u_int32_t cacheline_len; |
253 | |
254 | aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
255 | "bus-master DMA support present" ); |
256 | |
257 | sc->sc_dma_ok = 1; |
258 | |
259 | /* |
260 | * Errata #4 says that if the cacheline length is not set correctly, |
261 | * we can get corrupt MWI and Memory-Block-Write transactions. |
262 | */ |
263 | cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag, |
264 | PCI_BHLC_REG)); |
265 | if (cacheline_len == 0) { |
266 | aprint_verbose(", but unused (cacheline size not set in PCI conf)\n" ); |
267 | sc->sc_dma_ok = 0; |
268 | return; |
269 | } |
270 | |
271 | /* |
272 | * Final step of the work-around is to force the DMA engine to use |
273 | * the cache-line length information. |
274 | */ |
275 | dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR); |
276 | dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE; |
277 | pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl); |
278 | |
279 | sc->sc_wdcdev.dma_arg = sc; |
280 | sc->sc_wdcdev.dma_init = pciide_dma_init; |
281 | sc->sc_wdcdev.dma_start = pciide_dma_start; |
282 | sc->sc_wdcdev.dma_finish = pciide_dma_finish; |
283 | sc->sc_dma_iot = sc->sc_ba5_st; |
284 | sc->sc_dmat = pa->pa_dmat; |
285 | |
286 | if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & |
287 | PCIIDE_OPTIONS_NODMA) { |
288 | aprint_verbose( |
289 | ", but unused (forced off by config file)\n" ); |
290 | sc->sc_dma_ok = 0; |
291 | return; |
292 | } |
293 | |
294 | /* |
295 | * Set up the default handles for the DMA registers. |
296 | * Just reserve 32 bits for each handle, unless space |
297 | * doesn't permit it. |
298 | */ |
299 | for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) { |
300 | pc = &sc->pciide_channels[chan]; |
301 | if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, |
302 | ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2, |
303 | &pc->dma_iohs[IDEDMA_CMD]) != 0 || |
304 | bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, |
305 | ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1, |
306 | &pc->dma_iohs[IDEDMA_CTL]) != 0 || |
307 | bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, |
308 | ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4, |
309 | &pc->dma_iohs[IDEDMA_TBL]) != 0) { |
310 | sc->sc_dma_ok = 0; |
311 | aprint_verbose(", but can't subregion registers\n" ); |
312 | return; |
313 | } |
314 | } |
315 | |
316 | aprint_verbose("\n" ); |
317 | } |
318 | |
319 | static void |
320 | artisea_chip_map_dpa(struct pciide_softc *sc, const struct pci_attach_args *pa) |
321 | { |
322 | struct pciide_channel *cp; |
323 | pcireg_t interface; |
324 | int channel; |
325 | |
326 | interface = PCI_INTERFACE(pa->pa_class); |
327 | |
328 | aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
329 | "interface wired in DPA mode\n" ); |
330 | |
331 | if (pci_mapreg_map(pa, ARTISEA_PCI_DPA_BASE, PCI_MAPREG_MEM_TYPE_64BIT, |
332 | 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) |
333 | return; |
334 | |
335 | artisea_mapreg_dma(sc, pa); |
336 | |
337 | sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS; |
338 | |
339 | sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; |
340 | sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; |
341 | if (sc->sc_dma_ok) { |
342 | sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; |
343 | sc->sc_wdcdev.irqack = pciide_irqack; |
344 | sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; |
345 | sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; |
346 | } |
347 | sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; |
348 | |
349 | sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; |
350 | sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN; |
351 | sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; |
352 | sc->sc_wdcdev.wdc_maxdrives = 1; |
353 | |
354 | wdc_allocate_regs(&sc->sc_wdcdev); |
355 | |
356 | /* |
357 | * Perform a quick check to ensure that the device isn't configured |
358 | * in Spread-spectrum clocking mode. This feature is buggy and has |
359 | * been removed from the latest documentation. |
360 | * |
361 | * Note that although this bit is in the Channel regs, it's the same |
362 | * for all channels, so we check it just once here. |
363 | */ |
364 | if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh, |
365 | ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF + |
366 | ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) { |
367 | aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
368 | "Spread-specturm clocking not supported by device\n" ); |
369 | return; |
370 | } |
371 | |
372 | /* Clear the LED0-only bit. */ |
373 | pci_conf_write (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0, |
374 | pci_conf_read (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0) & |
375 | ~SUECSR0_LED0_ONLY); |
376 | |
377 | for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; |
378 | channel++) { |
379 | cp = &sc->pciide_channels[channel]; |
380 | if (artisea_chansetup(sc, channel, interface) == 0) |
381 | continue; |
382 | /* XXX We can probably do interrupts more efficiently. */ |
383 | artisea_mapregs(pa, cp, pciide_pci_intr); |
384 | } |
385 | } |
386 | |
387 | static void |
388 | artisea_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) |
389 | { |
390 | struct pciide_channel *cp; |
391 | pcireg_t interface; |
392 | int channel; |
393 | |
394 | if (pciide_chipen(sc, pa) == 0) |
395 | return; |
396 | |
397 | interface = PCI_INTERFACE(pa->pa_class); |
398 | |
399 | if (interface == 0) { |
400 | artisea_chip_map_dpa (sc, pa); |
401 | return; |
402 | } |
403 | |
404 | aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, |
405 | "bus-master DMA support present" ); |
406 | #ifdef PCIIDE_I31244_DISABLEDMA |
407 | if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 && |
408 | PCI_REVISION(pa->pa_class) == 0) { |
409 | aprint_verbose(" but disabled due to rev. 0" ); |
410 | sc->sc_dma_ok = 0; |
411 | } else |
412 | #endif |
413 | pciide_mapreg_dma(sc, pa); |
414 | aprint_verbose("\n" ); |
415 | |
416 | /* |
417 | * XXX Configure LEDs to show activity. |
418 | */ |
419 | |
420 | sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; |
421 | sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; |
422 | if (sc->sc_dma_ok) { |
423 | sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; |
424 | sc->sc_wdcdev.irqack = pciide_irqack; |
425 | sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; |
426 | sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; |
427 | } |
428 | sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; |
429 | |
430 | sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; |
431 | sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; |
432 | |
433 | wdc_allocate_regs(&sc->sc_wdcdev); |
434 | |
435 | for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; |
436 | channel++) { |
437 | cp = &sc->pciide_channels[channel]; |
438 | if (pciide_chansetup(sc, channel, interface) == 0) |
439 | continue; |
440 | pciide_mapchan(pa, cp, interface, pciide_pci_intr); |
441 | } |
442 | } |
443 | |