1/* $NetBSD: nfsmb.c,v 1.24 2016/02/14 19:54:21 chs Exp $ */
2/*
3 * Copyright (c) 2007 KIYOHARA Takashi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 *
27 */
28#include <sys/cdefs.h>
29__KERNEL_RCSID(0, "$NetBSD: nfsmb.c,v 1.24 2016/02/14 19:54:21 chs Exp $");
30
31#include <sys/param.h>
32#include <sys/device.h>
33#include <sys/errno.h>
34#include <sys/kernel.h>
35#include <sys/mutex.h>
36#include <sys/proc.h>
37
38#include <sys/bus.h>
39
40#include <dev/i2c/i2cvar.h>
41
42#include <dev/pci/pcivar.h>
43#include <dev/pci/pcireg.h>
44#include <dev/pci/pcidevs.h>
45
46#include <dev/pci/nfsmbreg.h>
47
48
49struct nfsmbc_attach_args {
50 int nfsmb_num;
51 bus_space_tag_t nfsmb_iot;
52 int nfsmb_addr;
53};
54
55struct nfsmb_softc;
56struct nfsmbc_softc {
57 device_t sc_dev;
58
59 pci_chipset_tag_t sc_pc;
60 pcitag_t sc_tag;
61 struct pci_attach_args *sc_pa;
62
63 bus_space_tag_t sc_iot;
64 device_t sc_nfsmb[2];
65};
66
67struct nfsmb_softc {
68 device_t sc_dev;
69 int sc_num;
70 device_t sc_nfsmbc;
71
72 bus_space_tag_t sc_iot;
73 bus_space_handle_t sc_ioh;
74
75 struct i2c_controller sc_i2c; /* i2c controller info */
76 kmutex_t sc_mutex;
77};
78
79
80static int nfsmbc_match(device_t, cfdata_t, void *);
81static void nfsmbc_attach(device_t, device_t, void *);
82static int nfsmbc_print(void *, const char *);
83
84static int nfsmb_match(device_t, cfdata_t, void *);
85static void nfsmb_attach(device_t, device_t, void *);
86static int nfsmb_acquire_bus(void *, int);
87static void nfsmb_release_bus(void *, int);
88static int nfsmb_exec(
89 void *, i2c_op_t, i2c_addr_t, const void *, size_t, void *, size_t, int);
90static int nfsmb_check_done(struct nfsmb_softc *);
91static int
92 nfsmb_send_1(struct nfsmb_softc *, uint8_t, i2c_addr_t, i2c_op_t, int);
93static int nfsmb_write_1(
94 struct nfsmb_softc *, uint8_t, uint8_t, i2c_addr_t, i2c_op_t, int);
95static int nfsmb_write_2(
96 struct nfsmb_softc *, uint8_t, uint16_t, i2c_addr_t, i2c_op_t, int);
97static int nfsmb_receive_1(struct nfsmb_softc *, i2c_addr_t, i2c_op_t, int);
98static int
99 nfsmb_read_1(struct nfsmb_softc *, uint8_t, i2c_addr_t, i2c_op_t, int);
100static int
101 nfsmb_read_2(struct nfsmb_softc *, uint8_t, i2c_addr_t, i2c_op_t, int);
102static int
103 nfsmb_quick(struct nfsmb_softc *, i2c_addr_t, i2c_op_t, int);
104
105CFATTACH_DECL_NEW(nfsmbc, sizeof(struct nfsmbc_softc),
106 nfsmbc_match, nfsmbc_attach, NULL, NULL);
107
108static int
109nfsmbc_match(device_t parent, cfdata_t match, void *aux)
110{
111 struct pci_attach_args *pa = aux;
112
113 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NVIDIA) {
114 switch (PCI_PRODUCT(pa->pa_id)) {
115 case PCI_PRODUCT_NVIDIA_NFORCE2_SMBUS:
116 case PCI_PRODUCT_NVIDIA_NFORCE2_400_SMBUS:
117 case PCI_PRODUCT_NVIDIA_NFORCE3_SMBUS:
118 case PCI_PRODUCT_NVIDIA_NFORCE3_250_SMBUS:
119 case PCI_PRODUCT_NVIDIA_NFORCE4_SMBUS:
120 case PCI_PRODUCT_NVIDIA_NFORCE430_SMBUS:
121 case PCI_PRODUCT_NVIDIA_MCP04_SMBUS:
122 case PCI_PRODUCT_NVIDIA_MCP55_SMB:
123 case PCI_PRODUCT_NVIDIA_MCP61_SMB:
124 case PCI_PRODUCT_NVIDIA_MCP65_SMB:
125 case PCI_PRODUCT_NVIDIA_MCP67_SMB:
126 case PCI_PRODUCT_NVIDIA_MCP73_SMB:
127 case PCI_PRODUCT_NVIDIA_MCP78S_SMB:
128 case PCI_PRODUCT_NVIDIA_MCP79_SMB:
129 return 1;
130 }
131 }
132
133 return 0;
134}
135
136static void
137nfsmbc_attach(device_t parent, device_t self, void *aux)
138{
139 struct nfsmbc_softc *sc = device_private(self);
140 struct pci_attach_args *pa = aux;
141 struct nfsmbc_attach_args nfsmbca;
142 pcireg_t reg;
143 int baseregs[2];
144
145 pci_aprint_devinfo(pa, NULL);
146
147 sc->sc_dev = self;
148 sc->sc_pc = pa->pa_pc;
149 sc->sc_tag = pa->pa_tag;
150 sc->sc_pa = pa;
151 sc->sc_iot = pa->pa_iot;
152
153 nfsmbca.nfsmb_iot = sc->sc_iot;
154
155 switch (PCI_PRODUCT(pa->pa_id)) {
156 case PCI_PRODUCT_NVIDIA_NFORCE2_SMBUS:
157 case PCI_PRODUCT_NVIDIA_NFORCE2_400_SMBUS:
158 case PCI_PRODUCT_NVIDIA_NFORCE3_SMBUS:
159 case PCI_PRODUCT_NVIDIA_NFORCE3_250_SMBUS:
160 case PCI_PRODUCT_NVIDIA_NFORCE4_SMBUS:
161 baseregs[0] = NFORCE_OLD_SMB1;
162 baseregs[1] = NFORCE_OLD_SMB2;
163 break;
164 default:
165 baseregs[0] = NFORCE_SMB1;
166 baseregs[1] = NFORCE_SMB2;
167 break;
168 }
169
170 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, baseregs[0]);
171 nfsmbca.nfsmb_num = 1;
172 nfsmbca.nfsmb_addr = NFORCE_SMBBASE(reg);
173 sc->sc_nfsmb[0] = config_found(sc->sc_dev, &nfsmbca, nfsmbc_print);
174
175 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, baseregs[1]);
176 nfsmbca.nfsmb_num = 2;
177 nfsmbca.nfsmb_addr = NFORCE_SMBBASE(reg);
178 sc->sc_nfsmb[1] = config_found(sc->sc_dev, &nfsmbca, nfsmbc_print);
179
180 /* This driver is similar to an ISA bridge that doesn't
181 * need any special handling. So registering NULL handlers
182 * are sufficent. */
183 if (!pmf_device_register(self, NULL, NULL))
184 aprint_error_dev(self, "couldn't establish power handler\n");
185}
186
187static int
188nfsmbc_print(void *aux, const char *pnp)
189{
190 struct nfsmbc_attach_args *nfsmbcap = aux;
191
192 if (pnp)
193 aprint_normal("nfsmb SMBus %d at %s",
194 nfsmbcap->nfsmb_num, pnp);
195 else
196 aprint_normal(" SMBus %d", nfsmbcap->nfsmb_num);
197 return UNCONF;
198}
199
200
201CFATTACH_DECL_NEW(nfsmb, sizeof(struct nfsmb_softc),
202 nfsmb_match, nfsmb_attach, NULL, NULL);
203
204static int
205nfsmb_match(device_t parent, cfdata_t match, void *aux)
206{
207 struct nfsmbc_attach_args *nfsmbcap = aux;
208
209 if (nfsmbcap->nfsmb_num == 1 || nfsmbcap->nfsmb_num == 2)
210 return 1;
211 return 0;
212}
213
214static void
215nfsmb_attach(device_t parent, device_t self, void *aux)
216{
217 struct nfsmb_softc *sc = device_private(self);
218 struct nfsmbc_attach_args *nfsmbcap = aux;
219 struct i2cbus_attach_args iba;
220
221 aprint_naive("\n");
222 aprint_normal("\n");
223
224 sc->sc_dev = self;
225 sc->sc_nfsmbc = parent;
226 sc->sc_num = nfsmbcap->nfsmb_num;
227 sc->sc_iot = nfsmbcap->nfsmb_iot;
228
229 /* register with iic */
230 sc->sc_i2c.ic_cookie = sc;
231 sc->sc_i2c.ic_acquire_bus = nfsmb_acquire_bus;
232 sc->sc_i2c.ic_release_bus = nfsmb_release_bus;
233 sc->sc_i2c.ic_send_start = NULL;
234 sc->sc_i2c.ic_send_stop = NULL;
235 sc->sc_i2c.ic_initiate_xfer = NULL;
236 sc->sc_i2c.ic_read_byte = NULL;
237 sc->sc_i2c.ic_write_byte = NULL;
238 sc->sc_i2c.ic_exec = nfsmb_exec;
239
240 mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_NONE);
241
242 if (bus_space_map(sc->sc_iot, nfsmbcap->nfsmb_addr, NFORCE_SMBSIZE, 0,
243 &sc->sc_ioh) != 0) {
244 aprint_error_dev(self, "failed to map SMBus space\n");
245 return;
246 }
247
248 memset(&iba, 0, sizeof(iba));
249 iba.iba_type = I2C_TYPE_SMBUS;
250 iba.iba_tag = &sc->sc_i2c;
251 (void) config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print);
252
253 /* This driver is similar to an ISA bridge that doesn't
254 * need any special handling. So registering NULL handlers
255 * are sufficent. */
256 if (!pmf_device_register(self, NULL, NULL))
257 aprint_error_dev(self, "couldn't establish power handler\n");
258}
259
260static int
261nfsmb_acquire_bus(void *cookie, int flags)
262{
263 struct nfsmb_softc *sc = cookie;
264
265 mutex_enter(&sc->sc_mutex);
266 return 0;
267}
268
269static void
270nfsmb_release_bus(void *cookie, int flags)
271{
272 struct nfsmb_softc *sc = cookie;
273
274 mutex_exit(&sc->sc_mutex);
275}
276
277static int
278nfsmb_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd,
279 size_t cmdlen, void *vbuf, size_t buflen, int flags)
280{
281 struct nfsmb_softc *sc = (struct nfsmb_softc *)cookie;
282 uint8_t *p = vbuf;
283 int rv;
284
285 if ((cmdlen == 0) && (buflen == 0)) {
286 return nfsmb_quick(sc, addr, op, flags);
287 }
288
289 if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) {
290 rv = nfsmb_receive_1(sc, addr, op, flags);
291 if (rv == -1)
292 return -1;
293 *p = (uint8_t)rv;
294 return 0;
295 }
296
297 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) {
298 rv = nfsmb_read_1(sc, *(const uint8_t*)cmd, addr, op, flags);
299 if (rv == -1)
300 return -1;
301 *p = (uint8_t)rv;
302 return 0;
303 }
304
305 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 2)) {
306 rv = nfsmb_read_2(sc, *(const uint8_t*)cmd, addr, op, flags);
307 if (rv == -1)
308 return -1;
309 *(uint16_t *)p = (uint16_t)rv;
310 return 0;
311 }
312
313 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1))
314 return nfsmb_send_1(sc, *(uint8_t*)vbuf, addr, op, flags);
315
316 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1))
317 return nfsmb_write_1(sc, *(const uint8_t*)cmd, *(uint8_t*)vbuf,
318 addr, op, flags);
319
320 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 2))
321 return nfsmb_write_2(sc,
322 *(const uint8_t*)cmd, *((uint16_t *)vbuf), addr, op, flags);
323
324 return -1;
325}
326
327static int
328nfsmb_check_done(struct nfsmb_softc *sc)
329{
330 int us;
331 uint8_t stat;
332
333 us = 10 * 1000; /* XXXX: wait maximum 10 msec */
334 do {
335 delay(10);
336 us -= 10;
337 if (us <= 0)
338 return -1;
339 } while (bus_space_read_1(sc->sc_iot, sc->sc_ioh,
340 NFORCE_SMB_PROTOCOL) != 0);
341
342 stat = bus_space_read_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_STATUS);
343 if ((stat & NFORCE_SMB_STATUS_DONE) &&
344 !(stat & NFORCE_SMB_STATUS_STATUS))
345 return 0;
346 return -1;
347}
348
349/* ARGSUSED */
350static int
351nfsmb_quick(struct nfsmb_softc *sc, i2c_addr_t addr, i2c_op_t op, int flags)
352{
353 uint8_t data;
354
355 /* write smbus slave address to register */
356 data = addr << 1;
357 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_ADDRESS, data);
358
359 /* write smbus protocol to register */
360 data = I2C_OP_READ_P(op) | NFORCE_SMB_PROTOCOL_QUICK;
361 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_PROTOCOL, data);
362
363 return nfsmb_check_done(sc);
364}
365
366/* ARGSUSED */
367static int
368nfsmb_send_1(struct nfsmb_softc *sc, uint8_t val, i2c_addr_t addr, i2c_op_t op,
369 int flags)
370{
371 uint8_t data;
372
373 /* store cmd */
374 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_COMMAND, val);
375
376 /* write smbus slave address to register */
377 data = addr << 1;
378 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_ADDRESS, data);
379
380 /* write smbus protocol to register */
381 data = I2C_OP_READ_P(op) | NFORCE_SMB_PROTOCOL_BYTE;
382 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_PROTOCOL, data);
383
384 return nfsmb_check_done(sc);
385}
386
387/* ARGSUSED */
388static int
389nfsmb_write_1(struct nfsmb_softc *sc, uint8_t cmd, uint8_t val, i2c_addr_t addr,
390 i2c_op_t op, int flags)
391{
392 uint8_t data;
393
394 /* store cmd */
395 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_COMMAND, cmd);
396
397 /* store data */
398 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_DATA, val);
399
400 /* write smbus slave address to register */
401 data = addr << 1;
402 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_ADDRESS, data);
403
404 /* write smbus protocol to register */
405 data = I2C_OP_READ_P(op) | NFORCE_SMB_PROTOCOL_BYTE_DATA;
406 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_PROTOCOL, data);
407
408 return nfsmb_check_done(sc);
409}
410
411static int
412nfsmb_write_2(struct nfsmb_softc *sc, uint8_t cmd, uint16_t val,
413 i2c_addr_t addr, i2c_op_t op, int flags)
414{
415 uint8_t data, low, high;
416
417 /* store cmd */
418 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_COMMAND, cmd);
419
420 /* store data */
421 low = val;
422 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_DATA, low);
423 high = val >> 8;
424 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_DATA + 1, high);
425
426 /* write smbus slave address to register */
427 data = addr << 1;
428 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_ADDRESS, data);
429
430 /* write smbus protocol to register */
431 data = I2C_OP_READ_P(op) | NFORCE_SMB_PROTOCOL_WORD_DATA;
432 if (flags & I2C_F_PEC)
433 data |= NFORCE_SMB_PROTOCOL_PEC;
434 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_PROTOCOL, data);
435
436 return nfsmb_check_done(sc);
437}
438
439/* ARGSUSED */
440static int
441nfsmb_receive_1(struct nfsmb_softc *sc, i2c_addr_t addr, i2c_op_t op, int flags)
442{
443 uint8_t data;
444
445 /* write smbus slave address to register */
446 data = addr << 1;
447 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_ADDRESS, data);
448
449 /* write smbus protocol to register */
450 data = I2C_OP_READ_P(op) | NFORCE_SMB_PROTOCOL_BYTE;
451 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_PROTOCOL, data);
452
453 /* check for errors */
454 if (nfsmb_check_done(sc) < 0)
455 return -1;
456
457 /* read data */
458 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_DATA);
459}
460
461/* ARGSUSED */
462static int
463nfsmb_read_1(struct nfsmb_softc *sc, uint8_t cmd, i2c_addr_t addr, i2c_op_t op,
464 int flags)
465{
466 uint8_t data;
467
468 /* store cmd */
469 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_COMMAND, cmd);
470
471 /* write smbus slave address to register */
472 data = addr << 1;
473 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_ADDRESS, data);
474
475 /* write smbus protocol to register */
476 data = I2C_OP_READ_P(op) | NFORCE_SMB_PROTOCOL_BYTE_DATA;
477 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_PROTOCOL, data);
478
479 /* check for errors */
480 if (nfsmb_check_done(sc) < 0)
481 return -1;
482
483 /* read data */
484 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_DATA);
485}
486
487static int
488nfsmb_read_2(struct nfsmb_softc *sc, uint8_t cmd, i2c_addr_t addr, i2c_op_t op,
489 int flags)
490{
491 uint8_t data, low, high;
492
493 /* store cmd */
494 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_COMMAND, cmd);
495
496 /* write smbus slave address to register */
497 data = addr << 1;
498 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_ADDRESS, data);
499
500 /* write smbus protocol to register */
501 data = I2C_OP_READ_P(op) | NFORCE_SMB_PROTOCOL_WORD_DATA;
502 if (flags & I2C_F_PEC)
503 data |= NFORCE_SMB_PROTOCOL_PEC;
504 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_PROTOCOL, data);
505
506 /* check for errors */
507 if (nfsmb_check_done(sc) < 0)
508 return -1;
509
510 /* read data */
511 low = bus_space_read_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_DATA);
512 high = bus_space_read_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_DATA + 1);
513 return low | high << 8;
514}
515