1/* $NetBSD: satareg.h,v 1.5 2008/04/28 20:23:47 martin Exp $ */
2
3/*-
4 * Copyright (c) 2003 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of Wasabi Systems, Inc.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _DEV_ATA_SATAREG_H_
33#define _DEV_ATA_SATAREG_H_
34
35/*
36 * Serial ATA register definitions.
37 *
38 * Reference:
39 *
40 * Serial ATA: High Speed Serialized AT Attachment
41 * Revision 1.0 29-August-2001
42 * Serial ATA Working Group
43 */
44
45/*
46 * SStatus (SCR0) --
47 * Serial ATA interface status register
48 */
49 /*
50 * The DET value indicates the interface device detection and
51 * PHY state.
52 */
53#define SStatus_DET_NODEV (0x0 << 0) /* no device connected */
54#define SStatus_DET_DEV_NE (0x1 << 0) /* device, but PHY comm not
55 established */
56#define SStatus_DET_DEV (0x3 << 0) /* device, PHY comm
57 established */
58#define SStatus_DET_OFFLINE (0x4 << 0) /* PHY in offline mode */
59#define SStatus_DET_mask (0xf << 0)
60#define SStatus_DET_shift 0
61 /*
62 * The SPD value indicates the negotiated interface communication
63 * speed established.
64 */
65#define SStatus_SPD_NONE (0x0 << 4) /* no negotiated speed */
66#define SStatus_SPD_G1 (0x1 << 4) /* Generation 1 (1.5Gb/s) */
67#define SStatus_SPD_G2 (0x2 << 4) /* Generation 2 (3.0Gb/s) */
68#define SStatus_SPD_mask (0xf << 4)
69#define SStatus_SPD_shift 4
70 /*
71 * The IPM value indicates the current interface power managemnt
72 * state.
73 */
74#define SStatus_IPM_NODEV (0x0 << 8) /* no device connected */
75#define SStatus_IPM_ACTIVE (0x1 << 8) /* ACTIVE state */
76#define SStatus_IPM_PARTIAL (0x2 << 8) /* PARTIAL pm state */
77#define SStatus_IPM_SLUMBER (0x6 << 8) /* SLUMBER pm state */
78#define SStatus_IPM_mask (0xf << 8)
79#define SStatus_IPM_shift 8
80
81/*
82 * SError (SCR1) --
83 * Serial ATA interface error register
84 */
85#define SError_ERR_I (1U << 0) /* Recovered data integrity
86 error */
87#define SError_ERR_M (1U << 1) /* Recovered communications
88 error */
89#define SError_ERR_T (1U << 8) /* Non-recovered transient
90 data integrity error */
91#define SError_ERR_C (1U << 9) /* Non-recovered persistent
92 communication or data
93 integrity error */
94#define SError_ERR_P (1U << 10) /* Protocol error */
95#define SError_ERR_E (1U << 11) /* Internal error */
96#define SError_DIAG_N (1U << 16) /* PhyRdy change */
97#define SError_DIAG_I (1U << 17) /* PHY internal error */
98#define SError_DIAG_W (1U << 18) /* Comm Wake */
99#define SError_DIAG_B (1U << 19) /* 10b to 8b decode error */
100#define SError_DIAG_D (1U << 20) /* Disparity error */
101#define SError_DIAG_C (1U << 21) /* CRC error */
102#define SError_DIAG_H (1U << 22) /* Handshake error */
103#define SError_DIAG_S (1U << 23) /* Link sequence error */
104#define SError_DIAG_T (1U << 24) /* Transport state transition
105 error */
106#define SError_DIAG_F (1U << 25) /* Unrecognized FIS type */
107#define SError_DIAG_X (1U << 26) /* Device Exchanged */
108
109/*
110 * SControl (SCR2) --
111 * Serial ATA interface control register
112 */
113 /*
114 * The DET field controls the host adapter device detection
115 * and interface initialization.
116 */
117#define SControl_DET_NONE (0x0 << 0) /* No device detection or
118 initialization action
119 requested */
120#define SControl_DET_INIT (0x1 << 0) /* Initialize interface
121 communication (equiv
122 of a hard reset) */
123#define SControl_DET_DISABLE (0x4 << 0) /* disable interface and
124 take PHY offline */
125 /*
126 * The SPD field represents the highest allowed communication
127 * speed the interface is allowed to negotiate when communication
128 * is established.
129 */
130#define SControl_SPD_ANY (0x0 << 4) /* No restrictions */
131#define SControl_SPD_G1 (0x1 << 4) /* Generation 1 (1.5Gb/s) */
132#define SControl_SPD_G2 (0x2 << 4) /* Generation 2 (3.0Gb/s) */
133 /*
134 * The IPM field represents the enabled interface power management
135 * states that can be invoked via the Serial ATA interface power
136 * management capabilities.
137 */
138#define SControl_IPM_ANY (0x0 << 8) /* No restrictions */
139#define SControl_IPM_NOPARTIAL (0x1 << 8) /* PARTIAL disabled */
140#define SControl_IPM_NOSLUMBER (0x2 << 8) /* SLUMBER disabled */
141#define SControl_IPM_NONE (0x3 << 8) /* No power management */
142 /*
143 * The SPM field selects a power management state. A non-zero
144 * value written to this field causes initiation of the selected
145 * power management state.
146 */
147#define SControl_SPM_PARTIAL (0x1 << 12) /* transition to PARTIAL */
148#define SControl_SPM_SLUMBER (0x2 << 12) /* transition to SLUBMER */
149#define SControl_SPM_ComWake (0x4 << 12) /* transition from PM */
150 /*
151 * The PMP field identifies the selected Port Multiplier Port
152 * for accessing the SActive register.
153 */
154#define SControl_PMP(x) ((x) << 16)
155
156#endif /* _DEV_ATA_SATAREG_H_ */
157