1 | /* $NetBSD: nouveau_subdev_clock_pllnv04.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 1993-2003 NVIDIA, Corporation |
5 | * Copyright 2007-2009 Stuart Bennett |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a |
8 | * copy of this software and associated documentation files (the "Software"), |
9 | * to deal in the Software without restriction, including without limitation |
10 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
11 | * and/or sell copies of the Software, and to permit persons to whom the |
12 | * Software is furnished to do so, subject to the following conditions: |
13 | * |
14 | * The above copyright notice and this permission notice shall be included in |
15 | * all copies or substantial portions of the Software. |
16 | * |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
20 | * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
21 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
22 | * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
23 | * SOFTWARE. |
24 | */ |
25 | |
26 | #include <sys/cdefs.h> |
27 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_clock_pllnv04.c,v 1.1.1.1 2014/08/06 12:36:29 riastradh Exp $" ); |
28 | |
29 | #include <subdev/bios.h> |
30 | #include <subdev/bios/pll.h> |
31 | |
32 | #include "pll.h" |
33 | |
34 | static int |
35 | getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, |
36 | int *pN, int *pM, int *pP) |
37 | { |
38 | /* Find M, N and P for a single stage PLL |
39 | * |
40 | * Note that some bioses (NV3x) have lookup tables of precomputed MNP |
41 | * values, but we're too lazy to use those atm |
42 | * |
43 | * "clk" parameter in kHz |
44 | * returns calculated clock |
45 | */ |
46 | struct nouveau_bios *bios = nouveau_bios(subdev); |
47 | int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq; |
48 | int minM = info->vco1.min_m, maxM = info->vco1.max_m; |
49 | int minN = info->vco1.min_n, maxN = info->vco1.max_n; |
50 | int minU = info->vco1.min_inputfreq; |
51 | int maxU = info->vco1.max_inputfreq; |
52 | int minP = info->min_p; |
53 | int maxP = info->max_p_usable; |
54 | int crystal = info->refclk; |
55 | int M, N, thisP, P; |
56 | int clkP, calcclk; |
57 | int delta, bestdelta = INT_MAX; |
58 | int bestclk = 0; |
59 | |
60 | /* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */ |
61 | /* possibly correlated with introduction of 27MHz crystal */ |
62 | if (bios->version.major < 0x60) { |
63 | int cv = bios->version.chip; |
64 | if (cv < 0x17 || cv == 0x1a || cv == 0x20) { |
65 | if (clk > 250000) |
66 | maxM = 6; |
67 | if (clk > 340000) |
68 | maxM = 2; |
69 | } else if (cv < 0x40) { |
70 | if (clk > 150000) |
71 | maxM = 6; |
72 | if (clk > 200000) |
73 | maxM = 4; |
74 | if (clk > 340000) |
75 | maxM = 2; |
76 | } |
77 | } |
78 | |
79 | P = 1 << maxP; |
80 | if ((clk * P) < minvco) { |
81 | minvco = clk * maxP; |
82 | maxvco = minvco * 2; |
83 | } |
84 | |
85 | if (clk + clk/200 > maxvco) /* +0.5% */ |
86 | maxvco = clk + clk/200; |
87 | |
88 | /* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */ |
89 | for (thisP = minP; thisP <= maxP; thisP++) { |
90 | P = 1 << thisP; |
91 | clkP = clk * P; |
92 | |
93 | if (clkP < minvco) |
94 | continue; |
95 | if (clkP > maxvco) |
96 | return bestclk; |
97 | |
98 | for (M = minM; M <= maxM; M++) { |
99 | if (crystal/M < minU) |
100 | return bestclk; |
101 | if (crystal/M > maxU) |
102 | continue; |
103 | |
104 | /* add crystal/2 to round better */ |
105 | N = (clkP * M + crystal/2) / crystal; |
106 | |
107 | if (N < minN) |
108 | continue; |
109 | if (N > maxN) |
110 | break; |
111 | |
112 | /* more rounding additions */ |
113 | calcclk = ((N * crystal + P/2) / P + M/2) / M; |
114 | delta = abs(calcclk - clk); |
115 | /* we do an exhaustive search rather than terminating |
116 | * on an optimality condition... |
117 | */ |
118 | if (delta < bestdelta) { |
119 | bestdelta = delta; |
120 | bestclk = calcclk; |
121 | *pN = N; |
122 | *pM = M; |
123 | *pP = thisP; |
124 | if (delta == 0) /* except this one */ |
125 | return bestclk; |
126 | } |
127 | } |
128 | } |
129 | |
130 | return bestclk; |
131 | } |
132 | |
133 | static int |
134 | getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, |
135 | int *pN1, int *pM1, int *pN2, int *pM2, int *pP) |
136 | { |
137 | /* Find M, N and P for a two stage PLL |
138 | * |
139 | * Note that some bioses (NV30+) have lookup tables of precomputed MNP |
140 | * values, but we're too lazy to use those atm |
141 | * |
142 | * "clk" parameter in kHz |
143 | * returns calculated clock |
144 | */ |
145 | int chip_version = nouveau_bios(subdev)->version.chip; |
146 | int minvco1 = info->vco1.min_freq, maxvco1 = info->vco1.max_freq; |
147 | int minvco2 = info->vco2.min_freq, maxvco2 = info->vco2.max_freq; |
148 | int minU1 = info->vco1.min_inputfreq, minU2 = info->vco2.min_inputfreq; |
149 | int maxU1 = info->vco1.max_inputfreq, maxU2 = info->vco2.max_inputfreq; |
150 | int minM1 = info->vco1.min_m, maxM1 = info->vco1.max_m; |
151 | int minN1 = info->vco1.min_n, maxN1 = info->vco1.max_n; |
152 | int minM2 = info->vco2.min_m, maxM2 = info->vco2.max_m; |
153 | int minN2 = info->vco2.min_n, maxN2 = info->vco2.max_n; |
154 | int maxlog2P = info->max_p_usable; |
155 | int crystal = info->refclk; |
156 | bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2); |
157 | int M1, N1, M2, N2, log2P; |
158 | int clkP, calcclk1, calcclk2, calcclkout; |
159 | int delta, bestdelta = INT_MAX; |
160 | int bestclk = 0; |
161 | |
162 | int vco2 = (maxvco2 - maxvco2/200) / 2; |
163 | for (log2P = 0; clk && log2P < maxlog2P && clk <= (vco2 >> log2P); log2P++) |
164 | ; |
165 | clkP = clk << log2P; |
166 | |
167 | if (maxvco2 < clk + clk/200) /* +0.5% */ |
168 | maxvco2 = clk + clk/200; |
169 | |
170 | for (M1 = minM1; M1 <= maxM1; M1++) { |
171 | if (crystal/M1 < minU1) |
172 | return bestclk; |
173 | if (crystal/M1 > maxU1) |
174 | continue; |
175 | |
176 | for (N1 = minN1; N1 <= maxN1; N1++) { |
177 | calcclk1 = crystal * N1 / M1; |
178 | if (calcclk1 < minvco1) |
179 | continue; |
180 | if (calcclk1 > maxvco1) |
181 | break; |
182 | |
183 | for (M2 = minM2; M2 <= maxM2; M2++) { |
184 | if (calcclk1/M2 < minU2) |
185 | break; |
186 | if (calcclk1/M2 > maxU2) |
187 | continue; |
188 | |
189 | /* add calcclk1/2 to round better */ |
190 | N2 = (clkP * M2 + calcclk1/2) / calcclk1; |
191 | if (N2 < minN2) |
192 | continue; |
193 | if (N2 > maxN2) |
194 | break; |
195 | |
196 | if (!fixedgain2) { |
197 | if (chip_version < 0x60) |
198 | if (N2/M2 < 4 || N2/M2 > 10) |
199 | continue; |
200 | |
201 | calcclk2 = calcclk1 * N2 / M2; |
202 | if (calcclk2 < minvco2) |
203 | break; |
204 | if (calcclk2 > maxvco2) |
205 | continue; |
206 | } else |
207 | calcclk2 = calcclk1; |
208 | |
209 | calcclkout = calcclk2 >> log2P; |
210 | delta = abs(calcclkout - clk); |
211 | /* we do an exhaustive search rather than terminating |
212 | * on an optimality condition... |
213 | */ |
214 | if (delta < bestdelta) { |
215 | bestdelta = delta; |
216 | bestclk = calcclkout; |
217 | *pN1 = N1; |
218 | *pM1 = M1; |
219 | *pN2 = N2; |
220 | *pM2 = M2; |
221 | *pP = log2P; |
222 | if (delta == 0) /* except this one */ |
223 | return bestclk; |
224 | } |
225 | } |
226 | } |
227 | } |
228 | |
229 | return bestclk; |
230 | } |
231 | |
232 | int |
233 | nv04_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, u32 freq, |
234 | int *N1, int *M1, int *N2, int *M2, int *P) |
235 | { |
236 | int ret; |
237 | |
238 | if (!info->vco2.max_freq || !N2) { |
239 | ret = getMNP_single(subdev, info, freq, N1, M1, P); |
240 | if (N2) { |
241 | *N2 = 1; |
242 | *M2 = 1; |
243 | } |
244 | } else { |
245 | ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P); |
246 | } |
247 | |
248 | if (!ret) |
249 | nv_error(subdev, "unable to compute acceptable pll values\n" ); |
250 | return ret; |
251 | } |
252 | |