1 | /* $NetBSD: if_run.c,v 1.20 2016/10/01 11:09:12 mlelstv Exp $ */ |
2 | /* $OpenBSD: if_run.c,v 1.90 2012/03/24 15:11:04 jsg Exp $ */ |
3 | |
4 | /*- |
5 | * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini@free.fr> |
6 | * |
7 | * Permission to use, copy, modify, and distribute this software for any |
8 | * purpose with or without fee is hereby granted, provided that the above |
9 | * copyright notice and this permission notice appear in all copies. |
10 | * |
11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
18 | */ |
19 | |
20 | /*- |
21 | * Ralink Technology RT2700U/RT2800U/RT3000U chipset driver. |
22 | * http://www.ralinktech.com/ |
23 | */ |
24 | |
25 | #include <sys/cdefs.h> |
26 | __KERNEL_RCSID(0, "$NetBSD: if_run.c,v 1.20 2016/10/01 11:09:12 mlelstv Exp $" ); |
27 | |
28 | #include <sys/param.h> |
29 | #include <sys/sockio.h> |
30 | #include <sys/sysctl.h> |
31 | #include <sys/mbuf.h> |
32 | #include <sys/kernel.h> |
33 | #include <sys/socket.h> |
34 | #include <sys/systm.h> |
35 | #include <sys/malloc.h> |
36 | #include <sys/callout.h> |
37 | #include <sys/module.h> |
38 | #include <sys/conf.h> |
39 | #include <sys/device.h> |
40 | |
41 | #include <sys/bus.h> |
42 | #include <machine/endian.h> |
43 | #include <sys/intr.h> |
44 | |
45 | #include <net/bpf.h> |
46 | #include <net/if.h> |
47 | #include <net/if_arp.h> |
48 | #include <net/if_dl.h> |
49 | #include <net/if_ether.h> |
50 | #include <net/if_media.h> |
51 | #include <net/if_types.h> |
52 | |
53 | #include <net80211/ieee80211_var.h> |
54 | #include <net80211/ieee80211_amrr.h> |
55 | #include <net80211/ieee80211_radiotap.h> |
56 | |
57 | #include <dev/firmload.h> |
58 | |
59 | #include <dev/usb/usb.h> |
60 | #include <dev/usb/usbdi.h> |
61 | #include <dev/usb/usbdivar.h> |
62 | #include <dev/usb/usbdi_util.h> |
63 | #include <dev/usb/usbdevs.h> |
64 | |
65 | #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ |
66 | #include <dev/usb/if_runvar.h> |
67 | |
68 | #ifdef RUN_DEBUG |
69 | #define DPRINTF(x) do { if (run_debug) printf x; } while (0) |
70 | #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) |
71 | int run_debug = 0; |
72 | #else |
73 | #define DPRINTF(x) |
74 | #define DPRINTFN(n, x) |
75 | #endif |
76 | |
77 | #define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) |
78 | |
79 | #define USB_ID(v, p) { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } |
80 | static const struct usb_devno run_devs[] = { |
81 | USB_ID(ABOCOM, RT2770), |
82 | USB_ID(ABOCOM, RT2870), |
83 | USB_ID(ABOCOM, RT3070), |
84 | USB_ID(ABOCOM, RT3071), |
85 | USB_ID(ABOCOM, RT3072), |
86 | USB_ID(ABOCOM2, RT2870_1), |
87 | USB_ID(ACCTON, RT2770), |
88 | USB_ID(ACCTON, RT2870_1), |
89 | USB_ID(ACCTON, RT2870_2), |
90 | USB_ID(ACCTON, RT2870_3), |
91 | USB_ID(ACCTON, RT2870_4), |
92 | USB_ID(ACCTON, RT2870_5), |
93 | USB_ID(ACCTON, RT3070), |
94 | USB_ID(ACCTON, RT3070_1), |
95 | USB_ID(ACCTON, RT3070_2), |
96 | USB_ID(ACCTON, RT3070_3), |
97 | USB_ID(ACCTON, RT3070_4), |
98 | USB_ID(ACCTON, RT3070_5), |
99 | USB_ID(ACCTON, RT3070_6), |
100 | USB_ID(AIRTIES, RT3070), |
101 | USB_ID(AIRTIES, RT3070_2), |
102 | USB_ID(ALLWIN, RT2070), |
103 | USB_ID(ALLWIN, RT2770), |
104 | USB_ID(ALLWIN, RT2870), |
105 | USB_ID(ALLWIN, RT3070), |
106 | USB_ID(ALLWIN, RT3071), |
107 | USB_ID(ALLWIN, RT3072), |
108 | USB_ID(ALLWIN, RT3572), |
109 | USB_ID(AMIGO, RT2870_1), |
110 | USB_ID(AMIGO, RT2870_2), |
111 | USB_ID(AMIT, CGWLUSB2GNR), |
112 | USB_ID(AMIT, RT2870_1), |
113 | USB_ID(AMIT2, RT2870), |
114 | USB_ID(ASUSTEK, RT2870_1), |
115 | USB_ID(ASUSTEK, RT2870_2), |
116 | USB_ID(ASUSTEK, RT2870_3), |
117 | USB_ID(ASUSTEK, RT2870_4), |
118 | USB_ID(ASUSTEK, RT2870_5), |
119 | USB_ID(ASUSTEK, RT3070), |
120 | USB_ID(ASUSTEK, RT3070_1), |
121 | USB_ID(ASUSTEK2, USBN11), |
122 | USB_ID(AZUREWAVE, RT2870_1), |
123 | USB_ID(AZUREWAVE, RT2870_2), |
124 | USB_ID(AZUREWAVE, RT3070), |
125 | USB_ID(AZUREWAVE, RT3070_2), |
126 | USB_ID(AZUREWAVE, RT3070_3), |
127 | USB_ID(AZUREWAVE, RT3070_4), |
128 | USB_ID(AZUREWAVE, RT3070_5), |
129 | USB_ID(BELKIN, F5D8053V3), |
130 | USB_ID(BELKIN, F5D8055), |
131 | USB_ID(BELKIN, F5D8055V2), |
132 | USB_ID(BELKIN, F6D4050V1), |
133 | USB_ID(BELKIN, F6D4050V2), |
134 | USB_ID(BELKIN, F7D1101V2), |
135 | USB_ID(BELKIN, RT2870_1), |
136 | USB_ID(BELKIN, RT2870_2), |
137 | USB_ID(BEWAN, RT3070), |
138 | USB_ID(CISCOLINKSYS, AE1000), |
139 | USB_ID(CISCOLINKSYS, AM10), |
140 | USB_ID(CISCOLINKSYS2, RT3070), |
141 | USB_ID(CISCOLINKSYS3, RT3070), |
142 | USB_ID(CONCEPTRONIC, RT2870_1), |
143 | USB_ID(CONCEPTRONIC, RT2870_2), |
144 | USB_ID(CONCEPTRONIC, RT2870_3), |
145 | USB_ID(CONCEPTRONIC, RT2870_4), |
146 | USB_ID(CONCEPTRONIC, RT2870_5), |
147 | USB_ID(CONCEPTRONIC, RT2870_6), |
148 | USB_ID(CONCEPTRONIC, RT2870_7), |
149 | USB_ID(CONCEPTRONIC, RT2870_8), |
150 | USB_ID(CONCEPTRONIC, RT3070_1), |
151 | USB_ID(CONCEPTRONIC, RT3070_2), |
152 | USB_ID(CONCEPTRONIC, RT3070_3), |
153 | USB_ID(COREGA, CGWLUSB300GNM), |
154 | USB_ID(COREGA, RT2870_1), |
155 | USB_ID(COREGA, RT2870_2), |
156 | USB_ID(COREGA, RT2870_3), |
157 | USB_ID(COREGA, RT3070), |
158 | USB_ID(CYBERTAN, RT2870), |
159 | USB_ID(DLINK, RT2870), |
160 | USB_ID(DLINK, RT3072), |
161 | USB_ID(DLINK2, DWA130), |
162 | USB_ID(DLINK2, RT2870_1), |
163 | USB_ID(DLINK2, RT2870_2), |
164 | USB_ID(DLINK2, RT3070_1), |
165 | USB_ID(DLINK2, RT3070_2), |
166 | USB_ID(DLINK2, RT3070_3), |
167 | USB_ID(DLINK2, RT3070_4), |
168 | USB_ID(DLINK2, RT3070_5), |
169 | USB_ID(DLINK2, RT3072), |
170 | USB_ID(DLINK2, RT3072_1), |
171 | USB_ID(DVICO, RT3070), |
172 | USB_ID(EDIMAX, EW7717), |
173 | USB_ID(EDIMAX, EW7718), |
174 | USB_ID(EDIMAX, EW7722UTN), |
175 | USB_ID(EDIMAX, RT2870_1), |
176 | USB_ID(ENCORE, RT3070), |
177 | USB_ID(ENCORE, RT3070_2), |
178 | USB_ID(ENCORE, RT3070_3), |
179 | USB_ID(GIGABYTE, GNWB31N), |
180 | USB_ID(GIGABYTE, GNWB32L), |
181 | USB_ID(GIGABYTE, RT2870_1), |
182 | USB_ID(GIGASET, RT3070_1), |
183 | USB_ID(GIGASET, RT3070_2), |
184 | USB_ID(GUILLEMOT, HWNU300), |
185 | USB_ID(HAWKING, HWUN2), |
186 | USB_ID(HAWKING, RT2870_1), |
187 | USB_ID(HAWKING, RT2870_2), |
188 | USB_ID(HAWKING, RT2870_3), |
189 | USB_ID(HAWKING, RT2870_4), |
190 | USB_ID(HAWKING, RT2870_5), |
191 | USB_ID(HAWKING, RT3070), |
192 | USB_ID(IODATA, RT3072_1), |
193 | USB_ID(IODATA, RT3072_2), |
194 | USB_ID(IODATA, RT3072_3), |
195 | USB_ID(IODATA, RT3072_4), |
196 | USB_ID(LINKSYS4, RT3070), |
197 | USB_ID(LINKSYS4, WUSB100), |
198 | USB_ID(LINKSYS4, WUSB54GC_3), |
199 | USB_ID(LINKSYS4, WUSB600N), |
200 | USB_ID(LINKSYS4, WUSB600NV2), |
201 | USB_ID(LOGITEC, LANW300NU2), |
202 | USB_ID(LOGITEC, RT2870_1), |
203 | USB_ID(LOGITEC, RT2870_2), |
204 | USB_ID(LOGITEC, RT2870_3), |
205 | USB_ID(LOGITEC, RT3020), |
206 | USB_ID(MELCO, RT2870_1), |
207 | USB_ID(MELCO, RT2870_2), |
208 | USB_ID(MELCO, WLIUCAG300N), |
209 | USB_ID(MELCO, WLIUCG300N), |
210 | USB_ID(MELCO, WLIUCG301N), |
211 | USB_ID(MELCO, WLIUCGN), |
212 | USB_ID(MELCO, WLIUCGNHP), |
213 | USB_ID(MELCO, WLIUCGNM), |
214 | USB_ID(MELCO, WLIUCGNM2T), |
215 | USB_ID(MOTOROLA4, RT2770), |
216 | USB_ID(MOTOROLA4, RT3070), |
217 | USB_ID(MSI, RT3070), |
218 | USB_ID(MSI, RT3070_2), |
219 | USB_ID(MSI, RT3070_3), |
220 | USB_ID(MSI, RT3070_4), |
221 | USB_ID(MSI, RT3070_5), |
222 | USB_ID(MSI, RT3070_6), |
223 | USB_ID(MSI, RT3070_7), |
224 | USB_ID(MSI, RT3070_8), |
225 | USB_ID(MSI, RT3070_9), |
226 | USB_ID(MSI, RT3070_10), |
227 | USB_ID(MSI, RT3070_11), |
228 | USB_ID(MSI, RT3070_12), |
229 | USB_ID(MSI, RT3070_13), |
230 | USB_ID(MSI, RT3070_14), |
231 | USB_ID(MSI, RT3070_15), |
232 | USB_ID(OVISLINK, RT3071), |
233 | USB_ID(OVISLINK, RT3072), |
234 | USB_ID(PARA, RT3070), |
235 | USB_ID(PEGATRON, RT2870), |
236 | USB_ID(PEGATRON, RT3070), |
237 | USB_ID(PEGATRON, RT3070_2), |
238 | USB_ID(PEGATRON, RT3070_3), |
239 | USB_ID(PEGATRON, RT3072), |
240 | USB_ID(PHILIPS, RT2870), |
241 | USB_ID(PLANEX2, GWUS300MINIS), |
242 | USB_ID(PLANEX2, GWUSMICRO300), |
243 | USB_ID(PLANEX2, GWUSMICRON), |
244 | USB_ID(PLANEX2, GWUS300MINIX), |
245 | USB_ID(PLANEX2, RT3070), |
246 | USB_ID(QCOM, RT2870), |
247 | USB_ID(QUANTA, RT3070), |
248 | USB_ID(RALINK, RT2070), |
249 | USB_ID(RALINK, RT2770), |
250 | USB_ID(RALINK, RT2870), |
251 | USB_ID(RALINK, RT3070), |
252 | USB_ID(RALINK, RT3071), |
253 | USB_ID(RALINK, RT3072), |
254 | USB_ID(RALINK, RT3370), |
255 | USB_ID(RALINK, RT3572), |
256 | USB_ID(RALINK, RT5572), |
257 | USB_ID(RALINK, RT8070), |
258 | USB_ID(SAMSUNG, RT2870_1), |
259 | USB_ID(SENAO, RT2870_1), |
260 | USB_ID(SENAO, RT2870_2), |
261 | USB_ID(SENAO, RT2870_3), |
262 | USB_ID(SENAO, RT2870_4), |
263 | USB_ID(SENAO, RT3070), |
264 | USB_ID(SENAO, RT3071), |
265 | USB_ID(SENAO, RT3072), |
266 | USB_ID(SENAO, RT3072_2), |
267 | USB_ID(SENAO, RT3072_3), |
268 | USB_ID(SENAO, RT3072_4), |
269 | USB_ID(SENAO, RT3072_5), |
270 | USB_ID(SITECOMEU, RT2870_1), |
271 | USB_ID(SITECOMEU, RT2870_2), |
272 | USB_ID(SITECOMEU, RT2870_3), |
273 | USB_ID(SITECOMEU, RT3070_1), |
274 | USB_ID(SITECOMEU, RT3072_3), |
275 | USB_ID(SITECOMEU, RT3072_4), |
276 | USB_ID(SITECOMEU, RT3072_5), |
277 | USB_ID(SITECOMEU, WL302), |
278 | USB_ID(SITECOMEU, WL315), |
279 | USB_ID(SITECOMEU, WL321), |
280 | USB_ID(SITECOMEU, WL324), |
281 | USB_ID(SITECOMEU, WL329), |
282 | USB_ID(SITECOMEU, WL343), |
283 | USB_ID(SITECOMEU, WL344), |
284 | USB_ID(SITECOMEU, WL345), |
285 | USB_ID(SITECOMEU, WL349V4), |
286 | USB_ID(SITECOMEU, WL608), |
287 | USB_ID(SITECOMEU, WLA4000), |
288 | USB_ID(SITECOMEU, WLA5000), |
289 | USB_ID(SPARKLAN, RT2870_1), |
290 | USB_ID(SPARKLAN, RT2870_2), |
291 | USB_ID(SPARKLAN, RT3070), |
292 | USB_ID(SWEEX2, LW153), |
293 | USB_ID(SWEEX2, LW303), |
294 | USB_ID(SWEEX2, LW313), |
295 | USB_ID(TOSHIBA, RT3070), |
296 | USB_ID(UMEDIA, RT2870_1), |
297 | USB_ID(UMEDIA, TEW645UB), |
298 | USB_ID(ZCOM, RT2870_1), |
299 | USB_ID(ZCOM, RT2870_2), |
300 | USB_ID(ZINWELL, RT2870_1), |
301 | USB_ID(ZINWELL, RT2870_2), |
302 | USB_ID(ZINWELL, RT3070), |
303 | USB_ID(ZINWELL, RT3072), |
304 | USB_ID(ZINWELL, RT3072_2), |
305 | USB_ID(ZYXEL, NWD2105), |
306 | USB_ID(ZYXEL, NWD211AN), |
307 | USB_ID(ZYXEL, RT2870_1), |
308 | USB_ID(ZYXEL, RT2870_2), |
309 | USB_ID(ZYXEL, RT3070), |
310 | }; |
311 | |
312 | static int run_match(device_t, cfdata_t, void *); |
313 | static void run_attach(device_t, device_t, void *); |
314 | static int run_detach(device_t, int); |
315 | static int run_activate(device_t, enum devact); |
316 | |
317 | CFATTACH_DECL_NEW(run, sizeof(struct run_softc), |
318 | run_match, run_attach, run_detach, run_activate); |
319 | |
320 | static int run_alloc_rx_ring(struct run_softc *); |
321 | static void run_free_rx_ring(struct run_softc *); |
322 | static int run_alloc_tx_ring(struct run_softc *, int); |
323 | static void run_free_tx_ring(struct run_softc *, int); |
324 | static int run_load_microcode(struct run_softc *); |
325 | static int run_reset(struct run_softc *); |
326 | static int run_read(struct run_softc *, uint16_t, uint32_t *); |
327 | static int run_read_region_1(struct run_softc *, uint16_t, |
328 | uint8_t *, int); |
329 | static int run_write_2(struct run_softc *, uint16_t, uint16_t); |
330 | static int run_write(struct run_softc *, uint16_t, uint32_t); |
331 | static int run_write_region_1(struct run_softc *, uint16_t, |
332 | const uint8_t *, int); |
333 | static int run_set_region_4(struct run_softc *, uint16_t, |
334 | uint32_t, int); |
335 | static int run_efuse_read(struct run_softc *, uint16_t, |
336 | uint16_t *, int); |
337 | static int run_efuse_read_2(struct run_softc *, uint16_t, |
338 | uint16_t *); |
339 | static int run_eeprom_read_2(struct run_softc *, uint16_t, |
340 | uint16_t *); |
341 | static int run_rt2870_rf_write(struct run_softc *, uint8_t, |
342 | uint32_t); |
343 | static int run_rt3070_rf_read(struct run_softc *, uint8_t, |
344 | uint8_t *); |
345 | static int run_rt3070_rf_write(struct run_softc *, uint8_t, |
346 | uint8_t); |
347 | static int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); |
348 | static int run_bbp_write(struct run_softc *, uint8_t, uint8_t); |
349 | static int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); |
350 | static const char * run_get_rf(int); |
351 | static void run_rt3593_get_txpower(struct run_softc *); |
352 | static void run_get_txpower(struct run_softc *); |
353 | static int run_read_eeprom(struct run_softc *); |
354 | static struct ieee80211_node * |
355 | run_node_alloc(struct ieee80211_node_table *); |
356 | static int run_media_change(struct ifnet *); |
357 | static void run_next_scan(void *); |
358 | static void run_task(void *); |
359 | static void run_do_async(struct run_softc *, |
360 | void (*)(struct run_softc *, void *), void *, int); |
361 | static int run_newstate(struct ieee80211com *, |
362 | enum ieee80211_state, int); |
363 | static void run_newstate_cb(struct run_softc *, void *); |
364 | static int run_updateedca(struct ieee80211com *); |
365 | static void run_updateedca_cb(struct run_softc *, void *); |
366 | #ifdef RUN_HWCRYPTO |
367 | static int run_set_key(struct ieee80211com *, |
368 | const struct ieee80211_key *, const uint8_t *); |
369 | static void run_set_key_cb(struct run_softc *, void *); |
370 | static int run_delete_key(struct ieee80211com *, |
371 | const struct ieee80211_key *); |
372 | static void run_delete_key_cb(struct run_softc *, void *); |
373 | #endif |
374 | static void run_calibrate_to(void *); |
375 | static void run_calibrate_cb(struct run_softc *, void *); |
376 | static void run_newassoc(struct ieee80211_node *, int); |
377 | static void run_rx_frame(struct run_softc *, uint8_t *, int); |
378 | static void run_rxeof(struct usbd_xfer *, void *, |
379 | usbd_status); |
380 | static void run_txeof(struct usbd_xfer *, void *, |
381 | usbd_status); |
382 | static int run_tx(struct run_softc *, struct mbuf *, |
383 | struct ieee80211_node *); |
384 | static void run_start(struct ifnet *); |
385 | static void run_watchdog(struct ifnet *); |
386 | static int run_ioctl(struct ifnet *, u_long, void *); |
387 | static void run_select_chan_group(struct run_softc *, int); |
388 | static void run_iq_calib(struct run_softc *, u_int); |
389 | static void run_set_agc(struct run_softc *, uint8_t); |
390 | static void run_set_rx_antenna(struct run_softc *, int); |
391 | static void run_rt2870_set_chan(struct run_softc *, u_int); |
392 | static void run_rt3070_set_chan(struct run_softc *, u_int); |
393 | static void run_rt3572_set_chan(struct run_softc *, u_int); |
394 | static void run_rt3593_set_chan(struct run_softc *, u_int); |
395 | static void run_rt5390_set_chan(struct run_softc *, u_int); |
396 | static void run_rt5592_set_chan(struct run_softc *, u_int); |
397 | static int run_set_chan(struct run_softc *, |
398 | struct ieee80211_channel *); |
399 | static void run_updateprot(struct run_softc *); |
400 | static void run_enable_tsf_sync(struct run_softc *); |
401 | static void run_enable_mrr(struct run_softc *); |
402 | static void run_set_txpreamble(struct run_softc *); |
403 | static void run_set_basicrates(struct run_softc *); |
404 | static void run_set_leds(struct run_softc *, uint16_t); |
405 | static void run_set_bssid(struct run_softc *, const uint8_t *); |
406 | static void run_set_macaddr(struct run_softc *, const uint8_t *); |
407 | static void run_updateslot(struct ifnet *); |
408 | static void run_updateslot_cb(struct run_softc *, void *); |
409 | static int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); |
410 | static void run_rt5390_bbp_init(struct run_softc *); |
411 | static int run_bbp_init(struct run_softc *); |
412 | static int run_rt3070_rf_init(struct run_softc *); |
413 | static int run_rt3593_rf_init(struct run_softc *); |
414 | static int run_rt5390_rf_init(struct run_softc *); |
415 | static int run_rt3070_filter_calib(struct run_softc *, uint8_t, |
416 | uint8_t, uint8_t *); |
417 | static void run_rt3070_rf_setup(struct run_softc *); |
418 | static void run_rt3593_rf_setup(struct run_softc *); |
419 | static void run_rt5390_rf_setup(struct run_softc *); |
420 | static int run_txrx_enable(struct run_softc *); |
421 | static int run_adjust_freq_offset(struct run_softc *); |
422 | static int run_init(struct ifnet *); |
423 | static void run_stop(struct ifnet *, int); |
424 | #ifndef IEEE80211_STA_ONLY |
425 | static int run_setup_beacon(struct run_softc *); |
426 | #endif |
427 | |
428 | static const struct { |
429 | uint32_t reg; |
430 | uint32_t val; |
431 | } rt2870_def_mac[] = { |
432 | RT2870_DEF_MAC |
433 | }; |
434 | |
435 | static const struct { |
436 | uint8_t reg; |
437 | uint8_t val; |
438 | } rt2860_def_bbp[] = { |
439 | RT2860_DEF_BBP |
440 | }, rt5390_def_bbp[] = { |
441 | RT5390_DEF_BBP |
442 | }, rt5592_def_bbp[] = { |
443 | RT5592_DEF_BBP |
444 | }; |
445 | |
446 | /* |
447 | * Default values for BBP register R196 for RT5592. |
448 | */ |
449 | static const uint8_t rt5592_bbp_r196[] = { |
450 | 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, |
451 | 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, |
452 | 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, |
453 | 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, |
454 | 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, |
455 | 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, |
456 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
457 | 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, |
458 | 0x2e, 0x36, 0x30, 0x6e |
459 | }; |
460 | |
461 | static const struct rfprog { |
462 | uint8_t chan; |
463 | uint32_t r1, r2, r3, r4; |
464 | } rt2860_rf2850[] = { |
465 | RT2860_RF2850 |
466 | }; |
467 | |
468 | static const struct { |
469 | uint8_t n, r, k; |
470 | } rt3070_freqs[] = { |
471 | RT3070_RF3052 |
472 | }; |
473 | |
474 | static const struct rt5592_freqs { |
475 | uint16_t n; |
476 | uint8_t k, m, r; |
477 | } rt5592_freqs_20mhz[] = { |
478 | RT5592_RF5592_20MHZ |
479 | },rt5592_freqs_40mhz[] = { |
480 | RT5592_RF5592_40MHZ |
481 | }; |
482 | |
483 | static const struct { |
484 | uint8_t reg; |
485 | uint8_t val; |
486 | } rt3070_def_rf[] = { |
487 | RT3070_DEF_RF |
488 | }, rt3572_def_rf[] = { |
489 | RT3572_DEF_RF |
490 | },rt3593_def_rf[] = { |
491 | RT3593_DEF_RF |
492 | },rt5390_def_rf[] = { |
493 | RT5390_DEF_RF |
494 | },rt5392_def_rf[] = { |
495 | RT5392_DEF_RF |
496 | },rt5592_def_rf[] = { |
497 | RT5592_DEF_RF |
498 | },rt5592_2ghz_def_rf[] = { |
499 | RT5592_2GHZ_DEF_RF |
500 | },rt5592_5ghz_def_rf[] = { |
501 | RT5592_5GHZ_DEF_RF |
502 | }; |
503 | |
504 | static const struct { |
505 | u_int firstchan; |
506 | u_int lastchan; |
507 | uint8_t reg; |
508 | uint8_t val; |
509 | } rt5592_chan_5ghz[] = { |
510 | RT5592_CHAN_5GHZ |
511 | }; |
512 | |
513 | static int |
514 | firmware_load(const char *dname, const char *iname, uint8_t **ucodep, |
515 | size_t *sizep) |
516 | { |
517 | firmware_handle_t fh; |
518 | int error; |
519 | |
520 | if ((error = firmware_open(dname, iname, &fh)) != 0) |
521 | return error; |
522 | *sizep = firmware_get_size(fh); |
523 | if ((*ucodep = firmware_malloc(*sizep)) == NULL) { |
524 | firmware_close(fh); |
525 | return ENOMEM; |
526 | } |
527 | if ((error = firmware_read(fh, 0, *ucodep, *sizep)) != 0) |
528 | firmware_free(*ucodep, *sizep); |
529 | firmware_close(fh); |
530 | |
531 | return error; |
532 | } |
533 | |
534 | static int |
535 | run_match(device_t parent, cfdata_t match, void *aux) |
536 | { |
537 | struct usb_attach_arg *uaa = aux; |
538 | |
539 | return (usb_lookup(run_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL) ? |
540 | UMATCH_VENDOR_PRODUCT : UMATCH_NONE; |
541 | } |
542 | |
543 | static void |
544 | run_attach(device_t parent, device_t self, void *aux) |
545 | { |
546 | struct run_softc *sc = device_private(self); |
547 | struct usb_attach_arg *uaa = aux; |
548 | struct ieee80211com *ic = &sc->sc_ic; |
549 | struct ifnet *ifp = &sc->sc_if; |
550 | usb_interface_descriptor_t *id; |
551 | usb_endpoint_descriptor_t *ed; |
552 | char *devinfop; |
553 | int i, nrx, ntx, ntries, error; |
554 | uint32_t ver; |
555 | |
556 | aprint_naive("\n" ); |
557 | aprint_normal("\n" ); |
558 | |
559 | sc->sc_dev = self; |
560 | sc->sc_udev = uaa->uaa_device; |
561 | |
562 | devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); |
563 | aprint_normal_dev(sc->sc_dev, "%s\n" , devinfop); |
564 | usbd_devinfo_free(devinfop); |
565 | |
566 | error = usbd_set_config_no(sc->sc_udev, 1, 0); |
567 | if (error != 0) { |
568 | aprint_error_dev(sc->sc_dev, "failed to set configuration" |
569 | ", err=%s\n" , usbd_errstr(error)); |
570 | return; |
571 | } |
572 | |
573 | /* get the first interface handle */ |
574 | error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); |
575 | if (error != 0) { |
576 | aprint_error_dev(sc->sc_dev, |
577 | "could not get interface handle\n" ); |
578 | return; |
579 | } |
580 | |
581 | /* |
582 | * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX |
583 | * and 6 for TX (4 EDCAs + HCCA + Prio). |
584 | * Update 03-14-2009: some devices like the Planex GW-US300MiniS |
585 | * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). |
586 | */ |
587 | nrx = ntx = 0; |
588 | id = usbd_get_interface_descriptor(sc->sc_iface); |
589 | for (i = 0; i < id->bNumEndpoints; i++) { |
590 | ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); |
591 | if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) |
592 | continue; |
593 | |
594 | if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { |
595 | sc->rxq.pipe_no = ed->bEndpointAddress; |
596 | nrx++; |
597 | } else if (ntx < 4) { |
598 | sc->txq[ntx].pipe_no = ed->bEndpointAddress; |
599 | ntx++; |
600 | } |
601 | } |
602 | /* make sure we've got them all */ |
603 | if (nrx < 1 || ntx < 4) { |
604 | aprint_error_dev(sc->sc_dev, "missing endpoint\n" ); |
605 | return; |
606 | } |
607 | |
608 | usb_init_task(&sc->sc_task, run_task, sc, 0); |
609 | callout_init(&sc->scan_to, 0); |
610 | callout_setfunc(&sc->scan_to, run_next_scan, sc); |
611 | callout_init(&sc->calib_to, 0); |
612 | callout_setfunc(&sc->calib_to, run_calibrate_to, sc); |
613 | |
614 | sc->amrr.amrr_min_success_threshold = 1; |
615 | sc->amrr.amrr_max_success_threshold = 10; |
616 | |
617 | /* wait for the chip to settle */ |
618 | for (ntries = 0; ntries < 100; ntries++) { |
619 | if (run_read(sc, RT2860_ASIC_VER_ID, &ver) != 0) |
620 | return; |
621 | if (ver != 0 && ver != 0xffffffff) |
622 | break; |
623 | DELAY(10); |
624 | } |
625 | if (ntries == 100) { |
626 | aprint_error_dev(sc->sc_dev, |
627 | "timeout waiting for NIC to initialize\n" ); |
628 | return; |
629 | } |
630 | sc->mac_ver = ver >> 16; |
631 | sc->mac_rev = ver & 0xffff; |
632 | |
633 | /* retrieve RF rev. no and various other things from EEPROM */ |
634 | run_read_eeprom(sc); |
635 | |
636 | aprint_error_dev(sc->sc_dev, |
637 | "MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), address %s\n" , |
638 | sc->mac_ver, sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, |
639 | sc->nrxchains, ether_sprintf(ic->ic_myaddr)); |
640 | |
641 | ic->ic_ifp = ifp; |
642 | ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ |
643 | ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ |
644 | ic->ic_state = IEEE80211_S_INIT; |
645 | |
646 | /* set device capabilities */ |
647 | ic->ic_caps = |
648 | IEEE80211_C_MONITOR | /* monitor mode supported */ |
649 | #ifndef IEEE80211_STA_ONLY |
650 | IEEE80211_C_IBSS | /* IBSS mode supported */ |
651 | IEEE80211_C_HOSTAP | /* HostAP mode supported */ |
652 | #endif |
653 | IEEE80211_C_SHPREAMBLE | /* short preamble supported */ |
654 | IEEE80211_C_SHSLOT | /* short slot time supported */ |
655 | #ifdef RUN_HWCRYPTO |
656 | IEEE80211_C_WEP | /* WEP */ |
657 | IEEE80211_C_TKIP | /* TKIP */ |
658 | IEEE80211_C_AES_CCM | /* AES CCMP */ |
659 | IEEE80211_C_TKIPMIC | /* TKIPMIC */ |
660 | #endif |
661 | IEEE80211_C_WME | /* WME */ |
662 | IEEE80211_C_WPA; /* WPA/RSN */ |
663 | |
664 | if (sc->rf_rev == RT2860_RF_2750 || |
665 | sc->rf_rev == RT2860_RF_2850 || |
666 | sc->rf_rev == RT3070_RF_3052 || |
667 | sc->rf_rev == RT3070_RF_3053 || |
668 | sc->rf_rev == RT5592_RF_5592) { |
669 | /* set supported .11a rates */ |
670 | ic->ic_sup_rates[IEEE80211_MODE_11A] = |
671 | ieee80211_std_rateset_11a; |
672 | |
673 | /* set supported .11a channels */ |
674 | for (i = 14; i < (int)__arraycount(rt2860_rf2850); i++) { |
675 | uint8_t chan = rt2860_rf2850[i].chan; |
676 | ic->ic_channels[chan].ic_freq = |
677 | ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); |
678 | ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; |
679 | } |
680 | } |
681 | |
682 | /* set supported .11b and .11g rates */ |
683 | ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; |
684 | ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; |
685 | |
686 | /* set supported .11b and .11g channels (1 through 14) */ |
687 | for (i = 1; i <= 14; i++) { |
688 | ic->ic_channels[i].ic_freq = |
689 | ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); |
690 | ic->ic_channels[i].ic_flags = |
691 | IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | |
692 | IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; |
693 | } |
694 | |
695 | ifp->if_softc = sc; |
696 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; |
697 | ifp->if_init = run_init; |
698 | ifp->if_ioctl = run_ioctl; |
699 | ifp->if_start = run_start; |
700 | ifp->if_watchdog = run_watchdog; |
701 | IFQ_SET_READY(&ifp->if_snd); |
702 | memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); |
703 | |
704 | if_attach(ifp); |
705 | ieee80211_ifattach(ic); |
706 | ic->ic_node_alloc = run_node_alloc; |
707 | ic->ic_newassoc = run_newassoc; |
708 | ic->ic_updateslot = run_updateslot; |
709 | ic->ic_wme.wme_update = run_updateedca; |
710 | #ifdef RUN_HWCRYPTO |
711 | ic->ic_crypto.cs_key_set = run_set_key; |
712 | ic->ic_crypto.cs_key_delete = run_delete_key; |
713 | #endif |
714 | /* override state transition machine */ |
715 | sc->sc_newstate = ic->ic_newstate; |
716 | ic->ic_newstate = run_newstate; |
717 | ieee80211_media_init(ic, run_media_change, ieee80211_media_status); |
718 | |
719 | bpf_attach2(ifp, DLT_IEEE802_11_RADIO, |
720 | sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, |
721 | &sc->sc_drvbpf); |
722 | |
723 | sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); |
724 | sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); |
725 | sc->sc_rxtap.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT); |
726 | |
727 | sc->sc_txtap_len = sizeof(sc->sc_txtapu); |
728 | sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); |
729 | sc->sc_txtap.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT); |
730 | |
731 | ieee80211_announce(ic); |
732 | |
733 | usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); |
734 | |
735 | if (!pmf_device_register(self, NULL, NULL)) |
736 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
737 | } |
738 | |
739 | static int |
740 | run_detach(device_t self, int flags) |
741 | { |
742 | struct run_softc *sc = device_private(self); |
743 | struct ifnet *ifp = &sc->sc_if; |
744 | struct ieee80211com *ic = &sc->sc_ic; |
745 | int s; |
746 | |
747 | if (ifp->if_softc == NULL) |
748 | return 0; |
749 | |
750 | pmf_device_deregister(self); |
751 | |
752 | s = splusb(); |
753 | |
754 | sc->sc_flags |= RUN_DETACHING; |
755 | |
756 | if (ifp->if_flags & IFF_RUNNING) { |
757 | usb_rem_task(sc->sc_udev, &sc->sc_task); |
758 | run_stop(ifp, 0); |
759 | } |
760 | |
761 | ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); |
762 | bpf_detach(ifp); |
763 | ieee80211_ifdetach(ic); |
764 | if_detach(ifp); |
765 | |
766 | splx(s); |
767 | |
768 | usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); |
769 | |
770 | callout_stop(&sc->scan_to); |
771 | callout_stop(&sc->calib_to); |
772 | |
773 | callout_destroy(&sc->scan_to); |
774 | callout_destroy(&sc->calib_to); |
775 | |
776 | return 0; |
777 | } |
778 | |
779 | static int |
780 | run_activate(device_t self, enum devact act) |
781 | { |
782 | struct run_softc *sc = device_private(self); |
783 | |
784 | switch (act) { |
785 | case DVACT_DEACTIVATE: |
786 | if_deactivate(sc->sc_ic.ic_ifp); |
787 | return 0; |
788 | default: |
789 | return EOPNOTSUPP; |
790 | } |
791 | } |
792 | |
793 | static int |
794 | run_alloc_rx_ring(struct run_softc *sc) |
795 | { |
796 | struct run_rx_ring *rxq = &sc->rxq; |
797 | int i, error; |
798 | |
799 | error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); |
800 | if (error != 0) |
801 | goto fail; |
802 | |
803 | for (i = 0; i < RUN_RX_RING_COUNT; i++) { |
804 | struct run_rx_data *data = &rxq->data[i]; |
805 | |
806 | data->sc = sc; /* backpointer for callbacks */ |
807 | |
808 | error = usbd_create_xfer(sc->rxq.pipeh, RUN_MAX_RXSZ, |
809 | USBD_SHORT_XFER_OK, 0, &data->xfer); |
810 | if (error) |
811 | goto fail; |
812 | |
813 | data->buf = usbd_get_buffer(data->xfer); |
814 | } |
815 | if (error != 0) |
816 | fail: run_free_rx_ring(sc); |
817 | return error; |
818 | } |
819 | |
820 | static void |
821 | run_free_rx_ring(struct run_softc *sc) |
822 | { |
823 | struct run_rx_ring *rxq = &sc->rxq; |
824 | int i; |
825 | |
826 | if (rxq->pipeh != NULL) { |
827 | usbd_abort_pipe(rxq->pipeh); |
828 | } |
829 | for (i = 0; i < RUN_RX_RING_COUNT; i++) { |
830 | if (rxq->data[i].xfer != NULL) |
831 | usbd_destroy_xfer(rxq->data[i].xfer); |
832 | rxq->data[i].xfer = NULL; |
833 | } |
834 | if (rxq->pipeh != NULL) { |
835 | usbd_close_pipe(rxq->pipeh); |
836 | rxq->pipeh = NULL; |
837 | } |
838 | } |
839 | |
840 | static int |
841 | run_alloc_tx_ring(struct run_softc *sc, int qid) |
842 | { |
843 | struct run_tx_ring *txq = &sc->txq[qid]; |
844 | int i, error; |
845 | |
846 | txq->cur = txq->queued = 0; |
847 | |
848 | error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); |
849 | if (error != 0) |
850 | goto fail; |
851 | |
852 | for (i = 0; i < RUN_TX_RING_COUNT; i++) { |
853 | struct run_tx_data *data = &txq->data[i]; |
854 | |
855 | data->sc = sc; /* backpointer for callbacks */ |
856 | data->qid = qid; |
857 | |
858 | error = usbd_create_xfer(txq->pipeh, RUN_MAX_TXSZ, |
859 | USBD_FORCE_SHORT_XFER, 0, &data->xfer); |
860 | if (error) |
861 | goto fail; |
862 | |
863 | data->buf = usbd_get_buffer(data->xfer); |
864 | /* zeroize the TXD + TXWI part */ |
865 | memset(data->buf, 0, sizeof(struct rt2870_txd) + |
866 | sizeof(struct rt2860_txwi)); |
867 | } |
868 | if (error != 0) |
869 | fail: run_free_tx_ring(sc, qid); |
870 | return error; |
871 | } |
872 | |
873 | static void |
874 | run_free_tx_ring(struct run_softc *sc, int qid) |
875 | { |
876 | struct run_tx_ring *txq = &sc->txq[qid]; |
877 | int i; |
878 | |
879 | if (txq->pipeh != NULL) { |
880 | usbd_abort_pipe(txq->pipeh); |
881 | usbd_close_pipe(txq->pipeh); |
882 | txq->pipeh = NULL; |
883 | } |
884 | for (i = 0; i < RUN_TX_RING_COUNT; i++) { |
885 | if (txq->data[i].xfer != NULL) |
886 | usbd_destroy_xfer(txq->data[i].xfer); |
887 | txq->data[i].xfer = NULL; |
888 | } |
889 | } |
890 | |
891 | static int |
892 | run_load_microcode(struct run_softc *sc) |
893 | { |
894 | usb_device_request_t req; |
895 | const char *fwname; |
896 | u_char *ucode = NULL; /* XXX gcc 4.8.3: maybe-uninitialized */ |
897 | size_t size = 0; /* XXX gcc 4.8.3: maybe-uninitialized */ |
898 | uint32_t tmp; |
899 | int ntries, error; |
900 | |
901 | /* RT3071/RT3072 use a different firmware */ |
902 | if (sc->mac_ver != 0x2860 && |
903 | sc->mac_ver != 0x2872 && |
904 | sc->mac_ver != 0x3070) |
905 | fwname = "run-rt3071" ; |
906 | else |
907 | fwname = "run-rt2870" ; |
908 | |
909 | if ((error = firmware_load("run" , fwname, &ucode, &size)) != 0) { |
910 | aprint_error_dev(sc->sc_dev, |
911 | "error %d, could not read firmware %s\n" , error, fwname); |
912 | return error; |
913 | } |
914 | if (size != 4096) { |
915 | aprint_error_dev(sc->sc_dev, |
916 | "invalid firmware size (should be 4KB)\n" ); |
917 | firmware_free(ucode, size); |
918 | return EINVAL; |
919 | } |
920 | |
921 | run_read(sc, RT2860_ASIC_VER_ID, &tmp); |
922 | /* write microcode image */ |
923 | run_write_region_1(sc, RT2870_FW_BASE, ucode, size); |
924 | firmware_free(ucode, size); |
925 | run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); |
926 | run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); |
927 | |
928 | req.bmRequestType = UT_WRITE_VENDOR_DEVICE; |
929 | req.bRequest = RT2870_RESET; |
930 | USETW(req.wValue, 8); |
931 | USETW(req.wIndex, 0); |
932 | USETW(req.wLength, 0); |
933 | if ((error = usbd_do_request(sc->sc_udev, &req, NULL)) != 0) |
934 | return error; |
935 | |
936 | usbd_delay_ms(sc->sc_udev, 10); |
937 | run_write(sc, RT2860_H2M_MAILBOX, 0); |
938 | if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) |
939 | return error; |
940 | |
941 | /* wait until microcontroller is ready */ |
942 | for (ntries = 0; ntries < 1000; ntries++) { |
943 | if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) |
944 | return error; |
945 | if (tmp & RT2860_MCU_READY) |
946 | break; |
947 | usbd_delay_ms(sc->sc_udev, 10); |
948 | } |
949 | if (ntries == 1000) { |
950 | aprint_error_dev(sc->sc_dev, |
951 | "timeout waiting for MCU to initialize\n" ); |
952 | return ETIMEDOUT; |
953 | } |
954 | |
955 | sc->sc_flags |= RUN_FWLOADED; |
956 | |
957 | DPRINTF(("microcode successfully loaded after %d tries\n" , ntries)); |
958 | return 0; |
959 | } |
960 | |
961 | static int |
962 | run_reset(struct run_softc *sc) |
963 | { |
964 | usb_device_request_t req; |
965 | |
966 | req.bmRequestType = UT_WRITE_VENDOR_DEVICE; |
967 | req.bRequest = RT2870_RESET; |
968 | USETW(req.wValue, 1); |
969 | USETW(req.wIndex, 0); |
970 | USETW(req.wLength, 0); |
971 | return usbd_do_request(sc->sc_udev, &req, NULL); |
972 | } |
973 | |
974 | static int |
975 | run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) |
976 | { |
977 | uint32_t tmp; |
978 | int error; |
979 | |
980 | error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof(tmp)); |
981 | if (error == 0) |
982 | *val = le32toh(tmp); |
983 | else |
984 | *val = 0xffffffff; |
985 | return error; |
986 | } |
987 | |
988 | static int |
989 | run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) |
990 | { |
991 | usb_device_request_t req; |
992 | |
993 | req.bmRequestType = UT_READ_VENDOR_DEVICE; |
994 | req.bRequest = RT2870_READ_REGION_1; |
995 | USETW(req.wValue, 0); |
996 | USETW(req.wIndex, reg); |
997 | USETW(req.wLength, len); |
998 | return usbd_do_request(sc->sc_udev, &req, buf); |
999 | } |
1000 | |
1001 | static int |
1002 | run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) |
1003 | { |
1004 | usb_device_request_t req; |
1005 | |
1006 | req.bmRequestType = UT_WRITE_VENDOR_DEVICE; |
1007 | req.bRequest = RT2870_WRITE_2; |
1008 | USETW(req.wValue, val); |
1009 | USETW(req.wIndex, reg); |
1010 | USETW(req.wLength, 0); |
1011 | return usbd_do_request(sc->sc_udev, &req, NULL); |
1012 | } |
1013 | |
1014 | static int |
1015 | run_write(struct run_softc *sc, uint16_t reg, uint32_t val) |
1016 | { |
1017 | int error; |
1018 | |
1019 | if ((error = run_write_2(sc, reg, val & 0xffff)) == 0) |
1020 | error = run_write_2(sc, reg + 2, val >> 16); |
1021 | return error; |
1022 | } |
1023 | |
1024 | static int |
1025 | run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, |
1026 | int len) |
1027 | { |
1028 | #if 1 |
1029 | int i, error = 0; |
1030 | /* |
1031 | * NB: the WRITE_REGION_1 command is not stable on RT2860. |
1032 | * We thus issue multiple WRITE_2 commands instead. |
1033 | */ |
1034 | KASSERT((len & 1) == 0); |
1035 | for (i = 0; i < len && error == 0; i += 2) |
1036 | error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); |
1037 | return error; |
1038 | #else |
1039 | usb_device_request_t req; |
1040 | |
1041 | req.bmRequestType = UT_WRITE_VENDOR_DEVICE; |
1042 | req.bRequest = RT2870_WRITE_REGION_1; |
1043 | USETW(req.wValue, 0); |
1044 | USETW(req.wIndex, reg); |
1045 | USETW(req.wLength, len); |
1046 | return usbd_do_request(sc->sc_udev, &req, buf); |
1047 | #endif |
1048 | } |
1049 | |
1050 | static int |
1051 | run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) |
1052 | { |
1053 | int error = 0; |
1054 | |
1055 | for (; count > 0 && error == 0; count--, reg += 4) |
1056 | error = run_write(sc, reg, val); |
1057 | return error; |
1058 | } |
1059 | |
1060 | static int |
1061 | run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val, int count) |
1062 | { |
1063 | uint32_t tmp; |
1064 | uint16_t reg; |
1065 | int error, ntries; |
1066 | |
1067 | if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) |
1068 | return error; |
1069 | |
1070 | if (count == 2) |
1071 | addr *= 2; |
1072 | /*- |
1073 | * Read one 16-byte block into registers EFUSE_DATA[0-3]: |
1074 | * DATA0: F E D C |
1075 | * DATA1: B A 9 8 |
1076 | * DATA2: 7 6 5 4 |
1077 | * DATA3: 3 2 1 0 |
1078 | */ |
1079 | tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); |
1080 | tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; |
1081 | run_write(sc, RT3070_EFUSE_CTRL, tmp); |
1082 | for (ntries = 0; ntries < 100; ntries++) { |
1083 | if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) |
1084 | return error; |
1085 | if (!(tmp & RT3070_EFSROM_KICK)) |
1086 | break; |
1087 | usbd_delay_ms(sc->sc_udev, 2); |
1088 | } |
1089 | if (ntries == 100) |
1090 | return ETIMEDOUT; |
1091 | |
1092 | if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { |
1093 | *val = 0xffff; /* address not found */ |
1094 | return 0; |
1095 | } |
1096 | /* determine to which 32-bit register our 16-bit word belongs */ |
1097 | reg = RT3070_EFUSE_DATA3 - (addr & 0xc); |
1098 | if ((error = run_read(sc, reg, &tmp)) != 0) |
1099 | return error; |
1100 | |
1101 | *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; |
1102 | return 0; |
1103 | } |
1104 | |
1105 | /* Read 16-bit from eFUSE ROM for RT3xxxx. */ |
1106 | static int |
1107 | run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) |
1108 | { |
1109 | return (run_efuse_read(sc, addr, val, 2)); |
1110 | } |
1111 | |
1112 | static int |
1113 | run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) |
1114 | { |
1115 | usb_device_request_t req; |
1116 | uint16_t tmp; |
1117 | int error; |
1118 | |
1119 | addr *= 2; |
1120 | req.bmRequestType = UT_READ_VENDOR_DEVICE; |
1121 | req.bRequest = RT2870_EEPROM_READ; |
1122 | USETW(req.wValue, 0); |
1123 | USETW(req.wIndex, addr); |
1124 | USETW(req.wLength, sizeof(tmp)); |
1125 | error = usbd_do_request(sc->sc_udev, &req, &tmp); |
1126 | if (error == 0) |
1127 | *val = le16toh(tmp); |
1128 | else |
1129 | *val = 0xffff; |
1130 | return error; |
1131 | } |
1132 | |
1133 | static __inline int |
1134 | run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) |
1135 | { |
1136 | |
1137 | /* either eFUSE ROM or EEPROM */ |
1138 | return sc->sc_srom_read(sc, addr, val); |
1139 | } |
1140 | |
1141 | static int |
1142 | run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) |
1143 | { |
1144 | uint32_t tmp; |
1145 | int error, ntries; |
1146 | |
1147 | for (ntries = 0; ntries < 10; ntries++) { |
1148 | if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0) |
1149 | return error; |
1150 | if (!(tmp & RT2860_RF_REG_CTRL)) |
1151 | break; |
1152 | } |
1153 | if (ntries == 10) |
1154 | return ETIMEDOUT; |
1155 | |
1156 | /* RF registers are 24-bit on the RT2860 */ |
1157 | tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | |
1158 | (val & 0x3fffff) << 2 | (reg & 3); |
1159 | return run_write(sc, RT2860_RF_CSR_CFG0, tmp); |
1160 | } |
1161 | |
1162 | static int |
1163 | run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) |
1164 | { |
1165 | uint32_t tmp; |
1166 | int error, ntries; |
1167 | |
1168 | for (ntries = 0; ntries < 100; ntries++) { |
1169 | if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) |
1170 | return error; |
1171 | if (!(tmp & RT3070_RF_KICK)) |
1172 | break; |
1173 | } |
1174 | if (ntries == 100) |
1175 | return ETIMEDOUT; |
1176 | |
1177 | tmp = RT3070_RF_KICK | reg << 8; |
1178 | if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0) |
1179 | return error; |
1180 | |
1181 | for (ntries = 0; ntries < 100; ntries++) { |
1182 | if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) |
1183 | return error; |
1184 | if (!(tmp & RT3070_RF_KICK)) |
1185 | break; |
1186 | } |
1187 | if (ntries == 100) |
1188 | return ETIMEDOUT; |
1189 | |
1190 | *val = tmp & 0xff; |
1191 | return 0; |
1192 | } |
1193 | |
1194 | static int |
1195 | run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) |
1196 | { |
1197 | uint32_t tmp; |
1198 | int error, ntries; |
1199 | |
1200 | for (ntries = 0; ntries < 10; ntries++) { |
1201 | if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) |
1202 | return error; |
1203 | if (!(tmp & RT3070_RF_KICK)) |
1204 | break; |
1205 | } |
1206 | if (ntries == 10) |
1207 | return ETIMEDOUT; |
1208 | |
1209 | tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; |
1210 | return run_write(sc, RT3070_RF_CSR_CFG, tmp); |
1211 | } |
1212 | |
1213 | static int |
1214 | run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) |
1215 | { |
1216 | uint32_t tmp; |
1217 | int ntries, error; |
1218 | |
1219 | for (ntries = 0; ntries < 10; ntries++) { |
1220 | if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) |
1221 | return error; |
1222 | if (!(tmp & RT2860_BBP_CSR_KICK)) |
1223 | break; |
1224 | } |
1225 | if (ntries == 10) |
1226 | return ETIMEDOUT; |
1227 | |
1228 | tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8; |
1229 | if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0) |
1230 | return error; |
1231 | |
1232 | for (ntries = 0; ntries < 10; ntries++) { |
1233 | if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) |
1234 | return error; |
1235 | if (!(tmp & RT2860_BBP_CSR_KICK)) |
1236 | break; |
1237 | } |
1238 | if (ntries == 10) |
1239 | return ETIMEDOUT; |
1240 | |
1241 | *val = tmp & 0xff; |
1242 | return 0; |
1243 | } |
1244 | |
1245 | static int |
1246 | run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) |
1247 | { |
1248 | uint32_t tmp; |
1249 | int ntries, error; |
1250 | |
1251 | for (ntries = 0; ntries < 10; ntries++) { |
1252 | if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) |
1253 | return error; |
1254 | if (!(tmp & RT2860_BBP_CSR_KICK)) |
1255 | break; |
1256 | } |
1257 | if (ntries == 10) |
1258 | return ETIMEDOUT; |
1259 | |
1260 | tmp = RT2860_BBP_CSR_KICK | reg << 8 | val; |
1261 | return run_write(sc, RT2860_BBP_CSR_CFG, tmp); |
1262 | } |
1263 | |
1264 | /* |
1265 | * Send a command to the 8051 microcontroller unit. |
1266 | */ |
1267 | static int |
1268 | run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) |
1269 | { |
1270 | uint32_t tmp; |
1271 | int error, ntries; |
1272 | |
1273 | for (ntries = 0; ntries < 100; ntries++) { |
1274 | if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0) |
1275 | return error; |
1276 | if (!(tmp & RT2860_H2M_BUSY)) |
1277 | break; |
1278 | } |
1279 | if (ntries == 100) |
1280 | return ETIMEDOUT; |
1281 | |
1282 | tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg; |
1283 | if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0) |
1284 | error = run_write(sc, RT2860_HOST_CMD, cmd); |
1285 | return error; |
1286 | } |
1287 | |
1288 | /* |
1289 | * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. |
1290 | * Used to adjust per-rate Tx power registers. |
1291 | */ |
1292 | static __inline uint32_t |
1293 | b4inc(uint32_t b32, int8_t delta) |
1294 | { |
1295 | int8_t i, b4; |
1296 | |
1297 | for (i = 0; i < 8; i++) { |
1298 | b4 = b32 & 0xf; |
1299 | b4 += delta; |
1300 | if (b4 < 0) |
1301 | b4 = 0; |
1302 | else if (b4 > 0xf) |
1303 | b4 = 0xf; |
1304 | b32 = b32 >> 4 | b4 << 28; |
1305 | } |
1306 | return b32; |
1307 | } |
1308 | |
1309 | static const char * |
1310 | run_get_rf(int rev) |
1311 | { |
1312 | switch (rev) { |
1313 | case RT2860_RF_2820: return "RT2820" ; |
1314 | case RT2860_RF_2850: return "RT2850" ; |
1315 | case RT2860_RF_2720: return "RT2720" ; |
1316 | case RT2860_RF_2750: return "RT2750" ; |
1317 | case RT3070_RF_3020: return "RT3020" ; |
1318 | case RT3070_RF_2020: return "RT2020" ; |
1319 | case RT3070_RF_3021: return "RT3021" ; |
1320 | case RT3070_RF_3022: return "RT3022" ; |
1321 | case RT3070_RF_3052: return "RT3052" ; |
1322 | case RT3070_RF_3053: return "RT3053" ; |
1323 | case RT5592_RF_5592: return "RT5592" ; |
1324 | case RT5390_RF_5370: return "RT5370" ; |
1325 | case RT5390_RF_5372: return "RT5372" ; |
1326 | } |
1327 | return "unknown" ; |
1328 | } |
1329 | |
1330 | static void |
1331 | run_rt3593_get_txpower(struct run_softc *sc) |
1332 | { |
1333 | uint16_t addr, val; |
1334 | int i; |
1335 | |
1336 | /* Read power settings for 2GHz channels. */ |
1337 | for (i = 0; i < 14; i += 2) { |
1338 | addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : |
1339 | RT2860_EEPROM_PWR2GHZ_BASE1; |
1340 | run_srom_read(sc, addr + i / 2, &val); |
1341 | sc->txpow1[i + 0] = (int8_t)(val & 0xff); |
1342 | sc->txpow1[i + 1] = (int8_t)(val >> 8); |
1343 | |
1344 | addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : |
1345 | RT2860_EEPROM_PWR2GHZ_BASE2; |
1346 | run_srom_read(sc, addr + i / 2, &val); |
1347 | sc->txpow2[i + 0] = (int8_t)(val & 0xff); |
1348 | sc->txpow2[i + 1] = (int8_t)(val >> 8); |
1349 | |
1350 | if (sc->ntxchains == 3) { |
1351 | run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, |
1352 | &val); |
1353 | sc->txpow3[i + 0] = (int8_t)(val & 0xff); |
1354 | sc->txpow3[i + 1] = (int8_t)(val >> 8); |
1355 | } |
1356 | } |
1357 | /* Fix broken Tx power entries. */ |
1358 | for (i = 0; i < 14; i++) { |
1359 | if (sc->txpow1[i] > 31) |
1360 | sc->txpow1[i] = 5; |
1361 | if (sc->txpow2[i] > 31) |
1362 | sc->txpow2[i] = 5; |
1363 | if (sc->ntxchains == 3) { |
1364 | if (sc->txpow3[i] > 31) |
1365 | sc->txpow3[i] = 5; |
1366 | } |
1367 | } |
1368 | /* Read power settings for 5GHz channels. */ |
1369 | for (i = 0; i < 40; i += 2) { |
1370 | run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); |
1371 | sc->txpow1[i + 14] = (int8_t)(val & 0xff); |
1372 | sc->txpow1[i + 15] = (int8_t)(val >> 8); |
1373 | |
1374 | run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); |
1375 | sc->txpow2[i + 14] = (int8_t)(val & 0xff); |
1376 | sc->txpow2[i + 15] = (int8_t)(val >> 8); |
1377 | |
1378 | if (sc->ntxchains == 3) { |
1379 | run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, |
1380 | &val); |
1381 | sc->txpow3[i + 14] = (int8_t)(val & 0xff); |
1382 | sc->txpow3[i + 15] = (int8_t)(val >> 8); |
1383 | } |
1384 | } |
1385 | } |
1386 | |
1387 | static void |
1388 | run_get_txpower(struct run_softc *sc) |
1389 | { |
1390 | uint16_t val; |
1391 | int i; |
1392 | |
1393 | /* Read power settings for 2GHz channels. */ |
1394 | for (i = 0; i < 14; i += 2) { |
1395 | run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); |
1396 | sc->txpow1[i + 0] = (int8_t)(val & 0xff); |
1397 | sc->txpow1[i + 1] = (int8_t)(val >> 8); |
1398 | |
1399 | if (sc->mac_ver != 0x5390) { |
1400 | run_srom_read(sc, |
1401 | RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); |
1402 | sc->txpow2[i + 0] = (int8_t)(val & 0xff); |
1403 | sc->txpow2[i + 1] = (int8_t)(val >> 8); |
1404 | } |
1405 | } |
1406 | /* Fix broken Tx power entries. */ |
1407 | for (i = 0; i < 14; i++) { |
1408 | if (sc->mac_ver >= 0x5390) { |
1409 | if (sc->txpow1[i] < 0 || sc->txpow1[i] > 39) |
1410 | sc->txpow1[i] = 5; |
1411 | } else { |
1412 | if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) |
1413 | sc->txpow1[i] = 5; |
1414 | } |
1415 | if (sc->mac_ver > 0x5390) { |
1416 | if (sc->txpow2[i] < 0 || sc->txpow2[i] > 39) |
1417 | sc->txpow2[i] = 5; |
1418 | } else if (sc->mac_ver < 0x5390) { |
1419 | if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) |
1420 | sc->txpow2[i] = 5; |
1421 | } |
1422 | DPRINTF(("chan %d: power1=%d, power2=%d\n" , |
1423 | rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); |
1424 | } |
1425 | /* Read power settings for 5GHz channels. */ |
1426 | for (i = 0; i < 40; i += 2) { |
1427 | run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); |
1428 | sc->txpow1[i + 14] = (int8_t)(val & 0xff); |
1429 | sc->txpow1[i + 15] = (int8_t)(val >> 8); |
1430 | |
1431 | run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); |
1432 | sc->txpow2[i + 14] = (int8_t)(val & 0xff); |
1433 | sc->txpow2[i + 15] = (int8_t)(val >> 8); |
1434 | } |
1435 | /* Fix broken Tx power entries. */ |
1436 | for (i = 0; i < 40; i++ ) { |
1437 | if (sc->mac_ver != 0x5592) { |
1438 | if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) |
1439 | sc->txpow1[14 + i] = 5; |
1440 | if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) |
1441 | sc->txpow2[14 + i] = 5; |
1442 | } |
1443 | DPRINTF(("chan %d: power1=%d, power2=%d\n" , |
1444 | rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], |
1445 | sc->txpow2[14 + i])); |
1446 | } |
1447 | } |
1448 | |
1449 | static int |
1450 | run_read_eeprom(struct run_softc *sc) |
1451 | { |
1452 | struct ieee80211com *ic = &sc->sc_ic; |
1453 | int8_t delta_2ghz, delta_5ghz; |
1454 | uint32_t tmp; |
1455 | uint16_t val; |
1456 | int ridx, ant, i; |
1457 | |
1458 | /* check whether the ROM is eFUSE ROM or EEPROM */ |
1459 | sc->sc_srom_read = run_eeprom_read_2; |
1460 | if (sc->mac_ver >= 0x3070) { |
1461 | run_read(sc, RT3070_EFUSE_CTRL, &tmp); |
1462 | DPRINTF(("EFUSE_CTRL=0x%08x\n" , tmp)); |
1463 | if (tmp & RT3070_SEL_EFUSE) |
1464 | sc->sc_srom_read = run_efuse_read_2; |
1465 | } |
1466 | |
1467 | /* read ROM version */ |
1468 | run_srom_read(sc, RT2860_EEPROM_VERSION, &val); |
1469 | DPRINTF(("EEPROM rev=%d, FAE=%d\n" , val & 0xff, val >> 8)); |
1470 | |
1471 | /* read MAC address */ |
1472 | run_srom_read(sc, RT2860_EEPROM_MAC01, &val); |
1473 | ic->ic_myaddr[0] = val & 0xff; |
1474 | ic->ic_myaddr[1] = val >> 8; |
1475 | run_srom_read(sc, RT2860_EEPROM_MAC23, &val); |
1476 | ic->ic_myaddr[2] = val & 0xff; |
1477 | ic->ic_myaddr[3] = val >> 8; |
1478 | run_srom_read(sc, RT2860_EEPROM_MAC45, &val); |
1479 | ic->ic_myaddr[4] = val & 0xff; |
1480 | ic->ic_myaddr[5] = val >> 8; |
1481 | |
1482 | /* read vendor BBP settings */ |
1483 | for (i = 0; i < 10; i++) { |
1484 | run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); |
1485 | sc->bbp[i].val = val & 0xff; |
1486 | sc->bbp[i].reg = val >> 8; |
1487 | DPRINTF(("BBP%d=0x%02x\n" , sc->bbp[i].reg, sc->bbp[i].val)); |
1488 | } |
1489 | |
1490 | /* read vendor RF settings */ |
1491 | for (i = 0; i < 8; i++) { |
1492 | run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, &val); |
1493 | sc->rf[i].val = val & 0xff; |
1494 | sc->rf[i].reg = val >> 8; |
1495 | DPRINTF(("RF%d=0x%02x\n" , sc->rf[i].reg, |
1496 | sc->rf[i].val)); |
1497 | } |
1498 | |
1499 | /* read RF frequency offset from EEPROM */ |
1500 | run_srom_read(sc, RT2860_EEPROM_FREQ_LEDS, &val); |
1501 | sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; |
1502 | DPRINTF(("EEPROM freq offset %d\n" , sc->freq & 0xff)); |
1503 | |
1504 | if ((val >> 8) != 0xff) { |
1505 | /* read LEDs operating mode */ |
1506 | sc->leds = val >> 8; |
1507 | run_srom_read(sc, RT2860_EEPROM_LED1, &sc->led[0]); |
1508 | run_srom_read(sc, RT2860_EEPROM_LED2, &sc->led[1]); |
1509 | run_srom_read(sc, RT2860_EEPROM_LED3, &sc->led[2]); |
1510 | } else { |
1511 | /* broken EEPROM, use default settings */ |
1512 | sc->leds = 0x01; |
1513 | sc->led[0] = 0x5555; |
1514 | sc->led[1] = 0x2221; |
1515 | sc->led[2] = 0x5627; /* differs from RT2860 */ |
1516 | } |
1517 | DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n" , |
1518 | sc->leds, sc->led[0], sc->led[1], sc->led[2])); |
1519 | |
1520 | /* read RF information */ |
1521 | run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); |
1522 | if (val == 0xffff) { |
1523 | DPRINTF(("invalid EEPROM antenna info, using default\n" )); |
1524 | if (sc->mac_ver == 0x3572) { |
1525 | /* default to RF3052 2T2R */ |
1526 | sc->rf_rev = RT3070_RF_3052; |
1527 | sc->ntxchains = 2; |
1528 | sc->nrxchains = 2; |
1529 | } else if (sc->mac_ver >= 0x3070) { |
1530 | /* default to RF3020 1T1R */ |
1531 | sc->rf_rev = RT3070_RF_3020; |
1532 | sc->ntxchains = 1; |
1533 | sc->nrxchains = 1; |
1534 | } else { |
1535 | /* default to RF2820 1T2R */ |
1536 | sc->rf_rev = RT2860_RF_2820; |
1537 | sc->ntxchains = 1; |
1538 | sc->nrxchains = 2; |
1539 | } |
1540 | } else { |
1541 | sc->rf_rev = (val >> 8) & 0xf; |
1542 | sc->ntxchains = (val >> 4) & 0xf; |
1543 | sc->nrxchains = val & 0xf; |
1544 | } |
1545 | DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n" , |
1546 | sc->rf_rev, sc->ntxchains, sc->nrxchains)); |
1547 | |
1548 | run_srom_read(sc, RT2860_EEPROM_CONFIG, &val); |
1549 | DPRINTF(("EEPROM CFG 0x%04x\n" , val)); |
1550 | /* check if driver should patch the DAC issue */ |
1551 | if ((val >> 8) != 0xff) |
1552 | sc->patch_dac = (val >> 15) & 1; |
1553 | if ((val & 0xff) != 0xff) { |
1554 | sc->ext_5ghz_lna = (val >> 3) & 1; |
1555 | sc->ext_2ghz_lna = (val >> 2) & 1; |
1556 | /* check if RF supports automatic Tx access gain control */ |
1557 | sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; |
1558 | /* check if we have a hardware radio switch */ |
1559 | sc->rfswitch = val & 1; |
1560 | } |
1561 | |
1562 | /* Read Tx power settings. */ |
1563 | if (sc->mac_ver == 0x3593) |
1564 | run_rt3593_get_txpower(sc); |
1565 | else |
1566 | run_get_txpower(sc); |
1567 | |
1568 | /* read Tx power compensation for each Tx rate */ |
1569 | run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); |
1570 | delta_2ghz = delta_5ghz = 0; |
1571 | if ((val & 0xff) != 0xff && (val & 0x80)) { |
1572 | delta_2ghz = val & 0xf; |
1573 | if (!(val & 0x40)) /* negative number */ |
1574 | delta_2ghz = -delta_2ghz; |
1575 | } |
1576 | val >>= 8; |
1577 | if ((val & 0xff) != 0xff && (val & 0x80)) { |
1578 | delta_5ghz = val & 0xf; |
1579 | if (!(val & 0x40)) /* negative number */ |
1580 | delta_5ghz = -delta_5ghz; |
1581 | } |
1582 | DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n" , |
1583 | delta_2ghz, delta_5ghz)); |
1584 | |
1585 | for (ridx = 0; ridx < 5; ridx++) { |
1586 | uint32_t reg; |
1587 | |
1588 | run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val); |
1589 | reg = val; |
1590 | run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val); |
1591 | reg |= (uint32_t)val << 16; |
1592 | |
1593 | sc->txpow20mhz[ridx] = reg; |
1594 | sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); |
1595 | sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); |
1596 | |
1597 | DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " |
1598 | "40MHz/5GHz=0x%08x\n" , ridx, sc->txpow20mhz[ridx], |
1599 | sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); |
1600 | } |
1601 | |
1602 | /* read RSSI offsets and LNA gains from EEPROM */ |
1603 | run_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ, &val); |
1604 | sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ |
1605 | sc->rssi_2ghz[1] = val >> 8; /* Ant B */ |
1606 | run_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ, &val); |
1607 | if (sc->mac_ver >= 0x3070) { |
1608 | if (sc->mac_ver == 0x3593) { |
1609 | sc->txmixgain_2ghz = 0; |
1610 | sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ |
1611 | } else { |
1612 | /* |
1613 | * On RT3070 chips (limited to 2 Rx chains), this ROM |
1614 | * field contains the Tx mixer gain for the 2GHz band. |
1615 | */ |
1616 | if ((val & 0xff) != 0xff) |
1617 | sc->txmixgain_2ghz = val & 0x7; |
1618 | } |
1619 | DPRINTF(("tx mixer gain=%u (2GHz)\n" , sc->txmixgain_2ghz)); |
1620 | } else { |
1621 | sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ |
1622 | } |
1623 | if (sc->mac_ver == 0x3593) |
1624 | run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); |
1625 | sc->lna[2] = val >> 8; /* channel group 2 */ |
1626 | |
1627 | run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : |
1628 | RT3593_EEPROM_RSSI2_5GHZ, &val); |
1629 | sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ |
1630 | sc->rssi_5ghz[1] = val >> 8; /* Ant B */ |
1631 | run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : |
1632 | RT3593_EEPROM_RSSI2_5GHZ, &val); |
1633 | if (sc->mac_ver == 0x3572) { |
1634 | /* |
1635 | * On RT3572 chips (limited to 2 Rx chains), this ROM |
1636 | * field contains the Tx mixer gain for the 5GHz band. |
1637 | */ |
1638 | if ((val & 0xff) != 0xff) |
1639 | sc->txmixgain_5ghz = val & 0x7; |
1640 | DPRINTF(("tx mixer gain=%u (5GHz)\n" , sc->txmixgain_5ghz)); |
1641 | } else { |
1642 | sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ |
1643 | } |
1644 | if (sc->mac_ver == 0x3593) { |
1645 | sc->txmixgain_5ghz = 0; |
1646 | run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); |
1647 | } |
1648 | sc->lna[3] = val >> 8; /* channel group 3 */ |
1649 | |
1650 | run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : |
1651 | RT3593_EEPROM_LNA, &val); |
1652 | sc->lna[0] = val & 0xff; /* channel group 0 */ |
1653 | sc->lna[1] = val >> 8; /* channel group 1 */ |
1654 | |
1655 | /* fix broken 5GHz LNA entries */ |
1656 | if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { |
1657 | DPRINTF(("invalid LNA for channel group %d\n" , 2)); |
1658 | sc->lna[2] = sc->lna[1]; |
1659 | } |
1660 | if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { |
1661 | DPRINTF(("invalid LNA for channel group %d\n" , 3)); |
1662 | sc->lna[3] = sc->lna[1]; |
1663 | } |
1664 | |
1665 | /* fix broken RSSI offset entries */ |
1666 | for (ant = 0; ant < 3; ant++) { |
1667 | if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { |
1668 | DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n" , |
1669 | ant + 1, sc->rssi_2ghz[ant])); |
1670 | sc->rssi_2ghz[ant] = 0; |
1671 | } |
1672 | if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { |
1673 | DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n" , |
1674 | ant + 1, sc->rssi_5ghz[ant])); |
1675 | sc->rssi_5ghz[ant] = 0; |
1676 | } |
1677 | } |
1678 | return 0; |
1679 | } |
1680 | |
1681 | static struct ieee80211_node * |
1682 | run_node_alloc(struct ieee80211_node_table *nt) |
1683 | { |
1684 | struct run_node *rn = |
1685 | malloc(sizeof(struct run_node), M_DEVBUF, M_NOWAIT | M_ZERO); |
1686 | return rn ? &rn->ni : NULL; |
1687 | } |
1688 | |
1689 | static int |
1690 | run_media_change(struct ifnet *ifp) |
1691 | { |
1692 | struct run_softc *sc = ifp->if_softc; |
1693 | struct ieee80211com *ic = &sc->sc_ic; |
1694 | uint8_t rate, ridx; |
1695 | int error; |
1696 | |
1697 | error = ieee80211_media_change(ifp); |
1698 | if (error != ENETRESET) |
1699 | return error; |
1700 | |
1701 | if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { |
1702 | rate = ic->ic_sup_rates[ic->ic_curmode]. |
1703 | rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; |
1704 | for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) |
1705 | if (rt2860_rates[ridx].rate == rate) |
1706 | break; |
1707 | sc->fixed_ridx = ridx; |
1708 | } |
1709 | |
1710 | if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) |
1711 | run_init(ifp); |
1712 | |
1713 | return 0; |
1714 | } |
1715 | |
1716 | static void |
1717 | run_next_scan(void *arg) |
1718 | { |
1719 | struct run_softc *sc = arg; |
1720 | |
1721 | if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) |
1722 | ieee80211_next_scan(&sc->sc_ic); |
1723 | } |
1724 | |
1725 | static void |
1726 | run_task(void *arg) |
1727 | { |
1728 | struct run_softc *sc = arg; |
1729 | struct run_host_cmd_ring *ring = &sc->cmdq; |
1730 | struct run_host_cmd *cmd; |
1731 | int s; |
1732 | |
1733 | /* process host commands */ |
1734 | s = splusb(); |
1735 | while (ring->next != ring->cur) { |
1736 | cmd = &ring->cmd[ring->next]; |
1737 | splx(s); |
1738 | /* callback */ |
1739 | cmd->cb(sc, cmd->data); |
1740 | s = splusb(); |
1741 | ring->queued--; |
1742 | ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT; |
1743 | } |
1744 | wakeup(ring); |
1745 | splx(s); |
1746 | } |
1747 | |
1748 | static void |
1749 | run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), |
1750 | void *arg, int len) |
1751 | { |
1752 | struct run_host_cmd_ring *ring = &sc->cmdq; |
1753 | struct run_host_cmd *cmd; |
1754 | int s; |
1755 | |
1756 | if (sc->sc_flags & RUN_DETACHING) |
1757 | return; |
1758 | |
1759 | s = splusb(); |
1760 | cmd = &ring->cmd[ring->cur]; |
1761 | cmd->cb = cb; |
1762 | KASSERT(len <= sizeof(cmd->data)); |
1763 | memcpy(cmd->data, arg, len); |
1764 | ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT; |
1765 | |
1766 | /* if there is no pending command already, schedule a task */ |
1767 | if (++ring->queued == 1) |
1768 | usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); |
1769 | splx(s); |
1770 | } |
1771 | |
1772 | static int |
1773 | run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) |
1774 | { |
1775 | struct run_softc *sc = ic->ic_ifp->if_softc; |
1776 | struct run_cmd_newstate cmd; |
1777 | |
1778 | callout_stop(&sc->scan_to); |
1779 | callout_stop(&sc->calib_to); |
1780 | |
1781 | /* do it in a process context */ |
1782 | cmd.state = nstate; |
1783 | cmd.arg = arg; |
1784 | run_do_async(sc, run_newstate_cb, &cmd, sizeof(cmd)); |
1785 | return 0; |
1786 | } |
1787 | |
1788 | static void |
1789 | run_newstate_cb(struct run_softc *sc, void *arg) |
1790 | { |
1791 | struct run_cmd_newstate *cmd = arg; |
1792 | struct ifnet *ifp = &sc->sc_if; |
1793 | struct ieee80211com *ic = &sc->sc_ic; |
1794 | enum ieee80211_state ostate; |
1795 | struct ieee80211_node *ni; |
1796 | uint32_t tmp, sta[3]; |
1797 | uint8_t wcid; |
1798 | int s; |
1799 | |
1800 | s = splnet(); |
1801 | ostate = ic->ic_state; |
1802 | |
1803 | if (ostate == IEEE80211_S_RUN) { |
1804 | /* turn link LED off */ |
1805 | run_set_leds(sc, RT2860_LED_RADIO); |
1806 | } |
1807 | |
1808 | switch (cmd->state) { |
1809 | case IEEE80211_S_INIT: |
1810 | if (ostate == IEEE80211_S_RUN) { |
1811 | /* abort TSF synchronization */ |
1812 | run_read(sc, RT2860_BCN_TIME_CFG, &tmp); |
1813 | run_write(sc, RT2860_BCN_TIME_CFG, |
1814 | tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | |
1815 | RT2860_TBTT_TIMER_EN)); |
1816 | } |
1817 | break; |
1818 | |
1819 | case IEEE80211_S_SCAN: |
1820 | run_set_chan(sc, ic->ic_curchan); |
1821 | callout_schedule(&sc->scan_to, hz / 5); |
1822 | break; |
1823 | |
1824 | case IEEE80211_S_AUTH: |
1825 | case IEEE80211_S_ASSOC: |
1826 | run_set_chan(sc, ic->ic_curchan); |
1827 | break; |
1828 | |
1829 | case IEEE80211_S_RUN: |
1830 | run_set_chan(sc, ic->ic_curchan); |
1831 | |
1832 | ni = ic->ic_bss; |
1833 | |
1834 | if (ic->ic_opmode != IEEE80211_M_MONITOR) { |
1835 | run_updateslot(ifp); |
1836 | run_enable_mrr(sc); |
1837 | run_set_txpreamble(sc); |
1838 | run_set_basicrates(sc); |
1839 | run_set_bssid(sc, ni->ni_bssid); |
1840 | } |
1841 | #ifndef IEEE80211_STA_ONLY |
1842 | if (ic->ic_opmode == IEEE80211_M_HOSTAP || |
1843 | ic->ic_opmode == IEEE80211_M_IBSS) |
1844 | (void)run_setup_beacon(sc); |
1845 | #endif |
1846 | if (ic->ic_opmode == IEEE80211_M_STA) { |
1847 | /* add BSS entry to the WCID table */ |
1848 | wcid = RUN_AID2WCID(ni->ni_associd); |
1849 | run_write_region_1(sc, RT2860_WCID_ENTRY(wcid), |
1850 | ni->ni_macaddr, IEEE80211_ADDR_LEN); |
1851 | |
1852 | /* fake a join to init the tx rate */ |
1853 | run_newassoc(ni, 1); |
1854 | } |
1855 | if (ic->ic_opmode != IEEE80211_M_MONITOR) { |
1856 | run_enable_tsf_sync(sc); |
1857 | |
1858 | /* clear statistic registers used by AMRR */ |
1859 | run_read_region_1(sc, RT2860_TX_STA_CNT0, |
1860 | (uint8_t *)sta, sizeof(sta)); |
1861 | /* start calibration timer */ |
1862 | callout_schedule(&sc->calib_to, hz); |
1863 | } |
1864 | |
1865 | /* turn link LED on */ |
1866 | run_set_leds(sc, RT2860_LED_RADIO | |
1867 | (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? |
1868 | RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); |
1869 | break; |
1870 | } |
1871 | (void)sc->sc_newstate(ic, cmd->state, cmd->arg); |
1872 | splx(s); |
1873 | } |
1874 | |
1875 | static int |
1876 | run_updateedca(struct ieee80211com *ic) |
1877 | { |
1878 | |
1879 | /* do it in a process context */ |
1880 | run_do_async(ic->ic_ifp->if_softc, run_updateedca_cb, NULL, 0); |
1881 | return 0; |
1882 | } |
1883 | |
1884 | /* ARGSUSED */ |
1885 | static void |
1886 | run_updateedca_cb(struct run_softc *sc, void *arg) |
1887 | { |
1888 | struct ieee80211com *ic = &sc->sc_ic; |
1889 | int s, aci; |
1890 | |
1891 | s = splnet(); |
1892 | /* update MAC TX configuration registers */ |
1893 | for (aci = 0; aci < WME_NUM_AC; aci++) { |
1894 | run_write(sc, RT2860_EDCA_AC_CFG(aci), |
1895 | ic->ic_wme.wme_params[aci].wmep_logcwmax << 16 | |
1896 | ic->ic_wme.wme_params[aci].wmep_logcwmin << 12 | |
1897 | ic->ic_wme.wme_params[aci].wmep_aifsn << 8 | |
1898 | ic->ic_wme.wme_params[aci].wmep_txopLimit); |
1899 | } |
1900 | |
1901 | /* update SCH/DMA registers too */ |
1902 | run_write(sc, RT2860_WMM_AIFSN_CFG, |
1903 | ic->ic_wme.wme_params[WME_AC_VO].wmep_aifsn << 12 | |
1904 | ic->ic_wme.wme_params[WME_AC_VI].wmep_aifsn << 8 | |
1905 | ic->ic_wme.wme_params[WME_AC_BK].wmep_aifsn << 4 | |
1906 | ic->ic_wme.wme_params[WME_AC_BE].wmep_aifsn); |
1907 | run_write(sc, RT2860_WMM_CWMIN_CFG, |
1908 | ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmin << 12 | |
1909 | ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmin << 8 | |
1910 | ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmin << 4 | |
1911 | ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmin); |
1912 | run_write(sc, RT2860_WMM_CWMAX_CFG, |
1913 | ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmax << 12 | |
1914 | ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmax << 8 | |
1915 | ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmax << 4 | |
1916 | ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmax); |
1917 | run_write(sc, RT2860_WMM_TXOP0_CFG, |
1918 | ic->ic_wme.wme_params[WME_AC_BK].wmep_txopLimit << 16 | |
1919 | ic->ic_wme.wme_params[WME_AC_BE].wmep_txopLimit); |
1920 | run_write(sc, RT2860_WMM_TXOP1_CFG, |
1921 | ic->ic_wme.wme_params[WME_AC_VO].wmep_txopLimit << 16 | |
1922 | ic->ic_wme.wme_params[WME_AC_VI].wmep_txopLimit); |
1923 | splx(s); |
1924 | } |
1925 | |
1926 | #ifdef RUN_HWCRYPTO |
1927 | static int |
1928 | run_set_key(struct ieee80211com *ic, const struct ieee80211_key *k, |
1929 | const uint8_t *mac) |
1930 | { |
1931 | struct run_softc *sc = ic->ic_ifp->if_softc; |
1932 | struct ieee80211_node *ni = ic->ic_bss; |
1933 | struct run_cmd_key cmd; |
1934 | |
1935 | /* do it in a process context */ |
1936 | cmd.key = *k; |
1937 | cmd.associd = (ni != NULL) ? ni->ni_associd : 0; |
1938 | run_do_async(sc, run_set_key_cb, &cmd, sizeof(cmd)); |
1939 | return 1; |
1940 | } |
1941 | |
1942 | static void |
1943 | run_set_key_cb(struct run_softc *sc, void *arg) |
1944 | { |
1945 | #ifndef IEEE80211_STA_ONLY |
1946 | struct ieee80211com *ic = &sc->sc_ic; |
1947 | #endif |
1948 | struct run_cmd_key *cmd = arg; |
1949 | struct ieee80211_key *k = &cmd->key; |
1950 | uint32_t attr; |
1951 | uint16_t base; |
1952 | uint8_t mode, wcid, iv[8]; |
1953 | |
1954 | /* map net80211 cipher to RT2860 security mode */ |
1955 | switch (k->wk_cipher->ic_cipher) { |
1956 | case IEEE80211_CIPHER_WEP: |
1957 | k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ |
1958 | if (k->wk_keylen == 5) |
1959 | mode = RT2860_MODE_WEP40; |
1960 | else |
1961 | mode = RT2860_MODE_WEP104; |
1962 | break; |
1963 | case IEEE80211_CIPHER_TKIP: |
1964 | mode = RT2860_MODE_TKIP; |
1965 | break; |
1966 | case IEEE80211_CIPHER_AES_CCM: |
1967 | mode = RT2860_MODE_AES_CCMP; |
1968 | break; |
1969 | default: |
1970 | return; |
1971 | } |
1972 | |
1973 | if (k->wk_flags & IEEE80211_KEY_GROUP) { |
1974 | wcid = 0; /* NB: update WCID0 for group keys */ |
1975 | base = RT2860_SKEY(0, k->wk_keyix); |
1976 | } else { |
1977 | wcid = RUN_AID2WCID(cmd->associd); |
1978 | base = RT2860_PKEY(wcid); |
1979 | } |
1980 | |
1981 | if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { |
1982 | run_write_region_1(sc, base, k->wk_key, 16); |
1983 | #ifndef IEEE80211_STA_ONLY |
1984 | if (ic->ic_opmode == IEEE80211_M_HOSTAP) { |
1985 | run_write_region_1(sc, base + 16, &k->wk_key[16], 8); |
1986 | run_write_region_1(sc, base + 24, &k->wk_key[24], 8); |
1987 | } else |
1988 | #endif |
1989 | { |
1990 | run_write_region_1(sc, base + 16, &k->wk_key[24], 8); |
1991 | run_write_region_1(sc, base + 24, &k->wk_key[16], 8); |
1992 | } |
1993 | } else { |
1994 | /* roundup len to 16-bit: XXX fix write_region_1() instead */ |
1995 | run_write_region_1(sc, base, k->wk_key, |
1996 | (k->wk_keylen + 1) & ~1); |
1997 | } |
1998 | |
1999 | if (!(k->wk_flags & IEEE80211_KEY_GROUP) || |
2000 | (k->wk_flags & IEEE80211_KEY_XMIT)) { |
2001 | /* set initial packet number in IV+EIV */ |
2002 | if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { |
2003 | memset(iv, 0, sizeof(iv)); |
2004 | iv[3] = sc->sc_ic.ic_crypto.cs_def_txkey << 6; |
2005 | } else { |
2006 | if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { |
2007 | iv[0] = k->wk_keytsc >> 8; |
2008 | iv[1] = (iv[0] | 0x20) & 0x7f; |
2009 | iv[2] = k->wk_keytsc; |
2010 | } else /* CCMP */ { |
2011 | iv[0] = k->wk_keytsc; |
2012 | iv[1] = k->wk_keytsc >> 8; |
2013 | iv[2] = 0; |
2014 | } |
2015 | iv[3] = k->wk_keyix << 6 | IEEE80211_WEP_EXTIV; |
2016 | iv[4] = k->wk_keytsc >> 16; |
2017 | iv[5] = k->wk_keytsc >> 24; |
2018 | iv[6] = k->wk_keytsc >> 32; |
2019 | iv[7] = k->wk_keytsc >> 40; |
2020 | } |
2021 | run_write_region_1(sc, RT2860_IVEIV(wcid), iv, 8); |
2022 | } |
2023 | |
2024 | if (k->wk_flags & IEEE80211_KEY_GROUP) { |
2025 | /* install group key */ |
2026 | run_read(sc, RT2860_SKEY_MODE_0_7, &attr); |
2027 | attr &= ~(0xf << (k->wk_keyix * 4)); |
2028 | attr |= mode << (k->wk_keyix * 4); |
2029 | run_write(sc, RT2860_SKEY_MODE_0_7, attr); |
2030 | } else { |
2031 | /* install pairwise key */ |
2032 | run_read(sc, RT2860_WCID_ATTR(wcid), &attr); |
2033 | attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; |
2034 | run_write(sc, RT2860_WCID_ATTR(wcid), attr); |
2035 | } |
2036 | } |
2037 | |
2038 | static int |
2039 | run_delete_key(struct ieee80211com *ic, const struct ieee80211_key *k) |
2040 | { |
2041 | struct run_softc *sc = ic->ic_ifp->if_softc; |
2042 | struct ieee80211_node *ni = ic->ic_bss; |
2043 | struct run_cmd_key cmd; |
2044 | |
2045 | /* do it in a process context */ |
2046 | cmd.key = *k; |
2047 | cmd.associd = (ni != NULL) ? ni->ni_associd : 0; |
2048 | run_do_async(sc, run_delete_key_cb, &cmd, sizeof(cmd)); |
2049 | return 1; |
2050 | } |
2051 | |
2052 | static void |
2053 | run_delete_key_cb(struct run_softc *sc, void *arg) |
2054 | { |
2055 | struct run_cmd_key *cmd = arg; |
2056 | struct ieee80211_key *k = &cmd->key; |
2057 | uint32_t attr; |
2058 | uint8_t wcid; |
2059 | |
2060 | if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) |
2061 | k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ |
2062 | |
2063 | if (k->wk_flags & IEEE80211_KEY_GROUP) { |
2064 | /* remove group key */ |
2065 | run_read(sc, RT2860_SKEY_MODE_0_7, &attr); |
2066 | attr &= ~(0xf << (k->wk_keyix * 4)); |
2067 | run_write(sc, RT2860_SKEY_MODE_0_7, attr); |
2068 | |
2069 | } else { |
2070 | /* remove pairwise key */ |
2071 | wcid = RUN_AID2WCID(cmd->associd); |
2072 | run_read(sc, RT2860_WCID_ATTR(wcid), &attr); |
2073 | attr &= ~0xf; |
2074 | run_write(sc, RT2860_WCID_ATTR(wcid), attr); |
2075 | } |
2076 | } |
2077 | #endif |
2078 | |
2079 | static void |
2080 | run_calibrate_to(void *arg) |
2081 | { |
2082 | |
2083 | /* do it in a process context */ |
2084 | run_do_async(arg, run_calibrate_cb, NULL, 0); |
2085 | /* next timeout will be rescheduled in the calibration task */ |
2086 | } |
2087 | |
2088 | /* ARGSUSED */ |
2089 | static void |
2090 | run_calibrate_cb(struct run_softc *sc, void *arg) |
2091 | { |
2092 | struct ifnet *ifp = &sc->sc_if; |
2093 | uint32_t sta[3]; |
2094 | int s, error; |
2095 | |
2096 | /* read statistic counters (clear on read) and update AMRR state */ |
2097 | error = run_read_region_1(sc, RT2860_TX_STA_CNT0, (uint8_t *)sta, |
2098 | sizeof(sta)); |
2099 | if (error != 0) |
2100 | goto skip; |
2101 | |
2102 | DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n" , |
2103 | le32toh(sta[1]) >> 16, le32toh(sta[1]) & 0xffff, |
2104 | le32toh(sta[0]) & 0xffff)); |
2105 | |
2106 | s = splnet(); |
2107 | /* count failed TX as errors */ |
2108 | ifp->if_oerrors += le32toh(sta[0]) & 0xffff; |
2109 | |
2110 | sc->amn.amn_retrycnt = |
2111 | (le32toh(sta[0]) & 0xffff) + /* failed TX count */ |
2112 | (le32toh(sta[1]) >> 16); /* TX retransmission count */ |
2113 | |
2114 | sc->amn.amn_txcnt = |
2115 | sc->amn.amn_retrycnt + |
2116 | (le32toh(sta[1]) & 0xffff); /* successful TX count */ |
2117 | |
2118 | ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); |
2119 | splx(s); |
2120 | |
2121 | skip: callout_schedule(&sc->calib_to, hz); |
2122 | } |
2123 | |
2124 | static void |
2125 | run_newassoc(struct ieee80211_node *ni, int isnew) |
2126 | { |
2127 | struct run_softc *sc = ni->ni_ic->ic_ifp->if_softc; |
2128 | struct run_node *rn = (void *)ni; |
2129 | struct ieee80211_rateset *rs = &ni->ni_rates; |
2130 | uint8_t rate; |
2131 | int ridx, i, j; |
2132 | |
2133 | DPRINTF(("new assoc isnew=%d addr=%s\n" , |
2134 | isnew, ether_sprintf(ni->ni_macaddr))); |
2135 | |
2136 | ieee80211_amrr_node_init(&sc->amrr, &sc->amn); |
2137 | /* start at lowest available bit-rate, AMRR will raise */ |
2138 | ni->ni_txrate = 0; |
2139 | |
2140 | for (i = 0; i < rs->rs_nrates; i++) { |
2141 | rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; |
2142 | /* convert 802.11 rate to hardware rate index */ |
2143 | for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) |
2144 | if (rt2860_rates[ridx].rate == rate) |
2145 | break; |
2146 | rn->ridx[i] = ridx; |
2147 | /* determine rate of control response frames */ |
2148 | for (j = i; j >= 0; j--) { |
2149 | if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && |
2150 | rt2860_rates[rn->ridx[i]].phy == |
2151 | rt2860_rates[rn->ridx[j]].phy) |
2152 | break; |
2153 | } |
2154 | if (j >= 0) { |
2155 | rn->ctl_ridx[i] = rn->ridx[j]; |
2156 | } else { |
2157 | /* no basic rate found, use mandatory one */ |
2158 | rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; |
2159 | } |
2160 | DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n" , |
2161 | rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); |
2162 | } |
2163 | } |
2164 | |
2165 | /* |
2166 | * Return the Rx chain with the highest RSSI for a given frame. |
2167 | */ |
2168 | static __inline uint8_t |
2169 | (struct run_softc *sc, const struct rt2860_rxwi *rxwi) |
2170 | { |
2171 | uint8_t rxchain = 0; |
2172 | |
2173 | if (sc->nrxchains > 1) { |
2174 | if (rxwi->rssi[1] > rxwi->rssi[rxchain]) |
2175 | rxchain = 1; |
2176 | if (sc->nrxchains > 2) |
2177 | if (rxwi->rssi[2] > rxwi->rssi[rxchain]) |
2178 | rxchain = 2; |
2179 | } |
2180 | return rxchain; |
2181 | } |
2182 | |
2183 | static void |
2184 | run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen) |
2185 | { |
2186 | struct ieee80211com *ic = &sc->sc_ic; |
2187 | struct ifnet *ifp = &sc->sc_if; |
2188 | struct ieee80211_frame *wh; |
2189 | struct ieee80211_node *ni; |
2190 | struct rt2870_rxd *rxd; |
2191 | struct rt2860_rxwi *rxwi; |
2192 | struct mbuf *m; |
2193 | uint32_t flags; |
2194 | uint16_t len, rxwisize, phy; |
2195 | uint8_t ant, ; |
2196 | int s; |
2197 | #ifdef RUN_HWCRYPTO |
2198 | int decrypted = 0; |
2199 | #endif |
2200 | |
2201 | rxwi = (struct rt2860_rxwi *)buf; |
2202 | len = le16toh(rxwi->len) & 0xfff; |
2203 | if (__predict_false(len > dmalen)) { |
2204 | DPRINTF(("bad RXWI length %u > %u\n" , len, dmalen)); |
2205 | return; |
2206 | } |
2207 | /* Rx descriptor is located at the end */ |
2208 | rxd = (struct rt2870_rxd *)(buf + dmalen); |
2209 | flags = le32toh(rxd->flags); |
2210 | |
2211 | if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { |
2212 | ifp->if_ierrors++; |
2213 | return; |
2214 | } |
2215 | |
2216 | rxwisize = sizeof(struct rt2860_rxwi); |
2217 | if (sc->mac_ver == 0x5592) |
2218 | rxwisize += sizeof(uint64_t); |
2219 | else if (sc->mac_ver == 0x3593) |
2220 | rxwisize += sizeof(uint32_t); |
2221 | |
2222 | wh = (struct ieee80211_frame *)(((uint8_t *)rxwi) + rxwisize); |
2223 | #ifdef RUN_HWCRYPTO |
2224 | if (wh->i_fc[1] & IEEE80211_FC1_WEP) { |
2225 | wh->i_fc[1] &= ~IEEE80211_FC1_WEP; |
2226 | decrypted = 1; |
2227 | } |
2228 | #endif |
2229 | |
2230 | if (__predict_false((flags & RT2860_RX_MICERR))) { |
2231 | /* report MIC failures to net80211 for TKIP */ |
2232 | ieee80211_notify_michael_failure(ic, wh, 0/* XXX */); |
2233 | ifp->if_ierrors++; |
2234 | return; |
2235 | } |
2236 | |
2237 | if (flags & RT2860_RX_L2PAD) { |
2238 | u_int hdrlen = ieee80211_hdrspace(ic, wh); |
2239 | ovbcopy(wh, (uint8_t *)wh + 2, hdrlen); |
2240 | wh = (struct ieee80211_frame *)((uint8_t *)wh + 2); |
2241 | } |
2242 | |
2243 | /* could use m_devget but net80211 wants contig mgmt frames */ |
2244 | MGETHDR(m, M_DONTWAIT, MT_DATA); |
2245 | if (__predict_false(m == NULL)) { |
2246 | ifp->if_ierrors++; |
2247 | return; |
2248 | } |
2249 | if (len > MHLEN) { |
2250 | MCLGET(m, M_DONTWAIT); |
2251 | if (__predict_false(!(m->m_flags & M_EXT))) { |
2252 | ifp->if_ierrors++; |
2253 | m_freem(m); |
2254 | return; |
2255 | } |
2256 | } |
2257 | /* finalize mbuf */ |
2258 | m_set_rcvif(m, ifp); |
2259 | memcpy(mtod(m, void *), wh, len); |
2260 | m->m_pkthdr.len = m->m_len = len; |
2261 | |
2262 | ant = run_maxrssi_chain(sc, rxwi); |
2263 | rssi = rxwi->rssi[ant]; |
2264 | |
2265 | if (__predict_false(sc->sc_drvbpf != NULL)) { |
2266 | struct run_rx_radiotap_header *tap = &sc->sc_rxtap; |
2267 | |
2268 | tap->wr_flags = 0; |
2269 | tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); |
2270 | tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); |
2271 | tap->wr_antsignal = rssi; |
2272 | tap->wr_antenna = ant; |
2273 | tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); |
2274 | tap->wr_rate = 2; /* in case it can't be found below */ |
2275 | phy = le16toh(rxwi->phy); |
2276 | switch (phy & RT2860_PHY_MODE) { |
2277 | case RT2860_PHY_CCK: |
2278 | switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { |
2279 | case 0: tap->wr_rate = 2; break; |
2280 | case 1: tap->wr_rate = 4; break; |
2281 | case 2: tap->wr_rate = 11; break; |
2282 | case 3: tap->wr_rate = 22; break; |
2283 | } |
2284 | if (phy & RT2860_PHY_SHPRE) |
2285 | tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; |
2286 | break; |
2287 | case RT2860_PHY_OFDM: |
2288 | switch (phy & RT2860_PHY_MCS) { |
2289 | case 0: tap->wr_rate = 12; break; |
2290 | case 1: tap->wr_rate = 18; break; |
2291 | case 2: tap->wr_rate = 24; break; |
2292 | case 3: tap->wr_rate = 36; break; |
2293 | case 4: tap->wr_rate = 48; break; |
2294 | case 5: tap->wr_rate = 72; break; |
2295 | case 6: tap->wr_rate = 96; break; |
2296 | case 7: tap->wr_rate = 108; break; |
2297 | } |
2298 | break; |
2299 | } |
2300 | bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); |
2301 | } |
2302 | |
2303 | s = splnet(); |
2304 | ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); |
2305 | #ifdef RUN_HWCRYPTO |
2306 | if (decrypted) { |
2307 | uint32_t icflags = ic->ic_flags; |
2308 | |
2309 | ic->ic_flags &= ~IEEE80211_F_DROPUNENC; /* XXX */ |
2310 | ieee80211_input(ic, m, ni, rssi, 0); |
2311 | ic->ic_flags = icflags; |
2312 | } else |
2313 | #endif |
2314 | ieee80211_input(ic, m, ni, rssi, 0); |
2315 | |
2316 | /* node is no longer needed */ |
2317 | ieee80211_free_node(ni); |
2318 | |
2319 | /* |
2320 | * In HostAP mode, ieee80211_input() will enqueue packets in if_snd |
2321 | * without calling if_start(). |
2322 | */ |
2323 | if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) |
2324 | run_start(ifp); |
2325 | |
2326 | splx(s); |
2327 | } |
2328 | |
2329 | static void |
2330 | run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) |
2331 | { |
2332 | struct run_rx_data *data = priv; |
2333 | struct run_softc *sc = data->sc; |
2334 | uint8_t *buf; |
2335 | uint32_t dmalen; |
2336 | int xferlen; |
2337 | |
2338 | if (__predict_false(sc->sc_flags & RUN_DETACHING)) |
2339 | return; |
2340 | |
2341 | if (__predict_false(status != USBD_NORMAL_COMPLETION)) { |
2342 | DPRINTF(("RX status=%d\n" , status)); |
2343 | if (status == USBD_STALLED) |
2344 | usbd_clear_endpoint_stall_async(sc->rxq.pipeh); |
2345 | if (status != USBD_CANCELLED) |
2346 | goto skip; |
2347 | return; |
2348 | } |
2349 | usbd_get_xfer_status(xfer, NULL, NULL, &xferlen, NULL); |
2350 | |
2351 | if (__predict_false(xferlen < (int)(sizeof(uint32_t) + |
2352 | sizeof(struct rt2860_rxwi) + sizeof(struct rt2870_rxd)))) { |
2353 | DPRINTF(("xfer too short %d\n" , xferlen)); |
2354 | goto skip; |
2355 | } |
2356 | |
2357 | /* HW can aggregate multiple 802.11 frames in a single USB xfer */ |
2358 | buf = data->buf; |
2359 | while (xferlen > 8) { |
2360 | dmalen = le32toh(*(uint32_t *)buf) & 0xffff; |
2361 | |
2362 | if (__predict_false((dmalen >= (uint32_t)-8) || dmalen == 0 || |
2363 | (dmalen & 3) != 0)) { |
2364 | DPRINTF(("bad DMA length %u (%x)\n" , dmalen, dmalen)); |
2365 | break; |
2366 | } |
2367 | if (__predict_false(dmalen + 8 > (uint32_t)xferlen)) { |
2368 | DPRINTF(("bad DMA length %u > %d\n" , |
2369 | dmalen + 8, xferlen)); |
2370 | break; |
2371 | } |
2372 | run_rx_frame(sc, buf + sizeof(uint32_t), dmalen); |
2373 | buf += dmalen + 8; |
2374 | xferlen -= dmalen + 8; |
2375 | } |
2376 | |
2377 | skip: /* setup a new transfer */ |
2378 | usbd_setup_xfer(xfer, data, data->buf, RUN_MAX_RXSZ, |
2379 | USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); |
2380 | (void)usbd_transfer(xfer); |
2381 | } |
2382 | |
2383 | static void |
2384 | run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) |
2385 | { |
2386 | struct run_tx_data *data = priv; |
2387 | struct run_softc *sc = data->sc; |
2388 | struct run_tx_ring *txq = &sc->txq[data->qid]; |
2389 | struct ifnet *ifp = &sc->sc_if; |
2390 | int s; |
2391 | |
2392 | if (__predict_false(status != USBD_NORMAL_COMPLETION)) { |
2393 | DPRINTF(("TX status=%d\n" , status)); |
2394 | if (status == USBD_STALLED) |
2395 | usbd_clear_endpoint_stall_async(txq->pipeh); |
2396 | ifp->if_oerrors++; |
2397 | return; |
2398 | } |
2399 | |
2400 | s = splnet(); |
2401 | sc->sc_tx_timer = 0; |
2402 | ifp->if_opackets++; |
2403 | if (--txq->queued < RUN_TX_RING_COUNT) { |
2404 | sc->qfullmsk &= ~(1 << data->qid); |
2405 | ifp->if_flags &= ~IFF_OACTIVE; |
2406 | run_start(ifp); |
2407 | } |
2408 | splx(s); |
2409 | } |
2410 | |
2411 | static int |
2412 | run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) |
2413 | { |
2414 | struct ieee80211com *ic = &sc->sc_ic; |
2415 | struct run_node *rn = (void *)ni; |
2416 | struct ieee80211_frame *wh; |
2417 | #ifndef RUN_HWCRYPTO |
2418 | struct ieee80211_key *k; |
2419 | #endif |
2420 | struct run_tx_ring *ring; |
2421 | struct run_tx_data *data; |
2422 | struct rt2870_txd *txd; |
2423 | struct rt2860_txwi *txwi; |
2424 | uint16_t dur, mcs; |
2425 | uint8_t type, tid, qid, qos = 0; |
2426 | int error, hasqos, ridx, ctl_ridx, xferlen, txwisize; |
2427 | uint8_t pad; |
2428 | |
2429 | wh = mtod(m, struct ieee80211_frame *); |
2430 | |
2431 | #ifndef RUN_HWCRYPTO |
2432 | if (wh->i_fc[1] & IEEE80211_FC1_WEP) { |
2433 | k = ieee80211_crypto_encap(ic, ni, m); |
2434 | if (k == NULL) { |
2435 | m_freem(m); |
2436 | return ENOBUFS; |
2437 | } |
2438 | |
2439 | /* packet header may have moved, reset our local pointer */ |
2440 | wh = mtod(m, struct ieee80211_frame *); |
2441 | } |
2442 | #endif |
2443 | type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; |
2444 | |
2445 | if ((hasqos = ieee80211_has_qos(wh))) { |
2446 | qos = ((struct ieee80211_qosframe *)wh)->i_qos[0]; |
2447 | tid = qos & IEEE80211_QOS_TID; |
2448 | qid = TID_TO_WME_AC(tid); |
2449 | } else { |
2450 | tid = 0; |
2451 | qid = WME_AC_BE; |
2452 | } |
2453 | ring = &sc->txq[qid]; |
2454 | data = &ring->data[ring->cur]; |
2455 | |
2456 | /* pickup a rate index */ |
2457 | if (IEEE80211_IS_MULTICAST(wh->i_addr1) || |
2458 | type != IEEE80211_FC0_TYPE_DATA) { |
2459 | ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? |
2460 | RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; |
2461 | ctl_ridx = rt2860_rates[ridx].ctl_ridx; |
2462 | } else if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { |
2463 | ridx = sc->fixed_ridx; |
2464 | ctl_ridx = rt2860_rates[ridx].ctl_ridx; |
2465 | } else { |
2466 | ridx = rn->ridx[ni->ni_txrate]; |
2467 | ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; |
2468 | } |
2469 | |
2470 | /* get MCS code from rate index */ |
2471 | mcs = rt2860_rates[ridx].mcs; |
2472 | |
2473 | txwisize = (sc->mac_ver == 0x5592) ? |
2474 | sizeof(*txwi) + sizeof(uint32_t) : sizeof(*txwi); |
2475 | xferlen = txwisize + m->m_pkthdr.len; |
2476 | /* roundup to 32-bit alignment */ |
2477 | xferlen = (xferlen + 3) & ~3; |
2478 | |
2479 | txd = (struct rt2870_txd *)data->buf; |
2480 | txd->flags = RT2860_TX_QSEL_EDCA; |
2481 | txd->len = htole16(xferlen); |
2482 | |
2483 | /* |
2484 | * Ether both are true or both are false, the header |
2485 | * are nicely aligned to 32-bit. So, no L2 padding. |
2486 | */ |
2487 | if (IEEE80211_HAS_ADDR4(wh) == IEEE80211_QOS_HAS_SEQ(wh)) |
2488 | pad = 0; |
2489 | else |
2490 | pad = 2; |
2491 | |
2492 | /* setup TX Wireless Information */ |
2493 | txwi = (struct rt2860_txwi *)(txd + 1); |
2494 | txwi->flags = 0; |
2495 | txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; |
2496 | txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? |
2497 | RUN_AID2WCID(ni->ni_associd) : 0xff; |
2498 | txwi->len = htole16(m->m_pkthdr.len - pad); |
2499 | if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { |
2500 | txwi->phy = htole16(RT2860_PHY_CCK); |
2501 | if (ridx != RT2860_RIDX_CCK1 && |
2502 | (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) |
2503 | mcs |= RT2860_PHY_SHPRE; |
2504 | } else |
2505 | mcs |= RT2860_PHY_OFDM; |
2506 | txwi->phy |= htole16(mcs); |
2507 | |
2508 | txwi->txop = RT2860_TX_TXOP_BACKOFF; |
2509 | |
2510 | if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && |
2511 | (!hasqos || (qos & IEEE80211_QOS_ACKPOLICY) != |
2512 | IEEE80211_QOS_ACKPOLICY_NOACK)) { |
2513 | txwi->xflags |= RT2860_TX_ACK; |
2514 | if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) |
2515 | dur = rt2860_rates[ctl_ridx].sp_ack_dur; |
2516 | else |
2517 | dur = rt2860_rates[ctl_ridx].lp_ack_dur; |
2518 | *(uint16_t *)wh->i_dur = htole16(dur); |
2519 | } |
2520 | |
2521 | #ifndef IEEE80211_STA_ONLY |
2522 | /* ask MAC to insert timestamp into probe responses */ |
2523 | if ((wh->i_fc[0] & |
2524 | (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == |
2525 | (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) |
2526 | /* NOTE: beacons do not pass through tx_data() */ |
2527 | txwi->flags |= RT2860_TX_TS; |
2528 | #endif |
2529 | |
2530 | if (__predict_false(sc->sc_drvbpf != NULL)) { |
2531 | struct run_tx_radiotap_header *tap = &sc->sc_txtap; |
2532 | |
2533 | tap->wt_flags = 0; |
2534 | tap->wt_rate = rt2860_rates[ridx].rate; |
2535 | tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); |
2536 | tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); |
2537 | tap->wt_hwqueue = qid; |
2538 | if (mcs & RT2860_PHY_SHPRE) |
2539 | tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; |
2540 | |
2541 | bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); |
2542 | } |
2543 | |
2544 | m_copydata(m, 0, m->m_pkthdr.len, ((uint8_t *)txwi) + txwisize); |
2545 | m_freem(m); |
2546 | |
2547 | xferlen += sizeof(*txd) + 4; |
2548 | |
2549 | usbd_setup_xfer(data->xfer, data, data->buf, xferlen, |
2550 | USBD_FORCE_SHORT_XFER, RUN_TX_TIMEOUT, run_txeof); |
2551 | error = usbd_transfer(data->xfer); |
2552 | if (__predict_false(error != USBD_IN_PROGRESS && |
2553 | error != USBD_NORMAL_COMPLETION)) |
2554 | return error; |
2555 | |
2556 | ieee80211_free_node(ni); |
2557 | |
2558 | ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT; |
2559 | if (++ring->queued >= RUN_TX_RING_COUNT) |
2560 | sc->qfullmsk |= 1 << qid; |
2561 | |
2562 | return 0; |
2563 | } |
2564 | |
2565 | static void |
2566 | run_start(struct ifnet *ifp) |
2567 | { |
2568 | struct run_softc *sc = ifp->if_softc; |
2569 | struct ieee80211com *ic = &sc->sc_ic; |
2570 | struct ether_header *eh; |
2571 | struct ieee80211_node *ni; |
2572 | struct mbuf *m; |
2573 | |
2574 | if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) |
2575 | return; |
2576 | |
2577 | for (;;) { |
2578 | if (sc->qfullmsk != 0) { |
2579 | ifp->if_flags |= IFF_OACTIVE; |
2580 | break; |
2581 | } |
2582 | /* send pending management frames first */ |
2583 | IF_DEQUEUE(&ic->ic_mgtq, m); |
2584 | if (m != NULL) { |
2585 | ni = M_GETCTX(m, struct ieee80211_node *); |
2586 | M_CLEARCTX(m); |
2587 | goto sendit; |
2588 | } |
2589 | if (ic->ic_state != IEEE80211_S_RUN) |
2590 | break; |
2591 | |
2592 | /* encapsulate and send data frames */ |
2593 | IFQ_DEQUEUE(&ifp->if_snd, m); |
2594 | if (m == NULL) |
2595 | break; |
2596 | if (m->m_len < (int)sizeof(*eh) && |
2597 | (m = m_pullup(m, sizeof(*eh))) == NULL) { |
2598 | ifp->if_oerrors++; |
2599 | continue; |
2600 | } |
2601 | |
2602 | eh = mtod(m, struct ether_header *); |
2603 | ni = ieee80211_find_txnode(ic, eh->ether_dhost); |
2604 | if (ni == NULL) { |
2605 | m_freem(m); |
2606 | ifp->if_oerrors++; |
2607 | continue; |
2608 | } |
2609 | |
2610 | bpf_mtap(ifp, m); |
2611 | |
2612 | if ((m = ieee80211_encap(ic, m, ni)) == NULL) { |
2613 | ieee80211_free_node(ni); |
2614 | ifp->if_oerrors++; |
2615 | continue; |
2616 | } |
2617 | sendit: |
2618 | bpf_mtap3(ic->ic_rawbpf, m); |
2619 | |
2620 | if (run_tx(sc, m, ni) != 0) { |
2621 | ieee80211_free_node(ni); |
2622 | ifp->if_oerrors++; |
2623 | continue; |
2624 | } |
2625 | |
2626 | sc->sc_tx_timer = 5; |
2627 | ifp->if_timer = 1; |
2628 | } |
2629 | } |
2630 | |
2631 | static void |
2632 | run_watchdog(struct ifnet *ifp) |
2633 | { |
2634 | struct run_softc *sc = ifp->if_softc; |
2635 | struct ieee80211com *ic = &sc->sc_ic; |
2636 | |
2637 | ifp->if_timer = 0; |
2638 | |
2639 | if (sc->sc_tx_timer > 0) { |
2640 | if (--sc->sc_tx_timer == 0) { |
2641 | aprint_error_dev(sc->sc_dev, "device timeout\n" ); |
2642 | /* run_init(ifp); XXX needs a process context! */ |
2643 | ifp->if_oerrors++; |
2644 | return; |
2645 | } |
2646 | ifp->if_timer = 1; |
2647 | } |
2648 | |
2649 | ieee80211_watchdog(ic); |
2650 | } |
2651 | |
2652 | static int |
2653 | run_ioctl(struct ifnet *ifp, u_long cmd, void *data) |
2654 | { |
2655 | struct run_softc *sc = ifp->if_softc; |
2656 | struct ieee80211com *ic = &sc->sc_ic; |
2657 | int s, error = 0; |
2658 | |
2659 | s = splnet(); |
2660 | |
2661 | switch (cmd) { |
2662 | case SIOCSIFFLAGS: |
2663 | if ((error = ifioctl_common(ifp, cmd, data)) != 0) |
2664 | break; |
2665 | switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { |
2666 | case IFF_UP|IFF_RUNNING: |
2667 | break; |
2668 | case IFF_UP: |
2669 | run_init(ifp); |
2670 | break; |
2671 | case IFF_RUNNING: |
2672 | run_stop(ifp, 1); |
2673 | break; |
2674 | case 0: |
2675 | break; |
2676 | } |
2677 | break; |
2678 | |
2679 | case SIOCADDMULTI: |
2680 | case SIOCDELMULTI: |
2681 | if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { |
2682 | /* setup multicast filter, etc */ |
2683 | error = 0; |
2684 | } |
2685 | break; |
2686 | |
2687 | default: |
2688 | error = ieee80211_ioctl(ic, cmd, data); |
2689 | break; |
2690 | } |
2691 | |
2692 | if (error == ENETRESET) { |
2693 | if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == |
2694 | (IFF_UP | IFF_RUNNING)) { |
2695 | run_init(ifp); |
2696 | } |
2697 | error = 0; |
2698 | } |
2699 | |
2700 | splx(s); |
2701 | |
2702 | return error; |
2703 | } |
2704 | |
2705 | static void |
2706 | run_select_chan_group(struct run_softc *sc, int group) |
2707 | { |
2708 | uint32_t tmp; |
2709 | uint8_t agc; |
2710 | |
2711 | run_bbp_write(sc, 62, 0x37 - sc->lna[group]); |
2712 | run_bbp_write(sc, 63, 0x37 - sc->lna[group]); |
2713 | run_bbp_write(sc, 64, 0x37 - sc->lna[group]); |
2714 | run_bbp_write(sc, 86, 0x00); |
2715 | |
2716 | if (group == 0) { |
2717 | if (sc->ext_2ghz_lna) { |
2718 | run_bbp_write(sc, 82, 0x62); |
2719 | run_bbp_write(sc, 75, 0x46); |
2720 | } else { |
2721 | run_bbp_write(sc, 82, 0x84); |
2722 | run_bbp_write(sc, 75, 0x50); |
2723 | } |
2724 | } else { |
2725 | if (sc->mac_ver == 0x3572) |
2726 | run_bbp_write(sc, 82, 0x94); |
2727 | else |
2728 | run_bbp_write(sc, 82, 0xf2); |
2729 | if (sc->ext_5ghz_lna) |
2730 | run_bbp_write(sc, 75, 0x46); |
2731 | else |
2732 | run_bbp_write(sc, 75, 0x50); |
2733 | } |
2734 | |
2735 | run_read(sc, RT2860_TX_BAND_CFG, &tmp); |
2736 | tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); |
2737 | tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; |
2738 | run_write(sc, RT2860_TX_BAND_CFG, tmp); |
2739 | |
2740 | /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ |
2741 | tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; |
2742 | if (sc->nrxchains > 1) |
2743 | tmp |= RT2860_LNA_PE1_EN; |
2744 | if (group == 0) { /* 2GHz */ |
2745 | tmp |= RT2860_PA_PE_G0_EN; |
2746 | if (sc->ntxchains > 1) |
2747 | tmp |= RT2860_PA_PE_G1_EN; |
2748 | } else { /* 5GHz */ |
2749 | tmp |= RT2860_PA_PE_A0_EN; |
2750 | if (sc->ntxchains > 1) |
2751 | tmp |= RT2860_PA_PE_A1_EN; |
2752 | } |
2753 | if (sc->mac_ver == 0x3572) { |
2754 | run_rt3070_rf_write(sc, 8, 0x00); |
2755 | run_write(sc, RT2860_TX_PIN_CFG, tmp); |
2756 | run_rt3070_rf_write(sc, 8, 0x80); |
2757 | } else |
2758 | run_write(sc, RT2860_TX_PIN_CFG, tmp); |
2759 | |
2760 | /* set initial AGC value */ |
2761 | if (group == 0) { /* 2GHz band */ |
2762 | if (sc->mac_ver >= 0x3070) |
2763 | agc = 0x1c + sc->lna[0] * 2; |
2764 | else |
2765 | agc = 0x2e + sc->lna[0]; |
2766 | } else { /* 5GHz band */ |
2767 | if (sc->mac_ver == 0x3572) |
2768 | agc = 0x22 + (sc->lna[group] * 5) / 3; |
2769 | else |
2770 | agc = 0x32 + (sc->lna[group] * 5) / 3; |
2771 | } |
2772 | run_set_agc(sc, agc); |
2773 | } |
2774 | |
2775 | static void |
2776 | run_rt2870_set_chan(struct run_softc *sc, u_int chan) |
2777 | { |
2778 | const struct rfprog *rfprog = rt2860_rf2850; |
2779 | uint32_t r2, r3, r4; |
2780 | int8_t txpow1, txpow2; |
2781 | int i; |
2782 | |
2783 | /* find the settings for this channel (we know it exists) */ |
2784 | for (i = 0; rfprog[i].chan != chan; i++); |
2785 | |
2786 | r2 = rfprog[i].r2; |
2787 | if (sc->ntxchains == 1) |
2788 | r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ |
2789 | if (sc->nrxchains == 1) |
2790 | r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ |
2791 | else if (sc->nrxchains == 2) |
2792 | r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ |
2793 | |
2794 | /* use Tx power values from EEPROM */ |
2795 | txpow1 = sc->txpow1[i]; |
2796 | txpow2 = sc->txpow2[i]; |
2797 | if (chan > 14) { |
2798 | if (txpow1 >= 0) |
2799 | txpow1 = txpow1 << 1 | 1; |
2800 | else |
2801 | txpow1 = (7 + txpow1) << 1; |
2802 | if (txpow2 >= 0) |
2803 | txpow2 = txpow2 << 1 | 1; |
2804 | else |
2805 | txpow2 = (7 + txpow2) << 1; |
2806 | } |
2807 | r3 = rfprog[i].r3 | txpow1 << 7; |
2808 | r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; |
2809 | |
2810 | run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); |
2811 | run_rt2870_rf_write(sc, RT2860_RF2, r2); |
2812 | run_rt2870_rf_write(sc, RT2860_RF3, r3); |
2813 | run_rt2870_rf_write(sc, RT2860_RF4, r4); |
2814 | |
2815 | usbd_delay_ms(sc->sc_udev, 10); |
2816 | |
2817 | run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); |
2818 | run_rt2870_rf_write(sc, RT2860_RF2, r2); |
2819 | run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1); |
2820 | run_rt2870_rf_write(sc, RT2860_RF4, r4); |
2821 | |
2822 | usbd_delay_ms(sc->sc_udev, 10); |
2823 | |
2824 | run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); |
2825 | run_rt2870_rf_write(sc, RT2860_RF2, r2); |
2826 | run_rt2870_rf_write(sc, RT2860_RF3, r3); |
2827 | run_rt2870_rf_write(sc, RT2860_RF4, r4); |
2828 | } |
2829 | |
2830 | static void |
2831 | run_rt3070_set_chan(struct run_softc *sc, u_int chan) |
2832 | { |
2833 | int8_t txpow1, txpow2; |
2834 | uint8_t rf; |
2835 | int i; |
2836 | |
2837 | KASSERT(chan >= 1 && chan <= 14); /* RT3070 is 2GHz only */ |
2838 | |
2839 | /* find the settings for this channel (we know it exists) */ |
2840 | for (i = 0; rt2860_rf2850[i].chan != chan; i++) |
2841 | continue; |
2842 | |
2843 | /* use Tx power values from EEPROM */ |
2844 | txpow1 = sc->txpow1[i]; |
2845 | txpow2 = sc->txpow2[i]; |
2846 | |
2847 | run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); |
2848 | run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); |
2849 | run_rt3070_rf_read(sc, 6, &rf); |
2850 | rf = (rf & ~0x03) | rt3070_freqs[i].r; |
2851 | run_rt3070_rf_write(sc, 6, rf); |
2852 | |
2853 | /* set Tx0 power */ |
2854 | run_rt3070_rf_read(sc, 12, &rf); |
2855 | rf = (rf & ~0x1f) | txpow1; |
2856 | run_rt3070_rf_write(sc, 12, rf); |
2857 | |
2858 | /* set Tx1 power */ |
2859 | run_rt3070_rf_read(sc, 13, &rf); |
2860 | rf = (rf & ~0x1f) | txpow2; |
2861 | run_rt3070_rf_write(sc, 13, rf); |
2862 | |
2863 | run_rt3070_rf_read(sc, 1, &rf); |
2864 | rf &= ~0xfc; |
2865 | if (sc->ntxchains == 1) |
2866 | rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ |
2867 | else if (sc->ntxchains == 2) |
2868 | rf |= 1 << 7; /* 2T: disable Tx chain 3 */ |
2869 | if (sc->nrxchains == 1) |
2870 | rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ |
2871 | else if (sc->nrxchains == 2) |
2872 | rf |= 1 << 6; /* 2R: disable Rx chain 3 */ |
2873 | run_rt3070_rf_write(sc, 1, rf); |
2874 | |
2875 | /* set RF offset */ |
2876 | run_rt3070_rf_read(sc, 23, &rf); |
2877 | rf = (rf & ~0x7f) | sc->freq; |
2878 | run_rt3070_rf_write(sc, 23, rf); |
2879 | |
2880 | /* program RF filter */ |
2881 | run_rt3070_rf_read(sc, 24, &rf); /* Tx */ |
2882 | rf = (rf & ~0x3f) | sc->rf24_20mhz; |
2883 | run_rt3070_rf_write(sc, 24, rf); |
2884 | run_rt3070_rf_read(sc, 31, &rf); /* Rx */ |
2885 | rf = (rf & ~0x3f) | sc->rf24_20mhz; |
2886 | run_rt3070_rf_write(sc, 31, rf); |
2887 | |
2888 | /* enable RF tuning */ |
2889 | run_rt3070_rf_read(sc, 7, &rf); |
2890 | run_rt3070_rf_write(sc, 7, rf | 0x01); |
2891 | } |
2892 | |
2893 | static void |
2894 | run_rt3572_set_chan(struct run_softc *sc, u_int chan) |
2895 | { |
2896 | int8_t txpow1, txpow2; |
2897 | uint32_t tmp; |
2898 | uint8_t rf; |
2899 | int i; |
2900 | |
2901 | /* find the settings for this channel (we know it exists) */ |
2902 | for (i = 0; rt2860_rf2850[i].chan != chan; i++); |
2903 | |
2904 | /* use Tx power values from EEPROM */ |
2905 | txpow1 = sc->txpow1[i]; |
2906 | txpow2 = sc->txpow2[i]; |
2907 | |
2908 | if (chan <= 14) { |
2909 | run_bbp_write(sc, 25, sc->bbp25); |
2910 | run_bbp_write(sc, 26, sc->bbp26); |
2911 | } else { |
2912 | /* enable IQ phase correction */ |
2913 | run_bbp_write(sc, 25, 0x09); |
2914 | run_bbp_write(sc, 26, 0xff); |
2915 | } |
2916 | |
2917 | run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); |
2918 | run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); |
2919 | run_rt3070_rf_read(sc, 6, &rf); |
2920 | rf = (rf & ~0x0f) | rt3070_freqs[i].r; |
2921 | rf |= (chan <= 14) ? 0x08 : 0x04; |
2922 | run_rt3070_rf_write(sc, 6, rf); |
2923 | |
2924 | /* set PLL mode */ |
2925 | run_rt3070_rf_read(sc, 5, &rf); |
2926 | rf &= ~(0x08 | 0x04); |
2927 | rf |= (chan <= 14) ? 0x04 : 0x08; |
2928 | run_rt3070_rf_write(sc, 5, rf); |
2929 | |
2930 | /* set Tx power for chain 0 */ |
2931 | if (chan <= 14) |
2932 | rf = 0x60 | txpow1; |
2933 | else |
2934 | rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); |
2935 | run_rt3070_rf_write(sc, 12, rf); |
2936 | |
2937 | /* set Tx power for chain 1 */ |
2938 | if (chan <= 14) |
2939 | rf = 0x60 | txpow2; |
2940 | else |
2941 | rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); |
2942 | run_rt3070_rf_write(sc, 13, rf); |
2943 | |
2944 | /* set Tx/Rx streams */ |
2945 | run_rt3070_rf_read(sc, 1, &rf); |
2946 | rf &= ~0xfc; |
2947 | if (sc->ntxchains == 1) |
2948 | rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ |
2949 | else if (sc->ntxchains == 2) |
2950 | rf |= 1 << 7; /* 2T: disable Tx chain 3 */ |
2951 | if (sc->nrxchains == 1) |
2952 | rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ |
2953 | else if (sc->nrxchains == 2) |
2954 | rf |= 1 << 6; /* 2R: disable Rx chain 3 */ |
2955 | run_rt3070_rf_write(sc, 1, rf); |
2956 | |
2957 | /* set RF offset */ |
2958 | run_rt3070_rf_read(sc, 23, &rf); |
2959 | rf = (rf & ~0x7f) | sc->freq; |
2960 | run_rt3070_rf_write(sc, 23, rf); |
2961 | |
2962 | /* program RF filter */ |
2963 | rf = sc->rf24_20mhz; |
2964 | run_rt3070_rf_write(sc, 24, rf); /* Tx */ |
2965 | run_rt3070_rf_write(sc, 31, rf); /* Rx */ |
2966 | |
2967 | /* enable RF tuning */ |
2968 | run_rt3070_rf_read(sc, 7, &rf); |
2969 | rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); |
2970 | run_rt3070_rf_write(sc, 7, rf); |
2971 | |
2972 | /* TSSI */ |
2973 | rf = (chan <= 14) ? 0xc3 : 0xc0; |
2974 | run_rt3070_rf_write(sc, 9, rf); |
2975 | |
2976 | /* set loop filter 1 */ |
2977 | run_rt3070_rf_write(sc, 10, 0xf1); |
2978 | /* set loop filter 2 */ |
2979 | run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); |
2980 | |
2981 | /* set tx_mx2_ic */ |
2982 | run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); |
2983 | /* set tx_mx1_ic */ |
2984 | if (chan <= 14) |
2985 | rf = 0x48 | sc->txmixgain_2ghz; |
2986 | else |
2987 | rf = 0x78 | sc->txmixgain_5ghz; |
2988 | run_rt3070_rf_write(sc, 16, rf); |
2989 | |
2990 | /* set tx_lo1 */ |
2991 | run_rt3070_rf_write(sc, 17, 0x23); |
2992 | /* set tx_lo2 */ |
2993 | if (chan <= 14) |
2994 | rf = 0x93; |
2995 | else if (chan <= 64) |
2996 | rf = 0xb7; |
2997 | else if (chan <= 128) |
2998 | rf = 0x74; |
2999 | else |
3000 | rf = 0x72; |
3001 | run_rt3070_rf_write(sc, 19, rf); |
3002 | |
3003 | /* set rx_lo1 */ |
3004 | if (chan <= 14) |
3005 | rf = 0xb3; |
3006 | else if (chan <= 64) |
3007 | rf = 0xf6; |
3008 | else if (chan <= 128) |
3009 | rf = 0xf4; |
3010 | else |
3011 | rf = 0xf3; |
3012 | run_rt3070_rf_write(sc, 20, rf); |
3013 | |
3014 | /* set pfd_delay */ |
3015 | if (chan <= 14) |
3016 | rf = 0x15; |
3017 | else if (chan <= 64) |
3018 | rf = 0x3d; |
3019 | else |
3020 | rf = 0x01; |
3021 | run_rt3070_rf_write(sc, 25, rf); |
3022 | |
3023 | /* set rx_lo2 */ |
3024 | run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); |
3025 | /* set ldo_rf_vc */ |
3026 | run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); |
3027 | /* set drv_cc */ |
3028 | run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); |
3029 | |
3030 | run_read(sc, RT2860_GPIO_CTRL, &tmp); |
3031 | tmp &= ~0x8080; |
3032 | if (chan <= 14) |
3033 | tmp |= 0x80; |
3034 | run_write(sc, RT2860_GPIO_CTRL, tmp); |
3035 | |
3036 | /* enable RF tuning */ |
3037 | run_rt3070_rf_read(sc, 7, &rf); |
3038 | run_rt3070_rf_write(sc, 7, rf | 0x01); |
3039 | |
3040 | usbd_delay_ms(sc->sc_udev, 2); |
3041 | } |
3042 | |
3043 | static void |
3044 | run_rt3593_set_chan(struct run_softc *sc, u_int chan) |
3045 | { |
3046 | int8_t txpow1, txpow2, txpow3; |
3047 | uint8_t h20mhz, rf; |
3048 | int i; |
3049 | |
3050 | /* find the settings for this channel (we know it exists) */ |
3051 | for (i = 0; rt2860_rf2850[i].chan != chan; i++); |
3052 | |
3053 | /* use Tx power values from EEPROM */ |
3054 | txpow1 = sc->txpow1[i]; |
3055 | txpow2 = sc->txpow2[i]; |
3056 | txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; |
3057 | |
3058 | if (chan <= 14) { |
3059 | run_bbp_write(sc, 25, sc->bbp25); |
3060 | run_bbp_write(sc, 26, sc->bbp26); |
3061 | } else { |
3062 | /* Enable IQ phase correction. */ |
3063 | run_bbp_write(sc, 25, 0x09); |
3064 | run_bbp_write(sc, 26, 0xff); |
3065 | } |
3066 | |
3067 | run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); |
3068 | run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); |
3069 | run_rt3070_rf_read(sc, 11, &rf); |
3070 | rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); |
3071 | run_rt3070_rf_write(sc, 11, rf); |
3072 | |
3073 | /* Set pll_idoh. */ |
3074 | run_rt3070_rf_read(sc, 11, &rf); |
3075 | rf &= ~0x4c; |
3076 | rf |= (chan <= 14) ? 0x44 : 0x48; |
3077 | run_rt3070_rf_write(sc, 11, rf); |
3078 | |
3079 | if (chan <= 14) |
3080 | rf = txpow1 & 0x1f; |
3081 | else |
3082 | rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); |
3083 | run_rt3070_rf_write(sc, 53, rf); |
3084 | |
3085 | if (chan <= 14) |
3086 | rf = txpow2 & 0x1f; |
3087 | else |
3088 | rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); |
3089 | run_rt3070_rf_write(sc, 55, rf); |
3090 | |
3091 | if (chan <= 14) |
3092 | rf = txpow3 & 0x1f; |
3093 | else |
3094 | rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); |
3095 | run_rt3070_rf_write(sc, 54, rf); |
3096 | |
3097 | rf = RT3070_RF_BLOCK | RT3070_PLL_PD; |
3098 | if (sc->ntxchains == 3) |
3099 | rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; |
3100 | else |
3101 | rf |= RT3070_TX0_PD | RT3070_TX1_PD; |
3102 | rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; |
3103 | run_rt3070_rf_write(sc, 1, rf); |
3104 | |
3105 | run_adjust_freq_offset(sc); |
3106 | |
3107 | run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); |
3108 | |
3109 | h20mhz = (sc->rf24_20mhz & 0x20) >> 5; |
3110 | run_rt3070_rf_read(sc, 30, &rf); |
3111 | rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); |
3112 | run_rt3070_rf_write(sc, 30, rf); |
3113 | |
3114 | run_rt3070_rf_read(sc, 36, &rf); |
3115 | if (chan <= 14) |
3116 | rf |= 0x80; |
3117 | else |
3118 | rf &= ~0x80; |
3119 | run_rt3070_rf_write(sc, 36, rf); |
3120 | |
3121 | /* Set vcolo_bs. */ |
3122 | run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); |
3123 | /* Set pfd_delay. */ |
3124 | run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); |
3125 | |
3126 | /* Set vco bias current control. */ |
3127 | run_rt3070_rf_read(sc, 6, &rf); |
3128 | rf &= ~0xc0; |
3129 | if (chan <= 14) |
3130 | rf |= 0x40; |
3131 | else if (chan <= 128) |
3132 | rf |= 0x80; |
3133 | else |
3134 | rf |= 0x40; |
3135 | run_rt3070_rf_write(sc, 6, rf); |
3136 | |
3137 | run_rt3070_rf_read(sc, 30, &rf); |
3138 | rf = (rf & ~0x18) | 0x10; |
3139 | run_rt3070_rf_write(sc, 30, rf); |
3140 | |
3141 | run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); |
3142 | run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); |
3143 | |
3144 | run_rt3070_rf_read(sc, 51, &rf); |
3145 | rf = (rf & ~0x03) | 0x01; |
3146 | run_rt3070_rf_write(sc, 51, rf); |
3147 | /* Set tx_mx1_cc. */ |
3148 | run_rt3070_rf_read(sc, 51, &rf); |
3149 | rf &= ~0x1c; |
3150 | rf |= (chan <= 14) ? 0x14 : 0x10; |
3151 | run_rt3070_rf_write(sc, 51, rf); |
3152 | /* Set tx_mx1_ic. */ |
3153 | run_rt3070_rf_read(sc, 51, &rf); |
3154 | rf &= ~0xe0; |
3155 | rf |= (chan <= 14) ? 0x60 : 0x40; |
3156 | run_rt3070_rf_write(sc, 51, rf); |
3157 | /* Set tx_lo1_ic. */ |
3158 | run_rt3070_rf_read(sc, 49, &rf); |
3159 | rf &= ~0x1c; |
3160 | rf |= (chan <= 14) ? 0x0c : 0x08; |
3161 | run_rt3070_rf_write(sc, 49, rf); |
3162 | /* Set tx_lo1_en. */ |
3163 | run_rt3070_rf_read(sc, 50, &rf); |
3164 | run_rt3070_rf_write(sc, 50, rf & ~0x20); |
3165 | /* Set drv_cc. */ |
3166 | run_rt3070_rf_read(sc, 57, &rf); |
3167 | rf &= ~0xfc; |
3168 | rf |= (chan <= 14) ? 0x6c : 0x3c; |
3169 | run_rt3070_rf_write(sc, 57, rf); |
3170 | /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ |
3171 | run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); |
3172 | /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ |
3173 | run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); |
3174 | /* Enable VCO calibration. */ |
3175 | run_rt3070_rf_read(sc, 3, &rf); |
3176 | rf &= ~RT5390_VCOCAL; |
3177 | rf |= (chan <= 14) ? RT5390_VCOCAL : 0xbe; |
3178 | run_rt3070_rf_write(sc, 3, rf); |
3179 | |
3180 | if (chan <= 14) |
3181 | rf = 0x23; |
3182 | else if (chan <= 64) |
3183 | rf = 0x36; |
3184 | else if (chan <= 128) |
3185 | rf = 0x32; |
3186 | else |
3187 | rf = 0x30; |
3188 | run_rt3070_rf_write(sc, 39, rf); |
3189 | if (chan <= 14) |
3190 | rf = 0xbb; |
3191 | else if (chan <= 64) |
3192 | rf = 0xeb; |
3193 | else if (chan <= 128) |
3194 | rf = 0xb3; |
3195 | else |
3196 | rf = 0x9b; |
3197 | run_rt3070_rf_write(sc, 45, rf); |
3198 | |
3199 | /* Set FEQ/AEQ control. */ |
3200 | run_bbp_write(sc, 105, 0x34); |
3201 | } |
3202 | |
3203 | static void |
3204 | run_rt5390_set_chan(struct run_softc *sc, u_int chan) |
3205 | { |
3206 | int8_t txpow1, txpow2; |
3207 | uint8_t rf; |
3208 | int i; |
3209 | |
3210 | /* find the settings for this channel (we know it exists) */ |
3211 | for (i = 0; rt2860_rf2850[i].chan != chan; i++); |
3212 | |
3213 | /* use Tx power values from EEPROM */ |
3214 | txpow1 = sc->txpow1[i]; |
3215 | txpow2 = sc->txpow2[i]; |
3216 | |
3217 | run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); |
3218 | run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); |
3219 | run_rt3070_rf_read(sc, 11, &rf); |
3220 | rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); |
3221 | run_rt3070_rf_write(sc, 11, rf); |
3222 | |
3223 | run_rt3070_rf_read(sc, 49, &rf); |
3224 | rf = (rf & ~0x3f) | (txpow1 & 0x3f); |
3225 | /* The valid range of the RF R49 is 0x00 to 0x27. */ |
3226 | if ((rf & 0x3f) > 0x27) |
3227 | rf = (rf & ~0x3f) | 0x27; |
3228 | run_rt3070_rf_write(sc, 49, rf); |
3229 | |
3230 | if (sc->mac_ver == 0x5392) { |
3231 | run_rt3070_rf_read(sc, 50, &rf); |
3232 | rf = (rf & ~0x3f) | (txpow2 & 0x3f); |
3233 | /* The valid range of the RF R50 is 0x00 to 0x27. */ |
3234 | if ((rf & 0x3f) > 0x27) |
3235 | rf = (rf & ~0x3f) | 0x27; |
3236 | run_rt3070_rf_write(sc, 50, rf); |
3237 | } |
3238 | |
3239 | run_rt3070_rf_read(sc, 1, &rf); |
3240 | rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; |
3241 | if (sc->mac_ver == 0x5392) |
3242 | rf |= RT3070_RX1_PD | RT3070_TX1_PD; |
3243 | run_rt3070_rf_write(sc, 1, rf); |
3244 | |
3245 | if (sc->mac_ver != 0x5392) { |
3246 | run_rt3070_rf_read(sc, 2, &rf); |
3247 | rf |= 0x80; |
3248 | run_rt3070_rf_write(sc, 2, rf); |
3249 | usbd_delay_ms(sc->sc_udev, 10); |
3250 | rf &= 0x7f; |
3251 | run_rt3070_rf_write(sc, 2, rf); |
3252 | } |
3253 | |
3254 | run_adjust_freq_offset(sc); |
3255 | |
3256 | if (sc->mac_ver == 0x5392) { |
3257 | /* Fix for RT5392C. */ |
3258 | if (sc->mac_rev >= 0x0223) { |
3259 | if (chan <= 4) |
3260 | rf = 0x0f; |
3261 | else if (chan >= 5 && chan <= 7) |
3262 | rf = 0x0e; |
3263 | else |
3264 | rf = 0x0d; |
3265 | run_rt3070_rf_write(sc, 23, rf); |
3266 | |
3267 | if (chan <= 4) |
3268 | rf = 0x0c; |
3269 | else if (chan == 5) |
3270 | rf = 0x0b; |
3271 | else if (chan >= 6 && chan <= 7) |
3272 | rf = 0x0a; |
3273 | else if (chan >= 8 && chan <= 10) |
3274 | rf = 0x09; |
3275 | else |
3276 | rf = 0x08; |
3277 | run_rt3070_rf_write(sc, 59, rf); |
3278 | } else { |
3279 | if (chan <= 11) |
3280 | rf = 0x0f; |
3281 | else |
3282 | rf = 0x0b; |
3283 | run_rt3070_rf_write(sc, 59, rf); |
3284 | } |
3285 | } else { |
3286 | /* Fix for RT5390F. */ |
3287 | if (sc->mac_rev >= 0x0502) { |
3288 | if (chan <= 11) |
3289 | rf = 0x43; |
3290 | else |
3291 | rf = 0x23; |
3292 | run_rt3070_rf_write(sc, 55, rf); |
3293 | |
3294 | if (chan <= 11) |
3295 | rf = 0x0f; |
3296 | else if (chan == 12) |
3297 | rf = 0x0d; |
3298 | else |
3299 | rf = 0x0b; |
3300 | run_rt3070_rf_write(sc, 59, rf); |
3301 | } else { |
3302 | run_rt3070_rf_write(sc, 55, 0x44); |
3303 | run_rt3070_rf_write(sc, 59, 0x8f); |
3304 | } |
3305 | } |
3306 | |
3307 | /* Enable VCO calibration. */ |
3308 | run_rt3070_rf_read(sc, 3, &rf); |
3309 | rf |= RT5390_VCOCAL; |
3310 | run_rt3070_rf_write(sc, 3, rf); |
3311 | } |
3312 | |
3313 | static void |
3314 | run_rt5592_set_chan(struct run_softc *sc, u_int chan) |
3315 | { |
3316 | const struct rt5592_freqs *freqs; |
3317 | uint32_t tmp; |
3318 | uint8_t reg, rf, txpow_bound; |
3319 | int8_t txpow1, txpow2; |
3320 | int i; |
3321 | |
3322 | run_read(sc, RT5592_DEBUG_INDEX, &tmp); |
3323 | freqs = (tmp & RT5592_SEL_XTAL) ? |
3324 | rt5592_freqs_40mhz : rt5592_freqs_20mhz; |
3325 | |
3326 | /* find the settings for this channel (we know it exists) */ |
3327 | for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); |
3328 | |
3329 | /* use Tx power values from EEPROM */ |
3330 | txpow1 = sc->txpow1[i]; |
3331 | txpow2 = sc->txpow2[i]; |
3332 | |
3333 | run_read(sc, RT3070_LDO_CFG0, &tmp); |
3334 | tmp &= ~0x1c000000; |
3335 | if (chan > 14) |
3336 | tmp |= 0x14000000; |
3337 | run_write(sc, RT3070_LDO_CFG0, tmp); |
3338 | |
3339 | /* N setting. */ |
3340 | run_rt3070_rf_write(sc, 8, freqs->n & 0xff); |
3341 | run_rt3070_rf_read(sc, 9, &rf); |
3342 | rf &= ~(1 << 4); |
3343 | rf |= ((freqs->n & 0x0100) >> 8) << 4; |
3344 | run_rt3070_rf_write(sc, 9, rf); |
3345 | |
3346 | /* K setting. */ |
3347 | run_rt3070_rf_read(sc, 9, &rf); |
3348 | rf &= ~0x0f; |
3349 | rf |= (freqs->k & 0x0f); |
3350 | run_rt3070_rf_write(sc, 9, rf); |
3351 | |
3352 | /* Mode setting. */ |
3353 | run_rt3070_rf_read(sc, 11, &rf); |
3354 | rf &= ~0x0c; |
3355 | rf |= ((freqs->m - 0x8) & 0x3) << 2; |
3356 | run_rt3070_rf_write(sc, 11, rf); |
3357 | run_rt3070_rf_read(sc, 9, &rf); |
3358 | rf &= ~(1 << 7); |
3359 | rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; |
3360 | run_rt3070_rf_write(sc, 9, rf); |
3361 | |
3362 | /* R setting. */ |
3363 | run_rt3070_rf_read(sc, 11, &rf); |
3364 | rf &= ~0x03; |
3365 | rf |= (freqs->r - 0x1); |
3366 | run_rt3070_rf_write(sc, 11, rf); |
3367 | |
3368 | if (chan <= 14) { |
3369 | /* Initialize RF registers for 2GHZ. */ |
3370 | for (i = 0; i < (int)__arraycount(rt5592_2ghz_def_rf); i++) { |
3371 | run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, |
3372 | rt5592_2ghz_def_rf[i].val); |
3373 | } |
3374 | |
3375 | rf = (chan <= 10) ? 0x07 : 0x06; |
3376 | run_rt3070_rf_write(sc, 23, rf); |
3377 | run_rt3070_rf_write(sc, 59, rf); |
3378 | |
3379 | run_rt3070_rf_write(sc, 55, 0x43); |
3380 | |
3381 | /* |
3382 | * RF R49/R50 Tx power ALC code. |
3383 | * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. |
3384 | */ |
3385 | reg = 2; |
3386 | txpow_bound = 0x27; |
3387 | } else { |
3388 | /* Initialize RF registers for 5GHZ. */ |
3389 | for (i = 0; i < (int)__arraycount(rt5592_5ghz_def_rf); i++) { |
3390 | run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, |
3391 | rt5592_5ghz_def_rf[i].val); |
3392 | } |
3393 | for (i = 0; i < (int)__arraycount(rt5592_chan_5ghz); i++) { |
3394 | if (chan >= rt5592_chan_5ghz[i].firstchan && |
3395 | chan <= rt5592_chan_5ghz[i].lastchan) { |
3396 | run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, |
3397 | rt5592_chan_5ghz[i].val); |
3398 | } |
3399 | } |
3400 | |
3401 | /* |
3402 | * RF R49/R50 Tx power ALC code. |
3403 | * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. |
3404 | */ |
3405 | reg = 3; |
3406 | txpow_bound = 0x2b; |
3407 | } |
3408 | |
3409 | /* RF R49 ch0 Tx power ALC code. */ |
3410 | run_rt3070_rf_read(sc, 49, &rf); |
3411 | rf &= ~0xc0; |
3412 | rf |= (reg << 6); |
3413 | rf = (rf & ~0x3f) | (txpow1 & 0x3f); |
3414 | if ((rf & 0x3f) > txpow_bound) |
3415 | rf = (rf & ~0x3f) | txpow_bound; |
3416 | run_rt3070_rf_write(sc, 49, rf); |
3417 | |
3418 | /* RF R50 ch1 Tx power ALC code. */ |
3419 | run_rt3070_rf_read(sc, 50, &rf); |
3420 | rf &= ~(1 << 7 | 1 << 6); |
3421 | rf |= (reg << 6); |
3422 | rf = (rf & ~0x3f) | (txpow2 & 0x3f); |
3423 | if ((rf & 0x3f) > txpow_bound) |
3424 | rf = (rf & ~0x3f) | txpow_bound; |
3425 | run_rt3070_rf_write(sc, 50, rf); |
3426 | |
3427 | /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ |
3428 | run_rt3070_rf_read(sc, 1, &rf); |
3429 | rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD); |
3430 | if (sc->ntxchains > 1) |
3431 | rf |= RT3070_TX1_PD; |
3432 | if (sc->nrxchains > 1) |
3433 | rf |= RT3070_RX1_PD; |
3434 | run_rt3070_rf_write(sc, 1, rf); |
3435 | |
3436 | run_rt3070_rf_write(sc, 6, 0xe4); |
3437 | |
3438 | run_rt3070_rf_write(sc, 30, 0x10); |
3439 | run_rt3070_rf_write(sc, 31, 0x80); |
3440 | run_rt3070_rf_write(sc, 32, 0x80); |
3441 | |
3442 | run_adjust_freq_offset(sc); |
3443 | |
3444 | /* Enable VCO calibration. */ |
3445 | run_rt3070_rf_read(sc, 3, &rf); |
3446 | rf |= RT5390_VCOCAL; |
3447 | run_rt3070_rf_write(sc, 3, rf); |
3448 | } |
3449 | |
3450 | static void |
3451 | run_iq_calib(struct run_softc *sc, u_int chan) |
3452 | { |
3453 | uint16_t val; |
3454 | |
3455 | /* Tx0 IQ gain. */ |
3456 | run_bbp_write(sc, 158, 0x2c); |
3457 | if (chan <= 14) |
3458 | run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val, 1); |
3459 | else if (chan <= 64) { |
3460 | run_efuse_read(sc, |
3461 | RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, |
3462 | &val, 1); |
3463 | } else if (chan <= 138) { |
3464 | run_efuse_read(sc, |
3465 | RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, |
3466 | &val, 1); |
3467 | } else if (chan <= 165) { |
3468 | run_efuse_read(sc, |
3469 | RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, |
3470 | &val, 1); |
3471 | } else |
3472 | val = 0; |
3473 | run_bbp_write(sc, 159, val); |
3474 | |
3475 | /* Tx0 IQ phase. */ |
3476 | run_bbp_write(sc, 158, 0x2d); |
3477 | if (chan <= 14) { |
3478 | run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, |
3479 | &val, 1); |
3480 | } else if (chan <= 64) { |
3481 | run_efuse_read(sc, |
3482 | RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, |
3483 | &val, 1); |
3484 | } else if (chan <= 138) { |
3485 | run_efuse_read(sc, |
3486 | RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, |
3487 | &val, 1); |
3488 | } else if (chan <= 165) { |
3489 | run_efuse_read(sc, |
3490 | RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, |
3491 | &val, 1); |
3492 | } else |
3493 | val = 0; |
3494 | run_bbp_write(sc, 159, val); |
3495 | |
3496 | /* Tx1 IQ gain. */ |
3497 | run_bbp_write(sc, 158, 0x4a); |
3498 | if (chan <= 14) { |
3499 | run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, |
3500 | &val, 1); |
3501 | } else if (chan <= 64) { |
3502 | run_efuse_read(sc, |
3503 | RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, |
3504 | &val, 1); |
3505 | } else if (chan <= 138) { |
3506 | run_efuse_read(sc, |
3507 | RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, |
3508 | &val, 1); |
3509 | } else if (chan <= 165) { |
3510 | run_efuse_read(sc, |
3511 | RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, |
3512 | &val, 1); |
3513 | } else |
3514 | val = 0; |
3515 | run_bbp_write(sc, 159, val); |
3516 | |
3517 | /* Tx1 IQ phase. */ |
3518 | run_bbp_write(sc, 158, 0x4b); |
3519 | if (chan <= 14) { |
3520 | run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, |
3521 | &val, 1); |
3522 | } else if (chan <= 64) { |
3523 | run_efuse_read(sc, |
3524 | RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, |
3525 | &val, 1); |
3526 | } else if (chan <= 138) { |
3527 | run_efuse_read(sc, |
3528 | RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, |
3529 | &val, 1); |
3530 | } else if (chan <= 165) { |
3531 | run_efuse_read(sc, |
3532 | RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, |
3533 | &val, 1); |
3534 | } else |
3535 | val = 0; |
3536 | run_bbp_write(sc, 159, val); |
3537 | |
3538 | /* RF IQ compensation control. */ |
3539 | run_bbp_write(sc, 158, 0x04); |
3540 | run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, |
3541 | &val, 1); |
3542 | run_bbp_write(sc, 159, val); |
3543 | |
3544 | /* RF IQ imbalance compensation control. */ |
3545 | run_bbp_write(sc, 158, 0x03); |
3546 | run_efuse_read(sc, |
3547 | RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val, 1); |
3548 | run_bbp_write(sc, 159, val); |
3549 | } |
3550 | |
3551 | static void |
3552 | run_set_agc(struct run_softc *sc, uint8_t agc) |
3553 | { |
3554 | uint8_t bbp; |
3555 | |
3556 | if (sc->mac_ver == 0x3572) { |
3557 | run_bbp_read(sc, 27, &bbp); |
3558 | bbp &= ~(0x3 << 5); |
3559 | run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ |
3560 | run_bbp_write(sc, 66, agc); |
3561 | run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ |
3562 | run_bbp_write(sc, 66, agc); |
3563 | } else |
3564 | run_bbp_write(sc, 66, agc); |
3565 | } |
3566 | |
3567 | static void |
3568 | run_set_rx_antenna(struct run_softc *sc, int aux) |
3569 | { |
3570 | uint32_t tmp; |
3571 | uint8_t bbp152; |
3572 | |
3573 | if (sc->rf_rev == RT5390_RF_5370) { |
3574 | run_bbp_read(sc, 152, &bbp152); |
3575 | bbp152 &= ~0x80; |
3576 | if (aux) |
3577 | bbp152 |= 0x80; |
3578 | run_bbp_write(sc, 152, bbp152); |
3579 | } else { |
3580 | run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, !aux); |
3581 | run_read(sc, RT2860_GPIO_CTRL, &tmp); |
3582 | tmp &= ~0x0808; |
3583 | if (aux) |
3584 | tmp |= 0x08; |
3585 | run_write(sc, RT2860_GPIO_CTRL, tmp); |
3586 | } |
3587 | } |
3588 | |
3589 | static int |
3590 | run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) |
3591 | { |
3592 | struct ieee80211com *ic = &sc->sc_ic; |
3593 | u_int chan, group; |
3594 | |
3595 | chan = ieee80211_chan2ieee(ic, c); |
3596 | if (chan == 0 || chan == IEEE80211_CHAN_ANY) |
3597 | return EINVAL; |
3598 | |
3599 | if (sc->mac_ver == 0x5592) |
3600 | run_rt5592_set_chan(sc, chan); |
3601 | else if (sc->mac_ver >= 0x5390) |
3602 | run_rt5390_set_chan(sc, chan); |
3603 | else if (sc->mac_ver == 0x3593) |
3604 | run_rt3593_set_chan(sc, chan); |
3605 | else if (sc->mac_ver == 0x3572) |
3606 | run_rt3572_set_chan(sc, chan); |
3607 | else if (sc->mac_ver >= 0x3070) |
3608 | run_rt3070_set_chan(sc, chan); |
3609 | else |
3610 | run_rt2870_set_chan(sc, chan); |
3611 | |
3612 | /* determine channel group */ |
3613 | if (chan <= 14) |
3614 | group = 0; |
3615 | else if (chan <= 64) |
3616 | group = 1; |
3617 | else if (chan <= 128) |
3618 | group = 2; |
3619 | else |
3620 | group = 3; |
3621 | |
3622 | /* XXX necessary only when group has changed! */ |
3623 | run_select_chan_group(sc, group); |
3624 | |
3625 | usbd_delay_ms(sc->sc_udev, 10); |
3626 | |
3627 | /* Perform IQ calibration. */ |
3628 | if (sc->mac_ver >= 0x5392) |
3629 | run_iq_calib(sc, chan); |
3630 | |
3631 | return 0; |
3632 | } |
3633 | |
3634 | static void |
3635 | run_updateprot(struct run_softc *sc) |
3636 | { |
3637 | struct ieee80211com *ic = &sc->sc_ic; |
3638 | uint32_t tmp; |
3639 | |
3640 | tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; |
3641 | /* setup protection frame rate (MCS code) */ |
3642 | tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? |
3643 | rt2860_rates[RT2860_RIDX_OFDM6].mcs | RT2860_PHY_OFDM : |
3644 | rt2860_rates[RT2860_RIDX_CCK11].mcs; |
3645 | |
3646 | /* CCK frames don't require protection */ |
3647 | run_write(sc, RT2860_CCK_PROT_CFG, tmp); |
3648 | if (ic->ic_flags & IEEE80211_F_USEPROT) { |
3649 | if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) |
3650 | tmp |= RT2860_PROT_CTRL_RTS_CTS; |
3651 | else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) |
3652 | tmp |= RT2860_PROT_CTRL_CTS; |
3653 | } |
3654 | run_write(sc, RT2860_OFDM_PROT_CFG, tmp); |
3655 | } |
3656 | |
3657 | static void |
3658 | run_enable_tsf_sync(struct run_softc *sc) |
3659 | { |
3660 | struct ieee80211com *ic = &sc->sc_ic; |
3661 | uint32_t tmp; |
3662 | |
3663 | run_read(sc, RT2860_BCN_TIME_CFG, &tmp); |
3664 | tmp &= ~0x1fffff; |
3665 | tmp |= ic->ic_bss->ni_intval * 16; |
3666 | tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; |
3667 | if (ic->ic_opmode == IEEE80211_M_STA) { |
3668 | /* |
3669 | * Local TSF is always updated with remote TSF on beacon |
3670 | * reception. |
3671 | */ |
3672 | tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; |
3673 | } |
3674 | #ifndef IEEE80211_STA_ONLY |
3675 | else if (ic->ic_opmode == IEEE80211_M_IBSS) { |
3676 | tmp |= RT2860_BCN_TX_EN; |
3677 | /* |
3678 | * Local TSF is updated with remote TSF on beacon reception |
3679 | * only if the remote TSF is greater than local TSF. |
3680 | */ |
3681 | tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; |
3682 | } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { |
3683 | tmp |= RT2860_BCN_TX_EN; |
3684 | /* SYNC with nobody */ |
3685 | tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; |
3686 | } |
3687 | #endif |
3688 | run_write(sc, RT2860_BCN_TIME_CFG, tmp); |
3689 | } |
3690 | |
3691 | static void |
3692 | run_enable_mrr(struct run_softc *sc) |
3693 | { |
3694 | #define CCK(mcs) (mcs) |
3695 | #define OFDM(mcs) (1 << 3 | (mcs)) |
3696 | run_write(sc, RT2860_LG_FBK_CFG0, |
3697 | OFDM(6) << 28 | /* 54->48 */ |
3698 | OFDM(5) << 24 | /* 48->36 */ |
3699 | OFDM(4) << 20 | /* 36->24 */ |
3700 | OFDM(3) << 16 | /* 24->18 */ |
3701 | OFDM(2) << 12 | /* 18->12 */ |
3702 | OFDM(1) << 8 | /* 12-> 9 */ |
3703 | OFDM(0) << 4 | /* 9-> 6 */ |
3704 | OFDM(0)); /* 6-> 6 */ |
3705 | |
3706 | run_write(sc, RT2860_LG_FBK_CFG1, |
3707 | CCK(2) << 12 | /* 11->5.5 */ |
3708 | CCK(1) << 8 | /* 5.5-> 2 */ |
3709 | CCK(0) << 4 | /* 2-> 1 */ |
3710 | CCK(0)); /* 1-> 1 */ |
3711 | #undef OFDM |
3712 | #undef CCK |
3713 | } |
3714 | |
3715 | static void |
3716 | run_set_txpreamble(struct run_softc *sc) |
3717 | { |
3718 | uint32_t tmp; |
3719 | |
3720 | run_read(sc, RT2860_AUTO_RSP_CFG, &tmp); |
3721 | if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) |
3722 | tmp |= RT2860_CCK_SHORT_EN; |
3723 | else |
3724 | tmp &= ~RT2860_CCK_SHORT_EN; |
3725 | run_write(sc, RT2860_AUTO_RSP_CFG, tmp); |
3726 | } |
3727 | |
3728 | static void |
3729 | run_set_basicrates(struct run_softc *sc) |
3730 | { |
3731 | struct ieee80211com *ic = &sc->sc_ic; |
3732 | |
3733 | /* set basic rates mask */ |
3734 | if (ic->ic_curmode == IEEE80211_MODE_11B) |
3735 | run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x003); |
3736 | else if (ic->ic_curmode == IEEE80211_MODE_11A) |
3737 | run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x150); |
3738 | else /* 11g */ |
3739 | run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); |
3740 | } |
3741 | |
3742 | static void |
3743 | run_set_leds(struct run_softc *sc, uint16_t which) |
3744 | { |
3745 | |
3746 | (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, |
3747 | which | (sc->leds & 0x7f)); |
3748 | } |
3749 | |
3750 | static void |
3751 | run_set_bssid(struct run_softc *sc, const uint8_t *bssid) |
3752 | { |
3753 | |
3754 | run_write(sc, RT2860_MAC_BSSID_DW0, |
3755 | bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); |
3756 | run_write(sc, RT2860_MAC_BSSID_DW1, |
3757 | bssid[4] | bssid[5] << 8); |
3758 | } |
3759 | |
3760 | static void |
3761 | run_set_macaddr(struct run_softc *sc, const uint8_t *addr) |
3762 | { |
3763 | |
3764 | run_write(sc, RT2860_MAC_ADDR_DW0, |
3765 | addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); |
3766 | run_write(sc, RT2860_MAC_ADDR_DW1, |
3767 | addr[4] | addr[5] << 8 | 0xff << 16); |
3768 | } |
3769 | |
3770 | static void |
3771 | run_updateslot(struct ifnet *ifp) |
3772 | { |
3773 | |
3774 | /* do it in a process context */ |
3775 | run_do_async(ifp->if_softc, run_updateslot_cb, NULL, 0); |
3776 | } |
3777 | |
3778 | /* ARGSUSED */ |
3779 | static void |
3780 | run_updateslot_cb(struct run_softc *sc, void *arg) |
3781 | { |
3782 | uint32_t tmp; |
3783 | |
3784 | run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp); |
3785 | tmp &= ~0xff; |
3786 | tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; |
3787 | run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp); |
3788 | } |
3789 | |
3790 | static int8_t |
3791 | (struct run_softc *sc, uint8_t , uint8_t rxchain) |
3792 | { |
3793 | struct ieee80211com *ic = &sc->sc_ic; |
3794 | struct ieee80211_channel *c = ic->ic_curchan; |
3795 | int delta; |
3796 | |
3797 | if (IEEE80211_IS_CHAN_5GHZ(c)) { |
3798 | u_int chan = ieee80211_chan2ieee(ic, c); |
3799 | delta = sc->rssi_5ghz[rxchain]; |
3800 | |
3801 | /* determine channel group */ |
3802 | if (chan <= 64) |
3803 | delta -= sc->lna[1]; |
3804 | else if (chan <= 128) |
3805 | delta -= sc->lna[2]; |
3806 | else |
3807 | delta -= sc->lna[3]; |
3808 | } else |
3809 | delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; |
3810 | |
3811 | return -12 - delta - rssi; |
3812 | } |
3813 | |
3814 | static void |
3815 | run_rt5390_bbp_init(struct run_softc *sc) |
3816 | { |
3817 | u_int i; |
3818 | uint8_t bbp; |
3819 | |
3820 | /* Apply maximum likelihood detection for 2 stream case. */ |
3821 | run_bbp_read(sc, 105, &bbp); |
3822 | if (sc->nrxchains > 1) |
3823 | run_bbp_write(sc, 105, bbp | RT5390_MLD); |
3824 | |
3825 | /* Avoid data lost and CRC error. */ |
3826 | run_bbp_read(sc, 4, &bbp); |
3827 | run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); |
3828 | |
3829 | if (sc->mac_ver == 0x5592) { |
3830 | for (i = 0; i < (int)__arraycount(rt5592_def_bbp); i++) { |
3831 | run_bbp_write(sc, rt5592_def_bbp[i].reg, |
3832 | rt5592_def_bbp[i].val); |
3833 | } |
3834 | for (i = 0; i < (int)__arraycount(rt5592_bbp_r196); i++) { |
3835 | run_bbp_write(sc, 195, i + 0x80); |
3836 | run_bbp_write(sc, 196, rt5592_bbp_r196[i]); |
3837 | } |
3838 | } else { |
3839 | for (i = 0; i < (int)__arraycount(rt5390_def_bbp); i++) { |
3840 | run_bbp_write(sc, rt5390_def_bbp[i].reg, |
3841 | rt5390_def_bbp[i].val); |
3842 | } |
3843 | } |
3844 | if (sc->mac_ver == 0x5392) { |
3845 | run_bbp_write(sc, 88, 0x90); |
3846 | run_bbp_write(sc, 95, 0x9a); |
3847 | run_bbp_write(sc, 98, 0x12); |
3848 | run_bbp_write(sc, 106, 0x12); |
3849 | run_bbp_write(sc, 134, 0xd0); |
3850 | run_bbp_write(sc, 135, 0xf6); |
3851 | run_bbp_write(sc, 148, 0x84); |
3852 | } |
3853 | |
3854 | run_bbp_read(sc, 152, &bbp); |
3855 | run_bbp_write(sc, 152, bbp | 0x80); |
3856 | |
3857 | /* Fix BBP254 for RT5592C. */ |
3858 | if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { |
3859 | run_bbp_read(sc, 254, &bbp); |
3860 | run_bbp_write(sc, 254, bbp | 0x80); |
3861 | } |
3862 | |
3863 | /* Disable hardware antenna diversity. */ |
3864 | if (sc->mac_ver == 0x5390) |
3865 | run_bbp_write(sc, 154, 0); |
3866 | |
3867 | /* Initialize Rx CCK/OFDM frequency offset report. */ |
3868 | run_bbp_write(sc, 142, 1); |
3869 | run_bbp_write(sc, 143, 57); |
3870 | } |
3871 | |
3872 | static int |
3873 | run_bbp_init(struct run_softc *sc) |
3874 | { |
3875 | int i, error, ntries; |
3876 | uint8_t bbp0; |
3877 | |
3878 | /* wait for BBP to wake up */ |
3879 | for (ntries = 0; ntries < 20; ntries++) { |
3880 | if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) |
3881 | return error; |
3882 | if (bbp0 != 0 && bbp0 != 0xff) |
3883 | break; |
3884 | } |
3885 | if (ntries == 20) |
3886 | return ETIMEDOUT; |
3887 | |
3888 | /* initialize BBP registers to default values */ |
3889 | if (sc->mac_ver >= 0x5390) |
3890 | run_rt5390_bbp_init(sc); |
3891 | else { |
3892 | for (i = 0; i < (int)__arraycount(rt2860_def_bbp); i++) { |
3893 | run_bbp_write(sc, rt2860_def_bbp[i].reg, |
3894 | rt2860_def_bbp[i].val); |
3895 | } |
3896 | } |
3897 | |
3898 | if (sc->mac_ver == 0x3593) { |
3899 | run_bbp_write(sc, 79, 0x13); |
3900 | run_bbp_write(sc, 80, 0x05); |
3901 | run_bbp_write(sc, 81, 0x33); |
3902 | run_bbp_write(sc, 86, 0x46); |
3903 | run_bbp_write(sc, 137, 0x0f); |
3904 | } |
3905 | |
3906 | /* fix BBP84 for RT2860E */ |
3907 | if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) |
3908 | run_bbp_write(sc, 84, 0x19); |
3909 | |
3910 | if (sc->mac_ver >= 0x3070) { |
3911 | run_bbp_write(sc, 79, 0x13); |
3912 | run_bbp_write(sc, 80, 0x05); |
3913 | run_bbp_write(sc, 81, 0x33); |
3914 | } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { |
3915 | run_bbp_write(sc, 69, 0x16); |
3916 | run_bbp_write(sc, 73, 0x12); |
3917 | } |
3918 | return 0; |
3919 | } |
3920 | |
3921 | static int |
3922 | run_rt3070_rf_init(struct run_softc *sc) |
3923 | { |
3924 | uint32_t tmp; |
3925 | uint8_t rf, target, bbp4; |
3926 | int i; |
3927 | |
3928 | run_rt3070_rf_read(sc, 30, &rf); |
3929 | /* toggle RF R30 bit 7 */ |
3930 | run_rt3070_rf_write(sc, 30, rf | 0x80); |
3931 | usbd_delay_ms(sc->sc_udev, 10); |
3932 | run_rt3070_rf_write(sc, 30, rf & ~0x80); |
3933 | |
3934 | /* initialize RF registers to default value */ |
3935 | if (sc->mac_ver == 0x3572) { |
3936 | for (i = 0; i < (int)__arraycount(rt3572_def_rf); i++) { |
3937 | run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, |
3938 | rt3572_def_rf[i].val); |
3939 | } |
3940 | } else { |
3941 | for (i = 0; i < (int)__arraycount(rt3070_def_rf); i++) { |
3942 | run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, |
3943 | rt3070_def_rf[i].val); |
3944 | } |
3945 | } |
3946 | if (sc->mac_ver == 0x3572) { |
3947 | run_rt3070_rf_read(sc, 6, &rf); |
3948 | run_rt3070_rf_write(sc, 6, rf | 0x40); |
3949 | run_rt3070_rf_write(sc, 31, 0x14); |
3950 | |
3951 | run_read(sc, RT3070_LDO_CFG0, &tmp); |
3952 | tmp &= ~0x1f000000; |
3953 | if (sc->mac_rev < 0x0211 && sc->patch_dac) |
3954 | tmp |= 0x0d000000; /* 1.3V */ |
3955 | else |
3956 | tmp |= 0x01000000; /* 1.2V */ |
3957 | run_write(sc, RT3070_LDO_CFG0, tmp); |
3958 | } else if (sc->mac_ver == 0x3071) { |
3959 | run_rt3070_rf_read(sc, 6, &rf); |
3960 | run_rt3070_rf_write(sc, 6, rf | 0x40); |
3961 | run_rt3070_rf_write(sc, 31, 0x14); |
3962 | |
3963 | run_read(sc, RT3070_LDO_CFG0, &tmp); |
3964 | tmp &= ~0x1f000000; |
3965 | if (sc->mac_rev < 0x0211) |
3966 | tmp |= 0x0d000000; /* 1.35V */ |
3967 | else |
3968 | tmp |= 0x01000000; /* 1.2V */ |
3969 | run_write(sc, RT3070_LDO_CFG0, tmp); |
3970 | |
3971 | /* patch LNA_PE_G1 */ |
3972 | run_read(sc, RT3070_GPIO_SWITCH, &tmp); |
3973 | run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); |
3974 | } else if (sc->mac_ver == 0x3070) { |
3975 | /* increase voltage from 1.2V to 1.35V */ |
3976 | run_read(sc, RT3070_LDO_CFG0, &tmp); |
3977 | tmp = (tmp & ~0x0f000000) | 0x0d000000; |
3978 | run_write(sc, RT3070_LDO_CFG0, tmp); |
3979 | } |
3980 | |
3981 | /* select 20MHz bandwidth */ |
3982 | run_rt3070_rf_read(sc, 31, &rf); |
3983 | run_rt3070_rf_write(sc, 31, rf & ~0x20); |
3984 | |
3985 | /* calibrate filter for 20MHz bandwidth */ |
3986 | sc->rf24_20mhz = 0x1f; /* default value */ |
3987 | target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; |
3988 | run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); |
3989 | |
3990 | /* select 40MHz bandwidth */ |
3991 | run_bbp_read(sc, 4, &bbp4); |
3992 | run_bbp_write(sc, 4, (bbp4 & ~0x08) | 0x10); |
3993 | run_rt3070_rf_read(sc, 31, &rf); |
3994 | run_rt3070_rf_write(sc, 31, rf | 0x20); |
3995 | |
3996 | /* calibrate filter for 40MHz bandwidth */ |
3997 | sc->rf24_40mhz = 0x2f; /* default value */ |
3998 | target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; |
3999 | run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); |
4000 | |
4001 | /* go back to 20MHz bandwidth */ |
4002 | run_bbp_read(sc, 4, &bbp4); |
4003 | run_bbp_write(sc, 4, bbp4 & ~0x18); |
4004 | |
4005 | if (sc->mac_ver == 0x3572) { |
4006 | /* save default BBP registers 25 and 26 values */ |
4007 | run_bbp_read(sc, 25, &sc->bbp25); |
4008 | run_bbp_read(sc, 26, &sc->bbp26); |
4009 | } else if (sc->mac_rev < 0x0211) |
4010 | run_rt3070_rf_write(sc, 27, 0x03); |
4011 | |
4012 | run_read(sc, RT3070_OPT_14, &tmp); |
4013 | run_write(sc, RT3070_OPT_14, tmp | 1); |
4014 | |
4015 | if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { |
4016 | run_rt3070_rf_read(sc, 17, &rf); |
4017 | rf &= ~RT3070_TX_LO1; |
4018 | if ((sc->mac_ver == 0x3070 || |
4019 | (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && |
4020 | !sc->ext_2ghz_lna) |
4021 | rf |= 0x20; /* fix for long range Rx issue */ |
4022 | if (sc->txmixgain_2ghz >= 1) |
4023 | rf = (rf & ~0x7) | sc->txmixgain_2ghz; |
4024 | run_rt3070_rf_write(sc, 17, rf); |
4025 | } |
4026 | if (sc->mac_ver == 0x3071) { |
4027 | run_rt3070_rf_read(sc, 1, &rf); |
4028 | rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); |
4029 | rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; |
4030 | run_rt3070_rf_write(sc, 1, rf); |
4031 | |
4032 | run_rt3070_rf_read(sc, 15, &rf); |
4033 | run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2); |
4034 | |
4035 | run_rt3070_rf_read(sc, 20, &rf); |
4036 | run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1); |
4037 | |
4038 | run_rt3070_rf_read(sc, 21, &rf); |
4039 | run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2); |
4040 | } |
4041 | if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { |
4042 | /* fix Tx to Rx IQ glitch by raising RF voltage */ |
4043 | run_rt3070_rf_read(sc, 27, &rf); |
4044 | rf &= ~0x77; |
4045 | if (sc->mac_rev < 0x0211) |
4046 | rf |= 0x03; |
4047 | run_rt3070_rf_write(sc, 27, rf); |
4048 | } |
4049 | return 0; |
4050 | } |
4051 | |
4052 | static int |
4053 | run_rt3593_rf_init(struct run_softc *sc) |
4054 | { |
4055 | uint32_t tmp; |
4056 | uint8_t rf; |
4057 | int i; |
4058 | |
4059 | /* Disable the GPIO bits 4 and 7 for LNA PE control. */ |
4060 | run_read(sc, RT3070_GPIO_SWITCH, &tmp); |
4061 | tmp &= ~(1 << 4 | 1 << 7); |
4062 | run_write(sc, RT3070_GPIO_SWITCH, tmp); |
4063 | |
4064 | /* Initialize RF registers to default value. */ |
4065 | for (i = 0; i < __arraycount(rt3593_def_rf); i++) { |
4066 | run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, |
4067 | rt3593_def_rf[i].val); |
4068 | } |
4069 | |
4070 | /* Toggle RF R2 to initiate calibration. */ |
4071 | run_rt3070_rf_write(sc, 2, RT5390_RESCAL); |
4072 | |
4073 | /* Initialize RF frequency offset. */ |
4074 | run_adjust_freq_offset(sc); |
4075 | |
4076 | run_rt3070_rf_read(sc, 18, &rf); |
4077 | run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); |
4078 | |
4079 | /* |
4080 | * Increase voltage from 1.2V to 1.35V, wait for 1 msec to |
4081 | * decrease voltage back to 1.2V. |
4082 | */ |
4083 | run_read(sc, RT3070_LDO_CFG0, &tmp); |
4084 | tmp = (tmp & ~0x1f000000) | 0x0d000000; |
4085 | run_write(sc, RT3070_LDO_CFG0, tmp); |
4086 | usbd_delay_ms(sc->sc_udev, 1); |
4087 | tmp = (tmp & ~0x1f000000) | 0x01000000; |
4088 | run_write(sc, RT3070_LDO_CFG0, tmp); |
4089 | |
4090 | sc->rf24_20mhz = 0x1f; |
4091 | sc->rf24_40mhz = 0x2f; |
4092 | |
4093 | /* Save default BBP registers 25 and 26 values. */ |
4094 | run_bbp_read(sc, 25, &sc->bbp25); |
4095 | run_bbp_read(sc, 26, &sc->bbp26); |
4096 | |
4097 | run_read(sc, RT3070_OPT_14, &tmp); |
4098 | run_write(sc, RT3070_OPT_14, tmp | 1); |
4099 | return (0); |
4100 | } |
4101 | |
4102 | static int |
4103 | run_rt5390_rf_init(struct run_softc *sc) |
4104 | { |
4105 | uint32_t tmp; |
4106 | uint8_t rf; |
4107 | int i; |
4108 | |
4109 | /* Toggle RF R2 to initiate calibration. */ |
4110 | if (sc->mac_ver == 0x5390) { |
4111 | run_rt3070_rf_read(sc, 2, &rf); |
4112 | run_rt3070_rf_write(sc, 2, rf | RT5390_RESCAL); |
4113 | usbd_delay_ms(sc->sc_udev, 10); |
4114 | run_rt3070_rf_write(sc, 2, rf & ~RT5390_RESCAL); |
4115 | } else { |
4116 | run_rt3070_rf_write(sc, 2, RT5390_RESCAL); |
4117 | usbd_delay_ms(sc->sc_udev, 10); |
4118 | } |
4119 | |
4120 | /* Initialize RF registers to default value. */ |
4121 | if (sc->mac_ver == 0x5592) { |
4122 | for (i = 0; i < __arraycount(rt5592_def_rf); i++) { |
4123 | run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, |
4124 | rt5592_def_rf[i].val); |
4125 | } |
4126 | /* Initialize RF frequency offset. */ |
4127 | run_adjust_freq_offset(sc); |
4128 | } else if (sc->mac_ver == 0x5392) { |
4129 | for (i = 0; i < __arraycount(rt5392_def_rf); i++) { |
4130 | run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, |
4131 | rt5392_def_rf[i].val); |
4132 | } |
4133 | if (sc->mac_rev >= 0x0223) { |
4134 | run_rt3070_rf_write(sc, 23, 0x0f); |
4135 | run_rt3070_rf_write(sc, 24, 0x3e); |
4136 | run_rt3070_rf_write(sc, 51, 0x32); |
4137 | run_rt3070_rf_write(sc, 53, 0x22); |
4138 | run_rt3070_rf_write(sc, 56, 0xc1); |
4139 | run_rt3070_rf_write(sc, 59, 0x0f); |
4140 | } |
4141 | } else { |
4142 | for (i = 0; i < __arraycount(rt5390_def_rf); i++) { |
4143 | run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, |
4144 | rt5390_def_rf[i].val); |
4145 | } |
4146 | if (sc->mac_rev >= 0x0502) { |
4147 | run_rt3070_rf_write(sc, 6, 0xe0); |
4148 | run_rt3070_rf_write(sc, 25, 0x80); |
4149 | run_rt3070_rf_write(sc, 46, 0x73); |
4150 | run_rt3070_rf_write(sc, 53, 0x00); |
4151 | run_rt3070_rf_write(sc, 56, 0x42); |
4152 | run_rt3070_rf_write(sc, 61, 0xd1); |
4153 | } |
4154 | } |
4155 | |
4156 | sc->rf24_20mhz = 0x1f; /* default value */ |
4157 | sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; |
4158 | |
4159 | if (sc->mac_rev < 0x0211) |
4160 | run_rt3070_rf_write(sc, 27, 0x3); |
4161 | |
4162 | run_read(sc, RT3070_OPT_14, &tmp); |
4163 | run_write(sc, RT3070_OPT_14, tmp | 1); |
4164 | return (0); |
4165 | } |
4166 | |
4167 | static int |
4168 | run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, |
4169 | uint8_t *val) |
4170 | { |
4171 | uint8_t rf22, rf24; |
4172 | uint8_t bbp55_pb, bbp55_sb, delta; |
4173 | int ntries; |
4174 | |
4175 | /* program filter */ |
4176 | run_rt3070_rf_read(sc, 24, &rf24); |
4177 | rf24 = (rf24 & 0xc0) | init; /* initial filter value */ |
4178 | run_rt3070_rf_write(sc, 24, rf24); |
4179 | |
4180 | /* enable baseband loopback mode */ |
4181 | run_rt3070_rf_read(sc, 22, &rf22); |
4182 | run_rt3070_rf_write(sc, 22, rf22 | 0x01); |
4183 | |
4184 | /* set power and frequency of passband test tone */ |
4185 | run_bbp_write(sc, 24, 0x00); |
4186 | for (ntries = 0; ntries < 100; ntries++) { |
4187 | /* transmit test tone */ |
4188 | run_bbp_write(sc, 25, 0x90); |
4189 | usbd_delay_ms(sc->sc_udev, 10); |
4190 | /* read received power */ |
4191 | run_bbp_read(sc, 55, &bbp55_pb); |
4192 | if (bbp55_pb != 0) |
4193 | break; |
4194 | } |
4195 | if (ntries == 100) |
4196 | return ETIMEDOUT; |
4197 | |
4198 | /* set power and frequency of stopband test tone */ |
4199 | run_bbp_write(sc, 24, 0x06); |
4200 | for (ntries = 0; ntries < 100; ntries++) { |
4201 | /* transmit test tone */ |
4202 | run_bbp_write(sc, 25, 0x90); |
4203 | usbd_delay_ms(sc->sc_udev, 10); |
4204 | /* read received power */ |
4205 | run_bbp_read(sc, 55, &bbp55_sb); |
4206 | |
4207 | delta = bbp55_pb - bbp55_sb; |
4208 | if (delta > target) |
4209 | break; |
4210 | |
4211 | /* reprogram filter */ |
4212 | rf24++; |
4213 | run_rt3070_rf_write(sc, 24, rf24); |
4214 | } |
4215 | if (ntries < 100) { |
4216 | if (rf24 != init) |
4217 | rf24--; /* backtrack */ |
4218 | *val = rf24; |
4219 | run_rt3070_rf_write(sc, 24, rf24); |
4220 | } |
4221 | |
4222 | /* restore initial state */ |
4223 | run_bbp_write(sc, 24, 0x00); |
4224 | |
4225 | /* disable baseband loopback mode */ |
4226 | run_rt3070_rf_read(sc, 22, &rf22); |
4227 | run_rt3070_rf_write(sc, 22, rf22 & ~0x01); |
4228 | |
4229 | return 0; |
4230 | } |
4231 | |
4232 | static void |
4233 | run_rt3070_rf_setup(struct run_softc *sc) |
4234 | { |
4235 | uint8_t bbp, rf; |
4236 | int i; |
4237 | |
4238 | if (sc->mac_ver == 0x3572) { |
4239 | /* enable DC filter */ |
4240 | if (sc->mac_rev >= 0x0201) |
4241 | run_bbp_write(sc, 103, 0xc0); |
4242 | |
4243 | run_bbp_read(sc, 138, &bbp); |
4244 | if (sc->ntxchains == 1) |
4245 | bbp |= 0x20; /* turn off DAC1 */ |
4246 | if (sc->nrxchains == 1) |
4247 | bbp &= ~0x02; /* turn off ADC1 */ |
4248 | run_bbp_write(sc, 138, bbp); |
4249 | |
4250 | if (sc->mac_rev >= 0x0211) { |
4251 | /* improve power consumption */ |
4252 | run_bbp_read(sc, 31, &bbp); |
4253 | run_bbp_write(sc, 31, bbp & ~0x03); |
4254 | } |
4255 | |
4256 | run_rt3070_rf_read(sc, 16, &rf); |
4257 | rf = (rf & ~0x07) | sc->txmixgain_2ghz; |
4258 | run_rt3070_rf_write(sc, 16, rf); |
4259 | } else if (sc->mac_ver == 0x3071) { |
4260 | /* enable DC filter */ |
4261 | if (sc->mac_rev >= 0x0201) |
4262 | run_bbp_write(sc, 103, 0xc0); |
4263 | |
4264 | run_bbp_read(sc, 138, &bbp); |
4265 | if (sc->ntxchains == 1) |
4266 | bbp |= 0x20; /* turn off DAC1 */ |
4267 | if (sc->nrxchains == 1) |
4268 | bbp &= ~0x02; /* turn off ADC1 */ |
4269 | run_bbp_write(sc, 138, bbp); |
4270 | |
4271 | if (sc->mac_rev >= 0x0211) { |
4272 | /* improve power consumption */ |
4273 | run_bbp_read(sc, 31, &bbp); |
4274 | run_bbp_write(sc, 31, bbp & ~0x03); |
4275 | } |
4276 | |
4277 | run_write(sc, RT2860_TX_SW_CFG1, 0); |
4278 | if (sc->mac_rev < 0x0211) { |
4279 | run_write(sc, RT2860_TX_SW_CFG2, |
4280 | sc->patch_dac ? 0x2c : 0x0f); |
4281 | } else |
4282 | run_write(sc, RT2860_TX_SW_CFG2, 0); |
4283 | } else if (sc->mac_ver == 0x3070) { |
4284 | if (sc->mac_rev >= 0x0201) { |
4285 | /* enable DC filter */ |
4286 | run_bbp_write(sc, 103, 0xc0); |
4287 | |
4288 | /* improve power consumption */ |
4289 | run_bbp_read(sc, 31, &bbp); |
4290 | run_bbp_write(sc, 31, bbp & ~0x03); |
4291 | } |
4292 | |
4293 | if (sc->mac_rev < 0x0211) { |
4294 | run_write(sc, RT2860_TX_SW_CFG1, 0); |
4295 | run_write(sc, RT2860_TX_SW_CFG2, 0x2c); |
4296 | } else |
4297 | run_write(sc, RT2860_TX_SW_CFG2, 0); |
4298 | } |
4299 | |
4300 | /* initialize RF registers from ROM for >=RT3071*/ |
4301 | if (sc->mac_ver >= 0x3071) { |
4302 | for (i = 0; i < 10; i++) { |
4303 | if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) |
4304 | continue; |
4305 | run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); |
4306 | } |
4307 | } |
4308 | } |
4309 | |
4310 | static void |
4311 | run_rt3593_rf_setup(struct run_softc *sc) |
4312 | { |
4313 | uint8_t bbp, rf; |
4314 | |
4315 | if (sc->mac_rev >= 0x0211) { |
4316 | /* Enable DC filter. */ |
4317 | run_bbp_write(sc, 103, 0xc0); |
4318 | } |
4319 | run_write(sc, RT2860_TX_SW_CFG1, 0); |
4320 | if (sc->mac_rev < 0x0211) { |
4321 | run_write(sc, RT2860_TX_SW_CFG2, |
4322 | sc->patch_dac ? 0x2c : 0x0f); |
4323 | } else |
4324 | run_write(sc, RT2860_TX_SW_CFG2, 0); |
4325 | |
4326 | run_rt3070_rf_read(sc, 50, &rf); |
4327 | run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); |
4328 | |
4329 | run_rt3070_rf_read(sc, 51, &rf); |
4330 | rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | |
4331 | ((sc->txmixgain_2ghz & 0x07) << 2); |
4332 | run_rt3070_rf_write(sc, 51, rf); |
4333 | |
4334 | run_rt3070_rf_read(sc, 38, &rf); |
4335 | run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); |
4336 | |
4337 | run_rt3070_rf_read(sc, 39, &rf); |
4338 | run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); |
4339 | |
4340 | run_rt3070_rf_read(sc, 1, &rf); |
4341 | run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); |
4342 | |
4343 | run_rt3070_rf_read(sc, 30, &rf); |
4344 | rf = (rf & ~0x18) | 0x10; |
4345 | run_rt3070_rf_write(sc, 30, rf); |
4346 | |
4347 | /* Apply maximum likelihood detection for 2 stream case. */ |
4348 | run_bbp_read(sc, 105, &bbp); |
4349 | if (sc->nrxchains > 1) |
4350 | run_bbp_write(sc, 105, bbp | RT5390_MLD); |
4351 | |
4352 | /* Avoid data lost and CRC error. */ |
4353 | run_bbp_read(sc, 4, &bbp); |
4354 | run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); |
4355 | |
4356 | run_bbp_write(sc, 92, 0x02); |
4357 | run_bbp_write(sc, 82, 0x82); |
4358 | run_bbp_write(sc, 106, 0x05); |
4359 | run_bbp_write(sc, 104, 0x92); |
4360 | run_bbp_write(sc, 88, 0x90); |
4361 | run_bbp_write(sc, 148, 0xc8); |
4362 | run_bbp_write(sc, 47, 0x48); |
4363 | run_bbp_write(sc, 120, 0x50); |
4364 | |
4365 | run_bbp_write(sc, 163, 0x9d); |
4366 | |
4367 | /* SNR mapping. */ |
4368 | run_bbp_write(sc, 142, 0x06); |
4369 | run_bbp_write(sc, 143, 0xa0); |
4370 | run_bbp_write(sc, 142, 0x07); |
4371 | run_bbp_write(sc, 143, 0xa1); |
4372 | run_bbp_write(sc, 142, 0x08); |
4373 | run_bbp_write(sc, 143, 0xa2); |
4374 | |
4375 | run_bbp_write(sc, 31, 0x08); |
4376 | run_bbp_write(sc, 68, 0x0b); |
4377 | run_bbp_write(sc, 105, 0x04); |
4378 | } |
4379 | |
4380 | static void |
4381 | run_rt5390_rf_setup(struct run_softc *sc) |
4382 | { |
4383 | uint8_t bbp, rf; |
4384 | |
4385 | if (sc->mac_rev >= 0x0211) { |
4386 | /* Enable DC filter. */ |
4387 | run_bbp_write(sc, 103, 0xc0); |
4388 | |
4389 | if (sc->mac_ver != 0x5592) { |
4390 | /* Improve power consumption. */ |
4391 | run_bbp_read(sc, 31, &bbp); |
4392 | run_bbp_write(sc, 31, bbp & ~0x03); |
4393 | } |
4394 | } |
4395 | |
4396 | run_bbp_read(sc, 138, &bbp); |
4397 | if (sc->ntxchains == 1) |
4398 | bbp |= 0x20; /* turn off DAC1 */ |
4399 | if (sc->nrxchains == 1) |
4400 | bbp &= ~0x02; /* turn off ADC1 */ |
4401 | run_bbp_write(sc, 138, bbp); |
4402 | |
4403 | run_rt3070_rf_read(sc, 38, &rf); |
4404 | run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); |
4405 | |
4406 | run_rt3070_rf_read(sc, 39, &rf); |
4407 | run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); |
4408 | |
4409 | /* Avoid data lost and CRC error. */ |
4410 | run_bbp_read(sc, 4, &bbp); |
4411 | run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); |
4412 | |
4413 | run_rt3070_rf_read(sc, 30, &rf); |
4414 | rf = (rf & ~0x18) | 0x10; |
4415 | run_rt3070_rf_write(sc, 30, rf); |
4416 | |
4417 | if (sc->mac_ver != 0x5592) { |
4418 | run_write(sc, RT2860_TX_SW_CFG1, 0); |
4419 | if (sc->mac_rev < 0x0211) { |
4420 | run_write(sc, RT2860_TX_SW_CFG2, |
4421 | sc->patch_dac ? 0x2c : 0x0f); |
4422 | } else |
4423 | run_write(sc, RT2860_TX_SW_CFG2, 0); |
4424 | } |
4425 | } |
4426 | |
4427 | static int |
4428 | run_txrx_enable(struct run_softc *sc) |
4429 | { |
4430 | uint32_t tmp; |
4431 | int error, ntries; |
4432 | |
4433 | run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); |
4434 | for (ntries = 0; ntries < 200; ntries++) { |
4435 | if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) |
4436 | return error; |
4437 | if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) |
4438 | break; |
4439 | usbd_delay_ms(sc->sc_udev, 50); |
4440 | } |
4441 | if (ntries == 200) |
4442 | return ETIMEDOUT; |
4443 | |
4444 | usbd_delay_ms(sc->sc_udev, 50); |
4445 | |
4446 | tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE; |
4447 | run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); |
4448 | |
4449 | /* enable Rx bulk aggregation (set timeout and limit) */ |
4450 | tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN | |
4451 | RT2860_USB_RX_AGG_TO(128) | RT2860_USB_RX_AGG_LMT(2); |
4452 | run_write(sc, RT2860_USB_DMA_CFG, tmp); |
4453 | |
4454 | /* set Rx filter */ |
4455 | tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; |
4456 | if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { |
4457 | tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | |
4458 | RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | |
4459 | RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | |
4460 | RT2860_DROP_CFACK | RT2860_DROP_CFEND; |
4461 | if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) |
4462 | tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; |
4463 | } |
4464 | run_write(sc, RT2860_RX_FILTR_CFG, tmp); |
4465 | |
4466 | run_write(sc, RT2860_MAC_SYS_CTRL, |
4467 | RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); |
4468 | |
4469 | return 0; |
4470 | } |
4471 | |
4472 | static int |
4473 | run_adjust_freq_offset(struct run_softc *sc) |
4474 | { |
4475 | uint8_t rf, tmp; |
4476 | |
4477 | run_rt3070_rf_read(sc, 17, &rf); |
4478 | tmp = rf; |
4479 | rf = (rf & ~0x7f) | (sc->freq & 0x7f); |
4480 | rf = MIN(rf, 0x5f); |
4481 | |
4482 | if (tmp != rf) |
4483 | run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); |
4484 | |
4485 | return (0); |
4486 | } |
4487 | |
4488 | static int |
4489 | run_init(struct ifnet *ifp) |
4490 | { |
4491 | struct run_softc *sc = ifp->if_softc; |
4492 | struct ieee80211com *ic = &sc->sc_ic; |
4493 | uint32_t tmp; |
4494 | uint8_t bbp1, bbp3; |
4495 | int i, error, qid, ridx, ntries; |
4496 | |
4497 | for (ntries = 0; ntries < 100; ntries++) { |
4498 | if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0) |
4499 | goto fail; |
4500 | if (tmp != 0 && tmp != 0xffffffff) |
4501 | break; |
4502 | usbd_delay_ms(sc->sc_udev, 10); |
4503 | } |
4504 | if (ntries == 100) { |
4505 | error = ETIMEDOUT; |
4506 | goto fail; |
4507 | } |
4508 | |
4509 | if ((sc->sc_flags & RUN_FWLOADED) == 0 && |
4510 | (error = run_load_microcode(sc)) != 0) { |
4511 | aprint_error_dev(sc->sc_dev, |
4512 | "could not load 8051 microcode\n" ); |
4513 | goto fail; |
4514 | } |
4515 | |
4516 | if (ifp->if_flags & IFF_RUNNING) |
4517 | run_stop(ifp, 0); |
4518 | |
4519 | /* init host command ring */ |
4520 | sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; |
4521 | |
4522 | /* init Tx rings (4 EDCAs) */ |
4523 | for (qid = 0; qid < 4; qid++) { |
4524 | if ((error = run_alloc_tx_ring(sc, qid)) != 0) |
4525 | goto fail; |
4526 | } |
4527 | /* init Rx ring */ |
4528 | if ((error = run_alloc_rx_ring(sc)) != 0) |
4529 | goto fail; |
4530 | |
4531 | IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); |
4532 | run_set_macaddr(sc, ic->ic_myaddr); |
4533 | |
4534 | for (ntries = 0; ntries < 100; ntries++) { |
4535 | if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) |
4536 | goto fail; |
4537 | if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) |
4538 | break; |
4539 | usbd_delay_ms(sc->sc_udev, 10); |
4540 | } |
4541 | if (ntries == 100) { |
4542 | aprint_error_dev(sc->sc_dev, |
4543 | "timeout waiting for DMA engine\n" ); |
4544 | error = ETIMEDOUT; |
4545 | goto fail; |
4546 | } |
4547 | tmp &= 0xff0; |
4548 | tmp |= RT2860_TX_WB_DDONE; |
4549 | run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); |
4550 | |
4551 | /* turn off PME_OEN to solve high-current issue */ |
4552 | run_read(sc, RT2860_SYS_CTRL, &tmp); |
4553 | run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN); |
4554 | |
4555 | run_write(sc, RT2860_MAC_SYS_CTRL, |
4556 | RT2860_BBP_HRST | RT2860_MAC_SRST); |
4557 | run_write(sc, RT2860_USB_DMA_CFG, 0); |
4558 | |
4559 | if ((error = run_reset(sc)) != 0) { |
4560 | aprint_error_dev(sc->sc_dev, "could not reset chipset\n" ); |
4561 | goto fail; |
4562 | } |
4563 | |
4564 | run_write(sc, RT2860_MAC_SYS_CTRL, 0); |
4565 | |
4566 | /* init Tx power for all Tx rates (from EEPROM) */ |
4567 | for (ridx = 0; ridx < 5; ridx++) { |
4568 | if (sc->txpow20mhz[ridx] == 0xffffffff) |
4569 | continue; |
4570 | run_write(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); |
4571 | } |
4572 | |
4573 | for (i = 0; i < (int)__arraycount(rt2870_def_mac); i++) |
4574 | run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); |
4575 | run_write(sc, RT2860_WMM_AIFSN_CFG, 0x00002273); |
4576 | run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344); |
4577 | run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa); |
4578 | |
4579 | if (sc->mac_ver >= 0x5390) { |
4580 | run_write(sc, RT2860_TX_SW_CFG0, |
4581 | 4 << RT2860_DLY_PAPE_EN_SHIFT | 4); |
4582 | if (sc->mac_ver >= 0x5392) { |
4583 | run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff); |
4584 | if (sc->mac_ver == 0x5592) { |
4585 | run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980); |
4586 | run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082); |
4587 | } else { |
4588 | run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980); |
4589 | run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); |
4590 | } |
4591 | } |
4592 | } else if (sc->mac_ver >= 0x3593) { |
4593 | run_write(sc, RT2860_TX_SW_CFG0, |
4594 | 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); |
4595 | } else if (sc->mac_ver >= 0x3070) { |
4596 | /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ |
4597 | run_write(sc, RT2860_TX_SW_CFG0, |
4598 | 4 << RT2860_DLY_PAPE_EN_SHIFT); |
4599 | } |
4600 | |
4601 | /* wait while MAC is busy */ |
4602 | for (ntries = 0; ntries < 100; ntries++) { |
4603 | if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0) |
4604 | goto fail; |
4605 | if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) |
4606 | break; |
4607 | DELAY(1000); |
4608 | } |
4609 | if (ntries == 100) { |
4610 | error = ETIMEDOUT; |
4611 | goto fail; |
4612 | } |
4613 | |
4614 | /* clear Host to MCU mailbox */ |
4615 | run_write(sc, RT2860_H2M_BBPAGENT, 0); |
4616 | run_write(sc, RT2860_H2M_MAILBOX, 0); |
4617 | usbd_delay_ms(sc->sc_udev, 10); |
4618 | |
4619 | if ((error = run_bbp_init(sc)) != 0) { |
4620 | aprint_error_dev(sc->sc_dev, "could not initialize BBP\n" ); |
4621 | goto fail; |
4622 | } |
4623 | |
4624 | /* abort TSF synchronization */ |
4625 | run_read(sc, RT2860_BCN_TIME_CFG, &tmp); |
4626 | tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | |
4627 | RT2860_TBTT_TIMER_EN); |
4628 | run_write(sc, RT2860_BCN_TIME_CFG, tmp); |
4629 | |
4630 | /* clear RX WCID search table */ |
4631 | run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); |
4632 | /* clear Pair-wise key table */ |
4633 | run_set_region_4(sc, RT2860_PKEY(0), 0, 2048); |
4634 | /* clear IV/EIV table */ |
4635 | run_set_region_4(sc, RT2860_IVEIV(0), 0, 512); |
4636 | /* clear WCID attribute table */ |
4637 | run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); |
4638 | /* clear shared key table */ |
4639 | run_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); |
4640 | /* clear shared key mode */ |
4641 | run_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); |
4642 | |
4643 | /* clear RX WCID search table */ |
4644 | run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); |
4645 | /* clear WCID attribute table */ |
4646 | run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); |
4647 | |
4648 | run_read(sc, RT2860_US_CYC_CNT, &tmp); |
4649 | tmp = (tmp & ~0xff) | 0x1e; |
4650 | run_write(sc, RT2860_US_CYC_CNT, tmp); |
4651 | |
4652 | if (sc->mac_rev != 0x0101) |
4653 | run_write(sc, RT2860_TXOP_CTRL_CFG, 0x0000583f); |
4654 | |
4655 | run_write(sc, RT2860_WMM_TXOP0_CFG, 0); |
4656 | run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); |
4657 | |
4658 | /* write vendor-specific BBP values (from EEPROM) */ |
4659 | if (sc->mac_ver < 0x3593) { |
4660 | for (i = 0; i < 10; i++) { |
4661 | if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) |
4662 | continue; |
4663 | run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); |
4664 | } |
4665 | } |
4666 | |
4667 | /* select Main antenna for 1T1R devices */ |
4668 | if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370) |
4669 | run_set_rx_antenna(sc, 0); |
4670 | |
4671 | /* send LEDs operating mode to microcontroller */ |
4672 | (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); |
4673 | (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); |
4674 | (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); |
4675 | |
4676 | if (sc->mac_ver >= 0x5390) |
4677 | run_rt5390_rf_init(sc); |
4678 | else if (sc->mac_ver == 0x3593) |
4679 | run_rt3593_rf_init(sc); |
4680 | else if (sc->mac_ver >= 0x3070) |
4681 | run_rt3070_rf_init(sc); |
4682 | |
4683 | /* disable non-existing Rx chains */ |
4684 | run_bbp_read(sc, 3, &bbp3); |
4685 | bbp3 &= ~(1 << 3 | 1 << 4); |
4686 | if (sc->nrxchains == 2) |
4687 | bbp3 |= 1 << 3; |
4688 | else if (sc->nrxchains == 3) |
4689 | bbp3 |= 1 << 4; |
4690 | run_bbp_write(sc, 3, bbp3); |
4691 | |
4692 | /* disable non-existing Tx chains */ |
4693 | run_bbp_read(sc, 1, &bbp1); |
4694 | if (sc->ntxchains == 1) |
4695 | bbp1 &= ~(1 << 3 | 1 << 4); |
4696 | run_bbp_write(sc, 1, bbp1); |
4697 | |
4698 | if (sc->mac_ver >= 0x5390) |
4699 | run_rt5390_rf_setup(sc); |
4700 | else if (sc->mac_ver == 0x3593) |
4701 | run_rt3593_rf_setup(sc); |
4702 | else if (sc->mac_ver >= 0x3070) |
4703 | run_rt3070_rf_setup(sc); |
4704 | |
4705 | /* select default channel */ |
4706 | run_set_chan(sc, ic->ic_curchan); |
4707 | |
4708 | /* setup initial protection mode */ |
4709 | run_updateprot(sc); |
4710 | |
4711 | /* turn radio LED on */ |
4712 | run_set_leds(sc, RT2860_LED_RADIO); |
4713 | |
4714 | #ifdef RUN_HWCRYPTO |
4715 | if (ic->ic_flags & IEEE80211_F_PRIVACY) { |
4716 | /* install WEP keys */ |
4717 | for (i = 0; i < IEEE80211_WEP_NKID; i++) |
4718 | (void)run_set_key(ic, &ic->ic_crypto.cs_nw_keys[i], |
4719 | NULL); |
4720 | } |
4721 | #endif |
4722 | |
4723 | for (i = 0; i < RUN_RX_RING_COUNT; i++) { |
4724 | struct run_rx_data *data = &sc->rxq.data[i]; |
4725 | |
4726 | usbd_setup_xfer(data->xfer, data, data->buf, RUN_MAX_RXSZ, |
4727 | USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); |
4728 | error = usbd_transfer(data->xfer); |
4729 | if (error != USBD_NORMAL_COMPLETION && |
4730 | error != USBD_IN_PROGRESS) |
4731 | goto fail; |
4732 | } |
4733 | |
4734 | if ((error = run_txrx_enable(sc)) != 0) |
4735 | goto fail; |
4736 | |
4737 | ifp->if_flags &= ~IFF_OACTIVE; |
4738 | ifp->if_flags |= IFF_RUNNING; |
4739 | |
4740 | if (ic->ic_opmode == IEEE80211_M_MONITOR) |
4741 | ieee80211_new_state(ic, IEEE80211_S_RUN, -1); |
4742 | else |
4743 | ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); |
4744 | |
4745 | if (error != 0) |
4746 | fail: run_stop(ifp, 1); |
4747 | return error; |
4748 | } |
4749 | |
4750 | static void |
4751 | run_stop(struct ifnet *ifp, int disable) |
4752 | { |
4753 | struct run_softc *sc = ifp->if_softc; |
4754 | struct ieee80211com *ic = &sc->sc_ic; |
4755 | uint32_t tmp; |
4756 | int ntries, qid; |
4757 | |
4758 | if (ifp->if_flags & IFF_RUNNING) |
4759 | run_set_leds(sc, 0); /* turn all LEDs off */ |
4760 | |
4761 | sc->sc_tx_timer = 0; |
4762 | ifp->if_timer = 0; |
4763 | ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); |
4764 | |
4765 | callout_stop(&sc->scan_to); |
4766 | callout_stop(&sc->calib_to); |
4767 | |
4768 | ieee80211_new_state(ic, IEEE80211_S_INIT, -1); |
4769 | /* wait for all queued asynchronous commands to complete */ |
4770 | while (sc->cmdq.queued > 0) |
4771 | tsleep(&sc->cmdq, 0, "cmdq" , 0); |
4772 | |
4773 | /* disable Tx/Rx */ |
4774 | run_read(sc, RT2860_MAC_SYS_CTRL, &tmp); |
4775 | tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); |
4776 | run_write(sc, RT2860_MAC_SYS_CTRL, tmp); |
4777 | |
4778 | /* wait for pending Tx to complete */ |
4779 | for (ntries = 0; ntries < 100; ntries++) { |
4780 | if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) |
4781 | break; |
4782 | if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) |
4783 | break; |
4784 | } |
4785 | DELAY(1000); |
4786 | run_write(sc, RT2860_USB_DMA_CFG, 0); |
4787 | |
4788 | /* reset adapter */ |
4789 | run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); |
4790 | run_write(sc, RT2860_MAC_SYS_CTRL, 0); |
4791 | |
4792 | /* reset Tx and Rx rings */ |
4793 | sc->qfullmsk = 0; |
4794 | for (qid = 0; qid < 4; qid++) |
4795 | run_free_tx_ring(sc, qid); |
4796 | run_free_rx_ring(sc); |
4797 | } |
4798 | |
4799 | #ifndef IEEE80211_STA_ONLY |
4800 | static int |
4801 | run_setup_beacon(struct run_softc *sc) |
4802 | { |
4803 | struct ieee80211com *ic = &sc->sc_ic; |
4804 | struct rt2860_txwi txwi; |
4805 | struct mbuf *m; |
4806 | uint16_t txwisize; |
4807 | int ridx; |
4808 | |
4809 | if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss, &sc->sc_bo)) == NULL) |
4810 | return ENOBUFS; |
4811 | |
4812 | memset(&txwi, 0, sizeof(txwi)); |
4813 | txwi.wcid = 0xff; |
4814 | txwi.len = htole16(m->m_pkthdr.len); |
4815 | /* send beacons at the lowest available rate */ |
4816 | ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? |
4817 | RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; |
4818 | txwi.phy = htole16(rt2860_rates[ridx].mcs); |
4819 | if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) |
4820 | txwi.phy |= htole16(RT2860_PHY_OFDM); |
4821 | txwi.txop = RT2860_TX_TXOP_HT; |
4822 | txwi.flags = RT2860_TX_TS; |
4823 | |
4824 | txwisize = (sc->mac_ver == 0x5592) ? |
4825 | sizeof(txwi) + sizeof(uint32_t) : sizeof(txwi); |
4826 | run_write_region_1(sc, RT2860_BCN_BASE(0), |
4827 | (uint8_t *)&txwi, txwisize); |
4828 | run_write_region_1(sc, RT2860_BCN_BASE(0) + txwisize, |
4829 | mtod(m, uint8_t *), (m->m_pkthdr.len + 1) & ~1); |
4830 | |
4831 | m_freem(m); |
4832 | |
4833 | return 0; |
4834 | } |
4835 | #endif |
4836 | |
4837 | MODULE(MODULE_CLASS_DRIVER, if_run, "bpf" ); |
4838 | |
4839 | #ifdef _MODULE |
4840 | #include "ioconf.c" |
4841 | #endif |
4842 | |
4843 | static int |
4844 | if_run_modcmd(modcmd_t cmd, void *arg) |
4845 | { |
4846 | int error = 0; |
4847 | |
4848 | switch (cmd) { |
4849 | case MODULE_CMD_INIT: |
4850 | #ifdef _MODULE |
4851 | error = config_init_component(cfdriver_ioconf_run, |
4852 | cfattach_ioconf_run, cfdata_ioconf_run); |
4853 | #endif |
4854 | return error; |
4855 | case MODULE_CMD_FINI: |
4856 | #ifdef _MODULE |
4857 | error = config_fini_component(cfdriver_ioconf_run, |
4858 | cfattach_ioconf_run, cfdata_ioconf_run); |
4859 | #endif |
4860 | return error; |
4861 | default: |
4862 | return ENOTTY; |
4863 | } |
4864 | } |
4865 | |