1 | /* $NetBSD: nouveau_subdev_i2c_anx9805.c,v 1.1.1.1 2014/08/06 12:36:30 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2013 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs <bskeggs@redhat.com> |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_i2c_anx9805.c,v 1.1.1.1 2014/08/06 12:36:30 riastradh Exp $" ); |
29 | |
30 | #include <subdev/i2c.h> |
31 | |
32 | struct anx9805_i2c_port { |
33 | struct nouveau_i2c_port base; |
34 | u32 addr; |
35 | u32 ctrl; |
36 | }; |
37 | |
38 | static int |
39 | anx9805_train(struct nouveau_i2c_port *port, int link_nr, int link_bw, bool enh) |
40 | { |
41 | struct anx9805_i2c_port *chan = (void *)port; |
42 | struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent; |
43 | u8 tmp, i; |
44 | |
45 | nv_wri2cr(mast, chan->addr, 0xa0, link_bw); |
46 | nv_wri2cr(mast, chan->addr, 0xa1, link_nr | (enh ? 0x80 : 0x00)); |
47 | nv_wri2cr(mast, chan->addr, 0xa2, 0x01); |
48 | nv_wri2cr(mast, chan->addr, 0xa8, 0x01); |
49 | |
50 | i = 0; |
51 | while ((tmp = nv_rdi2cr(mast, chan->addr, 0xa8)) & 0x01) { |
52 | mdelay(5); |
53 | if (i++ == 100) { |
54 | nv_error(port, "link training timed out\n" ); |
55 | return -ETIMEDOUT; |
56 | } |
57 | } |
58 | |
59 | if (tmp & 0x70) { |
60 | nv_error(port, "link training failed: 0x%02x\n" , tmp); |
61 | return -EIO; |
62 | } |
63 | |
64 | return 1; |
65 | } |
66 | |
67 | static int |
68 | anx9805_aux(struct nouveau_i2c_port *port, u8 type, u32 addr, u8 *data, u8 size) |
69 | { |
70 | struct anx9805_i2c_port *chan = (void *)port; |
71 | struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent; |
72 | int i, ret = -ETIMEDOUT; |
73 | u8 tmp; |
74 | |
75 | tmp = nv_rdi2cr(mast, chan->ctrl, 0x07) & ~0x04; |
76 | nv_wri2cr(mast, chan->ctrl, 0x07, tmp | 0x04); |
77 | nv_wri2cr(mast, chan->ctrl, 0x07, tmp); |
78 | nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01); |
79 | |
80 | nv_wri2cr(mast, chan->addr, 0xe4, 0x80); |
81 | for (i = 0; !(type & 1) && i < size; i++) |
82 | nv_wri2cr(mast, chan->addr, 0xf0 + i, data[i]); |
83 | nv_wri2cr(mast, chan->addr, 0xe5, ((size - 1) << 4) | type); |
84 | nv_wri2cr(mast, chan->addr, 0xe6, (addr & 0x000ff) >> 0); |
85 | nv_wri2cr(mast, chan->addr, 0xe7, (addr & 0x0ff00) >> 8); |
86 | nv_wri2cr(mast, chan->addr, 0xe8, (addr & 0xf0000) >> 16); |
87 | nv_wri2cr(mast, chan->addr, 0xe9, 0x01); |
88 | |
89 | i = 0; |
90 | while ((tmp = nv_rdi2cr(mast, chan->addr, 0xe9)) & 0x01) { |
91 | mdelay(5); |
92 | if (i++ == 32) |
93 | goto done; |
94 | } |
95 | |
96 | if ((tmp = nv_rdi2cr(mast, chan->ctrl, 0xf7)) & 0x01) { |
97 | ret = -EIO; |
98 | goto done; |
99 | } |
100 | |
101 | for (i = 0; (type & 1) && i < size; i++) |
102 | data[i] = nv_rdi2cr(mast, chan->addr, 0xf0 + i); |
103 | ret = 0; |
104 | done: |
105 | nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01); |
106 | return ret; |
107 | } |
108 | |
109 | static const struct nouveau_i2c_func |
110 | anx9805_aux_func = { |
111 | .aux = anx9805_aux, |
112 | .lnk_ctl = anx9805_train, |
113 | }; |
114 | |
115 | static int |
116 | anx9805_aux_chan_ctor(struct nouveau_object *parent, |
117 | struct nouveau_object *engine, |
118 | struct nouveau_oclass *oclass, void *data, u32 index, |
119 | struct nouveau_object **pobject) |
120 | { |
121 | struct nouveau_i2c_port *mast = (void *)parent; |
122 | struct anx9805_i2c_port *chan; |
123 | int ret; |
124 | |
125 | ret = nouveau_i2c_port_create(parent, engine, oclass, index, |
126 | &nouveau_i2c_aux_algo, &anx9805_aux_func, |
127 | &chan); |
128 | *pobject = nv_object(chan); |
129 | if (ret) |
130 | return ret; |
131 | |
132 | switch ((oclass->handle & 0xff00) >> 8) { |
133 | case 0x0d: |
134 | chan->addr = 0x38; |
135 | chan->ctrl = 0x39; |
136 | break; |
137 | case 0x0e: |
138 | chan->addr = 0x3c; |
139 | chan->ctrl = 0x3b; |
140 | break; |
141 | default: |
142 | BUG_ON(1); |
143 | } |
144 | |
145 | if (mast->adapter.algo == &i2c_bit_algo) { |
146 | struct i2c_algo_bit_data *algo = mast->adapter.algo_data; |
147 | algo->udelay = max(algo->udelay, 40); |
148 | } |
149 | return 0; |
150 | } |
151 | |
152 | static struct nouveau_ofuncs |
153 | anx9805_aux_ofuncs = { |
154 | .ctor = anx9805_aux_chan_ctor, |
155 | .dtor = _nouveau_i2c_port_dtor, |
156 | .init = _nouveau_i2c_port_init, |
157 | .fini = _nouveau_i2c_port_fini, |
158 | }; |
159 | |
160 | static int |
161 | anx9805_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) |
162 | { |
163 | struct anx9805_i2c_port *port = adap->algo_data; |
164 | struct nouveau_i2c_port *mast = (void *)nv_object(port)->parent; |
165 | struct i2c_msg *msg = msgs; |
166 | int ret = -ETIMEDOUT; |
167 | int i, j, cnt = num; |
168 | u8 seg = 0x00, off = 0x00, tmp; |
169 | |
170 | tmp = nv_rdi2cr(mast, port->ctrl, 0x07) & ~0x10; |
171 | nv_wri2cr(mast, port->ctrl, 0x07, tmp | 0x10); |
172 | nv_wri2cr(mast, port->ctrl, 0x07, tmp); |
173 | nv_wri2cr(mast, port->addr, 0x43, 0x05); |
174 | mdelay(5); |
175 | |
176 | while (cnt--) { |
177 | if ( (msg->flags & I2C_M_RD) && msg->addr == 0x50) { |
178 | nv_wri2cr(mast, port->addr, 0x40, msg->addr << 1); |
179 | nv_wri2cr(mast, port->addr, 0x41, seg); |
180 | nv_wri2cr(mast, port->addr, 0x42, off); |
181 | nv_wri2cr(mast, port->addr, 0x44, msg->len); |
182 | nv_wri2cr(mast, port->addr, 0x45, 0x00); |
183 | nv_wri2cr(mast, port->addr, 0x43, 0x01); |
184 | for (i = 0; i < msg->len; i++) { |
185 | j = 0; |
186 | while (nv_rdi2cr(mast, port->addr, 0x46) & 0x10) { |
187 | mdelay(5); |
188 | if (j++ == 32) |
189 | goto done; |
190 | } |
191 | msg->buf[i] = nv_rdi2cr(mast, port->addr, 0x47); |
192 | } |
193 | } else |
194 | if (!(msg->flags & I2C_M_RD)) { |
195 | if (msg->addr == 0x50 && msg->len == 0x01) { |
196 | off = msg->buf[0]; |
197 | } else |
198 | if (msg->addr == 0x30 && msg->len == 0x01) { |
199 | seg = msg->buf[0]; |
200 | } else |
201 | goto done; |
202 | } else { |
203 | goto done; |
204 | } |
205 | msg++; |
206 | } |
207 | |
208 | ret = num; |
209 | done: |
210 | nv_wri2cr(mast, port->addr, 0x43, 0x00); |
211 | return ret; |
212 | } |
213 | |
214 | static u32 |
215 | anx9805_func(struct i2c_adapter *adap) |
216 | { |
217 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
218 | } |
219 | |
220 | static const struct i2c_algorithm |
221 | anx9805_i2c_algo = { |
222 | .master_xfer = anx9805_xfer, |
223 | .functionality = anx9805_func |
224 | }; |
225 | |
226 | static const struct nouveau_i2c_func |
227 | anx9805_i2c_func = { |
228 | }; |
229 | |
230 | static int |
231 | anx9805_ddc_port_ctor(struct nouveau_object *parent, |
232 | struct nouveau_object *engine, |
233 | struct nouveau_oclass *oclass, void *data, u32 index, |
234 | struct nouveau_object **pobject) |
235 | { |
236 | struct nouveau_i2c_port *mast = (void *)parent; |
237 | struct anx9805_i2c_port *port; |
238 | int ret; |
239 | |
240 | ret = nouveau_i2c_port_create(parent, engine, oclass, index, |
241 | &anx9805_i2c_algo, &anx9805_i2c_func, |
242 | &port); |
243 | *pobject = nv_object(port); |
244 | if (ret) |
245 | return ret; |
246 | |
247 | switch ((oclass->handle & 0xff00) >> 8) { |
248 | case 0x0d: |
249 | port->addr = 0x3d; |
250 | port->ctrl = 0x39; |
251 | break; |
252 | case 0x0e: |
253 | port->addr = 0x3f; |
254 | port->ctrl = 0x3b; |
255 | break; |
256 | default: |
257 | BUG_ON(1); |
258 | } |
259 | |
260 | if (mast->adapter.algo == &i2c_bit_algo) { |
261 | struct i2c_algo_bit_data *algo = mast->adapter.algo_data; |
262 | algo->udelay = max(algo->udelay, 40); |
263 | } |
264 | return 0; |
265 | } |
266 | |
267 | static struct nouveau_ofuncs |
268 | anx9805_ddc_ofuncs = { |
269 | .ctor = anx9805_ddc_port_ctor, |
270 | .dtor = _nouveau_i2c_port_dtor, |
271 | .init = _nouveau_i2c_port_init, |
272 | .fini = _nouveau_i2c_port_fini, |
273 | }; |
274 | |
275 | struct nouveau_oclass |
276 | nouveau_anx9805_sclass[] = { |
277 | { .handle = NV_I2C_TYPE_EXTDDC(0x0d), .ofuncs = &anx9805_ddc_ofuncs }, |
278 | { .handle = NV_I2C_TYPE_EXTAUX(0x0d), .ofuncs = &anx9805_aux_ofuncs }, |
279 | { .handle = NV_I2C_TYPE_EXTDDC(0x0e), .ofuncs = &anx9805_ddc_ofuncs }, |
280 | { .handle = NV_I2C_TYPE_EXTAUX(0x0e), .ofuncs = &anx9805_aux_ofuncs }, |
281 | {} |
282 | }; |
283 | |