1 | /* $Id: rt2661reg.h,v 1.3 2008/04/29 22:21:45 scw Exp $ */ |
2 | /* $OpenBSD: rt2661reg.h,v 1.5 2006/01/14 12:43:27 damien Exp $ */ |
3 | |
4 | /*- |
5 | * Copyright (c) 2006 |
6 | * Damien Bergamini <damien.bergamini@free.fr> |
7 | * |
8 | * Permission to use, copy, modify, and distribute this software for any |
9 | * purpose with or without fee is hereby granted, provided that the above |
10 | * copyright notice and this permission notice appear in all copies. |
11 | * |
12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
19 | */ |
20 | |
21 | #define RT2661_TX_RING_COUNT 32 |
22 | #define RT2661_MGT_RING_COUNT 32 |
23 | #define RT2661_RX_RING_COUNT 64 |
24 | |
25 | #define RT2661_TX_DESC_SIZE (sizeof (struct rt2661_tx_desc)) |
26 | #define RT2661_TX_DESC_WSIZE (RT2661_TX_DESC_SIZE / 4) |
27 | #define RT2661_RX_DESC_SIZE (sizeof (struct rt2661_rx_desc)) |
28 | #define RT2661_RX_DESC_WSIZE (RT2661_RX_DESC_SIZE / 4) |
29 | |
30 | #define RT2661_MAX_SCATTER 5 |
31 | |
32 | /* |
33 | * Control and status registers. |
34 | */ |
35 | #define RT2661_HOST_CMD_CSR 0x0008 |
36 | #define RT2661_MCU_CNTL_CSR 0x000c |
37 | #define RT2661_SOFT_RESET_CSR 0x0010 |
38 | #define RT2661_MCU_INT_SOURCE_CSR 0x0014 |
39 | #define RT2661_MCU_INT_MASK_CSR 0x0018 |
40 | #define RT2661_PCI_USEC_CSR 0x001c |
41 | #define RT2661_H2M_MAILBOX_CSR 0x2100 |
42 | #define RT2661_M2H_CMD_DONE_CSR 0x2104 |
43 | #define RT2661_HW_BEACON_BASE0 0x2c00 |
44 | #define RT2661_MAC_CSR0 0x3000 |
45 | #define RT2661_MAC_CSR1 0x3004 |
46 | #define RT2661_MAC_CSR2 0x3008 |
47 | #define RT2661_MAC_CSR3 0x300c |
48 | #define RT2661_MAC_CSR4 0x3010 |
49 | #define RT2661_MAC_CSR5 0x3014 |
50 | #define RT2661_MAC_CSR6 0x3018 |
51 | #define RT2661_MAC_CSR7 0x301c |
52 | #define RT2661_MAC_CSR8 0x3020 |
53 | #define RT2661_MAC_CSR9 0x3024 |
54 | #define RT2661_MAC_CSR10 0x3028 |
55 | #define RT2661_MAC_CSR11 0x302c |
56 | #define RT2661_MAC_CSR12 0x3030 |
57 | #define RT2661_MAC_CSR13 0x3034 |
58 | #define RT2661_MAC_CSR14 0x3038 |
59 | #define RT2661_MAC_CSR15 0x303c |
60 | #define RT2661_TXRX_CSR0 0x3040 |
61 | #define RT2661_TXRX_CSR1 0x3044 |
62 | #define RT2661_TXRX_CSR2 0x3048 |
63 | #define RT2661_TXRX_CSR3 0x304c |
64 | #define RT2661_TXRX_CSR4 0x3050 |
65 | #define RT2661_TXRX_CSR5 0x3054 |
66 | #define RT2661_TXRX_CSR6 0x3058 |
67 | #define RT2661_TXRX_CSR7 0x305c |
68 | #define RT2661_TXRX_CSR8 0x3060 |
69 | #define RT2661_TXRX_CSR9 0x3064 |
70 | #define RT2661_TXRX_CSR10 0x3068 |
71 | #define RT2661_TXRX_CSR11 0x306c |
72 | #define RT2661_TXRX_CSR12 0x3070 |
73 | #define RT2661_TXRX_CSR13 0x3074 |
74 | #define RT2661_TXRX_CSR14 0x3078 |
75 | #define RT2661_TXRX_CSR15 0x307c |
76 | #define RT2661_PHY_CSR0 0x3080 |
77 | #define RT2661_PHY_CSR1 0x3084 |
78 | #define RT2661_PHY_CSR2 0x3088 |
79 | #define RT2661_PHY_CSR3 0x308c |
80 | #define RT2661_PHY_CSR4 0x3090 |
81 | #define RT2661_PHY_CSR5 0x3094 |
82 | #define RT2661_PHY_CSR6 0x3098 |
83 | #define RT2661_PHY_CSR7 0x309c |
84 | #define RT2661_SEC_CSR0 0x30a0 |
85 | #define RT2661_SEC_CSR1 0x30a4 |
86 | #define RT2661_SEC_CSR2 0x30a8 |
87 | #define RT2661_SEC_CSR3 0x30ac |
88 | #define RT2661_SEC_CSR4 0x30b0 |
89 | #define RT2661_SEC_CSR5 0x30b4 |
90 | #define RT2661_STA_CSR0 0x30c0 |
91 | #define RT2661_STA_CSR1 0x30c4 |
92 | #define RT2661_STA_CSR2 0x30c8 |
93 | #define RT2661_STA_CSR3 0x30cc |
94 | #define RT2661_STA_CSR4 0x30d0 |
95 | #define RT2661_AC0_BASE_CSR 0x3400 |
96 | #define RT2661_AC1_BASE_CSR 0x3404 |
97 | #define RT2661_AC2_BASE_CSR 0x3408 |
98 | #define RT2661_AC3_BASE_CSR 0x340c |
99 | #define RT2661_MGT_BASE_CSR 0x3410 |
100 | #define RT2661_TX_RING_CSR0 0x3418 |
101 | #define RT2661_TX_RING_CSR1 0x341c |
102 | #define RT2661_AIFSN_CSR 0x3420 |
103 | #define RT2661_CWMIN_CSR 0x3424 |
104 | #define RT2661_CWMAX_CSR 0x3428 |
105 | #define RT2661_TX_DMA_DST_CSR 0x342c |
106 | #define RT2661_TX_CNTL_CSR 0x3430 |
107 | #define RT2661_LOAD_TX_RING_CSR 0x3434 |
108 | #define RT2661_RX_BASE_CSR 0x3450 |
109 | #define RT2661_RX_RING_CSR 0x3454 |
110 | #define RT2661_RX_CNTL_CSR 0x3458 |
111 | #define RT2661_PCI_CFG_CSR 0x3460 |
112 | #define RT2661_INT_SOURCE_CSR 0x3468 |
113 | #define RT2661_INT_MASK_CSR 0x346c |
114 | #define RT2661_E2PROM_CSR 0x3470 |
115 | #define RT2661_AC_TXOP_CSR0 0x3474 |
116 | #define RT2661_AC_TXOP_CSR1 0x3478 |
117 | #define RT2661_TEST_MODE_CSR 0x3484 |
118 | #define RT2661_IO_CNTL_CSR 0x3498 |
119 | #define RT2661_MCU_CODE_BASE 0x4000 |
120 | |
121 | |
122 | /* possible flags for register HOST_CMD_CSR */ |
123 | #define RT2661_KICK_CMD (1 << 7) |
124 | /* Host to MCU (8051) command identifiers */ |
125 | #define RT2661_MCU_CMD_SLEEP 0x30 |
126 | #define RT2661_MCU_CMD_WAKEUP 0x31 |
127 | #define RT2661_MCU_SET_LED 0x50 |
128 | #define 0x52 |
129 | |
130 | /* possible flags for register MCU_CNTL_CSR */ |
131 | #define RT2661_MCU_SEL (1 << 0) |
132 | #define RT2661_MCU_RESET (1 << 1) |
133 | #define RT2661_MCU_READY (1 << 2) |
134 | |
135 | /* possible flags for register MCU_INT_SOURCE_CSR */ |
136 | #define RT2661_MCU_CMD_DONE 0xff |
137 | #define RT2661_MCU_WAKEUP (1 << 8) |
138 | #define RT2661_MCU_BEACON_EXPIRE (1 << 9) |
139 | #define RT2661_MCU_INT_ALL (RT2661_MCU_CMD_DONE | \ |
140 | RT2661_MCU_WAKEUP | \ |
141 | RT2661_MCU_BEACON_EXPIRE) |
142 | |
143 | /* possible flags for register H2M_MAILBOX_CSR */ |
144 | #define RT2661_H2M_BUSY (1 << 24) |
145 | #define RT2661_TOKEN_NO_INTR 0xff |
146 | |
147 | /* possible flags for register MAC_CSR5 */ |
148 | #define RT2661_ONE_BSSID 3 |
149 | |
150 | /* possible flags for register TXRX_CSR0 */ |
151 | /* Tx filter flags are in the low 16 bits */ |
152 | #define RT2661_AUTO_TX_SEQ (1 << 15) |
153 | /* Rx filter flags are in the high 16 bits */ |
154 | #define RT2661_DISABLE_RX (1 << 16) |
155 | #define RT2661_DROP_CRC_ERROR (1 << 17) |
156 | #define RT2661_DROP_PHY_ERROR (1 << 18) |
157 | #define RT2661_DROP_CTL (1 << 19) |
158 | #define RT2661_DROP_NOT_TO_ME (1 << 20) |
159 | #define RT2661_DROP_TODS (1 << 21) |
160 | #define RT2661_DROP_VER_ERROR (1 << 22) |
161 | #define RT2661_DROP_MULTICAST (1 << 23) |
162 | #define RT2661_DROP_BROADCAST (1 << 24) |
163 | #define RT2661_DROP_ACKCTS (1 << 25) |
164 | |
165 | /* possible flags for register TXRX_CSR4 */ |
166 | #define RT2661_SHORT_PREAMBLE (1 << 18) |
167 | #define RT2661_MRR_ENABLED (1 << 19) |
168 | #define RT2661_MRR_CCK_FALLBACK (1 << 22) |
169 | |
170 | /* possible flags for register TXRX_CSR9 */ |
171 | #define RT2661_TSF_TICKING (1 << 16) |
172 | #define RT2661_TSF_MODE(x) (((x) & 0x3) << 17) |
173 | /* TBTT stands for Target Beacon Transmission Time */ |
174 | #define RT2661_ENABLE_TBTT (1 << 19) |
175 | #define RT2661_GENERATE_BEACON (1 << 20) |
176 | |
177 | /* possible flags for register PHY_CSR0 */ |
178 | #define RT2661_PA_PE_2GHZ (1 << 16) |
179 | #define RT2661_PA_PE_5GHZ (1 << 17) |
180 | |
181 | /* possible flags for register PHY_CSR3 */ |
182 | #define RT2661_BBP_READ (1 << 15) |
183 | #define RT2661_BBP_BUSY (1 << 16) |
184 | |
185 | /* possible flags for register PHY_CSR4 */ |
186 | #define RT2661_RF_21BIT (21 << 24) |
187 | #define RT2661_RF_BUSY (1 << 31) |
188 | |
189 | /* possible values for register STA_CSR4 */ |
190 | #define RT2661_TX_STAT_VALID (1 << 0) |
191 | #define RT2661_TX_RESULT(v) (((v) >> 1) & 0x7) |
192 | #define RT2661_TX_RETRYCNT(v) (((v) >> 4) & 0xf) |
193 | #define RT2661_TX_QID(v) (((v) >> 8) & 0xf) |
194 | #define RT2661_TX_SUCCESS 0 |
195 | #define RT2661_TX_RETRY_FAIL 6 |
196 | |
197 | /* possible flags for register TX_CNTL_CSR */ |
198 | #define RT2661_KICK_MGT (1 << 4) |
199 | |
200 | /* possible flags for register INT_SOURCE_CSR */ |
201 | #define RT2661_TX_DONE (1 << 0) |
202 | #define RT2661_RX_DONE (1 << 1) |
203 | #define RT2661_TX0_DMA_DONE (1 << 16) |
204 | #define RT2661_TX1_DMA_DONE (1 << 17) |
205 | #define RT2661_TX2_DMA_DONE (1 << 18) |
206 | #define RT2661_TX3_DMA_DONE (1 << 19) |
207 | #define RT2661_MGT_DONE (1 << 20) |
208 | #define RT2661_INT_CSR_ALL (RT2661_TX_DONE | RT2661_RX_DONE | \ |
209 | RT2661_TX0_DMA_DONE | RT2661_TX1_DMA_DONE | \ |
210 | RT2661_TX2_DMA_DONE | RT2661_TX3_DMA_DONE | \ |
211 | RT2661_MGT_DONE | RT2661_MGT_DONE) |
212 | |
213 | /* possible flags for register E2PROM_CSR */ |
214 | #define RT2661_C (1 << 1) |
215 | #define RT2661_S (1 << 2) |
216 | #define RT2661_D (1 << 3) |
217 | #define RT2661_Q (1 << 4) |
218 | #define RT2661_93C46 (1 << 5) |
219 | |
220 | /* Tx descriptor */ |
221 | struct rt2661_tx_desc { |
222 | uint32_t flags; |
223 | #define RT2661_TX_BUSY (1 << 0) |
224 | #define RT2661_TX_VALID (1 << 1) |
225 | #define RT2661_TX_MORE_FRAG (1 << 2) |
226 | #define RT2661_TX_NEED_ACK (1 << 3) |
227 | #define RT2661_TX_TIMESTAMP (1 << 4) |
228 | #define RT2661_TX_OFDM (1 << 5) |
229 | #define RT2661_TX_IFS_SIFS (1 << 6) |
230 | #define RT2661_TX_LONG_RETRY (1 << 7) |
231 | #define RT2661_TX_BURST (1 << 28) |
232 | |
233 | uint16_t wme; |
234 | #define RT2661_QID(v) (v) |
235 | #define RT2661_AIFSN(v) ((v) << 4) |
236 | #define RT2661_LOGCWMIN(v) ((v) << 8) |
237 | #define RT2661_LOGCWMAX(v) ((v) << 12) |
238 | |
239 | uint16_t xflags; |
240 | #define RT2661_TX_HWSEQ (1 << 12) |
241 | |
242 | uint8_t plcp_signal; |
243 | uint8_t plcp_service; |
244 | #define RT2661_PLCP_LENGEXT 0x80 |
245 | |
246 | uint8_t plcp_length_lo; |
247 | uint8_t plcp_length_hi; |
248 | |
249 | uint32_t iv; |
250 | uint32_t eiv; |
251 | |
252 | uint8_t offset; |
253 | uint8_t qid; |
254 | #define RT2661_QID_MGT 13 |
255 | |
256 | uint8_t txpower; |
257 | #define RT2661_DEFAULT_TXPOWER 0 |
258 | |
259 | uint8_t reserved1; |
260 | |
261 | uint32_t addr[RT2661_MAX_SCATTER]; |
262 | uint16_t len[RT2661_MAX_SCATTER]; |
263 | |
264 | uint16_t reserved2; |
265 | } __packed; |
266 | |
267 | /* Rx descriptor */ |
268 | struct rt2661_rx_desc { |
269 | uint32_t flags; |
270 | #define RT2661_RX_BUSY (1 << 0) |
271 | #define RT2661_RX_DROP (1 << 1) |
272 | #define RT2661_RX_CRC_ERROR (1 << 6) |
273 | #define RT2661_RX_OFDM (1 << 7) |
274 | #define RT2661_RX_PHY_ERROR (1 << 8) |
275 | #define RT2661_RX_CIPHER_MASK 0x00000600 |
276 | |
277 | uint8_t rate; |
278 | uint8_t ; |
279 | uint8_t reserved1; |
280 | uint8_t offset; |
281 | uint32_t iv; |
282 | uint32_t eiv; |
283 | uint32_t reserved2; |
284 | uint32_t physaddr; |
285 | uint32_t reserved3[10]; |
286 | } __packed; |
287 | |
288 | #define RAL_RF1 0 |
289 | #define RAL_RF2 2 |
290 | #define RAL_RF3 1 |
291 | #define RAL_RF4 3 |
292 | |
293 | /* dual-band RF */ |
294 | #define RT2661_RF_5225 1 |
295 | #define RT2661_RF_5325 2 |
296 | /* single-band RF */ |
297 | #define RT2661_RF_2527 3 |
298 | #define RT2661_RF_2529 4 |
299 | |
300 | #define RT2661_RX_DESC_BACK 4 |
301 | |
302 | #define RT2661_SMART_MODE (1 << 0) |
303 | |
304 | #define RT2661_BBPR94_DEFAULT 6 |
305 | |
306 | #define RT2661_SHIFT_D 3 |
307 | #define RT2661_SHIFT_Q 4 |
308 | |
309 | #define RT2661_EEPROM_MAC01 0x02 |
310 | #define RT2661_EEPROM_MAC23 0x03 |
311 | #define RT2661_EEPROM_MAC45 0x04 |
312 | #define RT2661_EEPROM_ANTENNA 0x10 |
313 | #define RT2661_EEPROM_CONFIG2 0x11 |
314 | #define RT2661_EEPROM_BBP_BASE 0x13 |
315 | #define RT2661_EEPROM_TXPOWER 0x23 |
316 | #define RT2661_EEPROM_FREQ_OFFSET 0x2f |
317 | #define 0x4d |
318 | #define 0x4e |
319 | |
320 | #define RT2661_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ |
321 | |
322 | /* |
323 | * control and status registers access macros |
324 | */ |
325 | #define RAL_READ(sc, reg) \ |
326 | bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) |
327 | |
328 | #define RAL_READ_REGION_4(sc, offset, datap, count) \ |
329 | bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ |
330 | (datap), (count)) |
331 | |
332 | #define RAL_WRITE(sc, reg, val) \ |
333 | bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) |
334 | |
335 | #define RAL_WRITE_1(sc, reg, val) \ |
336 | bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) |
337 | |
338 | #define RAL_RW_BARRIER_1(sc, reg) \ |
339 | bus_space_barrier((sc)->sc_st, (sc)->sc_sh, (reg), 1, \ |
340 | BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) |
341 | |
342 | #define RAL_WRITE_REGION_1(sc, offset, datap, count) \ |
343 | bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ |
344 | (datap), (count)) |
345 | |
346 | /* |
347 | * EEPROM access macro |
348 | */ |
349 | #define RT2661_EEPROM_CTL(sc, val) do { \ |
350 | RAL_WRITE((sc), RT2661_E2PROM_CSR, (val)); \ |
351 | DELAY(RT2661_EEPROM_DELAY); \ |
352 | } while (/* CONSTCOND */0) |
353 | |
354 | /* |
355 | * Default values for MAC registers; values taken from the reference driver. |
356 | */ |
357 | #define RT2661_DEF_MAC \ |
358 | { RT2661_TXRX_CSR0, 0x0000b032 }, \ |
359 | { RT2661_TXRX_CSR1, 0x9eb39eb3 }, \ |
360 | { RT2661_TXRX_CSR2, 0x8a8b8c8d }, \ |
361 | { RT2661_TXRX_CSR3, 0x00858687 }, \ |
362 | { RT2661_TXRX_CSR7, 0x2e31353b }, \ |
363 | { RT2661_TXRX_CSR8, 0x2a2a2a2c }, \ |
364 | { RT2661_TXRX_CSR15, 0x0000000f }, \ |
365 | { RT2661_MAC_CSR6, 0x00000fff }, \ |
366 | { RT2661_MAC_CSR8, 0x016c030a }, \ |
367 | { RT2661_MAC_CSR10, 0x00000718 }, \ |
368 | { RT2661_MAC_CSR12, 0x00000004 }, \ |
369 | { RT2661_MAC_CSR13, 0x0000e000 }, \ |
370 | { RT2661_SEC_CSR0, 0x00000000 }, \ |
371 | { RT2661_SEC_CSR1, 0x00000000 }, \ |
372 | { RT2661_SEC_CSR5, 0x00000000 }, \ |
373 | { RT2661_PHY_CSR1, 0x000023b0 }, \ |
374 | { RT2661_PHY_CSR5, 0x060a100c }, \ |
375 | { RT2661_PHY_CSR6, 0x00080606 }, \ |
376 | { RT2661_PHY_CSR7, 0x00000a08 }, \ |
377 | { RT2661_PCI_CFG_CSR, 0x3cca4808 }, \ |
378 | { RT2661_AIFSN_CSR, 0x00002273 }, \ |
379 | { RT2661_CWMIN_CSR, 0x00002344 }, \ |
380 | { RT2661_CWMAX_CSR, 0x000034aa }, \ |
381 | { RT2661_TEST_MODE_CSR, 0x00000200 }, \ |
382 | { RT2661_M2H_CMD_DONE_CSR, 0xffffffff } |
383 | |
384 | /* |
385 | * Default values for BBP registers; values taken from the reference driver. |
386 | */ |
387 | #define RT2661_DEF_BBP \ |
388 | { 3, 0x00 }, \ |
389 | { 15, 0x30 }, \ |
390 | { 17, 0x20 }, \ |
391 | { 21, 0xc8 }, \ |
392 | { 22, 0x38 }, \ |
393 | { 23, 0x06 }, \ |
394 | { 24, 0xfe }, \ |
395 | { 25, 0x0a }, \ |
396 | { 26, 0x0d }, \ |
397 | { 34, 0x12 }, \ |
398 | { 37, 0x07 }, \ |
399 | { 39, 0xf8 }, \ |
400 | { 41, 0x60 }, \ |
401 | { 53, 0x10 }, \ |
402 | { 54, 0x18 }, \ |
403 | { 60, 0x10 }, \ |
404 | { 61, 0x04 }, \ |
405 | { 62, 0x04 }, \ |
406 | { 75, 0xfe }, \ |
407 | { 86, 0xfe }, \ |
408 | { 88, 0xfe }, \ |
409 | { 90, 0x0f }, \ |
410 | { 99, 0x00 }, \ |
411 | { 102, 0x16 }, \ |
412 | { 107, 0x04 } |
413 | |
414 | /* |
415 | * Default settings for RF registers; values taken from the reference driver. |
416 | */ |
417 | #define RT2661_RF5225_1 \ |
418 | { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ |
419 | { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ |
420 | { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ |
421 | { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ |
422 | { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ |
423 | { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ |
424 | { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ |
425 | { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ |
426 | { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ |
427 | { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ |
428 | { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ |
429 | { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ |
430 | { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ |
431 | { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ |
432 | \ |
433 | { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, \ |
434 | { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, \ |
435 | { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, \ |
436 | { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, \ |
437 | { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, \ |
438 | { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, \ |
439 | { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, \ |
440 | { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, \ |
441 | \ |
442 | { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, \ |
443 | { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, \ |
444 | { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, \ |
445 | { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, \ |
446 | { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, \ |
447 | { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, \ |
448 | { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, \ |
449 | { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, \ |
450 | { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, \ |
451 | { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, \ |
452 | { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, \ |
453 | \ |
454 | { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, \ |
455 | { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, \ |
456 | { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, \ |
457 | { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, \ |
458 | { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 } |
459 | |
460 | #define RT2661_RF5225_2 \ |
461 | { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ |
462 | { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ |
463 | { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ |
464 | { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ |
465 | { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ |
466 | { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ |
467 | { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ |
468 | { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ |
469 | { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ |
470 | { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ |
471 | { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ |
472 | { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ |
473 | { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ |
474 | { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ |
475 | \ |
476 | { 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, \ |
477 | { 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, \ |
478 | { 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, \ |
479 | { 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, \ |
480 | { 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, \ |
481 | { 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, \ |
482 | { 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, \ |
483 | { 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, \ |
484 | \ |
485 | { 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, \ |
486 | { 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, \ |
487 | { 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, \ |
488 | { 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, \ |
489 | { 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, \ |
490 | { 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, \ |
491 | { 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, \ |
492 | { 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, \ |
493 | { 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, \ |
494 | { 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, \ |
495 | { 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, \ |
496 | \ |
497 | { 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, \ |
498 | { 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, \ |
499 | { 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, \ |
500 | { 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, \ |
501 | { 165, 0x00b35, 0x11246, 0x2e014, 0x30285 } |
502 | |