1 | /* $NetBSD: nouveau_subdev_timer_nv04.c,v 1.2 2015/02/25 22:12:00 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_timer_nv04.c,v 1.2 2015/02/25 22:12:00 riastradh Exp $" ); |
29 | |
30 | #include "nv04.h" |
31 | |
32 | static u64 |
33 | nv04_timer_read(struct nouveau_timer *ptimer) |
34 | { |
35 | struct nv04_timer_priv *priv = (void *)ptimer; |
36 | u32 hi, lo; |
37 | |
38 | do { |
39 | hi = nv_rd32(priv, NV04_PTIMER_TIME_1); |
40 | lo = nv_rd32(priv, NV04_PTIMER_TIME_0); |
41 | } while (hi != nv_rd32(priv, NV04_PTIMER_TIME_1)); |
42 | |
43 | return ((u64)hi << 32 | lo); |
44 | } |
45 | |
46 | static void |
47 | nv04_timer_alarm_trigger(struct nouveau_timer *ptimer) |
48 | { |
49 | struct nv04_timer_priv *priv = (void *)ptimer; |
50 | struct nouveau_alarm *alarm, *atemp; |
51 | unsigned long flags; |
52 | struct list_head exec = LIST_HEAD_INIT(exec); |
53 | |
54 | /* move any due alarms off the pending list */ |
55 | spin_lock_irqsave(&priv->lock, flags); |
56 | list_for_each_entry_safe(alarm, atemp, &priv->alarms, head) { |
57 | if (alarm->timestamp <= ptimer->read(ptimer)) |
58 | list_move_tail(&alarm->head, &exec); |
59 | } |
60 | |
61 | /* reschedule interrupt for next alarm time */ |
62 | if (!list_empty(&priv->alarms)) { |
63 | alarm = list_first_entry(&priv->alarms, typeof(*alarm), head); |
64 | nv_wr32(priv, NV04_PTIMER_ALARM_0, alarm->timestamp); |
65 | nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000001); |
66 | } else { |
67 | nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); |
68 | } |
69 | spin_unlock_irqrestore(&priv->lock, flags); |
70 | |
71 | /* execute any pending alarm handlers */ |
72 | list_for_each_entry_safe(alarm, atemp, &exec, head) { |
73 | list_del_init(&alarm->head); |
74 | alarm->func(alarm); |
75 | } |
76 | } |
77 | |
78 | static void |
79 | nv04_timer_alarm(struct nouveau_timer *ptimer, u64 time, |
80 | struct nouveau_alarm *alarm) |
81 | { |
82 | struct nv04_timer_priv *priv = (void *)ptimer; |
83 | struct nouveau_alarm *list; |
84 | unsigned long flags; |
85 | |
86 | alarm->timestamp = ptimer->read(ptimer) + time; |
87 | |
88 | /* append new alarm to list, in soonest-alarm-first order */ |
89 | spin_lock_irqsave(&priv->lock, flags); |
90 | if (!time) { |
91 | if (!list_empty(&alarm->head)) |
92 | list_del(&alarm->head); |
93 | } else { |
94 | list_for_each_entry(list, &priv->alarms, head) { |
95 | if (list->timestamp > alarm->timestamp) |
96 | break; |
97 | } |
98 | list_add_tail(&alarm->head, &list->head); |
99 | } |
100 | spin_unlock_irqrestore(&priv->lock, flags); |
101 | |
102 | /* process pending alarms */ |
103 | nv04_timer_alarm_trigger(ptimer); |
104 | } |
105 | |
106 | static void |
107 | nv04_timer_alarm_cancel(struct nouveau_timer *ptimer, |
108 | struct nouveau_alarm *alarm) |
109 | { |
110 | struct nv04_timer_priv *priv = (void *)ptimer; |
111 | unsigned long flags; |
112 | spin_lock_irqsave(&priv->lock, flags); |
113 | list_del_init(&alarm->head); |
114 | spin_unlock_irqrestore(&priv->lock, flags); |
115 | } |
116 | |
117 | static void |
118 | nv04_timer_intr(struct nouveau_subdev *subdev) |
119 | { |
120 | struct nv04_timer_priv *priv = (void *)subdev; |
121 | u32 stat = nv_rd32(priv, NV04_PTIMER_INTR_0); |
122 | |
123 | if (stat & 0x00000001) { |
124 | nv04_timer_alarm_trigger(&priv->base); |
125 | nv_wr32(priv, NV04_PTIMER_INTR_0, 0x00000001); |
126 | stat &= ~0x00000001; |
127 | } |
128 | |
129 | if (stat) { |
130 | nv_error(priv, "unknown stat 0x%08x\n" , stat); |
131 | nv_wr32(priv, NV04_PTIMER_INTR_0, stat); |
132 | } |
133 | } |
134 | |
135 | int |
136 | nv04_timer_fini(struct nouveau_object *object, bool suspend) |
137 | { |
138 | struct nv04_timer_priv *priv = (void *)object; |
139 | if (suspend) |
140 | priv->suspend_time = nv04_timer_read(&priv->base); |
141 | nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); |
142 | return nouveau_timer_fini(&priv->base, suspend); |
143 | } |
144 | |
145 | static int |
146 | nv04_timer_init(struct nouveau_object *object) |
147 | { |
148 | struct nouveau_device *device = nv_device(object); |
149 | struct nv04_timer_priv *priv = (void *)object; |
150 | u32 m = 1, f, n, d, lo, hi; |
151 | int ret; |
152 | |
153 | ret = nouveau_timer_init(&priv->base); |
154 | if (ret) |
155 | return ret; |
156 | |
157 | /* aim for 31.25MHz, which gives us nanosecond timestamps */ |
158 | d = 1000000 / 32; |
159 | |
160 | /* determine base clock for timer source */ |
161 | #if 0 /*XXX*/ |
162 | if (device->chipset < 0x40) { |
163 | n = nouveau_hw_get_clock(device, PLL_CORE); |
164 | } else |
165 | #endif |
166 | if (device->chipset <= 0x40) { |
167 | /*XXX: figure this out */ |
168 | f = -1; |
169 | n = 0; |
170 | } else { |
171 | f = device->crystal; |
172 | n = f; |
173 | while (n < (d * 2)) { |
174 | n += (n / m); |
175 | m++; |
176 | } |
177 | |
178 | nv_wr32(priv, 0x009220, m - 1); |
179 | } |
180 | |
181 | if (!n) { |
182 | nv_warn(priv, "unknown input clock freq\n" ); |
183 | if (!nv_rd32(priv, NV04_PTIMER_NUMERATOR) || |
184 | !nv_rd32(priv, NV04_PTIMER_DENOMINATOR)) { |
185 | nv_wr32(priv, NV04_PTIMER_NUMERATOR, 1); |
186 | nv_wr32(priv, NV04_PTIMER_DENOMINATOR, 1); |
187 | } |
188 | return 0; |
189 | } |
190 | |
191 | /* reduce ratio to acceptable values */ |
192 | while (((n % 5) == 0) && ((d % 5) == 0)) { |
193 | n /= 5; |
194 | d /= 5; |
195 | } |
196 | |
197 | while (((n % 2) == 0) && ((d % 2) == 0)) { |
198 | n /= 2; |
199 | d /= 2; |
200 | } |
201 | |
202 | while (n > 0xffff || d > 0xffff) { |
203 | n >>= 1; |
204 | d >>= 1; |
205 | } |
206 | |
207 | /* restore the time before suspend */ |
208 | lo = priv->suspend_time; |
209 | hi = (priv->suspend_time >> 32); |
210 | |
211 | nv_debug(priv, "input frequency : %dHz\n" , f); |
212 | nv_debug(priv, "input multiplier: %d\n" , m); |
213 | nv_debug(priv, "numerator : 0x%08x\n" , n); |
214 | nv_debug(priv, "denominator : 0x%08x\n" , d); |
215 | nv_debug(priv, "timer frequency : %dHz\n" , (f * m) * d / n); |
216 | nv_debug(priv, "time low : 0x%08x\n" , lo); |
217 | nv_debug(priv, "time high : 0x%08x\n" , hi); |
218 | |
219 | nv_wr32(priv, NV04_PTIMER_NUMERATOR, n); |
220 | nv_wr32(priv, NV04_PTIMER_DENOMINATOR, d); |
221 | nv_wr32(priv, NV04_PTIMER_INTR_0, 0xffffffff); |
222 | nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); |
223 | nv_wr32(priv, NV04_PTIMER_TIME_1, hi); |
224 | nv_wr32(priv, NV04_PTIMER_TIME_0, lo); |
225 | |
226 | return 0; |
227 | } |
228 | |
229 | void |
230 | nv04_timer_dtor(struct nouveau_object *object) |
231 | { |
232 | struct nv04_timer_priv *priv = (void *)object; |
233 | return nouveau_timer_destroy(&priv->base); |
234 | } |
235 | |
236 | int |
237 | nv04_timer_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
238 | struct nouveau_oclass *oclass, void *data, u32 size, |
239 | struct nouveau_object **pobject) |
240 | { |
241 | struct nv04_timer_priv *priv; |
242 | int ret; |
243 | |
244 | ret = nouveau_timer_create(parent, engine, oclass, &priv); |
245 | *pobject = nv_object(priv); |
246 | if (ret) |
247 | return ret; |
248 | |
249 | priv->base.base.intr = nv04_timer_intr; |
250 | priv->base.read = nv04_timer_read; |
251 | priv->base.alarm = nv04_timer_alarm; |
252 | priv->base.alarm_cancel = nv04_timer_alarm_cancel; |
253 | priv->suspend_time = 0; |
254 | |
255 | INIT_LIST_HEAD(&priv->alarms); |
256 | spin_lock_init(&priv->lock); |
257 | return 0; |
258 | } |
259 | |
260 | struct nouveau_oclass |
261 | nv04_timer_oclass = { |
262 | .handle = NV_SUBDEV(TIMER, 0x04), |
263 | .ofuncs = &(struct nouveau_ofuncs) { |
264 | .ctor = nv04_timer_ctor, |
265 | .dtor = nv04_timer_dtor, |
266 | .init = nv04_timer_init, |
267 | .fini = nv04_timer_fini, |
268 | } |
269 | }; |
270 | |