1 | /* $NetBSD: sqphyreg.h,v 1.5 2008/04/28 20:23:53 martin Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 1998 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, |
9 | * NASA Ames Research Center. |
10 | * |
11 | * Redistribution and use in source and binary forms, with or without |
12 | * modification, are permitted provided that the following conditions |
13 | * are met: |
14 | * 1. Redistributions of source code must retain the above copyright |
15 | * notice, this list of conditions and the following disclaimer. |
16 | * 2. Redistributions in binary form must reproduce the above copyright |
17 | * notice, this list of conditions and the following disclaimer in the |
18 | * documentation and/or other materials provided with the distribution. |
19 | * |
20 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
21 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
22 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
23 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
24 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
30 | * POSSIBILITY OF SUCH DAMAGE. |
31 | */ |
32 | |
33 | #ifndef _DEV_MII_SQPHYREG_H_ |
34 | #define _DEV_MII_SQPHYREG_H_ |
35 | |
36 | /* |
37 | * Seeq 80220 registers. This also covers the Seeq 80225, which is |
38 | * a stripped-down-for-lower-power-consumption version of the 80223. |
39 | * It only has a STATUS register, and only the SPD_DET and DPLX_DET |
40 | * bits are valid. |
41 | */ |
42 | |
43 | #define MII_SQPHY_CONFIG1 0x10 /* Configuration 1 Register */ |
44 | #define CONFIG1_LNK_DIS 0x8000 /* Link Detect Disable */ |
45 | #define CONFIG1_XMT_DIS 0x4000 /* TP Transmitter Disable */ |
46 | #define CONFIG1_XMT_PDN 0x2000 /* TP Transmitter Powerdown */ |
47 | #define CONFIG1_TXEN_CRS 0x1000 /* TX_EN to CRS Loopback Disable */ |
48 | #define CONFIG1_BYP_ENC 0x0800 /* Bypass Encoder */ |
49 | #define CONFIG1_BYP_SCR 0x0400 /* Bypass Scrambler */ |
50 | #define CONFIG1_UNSCR_DIS 0x0200 /* Unscr. Idle Reception Disable */ |
51 | #define CONFIG1_EQLZR 0x0100 /* Rx Equalizer Disable */ |
52 | #define CONFIG1_CABLE 0x0080 /* Cable: 1 = STP, 0 = UTP */ |
53 | #define CONFIG1_RLVL0 0x0040 /* Receive Level Adjust */ |
54 | #define CONFIG1_TLVL3 0x0020 /* Transmit output level adjust */ |
55 | #define CONFIG1_TLVL2 0x0010 |
56 | #define CONFIG1_TLVL1 0x0008 |
57 | #define CONFIG1_TLVL0 0x0004 |
58 | #define CONFIG1_TRF1 0x0002 /* Transmitter Rise/Fall Adjust */ |
59 | #define CONFIG1_TRF0 0x0001 |
60 | |
61 | #define MII_SQPHY_CONFIG2 0x11 /* Configuration 2 Register */ |
62 | #define CONFIG2_PLED3_1 0x8000 /* PLED3 configuration */ |
63 | #define CONFIG2_PLED3_0 0x4000 |
64 | /* 1 1 LINK100 (default) */ |
65 | /* 1 0 Blink */ |
66 | /* 0 1 On */ |
67 | /* 0 0 Off */ |
68 | #define CONFIG2_PLED2_1 0x2000 /* PLED2 configuration */ |
69 | #define CONFIG2_PLED2_0 0x1000 |
70 | /* 1 1 Activity (default) */ |
71 | /* 1 0 Blink */ |
72 | /* 0 1 On */ |
73 | /* 0 0 Off */ |
74 | #define CONFIG2_PLED1_1 0x0800 /* PLED1 configuration */ |
75 | #define CONFIG2_PLED1_0 0x0400 |
76 | /* 1 1 Full duplex (default) */ |
77 | /* 1 0 Blink */ |
78 | /* 0 1 On */ |
79 | /* 0 0 Off */ |
80 | #define CONFIG2_PLED0_1 0x0200 /* PLED0 configuration */ |
81 | #define CONFIG2_PLED0_0 0x0100 |
82 | /* 1 1 LINK10 (default) */ |
83 | /* 1 0 Blink */ |
84 | /* 0 1 On */ |
85 | /* 0 0 Off */ |
86 | #define CONFIG2_LED_DEF1 0x0080 /* LED Normal Function Select */ |
87 | #define CONFIG2_LED_DEF0 0x0040 |
88 | #define CONFIG2_APOL_DIS 0x0020 /* Auto Polarity Correct Disable */ |
89 | #define CONFIG2_JAB_DIS 0x0010 /* Jabber Disable */ |
90 | #define CONFIG2_MREG 0x0008 /* Multiple Register Access Enable */ |
91 | #define CONFIG2_INT_MDIO 0x0004 /* MDIO Interrupt when idle */ |
92 | #define CONFIG2_RJ_CFG 0x0002 /* R/J Configuration Select */ |
93 | |
94 | #define MII_SQPHY_STATUS 0x12 /* Status Output Register */ |
95 | #define STATUS_INT 0x8000 /* Interrupt Detect */ |
96 | #define STATUS_LNK_FAIL 0x4000 /* Link Fail */ |
97 | #define STATUS_LOSS_SYNC 0x2000 /* Descrambler lost synchronization */ |
98 | #define STATUS_CWRD 0x1000 /* Codeword Error */ |
99 | #define STATUS_SSD 0x0800 /* Start of Stream Error */ |
100 | #define STATUS_ESD 0x0400 /* End of Stream Error */ |
101 | #define STATUS_RPOL 0x0200 /* Reverse Polarity Detected */ |
102 | #define STATUS_JAB 0x0100 /* Jabber Detected */ |
103 | #define STATUS_SPD_DET 0x0080 /* 100Mbps */ |
104 | #define STATUS_DPLX_DET 0x0040 /* Full Duplex */ |
105 | |
106 | #define MII_SQPHY_MASK 0x13 /* Mask Register */ |
107 | #define MASK_INT 0x8000 /* mask INT */ |
108 | #define MASK_LNK_FAIL 0x4000 /* mask LNK_FAIL */ |
109 | #define MASK_LOSS_SYNC 0x2000 /* mask LOSS_SYNC */ |
110 | #define MASK_CWRD 0x1000 /* mask CWRD */ |
111 | #define MASK_SSD 0x0800 /* mask SSD */ |
112 | #define MASK_ESD 0x0400 /* mask ESD */ |
113 | #define MASK_RPOL 0x0200 /* mask RPOL */ |
114 | #define MASK_JAB 0x0100 /* mask JAB */ |
115 | #define MASK_SPD_DET 0x0080 /* mask SPD_DET */ |
116 | #define MASK_DPLX_DET 0x0040 /* mask DPLX_DET */ |
117 | #define MASK_ANEG_STS1 0x0020 /* mask ANEG_STS1 */ |
118 | #define MASK_ANEG_STS0 0x0010 /* mask ANEG_STS0 */ |
119 | |
120 | #define MII_SQPHY_RESERVED 0x14 /* Reserved Register */ |
121 | /* All bits must be 0 */ |
122 | |
123 | #endif /* _DEV_MII_SQPHYREG_H_ */ |
124 | |