1/* $NetBSD: sa2400reg.h,v 1.8 2009/10/19 23:19:39 rmind Exp $ */
2
3/*
4 * Copyright (c) 2005 David Young. All rights reserved.
5 *
6 * This code was written by David Young.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
18 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
20 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
21 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
28 * OF SUCH DAMAGE.
29 */
30
31#ifndef _DEV_IC_SA2400REG_H_
32#define _DEV_IC_SA2400REG_H_
33
34/*
35 * Serial bus format for Philips SA2400 Single-chip Transceiver.
36 */
37#define SA2400_TWI_DATA_MASK __BITS(31,8)
38#define SA2400_TWI_WREN __BIT(7) /* enable write */
39#define SA2400_TWI_ADDR_MASK __BITS(6,0)
40
41/*
42 * Registers for Philips SA2400 Single-chip Transceiver.
43 */
44#define SA2400_SYNA 0 /* Synthesizer Register A */
45#define SA2400_SYNA_FM __BIT(21) /* fractional modulus select,
46 * 0: /8 (default)
47 * 1: /5
48 */
49#define SA2400_SYNA_NF_MASK __BITS(20,18) /* fractional increment value,
50 * 0 to 7, default 4
51 */
52#define SA2400_SYNA_N_MASK __BITS(17,2) /* main divider division ratio,
53 * 512 to 65535, default 615
54 */
55
56#define SA2400_SYNB 1 /* Synthesizer Register B */
57#define SA2400_SYNB_R_MASK __BITS(21,12) /* reference divider ratio,
58 * 4 to 1023, default 11
59 */
60#define SA2400_SYNB_L_MASK __BITS(11,10) /* lock detect mode */
61#define SA2400_SYNB_L_INACTIVE0 __SHIFTIN(0, SA2400_SYNB_L_MASK)
62#define SA2400_SYNB_L_INACTIVE1 __SHIFTIN(1, SA2400_SYNB_L_MASK)
63#define SA2400_SYNB_L_NORMAL __SHIFTIN(2, SA2400_SYNB_L_MASK)
64#define SA2400_SYNB_L_INACTIVE2 __SHIFTIN(3, SA2400_SYNB_L_MASK)
65
66#define SA2400_SYNB_ON __BIT(9) /* power on/off,
67 * 0: inverted chip mode control
68 * 1: as defined by chip mode
69 * (see SA2400_OPMODE)
70 */
71#define SA2400_SYNB_ONE __BIT(8) /* always 1 */
72#define SA2400_SYNB_FC_MASK __BITS(7,0) /* fractional compensation
73 * charge pump current DAC,
74 * 0 to 255, default 80.
75 */
76
77#define SA2400_SYNC 2 /* Synthesizer Register C */
78#define SA2400_SYNC_CP_MASK __BITS(7,6) /* charge pump current
79 * setting
80 */
81#define SA2400_SYNC_CP_NORMAL_ __SHIFTIN(0, SA2400_SYNC_CP_MASK)
82#define SA2400_SYNC_CP_THIRD_ __SHIFTIN(1, SA2400_SYNC_CP_MASK)
83#define SA2400_SYNC_CP_NORMAL __SHIFTIN(2, SA2400_SYNC_CP_MASK) /* recommended */
84#define SA2400_SYNC_CP_THIRD __SHIFTIN(3, SA2400_SYNC_CP_MASK)
85
86#define SA2400_SYNC_SM_MASK __BITS(5,3) /* comparison divider select,
87 * 0 to 4, extra division
88 * ratio is 2**SM.
89 */
90#define SA2400_SYNC_ZERO __BIT(2) /* always 0 */
91
92#define SA2400_SYND 3 /* Synthesizer Register D */
93#define SA2400_SYND_ZERO1_MASK __BITS(21,17) /* always 0 */
94#define SA2400_SYND_TPHPSU __BIT(16) /* T[phpsu], 1: disable
95 * PHP speedup pump,
96 * overrides SA2400_SYND_TSPU
97 */
98#define SA2400_SYND_TPSU __BIT(15) /* T[spu], 1: speedup on,
99 * 0: speedup off
100 */
101#define SA2400_SYND_ZERO2_MASK __BITS(14,3) /* always 0 */
102
103#define SA2400_OPMODE 4 /* Operating mode, filter tuner,
104 * other controls
105 */
106/* 1: in Rx mode, RSSI-ADC always on 0: RSSI-ADC only on during AGC */
107#define SA2400_OPMODE_ADC __BIT(19)
108/* read-only filter tuner error: 1 if tuner out of range */
109#define SA2400_OPMODE_FTERR __BIT(18)
110/* Rx & Tx filter tuning, write tuning value (test mode only) or
111 * read tuner setting (in normal mode).
112 */
113#define SA2400_OPMODE_FILTTUNE_MASK __BITS(17,15)
114
115/* external reference voltage (pad v2p5) on */
116#define SA2400_OPMODE_V2P5 __BIT(14)
117/* external reference current ... */
118#define SA2400_OPMODE_I1M __BIT(13)
119/* external reference current ... */
120#define SA2400_OPMODE_I0P3 __BIT(12)
121#define SA2400_OPMODE_IN22 __BIT(10) /* xtal input frequency,
122 * 0: 44 MHz
123 * 1: 22 MHz
124 */
125#define SA2400_OPMODE_CLK __BIT(9) /* reference clock output on */
126#define SA2400_OPMODE_XO __BIT(8) /* xtal oscillator on */
127#define SA2400_OPMODE_DIGIN __BIT(7) /* use digital Tx inputs
128 * (FIRDAC)
129 */
130#define SA2400_OPMODE_RXLV __BIT(6) /* Rx output common mode
131 * voltage,
132 * 0: V[DD]/2
133 * 1: 1.25V
134 */
135#define SA2400_OPMODE_VEO __BIT(5) /* make internal vco
136 * available at vco pads
137 * (vcoextout)
138 */
139#define SA2400_OPMODE_VEI __BIT(4) /* use external vco input
140 * (vcoextin)
141 */
142/* main operating mode */
143#define SA2400_OPMODE_MODE_MASK __BITS(3,0)
144#define SA2400_OPMODE_MODE_SLEEP __SHIFTIN(0, SA2400_OPMODE_MODE_MASK)
145#define SA2400_OPMODE_MODE_TXRX __SHIFTIN(1, SA2400_OPMODE_MODE_MASK)
146#define SA2400_OPMODE_MODE_WAIT __SHIFTIN(2, SA2400_OPMODE_MODE_MASK)
147#define SA2400_OPMODE_MODE_RXMGC __SHIFTIN(3, SA2400_OPMODE_MODE_MASK)
148#define SA2400_OPMODE_MODE_FCALIB __SHIFTIN(4, SA2400_OPMODE_MODE_MASK)
149#define SA2400_OPMODE_MODE_DCALIB __SHIFTIN(5, SA2400_OPMODE_MODE_MASK)
150#define SA2400_OPMODE_MODE_FASTTXRXMGC __SHIFTIN(6, SA2400_OPMODE_MODE_MASK)
151#define SA2400_OPMODE_MODE_RESET __SHIFTIN(7, SA2400_OPMODE_MODE_MASK)
152#define SA2400_OPMODE_MODE_VCOCALIB __SHIFTIN(8, SA2400_OPMODE_MODE_MASK)
153
154#define SA2400_OPMODE_DEFAULTS \
155 (SA2400_OPMODE_XO | SA2400_OPMODE_RXLV | SA2400_OPMODE_CLK | \
156 SA2400_OPMODE_I0P3 | __SHIFTIN(3, SA2400_OPMODE_FILTTUNE_MASK))
157
158#define SA2400_AGC 5 /* AGC adjustment */
159#define SA2400_AGC_TARGETSIGN __BIT(23) /* fine-tune AGC target:
160 * -7dB to 7dB, sign bit ... */
161#define SA2400_AGC_TARGET_MASK __BITS(22,20) /* ... plus 0dB - 7dB */
162#define SA2400_AGC_MAXGAIN_MASK __BITS(19,15) /* maximum AGC gain, 0 to 31,
163 * (yields 54dB to 85dB)
164 */
165/* write: settling time after baseband gain switching, units of
166 * 182 nanoseconds.
167 * read: output of RSSI/Tx-peak detector's ADC in 5-bit Gray code.
168 */
169#define SA2400_AGC_BBPDELAY_MASK __BITS(14,10)
170#define SA2400_AGC_ADCVAL_MASK SA2400_AGC_BBPDELAY_MASK
171
172/* write: settling time after LNA gain switching, units of
173 * 182 nanoseconds
174 * read: 2nd sample of RSSI in AGC cycle
175 */
176#define SA2400_AGC_LNADELAY_MASK __BITS(9,5)
177#define SA2400_AGC_SAMPLE2_MASK SA2400_AGC_LNADELAY_MASK
178
179/* write: time between turning on Rx and AGCSET, units of
180 * 182 nanoseconds
181 * read: 1st sample of RSSI in AGC cycle
182 */
183#define SA2400_AGC_RXONDELAY_MASK __BITS(4,0)
184#define SA2400_AGC_SAMPLE1_MASK SA2400_AGC_RXONDELAY_MASK
185
186#define SA2400_MANRX 6 /* Manual receiver control settings */
187#define SA2400_MANRX_AHSN __BIT(23) /* 1: AGC w/ high S/N---switch
188 * LNA at step 52
189 * (recommended)
190 * 0: switch LNA at step 60
191 */
192
193/* If _RXOSQON, Q offset is
194 * (_RXOSQSIGN ? -1 : 1) * (1 + _RXOSQ_MASK) * 8 millivolts,
195 * otherwise, Q offset is 0.
196 *
197 * Ditto I offset.
198 */
199#define SA2400_MANRX_RXOSQON __BIT(22) /* Rx Q-channel correction. */
200#define SA2400_MANRX_RXOSQSIGN __BIT(21)
201#define SA2400_MANRX_RXOSQ_MASK __BITS(20,18)
202
203#define SA2400_MANRX_RXOSION __BIT(17) /* Rx I-channel correction. */
204#define SA2400_MANRX_RXOSISIGN __BIT(16)
205#define SA2400_MANRX_RXOSI_MASK __BITS(15,13)
206#define SA2400_MANRX_TEN __BIT(12) /* use 10MHz offset cancellation
207 * cornerpoint for brief period
208 * after each gain change
209 */
210
211/* DC offset cancellation cornerpoint select
212 * write: in RXMGC, set the cornerpoint
213 * read: in other modes, read AGC-controlled cornerpoint
214 */
215#define SA2400_MANRX_CORNERFREQ_MASK __BITS(11,10)
216
217/* write: in RXMGC mode, sets receiver gain
218 * read: in other modes, read AGC-controlled gain
219 */
220#define SA2400_MANRX_RXGAIN_MASK __BITS(9,0)
221
222#define SA2400_TX 7 /* Transmitter settings */
223/* Tx offsets
224 *
225 * write: in test mode, sets the offsets
226 * read: in normal mode, returns automatic settings
227 */
228#define SA2400_TX_TXOSQON __BIT(19)
229#define SA2400_TX_TXOSQSIGN __BIT(18)
230#define SA2400_TX_TXOSQ_MASK __BITS(17,15)
231#define SA2400_TX_TXOSION __BIT(14)
232#define SA2400_TX_TXOSISIGN __BIT(13)
233#define SA2400_TX_TXOSI_MASK __BITS(12,10)
234
235#define SA2400_TX_RAMP_MASK __BITS(9,8) /* Ramp-up delay,
236 * 0: 1us
237 * 1: 2us
238 * 2: 3us
239 * 3: 4us
240 * datasheet says, "ramp-up
241 * time always 1us". huh?
242 */
243#define SA2400_TX_HIGAIN_MASK __BITS(7,4) /* Transmitter gain settings
244 * for TXHI output
245 */
246#define SA2400_TX_LOGAIN_MASK __BITS(3,0) /* Transmitter gain settings
247 * for TXLO output
248 */
249
250#define SA2400_VCO 8 /* VCO settings */
251#define SA2400_VCO_ZERO __BITS(6,5) /* always zero */
252#define SA2400_VCO_VCERR __BIT(4)/* VCO calibration error flag---no
253 * band with low enough frequency
254 * could be found
255 */
256#define SA2400_VCO_VCOBAND_MASK __BITS(3,0) /* VCO band,
257 * write: in test mode, sets
258 * VCO band
259 * read: in normal mode,
260 * the result of
261 * calibration (VCOCAL).
262 * 0 = highest
263 * frequencies
264 */
265#endif /* _DEV_IC_SA2400REG_H_ */
266