1/* $NetBSD: isp_pci.c,v 1.119 2016/07/14 04:00:46 msaitoh Exp $ */
2/*
3 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration
4 * All rights reserved.
5 *
6 * Additional Copyright (C) 2000-2007 by Matthew Jacob
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/*
32 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
33 */
34
35/*
36 * 24XX 4Gb material support provided by MetrumRG Associates.
37 * Many thanks are due to them.
38 */
39
40#include <sys/cdefs.h>
41__KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.119 2016/07/14 04:00:46 msaitoh Exp $");
42
43#include <dev/ic/isp_netbsd.h>
44#include <dev/pci/pcireg.h>
45#include <dev/pci/pcivar.h>
46#include <dev/pci/pcidevs.h>
47#include <sys/reboot.h>
48
49static uint32_t isp_pci_rd_reg(struct ispsoftc *, int);
50static void isp_pci_wr_reg(struct ispsoftc *, int, uint32_t);
51#if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT))
52static uint32_t isp_pci_rd_reg_1080(struct ispsoftc *, int);
53static void isp_pci_wr_reg_1080(struct ispsoftc *, int, uint32_t);
54#endif
55#if !defined(ISP_DISABLE_2100_SUPPORT) && \
56 !defined(ISP_DISABLE_2200_SUPPORT) && \
57 !defined(ISP_DISABLE_1020_SUPPORT) && \
58 !defined(ISP_DISABLE_1080_SUPPORT) && \
59 !defined(ISP_DISABLE_12160_SUPPORT)
60static int
61isp_pci_rd_isr(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *);
62#endif
63#if !(defined(ISP_DISABLE_2300_SUPPORT) && defined(ISP_DISABLE_2322_SUPPORT))
64static int
65isp_pci_rd_isr_2300(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *);
66#endif
67#if !defined(ISP_DISABLE_2400_SUPPORT)
68static uint32_t isp_pci_rd_reg_2400(struct ispsoftc *, int);
69static void isp_pci_wr_reg_2400(struct ispsoftc *, int, uint32_t);
70static int
71isp_pci_rd_isr_2400(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *);
72#endif
73static int isp_pci_mbxdma(struct ispsoftc *);
74static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, void *);
75static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, uint32_t);
76static void isp_pci_reset0(struct ispsoftc *);
77static void isp_pci_reset1(struct ispsoftc *);
78static void isp_pci_dumpregs(struct ispsoftc *, const char *);
79static int isp_pci_intr(void *);
80
81#if defined(ISP_DISABLE_1020_SUPPORT) || defined(ISP_DISABLE_FW)
82#define ISP_1040_RISC_CODE NULL
83#else
84#define ISP_1040_RISC_CODE (const uint16_t *) isp_1040_risc_code
85#include <dev/microcode/isp/asm_1040.h>
86#endif
87
88#if defined(ISP_DISABLE_1080_SUPPORT) || defined(ISP_DISABLE_FW)
89#define ISP_1080_RISC_CODE NULL
90#else
91#define ISP_1080_RISC_CODE (const uint16_t *) isp_1080_risc_code
92#include <dev/microcode/isp/asm_1080.h>
93#endif
94
95#if defined(ISP_DISABLE_12160_SUPPORT) || defined(ISP_DISABLE_FW)
96#define ISP_12160_RISC_CODE NULL
97#else
98#define ISP_12160_RISC_CODE (const uint16_t *) isp_12160_risc_code
99#include <dev/microcode/isp/asm_12160.h>
100#endif
101
102#if defined(ISP_DISABLE_2100_SUPPORT) || defined(ISP_DISABLE_FW)
103#define ISP_2100_RISC_CODE NULL
104#else
105#define ISP_2100_RISC_CODE (const uint16_t *) isp_2100_risc_code
106#include <dev/microcode/isp/asm_2100.h>
107#endif
108
109#if defined(ISP_DISABLE_2200_SUPPORT) || defined(ISP_DISABLE_FW)
110#define ISP_2200_RISC_CODE NULL
111#else
112#define ISP_2200_RISC_CODE (const uint16_t *) isp_2200_risc_code
113#include <dev/microcode/isp/asm_2200.h>
114#endif
115
116#if defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_FW)
117#define ISP_2300_RISC_CODE NULL
118#else
119#define ISP_2300_RISC_CODE (const uint16_t *) isp_2300_risc_code
120#include <dev/microcode/isp/asm_2300.h>
121#endif
122#if defined(ISP_DISABLE_2322_SUPPORT) || defined(ISP_DISABLE_FW)
123#define ISP_2322_RISC_CODE NULL
124#else
125#define ISP_2322_RISC_CODE (const uint16_t *) isp_2322_risc_code
126#include <dev/microcode/isp/asm_2322.h>
127#endif
128
129#if defined(ISP_DISABLE_2400_SUPPORT) || defined(ISP_DISABLE_FW)
130#define ISP_2400_RISC_CODE NULL
131#define ISP_2500_RISC_CODE NULL
132#else
133#define ISP_2500
134#define ISP_2400
135#define ISP_2400_RISC_CODE (const uint32_t *) isp_2400_risc_code
136#define ISP_2500_RISC_CODE (const uint32_t *) isp_2500_risc_code
137#include <dev/microcode/isp/asm_2400.h>
138#include <dev/microcode/isp/asm_2500.h>
139#endif
140
141#ifndef ISP_DISABLE_1020_SUPPORT
142static struct ispmdvec mdvec = {
143 isp_pci_rd_isr,
144 isp_pci_rd_reg,
145 isp_pci_wr_reg,
146 isp_pci_mbxdma,
147 isp_pci_dmasetup,
148 isp_pci_dmateardown,
149 isp_pci_reset0,
150 isp_pci_reset1,
151 isp_pci_dumpregs,
152 ISP_1040_RISC_CODE,
153 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64,
154 0
155};
156#endif
157
158#ifndef ISP_DISABLE_1080_SUPPORT
159static struct ispmdvec mdvec_1080 = {
160 isp_pci_rd_isr,
161 isp_pci_rd_reg_1080,
162 isp_pci_wr_reg_1080,
163 isp_pci_mbxdma,
164 isp_pci_dmasetup,
165 isp_pci_dmateardown,
166 isp_pci_reset0,
167 isp_pci_reset1,
168 isp_pci_dumpregs,
169 ISP_1080_RISC_CODE,
170 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64,
171 0
172};
173#endif
174
175#ifndef ISP_DISABLE_12160_SUPPORT
176static struct ispmdvec mdvec_12160 = {
177 isp_pci_rd_isr,
178 isp_pci_rd_reg_1080,
179 isp_pci_wr_reg_1080,
180 isp_pci_mbxdma,
181 isp_pci_dmasetup,
182 isp_pci_dmateardown,
183 isp_pci_reset0,
184 isp_pci_reset1,
185 isp_pci_dumpregs,
186 ISP_12160_RISC_CODE,
187 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64,
188 0
189};
190#endif
191
192#ifndef ISP_DISABLE_2100_SUPPORT
193static struct ispmdvec mdvec_2100 = {
194 isp_pci_rd_isr,
195 isp_pci_rd_reg,
196 isp_pci_wr_reg,
197 isp_pci_mbxdma,
198 isp_pci_dmasetup,
199 isp_pci_dmateardown,
200 isp_pci_reset0,
201 isp_pci_reset1,
202 isp_pci_dumpregs,
203 ISP_2100_RISC_CODE,
204 0,
205 0
206};
207#endif
208
209#ifndef ISP_DISABLE_2200_SUPPORT
210static struct ispmdvec mdvec_2200 = {
211 isp_pci_rd_isr,
212 isp_pci_rd_reg,
213 isp_pci_wr_reg,
214 isp_pci_mbxdma,
215 isp_pci_dmasetup,
216 isp_pci_dmateardown,
217 isp_pci_reset0,
218 isp_pci_reset1,
219 isp_pci_dumpregs,
220 ISP_2200_RISC_CODE,
221 0,
222 0
223};
224#endif
225
226#ifndef ISP_DISABLE_2300_SUPPORT
227static struct ispmdvec mdvec_2300 = {
228 isp_pci_rd_isr_2300,
229 isp_pci_rd_reg,
230 isp_pci_wr_reg,
231 isp_pci_mbxdma,
232 isp_pci_dmasetup,
233 isp_pci_dmateardown,
234 isp_pci_reset0,
235 isp_pci_reset1,
236 isp_pci_dumpregs,
237 ISP_2300_RISC_CODE,
238 0,
239 0
240};
241#endif
242
243#ifndef ISP_DISABLE_2322_SUPPORT
244static struct ispmdvec mdvec_2322 = {
245 isp_pci_rd_isr_2300,
246 isp_pci_rd_reg,
247 isp_pci_wr_reg,
248 isp_pci_mbxdma,
249 isp_pci_dmasetup,
250 isp_pci_dmateardown,
251 isp_pci_reset0,
252 isp_pci_reset1,
253 isp_pci_dumpregs,
254 ISP_2322_RISC_CODE,
255 0,
256 0
257};
258#endif
259
260#ifndef ISP_DISABLE_2400_SUPPORT
261static struct ispmdvec mdvec_2400 = {
262 isp_pci_rd_isr_2400,
263 isp_pci_rd_reg_2400,
264 isp_pci_wr_reg_2400,
265 isp_pci_mbxdma,
266 isp_pci_dmasetup,
267 isp_pci_dmateardown,
268 isp_pci_reset0,
269 isp_pci_reset1,
270 NULL,
271 ISP_2400_RISC_CODE,
272 0,
273 0
274};
275static struct ispmdvec mdvec_2500 = {
276 isp_pci_rd_isr_2400,
277 isp_pci_rd_reg_2400,
278 isp_pci_wr_reg_2400,
279 isp_pci_mbxdma,
280 isp_pci_dmasetup,
281 isp_pci_dmateardown,
282 isp_pci_reset0,
283 isp_pci_reset1,
284 NULL,
285 ISP_2500_RISC_CODE,
286 0,
287 0
288};
289#endif
290
291#ifndef PCI_VENDOR_QLOGIC
292#define PCI_VENDOR_QLOGIC 0x1077
293#endif
294
295#ifndef PCI_PRODUCT_QLOGIC_ISP1020
296#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
297#endif
298
299#ifndef PCI_PRODUCT_QLOGIC_ISP1080
300#define PCI_PRODUCT_QLOGIC_ISP1080 0x1080
301#endif
302
303#ifndef PCI_PRODUCT_QLOGIC_ISP1240
304#define PCI_PRODUCT_QLOGIC_ISP1240 0x1240
305#endif
306
307#ifndef PCI_PRODUCT_QLOGIC_ISP1280
308#define PCI_PRODUCT_QLOGIC_ISP1280 0x1280
309#endif
310
311#ifndef PCI_PRODUCT_QLOGIC_ISP10160
312#define PCI_PRODUCT_QLOGIC_ISP10160 0x1016
313#endif
314
315#ifndef PCI_PRODUCT_QLOGIC_ISP12160
316#define PCI_PRODUCT_QLOGIC_ISP12160 0x1216
317#endif
318
319#ifndef PCI_PRODUCT_QLOGIC_ISP2100
320#define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
321#endif
322
323#ifndef PCI_PRODUCT_QLOGIC_ISP2200
324#define PCI_PRODUCT_QLOGIC_ISP2200 0x2200
325#endif
326
327#ifndef PCI_PRODUCT_QLOGIC_ISP2300
328#define PCI_PRODUCT_QLOGIC_ISP2300 0x2300
329#endif
330
331#ifndef PCI_PRODUCT_QLOGIC_ISP2312
332#define PCI_PRODUCT_QLOGIC_ISP2312 0x2312
333#endif
334
335#ifndef PCI_PRODUCT_QLOGIC_ISP2322
336#define PCI_PRODUCT_QLOGIC_ISP2322 0x2322
337#endif
338
339#ifndef PCI_PRODUCT_QLOGIC_ISP2422
340#define PCI_PRODUCT_QLOGIC_ISP2422 0x2422
341#endif
342
343#ifndef PCI_PRODUCT_QLOGIC_ISP2432
344#define PCI_PRODUCT_QLOGIC_ISP2432 0x2432
345#endif
346
347#ifndef PCI_PRODUCT_QLOGIC_ISP2532
348#define PCI_PRODUCT_QLOGIC_ISP2532 0x2532
349#endif
350
351#ifndef PCI_PRODUCT_QLOGIC_ISP6312
352#define PCI_PRODUCT_QLOGIC_ISP6312 0x6312
353#endif
354
355#ifndef PCI_PRODUCT_QLOGIC_ISP6322
356#define PCI_PRODUCT_QLOGIC_ISP6322 0x6322
357#endif
358
359
360#define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
361
362#define PCI_QLOGIC_ISP1080 \
363 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC)
364
365#define PCI_QLOGIC_ISP10160 \
366 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC)
367
368#define PCI_QLOGIC_ISP12160 \
369 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC)
370
371#define PCI_QLOGIC_ISP1240 \
372 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC)
373
374#define PCI_QLOGIC_ISP1280 \
375 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC)
376
377#define PCI_QLOGIC_ISP2100 \
378 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
379
380#define PCI_QLOGIC_ISP2200 \
381 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC)
382
383#define PCI_QLOGIC_ISP2300 \
384 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC)
385
386#define PCI_QLOGIC_ISP2312 \
387 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC)
388
389#define PCI_QLOGIC_ISP2322 \
390 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC)
391
392#define PCI_QLOGIC_ISP2422 \
393 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC)
394
395#define PCI_QLOGIC_ISP2432 \
396 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC)
397
398#define PCI_QLOGIC_ISP2532 \
399 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC)
400
401#define PCI_QLOGIC_ISP6312 \
402 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC)
403
404#define PCI_QLOGIC_ISP6322 \
405 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC)
406
407#define IO_MAP_REG 0x10
408#define MEM_MAP_REG 0x14
409#define PCIR_ROMADDR 0x30
410
411#define PCI_DFLT_LTNCY 0x40
412#define PCI_DFLT_LNSZ 0x10
413
414static int isp_pci_probe(device_t, cfdata_t, void *);
415static void isp_pci_attach(device_t, device_t, void *);
416
417struct isp_pcisoftc {
418 struct ispsoftc pci_isp;
419 pci_chipset_tag_t pci_pc;
420 pcitag_t pci_tag;
421 bus_space_tag_t pci_st;
422 bus_space_handle_t pci_sh;
423 bus_dmamap_t *pci_xfer_dmap;
424 void * pci_ih;
425 int16_t pci_poff[_NREG_BLKS];
426};
427
428CFATTACH_DECL_NEW(isp_pci, sizeof (struct isp_pcisoftc),
429 isp_pci_probe, isp_pci_attach, NULL, NULL);
430
431static int
432isp_pci_probe(device_t parent, cfdata_t match, void *aux)
433{
434 struct pci_attach_args *pa = aux;
435 switch (pa->pa_id) {
436#ifndef ISP_DISABLE_1020_SUPPORT
437 case PCI_QLOGIC_ISP:
438 return (1);
439#endif
440#ifndef ISP_DISABLE_1080_SUPPORT
441 case PCI_QLOGIC_ISP1080:
442 case PCI_QLOGIC_ISP1240:
443 case PCI_QLOGIC_ISP1280:
444 return (1);
445#endif
446#ifndef ISP_DISABLE_12160_SUPPORT
447 case PCI_QLOGIC_ISP10160:
448 case PCI_QLOGIC_ISP12160:
449 return (1);
450#endif
451#ifndef ISP_DISABLE_2100_SUPPORT
452 case PCI_QLOGIC_ISP2100:
453 return (1);
454#endif
455#ifndef ISP_DISABLE_2200_SUPPORT
456 case PCI_QLOGIC_ISP2200:
457 return (1);
458#endif
459#ifndef ISP_DISABLE_2300_SUPPORT
460 case PCI_QLOGIC_ISP2300:
461 case PCI_QLOGIC_ISP2312:
462 case PCI_QLOGIC_ISP6312:
463#endif
464#ifndef ISP_DISABLE_2322_SUPPORT
465 case PCI_QLOGIC_ISP2322:
466 case PCI_QLOGIC_ISP6322:
467 return (1);
468#endif
469#ifndef ISP_DISABLE_2400_SUPPORT
470 case PCI_QLOGIC_ISP2422:
471 case PCI_QLOGIC_ISP2432:
472 case PCI_QLOGIC_ISP2532:
473 return (1);
474#endif
475 default:
476 return (0);
477 }
478}
479
480static void
481isp_pci_attach(device_t parent, device_t self, void *aux)
482{
483 static const char nomem[] = "\n%s: no mem for sdparam table\n";
484 uint32_t data, rev, linesz = PCI_DFLT_LNSZ;
485 struct pci_attach_args *pa = aux;
486 struct isp_pcisoftc *pcs = device_private(self);
487 struct ispsoftc *isp = &pcs->pci_isp;
488 bus_space_tag_t st, iot, memt;
489 bus_space_handle_t sh, ioh, memh;
490 pci_intr_handle_t ih;
491 pcireg_t mem_type;
492 const char *dstring;
493 const char *intrstr;
494 int ioh_valid, memh_valid;
495 size_t mamt;
496 char intrbuf[PCI_INTRSTR_LEN];
497
498 isp->isp_osinfo.dev = self;
499
500 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0,
501 &iot, &ioh, NULL, NULL) == 0);
502
503 mem_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, MEM_MAP_REG);
504 if (PCI_MAPREG_TYPE(mem_type) != PCI_MAPREG_TYPE_MEM) {
505 memh_valid = 0;
506 } else if (PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_32BIT &&
507 PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_64BIT) {
508 memh_valid = 0;
509 } else {
510 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, mem_type, 0,
511 &memt, &memh, NULL, NULL) == 0);
512 }
513 if (memh_valid) {
514 st = memt;
515 sh = memh;
516 } else if (ioh_valid) {
517 st = iot;
518 sh = ioh;
519 } else {
520 aprint_error(": unable to map device registers\n");
521 return;
522 }
523 dstring = "\n";
524
525 isp->isp_nchan = 1;
526 mamt = 0;
527
528 pcs->pci_st = st;
529 pcs->pci_sh = sh;
530 pcs->pci_pc = pa->pa_pc;
531 pcs->pci_tag = pa->pa_tag;
532 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF;
533 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF;
534 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF;
535 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF;
536 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF;
537 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff;
538
539
540#ifndef ISP_DISABLE_1020_SUPPORT
541 if (pa->pa_id == PCI_QLOGIC_ISP) {
542 dstring = ": QLogic 1020 Fast Wide SCSI HBA\n";
543 isp->isp_mdvec = &mdvec;
544 isp->isp_type = ISP_HA_SCSI_UNKNOWN;
545 mamt = sizeof (sdparam);
546 }
547#endif
548#ifndef ISP_DISABLE_1080_SUPPORT
549 if (pa->pa_id == PCI_QLOGIC_ISP1080) {
550 dstring = ": QLogic 1080 Ultra-2 Wide SCSI HBA\n";
551 isp->isp_mdvec = &mdvec_1080;
552 isp->isp_type = ISP_HA_SCSI_1080;
553 mamt = sizeof (sdparam);
554 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
555 ISP1080_DMA_REGS_OFF;
556 }
557 if (pa->pa_id == PCI_QLOGIC_ISP1240) {
558 dstring = ": QLogic Dual Channel Ultra Wide SCSI HBA\n";
559 isp->isp_mdvec = &mdvec_1080;
560 isp->isp_type = ISP_HA_SCSI_1240;
561 isp->isp_nchan++;
562 mamt = sizeof (sdparam) * 2;
563 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
564 ISP1080_DMA_REGS_OFF;
565 }
566 if (pa->pa_id == PCI_QLOGIC_ISP1280) {
567 dstring = ": QLogic Dual Channel Ultra-2 Wide SCSI HBA\n";
568 isp->isp_mdvec = &mdvec_1080;
569 isp->isp_type = ISP_HA_SCSI_1280;
570 isp->isp_nchan++;
571 mamt = sizeof (sdparam) * 2;
572 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
573 ISP1080_DMA_REGS_OFF;
574 }
575#endif
576#ifndef ISP_DISABLE_12160_SUPPORT
577 if (pa->pa_id == PCI_QLOGIC_ISP10160) {
578 dstring = ": QLogic Ultra-3 Wide SCSI HBA\n";
579 isp->isp_mdvec = &mdvec_12160;
580 isp->isp_type = ISP_HA_SCSI_10160;
581 mamt = sizeof (sdparam);
582 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
583 ISP1080_DMA_REGS_OFF;
584 }
585 if (pa->pa_id == PCI_QLOGIC_ISP12160) {
586 dstring = ": QLogic Dual Channel Ultra-3 Wide SCSI HBA\n";
587 isp->isp_mdvec = &mdvec_12160;
588 isp->isp_type = ISP_HA_SCSI_12160;
589 isp->isp_nchan++;
590 mamt = sizeof (sdparam) * 2;
591 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
592 ISP1080_DMA_REGS_OFF;
593 }
594#endif
595#ifndef ISP_DISABLE_2100_SUPPORT
596 if (pa->pa_id == PCI_QLOGIC_ISP2100) {
597 dstring = ": QLogic FC-AL HBA\n";
598 isp->isp_mdvec = &mdvec_2100;
599 isp->isp_type = ISP_HA_FC_2100;
600 mamt = sizeof (fcparam);
601 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
602 PCI_MBOX_REGS2100_OFF;
603 if (rev < 3) {
604 /*
605 * XXX: Need to get the actual revision
606 * XXX: number of the 2100 FB. At any rate,
607 * XXX: lower cache line size for early revision
608 * XXX; boards.
609 */
610 linesz = 1;
611 }
612 }
613#endif
614#ifndef ISP_DISABLE_2200_SUPPORT
615 if (pa->pa_id == PCI_QLOGIC_ISP2200) {
616 dstring = ": QLogic FC-AL and Fabric HBA\n";
617 isp->isp_mdvec = &mdvec_2200;
618 isp->isp_type = ISP_HA_FC_2200;
619 mamt = sizeof (fcparam);
620 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
621 PCI_MBOX_REGS2100_OFF;
622 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
623 }
624#endif
625#ifndef ISP_DISABLE_2300_SUPPORT
626 if (pa->pa_id == PCI_QLOGIC_ISP2300 ||
627 pa->pa_id == PCI_QLOGIC_ISP2312 ||
628 pa->pa_id == PCI_QLOGIC_ISP6312) {
629 isp->isp_mdvec = &mdvec_2300;
630 if (pa->pa_id == PCI_QLOGIC_ISP2300 ||
631 pa->pa_id == PCI_QLOGIC_ISP6312) {
632 dstring = ": QLogic FC-AL and 2Gbps Fabric HBA\n";
633 isp->isp_type = ISP_HA_FC_2300;
634 } else {
635 dstring =
636 ": QLogic Dual Port FC-AL and 2Gbps Fabric HBA\n";
637 isp->isp_port = pa->pa_function;
638 }
639 isp->isp_type = ISP_HA_FC_2312;
640 mamt = sizeof (fcparam);
641 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
642 PCI_MBOX_REGS2300_OFF;
643 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
644 }
645#endif
646#ifndef ISP_DISABLE_2322_SUPPORT
647 if (pa->pa_id == PCI_QLOGIC_ISP2322 ||
648 pa->pa_id == PCI_QLOGIC_ISP6322) {
649 isp->isp_mdvec = &mdvec_2322;
650 dstring = ": QLogic FC-AL and 2Gbps Fabric PCI-E HBA\n";
651 isp->isp_type = ISP_HA_FC_2322;
652 isp->isp_port = pa->pa_function;
653 mamt = sizeof (fcparam);
654 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
655 PCI_MBOX_REGS2300_OFF;
656 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
657 }
658#endif
659#ifndef ISP_DISABLE_2400_SUPPORT
660 if (pa->pa_id == PCI_QLOGIC_ISP2422 ||
661 pa->pa_id == PCI_QLOGIC_ISP2432) {
662 isp->isp_mdvec = &mdvec_2400;
663 if (pa->pa_id == PCI_QLOGIC_ISP2422) {
664 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-X HBA\n";
665 } else {
666 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-E HBA\n";
667 }
668 isp->isp_type = ISP_HA_FC_2400;
669 isp->isp_port = pa->pa_function;
670 mamt = sizeof (fcparam);
671 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
672 PCI_MBOX_REGS2400_OFF;
673 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
674 }
675 if (pa->pa_id == PCI_QLOGIC_ISP2532) {
676 isp->isp_mdvec = &mdvec_2500;
677 dstring = ": QLogic FC-AL and 8Gbps Fabric PCI-E HBA\n";
678 isp->isp_type = ISP_HA_FC_2500;
679 isp->isp_port = pa->pa_function;
680 mamt = sizeof (fcparam);
681 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
682 PCI_MBOX_REGS2400_OFF;
683 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
684 }
685#endif
686 if (mamt == 0) {
687 return;
688 }
689
690 isp->isp_param = malloc(mamt, M_DEVBUF, M_NOWAIT);
691 if (isp->isp_param == NULL) {
692 aprint_error(nomem, device_xname(self));
693 return;
694 }
695 memset(isp->isp_param, 0, mamt);
696 mamt = sizeof (struct scsipi_channel) * isp->isp_nchan;
697 isp->isp_osinfo.chan = malloc(mamt, M_DEVBUF, M_NOWAIT);
698 if (isp->isp_osinfo.chan == NULL) {
699 free(isp->isp_param, M_DEVBUF);
700 aprint_error(nomem, device_xname(self));
701 return;
702 }
703 memset(isp->isp_osinfo.chan, 0, mamt);
704 isp->isp_osinfo.adapter.adapt_nchannels = isp->isp_nchan;
705
706 /*
707 * Set up logging levels.
708 */
709#ifdef ISP_LOGDEFAULT
710 isp->isp_dblev = ISP_LOGDEFAULT;
711#else
712 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR;
713 if (bootverbose)
714 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO;
715#ifdef SCSIDEBUG
716 isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGDEBUG1|ISP_LOGDEBUG2;
717#endif
718#endif
719 if (isp->isp_dblev & ISP_LOGCONFIG) {
720 aprint_normal("\n");
721 } else {
722 aprint_normal("%s", dstring);
723 }
724
725 isp->isp_dmatag = pa->pa_dmat;
726 isp->isp_revision = rev;
727
728 /*
729 * Make sure that command register set sanely.
730 */
731 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
732 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE;
733
734 /*
735 * Not so sure about these- but I think it's important that they get
736 * enabled......
737 */
738 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
739 if (IS_2300(isp)) { /* per QLogic errata */
740 data &= ~PCI_COMMAND_INVALIDATE_ENABLE;
741 }
742 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data);
743
744 /*
745 * Make sure that the latency timer, cache line size,
746 * and ROM is disabled.
747 */
748 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
749 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
750 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT);
751 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT);
752 data |= (linesz << PCI_CACHELINE_SHIFT);
753 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data);
754
755 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR);
756 data &= ~1;
757 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data);
758
759 if (pci_intr_map(pa, &ih)) {
760 aprint_error_dev(self, "couldn't map interrupt\n");
761 free(isp->isp_param, M_DEVBUF);
762 free(isp->isp_osinfo.chan, M_DEVBUF);
763 return;
764 }
765 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf));
766 if (intrstr == NULL)
767 intrstr = "<I dunno>";
768 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO,
769 isp_pci_intr, isp);
770 if (pcs->pci_ih == NULL) {
771 aprint_error_dev(self, "couldn't establish interrupt at %s\n",
772 intrstr);
773 free(isp->isp_param, M_DEVBUF);
774 free(isp->isp_osinfo.chan, M_DEVBUF);
775 return;
776 }
777
778 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
779
780 isp->isp_confopts = device_cfdata(self)->cf_flags;
781 ISP_LOCK(isp);
782 isp_reset(isp, 1);
783 if (isp->isp_state != ISP_RESETSTATE) {
784 ISP_UNLOCK(isp);
785 free(isp->isp_param, M_DEVBUF);
786 free(isp->isp_osinfo.chan, M_DEVBUF);
787 return;
788 }
789 isp_init(isp);
790 if (isp->isp_state != ISP_INITSTATE) {
791 isp_uninit(isp);
792 ISP_UNLOCK(isp);
793 free(isp->isp_param, M_DEVBUF);
794 free(isp->isp_osinfo.chan, M_DEVBUF);
795 return;
796 }
797 /*
798 * Do platform attach.
799 */
800 ISP_UNLOCK(isp);
801 isp_attach(isp);
802}
803
804#define IspVirt2Off(a, x) \
805 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \
806 _BLK_REG_SHFT] + ((x) & 0xff))
807
808#define BXR2(pcs, off) \
809 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off)
810#define BXW2(pcs, off, v) \
811 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v)
812#define BXR4(pcs, off) \
813 bus_space_read_4(pcs->pci_st, pcs->pci_sh, off)
814#define BXW4(pcs, off, v) \
815 bus_space_write_4(pcs->pci_st, pcs->pci_sh, off, v)
816
817
818static int
819isp_pci_rd_debounced(struct ispsoftc *isp, int off, uint16_t *rp)
820{
821 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
822 uint16_t val0, val1;
823 int i = 0;
824
825 do {
826 val0 = BXR2(pcs, IspVirt2Off(isp, off));
827 val1 = BXR2(pcs, IspVirt2Off(isp, off));
828 } while (val0 != val1 && ++i < 1000);
829 if (val0 != val1) {
830 return (1);
831 }
832 *rp = val0;
833 return (0);
834}
835
836#if !defined(ISP_DISABLE_2100_SUPPORT) && \
837 !defined(ISP_DISABLE_2200_SUPPORT) && \
838 !defined(ISP_DISABLE_1020_SUPPORT) && \
839 !defined(ISP_DISABLE_1080_SUPPORT) && \
840 !defined(ISP_DISABLE_12160_SUPPORT)
841static int
842isp_pci_rd_isr(struct ispsoftc *isp, uint32_t *isrp,
843 uint16_t *semap, uint16_t *mbp)
844{
845 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
846 uint16_t isr, sema;
847
848 if (IS_2100(isp)) {
849 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) {
850 return (0);
851 }
852 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) {
853 return (0);
854 }
855 } else {
856 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR));
857 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA));
858 }
859 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema);
860 isr &= INT_PENDING_MASK(isp);
861 sema &= BIU_SEMA_LOCK;
862 if (isr == 0 && sema == 0) {
863 return (0);
864 }
865 *isrp = isr;
866 if ((*semap = sema) != 0) {
867 if (IS_2100(isp)) {
868 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) {
869 return (0);
870 }
871 } else {
872 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0));
873 }
874 }
875 return (1);
876}
877#endif
878
879#if !(defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_2322_SUPPORT))
880static int
881isp_pci_rd_isr_2300(struct ispsoftc *isp, uint32_t *isrp,
882 uint16_t *semap, uint16_t *mbox0p)
883{
884 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
885 uint32_t r2hisr;
886
887 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) {
888 *isrp = 0;
889 return (0);
890 }
891 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh,
892 IspVirt2Off(pcs, BIU_R2HSTSLO));
893 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
894 if ((r2hisr & BIU_R2HST_INTR) == 0) {
895 *isrp = 0;
896 return (0);
897 }
898 switch (r2hisr & BIU_R2HST_ISTAT_MASK) {
899 case ISPR2HST_ROM_MBX_OK:
900 case ISPR2HST_ROM_MBX_FAIL:
901 case ISPR2HST_MBX_OK:
902 case ISPR2HST_MBX_FAIL:
903 case ISPR2HST_ASYNC_EVENT:
904 *isrp = r2hisr & 0xffff;
905 *mbox0p = (r2hisr >> 16);
906 *semap = 1;
907 return (1);
908 case ISPR2HST_RIO_16:
909 *isrp = r2hisr & 0xffff;
910 *mbox0p = ASYNC_RIO16_1;
911 *semap = 1;
912 return (1);
913 case ISPR2HST_FPOST:
914 *isrp = r2hisr & 0xffff;
915 *mbox0p = ASYNC_CMD_CMPLT;
916 *semap = 1;
917 return (1);
918 case ISPR2HST_FPOST_CTIO:
919 *isrp = r2hisr & 0xffff;
920 *mbox0p = ASYNC_CTIO_DONE;
921 *semap = 1;
922 return (1);
923 case ISPR2HST_RSPQ_UPDATE:
924 *isrp = r2hisr & 0xffff;
925 *mbox0p = 0;
926 *semap = 0;
927 return (1);
928 default:
929 return (0);
930 }
931}
932#endif
933
934#ifndef ISP_DISABLE_2400_SUPPORT
935static int
936isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp,
937 uint16_t *semap, uint16_t *mbox0p)
938{
939 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
940 uint32_t r2hisr;
941
942 r2hisr = BXR4(pcs, IspVirt2Off(pcs, BIU2400_R2HSTSLO));
943 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
944 if ((r2hisr & BIU2400_R2HST_INTR) == 0) {
945 *isrp = 0;
946 return (0);
947 }
948 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) {
949 case ISP2400R2HST_ROM_MBX_OK:
950 case ISP2400R2HST_ROM_MBX_FAIL:
951 case ISP2400R2HST_MBX_OK:
952 case ISP2400R2HST_MBX_FAIL:
953 case ISP2400R2HST_ASYNC_EVENT:
954 *isrp = r2hisr & 0xffff;
955 *mbox0p = (r2hisr >> 16);
956 *semap = 1;
957 return (1);
958 case ISP2400R2HST_RSPQ_UPDATE:
959 case ISP2400R2HST_ATIO_RSPQ_UPDATE:
960 case ISP2400R2HST_ATIO_RQST_UPDATE:
961 *isrp = r2hisr & 0xffff;
962 *mbox0p = 0;
963 *semap = 0;
964 return (1);
965 default:
966 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
967 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
968 return (0);
969 }
970}
971
972static uint32_t
973isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff)
974{
975 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
976 uint32_t rv;
977 int block = regoff & _BLK_REG_MASK;
978
979 switch (block) {
980 case BIU_BLOCK:
981 break;
982 case MBOX_BLOCK:
983 return (BXR2(pcs, IspVirt2Off(pcs, regoff)));
984 case SXP_BLOCK:
985 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff);
986 return (0xffffffff);
987 case RISC_BLOCK:
988 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff);
989 return (0xffffffff);
990 case DMA_BLOCK:
991 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff);
992 return (0xffffffff);
993 default:
994 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff);
995 return (0xffffffff);
996 }
997
998
999 switch (regoff) {
1000 case BIU2400_FLASH_ADDR:
1001 case BIU2400_FLASH_DATA:
1002 case BIU2400_ICR:
1003 case BIU2400_ISR:
1004 case BIU2400_CSR:
1005 case BIU2400_REQINP:
1006 case BIU2400_REQOUTP:
1007 case BIU2400_RSPINP:
1008 case BIU2400_RSPOUTP:
1009 case BIU2400_PRI_REQINP:
1010 case BIU2400_PRI_REQOUTP:
1011 case BIU2400_ATIO_RSPINP:
1012 case BIU2400_ATIO_RSPOUTP:
1013 case BIU2400_HCCR:
1014 case BIU2400_GPIOD:
1015 case BIU2400_GPIOE:
1016 case BIU2400_HSEMA:
1017 rv = BXR4(pcs, IspVirt2Off(pcs, regoff));
1018 break;
1019 case BIU2400_R2HSTSLO:
1020 rv = BXR4(pcs, IspVirt2Off(pcs, regoff));
1021 break;
1022 case BIU2400_R2HSTSHI:
1023 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)) >> 16;
1024 break;
1025 default:
1026 isp_prt(isp, ISP_LOGERR,
1027 "isp_pci_rd_reg_2400: unknown offset %x", regoff);
1028 rv = 0xffffffff;
1029 break;
1030 }
1031 return (rv);
1032}
1033
1034static void
1035isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val)
1036{
1037 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1038 int block = regoff & _BLK_REG_MASK;
1039
1040 switch (block) {
1041 case BIU_BLOCK:
1042 break;
1043 case MBOX_BLOCK:
1044 BXW2(pcs, IspVirt2Off(pcs, regoff), val);
1045 (void)BXR2(pcs, IspVirt2Off(pcs, regoff));
1046 return;
1047 case SXP_BLOCK:
1048 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff);
1049 return;
1050 case RISC_BLOCK:
1051 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff);
1052 return;
1053 case DMA_BLOCK:
1054 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff);
1055 return;
1056 default:
1057 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x",
1058 regoff);
1059 break;
1060 }
1061
1062 switch (regoff) {
1063 case BIU2400_FLASH_ADDR:
1064 case BIU2400_FLASH_DATA:
1065 case BIU2400_ICR:
1066 case BIU2400_ISR:
1067 case BIU2400_CSR:
1068 case BIU2400_REQINP:
1069 case BIU2400_REQOUTP:
1070 case BIU2400_RSPINP:
1071 case BIU2400_RSPOUTP:
1072 case BIU2400_PRI_REQINP:
1073 case BIU2400_PRI_REQOUTP:
1074 case BIU2400_ATIO_RSPINP:
1075 case BIU2400_ATIO_RSPOUTP:
1076 case BIU2400_HCCR:
1077 case BIU2400_GPIOD:
1078 case BIU2400_GPIOE:
1079 case BIU2400_HSEMA:
1080 BXW4(pcs, IspVirt2Off(pcs, regoff), val);
1081 (void)BXR4(pcs, IspVirt2Off(pcs, regoff));
1082 break;
1083 default:
1084 isp_prt(isp, ISP_LOGERR,
1085 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff);
1086 break;
1087 }
1088}
1089#endif
1090
1091static uint32_t
1092isp_pci_rd_reg(struct ispsoftc *isp, int regoff)
1093{
1094 uint32_t rv;
1095 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1096 int oldconf = 0;
1097
1098 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1099 /*
1100 * We will assume that someone has paused the RISC processor.
1101 */
1102 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1103 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1104 oldconf | BIU_PCI_CONF1_SXP);
1105 }
1106 rv = BXR2(pcs, IspVirt2Off(isp, regoff));
1107 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1108 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
1109 }
1110 return (rv);
1111}
1112
1113static void
1114isp_pci_wr_reg(struct ispsoftc *isp, int regoff, uint32_t val)
1115{
1116 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1117 int oldconf = 0;
1118
1119 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1120 /*
1121 * We will assume that someone has paused the RISC processor.
1122 */
1123 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1124 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1125 oldconf | BIU_PCI_CONF1_SXP);
1126 }
1127 BXW2(pcs, IspVirt2Off(isp, regoff), val);
1128 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1129 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
1130 }
1131}
1132
1133#if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT))
1134static uint32_t
1135isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff)
1136{
1137 uint16_t rv, oc = 0;
1138 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1139
1140 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
1141 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
1142 uint16_t tc;
1143 /*
1144 * We will assume that someone has paused the RISC processor.
1145 */
1146 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1147 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1148 if (regoff & SXP_BANK1_SELECT)
1149 tc |= BIU_PCI1080_CONF1_SXP1;
1150 else
1151 tc |= BIU_PCI1080_CONF1_SXP0;
1152 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc);
1153 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1154 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1155 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1156 oc | BIU_PCI1080_CONF1_DMA);
1157 }
1158 rv = BXR2(pcs, IspVirt2Off(isp, regoff));
1159 if (oc) {
1160 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
1161 }
1162 return (rv);
1163}
1164
1165static void
1166isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, uint32_t val)
1167{
1168 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1169 int oc = 0;
1170
1171 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
1172 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
1173 uint16_t tc;
1174 /*
1175 * We will assume that someone has paused the RISC processor.
1176 */
1177 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1178 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1179 if (regoff & SXP_BANK1_SELECT)
1180 tc |= BIU_PCI1080_CONF1_SXP1;
1181 else
1182 tc |= BIU_PCI1080_CONF1_SXP0;
1183 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc);
1184 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1185 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1186 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1187 oc | BIU_PCI1080_CONF1_DMA);
1188 }
1189 BXW2(pcs, IspVirt2Off(isp, regoff), val);
1190 if (oc) {
1191 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
1192 }
1193}
1194#endif
1195
1196static int
1197isp_pci_mbxdma(struct ispsoftc *isp)
1198{
1199 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1200 bus_dma_tag_t dmat = isp->isp_dmatag;
1201 bus_dma_segment_t sg;
1202 bus_size_t len, dbound;
1203 fcparam *fcp;
1204 int rs, i;
1205
1206 if (isp->isp_rquest_dma) /* been here before? */
1207 return (0);
1208
1209 if (isp->isp_type <= ISP_HA_SCSI_1040B) {
1210 dbound = 1 << 24;
1211 } else {
1212 /*
1213 * For 32-bit PCI DMA, the range is 32 bits or zero :-)
1214 */
1215 dbound = 0;
1216 }
1217 len = isp->isp_maxcmds * sizeof (isp_hdl_t);
1218 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK);
1219 if (isp->isp_xflist == NULL) {
1220 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array");
1221 return (1);
1222 }
1223 memset(isp->isp_xflist, 0, len);
1224 for (len = 0; len < isp->isp_maxcmds - 1; len++) {
1225 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1];
1226 }
1227 isp->isp_xffree = isp->isp_xflist;
1228 len = isp->isp_maxcmds * sizeof (bus_dmamap_t);
1229 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK);
1230 if (pcs->pci_xfer_dmap == NULL) {
1231 free(isp->isp_xflist, M_DEVBUF);
1232 isp->isp_xflist = NULL;
1233 isp_prt(isp, ISP_LOGERR, "cannot malloc DMA map array");
1234 return (1);
1235 }
1236 for (i = 0; i < isp->isp_maxcmds; i++) {
1237 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1,
1238 MAXPHYS, dbound, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) {
1239 isp_prt(isp, ISP_LOGERR, "cannot create DMA maps");
1240 break;
1241 }
1242 }
1243 if (i < isp->isp_maxcmds) {
1244 while (--i >= 0) {
1245 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]);
1246 }
1247 free(isp->isp_xflist, M_DEVBUF);
1248 free(pcs->pci_xfer_dmap, M_DEVBUF);
1249 isp->isp_xflist = NULL;
1250 pcs->pci_xfer_dmap = NULL;
1251 return (1);
1252 }
1253
1254 /*
1255 * Allocate and map the request queue.
1256 */
1257 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
1258 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 0)) {
1259 goto dmafail;
1260 }
1261 if (bus_dmamem_map(isp->isp_dmatag, &sg, rs, len,
1262 (void *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
1263 goto dmafail;
1264 }
1265 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT,
1266 &isp->isp_rqdmap)) {
1267 goto dmafail;
1268 }
1269 if (bus_dmamap_load(dmat, isp->isp_rqdmap, isp->isp_rquest, len, NULL,
1270 BUS_DMA_NOWAIT)) {
1271 goto dmafail;
1272 }
1273 isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr;
1274
1275 /*
1276 * Allocate and map the result queue.
1277 */
1278 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
1279 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs,
1280 BUS_DMA_NOWAIT)) {
1281 goto dmafail;
1282 }
1283 if (bus_dmamem_map(dmat, &sg, rs, len,
1284 (void *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
1285 goto dmafail;
1286 }
1287 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT,
1288 &isp->isp_rsdmap)) {
1289 goto dmafail;
1290 }
1291 if (bus_dmamap_load(dmat, isp->isp_rsdmap, isp->isp_result, len, NULL,
1292 BUS_DMA_NOWAIT)) {
1293 goto dmafail;
1294 }
1295 isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr;
1296
1297 if (IS_SCSI(isp)) {
1298 return (0);
1299 }
1300
1301 /*
1302 * Allocate and map an FC scratch area
1303 */
1304 fcp = isp->isp_param;
1305 len = ISP_FC_SCRLEN;
1306 if (bus_dmamem_alloc(dmat, len, sizeof (uint64_t), 0, &sg, 1, &rs,
1307 BUS_DMA_NOWAIT)) {
1308 goto dmafail;
1309 }
1310 if (bus_dmamem_map(dmat, &sg, rs, len,
1311 (void *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
1312 goto dmafail;
1313 }
1314 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT,
1315 &isp->isp_scdmap)) {
1316 goto dmafail;
1317 }
1318 if (bus_dmamap_load(dmat, isp->isp_scdmap, fcp->isp_scratch, len, NULL,
1319 BUS_DMA_NOWAIT)) {
1320 goto dmafail;
1321 }
1322 fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr;
1323 return (0);
1324dmafail:
1325 isp_prt(isp, ISP_LOGERR, "mailbox DMA setup failure");
1326 for (i = 0; i < isp->isp_maxcmds; i++) {
1327 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]);
1328 }
1329 free(isp->isp_xflist, M_DEVBUF);
1330 free(pcs->pci_xfer_dmap, M_DEVBUF);
1331 isp->isp_xflist = NULL;
1332 pcs->pci_xfer_dmap = NULL;
1333 return (1);
1334}
1335
1336static int
1337isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, void *arg)
1338{
1339 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1340 ispreq_t *rq = arg;
1341 bus_dmamap_t dmap;
1342 bus_dma_segment_t *dm_segs;
1343 uint32_t nsegs, hidx;
1344 isp_ddir_t ddir;
1345
1346 hidx = isp_handle_index(isp, rq->req_handle);
1347 if (hidx == ISP_BAD_HANDLE_INDEX) {
1348 XS_SETERR(xs, HBA_BOTCH);
1349 return (CMD_COMPLETE);
1350 }
1351 dmap = pcs->pci_xfer_dmap[hidx];
1352 if (xs->datalen == 0) {
1353 ddir = ISP_NOXFR;
1354 nsegs = 0;
1355 dm_segs = NULL;
1356 } else {
1357 int error;
1358 uint32_t flag, flg2;
1359
1360 if (sizeof (bus_addr_t) > 4) {
1361 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) {
1362 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS;
1363 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) {
1364 rq->req_header.rqs_entry_type = RQSTYPE_A64;
1365 }
1366 }
1367
1368 if (xs->xs_control & XS_CTL_DATA_IN) {
1369 flg2 = BUS_DMASYNC_PREREAD;
1370 flag = BUS_DMA_READ;
1371 ddir = ISP_FROM_DEVICE;
1372 } else {
1373 flg2 = BUS_DMASYNC_PREWRITE;
1374 flag = BUS_DMA_WRITE;
1375 ddir = ISP_TO_DEVICE;
1376 }
1377 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data,
1378 xs->datalen, NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ?
1379 BUS_DMA_NOWAIT :
1380 BUS_DMA_WAITOK) | BUS_DMA_STREAMING | flag);
1381 if (error) {
1382 isp_prt(isp, ISP_LOGWARN, "unable to load DMA (%d)",
1383 error);
1384 XS_SETERR(xs, HBA_BOTCH);
1385 if (error == EAGAIN || error == ENOMEM) {
1386 return (CMD_EAGAIN);
1387 } else {
1388 return (CMD_COMPLETE);
1389 }
1390 }
1391 dm_segs = dmap->dm_segs;
1392 nsegs = dmap->dm_nsegs;
1393 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize,
1394 flg2);
1395 }
1396
1397 if (isp_send_cmd(isp, rq, dm_segs, nsegs, xs->datalen, ddir)
1398 != CMD_QUEUED) {
1399 return (CMD_EAGAIN);
1400 } else {
1401 return (CMD_QUEUED);
1402 }
1403}
1404
1405static int
1406isp_pci_intr(void *arg)
1407{
1408 uint32_t isr;
1409 uint16_t sema, mbox;
1410 struct ispsoftc *isp = arg;
1411
1412 isp->isp_intcnt++;
1413 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) {
1414 isp->isp_intbogus++;
1415 return (0);
1416 } else {
1417 isp->isp_osinfo.onintstack = 1;
1418 isp_intr(isp, isr, sema, mbox);
1419 isp->isp_osinfo.onintstack = 0;
1420 return (1);
1421 }
1422}
1423
1424static void
1425isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, uint32_t handle)
1426{
1427 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1428 uint32_t hidx;
1429 bus_dmamap_t dmap;
1430
1431 hidx = isp_handle_index(isp, handle);
1432 if (hidx == ISP_BAD_HANDLE_INDEX) {
1433 isp_xs_prt(isp, xs, ISP_LOGERR, "bad handle on teardown");
1434 return;
1435 }
1436 dmap = pcs->pci_xfer_dmap[hidx];
1437 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize,
1438 xs->xs_control & XS_CTL_DATA_IN ?
1439 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1440 bus_dmamap_unload(isp->isp_dmatag, dmap);
1441}
1442
1443static void
1444isp_pci_reset0(ispsoftc_t *isp)
1445{
1446 ISP_DISABLE_INTS(isp);
1447}
1448
1449static void
1450isp_pci_reset1(ispsoftc_t *isp)
1451{
1452 if (!IS_24XX(isp)) {
1453 /* Make sure the BIOS is disabled */
1454 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
1455 }
1456 /* and enable interrupts */
1457 ISP_ENABLE_INTS(isp);
1458}
1459
1460static void
1461isp_pci_dumpregs(struct ispsoftc *isp, const char *msg)
1462{
1463 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1464 if (msg)
1465 printf("%s: %s\n", device_xname(isp->isp_osinfo.dev), msg);
1466 if (IS_SCSI(isp))
1467 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1));
1468 else
1469 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR));
1470 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR),
1471 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA));
1472 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR));
1473
1474
1475 if (IS_SCSI(isp)) {
1476 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
1477 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n",
1478 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS),
1479 ISP_READ(isp, CDMA_FIFO_STS));
1480 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n",
1481 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS),
1482 ISP_READ(isp, DDMA_FIFO_STS));
1483 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n",
1484 ISP_READ(isp, SXP_INTERRUPT),
1485 ISP_READ(isp, SXP_GROSS_ERR),
1486 ISP_READ(isp, SXP_PINS_CTRL));
1487 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
1488 }
1489 printf(" mbox regs: %x %x %x %x %x\n",
1490 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1),
1491 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3),
1492 ISP_READ(isp, OUTMAILBOX4));
1493 printf(" PCI Status Command/Status=%x\n",
1494 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG));
1495}
1496