1/* $NetBSD: athnvar.h,v 1.5 2015/11/27 21:16:17 jmcneill Exp $ */
2/* $OpenBSD: athnvar.h,v 1.34 2013/10/21 16:13:49 stsp Exp $ */
3
4/*-
5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#ifndef _ATHNVAR_H_
21#define _ATHNVAR_H_
22
23#ifdef _KERNEL_OPT
24#include "opt_athn.h"
25#endif
26
27#define PUBLIC
28
29#define IEEE80211_NO_HT /* XXX: porting artifact */
30
31#ifdef notyet
32#define ATHN_BT_COEXISTENCE 1
33#endif
34
35#define ATHN_SOFTC(sc) ((struct athn_softc *)(sc))
36#define ATHN_NODE(ni) ((struct athn_node *)(ni))
37
38#ifdef ATHN_DEBUG
39#define DBG_INIT __BIT(0)
40#define DBG_FN __BIT(1)
41#define DBG_TX __BIT(2)
42#define DBG_RX __BIT(3)
43#define DBG_STM __BIT(4)
44#define DBG_RF __BIT(5)
45#define DBG_NODES __BIT(6)
46#define DBG_INTR __BIT(7)
47#define DBG_ALL 0xffffffffU
48#define DPRINTFN(n, s, ...) do { \
49 if (athn_debug & (n)) { \
50 printf("%s: %s: ", \
51 device_xname(ATHN_SOFTC(s)->sc_dev), __func__); \
52 printf(__VA_ARGS__); \
53 } \
54} while (0)
55extern int athn_debug;
56#else /* ATHN_DEBUG */
57#define DPRINTFN(n, s, ...)
58#endif /* ATHN_DEBUG */
59
60#define LE_READ_4(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24)
61#define LE_READ_2(p) ((p)[0] | (p)[1] << 8)
62
63#define ATHN_RXBUFSZ 3872
64#define ATHN_TXBUFSZ 4096
65
66#define ATHN_NRXBUFS 64
67#define ATHN_NTXBUFS 64 /* Shared between all Tx queues. */
68
69struct athn_rx_radiotap_header {
70 struct ieee80211_radiotap_header wr_ihdr;
71 uint64_t wr_tsft;
72 uint8_t wr_flags;
73 uint8_t wr_rate;
74 uint16_t wr_chan_freq;
75 uint16_t wr_chan_flags;
76 int8_t wr_dbm_antsignal;
77 uint8_t wr_antenna;
78} __packed;
79
80#define ATHN_RX_RADIOTAP_PRESENT \
81 (1 << IEEE80211_RADIOTAP_TSFT | \
82 1 << IEEE80211_RADIOTAP_FLAGS | \
83 1 << IEEE80211_RADIOTAP_RATE | \
84 1 << IEEE80211_RADIOTAP_CHANNEL | \
85 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL | \
86 1 << IEEE80211_RADIOTAP_ANTENNA)
87
88struct athn_tx_radiotap_header {
89 struct ieee80211_radiotap_header wt_ihdr;
90 uint8_t wt_flags;
91 uint8_t wt_rate;
92 uint16_t wt_chan_freq;
93 uint16_t wt_chan_flags;
94} __packed;
95
96#define ATHN_TX_RADIOTAP_PRESENT \
97 (1 << IEEE80211_RADIOTAP_FLAGS | \
98 1 << IEEE80211_RADIOTAP_RATE | \
99 1 << IEEE80211_RADIOTAP_CHANNEL)
100
101struct athn_tx_buf {
102 SIMPLEQ_ENTRY(athn_tx_buf) bf_list;
103
104 void *bf_descs;
105 bus_dmamap_t bf_map;
106 bus_addr_t bf_daddr;
107
108 struct mbuf *bf_m;
109 struct ieee80211_node *bf_ni;
110 int bf_txflags;
111#define ATHN_TXFLAG_PAPRD (1 << 0)
112#define ATHN_TXFLAG_CAB (1 << 1)
113};
114
115struct athn_txq {
116 SIMPLEQ_HEAD(, athn_tx_buf) head;
117 void *lastds;
118 struct athn_tx_buf *wait;
119 int queued;
120};
121
122struct athn_rx_buf {
123 SIMPLEQ_ENTRY(athn_rx_buf) bf_list;
124
125 void *bf_desc;
126 bus_dmamap_t bf_map;
127
128 struct mbuf *bf_m;
129 bus_addr_t bf_daddr;
130};
131
132struct athn_rxq {
133 struct athn_rx_buf *bf;
134
135 void *descs;
136 void *lastds;
137 bus_dmamap_t map;
138 bus_dma_segment_t seg;
139 int count;
140
141 SIMPLEQ_HEAD(, athn_rx_buf) head;
142};
143
144/* Software rate indexes. */
145#define ATHN_RIDX_CCK1 0
146#define ATHN_RIDX_CCK2 1
147#define ATHN_RIDX_OFDM6 4
148#define ATHN_RIDX_MCS0 12
149#define ATHN_RIDX_MCS15 27
150#define ATHN_RIDX_MAX 27
151#define ATHN_IS_HT_RIDX(ridx) ((ridx) >= ATHN_RIDX_MCS0)
152
153static const struct athn_rate {
154 uint8_t rate; /* Rate in 500Kbps unit or MCS if 0x80. */
155 uint8_t hwrate; /* HW representation. */
156 uint8_t rspridx; /* Control Response Frame rate index. */
157 enum ieee80211_phytype phy;
158} athn_rates[] = {
159 { 2, 0x1b, 0, IEEE80211_T_DS },
160 { 4, 0x1a, 1, IEEE80211_T_DS },
161 { 11, 0x19, 1, IEEE80211_T_DS },
162 { 22, 0x18, 1, IEEE80211_T_DS },
163 { 12, 0x0b, 4, IEEE80211_T_OFDM },
164 { 18, 0x0f, 4, IEEE80211_T_OFDM },
165 { 24, 0x0a, 6, IEEE80211_T_OFDM },
166 { 36, 0x0e, 6, IEEE80211_T_OFDM },
167 { 48, 0x09, 8, IEEE80211_T_OFDM },
168 { 72, 0x0d, 8, IEEE80211_T_OFDM },
169 { 96, 0x08, 8, IEEE80211_T_OFDM },
170 { 108, 0x0c, 8, IEEE80211_T_OFDM },
171 { 0x80, 0x80, 8, IEEE80211_T_OFDM },
172 { 0x81, 0x81, 8, IEEE80211_T_OFDM },
173 { 0x82, 0x82, 8, IEEE80211_T_OFDM },
174 { 0x83, 0x83, 8, IEEE80211_T_OFDM },
175 { 0x84, 0x84, 8, IEEE80211_T_OFDM },
176 { 0x85, 0x85, 8, IEEE80211_T_OFDM },
177 { 0x86, 0x86, 8, IEEE80211_T_OFDM },
178 { 0x87, 0x87, 8, IEEE80211_T_OFDM },
179 { 0x88, 0x88, 8, IEEE80211_T_OFDM },
180 { 0x89, 0x89, 8, IEEE80211_T_OFDM },
181 { 0x8a, 0x8a, 8, IEEE80211_T_OFDM },
182 { 0x8b, 0x8b, 8, IEEE80211_T_OFDM },
183 { 0x8c, 0x8c, 8, IEEE80211_T_OFDM },
184 { 0x8d, 0x8d, 8, IEEE80211_T_OFDM },
185 { 0x8e, 0x8e, 8, IEEE80211_T_OFDM },
186 { 0x8f, 0x8f, 8, IEEE80211_T_OFDM }
187};
188
189struct athn_series {
190 uint16_t dur;
191 uint8_t hwrate;
192};
193
194struct athn_pier {
195 uint8_t fbin;
196 const uint8_t *pwr[AR_PD_GAINS_IN_MASK];
197 const uint8_t *vpd[AR_PD_GAINS_IN_MASK];
198};
199
200/*
201 * Structures used to store initialization values.
202 */
203struct athn_ini {
204 int nregs;
205 const uint16_t *regs;
206 const uint32_t *vals_5g20;
207#ifndef IEEE80211_NO_HT
208 const uint32_t *vals_5g40;
209 const uint32_t *vals_2g40;
210#endif
211 const uint32_t *vals_2g20;
212 int ncmregs;
213 const uint16_t *cmregs;
214 const uint32_t *cmvals;
215 int nfastregs;
216 const uint16_t *fastregs;
217 const uint32_t *fastvals_5g20;
218#ifndef IEEE80211_NO_HT
219 const uint32_t *fastvals_5g40;
220#endif
221};
222
223struct athn_gain {
224 int nregs;
225 const uint16_t *regs;
226 const uint32_t *vals_5g;
227 const uint32_t *vals_2g;
228};
229
230struct athn_addac {
231 int nvals;
232 const uint32_t *vals;
233};
234
235struct athn_serdes {
236 int nvals;
237 const uint32_t *regs;
238 const uint32_t *vals;
239};
240
241/* Rx queue software indexes. */
242#define ATHN_QID_LP 0
243#define ATHN_QID_HP 1
244
245/* Tx queue software indexes. */
246#define ATHN_QID_AC_BE 0
247#define ATHN_QID_PSPOLL 1
248#define ATHN_QID_AC_BK 2
249#define ATHN_QID_AC_VI 3
250#define ATHN_QID_AC_VO 4
251#define ATHN_QID_UAPSD 5
252#define ATHN_QID_CAB 6
253#define ATHN_QID_BEACON 7
254#define ATHN_QID_COUNT 8
255
256/* Map Access Category to Tx queue Id. */
257static const uint8_t athn_ac2qid[WME_NUM_AC] = {
258 ATHN_QID_AC_BE, /* WME_AC_BE */
259 ATHN_QID_AC_BK, /* WME_AC_BK */
260 ATHN_QID_AC_VI, /* WME_AC_VI */
261 ATHN_QID_AC_VO /* WME_AC_VO */
262};
263
264static const uint8_t athn_5ghz_chans[] = {
265 /* UNII 1. */
266 36, 40, 44, 48,
267 /* UNII 2. */
268 52, 56, 60, 64,
269 /* Middle band. */
270 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140,
271 /* UNII 3. */
272 149, 153, 157, 161, 165
273};
274
275/* Number of data bits per OFDM symbol for MCS[0-15]. */
276/* See tables 20-29, 20-30, 20-33, 20-34. */
277static const uint16_t ar_mcs_ndbps[][2] = {
278 /* 20MHz 40MHz */
279 { 26, 54 }, /* MCS0 */
280 { 52, 108 }, /* MCS1 */
281 { 78, 162 }, /* MCS2 */
282 { 104, 216 }, /* MCS3 */
283 { 156, 324 }, /* MCS4 */
284 { 208, 432 }, /* MCS5 */
285 { 234, 486 }, /* MCS6 */
286 { 260, 540 }, /* MCS7 */
287 { 26, 108 }, /* MCS8 */
288 { 52, 216 }, /* MCS9 */
289 { 78, 324 }, /* MCS10 */
290 { 104, 432 }, /* MCS11 */
291 { 156, 648 }, /* MCS12 */
292 { 208, 864 }, /* MCS13 */
293 { 234, 972 }, /* MCS14 */
294 { 260, 1080 } /* MCS15 */
295};
296
297#define ATHN_POWER_OFDM6 0
298#define ATHN_POWER_OFDM9 1
299#define ATHN_POWER_OFDM12 2
300#define ATHN_POWER_OFDM18 3
301#define ATHN_POWER_OFDM24 4
302#define ATHN_POWER_OFDM36 5
303#define ATHN_POWER_OFDM48 6
304#define ATHN_POWER_OFDM54 7
305#define ATHN_POWER_CCK1_LP 8
306#define ATHN_POWER_CCK2_LP 9
307#define ATHN_POWER_CCK2_SP 10
308#define ATHN_POWER_CCK55_LP 11
309#define ATHN_POWER_CCK55_SP 12
310#define ATHN_POWER_CCK11_LP 13
311#define ATHN_POWER_CCK11_SP 14
312#define ATHN_POWER_XR 15
313#define ATHN_POWER_HT20(mcs) (16 + (mcs))
314#define ATHN_POWER_HT40(mcs) (40 + (mcs))
315#define ATHN_POWER_CCK_DUP 64
316#define ATHN_POWER_OFDM_DUP 65
317#define ATHN_POWER_CCK_EXT 66
318#define ATHN_POWER_OFDM_EXT 67
319#define ATHN_POWER_COUNT 68
320
321struct athn_node {
322 struct ieee80211_node ni;
323 struct ieee80211_amrr_node amn;
324 uint8_t ridx[IEEE80211_RATE_MAXSIZE];
325 uint8_t fallback[IEEE80211_RATE_MAXSIZE];
326 uint8_t sta_index;
327};
328
329/*
330 * Adaptive noise immunity state.
331 */
332#define ATHN_ANI_PERIOD 100
333#define ATHN_ANI_RSSI_THR_HIGH 40
334#define ATHN_ANI_RSSI_THR_LOW 7
335struct athn_ani {
336 uint8_t noise_immunity_level;
337 uint8_t spur_immunity_level;
338 uint8_t firstep_level;
339 uint8_t ofdm_weak_signal;
340 uint8_t cck_weak_signal;
341
342 uint32_t listen_time;
343
344 uint32_t ofdm_trig_high;
345 uint32_t ofdm_trig_low;
346
347 int32_t cck_trig_high;
348 int32_t cck_trig_low;
349
350 uint32_t ofdm_phy_err_base;
351 uint32_t cck_phy_err_base;
352 uint32_t ofdm_phy_err_count;
353 uint32_t cck_phy_err_count;
354
355 uint32_t cyccnt;
356 uint32_t txfcnt;
357 uint32_t rxfcnt;
358};
359
360struct athn_iq_cal {
361 uint32_t pwr_meas_i;
362 uint32_t pwr_meas_q;
363 int32_t iq_corr_meas;
364};
365
366struct athn_adc_cal {
367 uint32_t pwr_meas_odd_i;
368 uint32_t pwr_meas_even_i;
369 uint32_t pwr_meas_odd_q;
370 uint32_t pwr_meas_even_q;
371};
372
373struct athn_calib {
374 int nsamples;
375 struct athn_iq_cal iq[AR_MAX_CHAINS];
376 struct athn_adc_cal adc_gain[AR_MAX_CHAINS];
377 struct athn_adc_cal adc_dc_offset[AR_MAX_CHAINS];
378};
379
380#define ATHN_NF_CAL_HIST_MAX 5
381
382struct athn_softc;
383
384struct athn_ops {
385 /* Bus callbacks. */
386 uint32_t (*read)(struct athn_softc *, uint32_t);
387 void (*write)(struct athn_softc *, uint32_t, uint32_t);
388 void (*write_barrier)(struct athn_softc *);
389
390 void (*setup)(struct athn_softc *);
391 void (*set_txpower)(struct athn_softc *, struct ieee80211_channel *,
392 struct ieee80211_channel *);
393 void (*spur_mitigate)(struct athn_softc *,
394 struct ieee80211_channel *, struct ieee80211_channel *);
395 const struct ar_spur_chan *
396 (*get_spur_chans)(struct athn_softc *, int);
397 void (*init_from_rom)(struct athn_softc *,
398 struct ieee80211_channel *, struct ieee80211_channel *);
399 int (*set_synth)(struct athn_softc *, struct ieee80211_channel *,
400 struct ieee80211_channel *);
401 int (*read_rom_data)(struct athn_softc *, uint32_t, void *, int);
402 const uint8_t *
403 (*get_rom_template)(struct athn_softc *, uint8_t);
404 void (*swap_rom)(struct athn_softc *);
405 void (*olpc_init)(struct athn_softc *);
406 void (*olpc_temp_compensation)(struct athn_softc *);
407
408 /* GPIO callbacks. */
409 int (*gpio_read)(struct athn_softc *, int);
410 void (*gpio_write)(struct athn_softc *, int, int);
411 void (*gpio_config_input)(struct athn_softc *, int);
412 void (*gpio_config_output)(struct athn_softc *, int, int);
413 void (*rfsilent_init)(struct athn_softc *);
414
415 /* DMA callbacks. */
416 int (*dma_alloc)(struct athn_softc *);
417 void (*dma_free)(struct athn_softc *);
418 void (*rx_enable)(struct athn_softc *);
419 int (*intr)(struct athn_softc *);
420 int (*tx)(struct athn_softc *, struct mbuf *,
421 struct ieee80211_node *, int);
422
423 /* PHY callbacks. */
424 void (*set_rf_mode)(struct athn_softc *,
425 struct ieee80211_channel *);
426 int (*rf_bus_request)(struct athn_softc *);
427 void (*rf_bus_release)(struct athn_softc *);
428 void (*set_phy)(struct athn_softc *, struct ieee80211_channel *,
429 struct ieee80211_channel *);
430 void (*set_delta_slope)(struct athn_softc *,
431 struct ieee80211_channel *, struct ieee80211_channel *);
432 void (*enable_antenna_diversity)(struct athn_softc *);
433 void (*init_baseband)(struct athn_softc *);
434 void (*disable_phy)(struct athn_softc *);
435 void (*set_rxchains)(struct athn_softc *);
436 void (*noisefloor_calib)(struct athn_softc *);
437 void (*do_calib)(struct athn_softc *);
438 void (*next_calib)(struct athn_softc *);
439 void (*hw_init)(struct athn_softc *, struct ieee80211_channel *,
440 struct ieee80211_channel *);
441 void (*get_paprd_masks)(struct athn_softc *sc,
442 struct ieee80211_channel *, uint32_t *, uint32_t *);
443
444 /* ANI callbacks. */
445 void (*set_noise_immunity_level)(struct athn_softc *, int);
446 void (*enable_ofdm_weak_signal)(struct athn_softc *);
447 void (*disable_ofdm_weak_signal)(struct athn_softc *);
448 void (*set_cck_weak_signal)(struct athn_softc *, int);
449 void (*set_firstep_level)(struct athn_softc *, int);
450 void (*set_spur_immunity_level)(struct athn_softc *, int);
451};
452
453struct athn_softc {
454 device_t sc_dev;
455 device_suspensor_t sc_suspensor;
456 pmf_qual_t sc_qual;
457 struct ieee80211com sc_ic;
458 struct ethercom sc_ec;
459#define sc_if sc_ec.ec_if
460
461#if 0
462 int (*sc_enable)(struct athn_softc *);
463 void (*sc_disable)(struct athn_softc *);
464 void (*sc_power)(struct athn_softc *, int);
465#endif
466 void (*sc_disable_aspm)(struct athn_softc *);
467 void (*sc_enable_extsynch)(
468 struct athn_softc *);
469
470 int (*sc_newstate)(struct ieee80211com *,
471 enum ieee80211_state, int);
472
473 bus_dma_tag_t sc_dmat;
474
475 callout_t sc_scan_to;
476 callout_t sc_calib_to;
477 struct ieee80211_amrr sc_amrr;
478
479 u_int sc_flags;
480#define ATHN_FLAG_PCIE (1 << 0)
481#define ATHN_FLAG_USB (1 << 1)
482#define ATHN_FLAG_OLPC (1 << 2)
483#define ATHN_FLAG_PAPRD (1 << 3)
484#define ATHN_FLAG_FAST_PLL_CLOCK (1 << 4)
485#define ATHN_FLAG_RFSILENT (1 << 5)
486#define ATHN_FLAG_RFSILENT_REVERSED (1 << 6)
487#define ATHN_FLAG_BTCOEX2WIRE (1 << 7)
488#define ATHN_FLAG_BTCOEX3WIRE (1 << 8)
489/* Shortcut. */
490#define ATHN_FLAG_BTCOEX (ATHN_FLAG_BTCOEX2WIRE | ATHN_FLAG_BTCOEX3WIRE)
491#define ATHN_FLAG_11A (1 << 9)
492#define ATHN_FLAG_11G (1 << 10)
493#define ATHN_FLAG_11N (1 << 11)
494#define ATHN_FLAG_AN_TOP2_FIXUP (1 << 12)
495#define ATHN_FLAG_NON_ENTERPRISE (1 << 13)
496#define ATHN_FLAG_3TREDUCE_CHAIN (1 << 14)
497
498 uint8_t sc_ngpiopins;
499 int sc_led_pin;
500 int sc_rfsilent_pin;
501 int sc_led_state;
502 uint32_t sc_isync;
503 uint32_t sc_imask;
504
505 uint16_t sc_mac_ver;
506 uint8_t sc_mac_rev;
507 uint8_t sc_rf_rev;
508 uint16_t sc_eep_rev;
509
510 uint8_t sc_txchainmask;
511 uint8_t sc_rxchainmask;
512 uint8_t sc_ntxchains;
513 uint8_t sc_nrxchains;
514
515 uint8_t sc_sup_calib_mask;
516 uint8_t sc_cur_calib_mask;
517#define ATHN_CAL_IQ (1 << 0)
518#define ATHN_CAL_ADC_GAIN (1 << 1)
519#define ATHN_CAL_ADC_DC (1 << 2)
520#define ATHN_CAL_TEMP (1 << 3)
521
522 struct ieee80211_channel *sc_curchan;
523 struct ieee80211_channel *sc_curchanext;
524
525 /* Open Loop Power Control. */
526 int8_t sc_tx_gain_tbl[AR9280_TX_GAIN_TABLE_SIZE];
527 int8_t sc_pdadc;
528 int8_t sc_tcomp;
529 int sc_olpc_ticks;
530
531 /* PA predistortion. */
532 uint16_t sc_gain1[AR_MAX_CHAINS];
533 uint32_t sc_txgain[AR9003_TX_GAIN_TABLE_SIZE];
534 int16_t sc_pa_in[AR_MAX_CHAINS]
535 [AR9003_PAPRD_MEM_TAB_SIZE];
536 int16_t sc_angle[AR_MAX_CHAINS]
537 [AR9003_PAPRD_MEM_TAB_SIZE];
538 int32_t sc_trainpow;
539 uint8_t sc_paprd_curchain;
540
541 uint32_t sc_rwbuf[64];
542
543 size_t sc_kc_entries;
544
545 void *sc_eep;
546 const void *sc_eep_def;
547 uint32_t sc_eep_base;
548 uint32_t sc_eep_size;
549
550 struct athn_rxq sc_rxq[2];
551 struct athn_txq sc_txq[31];
552
553 void *sc_descs;
554 bus_dmamap_t sc_map;
555 bus_dma_segment_t sc_seg;
556 SIMPLEQ_HEAD(, athn_tx_buf) sc_txbufs;
557 struct athn_tx_buf *sc_bcnbuf;
558 struct athn_tx_buf sc_txpool[ATHN_NTXBUFS];
559
560 bus_dmamap_t sc_txsmap;
561 bus_dma_segment_t sc_txsseg;
562 void *sc_txsring;
563 int sc_txscur;
564
565 int sc_if_flags;
566 int sc_tx_timer;
567
568 const struct athn_ini *sc_ini;
569 const struct athn_gain *sc_rx_gain;
570 const struct athn_gain *sc_tx_gain;
571 const struct athn_addac *sc_addac;
572 const struct athn_serdes *sc_serdes;
573 uint32_t sc_workaround;
574 uint32_t sc_obs_off;
575 uint32_t sc_gpio_input_en_off;
576
577 struct athn_ops sc_ops;
578
579 int sc_fixed_ridx;
580
581 int16_t sc_cca_min_2g;
582 int16_t sc_cca_max_2g;
583 int16_t sc_cca_min_5g;
584 int16_t sc_cca_max_5g;
585 int16_t sc_def_nf;
586 struct {
587 int16_t nf[AR_MAX_CHAINS];
588 int16_t nf_ext[AR_MAX_CHAINS];
589 } sc_nf_hist[ATHN_NF_CAL_HIST_MAX];
590 int sc_nf_hist_cur;
591 int16_t sc_nf_priv[AR_MAX_CHAINS];
592 int16_t sc_nf_ext_priv[AR_MAX_CHAINS];
593 int sc_pa_calib_ticks;
594
595 struct athn_calib sc_calib;
596 struct athn_ani sc_ani;
597
598 struct bpf_if * sc_drvbpf;
599
600 union {
601 struct athn_rx_radiotap_header th;
602 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN];
603 } sc_rxtapu;
604#define sc_rxtap sc_rxtapu.th
605 int sc_rxtap_len;
606
607 union {
608 struct athn_tx_radiotap_header th;
609 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN];
610 } sc_txtapu;
611#define sc_txtap sc_txtapu.th
612 int sc_txtap_len;
613
614 /*
615 * Attach overrides. Set before calling athn_attach().
616 */
617 int sc_max_aid;
618 int (*sc_media_change)(struct ifnet *);
619};
620
621int athn_attach(struct athn_softc *);
622void athn_detach(struct athn_softc *);
623void athn_suspend(struct athn_softc *);
624bool athn_resume(struct athn_softc *);
625int athn_intr(void *);
626
627/* used by if_athn_usb.c */
628void athn_btcoex_init(struct athn_softc *);
629int athn_hw_reset(struct athn_softc *, struct ieee80211_channel *,
630 struct ieee80211_channel *, int);
631void athn_init_pll(struct athn_softc *, const struct ieee80211_channel *);
632void athn_led_init(struct athn_softc *);
633int athn_reset(struct athn_softc *, int);
634void athn_reset_key(struct athn_softc *, int);
635void athn_rx_start(struct athn_softc *);
636void athn_set_bss(struct athn_softc *, struct ieee80211_node *);
637int athn_set_chan(struct athn_softc *, struct ieee80211_channel *,
638 struct ieee80211_channel *);
639void athn_set_hostap_timers(struct athn_softc *);
640void athn_set_led(struct athn_softc *, int);
641void athn_set_opmode(struct athn_softc *);
642int athn_set_power_awake(struct athn_softc *);
643void athn_set_power_sleep(struct athn_softc *);
644void athn_set_rxfilter(struct athn_softc *, uint32_t);
645void athn_set_sta_timers(struct athn_softc *);
646void athn_updateslot(struct ifnet *);
647
648#ifdef notyet_edca
649void athn_updateedca(struct ieee80211com *);
650#endif
651#ifdef notyet
652void athn_delete_key(struct ieee80211com *, struct ieee80211_node *,
653 struct ieee80211_key *);
654int athn_set_key(struct ieee80211com *, struct ieee80211_node *,
655 struct ieee80211_key *);
656#endif /* notyet */
657
658/* used by ar9285.c */
659uint8_t athn_chan2fbin(struct ieee80211_channel *);
660void athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, int *);
661
662/* used by arn5008.c and arn9003.c */
663void athn_config_nonpcie(struct athn_softc *);
664void athn_config_pcie(struct athn_softc *);
665void athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *);
666void athn_inc_tx_trigger_level(struct athn_softc *);
667void athn_stop(struct ifnet *, int);
668void athn_stop_tx_dma(struct athn_softc *, int);
669int athn_tx_pending(struct athn_softc *, int);
670int athn_txtime(struct athn_softc *, int, int, u_int);
671
672/* used by arn5008.c, arn9003.c, arn9287.c, and arn9380.c */
673int athn_interpolate(int, int, int, int, int);
674
675#endif /* _ATHNVAR_H_ */
676