1/* $NetBSD: wdcvar.h,v 1.97 2013/02/03 20:13:28 jakllsch Exp $ */
2
3/*-
4 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _DEV_IC_WDCVAR_H_
33#define _DEV_IC_WDCVAR_H_
34
35#include <sys/callout.h>
36
37#include <dev/ata/ataconf.h>
38#include <dev/ic/wdcreg.h>
39
40#define WAITTIME (10 * hz) /* time to wait for a completion */
41 /* this is a lot for hard drives, but not for cdroms */
42
43#define WDC_NREG 8 /* number of command registers */
44#define WDC_NSHADOWREG 2 /* number of command "shadow" registers */
45
46#define WDC_MAXDRIVES 2 /* absolute max number of drives per channel */
47
48struct wdc_regs {
49 /* Our registers */
50 bus_space_tag_t cmd_iot;
51 bus_space_handle_t cmd_baseioh;
52 bus_size_t cmd_ios;
53 bus_space_handle_t cmd_iohs[WDC_NREG+WDC_NSHADOWREG];
54 bus_space_tag_t ctl_iot;
55 bus_space_handle_t ctl_ioh;
56 bus_size_t ctl_ios;
57
58 /* data32{iot,ioh} are only used for 32-bit data xfers */
59 bus_space_tag_t data32iot;
60 bus_space_handle_t data32ioh;
61
62 /* SATA native registers */
63 bus_space_tag_t sata_iot;
64 bus_space_handle_t sata_baseioh;
65 bus_space_handle_t sata_control;
66 bus_space_handle_t sata_status;
67 bus_space_handle_t sata_error;
68
69};
70
71/*
72 * Per-controller data
73 */
74struct wdc_softc {
75 struct atac_softc sc_atac; /* generic ATA controller info */
76
77 struct wdc_regs *regs; /* register array (per-channel) */
78
79 int wdc_maxdrives; /* max number of drives per channel */
80
81 int cap; /* controller capabilities */
82#define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */
83#define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */
84#define WDC_CAPABILITY_WIDEREGS 0x0400 /* ctrl has wide (16bit) registers */
85#define WDC_CAPABILITY_NO_AUXCTL 0x0800 /* ctrl has no aux control registers */
86
87#if NATA_DMA || NATA_PIOBM
88 /* if WDC_CAPABILITY_DMA set in 'cap' */
89 void *dma_arg;
90 int (*dma_init)(void *, int, int, void *, size_t, int);
91 void (*dma_start)(void *, int, int);
92 int (*dma_finish)(void *, int, int, int);
93#if NATA_PIOBM
94 void (*piobm_start)(void *, int, int, int, int, int);
95 void (*piobm_done)(void *, int, int);
96#endif
97/* flags passed to dma_init */
98#define WDC_DMA_READ 0x01
99#define WDC_DMA_IRQW 0x02
100#define WDC_DMA_LBA48 0x04
101#define WDC_DMA_PIOBM_ATA 0x08
102#define WDC_DMA_PIOBM_ATAPI 0x10
103#if NATA_PIOBM
104/* flags passed to piobm_start */
105#define WDC_PIOBM_XFER_IRQ 0x01
106#endif
107
108/* values passed to dma_finish */
109#define WDC_DMAEND_END 0 /* check for proper end of a DMA xfer */
110#define WDC_DMAEND_ABRT 1 /* abort a DMA xfer, verbose */
111#define WDC_DMAEND_ABRT_QUIET 2 /* abort a DMA xfer, quiet */
112
113 int dma_status; /* status returned from dma_finish() */
114#define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */
115#define WDC_DMAST_ERR 0x02 /* DMA error */
116#define WDC_DMAST_UNDER 0x04 /* DMA underrun */
117#endif /* NATA_DMA || NATA_PIOBM */
118
119 /* Optional callback to select drive. */
120 void (*select)(struct ata_channel *,int);
121
122 /* Optional callback to ack IRQ. */
123 void (*irqack)(struct ata_channel *);
124
125 /* Optional callback to perform a bus reset */
126 void (*reset)(struct ata_channel *, int);
127
128 /* overridden if the backend has a different data transfer method */
129 void (*datain_pio)(struct ata_channel *, int, void *, size_t);
130 void (*dataout_pio)(struct ata_channel *, int, void *, size_t);
131};
132
133/* Given an ata_channel, get the wdc_softc. */
134#define CHAN_TO_WDC(chp) ((struct wdc_softc *)(chp)->ch_atac)
135
136/* Given an ata_channel, get the wdc_regs. */
137#define CHAN_TO_WDC_REGS(chp) (&CHAN_TO_WDC(chp)->regs[(chp)->ch_channel])
138
139/*
140 * Public functions which can be called by ATA or ATAPI specific parts,
141 * or bus-specific backends.
142 */
143
144void wdc_allocate_regs(struct wdc_softc *);
145void wdc_init_shadow_regs(struct ata_channel *);
146
147int wdcprobe(struct ata_channel *);
148void wdcattach(struct ata_channel *);
149int wdcdetach(device_t, int);
150void wdc_childdetached(device_t, device_t);
151int wdcintr(void *);
152
153void wdc_sataprobe(struct ata_channel *);
154void wdc_drvprobe(struct ata_channel *);
155
156void wdcrestart(void*);
157
158int wdcwait(struct ata_channel *, int, int, int, int);
159#define WDCWAIT_OK 0 /* we have what we asked */
160#define WDCWAIT_TOUT -1 /* timed out */
161#define WDCWAIT_THR 1 /* return, the kernel thread has been awakened */
162
163void wdcbit_bucket(struct ata_channel *, int);
164
165int wdc_dmawait(struct ata_channel *, struct ata_xfer *, int);
166void wdccommand(struct ata_channel *, u_int8_t, u_int8_t, u_int16_t,
167 u_int8_t, u_int8_t, u_int8_t, u_int8_t);
168void wdccommandext(struct ata_channel *, u_int8_t, u_int8_t, u_int64_t,
169 u_int16_t, u_int16_t, u_int8_t);
170void wdccommandshort(struct ata_channel *, int, int);
171void wdctimeout(void *arg);
172void wdc_reset_drive(struct ata_drive_datas *, int, uint32_t *);
173void wdc_reset_channel(struct ata_channel *, int);
174void wdc_do_reset(struct ata_channel *, int);
175
176int wdc_exec_command(struct ata_drive_datas *, struct ata_command*);
177
178/*
179 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write
180 * command is aborted.
181 */
182#define wdc_wait_for_drq(chp, timeout, flags) \
183 wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout), (flags))
184#define wdc_wait_for_unbusy(chp, timeout, flags) \
185 wdcwait((chp), 0, 0, (timeout), (flags))
186#define wdc_wait_for_ready(chp, timeout, flags) \
187 wdcwait((chp), WDCS_DRDY, WDCS_DRDY, (timeout), (flags))
188
189/* ATA/ATAPI specs says a device can take 31s to reset */
190#define WDC_RESET_WAIT 31000
191
192void wdc_atapibus_attach(struct atabus_softc *);
193
194#endif /* _DEV_IC_WDCVAR_H_ */
195