1 | /* $NetBSD: wdc.c,v 1.282 2016/08/17 22:03:02 skrll Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
9 | * 1. Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * 2. Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
14 | * |
15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
18 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
22 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
25 | */ |
26 | |
27 | /*- |
28 | * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. |
29 | * All rights reserved. |
30 | * |
31 | * This code is derived from software contributed to The NetBSD Foundation |
32 | * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. |
33 | * |
34 | * Redistribution and use in source and binary forms, with or without |
35 | * modification, are permitted provided that the following conditions |
36 | * are met: |
37 | * 1. Redistributions of source code must retain the above copyright |
38 | * notice, this list of conditions and the following disclaimer. |
39 | * 2. Redistributions in binary form must reproduce the above copyright |
40 | * notice, this list of conditions and the following disclaimer in the |
41 | * documentation and/or other materials provided with the distribution. |
42 | * |
43 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
44 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
45 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
46 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
47 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
48 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
49 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
50 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
51 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
52 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
53 | * POSSIBILITY OF SUCH DAMAGE. |
54 | */ |
55 | |
56 | /* |
57 | * CODE UNTESTED IN THE CURRENT REVISION: |
58 | */ |
59 | |
60 | #include <sys/cdefs.h> |
61 | __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.282 2016/08/17 22:03:02 skrll Exp $" ); |
62 | |
63 | #include "opt_ata.h" |
64 | #include "opt_wdc.h" |
65 | |
66 | #include <sys/param.h> |
67 | #include <sys/systm.h> |
68 | #include <sys/kernel.h> |
69 | #include <sys/conf.h> |
70 | #include <sys/buf.h> |
71 | #include <sys/device.h> |
72 | #include <sys/malloc.h> |
73 | #include <sys/syslog.h> |
74 | #include <sys/proc.h> |
75 | |
76 | #include <sys/intr.h> |
77 | #include <sys/bus.h> |
78 | |
79 | #ifndef __BUS_SPACE_HAS_STREAM_METHODS |
80 | #define bus_space_write_multi_stream_2 bus_space_write_multi_2 |
81 | #define bus_space_write_multi_stream_4 bus_space_write_multi_4 |
82 | #define bus_space_read_multi_stream_2 bus_space_read_multi_2 |
83 | #define bus_space_read_multi_stream_4 bus_space_read_multi_4 |
84 | #define bus_space_read_stream_2 bus_space_read_2 |
85 | #define bus_space_read_stream_4 bus_space_read_4 |
86 | #define bus_space_write_stream_2 bus_space_write_2 |
87 | #define bus_space_write_stream_4 bus_space_write_4 |
88 | #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ |
89 | |
90 | #include <dev/ata/atavar.h> |
91 | #include <dev/ata/atareg.h> |
92 | #include <dev/ata/satareg.h> |
93 | #include <dev/ata/satavar.h> |
94 | #include <dev/ic/wdcreg.h> |
95 | #include <dev/ic/wdcvar.h> |
96 | |
97 | #include "locators.h" |
98 | |
99 | #include "atapibus.h" |
100 | #include "wd.h" |
101 | #include "sata.h" |
102 | |
103 | #define WDCDELAY 100 /* 100 microseconds */ |
104 | #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) |
105 | #if 0 |
106 | /* If you enable this, it will report any delays more than WDCDELAY * N long. */ |
107 | #define WDCNDELAY_DEBUG 50 |
108 | #endif |
109 | |
110 | /* When polling wait that much and then tsleep for 1/hz seconds */ |
111 | #define WDCDELAY_POLL 1 /* ms */ |
112 | |
113 | /* timeout for the control commands */ |
114 | #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ |
115 | |
116 | /* |
117 | * timeout when waiting for BSY to deassert when probing. |
118 | * set to 5s. From the standards this could be up to 31, but we can't |
119 | * wait that much at boot time, and 5s seems to be enough. |
120 | */ |
121 | #define WDC_PROBE_WAIT 5 |
122 | |
123 | |
124 | #if NWD > 0 |
125 | extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ |
126 | #else |
127 | /* A fake one, the autoconfig will print "wd at foo ... not configured */ |
128 | const struct ata_bustype wdc_ata_bustype = { |
129 | SCSIPI_BUSTYPE_ATA, |
130 | NULL, /* wdc_ata_bio */ |
131 | NULL, /* wdc_reset_drive */ |
132 | wdc_reset_channel, |
133 | wdc_exec_command, |
134 | NULL, /* ata_get_params */ |
135 | NULL, /* wdc_ata_addref */ |
136 | NULL, /* wdc_ata_delref */ |
137 | NULL /* ata_kill_pending */ |
138 | }; |
139 | #endif |
140 | |
141 | /* Flags to wdcreset(). */ |
142 | #define RESET_POLL 1 |
143 | #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ |
144 | |
145 | static int wdcprobe1(struct ata_channel *, int); |
146 | static int wdcreset(struct ata_channel *, int); |
147 | static void __wdcerror(struct ata_channel *, const char *); |
148 | static int __wdcwait_reset(struct ata_channel *, int, int); |
149 | static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); |
150 | static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); |
151 | static void __wdccommand_kill_xfer(struct ata_channel *, |
152 | struct ata_xfer *, int); |
153 | static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); |
154 | static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); |
155 | static int __wdcwait(struct ata_channel *, int, int, int); |
156 | |
157 | static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); |
158 | static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); |
159 | #define DEBUG_INTR 0x01 |
160 | #define DEBUG_XFERS 0x02 |
161 | #define DEBUG_STATUS 0x04 |
162 | #define DEBUG_FUNCS 0x08 |
163 | #define DEBUG_PROBE 0x10 |
164 | #define DEBUG_DETACH 0x20 |
165 | #define DEBUG_DELAY 0x40 |
166 | #ifdef ATADEBUG |
167 | extern int atadebug_mask; /* init'ed in ata.c */ |
168 | int wdc_nxfer = 0; |
169 | #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args |
170 | #else |
171 | #define ATADEBUG_PRINT(args, level) |
172 | #endif |
173 | |
174 | /* |
175 | * Initialize the "shadow register" handles for a standard wdc controller. |
176 | */ |
177 | void |
178 | wdc_init_shadow_regs(struct ata_channel *chp) |
179 | { |
180 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); |
181 | |
182 | wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; |
183 | wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; |
184 | } |
185 | |
186 | /* |
187 | * Allocate a wdc_regs array, based on the number of channels. |
188 | */ |
189 | void |
190 | wdc_allocate_regs(struct wdc_softc *wdc) |
191 | { |
192 | |
193 | wdc->regs = malloc(wdc->sc_atac.atac_nchannels * |
194 | sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); |
195 | } |
196 | |
197 | #if NSATA > 0 |
198 | /* |
199 | * probe drives on SATA controllers with standard SATA registers: |
200 | * bring the PHYs online, read the drive signature and set drive flags |
201 | * appropriately. |
202 | */ |
203 | void |
204 | wdc_sataprobe(struct ata_channel *chp) |
205 | { |
206 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); |
207 | uint8_t st = 0, sc __unused, sn __unused, cl, ch; |
208 | int i, s; |
209 | |
210 | KASSERT(chp->ch_ndrives == 0 || chp->ch_drive != NULL); |
211 | |
212 | /* reset the PHY and bring online */ |
213 | switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, |
214 | wdr->sata_status, AT_WAIT)) { |
215 | case SStatus_DET_DEV: |
216 | /* wait 5s for BSY to clear */ |
217 | for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { |
218 | bus_space_write_1(wdr->cmd_iot, |
219 | wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); |
220 | delay(10); /* 400ns delay */ |
221 | st = bus_space_read_1(wdr->cmd_iot, |
222 | wdr->cmd_iohs[wd_status], 0); |
223 | if ((st & WDCS_BSY) == 0) |
224 | break; |
225 | tsleep(&chp, PRIBIO, "sataprb" , 1); |
226 | } |
227 | if (i == WDC_PROBE_WAIT * hz) |
228 | aprint_error_dev(chp->ch_atac->atac_dev, |
229 | "BSY never cleared, status 0x%02x\n" , st); |
230 | sc = bus_space_read_1(wdr->cmd_iot, |
231 | wdr->cmd_iohs[wd_seccnt], 0); |
232 | sn = bus_space_read_1(wdr->cmd_iot, |
233 | wdr->cmd_iohs[wd_sector], 0); |
234 | cl = bus_space_read_1(wdr->cmd_iot, |
235 | wdr->cmd_iohs[wd_cyl_lo], 0); |
236 | ch = bus_space_read_1(wdr->cmd_iot, |
237 | wdr->cmd_iohs[wd_cyl_hi], 0); |
238 | ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " |
239 | "cl=0x%x ch=0x%x\n" , |
240 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, |
241 | sc, sn, cl, ch), DEBUG_PROBE); |
242 | if (atabus_alloc_drives(chp, 1) != 0) |
243 | return; |
244 | /* |
245 | * sc and sn are supposed to be 0x1 for ATAPI, but in some |
246 | * cases we get wrong values here, so ignore it. |
247 | */ |
248 | s = splbio(); |
249 | if (cl == 0x14 && ch == 0xeb) |
250 | chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; |
251 | else |
252 | chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; |
253 | splx(s); |
254 | |
255 | /* |
256 | * issue a reset in case only the interface part of the drive |
257 | * is up |
258 | */ |
259 | if (wdcreset(chp, RESET_SLEEP) != 0) |
260 | chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; |
261 | break; |
262 | |
263 | default: |
264 | break; |
265 | } |
266 | } |
267 | #endif /* NSATA > 0 */ |
268 | |
269 | |
270 | /* Test to see controller with at last one attached drive is there. |
271 | * Returns a bit for each possible drive found (0x01 for drive 0, |
272 | * 0x02 for drive 1). |
273 | * Logic: |
274 | * - If a status register is at 0xff, assume there is no drive here |
275 | * (ISA has pull-up resistors). Similarly if the status register has |
276 | * the value we last wrote to the bus (for IDE interfaces without pullups). |
277 | * If no drive at all -> return. |
278 | * - reset the controller, wait for it to complete (may take up to 31s !). |
279 | * If timeout -> return. |
280 | * - test ATA/ATAPI signatures. If at last one drive found -> return. |
281 | * - try an ATA command on the master. |
282 | */ |
283 | |
284 | void |
285 | wdc_drvprobe(struct ata_channel *chp) |
286 | { |
287 | struct ataparams params; /* XXX: large struct */ |
288 | struct atac_softc *atac = chp->ch_atac; |
289 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
290 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
291 | u_int8_t st0 = 0, st1 = 0; |
292 | int i, j, error, s; |
293 | |
294 | if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) |
295 | return; |
296 | if (wdcprobe1(chp, 0) == 0) { |
297 | /* No drives, abort the attach here. */ |
298 | atabus_free_drives(chp); |
299 | return; |
300 | } |
301 | |
302 | s = splbio(); |
303 | /* for ATA/OLD drives, wait for DRDY, 3s timeout */ |
304 | for (i = 0; i < mstohz(3000); i++) { |
305 | /* |
306 | * select drive 1 first, so that master is selected on |
307 | * exit from the loop |
308 | */ |
309 | if (chp->ch_ndrives > 1 && |
310 | chp->ch_drive[1].drive_type == ATA_DRIVET_ATA) { |
311 | if (wdc->select) |
312 | wdc->select(chp,1); |
313 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
314 | 0, WDSD_IBM | 0x10); |
315 | delay(10); /* 400ns delay */ |
316 | st1 = bus_space_read_1(wdr->cmd_iot, |
317 | wdr->cmd_iohs[wd_status], 0); |
318 | } |
319 | if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATA) { |
320 | if (wdc->select) |
321 | wdc->select(chp,0); |
322 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
323 | 0, WDSD_IBM); |
324 | delay(10); /* 400ns delay */ |
325 | st0 = bus_space_read_1(wdr->cmd_iot, |
326 | wdr->cmd_iohs[wd_status], 0); |
327 | } |
328 | |
329 | |
330 | if ((chp->ch_drive[0].drive_type != ATA_DRIVET_ATA || |
331 | (st0 & WDCS_DRDY)) && |
332 | (chp->ch_ndrives < 2 || |
333 | chp->ch_drive[1].drive_type != ATA_DRIVET_ATA || |
334 | (st1 & WDCS_DRDY))) |
335 | break; |
336 | #ifdef WDC_NO_IDS |
337 | /* cannot tsleep here (can't enable IPL_BIO interrups), |
338 | * delay instead |
339 | */ |
340 | delay(1000000 / hz); |
341 | #else |
342 | tsleep(¶ms, PRIBIO, "atadrdy" , 1); |
343 | #endif |
344 | } |
345 | if ((st0 & WDCS_DRDY) == 0 && |
346 | chp->ch_drive[0].drive_type != ATA_DRIVET_ATAPI) |
347 | chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; |
348 | if (chp->ch_ndrives > 1 && (st1 & WDCS_DRDY) == 0 && |
349 | chp->ch_drive[1].drive_type != ATA_DRIVET_ATAPI) |
350 | chp->ch_drive[1].drive_type = ATA_DRIVET_NONE; |
351 | splx(s); |
352 | |
353 | ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n" , |
354 | device_xname(atac->atac_dev), |
355 | chp->ch_channel, st0, st1), DEBUG_PROBE); |
356 | |
357 | /* Wait a bit, some devices are weird just after a reset. */ |
358 | delay(5000); |
359 | |
360 | for (i = 0; i < chp->ch_ndrives; i++) { |
361 | #if NATA_DMA |
362 | /* |
363 | * Init error counter so that an error within the first xfers |
364 | * will trigger a downgrade |
365 | */ |
366 | chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; |
367 | #endif |
368 | |
369 | /* If controller can't do 16bit flag the drives as 32bit */ |
370 | if ((atac->atac_cap & |
371 | (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { |
372 | s = splbio(); |
373 | chp->ch_drive[i].drive_flags |= ATA_DRIVE_CAP32; |
374 | splx(s); |
375 | } |
376 | if (chp->ch_drive[i].drive_type == ATA_DRIVET_NONE) |
377 | continue; |
378 | |
379 | /* Shortcut in case we've been shutdown */ |
380 | if (chp->ch_flags & ATACH_SHUTDOWN) |
381 | return; |
382 | |
383 | /* |
384 | * Issue an identify, to try to detect ghosts. |
385 | * Note that we can't use interrupts here, because if there |
386 | * is no devices, we will get a command aborted without |
387 | * interrupts. |
388 | */ |
389 | error = ata_get_params(&chp->ch_drive[i], |
390 | AT_WAIT | AT_POLL, ¶ms); |
391 | if (error != CMD_OK) { |
392 | tsleep(¶ms, PRIBIO, "atacnf" , mstohz(1000)); |
393 | |
394 | /* Shortcut in case we've been shutdown */ |
395 | if (chp->ch_flags & ATACH_SHUTDOWN) |
396 | return; |
397 | |
398 | error = ata_get_params(&chp->ch_drive[i], |
399 | AT_WAIT | AT_POLL, ¶ms); |
400 | } |
401 | if (error != CMD_OK) { |
402 | ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n" , |
403 | device_xname(atac->atac_dev), |
404 | chp->ch_channel, i, error), DEBUG_PROBE); |
405 | s = splbio(); |
406 | if (chp->ch_drive[i].drive_type != ATA_DRIVET_ATA || |
407 | (wdc->cap & WDC_CAPABILITY_PREATA) == 0) { |
408 | chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; |
409 | splx(s); |
410 | continue; |
411 | } |
412 | splx(s); |
413 | /* |
414 | * Pre-ATA drive ? |
415 | * Test registers writability (Error register not |
416 | * writable, but cyllo is), then try an ATA command. |
417 | */ |
418 | if (wdc->select) |
419 | wdc->select(chp,i); |
420 | bus_space_write_1(wdr->cmd_iot, |
421 | wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); |
422 | delay(10); /* 400ns delay */ |
423 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], |
424 | 0, 0x58); |
425 | bus_space_write_1(wdr->cmd_iot, |
426 | wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); |
427 | if (bus_space_read_1(wdr->cmd_iot, |
428 | wdr->cmd_iohs[wd_error], 0) == 0x58 || |
429 | bus_space_read_1(wdr->cmd_iot, |
430 | wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { |
431 | ATADEBUG_PRINT(("%s:%d:%d: register " |
432 | "writability failed\n" , |
433 | device_xname(atac->atac_dev), |
434 | chp->ch_channel, i), DEBUG_PROBE); |
435 | s = splbio(); |
436 | chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; |
437 | splx(s); |
438 | continue; |
439 | } |
440 | if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { |
441 | ATADEBUG_PRINT(("%s:%d:%d: not ready\n" , |
442 | device_xname(atac->atac_dev), |
443 | chp->ch_channel, i), DEBUG_PROBE); |
444 | s = splbio(); |
445 | chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; |
446 | splx(s); |
447 | continue; |
448 | } |
449 | bus_space_write_1(wdr->cmd_iot, |
450 | wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); |
451 | delay(10); /* 400ns delay */ |
452 | if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { |
453 | ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n" , |
454 | device_xname(atac->atac_dev), |
455 | chp->ch_channel, i), DEBUG_PROBE); |
456 | s = splbio(); |
457 | chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; |
458 | splx(s); |
459 | } else { |
460 | s = splbio(); |
461 | for (j = 0; j < chp->ch_ndrives; j++) { |
462 | if (chp->ch_drive[i].drive_type != |
463 | ATA_DRIVET_NONE) { |
464 | chp->ch_drive[j].drive_type = |
465 | ATA_DRIVET_OLD; |
466 | } |
467 | } |
468 | splx(s); |
469 | } |
470 | } |
471 | } |
472 | } |
473 | |
474 | int |
475 | wdcprobe(struct ata_channel *chp) |
476 | { |
477 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
478 | /* default reset method */ |
479 | if (wdc->reset == NULL) |
480 | wdc->reset = wdc_do_reset; |
481 | |
482 | return (wdcprobe1(chp, 1)); |
483 | } |
484 | |
485 | static int |
486 | wdcprobe1(struct ata_channel *chp, int poll) |
487 | { |
488 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
489 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
490 | u_int8_t st0 = 0, st1 = 0, sc __unused, sn __unused, cl, ch; |
491 | u_int8_t ret_value = 0x03; |
492 | u_int8_t drive; |
493 | int s; |
494 | /* XXX if poll, wdc_probe_count is 0. */ |
495 | int wdc_probe_count = |
496 | poll ? (WDC_PROBE_WAIT / WDCDELAY) |
497 | : (WDC_PROBE_WAIT * hz); |
498 | |
499 | /* |
500 | * Sanity check to see if the wdc channel responds at all. |
501 | */ |
502 | |
503 | s = splbio(); |
504 | if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { |
505 | while (wdc_probe_count-- > 0) { |
506 | if (wdc->select) |
507 | wdc->select(chp,0); |
508 | |
509 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
510 | 0, WDSD_IBM); |
511 | delay(10); /* 400ns delay */ |
512 | st0 = bus_space_read_1(wdr->cmd_iot, |
513 | wdr->cmd_iohs[wd_status], 0); |
514 | |
515 | if (wdc->select) |
516 | wdc->select(chp,1); |
517 | |
518 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
519 | 0, WDSD_IBM | 0x10); |
520 | delay(10); /* 400ns delay */ |
521 | st1 = bus_space_read_1(wdr->cmd_iot, |
522 | wdr->cmd_iohs[wd_status], 0); |
523 | if ((st0 & WDCS_BSY) == 0) |
524 | break; |
525 | } |
526 | |
527 | ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n" , |
528 | __func__, chp->ch_channel, st0, st1), DEBUG_PROBE); |
529 | |
530 | if (st0 == 0xff || st0 == WDSD_IBM) |
531 | ret_value &= ~0x01; |
532 | if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) |
533 | ret_value &= ~0x02; |
534 | /* Register writability test, drive 0. */ |
535 | if (ret_value & 0x01) { |
536 | if (wdc->select) |
537 | wdc->select(chp,0); |
538 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
539 | 0, WDSD_IBM); |
540 | bus_space_write_1(wdr->cmd_iot, |
541 | wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); |
542 | cl = bus_space_read_1(wdr->cmd_iot, |
543 | wdr->cmd_iohs[wd_cyl_lo], 0); |
544 | if (cl != 0x02) { |
545 | ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " |
546 | "got 0x%x != 0x02\n" , |
547 | __func__, chp->ch_channel, cl), |
548 | DEBUG_PROBE); |
549 | ret_value &= ~0x01; |
550 | } |
551 | bus_space_write_1(wdr->cmd_iot, |
552 | wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); |
553 | cl = bus_space_read_1(wdr->cmd_iot, |
554 | wdr->cmd_iohs[wd_cyl_lo], 0); |
555 | if (cl != 0x01) { |
556 | ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " |
557 | "got 0x%x != 0x01\n" , |
558 | __func__, chp->ch_channel, cl), |
559 | DEBUG_PROBE); |
560 | ret_value &= ~0x01; |
561 | } |
562 | bus_space_write_1(wdr->cmd_iot, |
563 | wdr->cmd_iohs[wd_sector], 0, 0x01); |
564 | cl = bus_space_read_1(wdr->cmd_iot, |
565 | wdr->cmd_iohs[wd_sector], 0); |
566 | if (cl != 0x01) { |
567 | ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " |
568 | "got 0x%x != 0x01\n" , |
569 | __func__, chp->ch_channel, cl), |
570 | DEBUG_PROBE); |
571 | ret_value &= ~0x01; |
572 | } |
573 | bus_space_write_1(wdr->cmd_iot, |
574 | wdr->cmd_iohs[wd_sector], 0, 0x02); |
575 | cl = bus_space_read_1(wdr->cmd_iot, |
576 | wdr->cmd_iohs[wd_sector], 0); |
577 | if (cl != 0x02) { |
578 | ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " |
579 | "got 0x%x != 0x02\n" , |
580 | __func__, chp->ch_channel, cl), |
581 | DEBUG_PROBE); |
582 | ret_value &= ~0x01; |
583 | } |
584 | cl = bus_space_read_1(wdr->cmd_iot, |
585 | wdr->cmd_iohs[wd_cyl_lo], 0); |
586 | if (cl != 0x01) { |
587 | ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " |
588 | "got 0x%x != 0x01\n" , |
589 | __func__, chp->ch_channel, cl), |
590 | DEBUG_PROBE); |
591 | ret_value &= ~0x01; |
592 | } |
593 | } |
594 | /* Register writability test, drive 1. */ |
595 | if (ret_value & 0x02) { |
596 | if (wdc->select) |
597 | wdc->select(chp,1); |
598 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
599 | 0, WDSD_IBM | 0x10); |
600 | bus_space_write_1(wdr->cmd_iot, |
601 | wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); |
602 | cl = bus_space_read_1(wdr->cmd_iot, |
603 | wdr->cmd_iohs[wd_cyl_lo], 0); |
604 | if (cl != 0x02) { |
605 | ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " |
606 | "got 0x%x != 0x02\n" , |
607 | __func__, chp->ch_channel, cl), |
608 | DEBUG_PROBE); |
609 | ret_value &= ~0x02; |
610 | } |
611 | bus_space_write_1(wdr->cmd_iot, |
612 | wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); |
613 | cl = bus_space_read_1(wdr->cmd_iot, |
614 | wdr->cmd_iohs[wd_cyl_lo], 0); |
615 | if (cl != 0x01) { |
616 | ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " |
617 | "got 0x%x != 0x01\n" , |
618 | __func__, chp->ch_channel, cl), |
619 | DEBUG_PROBE); |
620 | ret_value &= ~0x02; |
621 | } |
622 | bus_space_write_1(wdr->cmd_iot, |
623 | wdr->cmd_iohs[wd_sector], 0, 0x01); |
624 | cl = bus_space_read_1(wdr->cmd_iot, |
625 | wdr->cmd_iohs[wd_sector], 0); |
626 | if (cl != 0x01) { |
627 | ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " |
628 | "got 0x%x != 0x01\n" , |
629 | __func__, chp->ch_channel, cl), |
630 | DEBUG_PROBE); |
631 | ret_value &= ~0x02; |
632 | } |
633 | bus_space_write_1(wdr->cmd_iot, |
634 | wdr->cmd_iohs[wd_sector], 0, 0x02); |
635 | cl = bus_space_read_1(wdr->cmd_iot, |
636 | wdr->cmd_iohs[wd_sector], 0); |
637 | if (cl != 0x02) { |
638 | ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " |
639 | "got 0x%x != 0x02\n" , |
640 | __func__, chp->ch_channel, cl), |
641 | DEBUG_PROBE); |
642 | ret_value &= ~0x02; |
643 | } |
644 | cl = bus_space_read_1(wdr->cmd_iot, |
645 | wdr->cmd_iohs[wd_cyl_lo], 0); |
646 | if (cl != 0x01) { |
647 | ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " |
648 | "got 0x%x != 0x01\n" , |
649 | __func__, chp->ch_channel, cl), |
650 | DEBUG_PROBE); |
651 | ret_value &= ~0x02; |
652 | } |
653 | } |
654 | |
655 | if (ret_value == 0) { |
656 | splx(s); |
657 | return 0; |
658 | } |
659 | } |
660 | |
661 | #if 0 /* XXX this break some ATA or ATAPI devices */ |
662 | /* |
663 | * reset bus. Also send an ATAPI_RESET to devices, in case there are |
664 | * ATAPI device out there which don't react to the bus reset |
665 | */ |
666 | if (ret_value & 0x01) { |
667 | if (wdc->select) |
668 | wdc->select(chp,0); |
669 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
670 | 0, WDSD_IBM); |
671 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, |
672 | ATAPI_SOFT_RESET); |
673 | } |
674 | if (ret_value & 0x02) { |
675 | if (wdc->select) |
676 | wdc->select(chp,0); |
677 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
678 | 0, WDSD_IBM | 0x10); |
679 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, |
680 | ATAPI_SOFT_RESET); |
681 | } |
682 | |
683 | delay(5000); |
684 | #endif |
685 | |
686 | wdc->reset(chp, RESET_POLL); |
687 | DELAY(2000); |
688 | (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); |
689 | |
690 | if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) |
691 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, |
692 | WDCTL_4BIT); |
693 | |
694 | #ifdef WDC_NO_IDS |
695 | ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); |
696 | #else |
697 | splx(s); |
698 | ret_value = __wdcwait_reset(chp, ret_value, poll); |
699 | s = splbio(); |
700 | #endif |
701 | ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n" , |
702 | __func__, chp->ch_channel, ret_value), DEBUG_PROBE); |
703 | |
704 | /* if reset failed, there's nothing here */ |
705 | if (ret_value == 0) { |
706 | splx(s); |
707 | return 0; |
708 | } |
709 | |
710 | /* |
711 | * Test presence of drives. First test register signatures looking |
712 | * for ATAPI devices. If it's not an ATAPI and reset said there may |
713 | * be something here assume it's ATA or OLD. Ghost will be killed |
714 | * later in attach routine. |
715 | */ |
716 | for (drive = 0; drive < wdc->wdc_maxdrives; drive++) { |
717 | if ((ret_value & (0x01 << drive)) == 0) |
718 | continue; |
719 | if (wdc->select) |
720 | wdc->select(chp,drive); |
721 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, |
722 | WDSD_IBM | (drive << 4)); |
723 | delay(10); /* 400ns delay */ |
724 | /* Save registers contents */ |
725 | sc = bus_space_read_1(wdr->cmd_iot, |
726 | wdr->cmd_iohs[wd_seccnt], 0); |
727 | sn = bus_space_read_1(wdr->cmd_iot, |
728 | wdr->cmd_iohs[wd_sector], 0); |
729 | cl = bus_space_read_1(wdr->cmd_iot, |
730 | wdr->cmd_iohs[wd_cyl_lo], 0); |
731 | ch = bus_space_read_1(wdr->cmd_iot, |
732 | wdr->cmd_iohs[wd_cyl_hi], 0); |
733 | |
734 | ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " |
735 | "cl=0x%x ch=0x%x\n" , __func__, chp->ch_channel, drive, sc, |
736 | sn, cl, ch), DEBUG_PROBE); |
737 | /* |
738 | * sc & sn are supposed to be 0x1 for ATAPI but in some cases |
739 | * we get wrong values here, so ignore it. |
740 | */ |
741 | if (chp->ch_drive != NULL) { |
742 | if (cl == 0x14 && ch == 0xeb) { |
743 | chp->ch_drive[drive].drive_type = ATA_DRIVET_ATAPI; |
744 | } else { |
745 | chp->ch_drive[drive].drive_type = ATA_DRIVET_ATA; |
746 | } |
747 | } |
748 | } |
749 | /* |
750 | * Select an existing drive before lowering spl, some WDC_NO_IDS |
751 | * devices incorrectly assert IRQ on nonexistent slave |
752 | */ |
753 | if (ret_value & 0x01) { |
754 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, |
755 | WDSD_IBM); |
756 | (void)bus_space_read_1(wdr->cmd_iot, |
757 | wdr->cmd_iohs[wd_status], 0); |
758 | } |
759 | splx(s); |
760 | return (ret_value); |
761 | } |
762 | |
763 | void |
764 | wdcattach(struct ata_channel *chp) |
765 | { |
766 | struct atac_softc *atac = chp->ch_atac; |
767 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
768 | |
769 | KASSERT(wdc->wdc_maxdrives > 0 && wdc->wdc_maxdrives <= WDC_MAXDRIVES); |
770 | |
771 | /* default data transfer methods */ |
772 | if (wdc->datain_pio == NULL) |
773 | wdc->datain_pio = wdc_datain_pio; |
774 | if (wdc->dataout_pio == NULL) |
775 | wdc->dataout_pio = wdc_dataout_pio; |
776 | /* default reset method */ |
777 | if (wdc->reset == NULL) |
778 | wdc->reset = wdc_do_reset; |
779 | |
780 | /* initialise global data */ |
781 | if (atac->atac_bustype_ata == NULL) |
782 | atac->atac_bustype_ata = &wdc_ata_bustype; |
783 | if (atac->atac_probe == NULL) |
784 | atac->atac_probe = wdc_drvprobe; |
785 | #if NATAPIBUS > 0 |
786 | if (atac->atac_atapibus_attach == NULL) |
787 | atac->atac_atapibus_attach = wdc_atapibus_attach; |
788 | #endif |
789 | |
790 | ata_channel_attach(chp); |
791 | } |
792 | |
793 | void |
794 | wdc_childdetached(device_t self, device_t child) |
795 | { |
796 | struct atac_softc *atac = device_private(self); |
797 | struct ata_channel *chp; |
798 | int i; |
799 | |
800 | for (i = 0; i < atac->atac_nchannels; i++) { |
801 | chp = atac->atac_channels[i]; |
802 | if (child == chp->atabus) { |
803 | chp->atabus = NULL; |
804 | return; |
805 | } |
806 | } |
807 | } |
808 | |
809 | int |
810 | wdcdetach(device_t self, int flags) |
811 | { |
812 | struct atac_softc *atac = device_private(self); |
813 | struct ata_channel *chp; |
814 | struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; |
815 | int i, error = 0; |
816 | |
817 | for (i = 0; i < atac->atac_nchannels; i++) { |
818 | chp = atac->atac_channels[i]; |
819 | if (chp->atabus == NULL) |
820 | continue; |
821 | ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n" , |
822 | device_xname(atac->atac_dev), device_xname(chp->atabus)), |
823 | DEBUG_DETACH); |
824 | if ((error = config_detach(chp->atabus, flags)) != 0) |
825 | return error; |
826 | } |
827 | if (adapt->adapt_refcnt != 0) |
828 | return EBUSY; |
829 | return 0; |
830 | } |
831 | |
832 | /* restart an interrupted I/O */ |
833 | void |
834 | wdcrestart(void *v) |
835 | { |
836 | struct ata_channel *chp = v; |
837 | int s; |
838 | |
839 | s = splbio(); |
840 | atastart(chp); |
841 | splx(s); |
842 | } |
843 | |
844 | |
845 | /* |
846 | * Interrupt routine for the controller. Acknowledge the interrupt, check for |
847 | * errors on the current operation, mark it done if necessary, and start the |
848 | * next request. Also check for a partially done transfer, and continue with |
849 | * the next chunk if so. |
850 | */ |
851 | int |
852 | wdcintr(void *arg) |
853 | { |
854 | struct ata_channel *chp = arg; |
855 | struct atac_softc *atac = chp->ch_atac; |
856 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
857 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
858 | struct ata_xfer *xfer; |
859 | int ret; |
860 | |
861 | if (!device_is_active(atac->atac_dev)) { |
862 | ATADEBUG_PRINT(("wdcintr: deactivated controller\n" ), |
863 | DEBUG_INTR); |
864 | return (0); |
865 | } |
866 | if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { |
867 | ATADEBUG_PRINT(("wdcintr: inactive controller\n" ), DEBUG_INTR); |
868 | /* try to clear the pending interrupt anyway */ |
869 | (void)bus_space_read_1(wdr->cmd_iot, |
870 | wdr->cmd_iohs[wd_status], 0); |
871 | return (0); |
872 | } |
873 | |
874 | ATADEBUG_PRINT(("wdcintr\n" ), DEBUG_INTR); |
875 | xfer = chp->ch_queue->active_xfer; |
876 | #ifdef DIAGNOSTIC |
877 | if (xfer == NULL) |
878 | panic("wdcintr: no xfer" ); |
879 | if (xfer->c_chp != chp) { |
880 | printf("channel %d expected %d\n" , xfer->c_chp->ch_channel, |
881 | chp->ch_channel); |
882 | panic("wdcintr: wrong channel" ); |
883 | } |
884 | #endif |
885 | #if NATA_DMA || NATA_PIOBM |
886 | if (chp->ch_flags & ATACH_DMA_WAIT) { |
887 | wdc->dma_status = |
888 | (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, |
889 | xfer->c_drive, WDC_DMAEND_END); |
890 | if (wdc->dma_status & WDC_DMAST_NOIRQ) { |
891 | /* IRQ not for us, not detected by DMA engine */ |
892 | return 0; |
893 | } |
894 | chp->ch_flags &= ~ATACH_DMA_WAIT; |
895 | } |
896 | #endif |
897 | chp->ch_flags &= ~ATACH_IRQ_WAIT; |
898 | KASSERT(xfer->c_intr != NULL); |
899 | ret = xfer->c_intr(chp, xfer, 1); |
900 | if (ret == 0) /* irq was not for us, still waiting for irq */ |
901 | chp->ch_flags |= ATACH_IRQ_WAIT; |
902 | return (ret); |
903 | } |
904 | |
905 | /* Put all disk in RESET state */ |
906 | void |
907 | wdc_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) |
908 | { |
909 | struct ata_channel *chp = drvp->chnl_softc; |
910 | |
911 | KASSERT(sigp == NULL); |
912 | |
913 | ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n" , |
914 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, |
915 | drvp->drive), DEBUG_FUNCS); |
916 | |
917 | ata_reset_channel(chp, flags); |
918 | } |
919 | |
920 | void |
921 | wdc_reset_channel(struct ata_channel *chp, int flags) |
922 | { |
923 | TAILQ_HEAD(, ata_xfer) reset_xfer; |
924 | struct ata_xfer *xfer, *next_xfer; |
925 | #if NATA_DMA || NATA_PIOBM |
926 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
927 | #endif |
928 | TAILQ_INIT(&reset_xfer); |
929 | |
930 | chp->ch_flags &= ~ATACH_IRQ_WAIT; |
931 | |
932 | /* |
933 | * if the current command if on an ATAPI device, issue a |
934 | * ATAPI_SOFT_RESET |
935 | */ |
936 | xfer = chp->ch_queue->active_xfer; |
937 | if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { |
938 | wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); |
939 | if (flags & AT_WAIT) |
940 | tsleep(&flags, PRIBIO, "atardl" , mstohz(1) + 1); |
941 | else |
942 | delay(1000); |
943 | } |
944 | |
945 | /* reset the channel */ |
946 | if (flags & AT_WAIT) |
947 | (void) wdcreset(chp, RESET_SLEEP); |
948 | else |
949 | (void) wdcreset(chp, RESET_POLL); |
950 | |
951 | /* |
952 | * wait a bit after reset; in case the DMA engines needs some time |
953 | * to recover. |
954 | */ |
955 | if (flags & AT_WAIT) |
956 | tsleep(&flags, PRIBIO, "atardl" , mstohz(1) + 1); |
957 | else |
958 | delay(1000); |
959 | /* |
960 | * look for pending xfers. If we have a shared queue, we'll also reset |
961 | * the other channel if the current xfer is running on it. |
962 | * Then we'll dequeue only the xfers for this channel. |
963 | */ |
964 | if ((flags & AT_RST_NOCMD) == 0) { |
965 | /* |
966 | * move all xfers queued for this channel to the reset queue, |
967 | * and then process the current xfer and then the reset queue. |
968 | * We have to use a temporary queue because c_kill_xfer() |
969 | * may requeue commands. |
970 | */ |
971 | for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); |
972 | xfer != NULL; xfer = next_xfer) { |
973 | next_xfer = TAILQ_NEXT(xfer, c_xferchain); |
974 | if (xfer->c_chp != chp) |
975 | continue; |
976 | TAILQ_REMOVE(&chp->ch_queue->queue_xfer, |
977 | xfer, c_xferchain); |
978 | TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); |
979 | } |
980 | xfer = chp->ch_queue->active_xfer; |
981 | if (xfer) { |
982 | if (xfer->c_chp != chp) |
983 | ata_reset_channel(xfer->c_chp, flags); |
984 | else { |
985 | callout_stop(&chp->ch_callout); |
986 | #if NATA_DMA || NATA_PIOBM |
987 | /* |
988 | * If we're waiting for DMA, stop the |
989 | * DMA engine |
990 | */ |
991 | if (chp->ch_flags & ATACH_DMA_WAIT) { |
992 | (*wdc->dma_finish)(wdc->dma_arg, |
993 | chp->ch_channel, xfer->c_drive, |
994 | WDC_DMAEND_ABRT_QUIET); |
995 | chp->ch_flags &= ~ATACH_DMA_WAIT; |
996 | } |
997 | #endif |
998 | chp->ch_queue->active_xfer = NULL; |
999 | if ((flags & AT_RST_EMERG) == 0) |
1000 | xfer->c_kill_xfer( |
1001 | chp, xfer, KILL_RESET); |
1002 | } |
1003 | } |
1004 | |
1005 | for (xfer = TAILQ_FIRST(&reset_xfer); |
1006 | xfer != NULL; xfer = next_xfer) { |
1007 | next_xfer = TAILQ_NEXT(xfer, c_xferchain); |
1008 | TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); |
1009 | if ((flags & AT_RST_EMERG) == 0) |
1010 | xfer->c_kill_xfer(chp, xfer, KILL_RESET); |
1011 | } |
1012 | } |
1013 | } |
1014 | |
1015 | static int |
1016 | wdcreset(struct ata_channel *chp, int poll) |
1017 | { |
1018 | struct atac_softc *atac = chp->ch_atac; |
1019 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1020 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1021 | int drv_mask1, drv_mask2; |
1022 | |
1023 | #ifdef WDC_NO_IDS |
1024 | poll = RESET_POLL; |
1025 | #endif |
1026 | wdc->reset(chp, poll); |
1027 | |
1028 | drv_mask1 = (chp->ch_drive[0].drive_type != ATA_DRIVET_NONE) |
1029 | ? 0x01 : 0x00; |
1030 | if (chp->ch_ndrives > 1) |
1031 | drv_mask1 |= (chp->ch_drive[1].drive_type != ATA_DRIVET_NONE) |
1032 | ? 0x02 : 0x00; |
1033 | drv_mask2 = __wdcwait_reset(chp, drv_mask1, |
1034 | (poll == RESET_SLEEP) ? 0 : 1); |
1035 | if (drv_mask2 != drv_mask1) { |
1036 | aprint_error("%s channel %d: reset failed for" , |
1037 | device_xname(atac->atac_dev), chp->ch_channel); |
1038 | if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) |
1039 | aprint_normal(" drive 0" ); |
1040 | if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) |
1041 | aprint_normal(" drive 1" ); |
1042 | aprint_normal("\n" ); |
1043 | } |
1044 | if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) |
1045 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, |
1046 | WDCTL_4BIT); |
1047 | |
1048 | return (drv_mask1 != drv_mask2) ? 1 : 0; |
1049 | } |
1050 | |
1051 | void |
1052 | wdc_do_reset(struct ata_channel *chp, int poll) |
1053 | { |
1054 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1055 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1056 | int s = 0; |
1057 | |
1058 | if (poll != RESET_SLEEP) |
1059 | s = splbio(); |
1060 | if (wdc->select) |
1061 | wdc->select(chp,0); |
1062 | /* master */ |
1063 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); |
1064 | delay(10); /* 400ns delay */ |
1065 | /* assert SRST, wait for reset to complete */ |
1066 | if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { |
1067 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, |
1068 | WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); |
1069 | delay(2000); |
1070 | } |
1071 | (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); |
1072 | if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) |
1073 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, |
1074 | WDCTL_4BIT | WDCTL_IDS); |
1075 | delay(10); /* 400ns delay */ |
1076 | if (poll != RESET_SLEEP) { |
1077 | /* ACK interrupt in case there is one pending left */ |
1078 | if (wdc->irqack) |
1079 | wdc->irqack(chp); |
1080 | splx(s); |
1081 | } |
1082 | } |
1083 | |
1084 | static int |
1085 | __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) |
1086 | { |
1087 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1088 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1089 | int timeout, nloop; |
1090 | u_int8_t st0 = 0, st1 = 0; |
1091 | #ifdef ATADEBUG |
1092 | u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; |
1093 | u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; |
1094 | #endif |
1095 | if (poll) |
1096 | nloop = WDCNDELAY_RST; |
1097 | else |
1098 | nloop = WDC_RESET_WAIT * hz / 1000; |
1099 | /* wait for BSY to deassert */ |
1100 | for (timeout = 0; timeout < nloop; timeout++) { |
1101 | if ((drv_mask & 0x01) != 0) { |
1102 | if (wdc->select) |
1103 | wdc->select(chp,0); |
1104 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
1105 | 0, WDSD_IBM); /* master */ |
1106 | delay(10); |
1107 | st0 = bus_space_read_1(wdr->cmd_iot, |
1108 | wdr->cmd_iohs[wd_status], 0); |
1109 | #ifdef ATADEBUG |
1110 | sc0 = bus_space_read_1(wdr->cmd_iot, |
1111 | wdr->cmd_iohs[wd_seccnt], 0); |
1112 | sn0 = bus_space_read_1(wdr->cmd_iot, |
1113 | wdr->cmd_iohs[wd_sector], 0); |
1114 | cl0 = bus_space_read_1(wdr->cmd_iot, |
1115 | wdr->cmd_iohs[wd_cyl_lo], 0); |
1116 | ch0 = bus_space_read_1(wdr->cmd_iot, |
1117 | wdr->cmd_iohs[wd_cyl_hi], 0); |
1118 | #endif |
1119 | } |
1120 | if ((drv_mask & 0x02) != 0) { |
1121 | if (wdc->select) |
1122 | wdc->select(chp,1); |
1123 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
1124 | 0, WDSD_IBM | 0x10); /* slave */ |
1125 | delay(10); |
1126 | st1 = bus_space_read_1(wdr->cmd_iot, |
1127 | wdr->cmd_iohs[wd_status], 0); |
1128 | #ifdef ATADEBUG |
1129 | sc1 = bus_space_read_1(wdr->cmd_iot, |
1130 | wdr->cmd_iohs[wd_seccnt], 0); |
1131 | sn1 = bus_space_read_1(wdr->cmd_iot, |
1132 | wdr->cmd_iohs[wd_sector], 0); |
1133 | cl1 = bus_space_read_1(wdr->cmd_iot, |
1134 | wdr->cmd_iohs[wd_cyl_lo], 0); |
1135 | ch1 = bus_space_read_1(wdr->cmd_iot, |
1136 | wdr->cmd_iohs[wd_cyl_hi], 0); |
1137 | #endif |
1138 | } |
1139 | |
1140 | if ((drv_mask & 0x01) == 0) { |
1141 | /* no master */ |
1142 | if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { |
1143 | /* No master, slave is ready, it's done */ |
1144 | goto end; |
1145 | } |
1146 | if ((drv_mask & 0x02) == 0) { |
1147 | /* No master, no slave: it's done */ |
1148 | goto end; |
1149 | } |
1150 | } else if ((drv_mask & 0x02) == 0) { |
1151 | /* no slave */ |
1152 | if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { |
1153 | /* No slave, master is ready, it's done */ |
1154 | goto end; |
1155 | } |
1156 | } else { |
1157 | /* Wait for both master and slave to be ready */ |
1158 | if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { |
1159 | goto end; |
1160 | } |
1161 | } |
1162 | if (poll) |
1163 | delay(WDCDELAY); |
1164 | else |
1165 | tsleep(&nloop, PRIBIO, "atarst" , 1); |
1166 | } |
1167 | /* Reset timed out. Maybe it's because drv_mask was not right */ |
1168 | if (st0 & WDCS_BSY) |
1169 | drv_mask &= ~0x01; |
1170 | if (st1 & WDCS_BSY) |
1171 | drv_mask &= ~0x02; |
1172 | end: |
1173 | ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " |
1174 | "cl=0x%x ch=0x%x\n" , |
1175 | device_xname(chp->ch_atac->atac_dev), |
1176 | chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); |
1177 | ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " |
1178 | "cl=0x%x ch=0x%x\n" , |
1179 | device_xname(chp->ch_atac->atac_dev), |
1180 | chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); |
1181 | |
1182 | ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n" , |
1183 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, |
1184 | st0, st1), DEBUG_PROBE); |
1185 | |
1186 | return drv_mask; |
1187 | } |
1188 | |
1189 | /* |
1190 | * Wait for a drive to be !BSY, and have mask in its status register. |
1191 | * return -1 for a timeout after "timeout" ms. |
1192 | */ |
1193 | static int |
1194 | __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) |
1195 | { |
1196 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1197 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1198 | u_char status; |
1199 | int xtime = 0; |
1200 | |
1201 | ATADEBUG_PRINT(("__wdcwait %s:%d\n" , |
1202 | device_xname(chp->ch_atac->atac_dev), |
1203 | chp->ch_channel), DEBUG_STATUS); |
1204 | chp->ch_error = 0; |
1205 | |
1206 | timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ |
1207 | |
1208 | for (;;) { |
1209 | chp->ch_status = status = |
1210 | bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); |
1211 | if ((status & (WDCS_BSY | mask)) == bits) |
1212 | break; |
1213 | if (++xtime > timeout) { |
1214 | ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " |
1215 | "status %x error %x (mask 0x%x bits 0x%x)\n" , |
1216 | xtime, status, |
1217 | bus_space_read_1(wdr->cmd_iot, |
1218 | wdr->cmd_iohs[wd_error], 0), mask, bits), |
1219 | DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); |
1220 | return(WDCWAIT_TOUT); |
1221 | } |
1222 | delay(WDCDELAY); |
1223 | } |
1224 | #ifdef ATADEBUG |
1225 | if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) |
1226 | printf("__wdcwait: did busy-wait, time=%d\n" , xtime); |
1227 | #endif |
1228 | if (status & WDCS_ERR) |
1229 | chp->ch_error = bus_space_read_1(wdr->cmd_iot, |
1230 | wdr->cmd_iohs[wd_error], 0); |
1231 | #ifdef WDCNDELAY_DEBUG |
1232 | /* After autoconfig, there should be no long delays. */ |
1233 | if (!cold && xtime > WDCNDELAY_DEBUG) { |
1234 | struct ata_xfer *xfer = chp->ch_queue->active_xfer; |
1235 | if (xfer == NULL) |
1236 | printf("%s channel %d: warning: busy-wait took %dus\n" , |
1237 | device_xname(chp->ch_atac->atac_dev), |
1238 | chp->ch_channel, WDCDELAY * xtime); |
1239 | else |
1240 | printf("%s:%d:%d: warning: busy-wait took %dus\n" , |
1241 | device_xname(chp->ch_atac->atac_dev), |
1242 | chp->ch_channel, xfer->c_drive, |
1243 | WDCDELAY * xtime); |
1244 | } |
1245 | #endif |
1246 | return(WDCWAIT_OK); |
1247 | } |
1248 | |
1249 | /* |
1250 | * Call __wdcwait(), polling using tsleep() or waking up the kernel |
1251 | * thread if possible |
1252 | */ |
1253 | int |
1254 | wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) |
1255 | { |
1256 | int error, i, timeout_hz = mstohz(timeout); |
1257 | |
1258 | if (timeout_hz == 0 || |
1259 | (flags & (AT_WAIT | AT_POLL)) == AT_POLL) |
1260 | error = __wdcwait(chp, mask, bits, timeout); |
1261 | else { |
1262 | error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); |
1263 | if (error != 0) { |
1264 | if ((chp->ch_flags & ATACH_TH_RUN) || |
1265 | (flags & AT_WAIT)) { |
1266 | /* |
1267 | * we're running in the channel thread |
1268 | * or some userland thread context |
1269 | */ |
1270 | for (i = 0; i < timeout_hz; i++) { |
1271 | if (__wdcwait(chp, mask, bits, |
1272 | WDCDELAY_POLL) == 0) { |
1273 | error = 0; |
1274 | break; |
1275 | } |
1276 | tsleep(&chp, PRIBIO, "atapoll" , 1); |
1277 | } |
1278 | } else { |
1279 | /* |
1280 | * we're probably in interrupt context, |
1281 | * ask the thread to come back here |
1282 | */ |
1283 | #ifdef DIAGNOSTIC |
1284 | if (chp->ch_queue->queue_freeze > 0) |
1285 | panic("wdcwait: queue_freeze" ); |
1286 | #endif |
1287 | chp->ch_queue->queue_freeze++; |
1288 | wakeup(&chp->ch_thread); |
1289 | return(WDCWAIT_THR); |
1290 | } |
1291 | } |
1292 | } |
1293 | return (error); |
1294 | } |
1295 | |
1296 | |
1297 | #if NATA_DMA |
1298 | /* |
1299 | * Busy-wait for DMA to complete |
1300 | */ |
1301 | int |
1302 | wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) |
1303 | { |
1304 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1305 | int xtime; |
1306 | |
1307 | for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { |
1308 | wdc->dma_status = |
1309 | (*wdc->dma_finish)(wdc->dma_arg, |
1310 | chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); |
1311 | if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) |
1312 | return 0; |
1313 | delay(WDCDELAY); |
1314 | } |
1315 | /* timeout, force a DMA halt */ |
1316 | wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, |
1317 | chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); |
1318 | return 1; |
1319 | } |
1320 | #endif |
1321 | |
1322 | void |
1323 | wdctimeout(void *arg) |
1324 | { |
1325 | struct ata_channel *chp = (struct ata_channel *)arg; |
1326 | #if NATA_DMA || NATA_PIOBM |
1327 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1328 | #endif |
1329 | struct ata_xfer *xfer = chp->ch_queue->active_xfer; |
1330 | int s; |
1331 | |
1332 | ATADEBUG_PRINT(("wdctimeout\n" ), DEBUG_FUNCS); |
1333 | |
1334 | s = splbio(); |
1335 | if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { |
1336 | __wdcerror(chp, "lost interrupt" ); |
1337 | printf("\ttype: %s tc_bcount: %d tc_skip: %d\n" , |
1338 | (xfer->c_flags & C_ATAPI) ? "atapi" : "ata" , |
1339 | xfer->c_bcount, xfer->c_skip); |
1340 | #if NATA_DMA || NATA_PIOBM |
1341 | if (chp->ch_flags & ATACH_DMA_WAIT) { |
1342 | wdc->dma_status = |
1343 | (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, |
1344 | xfer->c_drive, WDC_DMAEND_ABRT); |
1345 | chp->ch_flags &= ~ATACH_DMA_WAIT; |
1346 | } |
1347 | #endif |
1348 | /* |
1349 | * Call the interrupt routine. If we just missed an interrupt, |
1350 | * it will do what's needed. Else, it will take the needed |
1351 | * action (reset the device). |
1352 | * Before that we need to reinstall the timeout callback, |
1353 | * in case it will miss another irq while in this transfer |
1354 | * We arbitray chose it to be 1s |
1355 | */ |
1356 | callout_reset(&chp->ch_callout, hz, wdctimeout, chp); |
1357 | xfer->c_flags |= C_TIMEOU; |
1358 | chp->ch_flags &= ~ATACH_IRQ_WAIT; |
1359 | KASSERT(xfer->c_intr != NULL); |
1360 | xfer->c_intr(chp, xfer, 1); |
1361 | } else |
1362 | __wdcerror(chp, "missing untimeout" ); |
1363 | splx(s); |
1364 | } |
1365 | |
1366 | int |
1367 | wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) |
1368 | { |
1369 | struct ata_channel *chp = drvp->chnl_softc; |
1370 | struct ata_xfer *xfer; |
1371 | int s, ret; |
1372 | |
1373 | ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n" , |
1374 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, |
1375 | drvp->drive), DEBUG_FUNCS); |
1376 | |
1377 | /* set up an xfer and queue. Wait for completion */ |
1378 | xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : |
1379 | ATAXF_NOSLEEP); |
1380 | if (xfer == NULL) { |
1381 | return ATACMD_TRY_AGAIN; |
1382 | } |
1383 | |
1384 | if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) |
1385 | ata_c->flags |= AT_POLL; |
1386 | if (ata_c->flags & AT_POLL) |
1387 | xfer->c_flags |= C_POLL; |
1388 | if (ata_c->flags & AT_WAIT) |
1389 | xfer->c_flags |= C_WAIT; |
1390 | xfer->c_drive = drvp->drive; |
1391 | xfer->c_databuf = ata_c->data; |
1392 | xfer->c_bcount = ata_c->bcount; |
1393 | xfer->c_cmd = ata_c; |
1394 | xfer->c_start = __wdccommand_start; |
1395 | xfer->c_intr = __wdccommand_intr; |
1396 | xfer->c_kill_xfer = __wdccommand_kill_xfer; |
1397 | |
1398 | s = splbio(); |
1399 | ata_exec_xfer(chp, xfer); |
1400 | #ifdef DIAGNOSTIC |
1401 | if ((ata_c->flags & AT_POLL) != 0 && |
1402 | (ata_c->flags & AT_DONE) == 0) |
1403 | panic("wdc_exec_command: polled command not done" ); |
1404 | #endif |
1405 | if (ata_c->flags & AT_DONE) { |
1406 | ret = ATACMD_COMPLETE; |
1407 | } else { |
1408 | if (ata_c->flags & AT_WAIT) { |
1409 | while ((ata_c->flags & AT_DONE) == 0) { |
1410 | tsleep(ata_c, PRIBIO, "wdccmd" , 0); |
1411 | } |
1412 | ret = ATACMD_COMPLETE; |
1413 | } else { |
1414 | ret = ATACMD_QUEUED; |
1415 | } |
1416 | } |
1417 | splx(s); |
1418 | return ret; |
1419 | } |
1420 | |
1421 | static void |
1422 | __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) |
1423 | { |
1424 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1425 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1426 | int drive = xfer->c_drive; |
1427 | int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; |
1428 | struct ata_command *ata_c = xfer->c_cmd; |
1429 | |
1430 | ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n" , |
1431 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, |
1432 | xfer->c_drive), DEBUG_FUNCS); |
1433 | |
1434 | if (wdc->select) |
1435 | wdc->select(chp,drive); |
1436 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, |
1437 | WDSD_IBM | (drive << 4)); |
1438 | switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, |
1439 | ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { |
1440 | case WDCWAIT_OK: |
1441 | break; |
1442 | case WDCWAIT_TOUT: |
1443 | ata_c->flags |= AT_TIMEOU; |
1444 | __wdccommand_done(chp, xfer); |
1445 | return; |
1446 | case WDCWAIT_THR: |
1447 | return; |
1448 | } |
1449 | if (ata_c->flags & AT_POLL) { |
1450 | /* polled command, disable interrupts */ |
1451 | if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) |
1452 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, |
1453 | wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); |
1454 | } |
1455 | if ((ata_c->flags & AT_LBA48) != 0) { |
1456 | wdccommandext(chp, drive, ata_c->r_command, |
1457 | ata_c->r_lba, ata_c->r_count, ata_c->r_features, |
1458 | ata_c->r_device & ~0x10); |
1459 | } else { |
1460 | wdccommand(chp, drive, ata_c->r_command, |
1461 | (ata_c->r_lba >> 8) & 0xffff, |
1462 | WDSD_IBM | (drive << 4) | |
1463 | (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | |
1464 | ((ata_c->r_lba >> 24) & 0x0f), |
1465 | ata_c->r_lba & 0xff, |
1466 | ata_c->r_count & 0xff, |
1467 | ata_c->r_features & 0xff); |
1468 | } |
1469 | |
1470 | if ((ata_c->flags & AT_POLL) == 0) { |
1471 | chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ |
1472 | callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, |
1473 | wdctimeout, chp); |
1474 | return; |
1475 | } |
1476 | /* |
1477 | * Polled command. Wait for drive ready or drq. Done in intr(). |
1478 | * Wait for at last 400ns for status bit to be valid. |
1479 | */ |
1480 | delay(10); /* 400ns delay */ |
1481 | __wdccommand_intr(chp, xfer, 0); |
1482 | } |
1483 | |
1484 | static int |
1485 | __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) |
1486 | { |
1487 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1488 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1489 | struct ata_command *ata_c = xfer->c_cmd; |
1490 | int bcount = ata_c->bcount; |
1491 | char *data = ata_c->data; |
1492 | int wflags; |
1493 | int drive_flags; |
1494 | |
1495 | if (ata_c->r_command == WDCC_IDENTIFY || |
1496 | ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { |
1497 | /* |
1498 | * The IDENTIFY data has been designed as an array of |
1499 | * u_int16_t, so we can byteswap it on the fly. |
1500 | * Historically it's what we have always done so keeping it |
1501 | * here ensure binary backward compatibility. |
1502 | */ |
1503 | drive_flags = ATA_DRIVE_NOSTREAM | |
1504 | chp->ch_drive[xfer->c_drive].drive_flags; |
1505 | } else { |
1506 | /* |
1507 | * Other data structure are opaque and should be transfered |
1508 | * as is. |
1509 | */ |
1510 | drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; |
1511 | } |
1512 | |
1513 | #ifdef WDC_NO_IDS |
1514 | wflags = AT_POLL; |
1515 | #else |
1516 | if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { |
1517 | /* both wait and poll, we can tsleep here */ |
1518 | wflags = AT_WAIT | AT_POLL; |
1519 | } else { |
1520 | wflags = AT_POLL; |
1521 | } |
1522 | #endif |
1523 | |
1524 | again: |
1525 | ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n" , |
1526 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, |
1527 | xfer->c_drive), DEBUG_INTR); |
1528 | /* |
1529 | * after a ATAPI_SOFT_RESET, the device will have released the bus. |
1530 | * Reselect again, it doesn't hurt for others commands, and the time |
1531 | * penalty for the extra register write is acceptable, |
1532 | * wdc_exec_command() isn't called often (mostly for autoconfig) |
1533 | */ |
1534 | if ((xfer->c_flags & C_ATAPI) != 0) { |
1535 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, |
1536 | WDSD_IBM | (xfer->c_drive << 4)); |
1537 | } |
1538 | if ((ata_c->flags & AT_XFDONE) != 0) { |
1539 | /* |
1540 | * We have completed a data xfer. The drive should now be |
1541 | * in its initial state |
1542 | */ |
1543 | if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, |
1544 | ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, |
1545 | wflags) == WDCWAIT_TOUT) { |
1546 | if (irq && (xfer->c_flags & C_TIMEOU) == 0) |
1547 | return 0; /* IRQ was not for us */ |
1548 | ata_c->flags |= AT_TIMEOU; |
1549 | } |
1550 | goto out; |
1551 | } |
1552 | if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, |
1553 | (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { |
1554 | if (irq && (xfer->c_flags & C_TIMEOU) == 0) |
1555 | return 0; /* IRQ was not for us */ |
1556 | ata_c->flags |= AT_TIMEOU; |
1557 | goto out; |
1558 | } |
1559 | if (wdc->irqack) |
1560 | wdc->irqack(chp); |
1561 | if (ata_c->flags & AT_READ) { |
1562 | if ((chp->ch_status & WDCS_DRQ) == 0) { |
1563 | ata_c->flags |= AT_TIMEOU; |
1564 | goto out; |
1565 | } |
1566 | wdc->datain_pio(chp, drive_flags, data, bcount); |
1567 | /* at this point the drive should be in its initial state */ |
1568 | ata_c->flags |= AT_XFDONE; |
1569 | /* |
1570 | * XXX checking the status register again here cause some |
1571 | * hardware to timeout. |
1572 | */ |
1573 | } else if (ata_c->flags & AT_WRITE) { |
1574 | if ((chp->ch_status & WDCS_DRQ) == 0) { |
1575 | ata_c->flags |= AT_TIMEOU; |
1576 | goto out; |
1577 | } |
1578 | wdc->dataout_pio(chp, drive_flags, data, bcount); |
1579 | ata_c->flags |= AT_XFDONE; |
1580 | if ((ata_c->flags & AT_POLL) == 0) { |
1581 | chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ |
1582 | callout_reset(&chp->ch_callout, |
1583 | mstohz(ata_c->timeout), wdctimeout, chp); |
1584 | return 1; |
1585 | } else { |
1586 | goto again; |
1587 | } |
1588 | } |
1589 | out: |
1590 | __wdccommand_done(chp, xfer); |
1591 | return 1; |
1592 | } |
1593 | |
1594 | static void |
1595 | __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) |
1596 | { |
1597 | struct atac_softc *atac = chp->ch_atac; |
1598 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1599 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1600 | struct ata_command *ata_c = xfer->c_cmd; |
1601 | |
1602 | ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n" , |
1603 | device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, |
1604 | ata_c->flags), DEBUG_FUNCS); |
1605 | |
1606 | |
1607 | if (chp->ch_status & WDCS_DWF) |
1608 | ata_c->flags |= AT_DF; |
1609 | if (chp->ch_status & WDCS_ERR) { |
1610 | ata_c->flags |= AT_ERROR; |
1611 | ata_c->r_error = chp->ch_error; |
1612 | } |
1613 | if ((ata_c->flags & AT_READREG) != 0 && |
1614 | device_is_active(atac->atac_dev) && |
1615 | (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { |
1616 | ata_c->r_status = bus_space_read_1(wdr->cmd_iot, |
1617 | wdr->cmd_iohs[wd_status], 0); |
1618 | ata_c->r_error = bus_space_read_1(wdr->cmd_iot, |
1619 | wdr->cmd_iohs[wd_error], 0); |
1620 | ata_c->r_count = bus_space_read_1(wdr->cmd_iot, |
1621 | wdr->cmd_iohs[wd_seccnt], 0); |
1622 | ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot, |
1623 | wdr->cmd_iohs[wd_sector], 0) << 0; |
1624 | ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, |
1625 | wdr->cmd_iohs[wd_cyl_lo], 0) << 8; |
1626 | ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, |
1627 | wdr->cmd_iohs[wd_cyl_hi], 0) << 16; |
1628 | ata_c->r_device = bus_space_read_1(wdr->cmd_iot, |
1629 | wdr->cmd_iohs[wd_sdh], 0); |
1630 | |
1631 | if ((ata_c->flags & AT_LBA48) != 0) { |
1632 | if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { |
1633 | if ((ata_c->flags & AT_POLL) != 0) |
1634 | bus_space_write_1(wdr->ctl_iot, |
1635 | wdr->ctl_ioh, wd_aux_ctlr, |
1636 | WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); |
1637 | else |
1638 | bus_space_write_1(wdr->ctl_iot, |
1639 | wdr->ctl_ioh, wd_aux_ctlr, |
1640 | WDCTL_HOB|WDCTL_4BIT); |
1641 | } |
1642 | ata_c->r_count |= bus_space_read_1(wdr->cmd_iot, |
1643 | wdr->cmd_iohs[wd_seccnt], 0) << 8; |
1644 | ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, |
1645 | wdr->cmd_iohs[wd_sector], 0) << 24; |
1646 | ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, |
1647 | wdr->cmd_iohs[wd_cyl_lo], 0) << 32; |
1648 | ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, |
1649 | wdr->cmd_iohs[wd_cyl_hi], 0) << 40; |
1650 | if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { |
1651 | if ((ata_c->flags & AT_POLL) != 0) |
1652 | bus_space_write_1(wdr->ctl_iot, |
1653 | wdr->ctl_ioh, wd_aux_ctlr, |
1654 | WDCTL_4BIT|WDCTL_IDS); |
1655 | else |
1656 | bus_space_write_1(wdr->ctl_iot, |
1657 | wdr->ctl_ioh, wd_aux_ctlr, |
1658 | WDCTL_4BIT); |
1659 | } |
1660 | } else { |
1661 | ata_c->r_lba |= |
1662 | (uint64_t)(ata_c->r_device & 0x0f) << 24; |
1663 | } |
1664 | ata_c->r_device &= 0xf0; |
1665 | } |
1666 | callout_stop(&chp->ch_callout); |
1667 | chp->ch_queue->active_xfer = NULL; |
1668 | if (ata_c->flags & AT_POLL) { |
1669 | /* enable interrupts */ |
1670 | if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) |
1671 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, |
1672 | wd_aux_ctlr, WDCTL_4BIT); |
1673 | delay(10); /* some drives need a little delay here */ |
1674 | } |
1675 | if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { |
1676 | __wdccommand_kill_xfer(chp, xfer, KILL_GONE); |
1677 | chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; |
1678 | wakeup(&chp->ch_queue->active_xfer); |
1679 | } else |
1680 | __wdccommand_done_end(chp, xfer); |
1681 | } |
1682 | |
1683 | static void |
1684 | __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) |
1685 | { |
1686 | struct ata_command *ata_c = xfer->c_cmd; |
1687 | |
1688 | ata_c->flags |= AT_DONE; |
1689 | ata_free_xfer(chp, xfer); |
1690 | if (ata_c->flags & AT_WAIT) |
1691 | wakeup(ata_c); |
1692 | else if (ata_c->callback) |
1693 | ata_c->callback(ata_c->callback_arg); |
1694 | atastart(chp); |
1695 | return; |
1696 | } |
1697 | |
1698 | static void |
1699 | __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, |
1700 | int reason) |
1701 | { |
1702 | struct ata_command *ata_c = xfer->c_cmd; |
1703 | |
1704 | switch (reason) { |
1705 | case KILL_GONE: |
1706 | ata_c->flags |= AT_GONE; |
1707 | break; |
1708 | case KILL_RESET: |
1709 | ata_c->flags |= AT_RESET; |
1710 | break; |
1711 | default: |
1712 | printf("__wdccommand_kill_xfer: unknown reason %d\n" , |
1713 | reason); |
1714 | panic("__wdccommand_kill_xfer" ); |
1715 | } |
1716 | __wdccommand_done_end(chp, xfer); |
1717 | } |
1718 | |
1719 | /* |
1720 | * Send a command. The drive should be ready. |
1721 | * Assumes interrupts are blocked. |
1722 | */ |
1723 | void |
1724 | wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, |
1725 | u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, |
1726 | u_int8_t features) |
1727 | { |
1728 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1729 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1730 | |
1731 | ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " |
1732 | "sector=%d count=%d features=%d\n" , |
1733 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, |
1734 | command, cylin, head, sector, count, features), DEBUG_FUNCS); |
1735 | |
1736 | if (wdc->select) |
1737 | wdc->select(chp,drive); |
1738 | |
1739 | /* Select drive, head, and addressing mode. */ |
1740 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, |
1741 | WDSD_IBM | (drive << 4) | head); |
1742 | /* Load parameters into the wd_features register. */ |
1743 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, |
1744 | features); |
1745 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); |
1746 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); |
1747 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); |
1748 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], |
1749 | 0, cylin >> 8); |
1750 | |
1751 | /* Send command. */ |
1752 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); |
1753 | return; |
1754 | } |
1755 | |
1756 | /* |
1757 | * Send a 48-bit addressing command. The drive should be ready. |
1758 | * Assumes interrupts are blocked. |
1759 | */ |
1760 | void |
1761 | wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, |
1762 | u_int64_t blkno, u_int16_t count, u_int16_t features, u_int8_t device) |
1763 | { |
1764 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1765 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1766 | |
1767 | ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%02x " |
1768 | "blkno=0x%012" PRIx64" count=0x%04x features=0x%04x " |
1769 | "device=0x%02x\n" , device_xname(chp->ch_atac->atac_dev), |
1770 | chp->ch_channel, drive, command, blkno, count, features, device), |
1771 | DEBUG_FUNCS); |
1772 | |
1773 | KASSERT(drive < wdc->wdc_maxdrives); |
1774 | |
1775 | if (wdc->select) |
1776 | wdc->select(chp,drive); |
1777 | |
1778 | /* Select drive, head, and addressing mode. */ |
1779 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, |
1780 | (drive << 4) | device); |
1781 | |
1782 | if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { |
1783 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], |
1784 | 0, features); |
1785 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], |
1786 | 0, count); |
1787 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], |
1788 | 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); |
1789 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], |
1790 | 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); |
1791 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], |
1792 | 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); |
1793 | } else { |
1794 | /* previous */ |
1795 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], |
1796 | 0, features >> 8); |
1797 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], |
1798 | 0, count >> 8); |
1799 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], |
1800 | 0, blkno >> 24); |
1801 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], |
1802 | 0, blkno >> 32); |
1803 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], |
1804 | 0, blkno >> 40); |
1805 | |
1806 | /* current */ |
1807 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], |
1808 | 0, features); |
1809 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], |
1810 | 0, count); |
1811 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], |
1812 | 0, blkno); |
1813 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], |
1814 | 0, blkno >> 8); |
1815 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], |
1816 | 0, blkno >> 16); |
1817 | } |
1818 | |
1819 | /* Send command. */ |
1820 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); |
1821 | return; |
1822 | } |
1823 | |
1824 | /* |
1825 | * Simplified version of wdccommand(). Unbusy/ready/drq must be |
1826 | * tested by the caller. |
1827 | */ |
1828 | void |
1829 | wdccommandshort(struct ata_channel *chp, int drive, int command) |
1830 | { |
1831 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1832 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1833 | |
1834 | ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n" , |
1835 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, |
1836 | command), DEBUG_FUNCS); |
1837 | |
1838 | if (wdc->select) |
1839 | wdc->select(chp,drive); |
1840 | |
1841 | /* Select drive. */ |
1842 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, |
1843 | WDSD_IBM | (drive << 4)); |
1844 | |
1845 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); |
1846 | } |
1847 | |
1848 | static void |
1849 | __wdcerror(struct ata_channel *chp, const char *msg) |
1850 | { |
1851 | struct atac_softc *atac = chp->ch_atac; |
1852 | struct ata_xfer *xfer = chp->ch_queue->active_xfer; |
1853 | |
1854 | if (xfer == NULL) |
1855 | aprint_error("%s:%d: %s\n" , device_xname(atac->atac_dev), |
1856 | chp->ch_channel, msg); |
1857 | else |
1858 | aprint_error("%s:%d:%d: %s\n" , device_xname(atac->atac_dev), |
1859 | chp->ch_channel, xfer->c_drive, msg); |
1860 | } |
1861 | |
1862 | /* |
1863 | * the bit bucket |
1864 | */ |
1865 | void |
1866 | wdcbit_bucket(struct ata_channel *chp, int size) |
1867 | { |
1868 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); |
1869 | |
1870 | for (; size >= 2; size -= 2) |
1871 | (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); |
1872 | if (size) |
1873 | (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); |
1874 | } |
1875 | |
1876 | static void |
1877 | wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) |
1878 | { |
1879 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); |
1880 | |
1881 | #ifndef __NO_STRICT_ALIGNMENT |
1882 | if ((uintptr_t)bf & 1) |
1883 | goto unaligned; |
1884 | if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) |
1885 | goto unaligned; |
1886 | #endif |
1887 | |
1888 | if (flags & ATA_DRIVE_NOSTREAM) { |
1889 | if ((flags & ATA_DRIVE_CAP32) && len > 3) { |
1890 | bus_space_read_multi_4(wdr->data32iot, |
1891 | wdr->data32ioh, 0, bf, len >> 2); |
1892 | bf = (char *)bf + (len & ~3); |
1893 | len &= 3; |
1894 | } |
1895 | if (len > 1) { |
1896 | bus_space_read_multi_2(wdr->cmd_iot, |
1897 | wdr->cmd_iohs[wd_data], 0, bf, len >> 1); |
1898 | bf = (char *)bf + (len & ~1); |
1899 | len &= 1; |
1900 | } |
1901 | } else { |
1902 | if ((flags & ATA_DRIVE_CAP32) && len > 3) { |
1903 | bus_space_read_multi_stream_4(wdr->data32iot, |
1904 | wdr->data32ioh, 0, bf, len >> 2); |
1905 | bf = (char *)bf + (len & ~3); |
1906 | len &= 3; |
1907 | } |
1908 | if (len > 1) { |
1909 | bus_space_read_multi_stream_2(wdr->cmd_iot, |
1910 | wdr->cmd_iohs[wd_data], 0, bf, len >> 1); |
1911 | bf = (char *)bf + (len & ~1); |
1912 | len &= 1; |
1913 | } |
1914 | } |
1915 | if (len) |
1916 | *((uint8_t *)bf) = bus_space_read_1(wdr->cmd_iot, |
1917 | wdr->cmd_iohs[wd_data], 0); |
1918 | return; |
1919 | |
1920 | #ifndef __NO_STRICT_ALIGNMENT |
1921 | unaligned: |
1922 | if (flags & ATA_DRIVE_NOSTREAM) { |
1923 | if (flags & ATA_DRIVE_CAP32) { |
1924 | while (len > 3) { |
1925 | uint32_t val; |
1926 | |
1927 | val = bus_space_read_4(wdr->data32iot, |
1928 | wdr->data32ioh, 0); |
1929 | memcpy(bf, &val, 4); |
1930 | bf = (char *)bf + 4; |
1931 | len -= 4; |
1932 | } |
1933 | } |
1934 | while (len > 1) { |
1935 | uint16_t val; |
1936 | |
1937 | val = bus_space_read_2(wdr->cmd_iot, |
1938 | wdr->cmd_iohs[wd_data], 0); |
1939 | memcpy(bf, &val, 2); |
1940 | bf = (char *)bf + 2; |
1941 | len -= 2; |
1942 | } |
1943 | } else { |
1944 | if (flags & ATA_DRIVE_CAP32) { |
1945 | while (len > 3) { |
1946 | uint32_t val; |
1947 | |
1948 | val = bus_space_read_stream_4(wdr->data32iot, |
1949 | wdr->data32ioh, 0); |
1950 | memcpy(bf, &val, 4); |
1951 | bf = (char *)bf + 4; |
1952 | len -= 4; |
1953 | } |
1954 | } |
1955 | while (len > 1) { |
1956 | uint16_t val; |
1957 | |
1958 | val = bus_space_read_stream_2(wdr->cmd_iot, |
1959 | wdr->cmd_iohs[wd_data], 0); |
1960 | memcpy(bf, &val, 2); |
1961 | bf = (char *)bf + 2; |
1962 | len -= 2; |
1963 | } |
1964 | } |
1965 | #endif |
1966 | } |
1967 | |
1968 | static void |
1969 | wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) |
1970 | { |
1971 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); |
1972 | |
1973 | #ifndef __NO_STRICT_ALIGNMENT |
1974 | if ((uintptr_t)bf & 1) |
1975 | goto unaligned; |
1976 | if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) |
1977 | goto unaligned; |
1978 | #endif |
1979 | |
1980 | if (flags & ATA_DRIVE_NOSTREAM) { |
1981 | if (flags & ATA_DRIVE_CAP32) { |
1982 | bus_space_write_multi_4(wdr->data32iot, |
1983 | wdr->data32ioh, 0, bf, len >> 2); |
1984 | bf = (char *)bf + (len & ~3); |
1985 | len &= 3; |
1986 | } |
1987 | if (len) { |
1988 | bus_space_write_multi_2(wdr->cmd_iot, |
1989 | wdr->cmd_iohs[wd_data], 0, bf, len >> 1); |
1990 | } |
1991 | } else { |
1992 | if (flags & ATA_DRIVE_CAP32) { |
1993 | bus_space_write_multi_stream_4(wdr->data32iot, |
1994 | wdr->data32ioh, 0, bf, len >> 2); |
1995 | bf = (char *)bf + (len & ~3); |
1996 | len &= 3; |
1997 | } |
1998 | if (len) { |
1999 | bus_space_write_multi_stream_2(wdr->cmd_iot, |
2000 | wdr->cmd_iohs[wd_data], 0, bf, len >> 1); |
2001 | } |
2002 | } |
2003 | return; |
2004 | |
2005 | #ifndef __NO_STRICT_ALIGNMENT |
2006 | unaligned: |
2007 | if (flags & ATA_DRIVE_NOSTREAM) { |
2008 | if (flags & ATA_DRIVE_CAP32) { |
2009 | while (len > 3) { |
2010 | uint32_t val; |
2011 | |
2012 | memcpy(&val, bf, 4); |
2013 | bus_space_write_4(wdr->data32iot, |
2014 | wdr->data32ioh, 0, val); |
2015 | bf = (char *)bf + 4; |
2016 | len -= 4; |
2017 | } |
2018 | } |
2019 | while (len > 1) { |
2020 | uint16_t val; |
2021 | |
2022 | memcpy(&val, bf, 2); |
2023 | bus_space_write_2(wdr->cmd_iot, |
2024 | wdr->cmd_iohs[wd_data], 0, val); |
2025 | bf = (char *)bf + 2; |
2026 | len -= 2; |
2027 | } |
2028 | } else { |
2029 | if (flags & ATA_DRIVE_CAP32) { |
2030 | while (len > 3) { |
2031 | uint32_t val; |
2032 | |
2033 | memcpy(&val, bf, 4); |
2034 | bus_space_write_stream_4(wdr->data32iot, |
2035 | wdr->data32ioh, 0, val); |
2036 | bf = (char *)bf + 4; |
2037 | len -= 4; |
2038 | } |
2039 | } |
2040 | while (len > 1) { |
2041 | uint16_t val; |
2042 | |
2043 | memcpy(&val, bf, 2); |
2044 | bus_space_write_stream_2(wdr->cmd_iot, |
2045 | wdr->cmd_iohs[wd_data], 0, val); |
2046 | bf = (char *)bf + 2; |
2047 | len -= 2; |
2048 | } |
2049 | } |
2050 | #endif |
2051 | } |
2052 | |