1 | /* $NetBSD: amdpm_smbus.c,v 1.22 2016/02/14 19:54:21 chs Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 2005 Anil Gopinath (anil_public@yahoo.com) |
5 | * All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * 3. The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
23 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
24 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
25 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
26 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
28 | * SUCH DAMAGE. |
29 | */ |
30 | |
31 | /* driver for SMBUS 1.0 host controller found in the |
32 | * AMD-8111 HyperTransport I/O Hub |
33 | */ |
34 | #include <sys/cdefs.h> |
35 | __KERNEL_RCSID(0, "$NetBSD: amdpm_smbus.c,v 1.22 2016/02/14 19:54:21 chs Exp $" ); |
36 | |
37 | #include <sys/param.h> |
38 | #include <sys/systm.h> |
39 | #include <sys/kernel.h> |
40 | #include <sys/device.h> |
41 | #include <sys/mutex.h> |
42 | |
43 | #include <dev/pci/pcireg.h> |
44 | #include <dev/pci/pcivar.h> |
45 | #include <dev/pci/pcidevs.h> |
46 | |
47 | #include <dev/i2c/i2cvar.h> |
48 | #include <dev/i2c/i2c_bitbang.h> |
49 | |
50 | #include <dev/pci/amdpmreg.h> |
51 | #include <dev/pci/amdpmvar.h> |
52 | |
53 | #include <dev/pci/amdpm_smbusreg.h> |
54 | |
55 | static int amdpm_smbus_acquire_bus(void *, int); |
56 | static void amdpm_smbus_release_bus(void *, int); |
57 | static int amdpm_smbus_exec(void *, i2c_op_t, i2c_addr_t, const void *, |
58 | size_t, void *, size_t, int); |
59 | static int amdpm_smbus_check_done(struct amdpm_softc *, i2c_op_t); |
60 | static void amdpm_smbus_clear_gsr(struct amdpm_softc *); |
61 | static uint16_t amdpm_smbus_get_gsr(struct amdpm_softc *); |
62 | static int amdpm_smbus_quick(struct amdpm_softc *, i2c_op_t); |
63 | static int amdpm_smbus_send_1(struct amdpm_softc *, uint8_t, i2c_op_t); |
64 | static int amdpm_smbus_write_1(struct amdpm_softc *, uint8_t, |
65 | uint8_t, i2c_op_t); |
66 | static int amdpm_smbus_receive_1(struct amdpm_softc *, i2c_op_t); |
67 | static int amdpm_smbus_read_1(struct amdpm_softc *sc, uint8_t, i2c_op_t); |
68 | |
69 | void |
70 | amdpm_smbus_attach(struct amdpm_softc *sc) |
71 | { |
72 | struct i2cbus_attach_args iba; |
73 | |
74 | /* register with iic */ |
75 | sc->sc_i2c.ic_cookie = sc; |
76 | sc->sc_i2c.ic_acquire_bus = amdpm_smbus_acquire_bus; |
77 | sc->sc_i2c.ic_release_bus = amdpm_smbus_release_bus; |
78 | sc->sc_i2c.ic_send_start = NULL; |
79 | sc->sc_i2c.ic_send_stop = NULL; |
80 | sc->sc_i2c.ic_initiate_xfer = NULL; |
81 | sc->sc_i2c.ic_read_byte = NULL; |
82 | sc->sc_i2c.ic_write_byte = NULL; |
83 | sc->sc_i2c.ic_exec = amdpm_smbus_exec; |
84 | |
85 | memset(&iba, 0, sizeof(iba)); |
86 | iba.iba_tag = &sc->sc_i2c; |
87 | (void)config_found_ia(sc->sc_dev, "i2cbus" , &iba, iicbus_print); |
88 | } |
89 | |
90 | static int |
91 | amdpm_smbus_acquire_bus(void *cookie, int flags) |
92 | { |
93 | struct amdpm_softc *sc = cookie; |
94 | |
95 | mutex_enter(&sc->sc_mutex); |
96 | return 0; |
97 | } |
98 | |
99 | static void |
100 | amdpm_smbus_release_bus(void *cookie, int flags) |
101 | { |
102 | struct amdpm_softc *sc = cookie; |
103 | |
104 | mutex_exit(&sc->sc_mutex); |
105 | } |
106 | |
107 | static int |
108 | amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, |
109 | size_t cmdlen, void *vbuf, size_t buflen, int flags) |
110 | { |
111 | struct amdpm_softc *sc = (struct amdpm_softc *) cookie; |
112 | sc->sc_smbus_slaveaddr = addr; |
113 | uint8_t *p = vbuf; |
114 | int rv; |
115 | |
116 | if ((cmdlen == 0) && (buflen == 0)) |
117 | return amdpm_smbus_quick(sc, op); |
118 | |
119 | if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { |
120 | rv = amdpm_smbus_receive_1(sc, op); |
121 | if (rv == -1) |
122 | return -1; |
123 | *p = (uint8_t)rv; |
124 | return 0; |
125 | } |
126 | |
127 | if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { |
128 | rv = amdpm_smbus_read_1(sc, *(const uint8_t *)cmd, op); |
129 | if (rv == -1) |
130 | return -1; |
131 | *p = (uint8_t)rv; |
132 | return 0; |
133 | } |
134 | |
135 | if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) |
136 | return amdpm_smbus_send_1(sc, *(uint8_t*)vbuf, op); |
137 | |
138 | if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) |
139 | return amdpm_smbus_write_1(sc, |
140 | *(const uint8_t*)cmd, |
141 | *(uint8_t*)vbuf, |
142 | op); |
143 | |
144 | return -1; |
145 | } |
146 | |
147 | static int |
148 | amdpm_smbus_check_done(struct amdpm_softc *sc, i2c_op_t op) |
149 | { |
150 | int i; |
151 | |
152 | for (i = 0; i < 1000; i++) { |
153 | /* check gsr and wait till cycle is done */ |
154 | uint16_t data = amdpm_smbus_get_gsr(sc); |
155 | if (data & AMDPM_8111_GSR_CYCLE_DONE) |
156 | return 0; |
157 | } |
158 | |
159 | if (!(op & I2C_F_POLL)) |
160 | delay(1); |
161 | |
162 | return -1; |
163 | } |
164 | |
165 | |
166 | static void |
167 | amdpm_smbus_clear_gsr(struct amdpm_softc *sc) |
168 | { |
169 | /* clear register */ |
170 | uint16_t data = 0xFFFF; |
171 | int off = (sc->sc_nforce ? 0xe0 : 0); |
172 | bus_space_write_2(sc->sc_iot, sc->sc_ioh, |
173 | AMDPM_8111_SMBUS_STAT - off, data); |
174 | } |
175 | |
176 | static uint16_t |
177 | amdpm_smbus_get_gsr(struct amdpm_softc *sc) |
178 | { |
179 | int off = (sc->sc_nforce ? 0xe0 : 0); |
180 | return bus_space_read_2(sc->sc_iot, sc->sc_ioh, |
181 | AMDPM_8111_SMBUS_STAT - off); |
182 | } |
183 | |
184 | static int |
185 | amdpm_smbus_quick(struct amdpm_softc *sc, i2c_op_t op) |
186 | { |
187 | uint16_t data = 0; |
188 | int off = (sc->sc_nforce ? 0xe0 : 0); |
189 | |
190 | /* first clear gsr */ |
191 | amdpm_smbus_clear_gsr(sc); |
192 | |
193 | /* write smbus slave address and read/write bit to register */ |
194 | data = sc->sc_smbus_slaveaddr; |
195 | data <<= 1; |
196 | if (I2C_OP_READ_P(op)) |
197 | data |= AMDPM_8111_SMBUS_READ; |
198 | |
199 | bus_space_write_1(sc->sc_iot, sc->sc_ioh, |
200 | AMDPM_8111_SMBUS_HOSTADDR - off, data); |
201 | |
202 | /* host start */ |
203 | bus_space_write_2(sc->sc_iot, sc->sc_ioh, |
204 | AMDPM_8111_SMBUS_CTRL - off, |
205 | AMDPM_8111_SMBUS_GSR_QUICK); |
206 | |
207 | return amdpm_smbus_check_done(sc, op); |
208 | } |
209 | |
210 | static int |
211 | amdpm_smbus_send_1(struct amdpm_softc *sc, uint8_t val, i2c_op_t op) |
212 | { |
213 | uint16_t data = 0; |
214 | int off = (sc->sc_nforce ? 0xe0 : 0); |
215 | |
216 | /* first clear gsr */ |
217 | amdpm_smbus_clear_gsr(sc); |
218 | |
219 | /* write smbus slave address to register */ |
220 | data = sc->sc_smbus_slaveaddr; |
221 | data <<= 1; |
222 | data |= AMDPM_8111_SMBUS_SEND; |
223 | bus_space_write_1(sc->sc_iot, sc->sc_ioh, |
224 | AMDPM_8111_SMBUS_HOSTADDR - off, data); |
225 | |
226 | data = val; |
227 | /* store data */ |
228 | bus_space_write_2(sc->sc_iot, sc->sc_ioh, |
229 | AMDPM_8111_SMBUS_HOSTDATA - off, data); |
230 | /* host start */ |
231 | bus_space_write_2(sc->sc_iot, sc->sc_ioh, |
232 | AMDPM_8111_SMBUS_CTRL - off, |
233 | AMDPM_8111_SMBUS_GSR_SB); |
234 | |
235 | return amdpm_smbus_check_done(sc, op); |
236 | } |
237 | |
238 | |
239 | static int |
240 | amdpm_smbus_write_1(struct amdpm_softc *sc, uint8_t cmd, uint8_t val, |
241 | i2c_op_t op) |
242 | { |
243 | uint16_t data = 0; |
244 | int off = (sc->sc_nforce ? 0xe0 : 0); |
245 | |
246 | /* first clear gsr */ |
247 | amdpm_smbus_clear_gsr(sc); |
248 | |
249 | data = sc->sc_smbus_slaveaddr; |
250 | data <<= 1; |
251 | data |= AMDPM_8111_SMBUS_WRITE; |
252 | bus_space_write_1(sc->sc_iot, sc->sc_ioh, |
253 | AMDPM_8111_SMBUS_HOSTADDR - off, data); |
254 | |
255 | data = val; |
256 | /* store cmd */ |
257 | bus_space_write_1(sc->sc_iot, sc->sc_ioh, |
258 | AMDPM_8111_SMBUS_HOSTCMD - off, cmd); |
259 | /* store data */ |
260 | bus_space_write_2(sc->sc_iot, sc->sc_ioh, |
261 | AMDPM_8111_SMBUS_HOSTDATA - off, data); |
262 | /* host start */ |
263 | bus_space_write_2(sc->sc_iot, sc->sc_ioh, |
264 | AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_WB); |
265 | |
266 | return amdpm_smbus_check_done(sc, op); |
267 | } |
268 | |
269 | static int |
270 | amdpm_smbus_receive_1(struct amdpm_softc *sc, i2c_op_t op) |
271 | { |
272 | uint16_t data = 0; |
273 | int off = (sc->sc_nforce ? 0xe0 : 0); |
274 | |
275 | /* first clear gsr */ |
276 | amdpm_smbus_clear_gsr(sc); |
277 | |
278 | /* write smbus slave address to register */ |
279 | data = sc->sc_smbus_slaveaddr; |
280 | data <<= 1; |
281 | data |= AMDPM_8111_SMBUS_RX; |
282 | bus_space_write_1(sc->sc_iot, sc->sc_ioh, |
283 | AMDPM_8111_SMBUS_HOSTADDR - off, data); |
284 | |
285 | /* start smbus cycle */ |
286 | bus_space_write_2(sc->sc_iot, sc->sc_ioh, |
287 | AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RXB); |
288 | |
289 | /* check for errors */ |
290 | if (amdpm_smbus_check_done(sc, op) < 0) |
291 | return -1; |
292 | |
293 | /* read data */ |
294 | data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, |
295 | AMDPM_8111_SMBUS_HOSTDATA - off); |
296 | uint8_t ret = (uint8_t)(data & 0x00FF); |
297 | return ret; |
298 | } |
299 | |
300 | static int |
301 | amdpm_smbus_read_1(struct amdpm_softc *sc, uint8_t cmd, i2c_op_t op) |
302 | { |
303 | uint16_t data = 0; |
304 | uint8_t ret; |
305 | int off = (sc->sc_nforce ? 0xe0 : 0); |
306 | |
307 | /* first clear gsr */ |
308 | amdpm_smbus_clear_gsr(sc); |
309 | |
310 | /* write smbus slave address to register */ |
311 | data = sc->sc_smbus_slaveaddr; |
312 | data <<= 1; |
313 | data |= AMDPM_8111_SMBUS_READ; |
314 | bus_space_write_1(sc->sc_iot, sc->sc_ioh, |
315 | AMDPM_8111_SMBUS_HOSTADDR - off, data); |
316 | |
317 | /* store cmd */ |
318 | bus_space_write_1(sc->sc_iot, sc->sc_ioh, |
319 | AMDPM_8111_SMBUS_HOSTCMD - off, cmd); |
320 | /* host start */ |
321 | bus_space_write_2(sc->sc_iot, sc->sc_ioh, |
322 | AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RB); |
323 | |
324 | /* check for errors */ |
325 | if (amdpm_smbus_check_done(sc, op) < 0) |
326 | return -1; |
327 | |
328 | /* store data */ |
329 | data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, |
330 | AMDPM_8111_SMBUS_HOSTDATA - off); |
331 | ret = (uint8_t)(data & 0x00FF); |
332 | return ret; |
333 | } |
334 | |