1 | /* $NetBSD: if_ath_pci.c,v 1.48 2014/03/29 19:28:24 christos Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting |
5 | * All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer, |
12 | * without modification. |
13 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer |
14 | * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any |
15 | * redistribution must be conditioned upon including a substantially |
16 | * similar Disclaimer requirement for further binary redistribution. |
17 | * 3. Neither the names of the above-listed copyright holders nor the names |
18 | * of any contributors may be used to endorse or promote products derived |
19 | * from this software without specific prior written permission. |
20 | * |
21 | * Alternatively, this software may be distributed under the terms of the |
22 | * GNU General Public License ("GPL") version 2 as published by the Free |
23 | * Software Foundation. |
24 | * |
25 | * NO WARRANTY |
26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
27 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
28 | * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY |
29 | * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL |
30 | * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, |
31 | * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
32 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
33 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER |
34 | * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
35 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
36 | * THE POSSIBILITY OF SUCH DAMAGES. |
37 | */ |
38 | /* |
39 | * Copyright (c) 2003 |
40 | * Ichiro FUKUHARA <ichiro@ichiro.org>. |
41 | * All rights reserved. |
42 | * |
43 | * Redistribution and use in source and binary forms, with or without |
44 | * modification, are permitted provided that the following conditions |
45 | * are met: |
46 | * 1. Redistributions of source code must retain the above copyright |
47 | * notice, this list of conditions and the following disclaimer. |
48 | * 2. Redistributions in binary form must reproduce the above copyright |
49 | * notice, this list of conditions and the following disclaimer in the |
50 | * documentation and/or other materials provided with the distribution. |
51 | * |
52 | * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR |
53 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
54 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
55 | * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR |
56 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
57 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
58 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
59 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
60 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
61 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
62 | * SUCH DAMAGE. |
63 | */ |
64 | |
65 | #include <sys/cdefs.h> |
66 | __KERNEL_RCSID(0, "$NetBSD: if_ath_pci.c,v 1.48 2014/03/29 19:28:24 christos Exp $" ); |
67 | |
68 | /* |
69 | * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver. |
70 | */ |
71 | |
72 | #include <sys/param.h> |
73 | #include <sys/systm.h> |
74 | #include <sys/kernel.h> |
75 | #include <sys/errno.h> |
76 | #include <sys/device.h> |
77 | #include <sys/module.h> |
78 | |
79 | #include <external/isc/atheros_hal/dist/ah.h> |
80 | |
81 | #include <dev/ic/ath_netbsd.h> |
82 | #include <dev/ic/athvar.h> |
83 | |
84 | #include <dev/pci/pcivar.h> |
85 | #include <dev/pci/pcireg.h> |
86 | #include <dev/pci/pcidevs.h> |
87 | |
88 | /* |
89 | * PCI configuration space registers |
90 | */ |
91 | #define ATH_PCI_MMBA PCI_BAR(0) /* memory mapped base */ |
92 | |
93 | struct ath_pci_softc { |
94 | struct ath_softc sc_sc; |
95 | pci_chipset_tag_t sc_pc; |
96 | pcitag_t sc_tag; |
97 | pci_intr_handle_t sc_pih; |
98 | void *sc_ih; |
99 | bus_space_tag_t sc_iot; |
100 | bus_space_handle_t sc_ioh; |
101 | bus_size_t sc_mapsz; |
102 | }; |
103 | |
104 | static void ath_pci_attach(device_t, device_t, void *); |
105 | static int ath_pci_detach(device_t, int); |
106 | static int ath_pci_match(device_t, cfdata_t, void *); |
107 | static bool ath_pci_setup(struct ath_pci_softc *); |
108 | |
109 | CFATTACH_DECL_NEW(ath_pci, sizeof(struct ath_pci_softc), |
110 | ath_pci_match, ath_pci_attach, ath_pci_detach, NULL); |
111 | |
112 | static int |
113 | ath_pci_match(device_t parent, cfdata_t match, void *aux) |
114 | { |
115 | const char *devname; |
116 | struct pci_attach_args *pa = aux; |
117 | |
118 | devname = ath_hal_probe(PCI_VENDOR(pa->pa_id), PCI_PRODUCT(pa->pa_id)); |
119 | return (devname != NULL) ? 1 : 0; |
120 | } |
121 | |
122 | static bool |
123 | ath_pci_suspend(device_t self, const pmf_qual_t *qual) |
124 | { |
125 | struct ath_pci_softc *sc = device_private(self); |
126 | |
127 | ath_suspend(&sc->sc_sc); |
128 | if (sc->sc_ih != NULL) { |
129 | pci_intr_disestablish(sc->sc_pc, sc->sc_ih); |
130 | sc->sc_ih = NULL; |
131 | } |
132 | return true; |
133 | } |
134 | |
135 | static bool |
136 | ath_pci_resume(device_t self, const pmf_qual_t *qual) |
137 | { |
138 | struct ath_pci_softc *sc = device_private(self); |
139 | |
140 | sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pih, IPL_NET, ath_intr, |
141 | &sc->sc_sc); |
142 | if (sc->sc_ih == NULL) { |
143 | aprint_error_dev(self, "couldn't map interrupt\n" ); |
144 | return false; |
145 | } |
146 | return ath_resume(&sc->sc_sc); |
147 | } |
148 | |
149 | static void |
150 | ath_pci_attach(device_t parent, device_t self, void *aux) |
151 | { |
152 | struct ath_pci_softc *psc = device_private(self); |
153 | struct ath_softc *sc = &psc->sc_sc; |
154 | struct pci_attach_args *pa = aux; |
155 | pci_chipset_tag_t pc = pa->pa_pc; |
156 | const char *intrstr = NULL; |
157 | const char *devname; |
158 | pcireg_t mem_type; |
159 | char intrbuf[PCI_INTRSTR_LEN]; |
160 | |
161 | sc->sc_dev = self; |
162 | sc->sc_dmat = pa->pa_dmat; |
163 | psc->sc_pc = pc; |
164 | psc->sc_tag = pa->pa_tag; |
165 | |
166 | devname = ath_hal_probe(PCI_VENDOR(pa->pa_id), PCI_PRODUCT(pa->pa_id)); |
167 | aprint_normal(": %s\n" , devname); |
168 | |
169 | if (!ath_pci_setup(psc)) |
170 | goto bad; |
171 | |
172 | /* |
173 | * Setup memory-mapping of PCI registers. |
174 | */ |
175 | mem_type = pci_mapreg_type(pc, pa->pa_tag, ATH_PCI_MMBA); |
176 | if (mem_type != PCI_MAPREG_TYPE_MEM && |
177 | mem_type != PCI_MAPREG_MEM_TYPE_64BIT) { |
178 | aprint_error_dev(self, "bad pci register type %d\n" , |
179 | (int)mem_type); |
180 | goto bad; |
181 | } |
182 | if (pci_mapreg_map(pa, ATH_PCI_MMBA, mem_type, 0, &psc->sc_iot, |
183 | &psc->sc_ioh, NULL, &psc->sc_mapsz) != 0) { |
184 | aprint_error_dev(self, "cannot map register space\n" ); |
185 | goto bad; |
186 | } |
187 | |
188 | sc->sc_st = HALTAG(psc->sc_iot); |
189 | sc->sc_sh = HALHANDLE(psc->sc_ioh); |
190 | |
191 | /* |
192 | * Arrange interrupt line. |
193 | */ |
194 | if (pci_intr_map(pa, &psc->sc_pih)) { |
195 | aprint_error("couldn't map interrupt\n" ); |
196 | goto bad1; |
197 | } |
198 | |
199 | intrstr = pci_intr_string(pc, psc->sc_pih, intrbuf, sizeof(intrbuf)); |
200 | psc->sc_ih = pci_intr_establish(pc, psc->sc_pih, IPL_NET, ath_intr, sc); |
201 | if (psc->sc_ih == NULL) { |
202 | aprint_error("couldn't map interrupt\n" ); |
203 | goto bad1; |
204 | } |
205 | |
206 | aprint_verbose_dev(self, "interrupting at %s\n" , intrstr); |
207 | |
208 | if (ath_attach(PCI_PRODUCT(pa->pa_id), sc) != 0) |
209 | goto bad3; |
210 | |
211 | if (pmf_device_register(self, ath_pci_suspend, ath_pci_resume)) { |
212 | pmf_class_network_register(self, &sc->sc_if); |
213 | pmf_device_suspend(self, &sc->sc_qual); |
214 | } else |
215 | aprint_error_dev(self, "couldn't establish power handler\n" ); |
216 | return; |
217 | bad3: |
218 | pci_intr_disestablish(pc, psc->sc_ih); |
219 | psc->sc_ih = NULL; |
220 | bad1: |
221 | bus_space_unmap(psc->sc_iot, psc->sc_ioh, psc->sc_mapsz); |
222 | psc->sc_mapsz = 0; |
223 | bad: |
224 | return; |
225 | } |
226 | |
227 | static int |
228 | ath_pci_detach(device_t self, int flags) |
229 | { |
230 | struct ath_pci_softc *psc = device_private(self); |
231 | int rv; |
232 | |
233 | if ((rv = ath_detach(&psc->sc_sc)) != 0) |
234 | return rv; |
235 | |
236 | pmf_device_deregister(self); |
237 | |
238 | if (psc->sc_ih != NULL) { |
239 | pci_intr_disestablish(psc->sc_pc, psc->sc_ih); |
240 | psc->sc_ih = NULL; |
241 | } |
242 | |
243 | if (psc->sc_mapsz != 0) { |
244 | bus_space_unmap(psc->sc_iot, psc->sc_ioh, psc->sc_mapsz); |
245 | psc->sc_mapsz = 0; |
246 | } |
247 | |
248 | return 0; |
249 | } |
250 | |
251 | static bool |
252 | ath_pci_setup(struct ath_pci_softc *sc) |
253 | { |
254 | int rc; |
255 | pcireg_t bhlc, csr, icr, lattimer; |
256 | |
257 | if ((rc = pci_set_powerstate(sc->sc_pc, sc->sc_tag, PCI_PWR_D0)) != 0) |
258 | aprint_debug("%s: pci_set_powerstate %d\n" , __func__, rc); |
259 | /* |
260 | * Enable memory mapping and bus mastering. |
261 | */ |
262 | csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); |
263 | csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; |
264 | pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, csr); |
265 | csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); |
266 | |
267 | if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { |
268 | aprint_error_dev(sc->sc_sc.sc_dev, |
269 | "couldn't enable memory mapping\n" ); |
270 | return false; |
271 | } |
272 | if ((csr & PCI_COMMAND_MASTER_ENABLE) == 0) { |
273 | aprint_error_dev(sc->sc_sc.sc_dev, |
274 | "couldn't enable bus mastering\n" ); |
275 | return false; |
276 | } |
277 | |
278 | /* |
279 | * XXX Both this comment and code are replicated in |
280 | * XXX cardbus_rescan(). |
281 | * |
282 | * Make sure the latency timer is set to some reasonable |
283 | * value. |
284 | * |
285 | * I will set the initial value of the Latency Timer here. |
286 | * |
287 | * While a PCI device owns the bus, its Latency Timer counts |
288 | * down bus cycles from its initial value to 0. Minimum |
289 | * Grant tells for how long the device wants to own the |
290 | * bus once it gets access, in units of 250ns. |
291 | * |
292 | * On a 33 MHz bus, there are 8 cycles per 250ns. So I |
293 | * multiply the Minimum Grant by 8 to find out the initial |
294 | * value of the Latency Timer. |
295 | * |
296 | * I never set a Latency Timer less than 0x10, since that |
297 | * is what the old code did. |
298 | */ |
299 | bhlc = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BHLC_REG); |
300 | icr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_INTERRUPT_REG); |
301 | lattimer = MAX(0x10, MIN(0xf8, 8 * PCI_MIN_GNT(icr))); |
302 | if (PCI_LATTIMER(bhlc) < lattimer) { |
303 | bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); |
304 | bhlc |= (lattimer << PCI_LATTIMER_SHIFT); |
305 | pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BHLC_REG, bhlc); |
306 | } |
307 | return true; |
308 | } |
309 | |
310 | MODULE(MODULE_CLASS_DRIVER, if_ath_pci, "ath,pci" ); |
311 | |
312 | #ifdef _MODULE |
313 | #include "ioconf.c" |
314 | #endif |
315 | |
316 | static int |
317 | if_ath_pci_modcmd(modcmd_t cmd, void *opaque) |
318 | { |
319 | int error = 0; |
320 | |
321 | switch (cmd) { |
322 | case MODULE_CMD_INIT: |
323 | #ifdef _MODULE |
324 | error = config_init_component(cfdriver_ioconf_if_ath_pci, |
325 | cfattach_ioconf_if_ath_pci, cfdata_ioconf_if_ath_pci); |
326 | #endif |
327 | return error; |
328 | case MODULE_CMD_FINI: |
329 | #ifdef _MODULE |
330 | error = config_fini_component(cfdriver_ioconf_if_ath_pci, |
331 | cfattach_ioconf_if_ath_pci, cfdata_ioconf_if_ath_pci); |
332 | #endif |
333 | return error; |
334 | default: |
335 | return ENOTTY; |
336 | } |
337 | } |
338 | |