1 | /* $NetBSD: smc83c170var.h,v 1.14 2009/09/03 14:13:16 tsutsui Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, |
9 | * NASA Ames Research Center. |
10 | * |
11 | * Redistribution and use in source and binary forms, with or without |
12 | * modification, are permitted provided that the following conditions |
13 | * are met: |
14 | * 1. Redistributions of source code must retain the above copyright |
15 | * notice, this list of conditions and the following disclaimer. |
16 | * 2. Redistributions in binary form must reproduce the above copyright |
17 | * notice, this list of conditions and the following disclaimer in the |
18 | * documentation and/or other materials provided with the distribution. |
19 | * |
20 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
21 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
22 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
23 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
24 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
30 | * POSSIBILITY OF SUCH DAMAGE. |
31 | */ |
32 | |
33 | #ifndef _DEV_IC_SMC83C170VAR_H_ |
34 | #define _DEV_IC_SMC83C170VAR_H_ |
35 | |
36 | #include <sys/callout.h> |
37 | |
38 | /* |
39 | * Misc. definitions for the Standard Microsystems Corp. 83C170 |
40 | * Ethernet PCI Integrated Controller (EPIC/100) driver. |
41 | */ |
42 | |
43 | /* |
44 | * Transmit descriptor list size. |
45 | */ |
46 | #define EPIC_NTXDESC 128 |
47 | #define EPIC_NTXDESC_MASK (EPIC_NTXDESC - 1) |
48 | #define EPIC_NEXTTX(x) ((x + 1) & EPIC_NTXDESC_MASK) |
49 | |
50 | /* |
51 | * Receive descriptor list size. |
52 | */ |
53 | #define EPIC_NRXDESC 64 |
54 | #define EPIC_NRXDESC_MASK (EPIC_NRXDESC - 1) |
55 | #define EPIC_NEXTRX(x) ((x + 1) & EPIC_NRXDESC_MASK) |
56 | |
57 | /* |
58 | * Control structures are DMA'd to the EPIC chip. We allocate them in |
59 | * a single clump that maps to a single DMA segment to make several things |
60 | * easier. |
61 | */ |
62 | struct epic_control_data { |
63 | /* |
64 | * The transmit descriptors. |
65 | */ |
66 | struct epic_txdesc ecd_txdescs[EPIC_NTXDESC]; |
67 | |
68 | /* |
69 | * The receive descriptors. |
70 | */ |
71 | struct epic_rxdesc ecd_rxdescs[EPIC_NRXDESC]; |
72 | |
73 | /* |
74 | * The transmit fraglists. |
75 | */ |
76 | struct epic_fraglist ecd_txfrags[EPIC_NTXDESC]; |
77 | }; |
78 | |
79 | #define EPIC_CDOFF(x) offsetof(struct epic_control_data, x) |
80 | #define EPIC_CDTXOFF(x) EPIC_CDOFF(ecd_txdescs[(x)]) |
81 | #define EPIC_CDRXOFF(x) EPIC_CDOFF(ecd_rxdescs[(x)]) |
82 | #define EPIC_CDFLOFF(x) EPIC_CDOFF(ecd_txfrags[(x)]) |
83 | |
84 | /* |
85 | * Software state for transmit and receive desciptors. |
86 | */ |
87 | struct epic_descsoft { |
88 | struct mbuf *ds_mbuf; /* head of mbuf chain */ |
89 | bus_dmamap_t ds_dmamap; /* our DMA map */ |
90 | }; |
91 | |
92 | /* |
93 | * Software state per device. |
94 | */ |
95 | struct epic_softc { |
96 | device_t sc_dev; /* generic device information */ |
97 | bus_space_tag_t sc_st; /* bus space tag */ |
98 | bus_space_handle_t sc_sh; /* bus space handle */ |
99 | bus_dma_tag_t sc_dmat; /* bus DMA tag */ |
100 | struct ethercom sc_ethercom; /* ethernet common data */ |
101 | |
102 | int sc_hwflags; /* info about board */ |
103 | #define EPIC_HAS_BNC 0x01 /* BNC on serial interface */ |
104 | #define EPIC_HAS_MII_FIBER 0x02 /* fiber on MII lxtphy */ |
105 | #define EPIC_DUPLEXLED_ON_694 0x04 /* duplex LED by software */ |
106 | |
107 | struct mii_data sc_mii; /* MII/media information */ |
108 | struct callout sc_mii_callout; /* MII callout */ |
109 | |
110 | bus_dmamap_t sc_cddmamap; /* control data DMA map */ |
111 | #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr |
112 | bus_dmamap_t sc_nulldmamap; /* DMA map for the pad buffer */ |
113 | #define sc_nulldma sc_nulldmamap->dm_segs[0].ds_addr |
114 | |
115 | /* |
116 | * Software state for transmit and receive descriptors. |
117 | */ |
118 | struct epic_descsoft sc_txsoft[EPIC_NTXDESC]; |
119 | struct epic_descsoft sc_rxsoft[EPIC_NRXDESC]; |
120 | |
121 | /* |
122 | * Control data structures. |
123 | */ |
124 | struct epic_control_data *sc_control_data; |
125 | |
126 | int sc_txpending; /* number of TX requests pending */ |
127 | int sc_txdirty; /* first dirty TX descriptor */ |
128 | int sc_txlast; /* last used TX descriptor */ |
129 | |
130 | int sc_rxptr; /* next ready RX descriptor */ |
131 | |
132 | u_int sc_serinst; /* ifmedia instance for serial mode */ |
133 | }; |
134 | |
135 | #define EPIC_CDTXADDR(sc, x) ((sc)->sc_cddma + EPIC_CDTXOFF((x))) |
136 | #define EPIC_CDRXADDR(sc, x) ((sc)->sc_cddma + EPIC_CDRXOFF((x))) |
137 | #define EPIC_CDFLADDR(sc, x) ((sc)->sc_cddma + EPIC_CDFLOFF((x))) |
138 | |
139 | #define EPIC_CDTX(sc, x) (&(sc)->sc_control_data->ecd_txdescs[(x)]) |
140 | #define EPIC_CDRX(sc, x) (&(sc)->sc_control_data->ecd_rxdescs[(x)]) |
141 | #define EPIC_CDFL(sc, x) (&(sc)->sc_control_data->ecd_txfrags[(x)]) |
142 | |
143 | #define EPIC_DSTX(sc, x) (&(sc)->sc_txsoft[(x)]) |
144 | #define EPIC_DSRX(sc, x) (&(sc)->sc_rxsoft[(x)]) |
145 | |
146 | #define EPIC_CDTXSYNC(sc, x, ops) \ |
147 | bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ |
148 | EPIC_CDTXOFF((x)), sizeof(struct epic_txdesc), (ops)) |
149 | |
150 | #define EPIC_CDRXSYNC(sc, x, ops) \ |
151 | bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ |
152 | EPIC_CDRXOFF((x)), sizeof(struct epic_rxdesc), (ops)) |
153 | |
154 | #define EPIC_CDFLSYNC(sc, x, ops) \ |
155 | bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ |
156 | EPIC_CDFLOFF((x)), sizeof(struct epic_fraglist), (ops)) |
157 | |
158 | #define EPIC_INIT_RXDESC(sc, x) \ |
159 | do { \ |
160 | struct epic_descsoft *__ds = EPIC_DSRX((sc), (x)); \ |
161 | struct epic_rxdesc *__rxd = EPIC_CDRX((sc), (x)); \ |
162 | struct mbuf *__m = __ds->ds_mbuf; \ |
163 | \ |
164 | /* \ |
165 | * Note we scoot the packet forward 2 bytes in the buffer \ |
166 | * so that the payload after the Ethernet header is aligned \ |
167 | * to a 4 byte boundary. \ |
168 | */ \ |
169 | __m->m_data = __m->m_ext.ext_buf + 2; \ |
170 | __rxd->er_bufaddr = __ds->ds_dmamap->dm_segs[0].ds_addr + 2; \ |
171 | __rxd->er_control = RXCTL_BUFLENGTH(__m->m_ext.ext_size - 2); \ |
172 | __rxd->er_nextdesc = EPIC_CDRXADDR((sc), EPIC_NEXTRX((x))); \ |
173 | __rxd->er_rxstatus = ER_RXSTAT_OWNER; \ |
174 | EPIC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ |
175 | } while (/* CONSTCOND */ 0) |
176 | |
177 | #ifdef _KERNEL |
178 | void epic_attach(struct epic_softc *); |
179 | int epic_intr(void *); |
180 | #endif /* _KERNEL */ |
181 | |
182 | #endif /* _DEV_IC_SMC83C170VAR_H_ */ |
183 | |