1/* $NetBSD: if_bnxreg.h,v 1.18 2014/07/01 17:11:35 msaitoh Exp $ */
2/* $OpenBSD: if_bnxreg.h,v 1.33 2009/09/05 16:02:28 claudio Exp $ */
3
4/*-
5 * Copyright (c) 2006 Broadcom Corporation
6 * David Christensen <davidch@broadcom.com>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written consent.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.4 2006/05/04 00:34:07 mjacob Exp $
33 */
34
35#define ETHER_ALIGN 2
36
37/* General controller flags -- bnx_flags element in bnx_softc */
38#define BNX_PCIX_FLAG 0x01
39#define BNX_PCI_32BIT_FLAG 0x02
40#define BNX_ONE_TDMA_FLAG 0x04 /* Deprecated */
41#define BNX_NO_WOL_FLAG 0x08
42#define BNX_USING_DAC_FLAG 0x10
43#define BNX_USING_MSI_FLAG 0x20
44#define BNX_MFW_ENABLE_FLAG 0x40
45#define BNX_ACTIVE_FLAG 0x80
46#define BNX_ALLOC_PKTS_FLAG 0x100
47#define BNX_PCIE_FLAG 0x200
48
49/* PHY specific flags -- bnx_phy_flags element in bnx_softc */
50#define BNX_PHY_SERDES_FLAG 0x001
51#define BNX_PHY_CRC_FIX_FLAG 0x002
52#define BNX_PHY_PARALLEL_DETECT_FLAG 0x004
53#define BNX_PHY_2_5G_CAPABLE_FLAG 0x008
54#define BNX_PHY_INT_MODE_MASK_FLAG 0x300
55#define BNX_PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
56#define BNX_PHY_INT_MODE_LINK_READY_FLAG 0x200
57#define BNX_PHY_IEEE_CLAUSE_45_FLAG 0x400
58
59/****************************************************************************/
60/* Debugging macros and definitions. */
61/****************************************************************************/
62#define BNX_CP_LOAD 0x00000001
63#define BNX_CP_SEND 0x00000002
64#define BNX_CP_RECV 0x00000004
65#define BNX_CP_INTR 0x00000008
66#define BNX_CP_UNLOAD 0x00000010
67#define BNX_CP_RESET 0x00000020
68#define BNX_CP_ALL 0x00FFFFFF
69
70#define BNX_CP_MASK 0x00FFFFFF
71
72#define BNX_LEVEL_FATAL 0x00000000
73#define BNX_LEVEL_WARN 0x01000000
74#define BNX_LEVEL_INFO 0x02000000
75#define BNX_LEVEL_VERBOSE 0x03000000
76#define BNX_LEVEL_EXCESSIVE 0x04000000
77
78#define BNX_LEVEL_MASK 0xFF000000
79
80#define BNX_WARN_LOAD (BNX_CP_LOAD | BNX_LEVEL_WARN)
81#define BNX_INFO_LOAD (BNX_CP_LOAD | BNX_LEVEL_INFO)
82#define BNX_VERBOSE_LOAD (BNX_CP_LOAD | BNX_LEVEL_VERBOSE)
83#define BNX_EXCESSIVE_LOAD (BNX_CP_LOAD | BNX_LEVEL_EXCESSIVE)
84
85#define BNX_WARN_SEND (BNX_CP_SEND | BNX_LEVEL_WARN)
86#define BNX_INFO_SEND (BNX_CP_SEND | BNX_LEVEL_INFO)
87#define BNX_VERBOSE_SEND (BNX_CP_SEND | BNX_LEVEL_VERBOSE)
88#define BNX_EXCESSIVE_SEND (BNX_CP_SEND | BNX_LEVEL_EXCESSIVE)
89
90#define BNX_WARN_RECV (BNX_CP_RECV | BNX_LEVEL_WARN)
91#define BNX_INFO_RECV (BNX_CP_RECV | BNX_LEVEL_INFO)
92#define BNX_VERBOSE_RECV (BNX_CP_RECV | BNX_LEVEL_VERBOSE)
93#define BNX_EXCESSIVE_RECV (BNX_CP_RECV | BNX_LEVEL_EXCESSIVE)
94
95#define BNX_WARN_INTR (BNX_CP_INTR | BNX_LEVEL_WARN)
96#define BNX_INFO_INTR (BNX_CP_INTR | BNX_LEVEL_INFO)
97#define BNX_VERBOSE_INTR (BNX_CP_INTR | BNX_LEVEL_VERBOSE)
98#define BNX_EXCESSIVE_INTR (BNX_CP_INTR | BNX_LEVEL_EXCESSIVE)
99
100#define BNX_WARN_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_WARN)
101#define BNX_INFO_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_INFO)
102#define BNX_VERBOSE_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_VERBOSE)
103#define BNX_EXCESSIVE_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_EXCESSIVE)
104
105#define BNX_WARN_RESET (BNX_CP_RESET | BNX_LEVEL_WARN)
106#define BNX_INFO_RESET (BNX_CP_RESET | BNX_LEVEL_INFO)
107#define BNX_VERBOSE_RESET (BNX_CP_RESET | BNX_LEVEL_VERBOSE)
108#define BNX_EXCESSIVE_RESET (BNX_CP_RESET | BNX_LEVEL_EXCESSIVE)
109
110#define BNX_FATAL (BNX_CP_ALL | BNX_LEVEL_FATAL)
111#define BNX_WARN (BNX_CP_ALL | BNX_LEVEL_WARN)
112#define BNX_INFO (BNX_CP_ALL | BNX_LEVEL_INFO)
113#define BNX_VERBOSE (BNX_CP_ALL | BNX_LEVEL_VERBOSE)
114#define BNX_EXCESSIVE (BNX_CP_ALL | BNX_LEVEL_EXCESSIVE)
115
116#define BNX_CODE_PATH(cp) ((cp & BNX_CP_MASK) & bnx_debug)
117#define BNX_MSG_LEVEL(lv) ((lv & BNX_LEVEL_MASK) <= (bnx_debug & BNX_LEVEL_MASK))
118#define BNX_LOG_MSG(m) (BNX_CODE_PATH(m) && BNX_MSG_LEVEL(m))
119
120#ifdef BNX_DEBUG
121
122/* Print a message based on the logging level and code path. */
123#define DBPRINT(sc, level, format, args...) \
124 if (BNX_LOG_MSG(level)) { \
125 aprint_debug_dev(sc->bnx_dev, format, ## args); \
126 }
127
128/* Runs a particular command based on the logging level and code path. */
129#define DBRUN(m, args...) \
130 if (BNX_LOG_MSG(m)) { \
131 args; \
132 }
133
134/* Runs a particular command based on the logging level. */
135#define DBRUNLV(level, args...) \
136 if (BNX_MSG_LEVEL(level)) { \
137 args; \
138 }
139
140/* Runs a particular command based on the code path. */
141#define DBRUNCP(cp, args...) \
142 if (BNX_CODE_PATH(cp)) { \
143 args; \
144 }
145
146/* Runs a particular command based on a condition. */
147#define DBRUNIF(cond, args...) \
148 if (cond) { \
149 args; \
150 }
151#if 0
152/* Needed for random() function which is only used in debugging. */
153#include <sys/random.h>
154#endif
155
156/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
157#define DB_RANDOMFALSE(defects) (random() > defects)
158#define DB_OR_RANDOMFALSE(defects) || (random() > defects)
159#define DB_AND_RANDOMFALSE(defects) && (random() > ddfects)
160
161/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
162#define DB_RANDOMTRUE(defects) (random() < defects)
163#define DB_OR_RANDOMTRUE(defects) || (random() < defects)
164#define DB_AND_RANDOMTRUE(defects) && (random() < defects)
165
166#else
167
168#define DBPRINT(level, format, ...)
169#define DBRUN(m, ...)
170#define DBRUNLV(level, ...)
171#define DBRUNCP(cp, ...)
172#define DBRUNIF(cond, ...)
173#define DB_RANDOMFALSE(defects)
174#define DB_OR_RANDOMFALSE(percent)
175#define DB_AND_RANDOMFALSE(percent)
176#define DB_RANDOMTRUE(defects)
177#define DB_OR_RANDOMTRUE(percent)
178#define DB_AND_RANDOMTRUE(percent)
179
180#endif /* BNX_DEBUG */
181
182
183/****************************************************************************/
184/* Device identification definitions. */
185/****************************************************************************/
186#define BRCM_VENDORID 0x14E4
187#define BRCM_DEVICEID_BCM5706 0x164A
188#define BRCM_DEVICEID_BCM5706S 0x16AA
189#define BRCM_DEVICEID_BCM5708 0x164C
190#define BRCM_DEVICEID_BCM5708S 0x16AC
191
192#define HP_VENDORID 0x103C
193
194#define PCI_ANY_ID (uint16_t) (~0U)
195
196/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
197
198#define _BNX_CHIP_NUM(chipid) ((chipid) & 0xffff0000)
199#define BNX_CHIP_NUM(sc) _BNX_CHIP_NUM((sc)->bnx_chipid)
200#define BNX_CHIP_NUM_5706 0x57060000
201#define BNX_CHIP_NUM_5708 0x57080000
202#define BNX_CHIP_NUM_5709 0x57090000
203#define BNX_CHIP_NUM_5716 0x57160000
204
205#define _BNX_CHIP_REV(chipid) ((chipid) & 0x0000f000)
206#define BNX_CHIP_REV(sc) _BNX_CHIP_REV((sc)->bnx_chipid)
207#define BNX_CHIP_REV_Ax 0x00000000
208#define BNX_CHIP_REV_Bx 0x00001000
209#define BNX_CHIP_REV_Cx 0x00002000
210
211#define BNX_CHIP_METAL(sc) (((sc)->bnx_chipid) & 0x00000ff0)
212#define BNX_CHIP_BOND(bp) (((sc)->bnx_chipid) & 0x0000000f)
213
214#define _BNX_CHIP_ID(chipid) ((chipid) & 0xfffffff0)
215#define BNX_CHIP_ID(sc) _BNX_CHIP_ID((sc)->bnx_chipid)
216
217#define BNX_CHIP_ID_5706_A0 0x57060000
218#define BNX_CHIP_ID_5706_A1 0x57060010
219#define BNX_CHIP_ID_5706_A2 0x57060020
220#define BNX_CHIP_ID_5706_A3 0x57060030
221#define BNX_CHIP_ID_5708_A0 0x57080000
222#define BNX_CHIP_ID_5708_B0 0x57081000
223#define BNX_CHIP_ID_5708_B1 0x57081010
224#define BNX_CHIP_ID_5708_B2 0x57081020
225#define BNX_CHIP_ID_5709_A0 0x57090000
226#define BNX_CHIP_ID_5709_A1 0x57090010
227#define BNX_CHIP_ID_5709_B0 0x57091000
228#define BNX_CHIP_ID_5709_B1 0x57091010
229#define BNX_CHIP_ID_5709_B2 0x57091020
230#define BNX_CHIP_ID_5709_C0 0x57092000
231#define BNX_CHIP_ID_5716_C0 0x57162000
232
233#define BNX_CHIP_BOND_ID(sc) (((sc)->bnx_chipid) & 0xf)
234
235/* A serdes chip will have the first bit of the bond id set. */
236#define BNX_CHIP_BOND_ID_SERDES_BIT 0x01
237
238
239/* shorthand one */
240#define BNXNUM(sc) (BNX_CHIP_NUM(sc) >> 16)
241#define BNXREV(sc) (BNX_CHIP_REV(sc) >> 12)
242#define BNXMETAL(sc) (BNX_CHIP_METAL(sc) >> 4)
243
244struct bnx_type {
245 uint16_t bnx_vid;
246 uint16_t bnx_did;
247 uint16_t bnx_svid;
248 uint16_t bnx_sdid;
249 char *bnx_name;
250};
251
252/****************************************************************************/
253/* Byte order conversions. */
254/****************************************************************************/
255#define betoh32(x) be32toh(x)
256#define bnx_htobe16(x) htobe16(x)
257#define bnx_htobe32(x) htobe32(x)
258#define bnx_htobe64(x) htobe64(x)
259#define bnx_htole16(x) htole16(x)
260#define bnx_htole32(x) htole32(x)
261#define bnx_htole64(x) htole64(x)
262
263#define bnx_be16toh(x) betoh16(x)
264#define bnx_be32toh(x) betoh32(x)
265#define bnx_be64toh(x) betoh64(x)
266#define bnx_le16toh(x) letoh16(x)
267#define bnx_le32toh(x) letoh32(x)
268#define bnx_le64toh(x) letoh64(x)
269
270
271/****************************************************************************/
272/* NVRAM Access */
273/****************************************************************************/
274
275/* Buffered flash (Atmel: AT45DB011B) specific information */
276#define SEEPROM_PAGE_BITS 2
277#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS)
278#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1)
279#define SEEPROM_PAGE_SIZE 4
280#define SEEPROM_TOTAL_SIZE 65536
281
282#define BUFFERED_FLASH_PAGE_BITS 9
283#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS)
284#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
285#define BUFFERED_FLASH_PAGE_SIZE 264
286#define BUFFERED_FLASH_TOTAL_SIZE 0x21000
287
288#define SAIFUN_FLASH_PAGE_BITS 8
289#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS)
290#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
291#define SAIFUN_FLASH_PAGE_SIZE 256
292#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
293
294#define ST_MICRO_FLASH_PAGE_BITS 8
295#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS)
296#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
297#define ST_MICRO_FLASH_PAGE_SIZE 256
298#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536
299
300#define BCM5709_FLASH_PAGE_BITS 8
301#define BCM5709_FLASH_PHY_PAGE_SIZE (1 << BCM5709_FLASH_PAGE_BITS)
302#define BCM5709_FLASH_BYTE_ADDR_MASK (BCM5709_FLASH_PHY_PAGE_SIZE-1)
303#define BCM5709_FLASH_PAGE_SIZE 256
304
305#define NVRAM_TIMEOUT_COUNT 30000
306#define BNX_FLASHDESC_MAX 64
307
308#define FLASH_STRAP_MASK (BNX_NVM_CFG1_FLASH_MODE | \
309 BNX_NVM_CFG1_BUFFER_MODE | \
310 BNX_NVM_CFG1_PROTECT_MODE | \
311 BNX_NVM_CFG1_FLASH_SIZE)
312
313#define FLASH_BACKUP_STRAP_MASK (0xf << 26)
314
315struct flash_spec {
316 uint32_t strapping;
317 uint32_t config1;
318 uint32_t config2;
319 uint32_t config3;
320 uint32_t write1;
321#define BNX_NV_BUFFERED 0x00000001
322#define BNX_NV_TRANSLATE 0x00000002
323#define BNX_NV_WREN 0x00000004
324 uint32_t flags;
325 uint32_t page_bits;
326 uint32_t page_size;
327 uint32_t addr_mask;
328 uint32_t total_size;
329 const uint8_t *name;
330};
331
332
333/****************************************************************************/
334/* Shared Memory layout */
335/* The BNX bootcode will initialize this data area with port configurtion */
336/* information which can be accessed by the driver. */
337/****************************************************************************/
338
339/*
340 * This value (in milliseconds) determines the frequency of the driver
341 * issuing the PULSE message code. The firmware monitors this periodic
342 * pulse to determine when to switch to an OS-absent mode.
343 */
344#define DRV_PULSE_PERIOD_MS 250
345
346/*
347 * This value (in milliseconds) determines how long the driver should
348 * wait for an acknowledgement from the firmware before timing out. Once
349 * the firmware has timed out, the driver will assume there is no firmware
350 * running and there won't be any firmware-driver synchronization during a
351 * driver reset.
352 */
353#define FW_ACK_TIME_OUT_MS 1000
354
355
356#define BNX_DRV_RESET_SIGNATURE 0x00000000
357#define BNX_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
358
359#define BNX_DRV_MB 0x00000004
360#define BNX_DRV_MSG_CODE 0xff000000
361#define BNX_DRV_MSG_CODE_RESET 0x01000000
362#define BNX_DRV_MSG_CODE_UNLOAD 0x02000000
363#define BNX_DRV_MSG_CODE_SHUTDOWN 0x03000000
364#define BNX_DRV_MSG_CODE_SUSPEND_WOL 0x04000000
365#define BNX_DRV_MSG_CODE_FW_TIMEOUT 0x05000000
366#define BNX_DRV_MSG_CODE_PULSE 0x06000000
367#define BNX_DRV_MSG_CODE_DIAG 0x07000000
368#define BNX_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
369
370#define BNX_DRV_MSG_DATA 0x00ff0000
371#define BNX_DRV_MSG_DATA_WAIT0 0x00010000
372#define BNX_DRV_MSG_DATA_WAIT1 0x00020000
373#define BNX_DRV_MSG_DATA_WAIT2 0x00030000
374#define BNX_DRV_MSG_DATA_WAIT3 0x00040000
375
376#define BNX_DRV_MSG_SEQ 0x0000ffff
377
378#define BNX_FW_MB 0x00000008
379#define BNX_FW_MSG_ACK 0x0000ffff
380#define BNX_FW_MSG_STATUS_MASK 0x00ff0000
381#define BNX_FW_MSG_STATUS_OK 0x00000000
382#define BNX_FW_MSG_STATUS_FAILURE 0x00ff0000
383
384#define BNX_LINK_STATUS 0x0000000c
385#define BNX_LINK_STATUS_INIT_VALUE 0xffffffff
386#define BNX_LINK_STATUS_LINK_UP 0x1
387#define BNX_LINK_STATUS_LINK_DOWN 0x0
388#define BNX_LINK_STATUS_SPEED_MASK 0x1e
389#define BNX_LINK_STATUS_AN_INCOMPLETE (0<<1)
390#define BNX_LINK_STATUS_10HALF (1<<1)
391#define BNX_LINK_STATUS_10FULL (2<<1)
392#define BNX_LINK_STATUS_100HALF (3<<1)
393#define BNX_LINK_STATUS_100BASE_T4 (4<<1)
394#define BNX_LINK_STATUS_100FULL (5<<1)
395#define BNX_LINK_STATUS_1000HALF (6<<1)
396#define BNX_LINK_STATUS_1000FULL (7<<1)
397#define BNX_LINK_STATUS_2500HALF (8<<1)
398#define BNX_LINK_STATUS_2500FULL (9<<1)
399#define BNX_LINK_STATUS_AN_ENABLED (1<<5)
400#define BNX_LINK_STATUS_AN_COMPLETE (1<<6)
401#define BNX_LINK_STATUS_PARALLEL_DET (1<<7)
402#define BNX_LINK_STATUS_RESERVED (1<<8)
403#define BNX_LINK_STATUS_PARTNER_AD_1000FULL (1<<9)
404#define BNX_LINK_STATUS_PARTNER_AD_1000HALF (1<<10)
405#define BNX_LINK_STATUS_PARTNER_AD_100BT4 (1<<11)
406#define BNX_LINK_STATUS_PARTNER_AD_100FULL (1<<12)
407#define BNX_LINK_STATUS_PARTNER_AD_100HALF (1<<13)
408#define BNX_LINK_STATUS_PARTNER_AD_10FULL (1<<14)
409#define BNX_LINK_STATUS_PARTNER_AD_10HALF (1<<15)
410#define BNX_LINK_STATUS_TX_FC_ENABLED (1<<16)
411#define BNX_LINK_STATUS_RX_FC_ENABLED (1<<17)
412#define BNX_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18)
413#define BNX_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19)
414#define BNX_LINK_STATUS_SERDES_LINK (1<<20)
415#define BNX_LINK_STATUS_PARTNER_AD_2500FULL (1<<21)
416#define BNX_LINK_STATUS_PARTNER_AD_2500HALF (1<<22)
417
418#define BNX_DRV_PULSE_MB 0x00000010
419#define BNX_DRV_PULSE_SEQ_MASK 0x00007fff
420
421#define BNX_MB_ARGS_0 0x00000014
422#define BNX_MB_ARGS_1 0x00000018
423
424/* Indicate to the firmware not to go into the
425 * OS absent when it is not getting driver pulse.
426 * This is used for debugging. */
427#define BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000
428
429#define BNX_DEV_INFO_SIGNATURE 0x00000020
430#define BNX_DEV_INFO_SIGNATURE_MAGIC 0x44564900
431#define BNX_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00
432#define BNX_DEV_INFO_FEATURE_CFG_VALID 0x01
433#define BNX_DEV_INFO_SECONDARY_PORT 0x80
434#define BNX_DEV_INFO_DRV_ALWAYS_ALIVE 0x40
435
436#define BNX_SHARED_HW_CFG_PART_NUM 0x00000024
437
438#define BNX_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034
439#define BNX_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000
440#define BNX_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000
441#define BNX_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00
442#define BNX_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff
443
444#define BNX_SHARED_HW_CFG_POWER_CONSUMED 0x00000038
445#define BNX_SHARED_HW_CFG_CONFIG 0x0000003c
446#define BNX_SHARED_HW_CFG_DESIGN_NIC 0
447#define BNX_SHARED_HW_CFG_DESIGN_LOM 0x1
448#define BNX_SHARED_HW_CFG_PHY_COPPER 0
449#define BNX_SHARED_HW_CFG_PHY_FIBER 0x2
450#define BNX_SHARED_HW_CFG_PHY_2_5G 0x20
451#define BNX_SHARED_HW_CFG_PHY_BACKPLANE 0x40
452#define BNX_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8
453#define BNX_SHARED_HW_CFG_LED_MODE_MASK 0x300
454#define BNX_SHARED_HW_CFG_LED_MODE_MAC 0
455#define BNX_SHARED_HW_CFG_LED_MODE_GPHY1 0x100
456#define BNX_SHARED_HW_CFG_LED_MODE_GPHY2 0x200
457
458#define BNX_SHARED_HW_CFG_CONFIG2 0x00000040
459#define BNX_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000
460
461#define BNX_DEV_INFO_BC_REV 0x0000004c
462
463#define BNX_PORT_HW_CFG_MAC_UPPER 0x00000050
464#define BNX_PORT_HW_CFG_UPPERMAC_MASK 0xffff
465
466#define BNX_PORT_HW_CFG_MAC_LOWER 0x00000054
467#define BNX_PORT_HW_CFG_CONFIG 0x00000058
468#define BNX_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff
469#define BNX_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000
470#define BNX_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000
471#define BNX_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000
472#define BNX_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000
473
474#define BNX_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
475#define BNX_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
476#define BNX_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070
477#define BNX_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074
478#define BNX_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078
479#define BNX_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c
480
481#define BNX_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4
482
483#define BNX_DEV_INFO_FORMAT_REV 0x000000c4
484#define BNX_DEV_INFO_FORMAT_REV_MASK 0xff000000
485#define BNX_DEV_INFO_FORMAT_REV_ID ('A' << 24)
486
487#define BNX_SHARED_FEATURE 0x000000c8
488#define BNX_SHARED_FEATURE_MASK 0xffffffff
489
490#define BNX_PORT_FEATURE 0x000000d8
491#define BNX_PORT2_FEATURE 0x00000014c
492#define BNX_PORT_FEATURE_WOL_ENABLED 0x01000000
493#define BNX_PORT_FEATURE_MBA_ENABLED 0x02000000
494#define BNX_PORT_FEATURE_ASF_ENABLED 0x04000000
495#define BNX_PORT_FEATURE_IMD_ENABLED 0x08000000
496#define BNX_PORT_FEATURE_BAR1_SIZE_MASK 0xf
497#define BNX_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0
498#define BNX_PORT_FEATURE_BAR1_SIZE_64K 0x1
499#define BNX_PORT_FEATURE_BAR1_SIZE_128K 0x2
500#define BNX_PORT_FEATURE_BAR1_SIZE_256K 0x3
501#define BNX_PORT_FEATURE_BAR1_SIZE_512K 0x4
502#define BNX_PORT_FEATURE_BAR1_SIZE_1M 0x5
503#define BNX_PORT_FEATURE_BAR1_SIZE_2M 0x6
504#define BNX_PORT_FEATURE_BAR1_SIZE_4M 0x7
505#define BNX_PORT_FEATURE_BAR1_SIZE_8M 0x8
506#define BNX_PORT_FEATURE_BAR1_SIZE_16M 0x9
507#define BNX_PORT_FEATURE_BAR1_SIZE_32M 0xa
508#define BNX_PORT_FEATURE_BAR1_SIZE_64M 0xb
509#define BNX_PORT_FEATURE_BAR1_SIZE_128M 0xc
510#define BNX_PORT_FEATURE_BAR1_SIZE_256M 0xd
511#define BNX_PORT_FEATURE_BAR1_SIZE_512M 0xe
512#define BNX_PORT_FEATURE_BAR1_SIZE_1G 0xf
513
514#define BNX_PORT_FEATURE_WOL 0xdc
515#define BNX_PORT2_FEATURE_WOL 0x150
516#define BNX_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4
517#define BNX_PORT_FEATURE_WOL_DEFAULT_MASK 0x30
518#define BNX_PORT_FEATURE_WOL_DEFAULT_DISABLE 0
519#define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10
520#define BNX_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20
521#define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30
522#define BNX_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf
523#define BNX_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0
524#define BNX_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1
525#define BNX_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2
526#define BNX_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
527#define BNX_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
528#define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5
529#define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6
530#define BNX_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40
531#define BNX_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
532#define BNX_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800
533
534#define BNX_PORT_FEATURE_MBA 0xe0
535#define BNX_PORT2_FEATURE_MBA 0x154
536#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0
537#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3
538#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0
539#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1
540#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2
541#define BNX_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2
542#define BNX_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c
543#define BNX_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0
544#define BNX_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4
545#define BNX_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8
546#define BNX_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc
547#define BNX_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10
548#define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14
549#define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18
550#define BNX_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40
551#define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0
552#define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80
553#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8
554#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00
555#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0
556#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100
557#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200
558#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300
559#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400
560#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500
561#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600
562#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700
563#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800
564#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900
565#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00
566#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00
567#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00
568#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00
569#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00
570#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00
571#define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16
572#define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000
573#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20
574#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000
575#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0
576#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000
577#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000
578#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000
579
580#define BNX_PORT_FEATURE_IMD 0xe4
581#define BNX_PORT2_FEATURE_IMD 0x158
582#define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0
583#define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1
584
585#define BNX_PORT_FEATURE_VLAN 0xe8
586#define BNX_PORT2_FEATURE_VLAN 0x15c
587#define BNX_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff
588#define BNX_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000
589
590#define BNX_BC_STATE_RESET_TYPE 0x000001c0
591#define BNX_BC_STATE_RESET_TYPE_SIG 0x00005254
592#define BNX_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff
593#define BNX_BC_STATE_RESET_TYPE_NONE (BNX_BC_STATE_RESET_TYPE_SIG | \
594 0x00010000)
595#define BNX_BC_STATE_RESET_TYPE_PCI (BNX_BC_STATE_RESET_TYPE_SIG | \
596 0x00020000)
597#define BNX_BC_STATE_RESET_TYPE_VAUX (BNX_BC_STATE_RESET_TYPE_SIG | \
598 0x00030000)
599#define BNX_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE
600#define BNX_BC_STATE_RESET_TYPE_DRV_RESET (BNX_BC_STATE_RESET_TYPE_SIG | \
601 DRV_MSG_CODE_RESET)
602#define BNX_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX_BC_STATE_RESET_TYPE_SIG | \
603 DRV_MSG_CODE_UNLOAD)
604#define BNX_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX_BC_STATE_RESET_TYPE_SIG | \
605 DRV_MSG_CODE_SHUTDOWN)
606#define BNX_BC_STATE_RESET_TYPE_DRV_WOL (BNX_BC_STATE_RESET_TYPE_SIG | \
607 DRV_MSG_CODE_WOL)
608#define BNX_BC_STATE_RESET_TYPE_DRV_DIAG (BNX_BC_STATE_RESET_TYPE_SIG | \
609 DRV_MSG_CODE_DIAG)
610#define BNX_BC_STATE_RESET_TYPE_VALUE(msg) (BNX_BC_STATE_RESET_TYPE_SIG | \
611 (msg))
612
613#define BNX_BC_STATE 0x000001c4
614#define BNX_BC_STATE_ERR_MASK 0x0000ff00
615#define BNX_BC_STATE_SIGN 0x42530000
616#define BNX_BC_STATE_SIGN_MASK 0xffff0000
617#define BNX_BC_STATE_BC1_START (BNX_BC_STATE_SIGN | 0x1)
618#define BNX_BC_STATE_GET_NVM_CFG1 (BNX_BC_STATE_SIGN | 0x2)
619#define BNX_BC_STATE_PROG_BAR (BNX_BC_STATE_SIGN | 0x3)
620#define BNX_BC_STATE_INIT_VID (BNX_BC_STATE_SIGN | 0x4)
621#define BNX_BC_STATE_GET_NVM_CFG2 (BNX_BC_STATE_SIGN | 0x5)
622#define BNX_BC_STATE_APPLY_WKARND (BNX_BC_STATE_SIGN | 0x6)
623#define BNX_BC_STATE_LOAD_BC2 (BNX_BC_STATE_SIGN | 0x7)
624#define BNX_BC_STATE_GOING_BC2 (BNX_BC_STATE_SIGN | 0x8)
625#define BNX_BC_STATE_GOING_DIAG (BNX_BC_STATE_SIGN | 0x9)
626#define BNX_BC_STATE_RT_FINAL_INIT (BNX_BC_STATE_SIGN | 0x81)
627#define BNX_BC_STATE_RT_WKARND (BNX_BC_STATE_SIGN | 0x82)
628#define BNX_BC_STATE_RT_DRV_PULSE (BNX_BC_STATE_SIGN | 0x83)
629#define BNX_BC_STATE_RT_FIOEVTS (BNX_BC_STATE_SIGN | 0x84)
630#define BNX_BC_STATE_RT_DRV_CMD (BNX_BC_STATE_SIGN | 0x85)
631#define BNX_BC_STATE_RT_LOW_POWER (BNX_BC_STATE_SIGN | 0x86)
632#define BNX_BC_STATE_RT_SET_WOL (BNX_BC_STATE_SIGN | 0x87)
633#define BNX_BC_STATE_RT_OTHER_FW (BNX_BC_STATE_SIGN | 0x88)
634#define BNX_BC_STATE_RT_GOING_D3 (BNX_BC_STATE_SIGN | 0x89)
635#define BNX_BC_STATE_ERR_BAD_VERSION (BNX_BC_STATE_SIGN | 0x0100)
636#define BNX_BC_STATE_ERR_BAD_BC2_CRC (BNX_BC_STATE_SIGN | 0x0200)
637#define BNX_BC_STATE_ERR_BC1_LOOP (BNX_BC_STATE_SIGN | 0x0300)
638#define BNX_BC_STATE_ERR_UNKNOWN_CMD (BNX_BC_STATE_SIGN | 0x0400)
639#define BNX_BC_STATE_ERR_DRV_DEAD (BNX_BC_STATE_SIGN | 0x0500)
640#define BNX_BC_STATE_ERR_NO_RXP (BNX_BC_STATE_SIGN | 0x0600)
641#define BNX_BC_STATE_ERR_TOO_MANY_RBUF (BNX_BC_STATE_SIGN | 0x0700)
642
643#define BNX_BC_STATE_DEBUG_CMD 0x1dc
644#define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000
645#define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000
646#define BNX_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff
647#define BNX_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff
648
649#define HOST_VIEW_SHMEM_BASE 0x167c00
650
651/****************************************************************************/
652/* Convenience definitions. */
653/****************************************************************************/
654#define BNX_PRINTF(sc, fmt, ...) aprint_error_dev(sc->bnx_dev, fmt, __VA_ARGS__)
655#define BNX_STATS(x) (u_long) stats->stat_ ## x ## _lo
656
657/*
658 * The following data structures are generated from RTL code.
659 * Do not modify any values below this line.
660 */
661
662/****************************************************************************/
663/* Do not modify any of the following data structures, they are generated */
664/* from RTL code. */
665/* */
666/* Begin machine generated definitions. */
667/****************************************************************************/
668
669/*
670 * tx_bd definition
671 */
672struct tx_bd {
673 uint32_t tx_bd_haddr_hi;
674 uint32_t tx_bd_haddr_lo;
675 uint32_t tx_bd_mss_nbytes;
676#if BYTE_ORDER == BIG_ENDIAN
677 uint16_t tx_bd_vlan_tag;
678 uint16_t tx_bd_flags;
679#else
680 uint16_t tx_bd_flags;
681 uint16_t tx_bd_vlan_tag;
682#endif
683 #define TX_BD_FLAGS_CONN_FAULT (1<<0)
684 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1)
685 #define TX_BD_FLAGS_IP_CKSUM (1<<2)
686 #define TX_BD_FLAGS_VLAN_TAG (1<<3)
687 #define TX_BD_FLAGS_COAL_NOW (1<<4)
688 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5)
689 #define TX_BD_FLAGS_END (1<<6)
690 #define TX_BD_FLAGS_START (1<<7)
691 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
692 #define TX_BD_FLAGS_SW_FLAGS (1<<13)
693 #define TX_BD_FLAGS_SW_SNAP (1<<14)
694 #define TX_BD_FLAGS_SW_LSO (1<<15)
695
696};
697
698
699/*
700 * rx_bd definition
701 */
702struct rx_bd {
703 uint32_t rx_bd_haddr_hi;
704 uint32_t rx_bd_haddr_lo;
705 uint32_t rx_bd_len;
706 uint32_t rx_bd_flags;
707 #define RX_BD_FLAGS_NOPUSH (1<<0)
708 #define RX_BD_FLAGS_DUMMY (1<<1)
709 #define RX_BD_FLAGS_END (1<<2)
710 #define RX_BD_FLAGS_START (1<<3)
711
712};
713
714
715/*
716 * status_block definition
717 */
718struct status_block {
719 uint32_t status_attn_bits;
720 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
721 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
722 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2)
723 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3)
724 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
725 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5)
726 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6)
727 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
728 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8)
729 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
730 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10)
731 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11)
732 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
733 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13)
734 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14)
735 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15)
736 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16)
737 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17)
738 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18)
739 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19)
740 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20)
741 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21)
742 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22)
743 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23)
744 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24)
745 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
746 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
747 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
748 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
749
750 uint32_t status_attn_bits_ack;
751#if BYTE_ORDER == BIG_ENDIAN
752 uint16_t status_tx_quick_consumer_index0;
753 uint16_t status_tx_quick_consumer_index1;
754 uint16_t status_tx_quick_consumer_index2;
755 uint16_t status_tx_quick_consumer_index3;
756 uint16_t status_rx_quick_consumer_index0;
757 uint16_t status_rx_quick_consumer_index1;
758 uint16_t status_rx_quick_consumer_index2;
759 uint16_t status_rx_quick_consumer_index3;
760 uint16_t status_rx_quick_consumer_index4;
761 uint16_t status_rx_quick_consumer_index5;
762 uint16_t status_rx_quick_consumer_index6;
763 uint16_t status_rx_quick_consumer_index7;
764 uint16_t status_rx_quick_consumer_index8;
765 uint16_t status_rx_quick_consumer_index9;
766 uint16_t status_rx_quick_consumer_index10;
767 uint16_t status_rx_quick_consumer_index11;
768 uint16_t status_rx_quick_consumer_index12;
769 uint16_t status_rx_quick_consumer_index13;
770 uint16_t status_rx_quick_consumer_index14;
771 uint16_t status_rx_quick_consumer_index15;
772 uint16_t status_completion_producer_index;
773 uint16_t status_cmd_consumer_index;
774 uint16_t status_idx;
775 uint16_t status_unused;
776#elif BYTE_ORDER == LITTLE_ENDIAN
777 uint16_t status_tx_quick_consumer_index1;
778 uint16_t status_tx_quick_consumer_index0;
779 uint16_t status_tx_quick_consumer_index3;
780 uint16_t status_tx_quick_consumer_index2;
781 uint16_t status_rx_quick_consumer_index1;
782 uint16_t status_rx_quick_consumer_index0;
783 uint16_t status_rx_quick_consumer_index3;
784 uint16_t status_rx_quick_consumer_index2;
785 uint16_t status_rx_quick_consumer_index5;
786 uint16_t status_rx_quick_consumer_index4;
787 uint16_t status_rx_quick_consumer_index7;
788 uint16_t status_rx_quick_consumer_index6;
789 uint16_t status_rx_quick_consumer_index9;
790 uint16_t status_rx_quick_consumer_index8;
791 uint16_t status_rx_quick_consumer_index11;
792 uint16_t status_rx_quick_consumer_index10;
793 uint16_t status_rx_quick_consumer_index13;
794 uint16_t status_rx_quick_consumer_index12;
795 uint16_t status_rx_quick_consumer_index15;
796 uint16_t status_rx_quick_consumer_index14;
797 uint16_t status_cmd_consumer_index;
798 uint16_t status_completion_producer_index;
799 uint16_t status_unused;
800 uint16_t status_idx;
801#endif
802};
803
804
805/*
806 * statistics_block definition
807 */
808struct statistics_block {
809 uint32_t stat_IfHCInOctets_hi;
810 uint32_t stat_IfHCInOctets_lo;
811 uint32_t stat_IfHCInBadOctets_hi;
812 uint32_t stat_IfHCInBadOctets_lo;
813 uint32_t stat_IfHCOutOctets_hi;
814 uint32_t stat_IfHCOutOctets_lo;
815 uint32_t stat_IfHCOutBadOctets_hi;
816 uint32_t stat_IfHCOutBadOctets_lo;
817 uint32_t stat_IfHCInUcastPkts_hi;
818 uint32_t stat_IfHCInUcastPkts_lo;
819 uint32_t stat_IfHCInMulticastPkts_hi;
820 uint32_t stat_IfHCInMulticastPkts_lo;
821 uint32_t stat_IfHCInBroadcastPkts_hi;
822 uint32_t stat_IfHCInBroadcastPkts_lo;
823 uint32_t stat_IfHCOutUcastPkts_hi;
824 uint32_t stat_IfHCOutUcastPkts_lo;
825 uint32_t stat_IfHCOutMulticastPkts_hi;
826 uint32_t stat_IfHCOutMulticastPkts_lo;
827 uint32_t stat_IfHCOutBroadcastPkts_hi;
828 uint32_t stat_IfHCOutBroadcastPkts_lo;
829 uint32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
830 uint32_t stat_Dot3StatsCarrierSenseErrors;
831 uint32_t stat_Dot3StatsFCSErrors;
832 uint32_t stat_Dot3StatsAlignmentErrors;
833 uint32_t stat_Dot3StatsSingleCollisionFrames;
834 uint32_t stat_Dot3StatsMultipleCollisionFrames;
835 uint32_t stat_Dot3StatsDeferredTransmissions;
836 uint32_t stat_Dot3StatsExcessiveCollisions;
837 uint32_t stat_Dot3StatsLateCollisions;
838 uint32_t stat_EtherStatsCollisions;
839 uint32_t stat_EtherStatsFragments;
840 uint32_t stat_EtherStatsJabbers;
841 uint32_t stat_EtherStatsUndersizePkts;
842 uint32_t stat_EtherStatsOverrsizePkts;
843 uint32_t stat_EtherStatsPktsRx64Octets;
844 uint32_t stat_EtherStatsPktsRx65Octetsto127Octets;
845 uint32_t stat_EtherStatsPktsRx128Octetsto255Octets;
846 uint32_t stat_EtherStatsPktsRx256Octetsto511Octets;
847 uint32_t stat_EtherStatsPktsRx512Octetsto1023Octets;
848 uint32_t stat_EtherStatsPktsRx1024Octetsto1522Octets;
849 uint32_t stat_EtherStatsPktsRx1523Octetsto9022Octets;
850 uint32_t stat_EtherStatsPktsTx64Octets;
851 uint32_t stat_EtherStatsPktsTx65Octetsto127Octets;
852 uint32_t stat_EtherStatsPktsTx128Octetsto255Octets;
853 uint32_t stat_EtherStatsPktsTx256Octetsto511Octets;
854 uint32_t stat_EtherStatsPktsTx512Octetsto1023Octets;
855 uint32_t stat_EtherStatsPktsTx1024Octetsto1522Octets;
856 uint32_t stat_EtherStatsPktsTx1523Octetsto9022Octets;
857 uint32_t stat_XonPauseFramesReceived;
858 uint32_t stat_XoffPauseFramesReceived;
859 uint32_t stat_OutXonSent;
860 uint32_t stat_OutXoffSent;
861 uint32_t stat_FlowControlDone;
862 uint32_t stat_MacControlFramesReceived;
863 uint32_t stat_XoffStateEntered;
864 uint32_t stat_IfInFramesL2FilterDiscards;
865 uint32_t stat_IfInRuleCheckerDiscards;
866 uint32_t stat_IfInFTQDiscards;
867 uint32_t stat_IfInMBUFDiscards;
868 uint32_t stat_IfInRuleCheckerP4Hit;
869 uint32_t stat_CatchupInRuleCheckerDiscards;
870 uint32_t stat_CatchupInFTQDiscards;
871 uint32_t stat_CatchupInMBUFDiscards;
872 uint32_t stat_CatchupInRuleCheckerP4Hit;
873 uint32_t stat_GenStat00;
874 uint32_t stat_GenStat01;
875 uint32_t stat_GenStat02;
876 uint32_t stat_GenStat03;
877 uint32_t stat_GenStat04;
878 uint32_t stat_GenStat05;
879 uint32_t stat_GenStat06;
880 uint32_t stat_GenStat07;
881 uint32_t stat_GenStat08;
882 uint32_t stat_GenStat09;
883 uint32_t stat_GenStat10;
884 uint32_t stat_GenStat11;
885 uint32_t stat_GenStat12;
886 uint32_t stat_GenStat13;
887 uint32_t stat_GenStat14;
888 uint32_t stat_GenStat15;
889};
890
891
892/*
893 * l2_fhdr definition
894 */
895struct l2_fhdr {
896 uint32_t l2_fhdr_status;
897 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
898 #define L2_FHDR_STATUS_RULE_P2 (1<<3)
899 #define L2_FHDR_STATUS_RULE_P3 (1<<4)
900 #define L2_FHDR_STATUS_RULE_P4 (1<<5)
901 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6)
902 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7)
903 #define L2_FHDR_STATUS_RSS_HASH (1<<8)
904 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13)
905 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14)
906 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
907
908 #define L2_FHDR_ERRORS_BAD_CRC (1<<17)
909 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18)
910 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19)
911 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20)
912 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21)
913 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28)
914 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31)
915
916 uint32_t l2_fhdr_hash;
917#if BYTE_ORDER == BIG_ENDIAN
918 uint16_t l2_fhdr_pkt_len;
919 uint16_t l2_fhdr_vlan_tag;
920 uint16_t l2_fhdr_ip_xsum;
921 uint16_t l2_fhdr_tcp_udp_xsum;
922#elif BYTE_ORDER == LITTLE_ENDIAN
923 uint16_t l2_fhdr_vlan_tag;
924 uint16_t l2_fhdr_pkt_len;
925 uint16_t l2_fhdr_tcp_udp_xsum;
926 uint16_t l2_fhdr_ip_xsum;
927#endif
928};
929
930
931/*
932 * l2_context definition
933 */
934#define BNX_L2CTX_TYPE 0x00000000
935#define BNX_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
936#define BNX_L2CTX_TYPE_TYPE (0xf<<28)
937#define BNX_L2CTX_TYPE_TYPE_EMPTY (0<<28)
938#define BNX_L2CTX_TYPE_TYPE_L2 (1<<28)
939
940#define BNX_L2CTX_TYPE_XI 0x00000080
941#define BNX_L2CTX_TX_HOST_BIDX 0x00000088
942#define BNX_L2CTX_EST_NBD 0x00000088
943#define BNX_L2CTX_CMD_TYPE 0x00000088
944#define BNX_L2CTX_CMD_TYPE_TYPE (0xf<<24)
945#define BNX_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
946#define BNX_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
947
948#define BNX_L2CTX_TX_HOST_BSEQ 0x00000090
949#define BNX_L2CTX_TSCH_BSEQ 0x00000094
950#define BNX_L2CTX_TBDR_BSEQ 0x00000098
951#define BNX_L2CTX_TBDR_BOFF 0x0000009c
952#define BNX_L2CTX_TBDR_BIDX 0x0000009c
953#define BNX_L2CTX_TBDR_BHADDR_HI 0x000000a0
954#define BNX_L2CTX_TBDR_BHADDR_LO 0x000000a4
955#define BNX_L2CTX_TXP_BOFF 0x000000a8
956#define BNX_L2CTX_TXP_BIDX 0x000000a8
957#define BNX_L2CTX_TXP_BSEQ 0x000000ac
958
959#define BNX_L2CTX_CMD_TYPE_XI 0x00000240
960#define BNX_L2CTX_TBDR_BHADDR_HI_XI 0x00000258
961#define BNX_L2CTX_TBDR_BHADDR_LO_XI 0x0000025c
962
963/*
964 * l2_bd_chain_context definition
965 */
966#define BNX_L2CTX_BD_PRE_READ 0x00000000
967#define BNX_L2CTX_CTX_SIZE 0x00000000
968#define BNX_L2CTX_CTX_TYPE 0x00000000
969#define BNX_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
970#define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
971#define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
972#define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
973
974#define BNX_L2CTX_HOST_BDIDX 0x00000004
975#define BNX_L2CTX_HOST_BSEQ 0x00000008
976#define BNX_L2CTX_NX_BSEQ 0x0000000c
977#define BNX_L2CTX_NX_BDHADDR_HI 0x00000010
978#define BNX_L2CTX_NX_BDHADDR_LO 0x00000014
979#define BNX_L2CTX_NX_BDIDX 0x00000018
980
981/*
982 * l2_rx_context definition (5706, 5708, 5709, and 5716)
983 */
984#define BNX_L2CTX_RX_WATER_MARK 0x00000000
985#define BNX_L2CTX_RX_LO_WATER_MARK_SHIFT 0
986#define BNX_L2CTX_RX_LO_WATER_MARK_DEFAULT 32
987#define BNX_L2CTX_RX_LO_WATER_MARK_SCALE 4
988#define BNX_L2CTX_RX_LO_WATER_MARK_DIS 0
989#define BNX_L2CTX_RX_HI_WATER_MARK_SHIFT 4
990#define BNX_L2CTX_RX_HI_WATER_MARK_SCALE 16
991#define BNX_L2CTX_RX_WATER_MARKS_MSK 0x000000ff
992
993#define BNX_L2CTX_RX_BD_PRE_READ 0x00000000
994#define BNX_L2CTX_RX_BD_PRE_READ_SHIFT 8
995
996#define BNX_L2CTX_RX_CTX_SIZE 0x00000000
997#define BNX_L2CTX_RX_CTX_SIZE_SHIFT 16
998#define BNX_L2CTX_RX_CTX_TYPE_SIZE_L2 ((0x20/20)<<BNX_L2CTX_RX_CTX_SIZE_SHIFT)
999
1000#define BNX_L2CTX_RX_CTX_TYPE 0x00000000
1001#define BNX_L2CTX_RX_CTX_TYPE_SHIFT 24
1002
1003#define BNX_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
1004#define BNX_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
1005#define BNX_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
1006
1007#define BNX_L2CTX_RX_HOST_BDIDX 0x00000004
1008#define BNX_L2CTX_RX_HOST_BSEQ 0x00000008
1009#define BNX_L2CTX_RX_NX_BSEQ 0x0000000c
1010#define BNX_L2CTX_RX_NX_BDHADDR_HI 0x00000010
1011#define BNX_L2CTX_RX_NX_BDHADDR_LO 0x00000014
1012#define BNX_L2CTX_RX_NX_BDIDX 0x00000018
1013
1014#define BNX_L2CTX_RX_HOST_PG_BDIDX 0x00000044
1015#define BNX_L2CTX_RX_PG_BUF_SIZE 0x00000048
1016#define BNX_L2CTX_RX_RBDC_KEY 0x0000004c
1017#define BNX_L2CTX_RX_RBDC_JUMBO_KEY 0x3ffe
1018#define BNX_L2CTX_RX_NX_PG_BDHADDR_HI 0x00000050
1019#define BNX_L2CTX_RX_NX_PG_BDHADDR_LO 0x00000054
1020#define BNX_L2CTX_RX_NX_PG_BDIDX 0x00000058
1021
1022/*
1023 * pci_config_l definition
1024 * offset: 0000
1025 */
1026#define BNX_PCICFG_MISC_CONFIG 0x00000068
1027#define BNX_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
1028#define BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
1029#define BNX_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
1030#define BNX_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
1031#define BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
1032#define BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
1033#define BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
1034#define BNX_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16)
1035#define BNX_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24)
1036#define BNX_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28)
1037#define BNX_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16)
1038
1039#define BNX_PCICFG_MISC_STATUS 0x0000006c
1040#define BNX_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
1041#define BNX_PCICFG_MISC_STATUS_32BIT_DET (1L<<1)
1042#define BNX_PCICFG_MISC_STATUS_M66EN (1L<<2)
1043#define BNX_PCICFG_MISC_STATUS_PCIX_DET (1L<<3)
1044#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4)
1045#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
1046#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
1047#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
1048#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
1049
1050#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070
1051#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
1052#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
1053#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
1054#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
1055#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
1056#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
1057#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
1058#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
1059#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
1060#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
1061#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
1062#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
1063#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
1064#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
1065#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
1066#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
1067#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
1068#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
1069#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
1070#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
1071#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
1072#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
1073#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
1074#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
1075#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
1076#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
1077#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
1078#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
1079#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
1080
1081#define BNX_PCICFG_REG_WINDOW_ADDRESS 0x00000078
1082#define BNX_PCICFG_REG_WINDOW 0x00000080
1083#define BNX_PCICFG_INT_ACK_CMD 0x00000084
1084#define BNX_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0)
1085#define BNX_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
1086#define BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
1087#define BNX_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
1088
1089#define BNX_PCICFG_STATUS_BIT_SET_CMD 0x00000088
1090#define BNX_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
1091#define BNX_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
1092#define BNX_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
1093
1094
1095/*
1096 * pci_reg definition
1097 * offset: 0x400
1098 */
1099#define BNX_PCI_GRC_WINDOW_ADDR 0x00000400
1100#define BNX_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8)
1101
1102#define BNX_PCI_CONFIG_1 0x00000404
1103#define BNX_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
1104#define BNX_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
1105#define BNX_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
1106#define BNX_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8)
1107#define BNX_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8)
1108#define BNX_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8)
1109#define BNX_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8)
1110#define BNX_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8)
1111#define BNX_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8)
1112#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11)
1113#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
1114#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11)
1115#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11)
1116#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11)
1117#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11)
1118#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
1119#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
1120#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
1121
1122#define BNX_PCI_CONFIG_2 0x00000408
1123#define BNX_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
1124#define BNX_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
1125#define BNX_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
1126#define BNX_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
1127#define BNX_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
1128#define BNX_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
1129#define BNX_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
1130#define BNX_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
1131#define BNX_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
1132#define BNX_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
1133#define BNX_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
1134#define BNX_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
1135#define BNX_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
1136#define BNX_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
1137#define BNX_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
1138#define BNX_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
1139#define BNX_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
1140#define BNX_PCI_CONFIG_2_BAR1_64ENA (1L<<4)
1141#define BNX_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
1142#define BNX_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
1143#define BNX_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
1144#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
1145#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
1146#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8)
1147#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8)
1148#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8)
1149#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8)
1150#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8)
1151#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8)
1152#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8)
1153#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8)
1154#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8)
1155#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8)
1156#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8)
1157#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8)
1158#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8)
1159#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8)
1160#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8)
1161#define BNX_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16)
1162#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21)
1163#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
1164#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21)
1165#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21)
1166#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21)
1167#define BNX_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
1168#define BNX_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
1169#define BNX_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
1170
1171#define BNX_PCI_CONFIG_3 0x0000040c
1172#define BNX_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
1173#define BNX_PCI_CONFIG_3_FORCE_PME (1L<<24)
1174#define BNX_PCI_CONFIG_3_PME_STATUS (1L<<25)
1175#define BNX_PCI_CONFIG_3_PME_ENABLE (1L<<26)
1176#define BNX_PCI_CONFIG_3_PM_STATE (0x3L<<27)
1177#define BNX_PCI_CONFIG_3_VAUX_PRESET (1L<<30)
1178#define BNX_PCI_CONFIG_3_PCI_POWER (1L<<31)
1179
1180#define BNX_PCI_PM_DATA_A 0x00000410
1181#define BNX_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0)
1182#define BNX_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8)
1183#define BNX_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16)
1184#define BNX_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24)
1185
1186#define BNX_PCI_PM_DATA_B 0x00000414
1187#define BNX_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0)
1188#define BNX_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8)
1189#define BNX_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16)
1190#define BNX_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24)
1191
1192#define BNX_PCI_SWAP_DIAG0 0x00000418
1193#define BNX_PCI_SWAP_DIAG1 0x0000041c
1194#define BNX_PCI_EXP_ROM_ADDR 0x00000420
1195#define BNX_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2)
1196#define BNX_PCI_EXP_ROM_ADDR_REQ (1L<<31)
1197
1198#define BNX_PCI_EXP_ROM_DATA 0x00000424
1199#define BNX_PCI_VPD_INTF 0x00000428
1200#define BNX_PCI_VPD_INTF_INTF_REQ (1L<<0)
1201
1202#define BNX_PCI_VPD_ADDR_FLAG 0x0000042c
1203#define BNX_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2)
1204#define BNX_PCI_VPD_ADDR_FLAG_WR (1<<15)
1205
1206#define BNX_PCI_VPD_DATA 0x00000430
1207#define BNX_PCI_ID_VAL1 0x00000434
1208#define BNX_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0)
1209#define BNX_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16)
1210
1211#define BNX_PCI_ID_VAL2 0x00000438
1212#define BNX_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0)
1213#define BNX_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16)
1214
1215#define BNX_PCI_ID_VAL3 0x0000043c
1216#define BNX_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0)
1217#define BNX_PCI_ID_VAL3_REVISION_ID (0xffL<<24)
1218
1219#define BNX_PCI_ID_VAL4 0x00000440
1220#define BNX_PCI_ID_VAL4_CAP_ENA (0xfL<<0)
1221#define BNX_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
1222#define BNX_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
1223#define BNX_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
1224#define BNX_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
1225#define BNX_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
1226#define BNX_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
1227#define BNX_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
1228#define BNX_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
1229#define BNX_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
1230#define BNX_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
1231#define BNX_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
1232#define BNX_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
1233#define BNX_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
1234#define BNX_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
1235#define BNX_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
1236#define BNX_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
1237#define BNX_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6)
1238#define BNX_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
1239#define BNX_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
1240#define BNX_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
1241#define BNX_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
1242#define BNX_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9)
1243#define BNX_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12)
1244#define BNX_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
1245#define BNX_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
1246#define BNX_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
1247#define BNX_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21)
1248#define BNX_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23)
1249#define BNX_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26)
1250
1251#define BNX_PCI_ID_VAL5 0x00000444
1252#define BNX_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
1253#define BNX_PCI_ID_VAL5_D2_SUPPORT (1L<<1)
1254#define BNX_PCI_ID_VAL5_PME_IN_D0 (1L<<2)
1255#define BNX_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
1256#define BNX_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
1257#define BNX_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
1258
1259#define BNX_PCI_PCIX_EXTENDED_STATUS 0x00000448
1260#define BNX_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
1261#define BNX_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9)
1262#define BNX_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16)
1263#define BNX_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24)
1264
1265#define BNX_PCI_ID_VAL6 0x0000044c
1266#define BNX_PCI_ID_VAL6_MAX_LAT (0xffL<<0)
1267#define BNX_PCI_ID_VAL6_MIN_GNT (0xffL<<8)
1268#define BNX_PCI_ID_VAL6_BIST (0xffL<<16)
1269
1270#define BNX_PCI_MSI_DATA 0x00000450
1271#define BNX_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0)
1272
1273#define BNX_PCI_MSI_ADDR_H 0x00000454
1274#define BNX_PCI_MSI_ADDR_L 0x00000458
1275
1276/*
1277 * misc_reg definition
1278 * offset: 0x800
1279 */
1280#define BNX_MISC_COMMAND 0x00000800
1281#define BNX_MISC_COMMAND_ENABLE_ALL (1L<<0)
1282#define BNX_MISC_COMMAND_DISABLE_ALL (1L<<1)
1283#define BNX_MISC_COMMAND_SW_RESET (1L<<4)
1284#define BNX_MISC_COMMAND_POR_RESET (1L<<5)
1285#define BNX_MISC_COMMAND_HD_RESET (1L<<6)
1286#define BNX_MISC_COMMAND_CMN_SW_RESET (1L<<7)
1287#define BNX_MISC_COMMAND_PAR_ERROR (1L<<8)
1288#define BNX_MISC_COMMAND_CS16_ERR (1L<<9)
1289#define BNX_MISC_COMMAND_CS16_ERR_LOC (0xfL<<12)
1290#define BNX_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
1291#define BNX_MISC_COMMAND_POWERDOWN_EVENT (1L<<23)
1292#define BNX_MISC_COMMAND_SW_SHUTDOWN (1L<<24)
1293#define BNX_MISC_COMMAND_SHUTDOWN_EN (1L<<25)
1294#define BNX_MISC_COMMAND_DINTEG_ATTN_EN (1L<<26)
1295#define BNX_MISC_COMMAND_PCIE_LINK_IN_L23 (1L<<27)
1296#define BNX_MISC_COMMAND_PCIE_DIS (1L<<28)
1297
1298
1299#define BNX_MISC_CFG 0x00000804
1300#define BNX_MISC_CFG_PCI_GRC_TMOUT (1L<<0)
1301#define BNX_MISC_CFG_NVM_WR_EN (0x3L<<1)
1302#define BNX_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
1303#define BNX_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
1304#define BNX_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
1305#define BNX_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
1306#define BNX_MISC_CFG_BIST_EN (1L<<3)
1307#define BNX_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
1308#define BNX_MISC_CFG_BYPASS_BSCAN (1L<<5)
1309#define BNX_MISC_CFG_BYPASS_EJTAG (1L<<6)
1310#define BNX_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
1311#define BNX_MISC_CFG_LEDMODE (0x3L<<8)
1312#define BNX_MISC_CFG_LEDMODE_MAC (0L<<8)
1313#define BNX_MISC_CFG_LEDMODE_GPHY1 (1L<<8)
1314#define BNX_MISC_CFG_LEDMODE_GPHY2 (2L<<8)
1315
1316#define BNX_MISC_ID 0x00000808
1317#define BNX_MISC_ID_BOND_ID (0xfL<<0)
1318#define BNX_MISC_ID_CHIP_METAL (0xffL<<4)
1319#define BNX_MISC_ID_CHIP_REV (0xfL<<12)
1320#define BNX_MISC_ID_CHIP_NUM (0xffffL<<16)
1321
1322#define BNX_MISC_ENABLE_STATUS_BITS 0x0000080c
1323#define BNX_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1324#define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
1325#define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1326#define BNX_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1327#define BNX_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
1328#define BNX_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
1329#define BNX_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1330#define BNX_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1331#define BNX_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1332#define BNX_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
1333#define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1334#define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1335#define BNX_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
1336#define BNX_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
1337#define BNX_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1338#define BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
1339#define BNX_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1340#define BNX_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
1341#define BNX_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
1342#define BNX_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
1343#define BNX_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1344#define BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
1345#define BNX_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1346#define BNX_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1347#define BNX_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1348#define BNX_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
1349#define BNX_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
1350#define BNX_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
1351
1352#define BNX_MISC_ENABLE_SET_BITS 0x00000810
1353#define BNX_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1354#define BNX_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
1355#define BNX_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1356#define BNX_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1357#define BNX_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
1358#define BNX_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
1359#define BNX_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1360#define BNX_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1361#define BNX_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1362#define BNX_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
1363#define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1364#define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1365#define BNX_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
1366#define BNX_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
1367#define BNX_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1368#define BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
1369#define BNX_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1370#define BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
1371#define BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
1372#define BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
1373#define BNX_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1374#define BNX_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
1375#define BNX_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1376#define BNX_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1377#define BNX_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1378#define BNX_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
1379#define BNX_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
1380#define BNX_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
1381
1382#define BNX_MISC_ENABLE_DEFAULT 0x05ffffff
1383#define BNX_MISC_ENABLE_DEFAULT_XI 0x17ffffff
1384
1385#define BNX_MISC_ENABLE_CLR_BITS 0x00000814
1386#define BNX_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1387#define BNX_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
1388#define BNX_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1389#define BNX_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1390#define BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
1391#define BNX_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
1392#define BNX_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1393#define BNX_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1394#define BNX_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1395#define BNX_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
1396#define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1397#define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1398#define BNX_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
1399#define BNX_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
1400#define BNX_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1401#define BNX_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
1402#define BNX_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1403#define BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
1404#define BNX_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
1405#define BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
1406#define BNX_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1407#define BNX_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
1408#define BNX_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1409#define BNX_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1410#define BNX_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1411#define BNX_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
1412#define BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
1413#define BNX_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
1414
1415#define BNX_MISC_CLOCK_CONTROL_BITS 0x00000818
1416#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
1417#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
1418#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
1419#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
1420#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
1421#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
1422#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
1423#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
1424#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
1425#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
1426#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
1427#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
1428#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
1429#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
1430#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
1431#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
1432#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
1433#define BNX_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
1434#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
1435#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
1436#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
1437#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
1438#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
1439#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
1440#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
1441#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
1442#define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
1443#define BNX_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
1444#define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
1445
1446#define BNX_MISC_GPIO 0x0000081c
1447#define BNX_MISC_GPIO_VALUE (0xffL<<0)
1448#define BNX_MISC_GPIO_SET (0xffL<<8)
1449#define BNX_MISC_GPIO_CLR (0xffL<<16)
1450#define BNX_MISC_GPIO_FLOAT (0xffL<<24)
1451
1452#define BNX_MISC_GPIO_INT 0x00000820
1453#define BNX_MISC_GPIO_INT_INT_STATE (0xfL<<0)
1454#define BNX_MISC_GPIO_INT_OLD_VALUE (0xfL<<8)
1455#define BNX_MISC_GPIO_INT_OLD_SET (0xfL<<16)
1456#define BNX_MISC_GPIO_INT_OLD_CLR (0xfL<<24)
1457
1458#define BNX_MISC_CONFIG_LFSR 0x00000824
1459#define BNX_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
1460
1461#define BNX_MISC_LFSR_MASK_BITS 0x00000828
1462#define BNX_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1463#define BNX_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
1464#define BNX_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1465#define BNX_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1466#define BNX_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4)
1467#define BNX_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5)
1468#define BNX_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1469#define BNX_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1470#define BNX_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1471#define BNX_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9)
1472#define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1473#define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1474#define BNX_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12)
1475#define BNX_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13)
1476#define BNX_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1477#define BNX_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15)
1478#define BNX_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1479#define BNX_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17)
1480#define BNX_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18)
1481#define BNX_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19)
1482#define BNX_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1483#define BNX_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
1484#define BNX_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1485#define BNX_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1486#define BNX_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1487#define BNX_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
1488#define BNX_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
1489#define BNX_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
1490
1491#define BNX_MISC_ARB_REQ0 0x0000082c
1492#define BNX_MISC_ARB_REQ1 0x00000830
1493#define BNX_MISC_ARB_REQ2 0x00000834
1494#define BNX_MISC_ARB_REQ3 0x00000838
1495#define BNX_MISC_ARB_REQ4 0x0000083c
1496#define BNX_MISC_ARB_FREE0 0x00000840
1497#define BNX_MISC_ARB_FREE1 0x00000844
1498#define BNX_MISC_ARB_FREE2 0x00000848
1499#define BNX_MISC_ARB_FREE3 0x0000084c
1500#define BNX_MISC_ARB_FREE4 0x00000850
1501#define BNX_MISC_ARB_REQ_STATUS0 0x00000854
1502#define BNX_MISC_ARB_REQ_STATUS1 0x00000858
1503#define BNX_MISC_ARB_REQ_STATUS2 0x0000085c
1504#define BNX_MISC_ARB_REQ_STATUS3 0x00000860
1505#define BNX_MISC_ARB_REQ_STATUS4 0x00000864
1506#define BNX_MISC_ARB_GNT0 0x00000868
1507#define BNX_MISC_ARB_GNT0_0 (0x7L<<0)
1508#define BNX_MISC_ARB_GNT0_1 (0x7L<<4)
1509#define BNX_MISC_ARB_GNT0_2 (0x7L<<8)
1510#define BNX_MISC_ARB_GNT0_3 (0x7L<<12)
1511#define BNX_MISC_ARB_GNT0_4 (0x7L<<16)
1512#define BNX_MISC_ARB_GNT0_5 (0x7L<<20)
1513#define BNX_MISC_ARB_GNT0_6 (0x7L<<24)
1514#define BNX_MISC_ARB_GNT0_7 (0x7L<<28)
1515
1516#define BNX_MISC_ARB_GNT1 0x0000086c
1517#define BNX_MISC_ARB_GNT1_8 (0x7L<<0)
1518#define BNX_MISC_ARB_GNT1_9 (0x7L<<4)
1519#define BNX_MISC_ARB_GNT1_10 (0x7L<<8)
1520#define BNX_MISC_ARB_GNT1_11 (0x7L<<12)
1521#define BNX_MISC_ARB_GNT1_12 (0x7L<<16)
1522#define BNX_MISC_ARB_GNT1_13 (0x7L<<20)
1523#define BNX_MISC_ARB_GNT1_14 (0x7L<<24)
1524#define BNX_MISC_ARB_GNT1_15 (0x7L<<28)
1525
1526#define BNX_MISC_ARB_GNT2 0x00000870
1527#define BNX_MISC_ARB_GNT2_16 (0x7L<<0)
1528#define BNX_MISC_ARB_GNT2_17 (0x7L<<4)
1529#define BNX_MISC_ARB_GNT2_18 (0x7L<<8)
1530#define BNX_MISC_ARB_GNT2_19 (0x7L<<12)
1531#define BNX_MISC_ARB_GNT2_20 (0x7L<<16)
1532#define BNX_MISC_ARB_GNT2_21 (0x7L<<20)
1533#define BNX_MISC_ARB_GNT2_22 (0x7L<<24)
1534#define BNX_MISC_ARB_GNT2_23 (0x7L<<28)
1535
1536#define BNX_MISC_ARB_GNT3 0x00000874
1537#define BNX_MISC_ARB_GNT3_24 (0x7L<<0)
1538#define BNX_MISC_ARB_GNT3_25 (0x7L<<4)
1539#define BNX_MISC_ARB_GNT3_26 (0x7L<<8)
1540#define BNX_MISC_ARB_GNT3_27 (0x7L<<12)
1541#define BNX_MISC_ARB_GNT3_28 (0x7L<<16)
1542#define BNX_MISC_ARB_GNT3_29 (0x7L<<20)
1543#define BNX_MISC_ARB_GNT3_30 (0x7L<<24)
1544#define BNX_MISC_ARB_GNT3_31 (0x7L<<28)
1545
1546#define BNX_MISC_PRBS_CONTROL 0x00000878
1547#define BNX_MISC_PRBS_CONTROL_EN (1L<<0)
1548#define BNX_MISC_PRBS_CONTROL_RSTB (1L<<1)
1549#define BNX_MISC_PRBS_CONTROL_INV (1L<<2)
1550#define BNX_MISC_PRBS_CONTROL_ERR_CLR (1L<<3)
1551#define BNX_MISC_PRBS_CONTROL_ORDER (0x3L<<4)
1552#define BNX_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4)
1553#define BNX_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4)
1554#define BNX_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4)
1555#define BNX_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4)
1556
1557#define BNX_MISC_PRBS_STATUS 0x0000087c
1558#define BNX_MISC_PRBS_STATUS_LOCK (1L<<0)
1559#define BNX_MISC_PRBS_STATUS_STKY (1L<<1)
1560#define BNX_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2)
1561#define BNX_MISC_PRBS_STATUS_STATE (0xfL<<16)
1562
1563#define BNX_MISC_SM_ASF_CONTROL 0x00000880
1564#define BNX_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
1565#define BNX_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
1566#define BNX_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
1567#define BNX_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
1568#define BNX_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
1569#define BNX_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
1570#define BNX_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
1571#define BNX_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
1572#define BNX_MISC_SM_ASF_CONTROL_RES (0xfL<<8)
1573#define BNX_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
1574#define BNX_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
1575#define BNX_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
1576#define BNX_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
1577#define BNX_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16)
1578#define BNX_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24)
1579#define BNX_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
1580#define BNX_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
1581
1582#define BNX_MISC_SMB_IN 0x00000884
1583#define BNX_MISC_SMB_IN_DAT_IN (0xffL<<0)
1584#define BNX_MISC_SMB_IN_RDY (1L<<8)
1585#define BNX_MISC_SMB_IN_DONE (1L<<9)
1586#define BNX_MISC_SMB_IN_FIRSTBYTE (1L<<10)
1587#define BNX_MISC_SMB_IN_STATUS (0x7L<<11)
1588#define BNX_MISC_SMB_IN_STATUS_OK (0x0L<<11)
1589#define BNX_MISC_SMB_IN_STATUS_PEC (0x1L<<11)
1590#define BNX_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11)
1591#define BNX_MISC_SMB_IN_STATUS_STOP (0x3L<<11)
1592#define BNX_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11)
1593
1594#define BNX_MISC_SMB_OUT 0x00000888
1595#define BNX_MISC_SMB_OUT_DAT_OUT (0xffL<<0)
1596#define BNX_MISC_SMB_OUT_RDY (1L<<8)
1597#define BNX_MISC_SMB_OUT_START (1L<<9)
1598#define BNX_MISC_SMB_OUT_LAST (1L<<10)
1599#define BNX_MISC_SMB_OUT_ACC_TYPE (1L<<11)
1600#define BNX_MISC_SMB_OUT_ENB_PEC (1L<<12)
1601#define BNX_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
1602#define BNX_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
1603#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
1604#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
1605#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
1606#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
1607#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
1608#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
1609#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
1610#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
1611#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
1612#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20)
1613#define BNX_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
1614#define BNX_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
1615#define BNX_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
1616#define BNX_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
1617#define BNX_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
1618
1619#define BNX_MISC_SMB_WATCHDOG 0x0000088c
1620#define BNX_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)
1621
1622#define BNX_MISC_SMB_HEARTBEAT 0x00000890
1623#define BNX_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0)
1624
1625#define BNX_MISC_SMB_POLL_ASF 0x00000894
1626#define BNX_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0)
1627
1628#define BNX_MISC_SMB_POLL_LEGACY 0x00000898
1629#define BNX_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
1630
1631#define BNX_MISC_SMB_RETRAN 0x0000089c
1632#define BNX_MISC_SMB_RETRAN_RETRAN (0xffL<<0)
1633
1634#define BNX_MISC_SMB_TIMESTAMP 0x000008a0
1635#define BNX_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
1636
1637#define BNX_MISC_PERR_ENA0 0x000008a4
1638#define BNX_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
1639#define BNX_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1)
1640#define BNX_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2)
1641#define BNX_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3)
1642#define BNX_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4)
1643#define BNX_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5)
1644#define BNX_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6)
1645#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7)
1646#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8)
1647#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9)
1648#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10)
1649#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11)
1650#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12)
1651#define BNX_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13)
1652#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14)
1653#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15)
1654#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16)
1655#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17)
1656#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18)
1657#define BNX_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19)
1658#define BNX_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20)
1659#define BNX_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21)
1660#define BNX_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22)
1661#define BNX_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23)
1662#define BNX_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
1663#define BNX_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
1664#define BNX_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
1665#define BNX_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
1666#define BNX_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
1667#define BNX_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
1668#define BNX_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
1669#define BNX_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
1670
1671#define BNX_MISC_PERR_ENA1 0x000008a8
1672#define BNX_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
1673#define BNX_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
1674#define BNX_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
1675#define BNX_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
1676#define BNX_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
1677#define BNX_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)
1678#define BNX_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6)
1679#define BNX_MISC_PERR_ENA1_TBDC_MISC (1L<<7)
1680#define BNX_MISC_PERR_ENA1_TDMA_MISC (1L<<8)
1681#define BNX_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9)
1682#define BNX_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10)
1683#define BNX_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11)
1684#define BNX_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12)
1685#define BNX_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13)
1686#define BNX_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14)
1687#define BNX_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15)
1688#define BNX_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16)
1689#define BNX_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17)
1690#define BNX_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18)
1691#define BNX_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19)
1692#define BNX_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20)
1693#define BNX_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21)
1694#define BNX_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22)
1695#define BNX_MISC_PERR_ENA1_CSQ_MISC (1L<<23)
1696#define BNX_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
1697#define BNX_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
1698#define BNX_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
1699#define BNX_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
1700#define BNX_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
1701#define BNX_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
1702#define BNX_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
1703#define BNX_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
1704
1705#define BNX_MISC_PERR_ENA2 0x000008ac
1706#define BNX_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
1707#define BNX_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
1708#define BNX_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
1709#define BNX_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
1710#define BNX_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
1711#define BNX_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
1712#define BNX_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
1713#define BNX_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
1714#define BNX_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
1715
1716#define BNX_MISC_DEBUG_VECTOR_SEL 0x000008b0
1717#define BNX_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
1718#define BNX_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
1719
1720#define BNX_MISC_VREG_CONTROL 0x000008b4
1721#define BNX_MISC_VREG_CONTROL_1_2 (0xfL<<0)
1722#define BNX_MISC_VREG_CONTROL_2_5 (0xfL<<4)
1723
1724#define BNX_MISC_FINAL_CLK_CTL_VAL 0x000008b8
1725#define BNX_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
1726
1727#define BNX_MISC_NEW_CORE_CTL 0x000008c8
1728#define BNX_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0)
1729#define BNX_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1)
1730#define BNX_MISC_NEW_CORE_CTL_DMA_ENABLE (1L<<16)
1731#define BNX_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2)
1732#define BNX_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16)
1733
1734#define BNX_MISC_DUAL_MEDIA_CTRL 0x000008ec
1735#define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID (0xffL<<0)
1736#define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0)
1737#define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3L<<0)
1738#define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12L<<0)
1739#define BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP (0x7L<<8)
1740#define BNX_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1L<<11)
1741#define BNX_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1L<<12)
1742#define BNX_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1L<<13)
1743#define BNX_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1L<<14)
1744#define BNX_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1L<<15)
1745#define BNX_MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1L<<16)
1746#define BNX_MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1L<<17)
1747#define BNX_MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1L<<18)
1748#define BNX_MISC_DUAL_MEDIA_CTRL_PHY1_RST (1L<<19)
1749#define BNX_MISC_DUAL_MEDIA_CTRL_PHY0_RST (1L<<20)
1750#define BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL (0x7L<<21)
1751#define BNX_MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1L<<24)
1752#define BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1L<<25)
1753#define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ (0xfL<<26)
1754#define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1L<<26)
1755#define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2L<<26)
1756#define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4L<<26)
1757#define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8L<<26)
1758
1759#define BNX_MISC_UNUSED0 0x000008bc
1760
1761
1762/*
1763 * nvm_reg definition
1764 * offset: 0x6400
1765 */
1766#define BNX_NVM_COMMAND 0x00006400
1767#define BNX_NVM_COMMAND_RST (1L<<0)
1768#define BNX_NVM_COMMAND_DONE (1L<<3)
1769#define BNX_NVM_COMMAND_DOIT (1L<<4)
1770#define BNX_NVM_COMMAND_WR (1L<<5)
1771#define BNX_NVM_COMMAND_ERASE (1L<<6)
1772#define BNX_NVM_COMMAND_FIRST (1L<<7)
1773#define BNX_NVM_COMMAND_LAST (1L<<8)
1774#define BNX_NVM_COMMAND_WREN (1L<<16)
1775#define BNX_NVM_COMMAND_WRDI (1L<<17)
1776#define BNX_NVM_COMMAND_EWSR (1L<<18)
1777#define BNX_NVM_COMMAND_WRSR (1L<<19)
1778
1779#define BNX_NVM_STATUS 0x00006404
1780#define BNX_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
1781#define BNX_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
1782#define BNX_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
1783
1784#define BNX_NVM_WRITE 0x00006408
1785#define BNX_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
1786#define BNX_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
1787#define BNX_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
1788#define BNX_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
1789#define BNX_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
1790#define BNX_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
1791#define BNX_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
1792#define BNX_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
1793
1794#define BNX_NVM_ADDR 0x0000640c
1795#define BNX_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
1796#define BNX_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
1797#define BNX_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
1798#define BNX_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
1799#define BNX_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
1800#define BNX_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
1801#define BNX_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
1802#define BNX_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
1803
1804#define BNX_NVM_READ 0x00006410
1805#define BNX_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
1806#define BNX_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
1807#define BNX_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
1808#define BNX_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
1809#define BNX_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
1810#define BNX_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
1811#define BNX_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
1812#define BNX_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
1813
1814#define BNX_NVM_CFG1 0x00006414
1815#define BNX_NVM_CFG1_FLASH_MODE (1L<<0)
1816#define BNX_NVM_CFG1_BUFFER_MODE (1L<<1)
1817#define BNX_NVM_CFG1_PASS_MODE (1L<<2)
1818#define BNX_NVM_CFG1_BITBANG_MODE (1L<<3)
1819#define BNX_NVM_CFG1_STATUS_BIT (0x7L<<4)
1820#define BNX_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
1821#define BNX_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
1822#define BNX_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
1823#define BNX_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
1824#define BNX_NVM_CFG1_PROTECT_MODE (1L<<24)
1825#define BNX_NVM_CFG1_FLASH_SIZE (1L<<25)
1826#define BNX_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
1827
1828#define BNX_NVM_CFG2 0x00006418
1829#define BNX_NVM_CFG2_ERASE_CMD (0xffL<<0)
1830#define BNX_NVM_CFG2_DUMMY (0xffL<<8)
1831#define BNX_NVM_CFG2_STATUS_CMD (0xffL<<16)
1832
1833#define BNX_NVM_CFG3 0x0000641c
1834#define BNX_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
1835#define BNX_NVM_CFG3_WRITE_CMD (0xffL<<8)
1836#define BNX_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16)
1837#define BNX_NVM_CFG3_READ_CMD (0xffL<<24)
1838
1839#define BNX_NVM_SW_ARB 0x00006420
1840#define BNX_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
1841#define BNX_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
1842#define BNX_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
1843#define BNX_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
1844#define BNX_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
1845#define BNX_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
1846#define BNX_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
1847#define BNX_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
1848#define BNX_NVM_SW_ARB_ARB_ARB0 (1L<<8)
1849#define BNX_NVM_SW_ARB_ARB_ARB1 (1L<<9)
1850#define BNX_NVM_SW_ARB_ARB_ARB2 (1L<<10)
1851#define BNX_NVM_SW_ARB_ARB_ARB3 (1L<<11)
1852#define BNX_NVM_SW_ARB_REQ0 (1L<<12)
1853#define BNX_NVM_SW_ARB_REQ1 (1L<<13)
1854#define BNX_NVM_SW_ARB_REQ2 (1L<<14)
1855#define BNX_NVM_SW_ARB_REQ3 (1L<<15)
1856
1857#define BNX_NVM_ACCESS_ENABLE 0x00006424
1858#define BNX_NVM_ACCESS_ENABLE_EN (1L<<0)
1859#define BNX_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
1860
1861#define BNX_NVM_WRITE1 0x00006428
1862#define BNX_NVM_WRITE1_WREN_CMD (0xffL<<0)
1863#define BNX_NVM_WRITE1_WRDI_CMD (0xffL<<8)
1864#define BNX_NVM_WRITE1_SR_DATA (0xffL<<16)
1865
1866
1867
1868/*
1869 * dma_reg definition
1870 * offset: 0xc00
1871 */
1872#define BNX_DMA_COMMAND 0x00000c00
1873#define BNX_DMA_COMMAND_ENABLE (1L<<0)
1874
1875#define BNX_DMA_STATUS 0x00000c04
1876#define BNX_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
1877#define BNX_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16)
1878#define BNX_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17)
1879#define BNX_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18)
1880#define BNX_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19)
1881#define BNX_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20)
1882#define BNX_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21)
1883#define BNX_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22)
1884#define BNX_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
1885#define BNX_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
1886#define BNX_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
1887
1888#define BNX_DMA_CONFIG 0x00000c08
1889#define BNX_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
1890#define BNX_DMA_CONFIG_DATA_WORD_SWAP (1L<<1)
1891#define BNX_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4)
1892#define BNX_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5)
1893#define BNX_DMA_CONFIG_ONE_DMA (1L<<6)
1894#define BNX_DMA_CONFIG_CNTL_TWO_DMA (1L<<7)
1895#define BNX_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8)
1896#define BNX_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10)
1897#define BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11)
1898#define BNX_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12)
1899#define BNX_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16)
1900#define BNX_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20)
1901#define BNX_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23)
1902#define BNX_DMA_CONFIG_BIG_SIZE (0xfL<<24)
1903#define BNX_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24)
1904#define BNX_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24)
1905#define BNX_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24)
1906#define BNX_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24)
1907#define BNX_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24)
1908
1909#define BNX_DMA_BLACKOUT 0x00000c0c
1910#define BNX_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0)
1911#define BNX_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8)
1912#define BNX_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16)
1913
1914#define BNX_DMA_RCHAN_STAT 0x00000c30
1915#define BNX_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0)
1916#define BNX_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3)
1917#define BNX_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4)
1918#define BNX_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7)
1919#define BNX_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8)
1920#define BNX_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11)
1921#define BNX_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12)
1922#define BNX_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15)
1923#define BNX_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16)
1924#define BNX_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19)
1925#define BNX_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20)
1926#define BNX_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23)
1927#define BNX_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24)
1928#define BNX_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27)
1929#define BNX_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28)
1930#define BNX_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31)
1931
1932#define BNX_DMA_WCHAN_STAT 0x00000c34
1933#define BNX_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0)
1934#define BNX_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3)
1935#define BNX_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4)
1936#define BNX_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7)
1937#define BNX_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8)
1938#define BNX_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11)
1939#define BNX_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12)
1940#define BNX_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15)
1941#define BNX_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16)
1942#define BNX_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19)
1943#define BNX_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20)
1944#define BNX_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23)
1945#define BNX_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24)
1946#define BNX_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27)
1947#define BNX_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28)
1948#define BNX_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31)
1949
1950#define BNX_DMA_RCHAN_ASSIGNMENT 0x00000c38
1951#define BNX_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0)
1952#define BNX_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4)
1953#define BNX_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8)
1954#define BNX_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12)
1955#define BNX_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16)
1956#define BNX_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20)
1957#define BNX_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24)
1958#define BNX_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28)
1959
1960#define BNX_DMA_WCHAN_ASSIGNMENT 0x00000c3c
1961#define BNX_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0)
1962#define BNX_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4)
1963#define BNX_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8)
1964#define BNX_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12)
1965#define BNX_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16)
1966#define BNX_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20)
1967#define BNX_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24)
1968#define BNX_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28)
1969
1970#define BNX_DMA_RCHAN_STAT_00 0x00000c40
1971#define BNX_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
1972
1973#define BNX_DMA_RCHAN_STAT_01 0x00000c44
1974#define BNX_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
1975
1976#define BNX_DMA_RCHAN_STAT_02 0x00000c48
1977#define BNX_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0)
1978#define BNX_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16)
1979#define BNX_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17)
1980#define BNX_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18)
1981
1982#define BNX_DMA_RCHAN_STAT_10 0x00000c4c
1983#define BNX_DMA_RCHAN_STAT_11 0x00000c50
1984#define BNX_DMA_RCHAN_STAT_12 0x00000c54
1985#define BNX_DMA_RCHAN_STAT_20 0x00000c58
1986#define BNX_DMA_RCHAN_STAT_21 0x00000c5c
1987#define BNX_DMA_RCHAN_STAT_22 0x00000c60
1988#define BNX_DMA_RCHAN_STAT_30 0x00000c64
1989#define BNX_DMA_RCHAN_STAT_31 0x00000c68
1990#define BNX_DMA_RCHAN_STAT_32 0x00000c6c
1991#define BNX_DMA_RCHAN_STAT_40 0x00000c70
1992#define BNX_DMA_RCHAN_STAT_41 0x00000c74
1993#define BNX_DMA_RCHAN_STAT_42 0x00000c78
1994#define BNX_DMA_RCHAN_STAT_50 0x00000c7c
1995#define BNX_DMA_RCHAN_STAT_51 0x00000c80
1996#define BNX_DMA_RCHAN_STAT_52 0x00000c84
1997#define BNX_DMA_RCHAN_STAT_60 0x00000c88
1998#define BNX_DMA_RCHAN_STAT_61 0x00000c8c
1999#define BNX_DMA_RCHAN_STAT_62 0x00000c90
2000#define BNX_DMA_RCHAN_STAT_70 0x00000c94
2001#define BNX_DMA_RCHAN_STAT_71 0x00000c98
2002#define BNX_DMA_RCHAN_STAT_72 0x00000c9c
2003#define BNX_DMA_WCHAN_STAT_00 0x00000ca0
2004#define BNX_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
2005
2006#define BNX_DMA_WCHAN_STAT_01 0x00000ca4
2007#define BNX_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
2008
2009#define BNX_DMA_WCHAN_STAT_02 0x00000ca8
2010#define BNX_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0)
2011#define BNX_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16)
2012#define BNX_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17)
2013#define BNX_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18)
2014
2015#define BNX_DMA_WCHAN_STAT_10 0x00000cac
2016#define BNX_DMA_WCHAN_STAT_11 0x00000cb0
2017#define BNX_DMA_WCHAN_STAT_12 0x00000cb4
2018#define BNX_DMA_WCHAN_STAT_20 0x00000cb8
2019#define BNX_DMA_WCHAN_STAT_21 0x00000cbc
2020#define BNX_DMA_WCHAN_STAT_22 0x00000cc0
2021#define BNX_DMA_WCHAN_STAT_30 0x00000cc4
2022#define BNX_DMA_WCHAN_STAT_31 0x00000cc8
2023#define BNX_DMA_WCHAN_STAT_32 0x00000ccc
2024#define BNX_DMA_WCHAN_STAT_40 0x00000cd0
2025#define BNX_DMA_WCHAN_STAT_41 0x00000cd4
2026#define BNX_DMA_WCHAN_STAT_42 0x00000cd8
2027#define BNX_DMA_WCHAN_STAT_50 0x00000cdc
2028#define BNX_DMA_WCHAN_STAT_51 0x00000ce0
2029#define BNX_DMA_WCHAN_STAT_52 0x00000ce4
2030#define BNX_DMA_WCHAN_STAT_60 0x00000ce8
2031#define BNX_DMA_WCHAN_STAT_61 0x00000cec
2032#define BNX_DMA_WCHAN_STAT_62 0x00000cf0
2033#define BNX_DMA_WCHAN_STAT_70 0x00000cf4
2034#define BNX_DMA_WCHAN_STAT_71 0x00000cf8
2035#define BNX_DMA_WCHAN_STAT_72 0x00000cfc
2036#define BNX_DMA_ARB_STAT_00 0x00000d00
2037#define BNX_DMA_ARB_STAT_00_MASTER (0xffffL<<0)
2038#define BNX_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16)
2039#define BNX_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24)
2040
2041#define BNX_DMA_ARB_STAT_01 0x00000d04
2042#define BNX_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0)
2043#define BNX_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4)
2044#define BNX_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8)
2045#define BNX_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12)
2046#define BNX_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16)
2047#define BNX_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20)
2048#define BNX_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24)
2049#define BNX_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28)
2050
2051#define BNX_DMA_FUSE_CTRL0_CMD 0x00000f00
2052#define BNX_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
2053#define BNX_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1)
2054#define BNX_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2)
2055#define BNX_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3)
2056#define BNX_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8)
2057
2058#define BNX_DMA_FUSE_CTRL0_DATA 0x00000f04
2059#define BNX_DMA_FUSE_CTRL1_CMD 0x00000f08
2060#define BNX_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
2061#define BNX_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1)
2062#define BNX_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2)
2063#define BNX_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3)
2064#define BNX_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8)
2065
2066#define BNX_DMA_FUSE_CTRL1_DATA 0x00000f0c
2067#define BNX_DMA_FUSE_CTRL2_CMD 0x00000f10
2068#define BNX_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
2069#define BNX_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1)
2070#define BNX_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2)
2071#define BNX_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3)
2072#define BNX_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8)
2073
2074#define BNX_DMA_FUSE_CTRL2_DATA 0x00000f14
2075
2076
2077/*
2078 * context_reg definition
2079 * offset: 0x1000
2080 */
2081#define BNX_CTX_COMMAND 0x00001000
2082#define BNX_CTX_COMMAND_ENABLED (1L<<0)
2083#define BNX_CTX_COMMAND_DISABLE_USAGE_CNT (1L<<1)
2084#define BNX_CTX_COMMAND_DISABLE_PLRU (1L<<2)
2085#define BNX_CTX_COMMAND_DISABLE_COMBINE_READ (1L<<3)
2086#define BNX_CTX_COMMAND_FLUSH_AHEAD (0x1fL<<8)
2087#define BNX_CTX_COMMAND_MEM_INIT (1L<<13)
2088#define BNX_CTX_COMMAND_PAGE_SIZE (0xfL<<16)
2089#define BNX_CTX_COMMAND_PAGE_SIZE_256 (0L<<16)
2090#define BNX_CTX_COMMAND_PAGE_SIZE_512 (1L<<16)
2091#define BNX_CTX_COMMAND_PAGE_SIZE_1K (2L<<16)
2092#define BNX_CTX_COMMAND_PAGE_SIZE_2K (3L<<16)
2093#define BNX_CTX_COMMAND_PAGE_SIZE_4K (4L<<16)
2094#define BNX_CTX_COMMAND_PAGE_SIZE_8K (5L<<16)
2095#define BNX_CTX_COMMAND_PAGE_SIZE_16K (6L<<16)
2096#define BNX_CTX_COMMAND_PAGE_SIZE_32K (7L<<16)
2097#define BNX_CTX_COMMAND_PAGE_SIZE_64K (8L<<16)
2098#define BNX_CTX_COMMAND_PAGE_SIZE_128K (9L<<16)
2099#define BNX_CTX_COMMAND_PAGE_SIZE_256K (10L<<16)
2100#define BNX_CTX_COMMAND_PAGE_SIZE_512K (11L<<16)
2101#define BNX_CTX_COMMAND_PAGE_SIZE_1M (12L<<16)
2102
2103#define BNX_CTX_STATUS 0x00001004
2104#define BNX_CTX_STATUS_LOCK_WAIT (1L<<0)
2105#define BNX_CTX_STATUS_READ_STAT (1L<<16)
2106#define BNX_CTX_STATUS_WRITE_STAT (1L<<17)
2107#define BNX_CTX_STATUS_ACC_STALL_STAT (1L<<18)
2108#define BNX_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
2109
2110#define BNX_CTX_VIRT_ADDR 0x00001008
2111#define BNX_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
2112
2113#define BNX_CTX_PAGE_TBL 0x0000100c
2114#define BNX_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
2115
2116#define BNX_CTX_DATA_ADR 0x00001010
2117#define BNX_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
2118
2119#define BNX_CTX_DATA 0x00001014
2120#define BNX_CTX_LOCK 0x00001018
2121#define BNX_CTX_LOCK_TYPE (0x7L<<0)
2122#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
2123#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
2124#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
2125#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
2126#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
2127#define BNX_CTX_LOCK_CID_VALUE (0x3fffL<<7)
2128#define BNX_CTX_LOCK_GRANTED (1L<<26)
2129#define BNX_CTX_LOCK_MODE (0x7L<<27)
2130#define BNX_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
2131#define BNX_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
2132#define BNX_CTX_LOCK_MODE_SURE (0x2L<<27)
2133#define BNX_CTX_LOCK_STATUS (1L<<30)
2134#define BNX_CTX_LOCK_REQ (1L<<31)
2135
2136#define BNX_CTX_CTX_CTRL 0x0000101c
2137#define BNX_CTX_CTX_CTRL_CTX_ADDR (0x7ffffL<<2)
2138#define BNX_CTX_CTX_CTRL_MOD_USAGE_CNT (0x3L<<21)
2139#define BNX_CTX_CTX_CTRL_NO_RAM_ACC (1L<<23)
2140#define BNX_CTX_CTX_CTRL_PREFETCH_SIZE (0x3L<<24)
2141#define BNX_CTX_CTX_CTRL_ATTR (1L<<26)
2142#define BNX_CTX_CTX_CTRL_WRITE_REQ (1L<<30)
2143#define BNX_CTX_CTX_CTRL_READ_REQ (1L<<31)
2144
2145#define BNX_CTX_CTX_DATA 0x00001020
2146
2147#define BNX_CTX_ACCESS_STATUS 0x00001040
2148#define BNX_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
2149#define BNX_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
2150#define BNX_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
2151#define BNX_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
2152#define BNX_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
2153#define BNX_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI (0x1fL<<0)
2154#define BNX_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI (0x1fL<<5)
2155#define BNX_CTX_ACCESS_STATUS_REQUEST_XI (0x3fffffL<<10)
2156
2157#define BNX_CTX_DBG_LOCK_STATUS 0x00001044
2158#define BNX_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
2159#define BNX_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
2160
2161#define BNX_CTX_CHNL_LOCK_STATUS_0 0x00001080
2162#define BNX_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
2163#define BNX_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
2164#define BNX_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
2165
2166#define BNX_CTX_CHNL_LOCK_STATUS_1 0x00001084
2167#define BNX_CTX_CHNL_LOCK_STATUS_2 0x00001088
2168#define BNX_CTX_CHNL_LOCK_STATUS_3 0x0000108c
2169#define BNX_CTX_CHNL_LOCK_STATUS_4 0x00001090
2170#define BNX_CTX_CHNL_LOCK_STATUS_5 0x00001094
2171#define BNX_CTX_CHNL_LOCK_STATUS_6 0x00001098
2172#define BNX_CTX_CHNL_LOCK_STATUS_7 0x0000109c
2173#define BNX_CTX_CHNL_LOCK_STATUS_8 0x000010a0
2174
2175#define BNX_CTX_CACHE_DATA 0x000010c4
2176#define BNX_CTX_HOST_PAGE_TBL_CTRL 0x000010c8
2177#define BNX_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR (0x1ffL<<0)
2178#define BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1L<<30)
2179#define BNX_CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1L<<31)
2180
2181#define BNX_CTX_HOST_PAGE_TBL_DATA0 0x000010cc
2182#define BNX_CTX_HOST_PAGE_TBL_DATA0_VALID (1L<<0)
2183#define BNX_CTX_HOST_PAGE_TBL_DATA0_VALUE (0xffffffL<<8)
2184
2185#define BNX_CTX_HOST_PAGE_TBL_DATA1 0x000010d0
2186
2187/*
2188 * emac_reg definition
2189 * offset: 0x1400
2190 */
2191#define BNX_EMAC_MODE 0x00001400
2192#define BNX_EMAC_MODE_RESET (1L<<0)
2193#define BNX_EMAC_MODE_HALF_DUPLEX (1L<<1)
2194#define BNX_EMAC_MODE_PORT (0x3L<<2)
2195#define BNX_EMAC_MODE_PORT_NONE (0L<<2)
2196#define BNX_EMAC_MODE_PORT_MII (1L<<2)
2197#define BNX_EMAC_MODE_PORT_GMII (2L<<2)
2198#define BNX_EMAC_MODE_PORT_MII_10 (3L<<2)
2199#define BNX_EMAC_MODE_MAC_LOOP (1L<<4)
2200#define BNX_EMAC_MODE_25G (1L<<5)
2201#define BNX_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
2202#define BNX_EMAC_MODE_TX_BURST (1L<<8)
2203#define BNX_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
2204#define BNX_EMAC_MODE_EXT_LINK_POL (1L<<10)
2205#define BNX_EMAC_MODE_FORCE_LINK (1L<<11)
2206#define BNX_EMAC_MODE_MPKT (1L<<18)
2207#define BNX_EMAC_MODE_MPKT_RCVD (1L<<19)
2208#define BNX_EMAC_MODE_ACPI_RCVD (1L<<20)
2209
2210#define BNX_EMAC_STATUS 0x00001404
2211#define BNX_EMAC_STATUS_LINK (1L<<11)
2212#define BNX_EMAC_STATUS_LINK_CHANGE (1L<<12)
2213#define BNX_EMAC_STATUS_MI_COMPLETE (1L<<22)
2214#define BNX_EMAC_STATUS_MI_INT (1L<<23)
2215#define BNX_EMAC_STATUS_AP_ERROR (1L<<24)
2216#define BNX_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
2217
2218#define BNX_EMAC_ATTENTION_ENA 0x00001408
2219#define BNX_EMAC_ATTENTION_ENA_LINK (1L<<11)
2220#define BNX_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
2221#define BNX_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
2222#define BNX_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
2223
2224#define BNX_EMAC_LED 0x0000140c
2225#define BNX_EMAC_LED_OVERRIDE (1L<<0)
2226#define BNX_EMAC_LED_1000MB_OVERRIDE (1L<<1)
2227#define BNX_EMAC_LED_100MB_OVERRIDE (1L<<2)
2228#define BNX_EMAC_LED_10MB_OVERRIDE (1L<<3)
2229#define BNX_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
2230#define BNX_EMAC_LED_BLNK_TRAFFIC (1L<<5)
2231#define BNX_EMAC_LED_TRAFFIC (1L<<6)
2232#define BNX_EMAC_LED_1000MB (1L<<7)
2233#define BNX_EMAC_LED_100MB (1L<<8)
2234#define BNX_EMAC_LED_10MB (1L<<9)
2235#define BNX_EMAC_LED_TRAFFIC_STAT (1L<<10)
2236#define BNX_EMAC_LED_BLNK_RATE (0xfffL<<19)
2237#define BNX_EMAC_LED_BLNK_RATE_ENA (1L<<31)
2238
2239#define BNX_EMAC_MAC_MATCH0 0x00001410
2240#define BNX_EMAC_MAC_MATCH1 0x00001414
2241#define BNX_EMAC_MAC_MATCH2 0x00001418
2242#define BNX_EMAC_MAC_MATCH3 0x0000141c
2243#define BNX_EMAC_MAC_MATCH4 0x00001420
2244#define BNX_EMAC_MAC_MATCH5 0x00001424
2245#define BNX_EMAC_MAC_MATCH6 0x00001428
2246#define BNX_EMAC_MAC_MATCH7 0x0000142c
2247#define BNX_EMAC_MAC_MATCH8 0x00001430
2248#define BNX_EMAC_MAC_MATCH9 0x00001434
2249#define BNX_EMAC_MAC_MATCH10 0x00001438
2250#define BNX_EMAC_MAC_MATCH11 0x0000143c
2251#define BNX_EMAC_MAC_MATCH12 0x00001440
2252#define BNX_EMAC_MAC_MATCH13 0x00001444
2253#define BNX_EMAC_MAC_MATCH14 0x00001448
2254#define BNX_EMAC_MAC_MATCH15 0x0000144c
2255#define BNX_EMAC_MAC_MATCH16 0x00001450
2256#define BNX_EMAC_MAC_MATCH17 0x00001454
2257#define BNX_EMAC_MAC_MATCH18 0x00001458
2258#define BNX_EMAC_MAC_MATCH19 0x0000145c
2259#define BNX_EMAC_MAC_MATCH20 0x00001460
2260#define BNX_EMAC_MAC_MATCH21 0x00001464
2261#define BNX_EMAC_MAC_MATCH22 0x00001468
2262#define BNX_EMAC_MAC_MATCH23 0x0000146c
2263#define BNX_EMAC_MAC_MATCH24 0x00001470
2264#define BNX_EMAC_MAC_MATCH25 0x00001474
2265#define BNX_EMAC_MAC_MATCH26 0x00001478
2266#define BNX_EMAC_MAC_MATCH27 0x0000147c
2267#define BNX_EMAC_MAC_MATCH28 0x00001480
2268#define BNX_EMAC_MAC_MATCH29 0x00001484
2269#define BNX_EMAC_MAC_MATCH30 0x00001488
2270#define BNX_EMAC_MAC_MATCH31 0x0000148c
2271#define BNX_EMAC_BACKOFF_SEED 0x00001498
2272#define BNX_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
2273
2274#define BNX_EMAC_RX_MTU_SIZE 0x0000149c
2275#define BNX_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
2276#define BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
2277
2278#define BNX_EMAC_SERDES_CNTL 0x000014a4
2279#define BNX_EMAC_SERDES_CNTL_RXR (0x7L<<0)
2280#define BNX_EMAC_SERDES_CNTL_RXG (0x3L<<3)
2281#define BNX_EMAC_SERDES_CNTL_RXCKSEL (1L<<6)
2282#define BNX_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7)
2283#define BNX_EMAC_SERDES_CNTL_BGMAX (1L<<10)
2284#define BNX_EMAC_SERDES_CNTL_BGMIN (1L<<11)
2285#define BNX_EMAC_SERDES_CNTL_TXMODE (1L<<12)
2286#define BNX_EMAC_SERDES_CNTL_TXEDGE (1L<<13)
2287#define BNX_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14)
2288#define BNX_EMAC_SERDES_CNTL_PLLTEST (1L<<15)
2289#define BNX_EMAC_SERDES_CNTL_CDET_EN (1L<<16)
2290#define BNX_EMAC_SERDES_CNTL_TBI_LBK (1L<<17)
2291#define BNX_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18)
2292#define BNX_EMAC_SERDES_CNTL_REV_PHASE (1L<<19)
2293#define BNX_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20)
2294#define BNX_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22)
2295
2296#define BNX_EMAC_SERDES_STATUS 0x000014a8
2297#define BNX_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0)
2298#define BNX_EMAC_SERDES_STATUS_COMMA_DET (1L<<8)
2299
2300#define BNX_EMAC_MDIO_COMM 0x000014ac
2301#define BNX_EMAC_MDIO_COMM_DATA (0xffffL<<0)
2302#define BNX_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
2303#define BNX_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
2304#define BNX_EMAC_MDIO_COMM_COMMAND (0x3L<<26)
2305#define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
2306#define BNX_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
2307#define BNX_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
2308#define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
2309#define BNX_EMAC_MDIO_COMM_FAIL (1L<<28)
2310#define BNX_EMAC_MDIO_COMM_START_BUSY (1L<<29)
2311#define BNX_EMAC_MDIO_COMM_DISEXT (1L<<30)
2312
2313#define BNX_EMAC_MDIO_STATUS 0x000014b0
2314#define BNX_EMAC_MDIO_STATUS_LINK (1L<<0)
2315#define BNX_EMAC_MDIO_STATUS_10MB (1L<<1)
2316
2317#define BNX_EMAC_MDIO_MODE 0x000014b4
2318#define BNX_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
2319#define BNX_EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
2320#define BNX_EMAC_MDIO_MODE_BIT_BANG (1L<<8)
2321#define BNX_EMAC_MDIO_MODE_MDIO (1L<<9)
2322#define BNX_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
2323#define BNX_EMAC_MDIO_MODE_MDC (1L<<11)
2324#define BNX_EMAC_MDIO_MODE_MDINT (1L<<12)
2325#define BNX_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16)
2326
2327#define BNX_EMAC_MDIO_AUTO_STATUS 0x000014b8
2328#define BNX_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
2329
2330#define BNX_EMAC_TX_MODE 0x000014bc
2331#define BNX_EMAC_TX_MODE_RESET (1L<<0)
2332#define BNX_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
2333#define BNX_EMAC_TX_MODE_FLOW_EN (1L<<4)
2334#define BNX_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
2335#define BNX_EMAC_TX_MODE_LONG_PAUSE (1L<<6)
2336#define BNX_EMAC_TX_MODE_LINK_AWARE (1L<<7)
2337
2338#define BNX_EMAC_TX_STATUS 0x000014c0
2339#define BNX_EMAC_TX_STATUS_XOFFED (1L<<0)
2340#define BNX_EMAC_TX_STATUS_XOFF_SENT (1L<<1)
2341#define BNX_EMAC_TX_STATUS_XON_SENT (1L<<2)
2342#define BNX_EMAC_TX_STATUS_LINK_UP (1L<<3)
2343#define BNX_EMAC_TX_STATUS_UNDERRUN (1L<<4)
2344
2345#define BNX_EMAC_TX_LENGTHS 0x000014c4
2346#define BNX_EMAC_TX_LENGTHS_SLOT (0xffL<<0)
2347#define BNX_EMAC_TX_LENGTHS_IPG (0xfL<<8)
2348#define BNX_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
2349
2350#define BNX_EMAC_RX_MODE 0x000014c8
2351#define BNX_EMAC_RX_MODE_RESET (1L<<0)
2352#define BNX_EMAC_RX_MODE_FLOW_EN (1L<<2)
2353#define BNX_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
2354#define BNX_EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
2355#define BNX_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
2356#define BNX_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
2357#define BNX_EMAC_RX_MODE_LLC_CHK (1L<<7)
2358#define BNX_EMAC_RX_MODE_PROMISCUOUS (1L<<8)
2359#define BNX_EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
2360#define BNX_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
2361#define BNX_EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
2362#define BNX_EMAC_RX_MODE_SORT_MODE (1L<<12)
2363
2364#define BNX_EMAC_RX_STATUS 0x000014cc
2365#define BNX_EMAC_RX_STATUS_FFED (1L<<0)
2366#define BNX_EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
2367#define BNX_EMAC_RX_STATUS_N_RECEIVED (1L<<2)
2368
2369#define BNX_EMAC_MULTICAST_HASH0 0x000014d0
2370#define BNX_EMAC_MULTICAST_HASH1 0x000014d4
2371#define BNX_EMAC_MULTICAST_HASH2 0x000014d8
2372#define BNX_EMAC_MULTICAST_HASH3 0x000014dc
2373#define BNX_EMAC_MULTICAST_HASH4 0x000014e0
2374#define BNX_EMAC_MULTICAST_HASH5 0x000014e4
2375#define BNX_EMAC_MULTICAST_HASH6 0x000014e8
2376#define BNX_EMAC_MULTICAST_HASH7 0x000014ec
2377#define BNX_EMAC_RX_STAT_IFHCINOCTETS 0x00001500
2378#define BNX_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504
2379#define BNX_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508
2380#define BNX_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c
2381#define BNX_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510
2382#define BNX_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514
2383#define BNX_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518
2384#define BNX_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c
2385#define BNX_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520
2386#define BNX_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524
2387#define BNX_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528
2388#define BNX_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c
2389#define BNX_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530
2390#define BNX_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534
2391#define BNX_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538
2392#define BNX_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c
2393#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540
2394#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544
2395#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548
2396#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c
2397#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550
2398#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
2399#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558
2400#define BNX_EMAC_RXMAC_DEBUG0 0x0000155c
2401#define BNX_EMAC_RXMAC_DEBUG1 0x00001560
2402#define BNX_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
2403#define BNX_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
2404#define BNX_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
2405#define BNX_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
2406#define BNX_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
2407#define BNX_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
2408#define BNX_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
2409#define BNX_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
2410#define BNX_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
2411
2412#define BNX_EMAC_RXMAC_DEBUG2 0x00001564
2413#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
2414#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0)
2415#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0)
2416#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0)
2417#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0)
2418#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0)
2419#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0)
2420#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0)
2421#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0)
2422#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
2423#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3)
2424#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3)
2425#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3)
2426#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3)
2427#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3)
2428#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3)
2429#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3)
2430#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3)
2431#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3)
2432#define BNX_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
2433#define BNX_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
2434#define BNX_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
2435#define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
2436#define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
2437#define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
2438#define BNX_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
2439#define BNX_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
2440
2441#define BNX_EMAC_RXMAC_DEBUG3 0x00001568
2442#define BNX_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
2443#define BNX_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
2444
2445#define BNX_EMAC_RXMAC_DEBUG4 0x0000156c
2446#define BNX_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
2447#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
2448#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16)
2449#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16)
2450#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16)
2451#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16)
2452#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
2453#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16)
2454#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16)
2455#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16)
2456#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16)
2457#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16)
2458#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16)
2459#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16)
2460#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16)
2461#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16)
2462#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16)
2463#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16)
2464#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16)
2465#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16)
2466#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16)
2467#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16)
2468#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16)
2469#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16)
2470#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16)
2471#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16)
2472#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16)
2473#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16)
2474#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16)
2475#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16)
2476#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16)
2477#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16)
2478#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16)
2479#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16)
2480#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16)
2481#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16)
2482#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16)
2483#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16)
2484#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16)
2485#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16)
2486#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16)
2487#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16)
2488#define BNX_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
2489#define BNX_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
2490#define BNX_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
2491#define BNX_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
2492#define BNX_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26)
2493#define BNX_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
2494#define BNX_EMAC_RXMAC_DEBUG4_START (1L<<28)
2495
2496#define BNX_EMAC_RXMAC_DEBUG5 0x00001570
2497#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
2498#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
2499#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
2500#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
2501#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
2502#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
2503#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
2504#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
2505#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
2506#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4)
2507#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4)
2508#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4)
2509#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4)
2510#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4)
2511#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4)
2512#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4)
2513#define BNX_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
2514#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
2515#define BNX_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
2516#define BNX_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
2517#define BNX_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
2518#define BNX_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
2519#define BNX_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
2520#define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
2521#define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
2522#define BNX_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
2523
2524#define BNX_EMAC_RX_STAT_AC0 0x00001580
2525#define BNX_EMAC_RX_STAT_AC1 0x00001584
2526#define BNX_EMAC_RX_STAT_AC2 0x00001588
2527#define BNX_EMAC_RX_STAT_AC3 0x0000158c
2528#define BNX_EMAC_RX_STAT_AC4 0x00001590
2529#define BNX_EMAC_RX_STAT_AC5 0x00001594
2530#define BNX_EMAC_RX_STAT_AC6 0x00001598
2531#define BNX_EMAC_RX_STAT_AC7 0x0000159c
2532#define BNX_EMAC_RX_STAT_AC8 0x000015a0
2533#define BNX_EMAC_RX_STAT_AC9 0x000015a4
2534#define BNX_EMAC_RX_STAT_AC10 0x000015a8
2535#define BNX_EMAC_RX_STAT_AC11 0x000015ac
2536#define BNX_EMAC_RX_STAT_AC12 0x000015b0
2537#define BNX_EMAC_RX_STAT_AC13 0x000015b4
2538#define BNX_EMAC_RX_STAT_AC14 0x000015b8
2539#define BNX_EMAC_RX_STAT_AC15 0x000015bc
2540#define BNX_EMAC_RX_STAT_AC16 0x000015c0
2541#define BNX_EMAC_RX_STAT_AC17 0x000015c4
2542#define BNX_EMAC_RX_STAT_AC18 0x000015c8
2543#define BNX_EMAC_RX_STAT_AC19 0x000015cc
2544#define BNX_EMAC_RX_STAT_AC20 0x000015d0
2545#define BNX_EMAC_RX_STAT_AC21 0x000015d4
2546#define BNX_EMAC_RX_STAT_AC22 0x000015d8
2547#define BNX_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc
2548#define BNX_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600
2549#define BNX_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604
2550#define BNX_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608
2551#define BNX_EMAC_TX_STAT_OUTXONSENT 0x0000160c
2552#define BNX_EMAC_TX_STAT_OUTXOFFSENT 0x00001610
2553#define BNX_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614
2554#define BNX_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618
2555#define BNX_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c
2556#define BNX_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620
2557#define BNX_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624
2558#define BNX_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628
2559#define BNX_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c
2560#define BNX_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630
2561#define BNX_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634
2562#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638
2563#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c
2564#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640
2565#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644
2566#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648
2567#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
2568#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650
2569#define BNX_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654
2570#define BNX_EMAC_TXMAC_DEBUG0 0x00001658
2571#define BNX_EMAC_TXMAC_DEBUG1 0x0000165c
2572#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
2573#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0)
2574#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0)
2575#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0)
2576#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0)
2577#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0)
2578#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0)
2579#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0)
2580#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0)
2581#define BNX_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
2582#define BNX_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
2583#define BNX_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
2584#define BNX_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
2585#define BNX_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
2586#define BNX_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
2587#define BNX_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
2588#define BNX_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
2589#define BNX_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
2590#define BNX_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
2591
2592#define BNX_EMAC_TXMAC_DEBUG2 0x00001660
2593#define BNX_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
2594#define BNX_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
2595#define BNX_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
2596#define BNX_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
2597
2598#define BNX_EMAC_TXMAC_DEBUG3 0x00001664
2599#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
2600#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0)
2601#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0)
2602#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0)
2603#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0)
2604#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0)
2605#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0)
2606#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0)
2607#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0)
2608#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0)
2609#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0)
2610#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0)
2611#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0)
2612#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0)
2613#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0)
2614#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0)
2615#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
2616#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4)
2617#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4)
2618#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4)
2619#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4)
2620#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4)
2621#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4)
2622#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4)
2623#define BNX_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
2624#define BNX_EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
2625#define BNX_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
2626#define BNX_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
2627
2628#define BNX_EMAC_TXMAC_DEBUG4 0x00001668
2629#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
2630#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
2631#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16)
2632#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16)
2633#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16)
2634#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16)
2635#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16)
2636#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
2637#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
2638#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
2639#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
2640#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
2641#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16)
2642#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16)
2643#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16)
2644#define BNX_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
2645#define BNX_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
2646#define BNX_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
2647#define BNX_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
2648#define BNX_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
2649#define BNX_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
2650#define BNX_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
2651#define BNX_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
2652#define BNX_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
2653#define BNX_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
2654#define BNX_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
2655#define BNX_EMAC_TXMAC_DEBUG4_GO (1L<<31)
2656
2657#define BNX_EMAC_TX_STAT_AC0 0x00001680
2658#define BNX_EMAC_TX_STAT_AC1 0x00001684
2659#define BNX_EMAC_TX_STAT_AC2 0x00001688
2660#define BNX_EMAC_TX_STAT_AC3 0x0000168c
2661#define BNX_EMAC_TX_STAT_AC4 0x00001690
2662#define BNX_EMAC_TX_STAT_AC5 0x00001694
2663#define BNX_EMAC_TX_STAT_AC6 0x00001698
2664#define BNX_EMAC_TX_STAT_AC7 0x0000169c
2665#define BNX_EMAC_TX_STAT_AC8 0x000016a0
2666#define BNX_EMAC_TX_STAT_AC9 0x000016a4
2667#define BNX_EMAC_TX_STAT_AC10 0x000016a8
2668#define BNX_EMAC_TX_STAT_AC11 0x000016ac
2669#define BNX_EMAC_TX_STAT_AC12 0x000016b0
2670#define BNX_EMAC_TX_STAT_AC13 0x000016b4
2671#define BNX_EMAC_TX_STAT_AC14 0x000016b8
2672#define BNX_EMAC_TX_STAT_AC15 0x000016bc
2673#define BNX_EMAC_TX_STAT_AC16 0x000016c0
2674#define BNX_EMAC_TX_STAT_AC17 0x000016c4
2675#define BNX_EMAC_TX_STAT_AC18 0x000016c8
2676#define BNX_EMAC_TX_STAT_AC19 0x000016cc
2677#define BNX_EMAC_TX_STAT_AC20 0x000016d0
2678#define BNX_EMAC_TX_STAT_AC21 0x000016d4
2679#define BNX_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
2680
2681
2682/*
2683 * rpm_reg definition
2684 * offset: 0x1800
2685 */
2686#define BNX_RPM_COMMAND 0x00001800
2687#define BNX_RPM_COMMAND_ENABLED (1L<<0)
2688#define BNX_RPM_COMMAND_OVERRUN_ABORT (1L<<4)
2689
2690#define BNX_RPM_STATUS 0x00001804
2691#define BNX_RPM_STATUS_MBUF_WAIT (1L<<0)
2692#define BNX_RPM_STATUS_FREE_WAIT (1L<<1)
2693
2694#define BNX_RPM_CONFIG 0x00001808
2695#define BNX_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
2696#define BNX_RPM_CONFIG_ACPI_ENA (1L<<1)
2697#define BNX_RPM_CONFIG_ACPI_KEEP (1L<<2)
2698#define BNX_RPM_CONFIG_MP_KEEP (1L<<3)
2699#define BNX_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4)
2700#define BNX_RPM_CONFIG_IGNORE_VLAN (1L<<31)
2701
2702#define BNX_RPM_VLAN_MATCH0 0x00001810
2703#define BNX_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
2704
2705#define BNX_RPM_VLAN_MATCH1 0x00001814
2706#define BNX_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0)
2707
2708#define BNX_RPM_VLAN_MATCH2 0x00001818
2709#define BNX_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0)
2710
2711#define BNX_RPM_VLAN_MATCH3 0x0000181c
2712#define BNX_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0)
2713
2714#define BNX_RPM_SORT_USER0 0x00001820
2715#define BNX_RPM_SORT_USER0_PM_EN (0xffffL<<0)
2716#define BNX_RPM_SORT_USER0_BC_EN (1L<<16)
2717#define BNX_RPM_SORT_USER0_MC_EN (1L<<17)
2718#define BNX_RPM_SORT_USER0_MC_HSH_EN (1L<<18)
2719#define BNX_RPM_SORT_USER0_PROM_EN (1L<<19)
2720#define BNX_RPM_SORT_USER0_VLAN_EN (0xfL<<20)
2721#define BNX_RPM_SORT_USER0_PROM_VLAN (1L<<24)
2722#define BNX_RPM_SORT_USER0_ENA (1L<<31)
2723
2724#define BNX_RPM_SORT_USER1 0x00001824
2725#define BNX_RPM_SORT_USER1_PM_EN (0xffffL<<0)
2726#define BNX_RPM_SORT_USER1_BC_EN (1L<<16)
2727#define BNX_RPM_SORT_USER1_MC_EN (1L<<17)
2728#define BNX_RPM_SORT_USER1_MC_HSH_EN (1L<<18)
2729#define BNX_RPM_SORT_USER1_PROM_EN (1L<<19)
2730#define BNX_RPM_SORT_USER1_VLAN_EN (0xfL<<20)
2731#define BNX_RPM_SORT_USER1_PROM_VLAN (1L<<24)
2732#define BNX_RPM_SORT_USER1_ENA (1L<<31)
2733
2734#define BNX_RPM_SORT_USER2 0x00001828
2735#define BNX_RPM_SORT_USER2_PM_EN (0xffffL<<0)
2736#define BNX_RPM_SORT_USER2_BC_EN (1L<<16)
2737#define BNX_RPM_SORT_USER2_MC_EN (1L<<17)
2738#define BNX_RPM_SORT_USER2_MC_HSH_EN (1L<<18)
2739#define BNX_RPM_SORT_USER2_PROM_EN (1L<<19)
2740#define BNX_RPM_SORT_USER2_VLAN_EN (0xfL<<20)
2741#define BNX_RPM_SORT_USER2_PROM_VLAN (1L<<24)
2742#define BNX_RPM_SORT_USER2_ENA (1L<<31)
2743
2744#define BNX_RPM_SORT_USER3 0x0000182c
2745#define BNX_RPM_SORT_USER3_PM_EN (0xffffL<<0)
2746#define BNX_RPM_SORT_USER3_BC_EN (1L<<16)
2747#define BNX_RPM_SORT_USER3_MC_EN (1L<<17)
2748#define BNX_RPM_SORT_USER3_MC_HSH_EN (1L<<18)
2749#define BNX_RPM_SORT_USER3_PROM_EN (1L<<19)
2750#define BNX_RPM_SORT_USER3_VLAN_EN (0xfL<<20)
2751#define BNX_RPM_SORT_USER3_PROM_VLAN (1L<<24)
2752#define BNX_RPM_SORT_USER3_ENA (1L<<31)
2753
2754#define BNX_RPM_STAT_L2_FILTER_DISCARDS 0x00001840
2755#define BNX_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844
2756#define BNX_RPM_STAT_IFINFTQDISCARDS 0x00001848
2757#define BNX_RPM_STAT_IFINMBUFDISCARD 0x0000184c
2758#define BNX_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850
2759#define BNX_RPM_STAT_AC0 0x00001880
2760#define BNX_RPM_STAT_AC1 0x00001884
2761#define BNX_RPM_STAT_AC2 0x00001888
2762#define BNX_RPM_STAT_AC3 0x0000188c
2763#define BNX_RPM_STAT_AC4 0x00001890
2764#define BNX_RPM_RC_CNTL_0 0x00001900
2765#define BNX_RPM_RC_CNTL_0_OFFSET (0xffL<<0)
2766#define BNX_RPM_RC_CNTL_0_CLASS (0x7L<<8)
2767#define BNX_RPM_RC_CNTL_0_PRIORITY (1L<<11)
2768#define BNX_RPM_RC_CNTL_0_P4 (1L<<12)
2769#define BNX_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13)
2770#define BNX_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
2771#define BNX_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13)
2772#define BNX_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
2773#define BNX_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
2774#define BNX_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
2775#define BNX_RPM_RC_CNTL_0_COMP (0x3L<<16)
2776#define BNX_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
2777#define BNX_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
2778#define BNX_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
2779#define BNX_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
2780#define BNX_RPM_RC_CNTL_0_SBIT (1L<<19)
2781#define BNX_RPM_RC_CNTL_0_CMDSEL (0xfL<<20)
2782#define BNX_RPM_RC_CNTL_0_MAP (1L<<24)
2783#define BNX_RPM_RC_CNTL_0_DISCARD (1L<<25)
2784#define BNX_RPM_RC_CNTL_0_MASK (1L<<26)
2785#define BNX_RPM_RC_CNTL_0_P1 (1L<<27)
2786#define BNX_RPM_RC_CNTL_0_P2 (1L<<28)
2787#define BNX_RPM_RC_CNTL_0_P3 (1L<<29)
2788#define BNX_RPM_RC_CNTL_0_NBIT (1L<<30)
2789
2790#define BNX_RPM_RC_VALUE_MASK_0 0x00001904
2791#define BNX_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0)
2792#define BNX_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16)
2793
2794#define BNX_RPM_RC_CNTL_1 0x00001908
2795#define BNX_RPM_RC_CNTL_1_A (0x3ffffL<<0)
2796#define BNX_RPM_RC_CNTL_1_B (0xfffL<<19)
2797
2798#define BNX_RPM_RC_VALUE_MASK_1 0x0000190c
2799#define BNX_RPM_RC_CNTL_2 0x00001910
2800#define BNX_RPM_RC_CNTL_2_A (0x3ffffL<<0)
2801#define BNX_RPM_RC_CNTL_2_B (0xfffL<<19)
2802
2803#define BNX_RPM_RC_VALUE_MASK_2 0x00001914
2804#define BNX_RPM_RC_CNTL_3 0x00001918
2805#define BNX_RPM_RC_CNTL_3_A (0x3ffffL<<0)
2806#define BNX_RPM_RC_CNTL_3_B (0xfffL<<19)
2807
2808#define BNX_RPM_RC_VALUE_MASK_3 0x0000191c
2809#define BNX_RPM_RC_CNTL_4 0x00001920
2810#define BNX_RPM_RC_CNTL_4_A (0x3ffffL<<0)
2811#define BNX_RPM_RC_CNTL_4_B (0xfffL<<19)
2812
2813#define BNX_RPM_RC_VALUE_MASK_4 0x00001924
2814#define BNX_RPM_RC_CNTL_5 0x00001928
2815#define BNX_RPM_RC_CNTL_5_A (0x3ffffL<<0)
2816#define BNX_RPM_RC_CNTL_5_B (0xfffL<<19)
2817
2818#define BNX_RPM_RC_VALUE_MASK_5 0x0000192c
2819#define BNX_RPM_RC_CNTL_6 0x00001930
2820#define BNX_RPM_RC_CNTL_6_A (0x3ffffL<<0)
2821#define BNX_RPM_RC_CNTL_6_B (0xfffL<<19)
2822
2823#define BNX_RPM_RC_VALUE_MASK_6 0x00001934
2824#define BNX_RPM_RC_CNTL_7 0x00001938
2825#define BNX_RPM_RC_CNTL_7_A (0x3ffffL<<0)
2826#define BNX_RPM_RC_CNTL_7_B (0xfffL<<19)
2827
2828#define BNX_RPM_RC_VALUE_MASK_7 0x0000193c
2829#define BNX_RPM_RC_CNTL_8 0x00001940
2830#define BNX_RPM_RC_CNTL_8_A (0x3ffffL<<0)
2831#define BNX_RPM_RC_CNTL_8_B (0xfffL<<19)
2832
2833#define BNX_RPM_RC_VALUE_MASK_8 0x00001944
2834#define BNX_RPM_RC_CNTL_9 0x00001948
2835#define BNX_RPM_RC_CNTL_9_A (0x3ffffL<<0)
2836#define BNX_RPM_RC_CNTL_9_B (0xfffL<<19)
2837
2838#define BNX_RPM_RC_VALUE_MASK_9 0x0000194c
2839#define BNX_RPM_RC_CNTL_10 0x00001950
2840#define BNX_RPM_RC_CNTL_10_A (0x3ffffL<<0)
2841#define BNX_RPM_RC_CNTL_10_B (0xfffL<<19)
2842
2843#define BNX_RPM_RC_VALUE_MASK_10 0x00001954
2844#define BNX_RPM_RC_CNTL_11 0x00001958
2845#define BNX_RPM_RC_CNTL_11_A (0x3ffffL<<0)
2846#define BNX_RPM_RC_CNTL_11_B (0xfffL<<19)
2847
2848#define BNX_RPM_RC_VALUE_MASK_11 0x0000195c
2849#define BNX_RPM_RC_CNTL_12 0x00001960
2850#define BNX_RPM_RC_CNTL_12_A (0x3ffffL<<0)
2851#define BNX_RPM_RC_CNTL_12_B (0xfffL<<19)
2852
2853#define BNX_RPM_RC_VALUE_MASK_12 0x00001964
2854#define BNX_RPM_RC_CNTL_13 0x00001968
2855#define BNX_RPM_RC_CNTL_13_A (0x3ffffL<<0)
2856#define BNX_RPM_RC_CNTL_13_B (0xfffL<<19)
2857
2858#define BNX_RPM_RC_VALUE_MASK_13 0x0000196c
2859#define BNX_RPM_RC_CNTL_14 0x00001970
2860#define BNX_RPM_RC_CNTL_14_A (0x3ffffL<<0)
2861#define BNX_RPM_RC_CNTL_14_B (0xfffL<<19)
2862
2863#define BNX_RPM_RC_VALUE_MASK_14 0x00001974
2864#define BNX_RPM_RC_CNTL_15 0x00001978
2865#define BNX_RPM_RC_CNTL_15_A (0x3ffffL<<0)
2866#define BNX_RPM_RC_CNTL_15_B (0xfffL<<19)
2867
2868#define BNX_RPM_RC_VALUE_MASK_15 0x0000197c
2869#define BNX_RPM_RC_CONFIG 0x00001980
2870#define BNX_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0)
2871#define BNX_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24)
2872
2873#define BNX_RPM_DEBUG0 0x00001984
2874#define BNX_RPM_DEBUG0_FM_BCNT (0xffffL<<0)
2875#define BNX_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16)
2876#define BNX_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17)
2877#define BNX_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18)
2878#define BNX_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19)
2879#define BNX_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20)
2880#define BNX_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21)
2881#define BNX_RPM_DEBUG0_LLC_SNAP (1L<<22)
2882#define BNX_RPM_DEBUG0_FM_STARTED (1L<<23)
2883#define BNX_RPM_DEBUG0_DONE (1L<<24)
2884#define BNX_RPM_DEBUG0_WAIT_4_DONE (1L<<25)
2885#define BNX_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26)
2886#define BNX_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27)
2887#define BNX_RPM_DEBUG0_IGNORE_VLAN (1L<<28)
2888#define BNX_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31)
2889
2890#define BNX_RPM_DEBUG1 0x00001988
2891#define BNX_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0)
2892#define BNX_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
2893#define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
2894#define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
2895#define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
2896#define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
2897#define BNX_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
2898#define BNX_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
2899#define BNX_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
2900#define BNX_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
2901#define BNX_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
2902#define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
2903#define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
2904#define BNX_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
2905#define BNX_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0)
2906#define BNX_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0)
2907#define BNX_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0)
2908#define BNX_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16)
2909#define BNX_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28)
2910#define BNX_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29)
2911#define BNX_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30)
2912#define BNX_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31)
2913
2914#define BNX_RPM_DEBUG2 0x0000198c
2915#define BNX_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0)
2916#define BNX_RPM_DEBUG2_IP_BCNT (0xffL<<16)
2917#define BNX_RPM_DEBUG2_THIS_CMD_M4 (1L<<24)
2918#define BNX_RPM_DEBUG2_THIS_CMD_M3 (1L<<25)
2919#define BNX_RPM_DEBUG2_THIS_CMD_M2 (1L<<26)
2920#define BNX_RPM_DEBUG2_THIS_CMD_M1 (1L<<27)
2921#define BNX_RPM_DEBUG2_IPIPE_EMPTY (1L<<28)
2922#define BNX_RPM_DEBUG2_FM_DISCARD (1L<<29)
2923#define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30)
2924#define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31)
2925
2926#define BNX_RPM_DEBUG3 0x00001990
2927#define BNX_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0)
2928#define BNX_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9)
2929#define BNX_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10)
2930#define BNX_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11)
2931#define BNX_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12)
2932#define BNX_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13)
2933#define BNX_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14)
2934#define BNX_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15)
2935#define BNX_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16)
2936#define BNX_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21)
2937#define BNX_RPM_DEBUG3_DROP_NXT_VLD (1L<<22)
2938#define BNX_RPM_DEBUG3_DROP_NXT (1L<<23)
2939#define BNX_RPM_DEBUG3_FTQ_FSM (0x3L<<24)
2940#define BNX_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24)
2941#define BNX_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24)
2942#define BNX_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24)
2943#define BNX_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26)
2944#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26)
2945#define BNX_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26)
2946#define BNX_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26)
2947#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26)
2948#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26)
2949#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26)
2950#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26)
2951#define BNX_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26)
2952#define BNX_RPM_DEBUG3_MBFREE_FSM (1L<<29)
2953#define BNX_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
2954#define BNX_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29)
2955#define BNX_RPM_DEBUG3_MBALLOC_FSM (1L<<30)
2956#define BNX_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30)
2957#define BNX_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30)
2958#define BNX_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31)
2959
2960#define BNX_RPM_DEBUG4 0x00001994
2961#define BNX_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0)
2962#define BNX_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25)
2963#define BNX_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28)
2964#define BNX_RPM_DEBUG4_DFIFO_EMPTY (1L<<31)
2965
2966#define BNX_RPM_DEBUG5 0x00001998
2967#define BNX_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0)
2968#define BNX_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5)
2969#define BNX_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10)
2970#define BNX_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15)
2971#define BNX_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20)
2972#define BNX_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21)
2973#define BNX_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22)
2974#define BNX_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23)
2975#define BNX_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24)
2976#define BNX_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25)
2977#define BNX_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26)
2978#define BNX_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27)
2979#define BNX_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28)
2980#define BNX_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29)
2981#define BNX_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30)
2982#define BNX_RPM_DEBUG5_HOLDREG_RD (1L<<31)
2983
2984#define BNX_RPM_DEBUG6 0x0000199c
2985#define BNX_RPM_DEBUG6_ACPI_VEC (0xffffL<<0)
2986#define BNX_RPM_DEBUG6_VEC (0xffffL<<16)
2987
2988#define BNX_RPM_DEBUG7 0x000019a0
2989#define BNX_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0)
2990
2991#define BNX_RPM_DEBUG8 0x000019a4
2992#define BNX_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0)
2993#define BNX_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
2994#define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
2995#define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
2996#define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
2997#define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
2998#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
2999#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
3000#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
3001#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
3002#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
3003#define BNX_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
3004#define BNX_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4)
3005#define BNX_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5)
3006#define BNX_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6)
3007#define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7)
3008#define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8)
3009#define BNX_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9)
3010#define BNX_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10)
3011#define BNX_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11)
3012#define BNX_RPM_DEBUG8_EOF_DET (1L<<12)
3013#define BNX_RPM_DEBUG8_SOF_DET (1L<<13)
3014#define BNX_RPM_DEBUG8_WAIT_4_SOF (1L<<14)
3015#define BNX_RPM_DEBUG8_ALL_DONE (1L<<15)
3016#define BNX_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16)
3017#define BNX_RPM_DEBUG8_BYTE_CTR (0xffL<<24)
3018
3019#define BNX_RPM_DEBUG9 0x000019a8
3020#define BNX_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0)
3021#define BNX_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3)
3022#define BNX_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4)
3023#define BNX_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28)
3024#define BNX_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
3025#define BNX_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
3026#define BNX_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
3027
3028#define BNX_RPM_ACPI_DBG_BUF_W00 0x000019c0
3029#define BNX_RPM_ACPI_DBG_BUF_W01 0x000019c4
3030#define BNX_RPM_ACPI_DBG_BUF_W02 0x000019c8
3031#define BNX_RPM_ACPI_DBG_BUF_W03 0x000019cc
3032#define BNX_RPM_ACPI_DBG_BUF_W10 0x000019d0
3033#define BNX_RPM_ACPI_DBG_BUF_W11 0x000019d4
3034#define BNX_RPM_ACPI_DBG_BUF_W12 0x000019d8
3035#define BNX_RPM_ACPI_DBG_BUF_W13 0x000019dc
3036#define BNX_RPM_ACPI_DBG_BUF_W20 0x000019e0
3037#define BNX_RPM_ACPI_DBG_BUF_W21 0x000019e4
3038#define BNX_RPM_ACPI_DBG_BUF_W22 0x000019e8
3039#define BNX_RPM_ACPI_DBG_BUF_W23 0x000019ec
3040#define BNX_RPM_ACPI_DBG_BUF_W30 0x000019f0
3041#define BNX_RPM_ACPI_DBG_BUF_W31 0x000019f4
3042#define BNX_RPM_ACPI_DBG_BUF_W32 0x000019f8
3043#define BNX_RPM_ACPI_DBG_BUF_W33 0x000019fc
3044
3045
3046/*
3047 * rbuf_reg definition
3048 * offset: 0x200000
3049 */
3050#define BNX_RBUF_COMMAND 0x00200000
3051#define BNX_RBUF_COMMAND_ENABLED (1L<<0)
3052#define BNX_RBUF_COMMAND_FREE_INIT (1L<<1)
3053#define BNX_RBUF_COMMAND_RAM_INIT (1L<<2)
3054#define BNX_RBUF_COMMAND_OVER_FREE (1L<<4)
3055#define BNX_RBUF_COMMAND_ALLOC_REQ (1L<<5)
3056
3057#define BNX_RBUF_STATUS1 0x00200004
3058#define BNX_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0)
3059
3060#define BNX_RBUF_STATUS2 0x00200008
3061#define BNX_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0)
3062#define BNX_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16)
3063
3064#define BNX_RBUF_CONFIG 0x0020000c
3065#define BNX_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
3066#define BNX_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
3067
3068#define BNX_RBUF_FW_BUF_ALLOC 0x00200010
3069#define BNX_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
3070
3071#define BNX_RBUF_FW_BUF_FREE 0x00200014
3072#define BNX_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0)
3073#define BNX_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7)
3074#define BNX_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16)
3075
3076#define BNX_RBUF_FW_BUF_SEL 0x00200018
3077#define BNX_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0)
3078#define BNX_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7)
3079#define BNX_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16)
3080
3081#define BNX_RBUF_CONFIG2 0x0020001c
3082#define BNX_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
3083#define BNX_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
3084
3085#define BNX_RBUF_CONFIG3 0x00200020
3086#define BNX_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
3087#define BNX_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
3088
3089#define BNX_RBUF_PKT_DATA 0x00208000
3090#define BNX_RBUF_CLIST_DATA 0x00210000
3091#define BNX_RBUF_BUF_DATA 0x00220000
3092
3093
3094/*
3095 * rv2p_reg definition
3096 * offset: 0x2800
3097 */
3098#define BNX_RV2P_COMMAND 0x00002800
3099#define BNX_RV2P_COMMAND_ENABLED (1L<<0)
3100#define BNX_RV2P_COMMAND_PROC1_INTRPT (1L<<1)
3101#define BNX_RV2P_COMMAND_PROC2_INTRPT (1L<<2)
3102#define BNX_RV2P_COMMAND_ABORT0 (1L<<4)
3103#define BNX_RV2P_COMMAND_ABORT1 (1L<<5)
3104#define BNX_RV2P_COMMAND_ABORT2 (1L<<6)
3105#define BNX_RV2P_COMMAND_ABORT3 (1L<<7)
3106#define BNX_RV2P_COMMAND_ABORT4 (1L<<8)
3107#define BNX_RV2P_COMMAND_ABORT5 (1L<<9)
3108#define BNX_RV2P_COMMAND_PROC1_RESET (1L<<16)
3109#define BNX_RV2P_COMMAND_PROC2_RESET (1L<<17)
3110#define BNX_RV2P_COMMAND_CTXIF_RESET (1L<<18)
3111
3112#define BNX_RV2P_STATUS 0x00002804
3113#define BNX_RV2P_STATUS_ALWAYS_0 (1L<<0)
3114#define BNX_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8)
3115#define BNX_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9)
3116#define BNX_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10)
3117#define BNX_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11)
3118#define BNX_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12)
3119#define BNX_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13)
3120
3121#define BNX_RV2P_CONFIG 0x00002808
3122#define BNX_RV2P_CONFIG_STALL_PROC1 (1L<<0)
3123#define BNX_RV2P_CONFIG_STALL_PROC2 (1L<<1)
3124#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8)
3125#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9)
3126#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10)
3127#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11)
3128#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12)
3129#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13)
3130#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16)
3131#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17)
3132#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18)
3133#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19)
3134#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20)
3135#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21)
3136#define BNX_RV2P_CONFIG_PAGE_SIZE (0xfL<<24)
3137#define BNX_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
3138#define BNX_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24)
3139#define BNX_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24)
3140#define BNX_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24)
3141#define BNX_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24)
3142#define BNX_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24)
3143#define BNX_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24)
3144#define BNX_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24)
3145#define BNX_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24)
3146#define BNX_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24)
3147#define BNX_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24)
3148#define BNX_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24)
3149#define BNX_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24)
3150
3151#define BNX_RV2P_GEN_BFR_ADDR_0 0x00002810
3152#define BNX_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16)
3153
3154#define BNX_RV2P_GEN_BFR_ADDR_1 0x00002814
3155#define BNX_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16)
3156
3157#define BNX_RV2P_GEN_BFR_ADDR_2 0x00002818
3158#define BNX_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16)
3159
3160#define BNX_RV2P_GEN_BFR_ADDR_3 0x0000281c
3161#define BNX_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16)
3162
3163#define BNX_RV2P_INSTR_HIGH 0x00002830
3164#define BNX_RV2P_INSTR_HIGH_HIGH (0x1fL<<0)
3165
3166#define BNX_RV2P_INSTR_LOW 0x00002834
3167#define BNX_RV2P_PROC1_ADDR_CMD 0x00002838
3168#define BNX_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0)
3169#define BNX_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
3170
3171#define BNX_RV2P_PROC2_ADDR_CMD 0x0000283c
3172#define BNX_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0)
3173#define BNX_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31)
3174
3175#define BNX_RV2P_PROC1_GRC_DEBUG 0x00002840
3176#define BNX_RV2P_PROC2_GRC_DEBUG 0x00002844
3177#define BNX_RV2P_GRC_PROC_DEBUG 0x00002848
3178#define BNX_RV2P_DEBUG_VECT_PEEK 0x0000284c
3179#define BNX_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3180#define BNX_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3181#define BNX_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3182#define BNX_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3183#define BNX_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3184#define BNX_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3185
3186#define BNX_RV2P_PFTQ_DATA 0x00002b40
3187#define BNX_RV2P_PFTQ_CMD 0x00002b78
3188#define BNX_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0)
3189#define BNX_RV2P_PFTQ_CMD_WR_TOP (1L<<10)
3190#define BNX_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
3191#define BNX_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10)
3192#define BNX_RV2P_PFTQ_CMD_SFT_RESET (1L<<25)
3193#define BNX_RV2P_PFTQ_CMD_RD_DATA (1L<<26)
3194#define BNX_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27)
3195#define BNX_RV2P_PFTQ_CMD_ADD_DATA (1L<<28)
3196#define BNX_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29)
3197#define BNX_RV2P_PFTQ_CMD_POP (1L<<30)
3198#define BNX_RV2P_PFTQ_CMD_BUSY (1L<<31)
3199
3200#define BNX_RV2P_PFTQ_CTL 0x00002b7c
3201#define BNX_RV2P_PFTQ_CTL_INTERVENE (1L<<0)
3202#define BNX_RV2P_PFTQ_CTL_OVERFLOW (1L<<1)
3203#define BNX_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2)
3204#define BNX_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3205#define BNX_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3206
3207#define BNX_RV2P_TFTQ_DATA 0x00002b80
3208#define BNX_RV2P_TFTQ_CMD 0x00002bb8
3209#define BNX_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0)
3210#define BNX_RV2P_TFTQ_CMD_WR_TOP (1L<<10)
3211#define BNX_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
3212#define BNX_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10)
3213#define BNX_RV2P_TFTQ_CMD_SFT_RESET (1L<<25)
3214#define BNX_RV2P_TFTQ_CMD_RD_DATA (1L<<26)
3215#define BNX_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27)
3216#define BNX_RV2P_TFTQ_CMD_ADD_DATA (1L<<28)
3217#define BNX_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29)
3218#define BNX_RV2P_TFTQ_CMD_POP (1L<<30)
3219#define BNX_RV2P_TFTQ_CMD_BUSY (1L<<31)
3220
3221#define BNX_RV2P_TFTQ_CTL 0x00002bbc
3222#define BNX_RV2P_TFTQ_CTL_INTERVENE (1L<<0)
3223#define BNX_RV2P_TFTQ_CTL_OVERFLOW (1L<<1)
3224#define BNX_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2)
3225#define BNX_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3226#define BNX_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3227
3228#define BNX_RV2P_MFTQ_DATA 0x00002bc0
3229#define BNX_RV2P_MFTQ_CMD 0x00002bf8
3230#define BNX_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0)
3231#define BNX_RV2P_MFTQ_CMD_WR_TOP (1L<<10)
3232#define BNX_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
3233#define BNX_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10)
3234#define BNX_RV2P_MFTQ_CMD_SFT_RESET (1L<<25)
3235#define BNX_RV2P_MFTQ_CMD_RD_DATA (1L<<26)
3236#define BNX_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27)
3237#define BNX_RV2P_MFTQ_CMD_ADD_DATA (1L<<28)
3238#define BNX_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29)
3239#define BNX_RV2P_MFTQ_CMD_POP (1L<<30)
3240#define BNX_RV2P_MFTQ_CMD_BUSY (1L<<31)
3241
3242#define BNX_RV2P_MFTQ_CTL 0x00002bfc
3243#define BNX_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
3244#define BNX_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
3245#define BNX_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
3246#define BNX_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3247#define BNX_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3248
3249
3250
3251/*
3252 * mq_reg definition
3253 * offset: 0x3c00
3254 */
3255#define BNX_MQ_COMMAND 0x00003c00
3256#define BNX_MQ_COMMAND_ENABLED (1L<<0)
3257#define BNX_MQ_COMMAND_OVERFLOW (1L<<4)
3258#define BNX_MQ_COMMAND_WR_ERROR (1L<<5)
3259#define BNX_MQ_COMMAND_RD_ERROR (1L<<6)
3260
3261#define BNX_MQ_STATUS 0x00003c04
3262#define BNX_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
3263#define BNX_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
3264#define BNX_MQ_STATUS_PCI_STALL_STAT (1L<<18)
3265
3266#define BNX_MQ_CONFIG 0x00003c08
3267#define BNX_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
3268#define BNX_MQ_CONFIG_HALT_DIS (1L<<1)
3269#define BNX_MQ_CONFIG_BIN_MQ_MODE (1L<<2)
3270#define BNX_MQ_CONFIG_DIS_IDB_DROP (1L<<3)
3271#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
3272#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
3273#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
3274#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
3275#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
3276#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
3277#define BNX_MQ_CONFIG_MAX_DEPTH (0x7fL<<8)
3278#define BNX_MQ_CONFIG_CUR_DEPTH (0x7fL<<20)
3279
3280
3281#define BNX_MQ_ENQUEUE1 0x00003c0c
3282#define BNX_MQ_ENQUEUE1_OFFSET (0x3fL<<2)
3283#define BNX_MQ_ENQUEUE1_CID (0x3fffL<<8)
3284#define BNX_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24)
3285#define BNX_MQ_ENQUEUE1_KNL_MODE (1L<<28)
3286
3287#define BNX_MQ_ENQUEUE2 0x00003c10
3288#define BNX_MQ_BAD_WR_ADDR 0x00003c14
3289#define BNX_MQ_BAD_RD_ADDR 0x00003c18
3290#define BNX_MQ_KNL_BYP_WIND_START 0x00003c1c
3291#define BNX_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12)
3292
3293#define BNX_MQ_KNL_WIND_END 0x00003c20
3294#define BNX_MQ_KNL_WIND_END_VALUE (0xffffffL<<8)
3295
3296#define BNX_MQ_KNL_WRITE_MASK1 0x00003c24
3297#define BNX_MQ_KNL_TX_MASK1 0x00003c28
3298#define BNX_MQ_KNL_CMD_MASK1 0x00003c2c
3299#define BNX_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30
3300#define BNX_MQ_KNL_RX_V2P_MASK1 0x00003c34
3301#define BNX_MQ_KNL_WRITE_MASK2 0x00003c38
3302#define BNX_MQ_KNL_TX_MASK2 0x00003c3c
3303#define BNX_MQ_KNL_CMD_MASK2 0x00003c40
3304#define BNX_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44
3305#define BNX_MQ_KNL_RX_V2P_MASK2 0x00003c48
3306#define BNX_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c
3307#define BNX_MQ_KNL_BYP_TX_MASK1 0x00003c50
3308#define BNX_MQ_KNL_BYP_CMD_MASK1 0x00003c54
3309#define BNX_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58
3310#define BNX_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c
3311#define BNX_MQ_KNL_BYP_WRITE_MASK2 0x00003c60
3312#define BNX_MQ_KNL_BYP_TX_MASK2 0x00003c64
3313#define BNX_MQ_KNL_BYP_CMD_MASK2 0x00003c68
3314#define BNX_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c
3315#define BNX_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70
3316#define BNX_MQ_MEM_WR_ADDR 0x00003c74
3317#define BNX_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0)
3318
3319#define BNX_MQ_MEM_WR_DATA0 0x00003c78
3320#define BNX_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0)
3321
3322#define BNX_MQ_MEM_WR_DATA1 0x00003c7c
3323#define BNX_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0)
3324
3325#define BNX_MQ_MEM_WR_DATA2 0x00003c80
3326#define BNX_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
3327
3328#define BNX_MQ_MEM_RD_ADDR 0x00003c84
3329#define BNX_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
3330
3331#define BNX_MQ_MEM_RD_DATA0 0x00003c88
3332#define BNX_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0)
3333
3334#define BNX_MQ_MEM_RD_DATA1 0x00003c8c
3335#define BNX_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
3336
3337#define BNX_MQ_MEM_RD_DATA2 0x00003c90
3338#define BNX_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
3339
3340#define BNX_MQ_MAP_L2_5 0x00003d34
3341#define BNX_MQ_MAP_L2_5_MQ_OFFSET (0xffL<<0)
3342#define BNX_MQ_MAP_L2_5_SZ (0x3L<<8)
3343#define BNX_MQ_MAP_L2_5_CTX_OFFSET (0x2ffL<<10)
3344#define BNX_MQ_MAP_L2_5_BIN_OFFSET (0x7L<<23)
3345#define BNX_MQ_MAP_L2_5_ARM (0x3L<<26)
3346#define BNX_MQ_MAP_L2_5_ENA (0x1L<<31)
3347#define BNX_MQ_MAP_L2_5_DEFAULT 0x83000b08
3348
3349/*
3350 * tbdr_reg definition
3351 * offset: 0x5000
3352 */
3353#define BNX_TBDR_COMMAND 0x00005000
3354#define BNX_TBDR_COMMAND_ENABLE (1L<<0)
3355#define BNX_TBDR_COMMAND_SOFT_RST (1L<<1)
3356#define BNX_TBDR_COMMAND_MSTR_ABORT (1L<<4)
3357
3358#define BNX_TBDR_STATUS 0x00005004
3359#define BNX_TBDR_STATUS_DMA_WAIT (1L<<0)
3360#define BNX_TBDR_STATUS_FTQ_WAIT (1L<<1)
3361#define BNX_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
3362#define BNX_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
3363#define BNX_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
3364#define BNX_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
3365#define BNX_TBDR_STATUS_BURST_CNT (1L<<6)
3366
3367#define BNX_TBDR_CONFIG 0x00005008
3368#define BNX_TBDR_CONFIG_MAX_BDS (0xffL<<0)
3369#define BNX_TBDR_CONFIG_SWAP_MODE (1L<<8)
3370#define BNX_TBDR_CONFIG_PRIORITY (1L<<9)
3371#define BNX_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
3372#define BNX_TBDR_CONFIG_PAGE_SIZE (0xfL<<24)
3373#define BNX_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
3374#define BNX_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
3375#define BNX_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
3376#define BNX_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
3377#define BNX_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
3378#define BNX_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
3379#define BNX_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
3380#define BNX_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
3381#define BNX_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
3382#define BNX_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
3383#define BNX_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
3384#define BNX_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
3385#define BNX_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
3386
3387#define BNX_TBDR_DEBUG_VECT_PEEK 0x0000500c
3388#define BNX_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3389#define BNX_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3390#define BNX_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3391#define BNX_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3392#define BNX_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3393#define BNX_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3394
3395#define BNX_TBDR_FTQ_DATA 0x000053c0
3396#define BNX_TBDR_FTQ_CMD 0x000053f8
3397#define BNX_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
3398#define BNX_TBDR_FTQ_CMD_WR_TOP (1L<<10)
3399#define BNX_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
3400#define BNX_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
3401#define BNX_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
3402#define BNX_TBDR_FTQ_CMD_RD_DATA (1L<<26)
3403#define BNX_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
3404#define BNX_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
3405#define BNX_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
3406#define BNX_TBDR_FTQ_CMD_POP (1L<<30)
3407#define BNX_TBDR_FTQ_CMD_BUSY (1L<<31)
3408
3409#define BNX_TBDR_FTQ_CTL 0x000053fc
3410#define BNX_TBDR_FTQ_CTL_INTERVENE (1L<<0)
3411#define BNX_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
3412#define BNX_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3413#define BNX_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3414#define BNX_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3415
3416
3417
3418/*
3419 * tdma_reg definition
3420 * offset: 0x5c00
3421 */
3422#define BNX_TDMA_COMMAND 0x00005c00
3423#define BNX_TDMA_COMMAND_ENABLED (1L<<0)
3424#define BNX_TDMA_COMMAND_MASTER_ABORT (1L<<4)
3425#define BNX_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
3426
3427#define BNX_TDMA_STATUS 0x00005c04
3428#define BNX_TDMA_STATUS_DMA_WAIT (1L<<0)
3429#define BNX_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
3430#define BNX_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
3431#define BNX_TDMA_STATUS_LOCK_WAIT (1L<<3)
3432#define BNX_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
3433#define BNX_TDMA_STATUS_BURST_CNT (1L<<17)
3434
3435#define BNX_TDMA_CONFIG 0x00005c08
3436#define BNX_TDMA_CONFIG_ONE_DMA (1L<<0)
3437#define BNX_TDMA_CONFIG_ONE_RECORD (1L<<1)
3438#define BNX_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)
3439#define BNX_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
3440#define BNX_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4)
3441#define BNX_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4)
3442#define BNX_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4)
3443#define BNX_TDMA_CONFIG_LINE_SZ (0xfL<<8)
3444#define BNX_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
3445#define BNX_TDMA_CONFIG_LINE_SZ_128 (4L<<8)
3446#define BNX_TDMA_CONFIG_LINE_SZ_256 (6L<<8)
3447#define BNX_TDMA_CONFIG_LINE_SZ_512 (8L<<8)
3448#define BNX_TDMA_CONFIG_ALIGN_ENA (1L<<15)
3449#define BNX_TDMA_CONFIG_CHK_L2_BD (1L<<16)
3450#define BNX_TDMA_CONFIG_FIFO_CMP (0xfL<<20)
3451
3452#define BNX_TDMA_PAYLOAD_PROD 0x00005c0c
3453#define BNX_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3)
3454
3455#define BNX_TDMA_DBG_WATCHDOG 0x00005c10
3456#define BNX_TDMA_DBG_TRIGGER 0x00005c14
3457#define BNX_TDMA_DMAD_FSM 0x00005c80
3458#define BNX_TDMA_DMAD_FSM_BD_INVLD (1L<<0)
3459#define BNX_TDMA_DMAD_FSM_PUSH (0xfL<<4)
3460#define BNX_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8)
3461#define BNX_TDMA_DMAD_FSM_ARB_CTX (1L<<12)
3462#define BNX_TDMA_DMAD_FSM_DR_INTF (1L<<16)
3463#define BNX_TDMA_DMAD_FSM_DMAD (0x7L<<20)
3464#define BNX_TDMA_DMAD_FSM_BD (0xfL<<24)
3465
3466#define BNX_TDMA_DMAD_STATUS 0x00005c84
3467#define BNX_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0)
3468#define BNX_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4)
3469#define BNX_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8)
3470#define BNX_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12)
3471
3472#define BNX_TDMA_DR_INTF_FSM 0x00005c88
3473#define BNX_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0)
3474#define BNX_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4)
3475#define BNX_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8)
3476#define BNX_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12)
3477#define BNX_TDMA_DR_INTF_FSM_DMAD (0x7L<<16)
3478
3479#define BNX_TDMA_DR_INTF_STATUS 0x00005c8c
3480#define BNX_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0)
3481#define BNX_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4)
3482#define BNX_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8)
3483#define BNX_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12)
3484#define BNX_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16)
3485
3486#define BNX_TDMA_FTQ_DATA 0x00005fc0
3487#define BNX_TDMA_FTQ_CMD 0x00005ff8
3488#define BNX_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0)
3489#define BNX_TDMA_FTQ_CMD_WR_TOP (1L<<10)
3490#define BNX_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
3491#define BNX_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10)
3492#define BNX_TDMA_FTQ_CMD_SFT_RESET (1L<<25)
3493#define BNX_TDMA_FTQ_CMD_RD_DATA (1L<<26)
3494#define BNX_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27)
3495#define BNX_TDMA_FTQ_CMD_ADD_DATA (1L<<28)
3496#define BNX_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29)
3497#define BNX_TDMA_FTQ_CMD_POP (1L<<30)
3498#define BNX_TDMA_FTQ_CMD_BUSY (1L<<31)
3499
3500#define BNX_TDMA_FTQ_CTL 0x00005ffc
3501#define BNX_TDMA_FTQ_CTL_INTERVENE (1L<<0)
3502#define BNX_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
3503#define BNX_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3504#define BNX_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3505#define BNX_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3506
3507
3508
3509/*
3510 * hc_reg definition
3511 * offset: 0x6800
3512 */
3513#define BNX_HC_COMMAND 0x00006800
3514#define BNX_HC_COMMAND_ENABLE (1L<<0)
3515#define BNX_HC_COMMAND_SKIP_ABORT (1L<<4)
3516#define BNX_HC_COMMAND_COAL_NOW (1L<<16)
3517#define BNX_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
3518#define BNX_HC_COMMAND_STATS_NOW (1L<<18)
3519#define BNX_HC_COMMAND_FORCE_INT (0x3L<<19)
3520#define BNX_HC_COMMAND_FORCE_INT_NULL (0L<<19)
3521#define BNX_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
3522#define BNX_HC_COMMAND_FORCE_INT_LOW (2L<<19)
3523#define BNX_HC_COMMAND_FORCE_INT_FREE (3L<<19)
3524#define BNX_HC_COMMAND_CLR_STAT_NOW (1L<<21)
3525
3526#define BNX_HC_STATUS 0x00006804
3527#define BNX_HC_STATUS_MASTER_ABORT (1L<<0)
3528#define BNX_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
3529#define BNX_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
3530#define BNX_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
3531#define BNX_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
3532#define BNX_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)
3533#define BNX_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20)
3534#define BNX_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23)
3535#define BNX_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24)
3536#define BNX_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25)
3537
3538#define BNX_HC_CONFIG 0x00006808
3539#define BNX_HC_CONFIG_COLLECT_STATS (1L<<0)
3540#define BNX_HC_CONFIG_RX_TMR_MODE (1L<<1)
3541#define BNX_HC_CONFIG_TX_TMR_MODE (1L<<2)
3542#define BNX_HC_CONFIG_COM_TMR_MODE (1L<<3)
3543#define BNX_HC_CONFIG_CMD_TMR_MODE (1L<<4)
3544#define BNX_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
3545#define BNX_HC_CONFIG_STATUS_PRIORITY (1L<<6)
3546#define BNX_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
3547
3548#define BNX_HC_ATTN_BITS_ENABLE 0x0000680c
3549#define BNX_HC_STATUS_ADDR_L 0x00006810
3550#define BNX_HC_STATUS_ADDR_H 0x00006814
3551#define BNX_HC_STATISTICS_ADDR_L 0x00006818
3552#define BNX_HC_STATISTICS_ADDR_H 0x0000681c
3553#define BNX_HC_TX_QUICK_CONS_TRIP 0x00006820
3554#define BNX_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
3555#define BNX_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16)
3556
3557#define BNX_HC_COMP_PROD_TRIP 0x00006824
3558#define BNX_HC_COMP_PROD_TRIP_VALUE (0xffL<<0)
3559#define BNX_HC_COMP_PROD_TRIP_INT (0xffL<<16)
3560
3561#define BNX_HC_RX_QUICK_CONS_TRIP 0x00006828
3562#define BNX_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
3563#define BNX_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16)
3564
3565#define BNX_HC_RX_TICKS 0x0000682c
3566#define BNX_HC_RX_TICKS_VALUE (0x3ffL<<0)
3567#define BNX_HC_RX_TICKS_INT (0x3ffL<<16)
3568
3569#define BNX_HC_TX_TICKS 0x00006830
3570#define BNX_HC_TX_TICKS_VALUE (0x3ffL<<0)
3571#define BNX_HC_TX_TICKS_INT (0x3ffL<<16)
3572
3573#define BNX_HC_COM_TICKS 0x00006834
3574#define BNX_HC_COM_TICKS_VALUE (0x3ffL<<0)
3575#define BNX_HC_COM_TICKS_INT (0x3ffL<<16)
3576
3577#define BNX_HC_CMD_TICKS 0x00006838
3578#define BNX_HC_CMD_TICKS_VALUE (0x3ffL<<0)
3579#define BNX_HC_CMD_TICKS_INT (0x3ffL<<16)
3580
3581#define BNX_HC_PERIODIC_TICKS 0x0000683c
3582#define BNX_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
3583
3584#define BNX_HC_STAT_COLLECT_TICKS 0x00006840
3585#define BNX_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
3586
3587#define BNX_HC_STATS_TICKS 0x00006844
3588#define BNX_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
3589
3590#define BNX_HC_STAT_MEM_DATA 0x0000684c
3591#define BNX_HC_STAT_GEN_SEL_0 0x00006850
3592#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
3593#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
3594#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
3595#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
3596#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
3597#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)
3598#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0)
3599#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0)
3600#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0)
3601#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0)
3602#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0)
3603#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0)
3604#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0)
3605#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0)
3606#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0)
3607#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0)
3608#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0)
3609#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0)
3610#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0)
3611#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0)
3612#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0)
3613#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0)
3614#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0)
3615#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0)
3616#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0)
3617#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0)
3618#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0)
3619#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0)
3620#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0)
3621#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0)
3622#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0)
3623#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0)
3624#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0)
3625#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0)
3626#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0)
3627#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0)
3628#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0)
3629#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0)
3630#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0)
3631#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0)
3632#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0)
3633#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0)
3634#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0)
3635#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0)
3636#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0)
3637#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0)
3638#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0)
3639#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0)
3640#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0)
3641#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0)
3642#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0)
3643#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0)
3644#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0)
3645#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0)
3646#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0)
3647#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0)
3648#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0)
3649#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0)
3650#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0)
3651#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0)
3652#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0)
3653#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0)
3654#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0)
3655#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0)
3656#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0)
3657#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0)
3658#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0)
3659#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0)
3660#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
3661#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
3662#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
3663#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0)
3664#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0)
3665#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0)
3666#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0)
3667#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0)
3668#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0)
3669#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0)
3670#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0)
3671#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0)
3672#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0)
3673#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0)
3674#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0)
3675#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0)
3676#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0)
3677#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0)
3678#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0)
3679#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0)
3680#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0)
3681#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0)
3682#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0)
3683#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0)
3684#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0)
3685#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0)
3686#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0)
3687#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0)
3688#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0)
3689#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0)
3690#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0)
3691#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0)
3692#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0)
3693#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0)
3694#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0)
3695#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0)
3696#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0)
3697#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0)
3698#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0)
3699#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0)
3700#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0)
3701#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0)
3702#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0)
3703#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0)
3704#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0)
3705#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0)
3706#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0)
3707#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0)
3708#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0)
3709#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0)
3710#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
3711#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
3712#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
3713#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
3714#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
3715#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
3716#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
3717#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
3718
3719#define BNX_HC_STAT_GEN_SEL_1 0x00006854
3720#define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
3721#define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
3722#define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
3723#define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
3724
3725#define BNX_HC_STAT_GEN_SEL_2 0x00006858
3726#define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
3727#define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
3728#define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
3729#define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
3730
3731#define BNX_HC_STAT_GEN_SEL_3 0x0000685c
3732#define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
3733#define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
3734#define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
3735#define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
3736
3737#define BNX_HC_STAT_GEN_STAT0 0x00006888
3738#define BNX_HC_STAT_GEN_STAT1 0x0000688c
3739#define BNX_HC_STAT_GEN_STAT2 0x00006890
3740#define BNX_HC_STAT_GEN_STAT3 0x00006894
3741#define BNX_HC_STAT_GEN_STAT4 0x00006898
3742#define BNX_HC_STAT_GEN_STAT5 0x0000689c
3743#define BNX_HC_STAT_GEN_STAT6 0x000068a0
3744#define BNX_HC_STAT_GEN_STAT7 0x000068a4
3745#define BNX_HC_STAT_GEN_STAT8 0x000068a8
3746#define BNX_HC_STAT_GEN_STAT9 0x000068ac
3747#define BNX_HC_STAT_GEN_STAT10 0x000068b0
3748#define BNX_HC_STAT_GEN_STAT11 0x000068b4
3749#define BNX_HC_STAT_GEN_STAT12 0x000068b8
3750#define BNX_HC_STAT_GEN_STAT13 0x000068bc
3751#define BNX_HC_STAT_GEN_STAT14 0x000068c0
3752#define BNX_HC_STAT_GEN_STAT15 0x000068c4
3753#define BNX_HC_STAT_GEN_STAT_AC0 0x000068c8
3754#define BNX_HC_STAT_GEN_STAT_AC1 0x000068cc
3755#define BNX_HC_STAT_GEN_STAT_AC2 0x000068d0
3756#define BNX_HC_STAT_GEN_STAT_AC3 0x000068d4
3757#define BNX_HC_STAT_GEN_STAT_AC4 0x000068d8
3758#define BNX_HC_STAT_GEN_STAT_AC5 0x000068dc
3759#define BNX_HC_STAT_GEN_STAT_AC6 0x000068e0
3760#define BNX_HC_STAT_GEN_STAT_AC7 0x000068e4
3761#define BNX_HC_STAT_GEN_STAT_AC8 0x000068e8
3762#define BNX_HC_STAT_GEN_STAT_AC9 0x000068ec
3763#define BNX_HC_STAT_GEN_STAT_AC10 0x000068f0
3764#define BNX_HC_STAT_GEN_STAT_AC11 0x000068f4
3765#define BNX_HC_STAT_GEN_STAT_AC12 0x000068f8
3766#define BNX_HC_STAT_GEN_STAT_AC13 0x000068fc
3767#define BNX_HC_STAT_GEN_STAT_AC14 0x00006900
3768#define BNX_HC_STAT_GEN_STAT_AC15 0x00006904
3769#define BNX_HC_VIS 0x00006908
3770#define BNX_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
3771#define BNX_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
3772#define BNX_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
3773#define BNX_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
3774#define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
3775#define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
3776#define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)
3777#define BNX_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0)
3778#define BNX_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0)
3779#define BNX_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0)
3780#define BNX_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0)
3781#define BNX_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0)
3782#define BNX_HC_VIS_DMA_STAT_STATE (0xfL<<8)
3783#define BNX_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
3784#define BNX_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8)
3785#define BNX_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8)
3786#define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8)
3787#define BNX_HC_VIS_DMA_STAT_STATE_COMP (4L<<8)
3788#define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8)
3789#define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8)
3790#define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8)
3791#define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8)
3792#define BNX_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8)
3793#define BNX_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8)
3794#define BNX_HC_VIS_DMA_MSI_STATE (0x7L<<12)
3795#define BNX_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15)
3796#define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
3797#define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15)
3798#define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15)
3799
3800#define BNX_HC_VIS_1 0x0000690c
3801#define BNX_HC_VIS_1_HW_INTACK_STATE (1L<<4)
3802#define BNX_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
3803#define BNX_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4)
3804#define BNX_HC_VIS_1_SW_INTACK_STATE (1L<<5)
3805#define BNX_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
3806#define BNX_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5)
3807#define BNX_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6)
3808#define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
3809#define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6)
3810#define BNX_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7)
3811#define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
3812#define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7)
3813#define BNX_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17)
3814#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
3815#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17)
3816#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17)
3817#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17)
3818#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17)
3819#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17)
3820#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17)
3821#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17)
3822#define BNX_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21)
3823#define BNX_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
3824#define BNX_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21)
3825#define BNX_HC_VIS_1_INT_GEN_STATE (1L<<23)
3826#define BNX_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
3827#define BNX_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23)
3828#define BNX_HC_VIS_1_STAT_CHAN_ID (0x7L<<24)
3829#define BNX_HC_VIS_1_INT_B (1L<<27)
3830
3831#define BNX_HC_DEBUG_VECT_PEEK 0x00006910
3832#define BNX_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3833#define BNX_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3834#define BNX_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3835#define BNX_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3836#define BNX_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3837#define BNX_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3838
3839
3840
3841/*
3842 * txp_reg definition
3843 * offset: 0x40000
3844 */
3845#define BNX_TXP_CPU_MODE 0x00045000
3846#define BNX_TXP_CPU_MODE_LOCAL_RST (1L<<0)
3847#define BNX_TXP_CPU_MODE_STEP_ENA (1L<<1)
3848#define BNX_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3849#define BNX_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3850#define BNX_TXP_CPU_MODE_MSG_BIT1 (1L<<6)
3851#define BNX_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3852#define BNX_TXP_CPU_MODE_SOFT_HALT (1L<<10)
3853#define BNX_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3854#define BNX_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3855#define BNX_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3856#define BNX_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3857
3858#define BNX_TXP_CPU_STATE 0x00045004
3859#define BNX_TXP_CPU_STATE_BREAKPOINT (1L<<0)
3860#define BNX_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3861#define BNX_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3862#define BNX_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3863#define BNX_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3864#define BNX_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3865#define BNX_TXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3866#define BNX_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3867#define BNX_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
3868#define BNX_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3869#define BNX_TXP_CPU_STATE_INTERRRUPT (1L<<12)
3870#define BNX_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3871#define BNX_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3872#define BNX_TXP_CPU_STATE_BLOCKED_READ (1L<<31)
3873
3874#define BNX_TXP_CPU_EVENT_MASK 0x00045008
3875#define BNX_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3876#define BNX_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3877#define BNX_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3878#define BNX_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3879#define BNX_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3880#define BNX_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3881#define BNX_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3882#define BNX_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3883#define BNX_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3884#define BNX_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3885#define BNX_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3886
3887#define BNX_TXP_CPU_PROGRAM_COUNTER 0x0004501c
3888#define BNX_TXP_CPU_INSTRUCTION 0x00045020
3889#define BNX_TXP_CPU_DATA_ACCESS 0x00045024
3890#define BNX_TXP_CPU_INTERRUPT_ENABLE 0x00045028
3891#define BNX_TXP_CPU_INTERRUPT_VECTOR 0x0004502c
3892#define BNX_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030
3893#define BNX_TXP_CPU_HW_BREAKPOINT 0x00045034
3894#define BNX_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3895#define BNX_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3896
3897#define BNX_TXP_CPU_DEBUG_VECT_PEEK 0x00045038
3898#define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3899#define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3900#define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3901#define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3902#define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3903#define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3904
3905#define BNX_TXP_CPU_LAST_BRANCH_ADDR 0x00045048
3906#define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3907#define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3908#define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3909#define BNX_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3910
3911#define BNX_TXP_CPU_REG_FILE 0x00045200
3912#define BNX_TXP_FTQ_DATA 0x000453c0
3913#define BNX_TXP_FTQ_CMD 0x000453f8
3914#define BNX_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3915#define BNX_TXP_FTQ_CMD_WR_TOP (1L<<10)
3916#define BNX_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
3917#define BNX_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
3918#define BNX_TXP_FTQ_CMD_SFT_RESET (1L<<25)
3919#define BNX_TXP_FTQ_CMD_RD_DATA (1L<<26)
3920#define BNX_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
3921#define BNX_TXP_FTQ_CMD_ADD_DATA (1L<<28)
3922#define BNX_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
3923#define BNX_TXP_FTQ_CMD_POP (1L<<30)
3924#define BNX_TXP_FTQ_CMD_BUSY (1L<<31)
3925
3926#define BNX_TXP_FTQ_CTL 0x000453fc
3927#define BNX_TXP_FTQ_CTL_INTERVENE (1L<<0)
3928#define BNX_TXP_FTQ_CTL_OVERFLOW (1L<<1)
3929#define BNX_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3930#define BNX_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3931#define BNX_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3932
3933#define BNX_TXP_SCRATCH 0x00060000
3934
3935
3936/*
3937 * tpat_reg definition
3938 * offset: 0x80000
3939 */
3940#define BNX_TPAT_CPU_MODE 0x00085000
3941#define BNX_TPAT_CPU_MODE_LOCAL_RST (1L<<0)
3942#define BNX_TPAT_CPU_MODE_STEP_ENA (1L<<1)
3943#define BNX_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3944#define BNX_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3945#define BNX_TPAT_CPU_MODE_MSG_BIT1 (1L<<6)
3946#define BNX_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7)
3947#define BNX_TPAT_CPU_MODE_SOFT_HALT (1L<<10)
3948#define BNX_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3949#define BNX_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3950#define BNX_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3951#define BNX_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3952
3953#define BNX_TPAT_CPU_STATE 0x00085004
3954#define BNX_TPAT_CPU_STATE_BREAKPOINT (1L<<0)
3955#define BNX_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2)
3956#define BNX_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3957#define BNX_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3958#define BNX_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3959#define BNX_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6)
3960#define BNX_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7)
3961#define BNX_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3962#define BNX_TPAT_CPU_STATE_SOFT_HALTED (1L<<10)
3963#define BNX_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3964#define BNX_TPAT_CPU_STATE_INTERRRUPT (1L<<12)
3965#define BNX_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3966#define BNX_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15)
3967#define BNX_TPAT_CPU_STATE_BLOCKED_READ (1L<<31)
3968
3969#define BNX_TPAT_CPU_EVENT_MASK 0x00085008
3970#define BNX_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3971#define BNX_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3972#define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3973#define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3974#define BNX_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3975#define BNX_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3976#define BNX_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3977#define BNX_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3978#define BNX_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3979#define BNX_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3980#define BNX_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3981
3982#define BNX_TPAT_CPU_PROGRAM_COUNTER 0x0008501c
3983#define BNX_TPAT_CPU_INSTRUCTION 0x00085020
3984#define BNX_TPAT_CPU_DATA_ACCESS 0x00085024
3985#define BNX_TPAT_CPU_INTERRUPT_ENABLE 0x00085028
3986#define BNX_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c
3987#define BNX_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030
3988#define BNX_TPAT_CPU_HW_BREAKPOINT 0x00085034
3989#define BNX_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3990#define BNX_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3991
3992#define BNX_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038
3993#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3994#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3995#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3996#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3997#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3998#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3999
4000#define BNX_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048
4001#define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4002#define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4003#define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4004#define BNX_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4005
4006#define BNX_TPAT_CPU_REG_FILE 0x00085200
4007#define BNX_TPAT_FTQ_DATA 0x000853c0
4008#define BNX_TPAT_FTQ_CMD 0x000853f8
4009#define BNX_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
4010#define BNX_TPAT_FTQ_CMD_WR_TOP (1L<<10)
4011#define BNX_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
4012#define BNX_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
4013#define BNX_TPAT_FTQ_CMD_SFT_RESET (1L<<25)
4014#define BNX_TPAT_FTQ_CMD_RD_DATA (1L<<26)
4015#define BNX_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27)
4016#define BNX_TPAT_FTQ_CMD_ADD_DATA (1L<<28)
4017#define BNX_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29)
4018#define BNX_TPAT_FTQ_CMD_POP (1L<<30)
4019#define BNX_TPAT_FTQ_CMD_BUSY (1L<<31)
4020
4021#define BNX_TPAT_FTQ_CTL 0x000853fc
4022#define BNX_TPAT_FTQ_CTL_INTERVENE (1L<<0)
4023#define BNX_TPAT_FTQ_CTL_OVERFLOW (1L<<1)
4024#define BNX_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4025#define BNX_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4026#define BNX_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4027
4028#define BNX_TPAT_SCRATCH 0x000a0000
4029
4030
4031/*
4032 * rxp_reg definition
4033 * offset: 0xc0000
4034 */
4035#define BNX_RXP_CPU_MODE 0x000c5000
4036#define BNX_RXP_CPU_MODE_LOCAL_RST (1L<<0)
4037#define BNX_RXP_CPU_MODE_STEP_ENA (1L<<1)
4038#define BNX_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
4039#define BNX_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
4040#define BNX_RXP_CPU_MODE_MSG_BIT1 (1L<<6)
4041#define BNX_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
4042#define BNX_RXP_CPU_MODE_SOFT_HALT (1L<<10)
4043#define BNX_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
4044#define BNX_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
4045#define BNX_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
4046#define BNX_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
4047
4048#define BNX_RXP_CPU_STATE 0x000c5004
4049#define BNX_RXP_CPU_STATE_BREAKPOINT (1L<<0)
4050#define BNX_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
4051#define BNX_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
4052#define BNX_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
4053#define BNX_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
4054#define BNX_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
4055#define BNX_RXP_CPU_STATE_ALIGN_HALTED (1L<<7)
4056#define BNX_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
4057#define BNX_RXP_CPU_STATE_SOFT_HALTED (1L<<10)
4058#define BNX_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
4059#define BNX_RXP_CPU_STATE_INTERRRUPT (1L<<12)
4060#define BNX_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
4061#define BNX_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
4062#define BNX_RXP_CPU_STATE_BLOCKED_READ (1L<<31)
4063
4064#define BNX_RXP_CPU_EVENT_MASK 0x000c5008
4065#define BNX_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
4066#define BNX_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
4067#define BNX_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
4068#define BNX_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
4069#define BNX_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
4070#define BNX_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
4071#define BNX_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
4072#define BNX_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
4073#define BNX_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
4074#define BNX_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
4075#define BNX_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
4076
4077#define BNX_RXP_CPU_PROGRAM_COUNTER 0x000c501c
4078#define BNX_RXP_CPU_INSTRUCTION 0x000c5020
4079#define BNX_RXP_CPU_DATA_ACCESS 0x000c5024
4080#define BNX_RXP_CPU_INTERRUPT_ENABLE 0x000c5028
4081#define BNX_RXP_CPU_INTERRUPT_VECTOR 0x000c502c
4082#define BNX_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030
4083#define BNX_RXP_CPU_HW_BREAKPOINT 0x000c5034
4084#define BNX_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4085#define BNX_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4086
4087#define BNX_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038
4088#define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4089#define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4090#define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4091#define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4092#define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4093#define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4094
4095#define BNX_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048
4096#define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4097#define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4098#define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4099#define BNX_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4100
4101#define BNX_RXP_CPU_REG_FILE 0x000c5200
4102#define BNX_RXP_CFTQ_DATA 0x000c5380
4103#define BNX_RXP_CFTQ_CMD 0x000c53b8
4104#define BNX_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
4105#define BNX_RXP_CFTQ_CMD_WR_TOP (1L<<10)
4106#define BNX_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
4107#define BNX_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
4108#define BNX_RXP_CFTQ_CMD_SFT_RESET (1L<<25)
4109#define BNX_RXP_CFTQ_CMD_RD_DATA (1L<<26)
4110#define BNX_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27)
4111#define BNX_RXP_CFTQ_CMD_ADD_DATA (1L<<28)
4112#define BNX_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29)
4113#define BNX_RXP_CFTQ_CMD_POP (1L<<30)
4114#define BNX_RXP_CFTQ_CMD_BUSY (1L<<31)
4115
4116#define BNX_RXP_CFTQ_CTL 0x000c53bc
4117#define BNX_RXP_CFTQ_CTL_INTERVENE (1L<<0)
4118#define BNX_RXP_CFTQ_CTL_OVERFLOW (1L<<1)
4119#define BNX_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2)
4120#define BNX_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4121#define BNX_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4122
4123#define BNX_RXP_FTQ_DATA 0x000c53c0
4124#define BNX_RXP_FTQ_CMD 0x000c53f8
4125#define BNX_RXP_FTQ_CMD_OFFSET (0x3ffL<<0)
4126#define BNX_RXP_FTQ_CMD_WR_TOP (1L<<10)
4127#define BNX_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
4128#define BNX_RXP_FTQ_CMD_WR_TOP_1 (1L<<10)
4129#define BNX_RXP_FTQ_CMD_SFT_RESET (1L<<25)
4130#define BNX_RXP_FTQ_CMD_RD_DATA (1L<<26)
4131#define BNX_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
4132#define BNX_RXP_FTQ_CMD_ADD_DATA (1L<<28)
4133#define BNX_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
4134#define BNX_RXP_FTQ_CMD_POP (1L<<30)
4135#define BNX_RXP_FTQ_CMD_BUSY (1L<<31)
4136
4137#define BNX_RXP_FTQ_CTL 0x000c53fc
4138#define BNX_RXP_FTQ_CTL_INTERVENE (1L<<0)
4139#define BNX_RXP_FTQ_CTL_OVERFLOW (1L<<1)
4140#define BNX_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4141#define BNX_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4142#define BNX_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4143
4144#define BNX_RXP_SCRATCH 0x000e0000
4145
4146
4147/*
4148 * com_reg definition
4149 * offset: 0x100000
4150 */
4151#define BNX_COM_CPU_MODE 0x00105000
4152#define BNX_COM_CPU_MODE_LOCAL_RST (1L<<0)
4153#define BNX_COM_CPU_MODE_STEP_ENA (1L<<1)
4154#define BNX_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
4155#define BNX_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
4156#define BNX_COM_CPU_MODE_MSG_BIT1 (1L<<6)
4157#define BNX_COM_CPU_MODE_INTERRUPT_ENA (1L<<7)
4158#define BNX_COM_CPU_MODE_SOFT_HALT (1L<<10)
4159#define BNX_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
4160#define BNX_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
4161#define BNX_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
4162#define BNX_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
4163
4164#define BNX_COM_CPU_STATE 0x00105004
4165#define BNX_COM_CPU_STATE_BREAKPOINT (1L<<0)
4166#define BNX_COM_CPU_STATE_BAD_INST_HALTED (1L<<2)
4167#define BNX_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
4168#define BNX_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
4169#define BNX_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
4170#define BNX_COM_CPU_STATE_BAD_pc_HALTED (1L<<6)
4171#define BNX_COM_CPU_STATE_ALIGN_HALTED (1L<<7)
4172#define BNX_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
4173#define BNX_COM_CPU_STATE_SOFT_HALTED (1L<<10)
4174#define BNX_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
4175#define BNX_COM_CPU_STATE_INTERRRUPT (1L<<12)
4176#define BNX_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
4177#define BNX_COM_CPU_STATE_INST_FETCH_STALL (1L<<15)
4178#define BNX_COM_CPU_STATE_BLOCKED_READ (1L<<31)
4179
4180#define BNX_COM_CPU_EVENT_MASK 0x00105008
4181#define BNX_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
4182#define BNX_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
4183#define BNX_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
4184#define BNX_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
4185#define BNX_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
4186#define BNX_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
4187#define BNX_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
4188#define BNX_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
4189#define BNX_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
4190#define BNX_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
4191#define BNX_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
4192
4193#define BNX_COM_CPU_PROGRAM_COUNTER 0x0010501c
4194#define BNX_COM_CPU_INSTRUCTION 0x00105020
4195#define BNX_COM_CPU_DATA_ACCESS 0x00105024
4196#define BNX_COM_CPU_INTERRUPT_ENABLE 0x00105028
4197#define BNX_COM_CPU_INTERRUPT_VECTOR 0x0010502c
4198#define BNX_COM_CPU_INTERRUPT_SAVED_PC 0x00105030
4199#define BNX_COM_CPU_HW_BREAKPOINT 0x00105034
4200#define BNX_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4201#define BNX_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4202
4203#define BNX_COM_CPU_DEBUG_VECT_PEEK 0x00105038
4204#define BNX_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4205#define BNX_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4206#define BNX_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4207#define BNX_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4208#define BNX_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4209#define BNX_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4210
4211#define BNX_COM_CPU_LAST_BRANCH_ADDR 0x00105048
4212#define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4213#define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4214#define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4215#define BNX_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4216
4217#define BNX_COM_CPU_REG_FILE 0x00105200
4218#define BNX_COM_COMXQ_FTQ_DATA 0x00105340
4219#define BNX_COM_COMXQ_FTQ_CMD 0x00105378
4220#define BNX_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4221#define BNX_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
4222#define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4223#define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4224#define BNX_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)
4225#define BNX_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26)
4226#define BNX_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4227#define BNX_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28)
4228#define BNX_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4229#define BNX_COM_COMXQ_FTQ_CMD_POP (1L<<30)
4230#define BNX_COM_COMXQ_FTQ_CMD_BUSY (1L<<31)
4231
4232#define BNX_COM_COMXQ_FTQ_CTL 0x0010537c
4233#define BNX_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0)
4234#define BNX_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1)
4235#define BNX_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4236#define BNX_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4237#define BNX_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4238
4239#define BNX_COM_COMTQ_FTQ_DATA 0x00105380
4240#define BNX_COM_COMTQ_FTQ_CMD 0x001053b8
4241#define BNX_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4242#define BNX_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10)
4243#define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4244#define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4245#define BNX_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25)
4246#define BNX_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26)
4247#define BNX_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4248#define BNX_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28)
4249#define BNX_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4250#define BNX_COM_COMTQ_FTQ_CMD_POP (1L<<30)
4251#define BNX_COM_COMTQ_FTQ_CMD_BUSY (1L<<31)
4252
4253#define BNX_COM_COMTQ_FTQ_CTL 0x001053bc
4254#define BNX_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0)
4255#define BNX_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1)
4256#define BNX_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4257#define BNX_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4258#define BNX_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4259
4260#define BNX_COM_COMQ_FTQ_DATA 0x001053c0
4261#define BNX_COM_COMQ_FTQ_CMD 0x001053f8
4262#define BNX_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4263#define BNX_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10)
4264#define BNX_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4265#define BNX_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4266#define BNX_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25)
4267#define BNX_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26)
4268#define BNX_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4269#define BNX_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28)
4270#define BNX_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4271#define BNX_COM_COMQ_FTQ_CMD_POP (1L<<30)
4272#define BNX_COM_COMQ_FTQ_CMD_BUSY (1L<<31)
4273
4274#define BNX_COM_COMQ_FTQ_CTL 0x001053fc
4275#define BNX_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0)
4276#define BNX_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1)
4277#define BNX_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4278#define BNX_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4279#define BNX_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4280
4281#define BNX_COM_SCRATCH 0x00120000
4282
4283
4284/*
4285 * cp_reg definition
4286 * offset: 0x180000
4287 */
4288#define BNX_CP_CPU_MODE 0x00185000
4289#define BNX_CP_CPU_MODE_LOCAL_RST (1L<<0)
4290#define BNX_CP_CPU_MODE_STEP_ENA (1L<<1)
4291#define BNX_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
4292#define BNX_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
4293#define BNX_CP_CPU_MODE_MSG_BIT1 (1L<<6)
4294#define BNX_CP_CPU_MODE_INTERRUPT_ENA (1L<<7)
4295#define BNX_CP_CPU_MODE_SOFT_HALT (1L<<10)
4296#define BNX_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
4297#define BNX_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
4298#define BNX_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
4299#define BNX_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
4300
4301#define BNX_CP_CPU_STATE 0x00185004
4302#define BNX_CP_CPU_STATE_BREAKPOINT (1L<<0)
4303#define BNX_CP_CPU_STATE_BAD_INST_HALTED (1L<<2)
4304#define BNX_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
4305#define BNX_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
4306#define BNX_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
4307#define BNX_CP_CPU_STATE_BAD_pc_HALTED (1L<<6)
4308#define BNX_CP_CPU_STATE_ALIGN_HALTED (1L<<7)
4309#define BNX_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
4310#define BNX_CP_CPU_STATE_SOFT_HALTED (1L<<10)
4311#define BNX_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
4312#define BNX_CP_CPU_STATE_INTERRRUPT (1L<<12)
4313#define BNX_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
4314#define BNX_CP_CPU_STATE_INST_FETCH_STALL (1L<<15)
4315#define BNX_CP_CPU_STATE_BLOCKED_READ (1L<<31)
4316
4317#define BNX_CP_CPU_EVENT_MASK 0x00185008
4318#define BNX_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
4319#define BNX_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
4320#define BNX_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
4321#define BNX_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
4322#define BNX_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
4323#define BNX_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
4324#define BNX_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
4325#define BNX_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
4326#define BNX_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
4327#define BNX_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
4328#define BNX_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
4329
4330#define BNX_CP_CPU_PROGRAM_COUNTER 0x0018501c
4331#define BNX_CP_CPU_INSTRUCTION 0x00185020
4332#define BNX_CP_CPU_DATA_ACCESS 0x00185024
4333#define BNX_CP_CPU_INTERRUPT_ENABLE 0x00185028
4334#define BNX_CP_CPU_INTERRUPT_VECTOR 0x0018502c
4335#define BNX_CP_CPU_INTERRUPT_SAVED_PC 0x00185030
4336#define BNX_CP_CPU_HW_BREAKPOINT 0x00185034
4337#define BNX_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4338#define BNX_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4339
4340#define BNX_CP_CPU_DEBUG_VECT_PEEK 0x00185038
4341#define BNX_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4342#define BNX_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4343#define BNX_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4344#define BNX_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4345#define BNX_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4346#define BNX_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4347
4348#define BNX_CP_CPU_LAST_BRANCH_ADDR 0x00185048
4349#define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4350#define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4351#define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4352#define BNX_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4353
4354#define BNX_CP_CPU_REG_FILE 0x00185200
4355#define BNX_CP_CPQ_FTQ_DATA 0x001853c0
4356#define BNX_CP_CPQ_FTQ_CMD 0x001853f8
4357#define BNX_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4358#define BNX_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
4359#define BNX_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4360#define BNX_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4361#define BNX_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)
4362#define BNX_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26)
4363#define BNX_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4364#define BNX_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28)
4365#define BNX_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4366#define BNX_CP_CPQ_FTQ_CMD_POP (1L<<30)
4367#define BNX_CP_CPQ_FTQ_CMD_BUSY (1L<<31)
4368
4369#define BNX_CP_CPQ_FTQ_CTL 0x001853fc
4370#define BNX_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0)
4371#define BNX_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1)
4372#define BNX_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4373#define BNX_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4374#define BNX_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4375
4376#define BNX_CP_SCRATCH 0x001a0000
4377
4378
4379/*
4380 * mcp_reg definition
4381 * offset: 0x140000
4382 */
4383#define BNX_MCP_CPU_MODE 0x00145000
4384#define BNX_MCP_CPU_MODE_LOCAL_RST (1L<<0)
4385#define BNX_MCP_CPU_MODE_STEP_ENA (1L<<1)
4386#define BNX_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
4387#define BNX_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
4388#define BNX_MCP_CPU_MODE_MSG_BIT1 (1L<<6)
4389#define BNX_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7)
4390#define BNX_MCP_CPU_MODE_SOFT_HALT (1L<<10)
4391#define BNX_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
4392#define BNX_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
4393#define BNX_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
4394#define BNX_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
4395
4396#define BNX_MCP_CPU_STATE 0x00145004
4397#define BNX_MCP_CPU_STATE_BREAKPOINT (1L<<0)
4398#define BNX_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2)
4399#define BNX_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
4400#define BNX_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
4401#define BNX_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
4402#define BNX_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6)
4403#define BNX_MCP_CPU_STATE_ALIGN_HALTED (1L<<7)
4404#define BNX_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
4405#define BNX_MCP_CPU_STATE_SOFT_HALTED (1L<<10)
4406#define BNX_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
4407#define BNX_MCP_CPU_STATE_INTERRRUPT (1L<<12)
4408#define BNX_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
4409#define BNX_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15)
4410#define BNX_MCP_CPU_STATE_BLOCKED_READ (1L<<31)
4411
4412#define BNX_MCP_CPU_EVENT_MASK 0x00145008
4413#define BNX_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
4414#define BNX_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
4415#define BNX_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
4416#define BNX_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
4417#define BNX_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
4418#define BNX_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
4419#define BNX_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
4420#define BNX_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
4421#define BNX_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
4422#define BNX_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
4423#define BNX_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
4424
4425#define BNX_MCP_CPU_PROGRAM_COUNTER 0x0014501c
4426#define BNX_MCP_CPU_INSTRUCTION 0x00145020
4427#define BNX_MCP_CPU_DATA_ACCESS 0x00145024
4428#define BNX_MCP_CPU_INTERRUPT_ENABLE 0x00145028
4429#define BNX_MCP_CPU_INTERRUPT_VECTOR 0x0014502c
4430#define BNX_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030
4431#define BNX_MCP_CPU_HW_BREAKPOINT 0x00145034
4432#define BNX_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4433#define BNX_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4434
4435#define BNX_MCP_CPU_DEBUG_VECT_PEEK 0x00145038
4436#define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4437#define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4438#define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4439#define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4440#define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4441#define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4442
4443#define BNX_MCP_CPU_LAST_BRANCH_ADDR 0x00145048
4444#define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4445#define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4446#define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4447#define BNX_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4448
4449#define BNX_MCP_CPU_REG_FILE 0x00145200
4450#define BNX_MCP_MCPQ_FTQ_DATA 0x001453c0
4451#define BNX_MCP_MCPQ_FTQ_CMD 0x001453f8
4452#define BNX_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4453#define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
4454#define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4455#define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4456#define BNX_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)
4457#define BNX_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26)
4458#define BNX_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4459#define BNX_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28)
4460#define BNX_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4461#define BNX_MCP_MCPQ_FTQ_CMD_POP (1L<<30)
4462#define BNX_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31)
4463
4464#define BNX_MCP_MCPQ_FTQ_CTL 0x001453fc
4465#define BNX_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
4466#define BNX_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1)
4467#define BNX_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4468#define BNX_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4469#define BNX_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4470
4471#define BNX_MCP_ROM 0x00150000
4472#define BNX_MCP_SCRATCH 0x00160000
4473
4474#define BNX_SHM_HDR_SIGNATURE BNX_MCP_SCRATCH
4475#define BNX_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000
4476#define BNX_SHM_HDR_SIGNATURE_SIG 0x53530000
4477#define BNX_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff
4478#define BNX_SHM_HDR_SIGNATURE_VER_ONE 0x00000001
4479
4480#define BNX_SHM_HDR_ADDR_0 BNX_MCP_SCRATCH + 4
4481#define BNX_SHM_HDR_ADDR_1 BNX_MCP_SCRATCH + 8
4482
4483/****************************************************************************/
4484/* End machine generated definitions. */
4485/****************************************************************************/
4486
4487#define NUM_MC_HASH_REGISTERS 8
4488
4489
4490/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */
4491#define PHY_BCM5706_PHY_ID 0x00206160
4492
4493#define PHY_ID(id) ((id) & 0xfffffff0)
4494#define PHY_REV_ID(id) ((id) & 0xf)
4495
4496/* 5708 Serdes PHY registers */
4497
4498#define BCM5708S_UP1 0xb
4499
4500#define BCM5708S_UP1_2G5 0x1
4501
4502#define BCM5708S_BLK_ADDR 0x1f
4503
4504#define BCM5708S_BLK_ADDR_DIG 0x0000
4505#define BCM5708S_BLK_ADDR_DIG3 0x0002
4506#define BCM5708S_BLK_ADDR_TX_MISC 0x0005
4507
4508/* Digital Block */
4509#define BCM5708S_1000X_CTL1 0x10
4510
4511#define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001
4512#define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010
4513
4514#define BCM5708S_1000X_CTL2 0x11
4515
4516#define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001
4517
4518#define BCM5708S_1000X_STAT1 0x14
4519
4520#define BCM5708S_1000X_STAT1_SGMII 0x0001
4521#define BCM5708S_1000X_STAT1_LINK 0x0002
4522#define BCM5708S_1000X_STAT1_FD 0x0004
4523#define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018
4524#define BCM5708S_1000X_STAT1_SPEED_10 0x0000
4525#define BCM5708S_1000X_STAT1_SPEED_100 0x0008
4526#define BCM5708S_1000X_STAT1_SPEED_1G 0x0010
4527#define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018
4528#define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020
4529#define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040
4530
4531/* Digital3 Block */
4532#define BCM5708S_DIG_3_0 0x10
4533
4534#define BCM5708S_DIG_3_0_USE_IEEE 0x0001
4535
4536/* Tx/Misc Block */
4537#define BCM5708S_TX_ACTL1 0x15
4538
4539#define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30
4540
4541#define BCM5708S_TX_ACTL3 0x17
4542
4543#define RX_COPY_THRESH 92
4544
4545#define DMA_READ_CHANS 5
4546#define DMA_WRITE_CHANS 3
4547
4548/* Use the natural page size of the host CPU. */
4549#define BCM_PAGE_BITS PAGE_SHIFT
4550#define BCM_PAGE_SIZE PAGE_SIZE
4551
4552#define TX_PAGES 2
4553#define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd))
4554#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1)
4555#define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES)
4556#define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES)
4557#define MAX_TX_BD (TOTAL_TX_BD - 1)
4558
4559#define RX_PAGES 2
4560#define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd))
4561#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1)
4562#define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES)
4563#define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES)
4564#define MAX_RX_BD (TOTAL_RX_BD - 1)
4565
4566#define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \
4567 (USABLE_TX_BD_PER_PAGE - 1)) ? \
4568 (x) + 2 : (x) + 1
4569
4570#define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD)
4571
4572#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
4573#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
4574
4575#define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \
4576 (USABLE_RX_BD_PER_PAGE - 1)) ? \
4577 (x) + 2 : (x) + 1
4578
4579#define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD)
4580
4581#define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
4582#define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE)
4583
4584/* Context size. */
4585#define BNX_CTX_SHIFT 7
4586#define BNX_CTX_SIZE (1 << BNX_CTX_SHIFT)
4587#define BNX_CTX_MASK (BNX_CTX_SIZE - 1)
4588#define GET_CID_ADDR(_cid) ((_cid) << BNX_CTX_SHIFT)
4589#define GET_CID(_cid_addr) ((_cid_addr) >> BNX_CTX_SHIFT)
4590
4591#define BNX_PHY_CTX_SHIFT 6
4592#define BNX_PHY_CTX_SIZE (1 << BNX_PHY_CTX_SHIFT)
4593#define BNX_PHY_CTX_MASK (BNX_PHY_CTX_SIZE - 1)
4594#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_BNX_CTX_SHIFT)
4595#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_BNX_CTX_SHIFT)
4596
4597#define BNX_MB_KERNEL_CTX_SHIFT 8
4598#define BNX_MB_KERNEL_CTX_SIZE (1 << BNX_MB_KERNEL_CTX_SHIFT)
4599#define BNX_MB_KERNEL_CTX_MASK (BNX_MB_KERNEL_CTX_SIZE - 1)
4600#define BNX_MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << BNX_MB_KERNEL_CTX_SHIFT))
4601
4602#define MAX_CID_CNT 0x4000
4603#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT))
4604#define INVALID_CID_ADDR 0xffffffff
4605
4606#define TX_CID 16
4607#define RX_CID 0
4608
4609#define MB_TX_CID_ADDR BNX_MB_GET_CID_ADDR(TX_CID)
4610#define MB_RX_CID_ADDR BNX_MB_GET_CID_ADDR(RX_CID)
4611
4612/****************************************************************************/
4613/* BNX Processor Firmwware Load Definitions */
4614/****************************************************************************/
4615
4616struct cpu_reg {
4617 uint32_t mode;
4618 uint32_t mode_value_halt;
4619 uint32_t mode_value_sstep;
4620
4621 uint32_t state;
4622 uint32_t state_value_clear;
4623
4624 uint32_t gpr0;
4625 uint32_t evmask;
4626 uint32_t pc;
4627 uint32_t inst;
4628 uint32_t bp;
4629
4630 uint32_t spad_base;
4631
4632 uint32_t mips_view_base;
4633};
4634
4635struct fw_info {
4636 uint32_t ver_major;
4637 uint32_t ver_minor;
4638 uint32_t ver_fix;
4639
4640 uint32_t start_addr;
4641
4642 /* Text section. */
4643 uint32_t text_addr;
4644 uint32_t text_len;
4645 uint32_t text_index;
4646 uint32_t *text;
4647
4648 /* Data section. */
4649 uint32_t data_addr;
4650 uint32_t data_len;
4651 uint32_t data_index;
4652 uint32_t *data;
4653
4654 /* SBSS section. */
4655 uint32_t sbss_addr;
4656 uint32_t sbss_len;
4657 uint32_t sbss_index;
4658 uint32_t *sbss;
4659
4660 /* BSS section. */
4661 uint32_t bss_addr;
4662 uint32_t bss_len;
4663 uint32_t bss_index;
4664 uint32_t *bss;
4665
4666 /* Read-only section. */
4667 uint32_t rodata_addr;
4668 uint32_t rodata_len;
4669 uint32_t rodata_index;
4670 uint32_t *rodata;
4671};
4672
4673struct bnx_rv2p_header {
4674 int bnx_rv2p_proc1len;
4675 int bnx_rv2p_proc2len;
4676
4677 /*
4678 * Followed by blocks of data, each sized according to
4679 * the (rather obvious) block length stated above.
4680 */
4681};
4682
4683/*
4684 * The RV2P block must be configured for the system
4685 * page size, or more specifically, the number of
4686 * usable rx_bd's per page, and should be called
4687 * as follows prior to loading the RV2P firmware:
4688 *
4689 * BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE)
4690 *
4691 * The default value is 0xFF.
4692 */
4693#define BNX_RV2P_PROC2_MAX_BD_PAGE_LOC 5
4694#define BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(_rv2p, _v) { \
4695 _rv2p[BNX_RV2P_PROC2_MAX_BD_PAGE_LOC] = \
4696 (_rv2p[BNX_RV2P_PROC2_MAX_BD_PAGE_LOC] & ~0xFFFF) | (_v); \
4697}
4698
4699#define RV2P_PROC1 0
4700#define RV2P_PROC2 1
4701
4702#define BNX_MIREG(x) ((x & 0x1F) << 16)
4703#define BNX_MIPHY(x) ((x & 0x1F) << 21)
4704#define BNX_PHY_TIMEOUT 50
4705
4706#define BNX_NVRAM_SIZE 0x200
4707#define BNX_NVRAM_MAGIC 0x669955aa
4708#define BNX_CRC32_RESIDUAL 0xdebb20e3
4709
4710#define BNX_TX_TIMEOUT 5
4711
4712#define BNX_MAX_SEGMENTS 8
4713#define BNX_DMA_ALIGN 8
4714#define BNX_DMA_BOUNDARY 0
4715
4716#define BNX_MIN_MTU 60
4717#define BNX_MIN_ETHER_MTU 64
4718
4719#define BNX_MAX_STD_MTU 1500
4720#define BNX_MAX_STD_ETHER_MTU 1518
4721#define BNX_MAX_STD_ETHER_MTU_VLAN 1522
4722
4723#define BNX_MAX_JUMBO_MTU 9000
4724#define BNX_MAX_JUMBO_ETHER_MTU 9018
4725#define BNX_MAX_JUMBO_ETHER_MTU_VLAN 9022
4726
4727#define BNX_MAX_MRU MCLBYTES
4728#define BNX_MAX_JUMBO_MRU 9216
4729