1 | /* |
2 | * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting |
3 | * Copyright (c) 2002-2008 Atheros Communications, Inc. |
4 | * |
5 | * Permission to use, copy, modify, and/or distribute this software for any |
6 | * purpose with or without fee is hereby granted, provided that the above |
7 | * copyright notice and this permission notice appear in all copies. |
8 | * |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
16 | * |
17 | * $Id: ah_eeprom_v3.h,v 1.1.1.1 2008/12/11 04:46:25 alc Exp $ |
18 | */ |
19 | #ifndef _ATH_AH_EEPROM_V3_H_ |
20 | #define _ATH_AH_EEPROM_V3_H_ |
21 | |
22 | #include "ah_eeprom.h" |
23 | |
24 | /* EEPROM defines for Version 2 & 3 AR5211 chips */ |
25 | #define AR_EEPROM_RFSILENT 0x0f /* RF Silent/Clock Run Enable */ |
26 | #define AR_EEPROM_MAC(i) (0x1d+(i)) /* MAC address word */ |
27 | #define AR_EEPROM_MAGIC 0x3d /* magic number */ |
28 | #define AR_EEPROM_PROTECT 0x3f /* EEPROM protect bits */ |
29 | #define AR_EEPROM_PROTECT_PCIE 0x01 /* EEPROM protect bits for Condor/Swan*/ |
30 | #define AR_EEPROM_REG_DOMAIN 0xbf /* current regulatory domain */ |
31 | #define AR_EEPROM_ATHEROS_BASE 0xc0 /* Base of Atheros-specific data */ |
32 | #define AR_EEPROM_ATHEROS(i) (AR_EEPROM_ATHEROS_BASE+(i)) |
33 | #define AR_EEPROM_ATHEROS_MAX (0x400-AR_EEPROM_ATHEROS_BASE) |
34 | #define AR_EEPROM_VERSION AR_EEPROM_ATHEROS(1) |
35 | |
36 | /* FLASH(EEPROM) Defines for AR531X chips */ |
37 | #define AR_EEPROM_SIZE_LOWER 0x1b /* size info -- lower */ |
38 | #define AR_EEPROM_SIZE_UPPER 0x1c /* size info -- upper */ |
39 | #define AR_EEPROM_SIZE_UPPER_MASK 0xfff0 |
40 | #define AR_EEPROM_SIZE_UPPER_SHIFT 4 |
41 | #define AR_EEPROM_SIZE_ENDLOC_SHIFT 12 |
42 | #define AR_EEPROM_ATHEROS_MAX_LOC 0x400 |
43 | #define AR_EEPROM_ATHEROS_MAX_OFF (AR_EEPROM_ATHEROS_MAX_LOC-AR_EEPROM_ATHEROS_BASE) |
44 | |
45 | /* regulatory capabilities offsets */ |
46 | #define AR_EEPROM_REG_CAPABILITIES_OFFSET 0xCA |
47 | #define AR_EEPROM_REG_CAPABILITIES_OFFSET_PRE4_0 0xCF /* prior to 4.0 */ |
48 | |
49 | /* regulatory capabilities */ |
50 | #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 |
51 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 |
52 | #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 |
53 | #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 |
54 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 |
55 | #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 |
56 | |
57 | /* regulatory capabilities prior to eeprom version 4.0 */ |
58 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 |
59 | #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 |
60 | |
61 | /* |
62 | * AR2413 (includes AR5413) |
63 | */ |
64 | #define AR_EEPROM_SERIAL_NUM_OFFSET 0xB0 /* EEPROM serial number */ |
65 | #define AR_EEPROM_SERIAL_NUM_SIZE 12 /* EEPROM serial number size */ |
66 | #define AR_EEPROM_CAPABILITIES_OFFSET 0xC9 /* EEPROM Location of capabilities */ |
67 | |
68 | #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 |
69 | #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 |
70 | #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 |
71 | #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 |
72 | #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 |
73 | #define AR_EEPROM_EEPCAP_MAXQCU_S 4 |
74 | #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 |
75 | #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 |
76 | #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 |
77 | |
78 | /* XXX used to index various EEPROM-derived data structures */ |
79 | enum { |
80 | = 0, |
81 | = 1, |
82 | = 2, |
83 | }; |
84 | |
85 | #define GROUPS_OFFSET3_2 0x100 /* groups offset for ver3.2 and earlier */ |
86 | #define GROUPS_OFFSET3_3 0x150 /* groups offset for ver3.3 */ |
87 | /* relative offset of GROUPi to GROUPS_OFFSET */ |
88 | #define GROUP1_OFFSET 0x0 |
89 | #define GROUP2_OFFSET 0x5 |
90 | #define GROUP3_OFFSET 0x37 |
91 | #define GROUP4_OFFSET 0x46 |
92 | #define GROUP5_OFFSET 0x55 |
93 | #define GROUP6_OFFSET 0x65 |
94 | #define GROUP7_OFFSET 0x69 |
95 | #define GROUP8_OFFSET 0x6f |
96 | |
97 | /* RF silent fields in EEPROM */ |
98 | #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c |
99 | #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 |
100 | #define AR_EEPROM_RFSILENT_POLARITY 0x0002 |
101 | #define AR_EEPROM_RFSILENT_POLARITY_S 1 |
102 | |
103 | /* Protect Bits RP is read protect, WP is write protect */ |
104 | #define AR_EEPROM_PROTECT_RP_0_31 0x0001 |
105 | #define AR_EEPROM_PROTECT_WP_0_31 0x0002 |
106 | #define AR_EEPROM_PROTECT_RP_32_63 0x0004 |
107 | #define AR_EEPROM_PROTECT_WP_32_63 0x0008 |
108 | #define AR_EEPROM_PROTECT_RP_64_127 0x0010 |
109 | #define AR_EEPROM_PROTECT_WP_64_127 0x0020 |
110 | #define AR_EEPROM_PROTECT_RP_128_191 0x0040 |
111 | #define AR_EEPROM_PROTECT_WP_128_191 0x0080 |
112 | #define AR_EEPROM_PROTECT_RP_192_207 0x0100 |
113 | #define AR_EEPROM_PROTECT_WP_192_207 0x0200 |
114 | #define AR_EEPROM_PROTECT_RP_208_223 0x0400 |
115 | #define AR_EEPROM_PROTECT_WP_208_223 0x0800 |
116 | #define AR_EEPROM_PROTECT_RP_224_239 0x1000 |
117 | #define AR_EEPROM_PROTECT_WP_224_239 0x2000 |
118 | #define AR_EEPROM_PROTECT_RP_240_255 0x4000 |
119 | #define AR_EEPROM_PROTECT_WP_240_255 0x8000 |
120 | |
121 | #define AR_EEPROM_MODAL_SPURS 5 |
122 | #define AR_SPUR_5413_1 1640 /* Freq 2464 */ |
123 | #define AR_SPUR_5413_2 1200 /* Freq 2420 */ |
124 | |
125 | /* |
126 | * EEPROM fixed point conversion scale factors. |
127 | * NB: if you change one be sure to keep the other in sync. |
128 | */ |
129 | #define EEP_SCALE 100 /* conversion scale to avoid fp arith */ |
130 | #define EEP_DELTA 10 /* SCALE/10, to avoid arith divide */ |
131 | |
132 | #define PWR_MIN 0 |
133 | #define PWR_MAX 3150 /* 31.5 * SCALE */ |
134 | #define PWR_STEP 50 /* 0.5 * SCALE */ |
135 | /* Keep 2 above defines together */ |
136 | |
137 | #define NUM_11A_EEPROM_CHANNELS 10 |
138 | #define NUM_2_4_EEPROM_CHANNELS 3 |
139 | #define NUM_PCDAC_VALUES 11 |
140 | #define NUM_TEST_FREQUENCIES 8 |
141 | #define NUM_EDGES 8 |
142 | #define NUM_INTERCEPTS 11 |
143 | #define FREQ_MASK 0x7f |
144 | #define FREQ_MASK_3_3 0xff /* expanded in version 3.3 */ |
145 | #define PCDAC_MASK 0x3f |
146 | #define POWER_MASK 0x3f |
147 | #define NON_EDGE_FLAG_MASK 0x40 |
148 | #define CHANNEL_POWER_INFO 8 |
149 | #define OBDB_UNSET 0xffff |
150 | #define CHANNEL_UNUSED 0xff |
151 | #define SCALE_OC_DELTA(_x) (((_x) * 2) / 10) |
152 | |
153 | /* Used during pcdac table construction */ |
154 | #define PCDAC_START 1 |
155 | #define PCDAC_STOP 63 |
156 | #define PCDAC_STEP 1 |
157 | #define PWR_TABLE_SIZE 64 |
158 | #define MAX_RATE_POWER 63 |
159 | |
160 | /* Used during power/rate table construction */ |
161 | #define NUM_CTLS 16 |
162 | #define NUM_CTLS_3_3 32 /* expanded in version 3.3 */ |
163 | #define NUM_CTLS_MAX NUM_CTLS_3_3 |
164 | |
165 | typedef struct fullPcdacStruct { |
166 | uint16_t channelValue; |
167 | uint16_t pcdacMin; |
168 | uint16_t pcdacMax; |
169 | uint16_t numPcdacValues; |
170 | uint16_t PcdacValues[64]; |
171 | /* power is 32bit since in dest it is scaled */ |
172 | int16_t PwrValues[64]; |
173 | } FULL_PCDAC_STRUCT; |
174 | |
175 | typedef struct dataPerChannel { |
176 | uint16_t channelValue; |
177 | uint16_t pcdacMin; |
178 | uint16_t pcdacMax; |
179 | uint16_t numPcdacValues; |
180 | uint16_t PcdacValues[NUM_PCDAC_VALUES]; |
181 | /* NB: power is 32bit since in dest it is scaled */ |
182 | int16_t PwrValues[NUM_PCDAC_VALUES]; |
183 | } DATA_PER_CHANNEL; |
184 | |
185 | /* points to the appropriate pcdac structs in the above struct based on mode */ |
186 | typedef struct pcdacsEeprom { |
187 | const uint16_t *pChannelList; |
188 | uint16_t numChannels; |
189 | const DATA_PER_CHANNEL *pDataPerChannel; |
190 | } PCDACS_EEPROM; |
191 | |
192 | typedef struct trgtPowerInfo { |
193 | uint16_t twicePwr54; |
194 | uint16_t twicePwr48; |
195 | uint16_t twicePwr36; |
196 | uint16_t twicePwr6_24; |
197 | uint16_t testChannel; |
198 | } TRGT_POWER_INFO; |
199 | |
200 | typedef struct trgtPowerAllModes { |
201 | uint16_t numTargetPwr_11a; |
202 | TRGT_POWER_INFO trgtPwr_11a[NUM_TEST_FREQUENCIES]; |
203 | uint16_t numTargetPwr_11g; |
204 | TRGT_POWER_INFO trgtPwr_11g[3]; |
205 | uint16_t numTargetPwr_11b; |
206 | TRGT_POWER_INFO trgtPwr_11b[2]; |
207 | } TRGT_POWER_ALL_MODES; |
208 | |
209 | typedef struct cornerCalInfo { |
210 | uint16_t gSel; |
211 | uint16_t pd84; |
212 | uint16_t pd90; |
213 | uint16_t clip; |
214 | } CORNER_CAL_INFO; |
215 | |
216 | /* |
217 | * EEPROM version 4 definitions |
218 | */ |
219 | #define NUM_XPD_PER_CHANNEL 4 |
220 | #define NUM_POINTS_XPD0 4 |
221 | #define NUM_POINTS_XPD3 3 |
222 | #define IDEAL_10dB_INTERCEPT_2G 35 |
223 | #define IDEAL_10dB_INTERCEPT_5G 55 |
224 | |
225 | #define TENX_OFDM_CCK_DELTA_INIT 15 /* power 1.5 dbm */ |
226 | #define TENX_CH14_FILTER_CCK_DELTA_INIT 15 /* power 1.5 dbm */ |
227 | #define CCK_OFDM_GAIN_DELTA 15 |
228 | |
229 | #define NUM_TARGET_POWER_LOCATIONS_11B 4 |
230 | #define NUM_TARGET_POWER_LOCATIONS_11G 6 |
231 | |
232 | |
233 | typedef struct { |
234 | uint16_t xpd_gain; |
235 | uint16_t numPcdacs; |
236 | uint16_t pcdac[NUM_POINTS_XPD0]; |
237 | int16_t pwr_t4[NUM_POINTS_XPD0]; /* or gainF */ |
238 | } EXPN_DATA_PER_XPD_5112; |
239 | |
240 | typedef struct { |
241 | uint16_t channelValue; |
242 | int16_t maxPower_t4; |
243 | EXPN_DATA_PER_XPD_5112 pDataPerXPD[NUM_XPD_PER_CHANNEL]; |
244 | } EXPN_DATA_PER_CHANNEL_5112; |
245 | |
246 | typedef struct { |
247 | uint16_t *pChannels; |
248 | uint16_t numChannels; |
249 | uint16_t xpdMask; /* mask of permitted xpd_gains */ |
250 | EXPN_DATA_PER_CHANNEL_5112 *pDataPerChannel; |
251 | } EEPROM_POWER_EXPN_5112; |
252 | |
253 | typedef struct { |
254 | uint16_t channelValue; |
255 | uint16_t pcd1_xg0; |
256 | int16_t pwr1_xg0; |
257 | uint16_t pcd2_delta_xg0; |
258 | int16_t pwr2_xg0; |
259 | uint16_t pcd3_delta_xg0; |
260 | int16_t pwr3_xg0; |
261 | uint16_t pcd4_delta_xg0; |
262 | int16_t pwr4_xg0; |
263 | int16_t maxPower_t4; |
264 | int16_t pwr1_xg3; /* pcdac = 20 */ |
265 | int16_t pwr2_xg3; /* pcdac = 35 */ |
266 | int16_t pwr3_xg3; /* pcdac = 63 */ |
267 | /* XXX - Should be pwr1_xg2, etc to agree with documentation */ |
268 | } EEPROM_DATA_PER_CHANNEL_5112; |
269 | |
270 | typedef struct { |
271 | uint16_t pChannels[NUM_11A_EEPROM_CHANNELS]; |
272 | uint16_t numChannels; |
273 | uint16_t xpdMask; /* mask of permitted xpd_gains */ |
274 | EEPROM_DATA_PER_CHANNEL_5112 pDataPerChannel[NUM_11A_EEPROM_CHANNELS]; |
275 | } EEPROM_POWER_5112; |
276 | |
277 | /* |
278 | * EEPROM version 5 definitions (Griffin, et. al.). |
279 | */ |
280 | #define NUM_2_4_EEPROM_CHANNELS_2413 4 |
281 | #define NUM_11A_EEPROM_CHANNELS_2413 10 |
282 | #define PWR_TABLE_SIZE_2413 128 |
283 | |
284 | /* Used during pdadc construction */ |
285 | #define MAX_NUM_PDGAINS_PER_CHANNEL 4 |
286 | #define NUM_PDGAINS_PER_CHANNEL 2 |
287 | #define NUM_POINTS_LAST_PDGAIN 5 |
288 | #define NUM_POINTS_OTHER_PDGAINS 4 |
289 | #define XPD_GAIN1_GEN5 3 |
290 | #define XPD_GAIN2_GEN5 1 |
291 | #define MAX_PWR_RANGE_IN_HALF_DB 64 |
292 | #define PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB 4 |
293 | |
294 | typedef struct { |
295 | uint16_t pd_gain; |
296 | uint16_t numVpd; |
297 | uint16_t Vpd[NUM_POINTS_LAST_PDGAIN]; |
298 | int16_t pwr_t4[NUM_POINTS_LAST_PDGAIN]; /* or gainF */ |
299 | } RAW_DATA_PER_PDGAIN_2413; |
300 | |
301 | typedef struct { |
302 | uint16_t channelValue; |
303 | int16_t maxPower_t4; |
304 | uint16_t numPdGains; /* # Pd Gains per channel */ |
305 | RAW_DATA_PER_PDGAIN_2413 pDataPerPDGain[MAX_NUM_PDGAINS_PER_CHANNEL]; |
306 | } RAW_DATA_PER_CHANNEL_2413; |
307 | |
308 | /* XXX: assumes NUM_11A_EEPROM_CHANNELS_2413 >= NUM_2_4_EEPROM_CHANNELS_2413 ??? */ |
309 | typedef struct { |
310 | uint16_t pChannels[NUM_11A_EEPROM_CHANNELS_2413]; |
311 | uint16_t numChannels; |
312 | uint16_t xpd_mask; /* mask of permitted xpd_gains */ |
313 | RAW_DATA_PER_CHANNEL_2413 pDataPerChannel[NUM_11A_EEPROM_CHANNELS_2413]; |
314 | } RAW_DATA_STRUCT_2413; |
315 | |
316 | typedef struct { |
317 | uint16_t channelValue; |
318 | uint16_t numPdGains; |
319 | uint16_t Vpd_I[MAX_NUM_PDGAINS_PER_CHANNEL]; |
320 | int16_t pwr_I[MAX_NUM_PDGAINS_PER_CHANNEL]; |
321 | uint16_t Vpd_delta[NUM_POINTS_LAST_PDGAIN] |
322 | [MAX_NUM_PDGAINS_PER_CHANNEL]; |
323 | int16_t pwr_delta_t2[NUM_POINTS_LAST_PDGAIN] |
324 | [MAX_NUM_PDGAINS_PER_CHANNEL]; |
325 | int16_t maxPower_t4; |
326 | } EEPROM_DATA_PER_CHANNEL_2413; |
327 | |
328 | typedef struct { |
329 | uint16_t pChannels[NUM_11A_EEPROM_CHANNELS_2413]; |
330 | uint16_t numChannels; |
331 | uint16_t xpd_mask; /* mask of permitted xpd_gains */ |
332 | EEPROM_DATA_PER_CHANNEL_2413 pDataPerChannel[NUM_11A_EEPROM_CHANNELS_2413]; |
333 | } EEPROM_DATA_STRUCT_2413; |
334 | |
335 | /* |
336 | * Information retrieved from EEPROM. |
337 | */ |
338 | typedef struct { |
339 | uint16_t ee_version; /* Version field */ |
340 | uint16_t ee_protect; /* EEPROM protect field */ |
341 | uint16_t ee_regdomain; /* Regulatory domain */ |
342 | |
343 | /* General Device Parameters */ |
344 | uint16_t ee_turbo5Disable; |
345 | uint16_t ee_turbo2Disable; |
346 | uint16_t ee_rfKill; |
347 | uint16_t ee_deviceType; |
348 | uint16_t ee_turbo2WMaxPower5; |
349 | uint16_t ee_turbo2WMaxPower2; |
350 | uint16_t ee_xrTargetPower5; |
351 | uint16_t ee_xrTargetPower2; |
352 | uint16_t ee_Amode; |
353 | uint16_t ee_regCap; |
354 | uint16_t ee_Bmode; |
355 | uint16_t ee_Gmode; |
356 | int8_t ee_antennaGainMax[2]; |
357 | uint16_t ee_xtnd5GSupport; |
358 | uint8_t ee_cckOfdmPwrDelta; |
359 | uint8_t ee_exist32kHzCrystal; |
360 | uint16_t ; |
361 | uint16_t ee_fixedBias5; |
362 | uint16_t ee_fixedBias2; |
363 | uint16_t ee_cckOfdmGainDelta; |
364 | uint16_t ee_scaledCh14FilterCckDelta; |
365 | uint16_t ee_eepMap; |
366 | uint16_t ee_earStart; |
367 | |
368 | /* 5 GHz / 2.4 GHz CKK / 2.4 GHz OFDM common parameters */ |
369 | uint16_t ee_switchSettling[3]; |
370 | uint16_t ee_txrxAtten[3]; |
371 | uint16_t ee_txEndToXLNAOn[3]; |
372 | uint16_t ee_thresh62[3]; |
373 | uint16_t ee_txEndToXPAOff[3]; |
374 | uint16_t ee_txFrameToXPAOn[3]; |
375 | int8_t ee_adcDesiredSize[3]; /* 8-bit signed value */ |
376 | int8_t ee_pgaDesiredSize[3]; /* 8-bit signed value */ |
377 | int16_t ee_noiseFloorThresh[3]; |
378 | uint16_t ee_xlnaGain[3]; |
379 | uint16_t ee_xgain[3]; |
380 | uint16_t ee_xpd[3]; |
381 | uint16_t ee_antennaControl[11][3]; |
382 | uint16_t ee_falseDetectBackoff[3]; |
383 | uint16_t ee_gainI[3]; |
384 | uint16_t ee_rxtxMargin[3]; |
385 | |
386 | /* new parameters added for the AR2413 */ |
387 | HAL_BOOL ee_disableXr5; |
388 | HAL_BOOL ee_disableXr2; |
389 | uint16_t ee_eepMap2PowerCalStart; |
390 | uint16_t ee_capField; |
391 | |
392 | uint16_t ee_switchSettlingTurbo[2]; |
393 | uint16_t ee_txrxAttenTurbo[2]; |
394 | int8_t ee_adcDesiredSizeTurbo[2]; |
395 | int8_t ee_pgaDesiredSizeTurbo[2]; |
396 | uint16_t ee_rxtxMarginTurbo[2]; |
397 | |
398 | /* 5 GHz parameters */ |
399 | uint16_t ee_ob1; |
400 | uint16_t ee_db1; |
401 | uint16_t ee_ob2; |
402 | uint16_t ee_db2; |
403 | uint16_t ee_ob3; |
404 | uint16_t ee_db3; |
405 | uint16_t ee_ob4; |
406 | uint16_t ee_db4; |
407 | |
408 | /* 2.4 GHz parameters */ |
409 | uint16_t ee_obFor24; |
410 | uint16_t ee_dbFor24; |
411 | uint16_t ee_obFor24g; |
412 | uint16_t ee_dbFor24g; |
413 | uint16_t ee_ob2GHz[2]; |
414 | uint16_t ee_db2GHz[2]; |
415 | uint16_t ee_numCtls; |
416 | uint16_t ee_ctl[NUM_CTLS_MAX]; |
417 | uint16_t ee_iqCalI[2]; |
418 | uint16_t ee_iqCalQ[2]; |
419 | uint16_t ee_calPier11g[NUM_2_4_EEPROM_CHANNELS]; |
420 | uint16_t ee_calPier11b[NUM_2_4_EEPROM_CHANNELS]; |
421 | |
422 | /* corner calibration information */ |
423 | CORNER_CAL_INFO ee_cornerCal; |
424 | |
425 | uint16_t ee_opCap; |
426 | |
427 | /* 11a info */ |
428 | uint16_t ee_channels11a[NUM_11A_EEPROM_CHANNELS]; |
429 | uint16_t ee_numChannels11a; |
430 | DATA_PER_CHANNEL ee_dataPerChannel11a[NUM_11A_EEPROM_CHANNELS]; |
431 | |
432 | uint16_t ee_numChannels2_4; |
433 | uint16_t ee_channels11g[NUM_2_4_EEPROM_CHANNELS]; |
434 | uint16_t ee_channels11b[NUM_2_4_EEPROM_CHANNELS]; |
435 | uint16_t ee_spurChans[AR_EEPROM_MODAL_SPURS][2]; |
436 | |
437 | /* 11g info */ |
438 | DATA_PER_CHANNEL ee_dataPerChannel11g[NUM_2_4_EEPROM_CHANNELS]; |
439 | |
440 | /* 11b info */ |
441 | DATA_PER_CHANNEL ee_dataPerChannel11b[NUM_2_4_EEPROM_CHANNELS]; |
442 | |
443 | TRGT_POWER_ALL_MODES ee_tpow; |
444 | |
445 | RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*NUM_CTLS_MAX]; |
446 | |
447 | union { |
448 | EEPROM_POWER_EXPN_5112 eu_modePowerArray5112[3]; |
449 | RAW_DATA_STRUCT_2413 eu_rawDataset2413[3]; |
450 | } ee_u; |
451 | } HAL_EEPROM; |
452 | |
453 | /* write-around defines */ |
454 | #define ee_numTargetPwr_11a ee_tpow.numTargetPwr_11a |
455 | #define ee_trgtPwr_11a ee_tpow.trgtPwr_11a |
456 | #define ee_numTargetPwr_11g ee_tpow.numTargetPwr_11g |
457 | #define ee_trgtPwr_11g ee_tpow.trgtPwr_11g |
458 | #define ee_numTargetPwr_11b ee_tpow.numTargetPwr_11b |
459 | #define ee_trgtPwr_11b ee_tpow.trgtPwr_11b |
460 | #define ee_modePowerArray5112 ee_u.eu_modePowerArray5112 |
461 | #define ee_rawDataset2413 ee_u.eu_rawDataset2413 |
462 | #endif /* _ATH_AH_EEPROM_V3_H_ */ |
463 | |