1 | /****************************************************************************** |
2 | |
3 | Copyright (c) 2001-2013, Intel Corporation |
4 | All rights reserved. |
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7 | modification, are permitted provided that the following conditions are met: |
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32 | ******************************************************************************/ |
33 | /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_dcb.h 251964 2013-06-18 21:28:19Z jfv $*/ |
34 | |
35 | #ifndef _IXGBE_DCB_H_ |
36 | #define _IXGBE_DCB_H_ |
37 | |
38 | |
39 | #include "ixgbe_type.h" |
40 | |
41 | /* DCB defines */ |
42 | /* DCB credit calculation defines */ |
43 | #define IXGBE_DCB_CREDIT_QUANTUM 64 |
44 | #define IXGBE_DCB_MAX_CREDIT_REFILL 200 /* 200 * 64B = 12800B */ |
45 | #define IXGBE_DCB_MAX_TSO_SIZE (32 * 1024) /* Max TSO pkt size in DCB*/ |
46 | #define IXGBE_DCB_MAX_CREDIT (2 * IXGBE_DCB_MAX_CREDIT_REFILL) |
47 | |
48 | /* 513 for 32KB TSO packet */ |
49 | #define IXGBE_DCB_MIN_TSO_CREDIT \ |
50 | ((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1) |
51 | |
52 | /* DCB configuration defines */ |
53 | #define IXGBE_DCB_MAX_USER_PRIORITY 8 |
54 | #define IXGBE_DCB_MAX_BW_GROUP 8 |
55 | #define IXGBE_DCB_BW_PERCENT 100 |
56 | |
57 | #define IXGBE_DCB_TX_CONFIG 0 |
58 | #define IXGBE_DCB_RX_CONFIG 1 |
59 | |
60 | /* DCB capability defines */ |
61 | #define IXGBE_DCB_PG_SUPPORT 0x00000001 |
62 | #define IXGBE_DCB_PFC_SUPPORT 0x00000002 |
63 | #define IXGBE_DCB_BCN_SUPPORT 0x00000004 |
64 | #define IXGBE_DCB_UP2TC_SUPPORT 0x00000008 |
65 | #define IXGBE_DCB_GSP_SUPPORT 0x00000010 |
66 | |
67 | struct ixgbe_dcb_support { |
68 | u32 capabilities; /* DCB capabilities */ |
69 | |
70 | /* Each bit represents a number of TCs configurable in the hw. |
71 | * If 8 traffic classes can be configured, the value is 0x80. */ |
72 | u8 traffic_classes; |
73 | u8 pfc_traffic_classes; |
74 | }; |
75 | |
76 | enum ixgbe_dcb_tsa { |
77 | ixgbe_dcb_tsa_ets = 0, |
78 | ixgbe_dcb_tsa_group_strict_cee, |
79 | ixgbe_dcb_tsa_strict |
80 | }; |
81 | |
82 | /* Traffic class bandwidth allocation per direction */ |
83 | struct ixgbe_dcb_tc_path { |
84 | u8 bwg_id; /* Bandwidth Group (BWG) ID */ |
85 | u8 bwg_percent; /* % of BWG's bandwidth */ |
86 | u8 link_percent; /* % of link bandwidth */ |
87 | u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */ |
88 | u16 data_credits_refill; /* Credit refill amount in 64B granularity */ |
89 | u16 data_credits_max; /* Max credits for a configured packet buffer |
90 | * in 64B granularity.*/ |
91 | enum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */ |
92 | }; |
93 | |
94 | enum ixgbe_dcb_pfc { |
95 | ixgbe_dcb_pfc_disabled = 0, |
96 | ixgbe_dcb_pfc_enabled, |
97 | ixgbe_dcb_pfc_enabled_txonly, |
98 | ixgbe_dcb_pfc_enabled_rxonly |
99 | }; |
100 | |
101 | /* Traffic class configuration */ |
102 | struct ixgbe_dcb_tc_config { |
103 | struct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */ |
104 | enum ixgbe_dcb_pfc pfc; /* Class based flow control setting */ |
105 | |
106 | u16 desc_credits_max; /* For Tx Descriptor arbitration */ |
107 | u8 tc; /* Traffic class (TC) */ |
108 | }; |
109 | |
110 | enum ixgbe_dcb_pba { |
111 | /* PBA[0-7] each use 64KB FIFO */ |
112 | ixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL, |
113 | /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */ |
114 | ixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED |
115 | }; |
116 | |
117 | struct ixgbe_dcb_num_tcs { |
118 | u8 pg_tcs; |
119 | u8 pfc_tcs; |
120 | }; |
121 | |
122 | struct ixgbe_dcb_config { |
123 | struct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS]; |
124 | struct ixgbe_dcb_support support; |
125 | struct ixgbe_dcb_num_tcs num_tcs; |
126 | u8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */ |
127 | bool pfc_mode_enable; |
128 | bool round_robin_enable; |
129 | |
130 | enum ixgbe_dcb_pba rx_pba_cfg; |
131 | |
132 | u32 dcb_cfg_version; /* Not used...OS-specific? */ |
133 | u32 link_speed; /* For bandwidth allocation validation purpose */ |
134 | bool vt_mode; |
135 | }; |
136 | |
137 | /* DCB driver APIs */ |
138 | |
139 | /* DCB rule checking */ |
140 | s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *); |
141 | |
142 | /* DCB credits calculation */ |
143 | s32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int); |
144 | s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *, |
145 | struct ixgbe_dcb_config *, u32, u8); |
146 | |
147 | /* DCB PFC */ |
148 | s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *); |
149 | s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *); |
150 | |
151 | /* DCB stats */ |
152 | s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *); |
153 | s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8); |
154 | s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8); |
155 | |
156 | /* DCB config arbiters */ |
157 | s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *, |
158 | struct ixgbe_dcb_config *); |
159 | s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *, |
160 | struct ixgbe_dcb_config *); |
161 | s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *, |
162 | struct ixgbe_dcb_config *); |
163 | |
164 | /* DCB unpack routines */ |
165 | void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *); |
166 | void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *, int, u16 *); |
167 | void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *, u16 *); |
168 | void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *); |
169 | void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *); |
170 | void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *); |
171 | u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8); |
172 | |
173 | /* DCB initialization */ |
174 | s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *); |
175 | s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *); |
176 | #endif /* _IXGBE_DCB_H_ */ |
177 | |