1 | /* $NetBSD: nouveau_engine_device_nv10.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Ben Skeggs |
25 | */ |
26 | |
27 | #include <sys/cdefs.h> |
28 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_device_nv10.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $" ); |
29 | |
30 | #include <subdev/bios.h> |
31 | #include <subdev/bus.h> |
32 | #include <subdev/gpio.h> |
33 | #include <subdev/i2c.h> |
34 | #include <subdev/clock.h> |
35 | #include <subdev/devinit.h> |
36 | #include <subdev/mc.h> |
37 | #include <subdev/timer.h> |
38 | #include <subdev/fb.h> |
39 | #include <subdev/instmem.h> |
40 | #include <subdev/vm.h> |
41 | |
42 | #include <engine/device.h> |
43 | #include <engine/dmaobj.h> |
44 | #include <engine/fifo.h> |
45 | #include <engine/software.h> |
46 | #include <engine/graph.h> |
47 | #include <engine/disp.h> |
48 | |
49 | int |
50 | nv10_identify(struct nouveau_device *device) |
51 | { |
52 | switch (device->chipset) { |
53 | case 0x10: |
54 | device->cname = "NV10" ; |
55 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
56 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
57 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
58 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
59 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
60 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
61 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
62 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
63 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
64 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
65 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
66 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
67 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; |
68 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
69 | break; |
70 | case 0x15: |
71 | device->cname = "NV15" ; |
72 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
73 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
74 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
75 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
76 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
77 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
78 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
79 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
80 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
81 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
82 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
83 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
84 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; |
85 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
86 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; |
87 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
88 | break; |
89 | case 0x16: |
90 | device->cname = "NV16" ; |
91 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
92 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
93 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
94 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
95 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
96 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
97 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
98 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
99 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
100 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
101 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
102 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
103 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; |
104 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
105 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; |
106 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
107 | break; |
108 | case 0x1a: |
109 | device->cname = "nForce" ; |
110 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
111 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
112 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
113 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
114 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
115 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
116 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
117 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
118 | device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; |
119 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
120 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
121 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
122 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; |
123 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
124 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; |
125 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
126 | break; |
127 | case 0x11: |
128 | device->cname = "NV11" ; |
129 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
130 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
131 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
132 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
133 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
134 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
135 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
136 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
137 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
138 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
139 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
140 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
141 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; |
142 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
143 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; |
144 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
145 | break; |
146 | case 0x17: |
147 | device->cname = "NV17" ; |
148 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
149 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
150 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
151 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
152 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
153 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
154 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
155 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
156 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
157 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
158 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
159 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
160 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
161 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
162 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; |
163 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
164 | break; |
165 | case 0x1f: |
166 | device->cname = "nForce2" ; |
167 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
168 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
169 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
170 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
171 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
172 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
173 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
174 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
175 | device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; |
176 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
177 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
178 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
179 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
180 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
181 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; |
182 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
183 | break; |
184 | case 0x18: |
185 | device->cname = "NV18" ; |
186 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
187 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
188 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
189 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
190 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
191 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
192 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
193 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
194 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
195 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
196 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
197 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
198 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
199 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; |
200 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; |
201 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
202 | break; |
203 | default: |
204 | nv_fatal(device, "unknown Celsius chipset\n" ); |
205 | return -EINVAL; |
206 | } |
207 | |
208 | return 0; |
209 | } |
210 | |