1/* $NetBSD: atphy.c,v 1.18 2016/11/02 10:11:32 msaitoh Exp $ */
2/* $OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $ */
3
4/*-
5 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31/*
32 * Driver for the Attansic F1 10/100/1000 PHY.
33 */
34
35#include <sys/cdefs.h>
36__KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.18 2016/11/02 10:11:32 msaitoh Exp $");
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/kernel.h>
41#include <sys/device.h>
42#include <sys/socket.h>
43
44#include <net/if.h>
45#include <net/if_media.h>
46
47#include <dev/mii/mii.h>
48#include <dev/mii/miivar.h>
49#include <dev/mii/miidevs.h>
50
51/* Special Control Register */
52#define ATPHY_SCR 0x10
53#define ATPHY_SCR_JABBER_DISABLE 0x0001
54#define ATPHY_SCR_POLARITY_REVERSAL 0x0002
55#define ATPHY_SCR_SQE_TEST 0x0004
56#define ATPHY_SCR_MAC_PDOWN 0x0008
57#define ATPHY_SCR_CLK125_DISABLE 0x0010
58#define ATPHY_SCR_MDI_MANUAL_MODE 0x0000
59#define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020
60#define ATPHY_SCR_AUTO_X_1000T 0x0040
61#define ATPHY_SCR_AUTO_X_MODE 0x0060
62#define ATPHY_SCR_10BT_EXT_ENABLE 0x0080
63#define ATPHY_SCR_MII_5BIT_ENABLE 0x0100
64#define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200
65#define ATPHY_SCR_FORCE_LINK_GOOD 0x0400
66#define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800
67
68/* Special Status Register. */
69#define ATPHY_SSR 0x11
70#define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800
71#define ATPHY_SSR_DUPLEX 0x2000
72#define ATPHY_SSR_SPEED_MASK 0xC000
73#define ATPHY_SSR_10MBS 0x0000
74#define ATPHY_SSR_100MBS 0x4000
75#define ATPHY_SSR_1000MBS 0x8000
76
77static int atphy_match(device_t, cfdata_t, void *);
78static void atphy_attach(device_t, device_t, void *);
79
80static int atphy_service(struct mii_softc *, struct mii_data *, int);
81static void atphy_reset(struct mii_softc *);
82static void atphy_status(struct mii_softc *);
83static int atphy_mii_phy_auto(struct mii_softc *);
84static bool atphy_is_gige(const struct mii_phydesc *);
85
86CFATTACH_DECL_NEW(atphy, sizeof(struct mii_softc),
87 atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate);
88
89const struct mii_phy_funcs atphy_funcs = {
90 atphy_service, atphy_status, atphy_reset,
91};
92
93static const struct mii_phydesc etphys[] = {
94 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1,
95 MII_STR_ATHEROS_F1 },
96 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L1,
97 MII_STR_ATTANSIC_L1 },
98 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L2,
99 MII_STR_ATTANSIC_L2 },
100 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8021,
101 MII_STR_ATTANSIC_AR8021 },
102 { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8035,
103 MII_STR_ATTANSIC_AR8035 },
104 { 0, 0,
105 NULL },
106};
107
108static bool
109atphy_is_gige(const struct mii_phydesc *mpd)
110{
111 switch (mpd->mpd_oui) {
112 case MII_OUI_ATTANSIC:
113 switch (mpd->mpd_model) {
114 case MII_MODEL_ATTANSIC_L2:
115 return false;
116 }
117 }
118
119 return true;
120}
121
122static int
123atphy_match(device_t parent, cfdata_t match, void *aux)
124{
125 struct mii_attach_args *ma = aux;
126
127 if (mii_phy_match(ma, etphys) != NULL)
128 return 10;
129
130 return 0;
131}
132
133void
134atphy_attach(device_t parent, device_t self, void *aux)
135{
136 struct mii_softc *sc = device_private(self);
137 struct mii_attach_args *ma = aux;
138 struct mii_data *mii = ma->mii_data;
139 const struct mii_phydesc *mpd;
140 uint16_t bmsr;
141
142 mpd = mii_phy_match(ma, etphys);
143 aprint_naive(": Media interface\n");
144 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
145
146 sc->mii_dev = self;
147 sc->mii_inst = mii->mii_instance;
148 sc->mii_phy = ma->mii_phyno;
149 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
150 sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
151 sc->mii_mpd_rev = MII_REV(ma->mii_id2);
152 sc->mii_funcs = &atphy_funcs;
153 sc->mii_pdata = mii;
154 sc->mii_flags = ma->mii_flags;
155 if (atphy_is_gige(mpd))
156 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
157 else
158 sc->mii_anegticks = MII_ANEGTICKS;
159
160 sc->mii_flags |= MIIF_NOLOOP;
161
162 PHY_RESET(sc);
163
164 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
165 sc->mii_capabilities = bmsr & ma->mii_capmask;
166 if (atphy_is_gige(mpd) && (sc->mii_capabilities & BMSR_EXTSTAT))
167 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
168
169 aprint_normal_dev(self, "");
170 mii_phy_add_media(sc);
171 aprint_normal("\n");
172}
173
174int
175atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
176{
177 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
178 uint16_t anar, bmcr, bmsr;
179
180 switch (cmd) {
181 case MII_POLLSTAT:
182 /*
183 * If we're not polling our PHY instance, just return.
184 */
185 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
186 return 0;
187 break;
188
189 case MII_MEDIACHG:
190 /*
191 * If the media indicates a different PHY instance,
192 * isolate ourselves.
193 */
194 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
195 bmcr = PHY_READ(sc, MII_BMCR);
196 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
197 return 0;
198 }
199
200 /*
201 * If the interface is not up, don't do anything.
202 */
203 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
204 break;
205
206 bmcr = 0;
207 switch (IFM_SUBTYPE(ife->ifm_media)) {
208 case IFM_AUTO:
209 case IFM_1000_T:
210 atphy_mii_phy_auto(sc);
211 goto done;
212 case IFM_100_TX:
213 bmcr = BMCR_S100;
214 break;
215 case IFM_10_T:
216 bmcr = BMCR_S10;
217 break;
218 case IFM_NONE:
219 bmcr = PHY_READ(sc, MII_BMCR);
220 /*
221 * XXX
222 * Due to an unknown reason powering down PHY resulted
223 * in unexpected results such as inaccessibility of
224 * hardware of freshly rebooted system. Disable
225 * powering down PHY until I got more information for
226 * Attansic/Atheros PHY hardwares.
227 */
228 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
229 goto done;
230 default:
231 return EINVAL;
232 }
233
234 anar = mii_anar(IFM_SUBTYPE(ife->ifm_media));
235 if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
236 bmcr |= BMCR_FDX;
237 /* Enable pause. */
238 if (sc->mii_flags & MIIF_DOPAUSE)
239 anar |= ANAR_PAUSE_TOWARDS;
240 }
241
242 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX |
243 EXTSR_1000THDX)) != 0)
244 PHY_WRITE(sc, MII_100T2CR, 0);
245 PHY_WRITE(sc, MII_ANAR, anar);
246
247 /*
248 * Start autonegotiation.
249 */
250 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG);
251done:
252 break;
253
254 case MII_TICK:
255 /*
256 * If we're not currently selected, just return.
257 */
258 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
259 return 0;
260
261 /*
262 * Is the interface even up?
263 */
264 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
265 return 0;
266
267 /*
268 * Only used for autonegotiation.
269 */
270 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) &&
271 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) {
272 sc->mii_ticks = 0;
273 break;
274 }
275
276 /*
277 * Check for link.
278 * Read the status register twice; BMSR_LINK is latch-low.
279 */
280 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
281 if (bmsr & BMSR_LINK) {
282 sc->mii_ticks = 0;
283 break;
284 }
285
286 /* Announce link loss right after it happens. */
287 if (sc->mii_ticks++ == 0)
288 break;
289
290 /*
291 * Only retry autonegotiation every mii_anegticks seconds.
292 */
293 if (sc->mii_ticks <= sc->mii_anegticks)
294 break;
295
296 atphy_mii_phy_auto(sc);
297 break;
298 }
299
300 /* Update the media status. */
301 mii_phy_status(sc);
302
303 /* Callback if something changed. */
304 mii_phy_update(sc, cmd);
305 return 0;
306}
307
308static void
309atphy_status(struct mii_softc *sc)
310{
311 struct mii_data *mii = sc->mii_pdata;
312 uint32_t bmsr, bmcr, gsr, ssr;
313
314 mii->mii_media_status = IFM_AVALID;
315 mii->mii_media_active = IFM_ETHER;
316
317 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
318 if (bmsr & BMSR_LINK)
319 mii->mii_media_status |= IFM_ACTIVE;
320
321 bmcr = PHY_READ(sc, MII_BMCR);
322 if (bmcr & BMCR_ISO) {
323 mii->mii_media_active |= IFM_NONE;
324 mii->mii_media_status = 0;
325 return;
326 }
327
328 if (bmcr & BMCR_LOOP)
329 mii->mii_media_active |= IFM_LOOP;
330
331 ssr = PHY_READ(sc, ATPHY_SSR);
332 if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) {
333 /* Erg, still trying, I guess... */
334 mii->mii_media_active |= IFM_NONE;
335 return;
336 }
337
338 switch (ssr & ATPHY_SSR_SPEED_MASK) {
339 case ATPHY_SSR_1000MBS:
340 mii->mii_media_active |= IFM_1000_T;
341 /*
342 * atphy(4) has a valid link so reset mii_ticks.
343 * Resetting mii_ticks is needed in order to
344 * detect link loss after auto-negotiation.
345 */
346 sc->mii_ticks = 0;
347 break;
348 case ATPHY_SSR_100MBS:
349 mii->mii_media_active |= IFM_100_TX;
350 sc->mii_ticks = 0;
351 break;
352 case ATPHY_SSR_10MBS:
353 mii->mii_media_active |= IFM_10_T;
354 sc->mii_ticks = 0;
355 break;
356 default:
357 mii->mii_media_active |= IFM_NONE;
358 return;
359 }
360
361 if (ssr & ATPHY_SSR_DUPLEX)
362 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
363 else
364 mii->mii_media_active |= IFM_HDX;
365
366 gsr = PHY_READ(sc, MII_100T2SR);
367 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
368 gsr & GTSR_MS_RES)
369 mii->mii_media_active |= IFM_ETH_MASTER;
370}
371
372static void
373atphy_reset(struct mii_softc *sc)
374{
375 uint32_t reg;
376 int i;
377
378 /* Take PHY out of power down mode. */
379 PHY_WRITE(sc, 29, 0x29);
380 PHY_WRITE(sc, 30, 0);
381
382 reg = PHY_READ(sc, ATPHY_SCR);
383 /* Enable automatic crossover. */
384 reg |= ATPHY_SCR_AUTO_X_MODE;
385 /* Disable power down. */
386 reg &= ~ATPHY_SCR_MAC_PDOWN;
387 /* Enable CRS on Tx. */
388 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
389 /* Auto correction for reversed cable polarity. */
390 reg |= ATPHY_SCR_POLARITY_REVERSAL;
391 PHY_WRITE(sc, ATPHY_SCR, reg);
392
393 atphy_mii_phy_auto(sc);
394
395 /* Workaround F1 bug to reset phy. */
396 reg = PHY_READ(sc, MII_BMCR) | BMCR_RESET;
397 PHY_WRITE(sc, MII_BMCR, reg);
398
399 for (i = 0; i < 1000; i++) {
400 DELAY(1);
401 if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
402 break;
403 }
404}
405
406static int
407atphy_mii_phy_auto(struct mii_softc *sc)
408{
409 uint16_t anar;
410
411 sc->mii_ticks = 0;
412 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
413 if (sc->mii_flags & MIIF_DOPAUSE)
414 anar |= ANAR_PAUSE_TOWARDS;
415 PHY_WRITE(sc, MII_ANAR, anar);
416 if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX))
417 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
418 GTCR_ADV_1000THDX);
419 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
420
421 return EJUSTRETURN;
422}
423