1/* $NetBSD: nouveau_engine_disp_nva0.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */
2
3/*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26
27#include <sys/cdefs.h>
28__KERNEL_RCSID(0, "$NetBSD: nouveau_engine_disp_nva0.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $");
29
30#include <engine/software.h>
31#include <engine/disp.h>
32
33#include <core/class.h>
34
35#include "nv50.h"
36
37/*******************************************************************************
38 * EVO overlay channel objects
39 ******************************************************************************/
40
41static const struct nv50_disp_mthd_list
42nva0_disp_ovly_mthd_base = {
43 .mthd = 0x0000,
44 .addr = 0x000000,
45 .data = {
46 { 0x0080, 0x000000 },
47 { 0x0084, 0x6109a0 },
48 { 0x0088, 0x6109c0 },
49 { 0x008c, 0x6109c8 },
50 { 0x0090, 0x6109b4 },
51 { 0x0094, 0x610970 },
52 { 0x00a0, 0x610998 },
53 { 0x00a4, 0x610964 },
54 { 0x00b0, 0x610c98 },
55 { 0x00b4, 0x610ca4 },
56 { 0x00b8, 0x610cac },
57 { 0x00c0, 0x610958 },
58 { 0x00e0, 0x6109a8 },
59 { 0x00e4, 0x6109d0 },
60 { 0x00e8, 0x6109d8 },
61 { 0x0100, 0x61094c },
62 { 0x0104, 0x610984 },
63 { 0x0108, 0x61098c },
64 { 0x0800, 0x6109f8 },
65 { 0x0808, 0x610a08 },
66 { 0x080c, 0x610a10 },
67 { 0x0810, 0x610a00 },
68 {}
69 }
70};
71
72static const struct nv50_disp_mthd_chan
73nva0_disp_ovly_mthd_chan = {
74 .name = "Overlay",
75 .addr = 0x000540,
76 .data = {
77 { "Global", 1, &nva0_disp_ovly_mthd_base },
78 {}
79 }
80};
81
82/*******************************************************************************
83 * Base display object
84 ******************************************************************************/
85
86static struct nouveau_oclass
87nva0_disp_sclass[] = {
88 { NVA0_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
89 { NVA0_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
90 { NVA0_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
91 { NVA0_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
92 { NVA0_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
93 {}
94};
95
96static struct nouveau_oclass
97nva0_disp_base_oclass[] = {
98 { NVA0_DISP_CLASS, &nv50_disp_base_ofuncs, nv84_disp_base_omthds },
99 {}
100};
101
102/*******************************************************************************
103 * Display engine implementation
104 ******************************************************************************/
105
106static int
107nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
108 struct nouveau_oclass *oclass, void *data, u32 size,
109 struct nouveau_object **pobject)
110{
111 struct nv50_disp_priv *priv;
112 int ret;
113
114 ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
115 "display", &priv);
116 *pobject = nv_object(priv);
117 if (ret)
118 return ret;
119
120 nv_engine(priv)->sclass = nva0_disp_base_oclass;
121 nv_engine(priv)->cclass = &nv50_disp_cclass;
122 nv_subdev(priv)->intr = nv50_disp_intr;
123 INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
124 priv->sclass = nva0_disp_sclass;
125 priv->head.nr = 2;
126 priv->dac.nr = 3;
127 priv->sor.nr = 2;
128 priv->pior.nr = 3;
129 priv->dac.power = nv50_dac_power;
130 priv->dac.sense = nv50_dac_sense;
131 priv->sor.power = nv50_sor_power;
132 priv->sor.hdmi = nv84_hdmi_ctrl;
133 priv->pior.power = nv50_pior_power;
134 priv->pior.dp = &nv50_pior_dp_func;
135 return 0;
136}
137
138struct nouveau_oclass *
139nva0_disp_oclass = &(struct nv50_disp_impl) {
140 .base.base.handle = NV_ENGINE(DISP, 0x83),
141 .base.base.ofuncs = &(struct nouveau_ofuncs) {
142 .ctor = nva0_disp_ctor,
143 .dtor = _nouveau_disp_dtor,
144 .init = _nouveau_disp_init,
145 .fini = _nouveau_disp_fini,
146 },
147 .mthd.core = &nv84_disp_mast_mthd_chan,
148 .mthd.base = &nv84_disp_sync_mthd_chan,
149 .mthd.ovly = &nva0_disp_ovly_mthd_chan,
150 .mthd.prev = 0x000004,
151}.base.base;
152