1 | /* $NetBSD: nouveau_engine_falcon.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright 2012 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | */ |
24 | |
25 | #include <sys/cdefs.h> |
26 | __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_falcon.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $" ); |
27 | |
28 | #include <engine/falcon.h> |
29 | #include <subdev/timer.h> |
30 | |
31 | void |
32 | nouveau_falcon_intr(struct nouveau_subdev *subdev) |
33 | { |
34 | struct nouveau_falcon *falcon = (void *)subdev; |
35 | u32 dispatch = nv_ro32(falcon, 0x01c); |
36 | u32 intr = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16); |
37 | |
38 | if (intr & 0x00000010) { |
39 | nv_debug(falcon, "ucode halted\n" ); |
40 | nv_wo32(falcon, 0x004, 0x00000010); |
41 | intr &= ~0x00000010; |
42 | } |
43 | |
44 | if (intr) { |
45 | nv_error(falcon, "unhandled intr 0x%08x\n" , intr); |
46 | nv_wo32(falcon, 0x004, intr); |
47 | } |
48 | } |
49 | |
50 | u32 |
51 | _nouveau_falcon_rd32(struct nouveau_object *object, u64 addr) |
52 | { |
53 | struct nouveau_falcon *falcon = (void *)object; |
54 | return nv_rd32(falcon, falcon->addr + addr); |
55 | } |
56 | |
57 | void |
58 | _nouveau_falcon_wr32(struct nouveau_object *object, u64 addr, u32 data) |
59 | { |
60 | struct nouveau_falcon *falcon = (void *)object; |
61 | nv_wr32(falcon, falcon->addr + addr, data); |
62 | } |
63 | |
64 | static void * |
65 | vmemdup(const void *src, size_t len) |
66 | { |
67 | void *p = vmalloc(len); |
68 | |
69 | if (p) |
70 | memcpy(p, src, len); |
71 | return p; |
72 | } |
73 | |
74 | int |
75 | _nouveau_falcon_init(struct nouveau_object *object) |
76 | { |
77 | struct nouveau_device *device = nv_device(object); |
78 | struct nouveau_falcon *falcon = (void *)object; |
79 | const struct firmware *fw; |
80 | char name[32] = "internal" ; |
81 | int ret, i; |
82 | u32 caps; |
83 | |
84 | /* enable engine, and determine its capabilities */ |
85 | ret = nouveau_engine_init(&falcon->base); |
86 | if (ret) |
87 | return ret; |
88 | |
89 | if (device->chipset < 0xa3 || |
90 | device->chipset == 0xaa || device->chipset == 0xac) { |
91 | falcon->version = 0; |
92 | falcon->secret = (falcon->addr == 0x087000) ? 1 : 0; |
93 | } else { |
94 | caps = nv_ro32(falcon, 0x12c); |
95 | falcon->version = (caps & 0x0000000f); |
96 | falcon->secret = (caps & 0x00000030) >> 4; |
97 | } |
98 | |
99 | caps = nv_ro32(falcon, 0x108); |
100 | falcon->code.limit = (caps & 0x000001ff) << 8; |
101 | falcon->data.limit = (caps & 0x0003fe00) >> 1; |
102 | |
103 | nv_debug(falcon, "falcon version: %d\n" , falcon->version); |
104 | nv_debug(falcon, "secret level: %d\n" , falcon->secret); |
105 | nv_debug(falcon, "code limit: %d\n" , falcon->code.limit); |
106 | nv_debug(falcon, "data limit: %d\n" , falcon->data.limit); |
107 | |
108 | /* wait for 'uc halted' to be signalled before continuing */ |
109 | if (falcon->secret && falcon->version < 4) { |
110 | if (!falcon->version) |
111 | nv_wait(falcon, 0x008, 0x00000010, 0x00000010); |
112 | else |
113 | nv_wait(falcon, 0x180, 0x80000000, 0); |
114 | nv_wo32(falcon, 0x004, 0x00000010); |
115 | } |
116 | |
117 | /* disable all interrupts */ |
118 | nv_wo32(falcon, 0x014, 0xffffffff); |
119 | |
120 | /* no default ucode provided by the engine implementation, try and |
121 | * locate a "self-bootstrapping" firmware image for the engine |
122 | */ |
123 | if (!falcon->code.data) { |
124 | snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03x" , |
125 | device->chipset, falcon->addr >> 12); |
126 | |
127 | ret = request_firmware(&fw, name, nv_device_base(device)); |
128 | if (ret == 0) { |
129 | falcon->code.data = vmemdup(fw->data, fw->size); |
130 | falcon->code.size = fw->size; |
131 | falcon->data.data = NULL; |
132 | falcon->data.size = 0; |
133 | release_firmware(fw); |
134 | } |
135 | |
136 | falcon->external = true; |
137 | } |
138 | |
139 | /* next step is to try and load "static code/data segment" firmware |
140 | * images for the engine |
141 | */ |
142 | if (!falcon->code.data) { |
143 | snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xd" , |
144 | device->chipset, falcon->addr >> 12); |
145 | |
146 | ret = request_firmware(&fw, name, nv_device_base(device)); |
147 | if (ret) { |
148 | nv_error(falcon, "unable to load firmware data\n" ); |
149 | return ret; |
150 | } |
151 | |
152 | falcon->data.data = vmemdup(fw->data, fw->size); |
153 | falcon->data.size = fw->size; |
154 | release_firmware(fw); |
155 | if (!falcon->data.data) |
156 | return -ENOMEM; |
157 | |
158 | snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xc" , |
159 | device->chipset, falcon->addr >> 12); |
160 | |
161 | ret = request_firmware(&fw, name, nv_device_base(device)); |
162 | if (ret) { |
163 | nv_error(falcon, "unable to load firmware code\n" ); |
164 | return ret; |
165 | } |
166 | |
167 | falcon->code.data = vmemdup(fw->data, fw->size); |
168 | falcon->code.size = fw->size; |
169 | release_firmware(fw); |
170 | if (!falcon->code.data) |
171 | return -ENOMEM; |
172 | } |
173 | |
174 | nv_debug(falcon, "firmware: %s (%s)\n" , name, falcon->data.data ? |
175 | "static code/data segments" : "self-bootstrapping" ); |
176 | |
177 | /* ensure any "self-bootstrapping" firmware image is in vram */ |
178 | if (!falcon->data.data && !falcon->core) { |
179 | ret = nouveau_gpuobj_new(object->parent, NULL, |
180 | falcon->code.size, 256, 0, |
181 | &falcon->core); |
182 | if (ret) { |
183 | nv_error(falcon, "core allocation failed, %d\n" , ret); |
184 | return ret; |
185 | } |
186 | |
187 | for (i = 0; i < falcon->code.size; i += 4) |
188 | nv_wo32(falcon->core, i, falcon->code.data[i / 4]); |
189 | } |
190 | |
191 | /* upload firmware bootloader (or the full code segments) */ |
192 | if (falcon->core) { |
193 | if (device->card_type < NV_C0) |
194 | nv_wo32(falcon, 0x618, 0x04000000); |
195 | else |
196 | nv_wo32(falcon, 0x618, 0x00000114); |
197 | nv_wo32(falcon, 0x11c, 0); |
198 | nv_wo32(falcon, 0x110, falcon->core->addr >> 8); |
199 | nv_wo32(falcon, 0x114, 0); |
200 | nv_wo32(falcon, 0x118, 0x00006610); |
201 | } else { |
202 | if (falcon->code.size > falcon->code.limit || |
203 | falcon->data.size > falcon->data.limit) { |
204 | nv_error(falcon, "ucode exceeds falcon limit(s)\n" ); |
205 | return -EINVAL; |
206 | } |
207 | |
208 | if (falcon->version < 3) { |
209 | nv_wo32(falcon, 0xff8, 0x00100000); |
210 | for (i = 0; i < falcon->code.size / 4; i++) |
211 | nv_wo32(falcon, 0xff4, falcon->code.data[i]); |
212 | } else { |
213 | nv_wo32(falcon, 0x180, 0x01000000); |
214 | for (i = 0; i < falcon->code.size / 4; i++) { |
215 | if ((i & 0x3f) == 0) |
216 | nv_wo32(falcon, 0x188, i >> 6); |
217 | nv_wo32(falcon, 0x184, falcon->code.data[i]); |
218 | } |
219 | } |
220 | } |
221 | |
222 | /* upload data segment (if necessary), zeroing the remainder */ |
223 | if (falcon->version < 3) { |
224 | nv_wo32(falcon, 0xff8, 0x00000000); |
225 | for (i = 0; !falcon->core && i < falcon->data.size / 4; i++) |
226 | nv_wo32(falcon, 0xff4, falcon->data.data[i]); |
227 | for (; i < falcon->data.limit; i += 4) |
228 | nv_wo32(falcon, 0xff4, 0x00000000); |
229 | } else { |
230 | nv_wo32(falcon, 0x1c0, 0x01000000); |
231 | for (i = 0; !falcon->core && i < falcon->data.size / 4; i++) |
232 | nv_wo32(falcon, 0x1c4, falcon->data.data[i]); |
233 | for (; i < falcon->data.limit / 4; i++) |
234 | nv_wo32(falcon, 0x1c4, 0x00000000); |
235 | } |
236 | |
237 | /* start it running */ |
238 | nv_wo32(falcon, 0x10c, 0x00000001); /* BLOCK_ON_FIFO */ |
239 | nv_wo32(falcon, 0x104, 0x00000000); /* ENTRY */ |
240 | nv_wo32(falcon, 0x100, 0x00000002); /* TRIGGER */ |
241 | nv_wo32(falcon, 0x048, 0x00000003); /* FIFO | CHSW */ |
242 | return 0; |
243 | } |
244 | |
245 | int |
246 | _nouveau_falcon_fini(struct nouveau_object *object, bool suspend) |
247 | { |
248 | struct nouveau_falcon *falcon = (void *)object; |
249 | |
250 | if (!suspend) { |
251 | nouveau_gpuobj_ref(NULL, &falcon->core); |
252 | if (falcon->external) { |
253 | vfree(falcon->data.data); |
254 | vfree(falcon->code.data); |
255 | falcon->code.data = NULL; |
256 | } |
257 | } |
258 | |
259 | nv_mo32(falcon, 0x048, 0x00000003, 0x00000000); |
260 | nv_wo32(falcon, 0x014, 0xffffffff); |
261 | |
262 | return nouveau_engine_fini(&falcon->base, suspend); |
263 | } |
264 | |
265 | int |
266 | nouveau_falcon_create_(struct nouveau_object *parent, |
267 | struct nouveau_object *engine, |
268 | struct nouveau_oclass *oclass, u32 addr, bool enable, |
269 | const char *iname, const char *fname, |
270 | int length, void **pobject) |
271 | { |
272 | struct nouveau_falcon *falcon; |
273 | int ret; |
274 | |
275 | ret = nouveau_engine_create_(parent, engine, oclass, enable, iname, |
276 | fname, length, pobject); |
277 | falcon = *pobject; |
278 | if (ret) |
279 | return ret; |
280 | |
281 | falcon->addr = addr; |
282 | return 0; |
283 | } |
284 | |